diff --git a/.github/wiseconnect.yml b/.github/wiseconnect.yml new file mode 100644 index 000000000..6d19e8bc1 --- /dev/null +++ b/.github/wiseconnect.yml @@ -0,0 +1,164 @@ +files: + - license.md + - components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c + - components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c + - components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h + - components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h + - components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c + - components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h + - components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_rng.c + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/clock_update.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h + - components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h + - components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c + - components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/config/RTE_Device_917.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h + - components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/src/rsi_rom_table_si91x.c + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h + - components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_rng.h + - components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c + - components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h + - components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h + - components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h + - components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c + - components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c + - components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c + - components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c + - components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h + - components/device/silabs/si91x/mcu/core/chip/inc/data_types.h + - components/device/silabs/si91x/mcu/core/chip/inc/em_device.h + - components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h + - components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h + - components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h + - components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h + - components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h + - components/device/silabs/si91x/mcu/core/chip/inc/base_types.h + - components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h + - components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h + - components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h + - components/device/silabs/si91x/wireless/src/sl_si91x_driver.c + - components/device/silabs/si91x/wireless/src/sl_rsi_utility.c + - components/device/silabs/si91x/wireless/memory/malloc_buffers.c + - components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c + - components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c + - components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c + - components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c + - components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c + - components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c + - components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c + - components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h + - components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h + - components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h + - components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h + - components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h + - components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h + - components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h + - components/device/silabs/si91x/wireless/threading/sli_si91x_multithreaded.c + - components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c + - components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_callback_framework.c + - components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c + - components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c + - components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_internal_stack.c + - components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x.h + - components/device/silabs/si91x/wireless/sl_net/inc/sl_net_rsi_utility.h + - components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x_integration_handler.h + - components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c + - components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h + - components/device/silabs/si91x/wireless/socket/src/sl_si91x_socket_utility.c + - components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_types.h + - components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_constants.h + - components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_utility.h + - components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_callback_framework.h + - components/device/silabs/si91x/wireless/socket/inc/sl_bsd_utility.h + - components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h + - components/device/silabs/si91x/wireless/inc/sl_wifi_device.h + - components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h + - components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h + - components/device/silabs/si91x/wireless/inc/sl_si91x_status.h + - components/device/silabs/si91x/wireless/inc/sl_si91x_types.h + - components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h + - components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h + - components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h + - components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c + - components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c + - components/device/silabs/si91x/wireless/ble/src/rsi_utils.c + - components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c.orig + - components/device/silabs/si91x/wireless/ble/inc/rsi_common.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_common_apis.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_config.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_config.h.orig + - components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h + - components/device/silabs/si91x/wireless/ble/inc/sl_si91x_ble.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_user.h + - components/device/silabs/si91x/wireless/ble/inc/rsi_ble_common_config.h + - components/protocol/wifi/src/sl_wifi_basic_credentials.c + - components/protocol/wifi/src/sl_wifi_callback_framework.c + - components/protocol/wifi/si91x/sl_wifi.c + - components/protocol/wifi/inc/sl_wifi_host_interface.h + - components/protocol/wifi/inc/sl_wifi.h + - components/protocol/wifi/inc/sl_wifi_constants.h + - components/protocol/wifi/inc/sl_wifi_types.h + - components/protocol/wifi/inc/sl_wifi_callback_framework.h + - components/protocol/wifi/inc/sl_wifi_credentials.h + - components/service/bsd_socket/si91x_socket/sl_si91x_socket_support.h + - components/service/network_manager/src/sl_net.c + - components/service/network_manager/src/sl_net_credentials.c + - components/service/network_manager/src/sl_net_basic_profiles.c + - components/service/network_manager/si91x/sl_net_si91x.c + - components/service/network_manager/inc/sl_net_constants.h + - components/service/network_manager/inc/sl_net_ip_types.h + - components/service/network_manager/inc/sl_net_wifi_types.h + - components/service/network_manager/inc/sl_net.h + - components/service/network_manager/inc/sl_net_dns.h + - components/service/network_manager/inc/sl_net_types.h + - components/common/src/sl_utility.c + - components/common/inc/sl_additional_status.h + - components/common/inc/sl_ieee802_types.h + - components/common/inc/sl_utility.h + - components/common/inc/sl_ip_types.h + - components/common/inc/sl_constants.h + - resources/defaults/sl_net_default_values.h + - resources/defaults/sl_wifi_region_db_config.h \ No newline at end of file diff --git a/.github/workflows/update_wifi_sdk.yml b/.github/workflows/update_wifi_sdk.yml new file mode 100644 index 000000000..87072d53e --- /dev/null +++ b/.github/workflows/update_wifi_sdk.yml @@ -0,0 +1,109 @@ +name: Update SDK + +on: + repository_dispatch: + types: [update_sdk] + +jobs: + update_sdk: + runs-on: self-hosted + name: silabs-internal + + steps: + - name: Checkout code + uses: actions/checkout@v3 + with: + username: ${{ secrets.REPO_USERNAME }} + token: ${{ secrets.REPO_TOKEN }} + fetch-depth: 0 + + - name: Setup Python + uses: actions/setup-python@v5 + with: + python-version: '3.10' + + - name: Install dependencies + run: | + python3 -m pip install --upgrade pip + pip install pyyaml + + - name: Create/Update branch for new SDK changes + run: | + BRANCH_NAME="${{ github.event.client_payload.branch_name }}" + if git checkout --track "origin/${BRANCH_NAME}"; then + git checkout ${BRANCH_NAME} + git pull origin ${BRANCH_NAME} + else + git checkout -b ${BRANCH_NAME} + fi + + - name: Download SDK from Artifactory + run: | + curl -s -o sdk.zip "${{ github.event.client_payload.artifactory_url }}" + unzip sdk.zip -d wiseconnect_updated + + - name: Load files to copy from YAML + shell: python + run: | + import yaml + import os + from pathlib import Path + import shutil + + # Get the list of wiseconnect SDK source files needed for Zephyr + with open('.github/wiseconnect.yml', 'r') as file: + data = yaml.safe_load(file) + + if data and 'files' in data: + files_to_copy = data['files'] + else: + files_to_copy = [] + + # Copying wiseconnect SDK source files to respective paths + for file in files_to_copy: + extracted_file_path = Path("wiseconnect_updated") / file + target_file_path = Path("wiseconnect") / file + + if extracted_file_path.exists(): + print("Copying file "+ str(target_file_path)) + try: + target_dir_path = os.path.dirname(target_file_path) + os.makedirs(target_dir_path, exist_ok=True) + shutil.copy2(extracted_file_path, target_file_path) + except Exception as e: + print(f"unexpected error: {e}") + else: + print(str(target_file_path) + " Not found in the sdk package") + + - name: Remove downloaded artifacts + run: | + rm -rf wiseconnect_updated sdk.zip + + - name: Configure Git and Publish Changes + run: | + git config --local user.name "wifi-ci-agent" + git config --local user.email "wifi-ci-agent@users.noreply.silabs.com" + changed_files=$(git diff --name-status) + echo "Changed Files ${changed_files}" + # If there are any changed files, push changes to the branch. + if [[ -n "$changed_files" ]]; then + git add -A + git commit -m "Update SDK" + git push --set-upstream origin "${{ github.event.client_payload.branch_name }}" + UPDATED_COMMIT=$(git rev-parse HEAD) + echo "UPDATED_COMMIT=${UPDATED_COMMIT}" >> $GITHUB_ENV + echo "COMMIT_CHANGED=true" >> $GITHUB_ENV + else + echo "WiseConnect SDK has no updates related to zephyr" + echo "COMMIT_CHANGED=false" >> $GITHUB_ENV + fi + + - name: Trigger webhook to zephyr-silabs repo to test new Wiseconnect SDK changes + if: env.COMMIT_CHANGED == 'true' + run: | + echo "triggering build to zephyr-silabs with commitID: ${UPDATED_COMMIT}" + curl -X POST \ + -H "Accept: application/vnd.github+json" \ + -H "Authorization: Bearer ${{ secrets.REPO_TOKEN }}" \ + https://api.github.com/repos/SiliconLabsSoftware/zephyr-silabs/dispatches \ + -d '{"event_type": "update_project_revision", "client_payload": {"project_name": "hal_silabs", "commit_id": "'$UPDATED_COMMIT'"}}' diff --git a/gecko/common/inc/sl_bit.h b/gecko/common/inc/sl_bit.h new file mode 100644 index 000000000..ff15ae1b0 --- /dev/null +++ b/gecko/common/inc/sl_bit.h @@ -0,0 +1,189 @@ +/***************************************************************************//** + * @file + * @brief Implementation of bit operations. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BIT_H +#define SL_BIT_H + +/***************************************************************************//** + * @addtogroup bit Bit Manipulation + * @brief Bitwise operations + * @{ + ******************************************************************************/ + +/****************************************************************************************************//** + * SL_DEF_BIT() + * + * @brief Create bit mask with single, specified bit set. + * + * @param bit Bit number of bit to set. + * + * @return Bit mask with single, specified bit set. + * + * @note (1) 'bit' SHOULD be a non-negative integer. + * + * @note (2) 'bit' values that overflow the target CPU &/or compiler environment (e.g. negative + * or greater-than-CPU-data-size values) MAY generate compiler warnings &/or errors. + *******************************************************************************************************/ + +#define SL_DEF_BIT(bit) (1u << (bit)) + +/****************************************************************************************************//** + * SL_SET_BIT() + * + * @brief Set specified bit(s) in a value. + * + * @param val Value to modify by setting specified bit(s). + * + * @param mask Mask of bits to set. + * + * @return Modified value with specified bit(s) set. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + *******************************************************************************************************/ + +#define SL_SET_BIT(val, mask) ((val) = ((val) | (mask))) + +/****************************************************************************************************//** + * SL_CLEAR_BIT() + * + * @brief Clear specified bit(s) in a value. + * + * @param val Value to modify by clearing specified bit(s). + * + * @param mask Mask of bits to clear. + * + * @return Modified value with specified bit(s) clear. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note 'mask' SHOULD be cast with the same data type than 'val'. + *******************************************************************************************************/ + +#define SL_CLEAR_BIT(val, mask) ((val) = ((val) & (~(mask)))) + +/****************************************************************************************************//** + * SL_IS_BIT_SET() + * + * @brief Determine whether the specified bit(s) in a value are set. + * + * @param val Value to check for specified bit(s) set. + * + * @param mask Mask of bits to check if set. + * + * @return true, if ALL specified bit(s) are set in value. + * + * false, if ALL specified bit(s) are NOT set in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_BIT_SET(val, mask) (((((val) & (mask)) == (mask)) && ((mask) != 0u)) ? (true) : (false)) + +/****************************************************************************************************//** + * SL_IS_BIT_CLEAR() + * + * @brief Determine whether the specified bit(s) in a value are clear. + * + * @param val Value to check for specified bit(s) clear. + * + * @param mask Mask of bits to check if clear. + * + * @return true, if ALL specified bit(s) are clear in value. + * + * false, if ALL specified bit(s) are NOT clear in value. + * + * @note val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ +#define SL_IS_BIT_CLEAR(val, mask) (((((val) & (mask)) == 0u) && ((mask) != 0u)) ? (true) : (false)) + +/****************************************************************************************************//** + * SL_IS_ANY_BIT_SET() + * + * @brief Determine whether any specified bit(s) in a value are set. + * + * @param val Value to check for specified bit(s) set. + * + * @param mask Mask of bits to check if set (see Note #2). + * + * @return true, if ANY specified bit(s) are set in value. + * + * false, if ALL specified bit(s) are NOT set in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_ANY_BIT_SET(val, mask) ((((val) & (mask)) == 0u) ? (false) : (true)) + +/****************************************************************************************************//** + * SL_IS_ANY_BIT_CLEAR() + * + * @brief Determine whether any specified bit(s) in a value are clear. + * + * @param val Value to check for specified bit(s) clear. + * + * @param mask Mask of bits to check if clear (see Note #2). + * + * @return true, if ANY specified bit(s) are clear in value. + * + * false, if ALL specified bit(s) are NOT clear in value. + * + * @note 'val' & 'mask' SHOULD be unsigned integers. + * + * @note NULL 'mask' allowed; returns 'false' since NO mask bits specified. + *******************************************************************************************************/ + +#define SL_IS_ANY_BIT_CLEAR(val, mask) ((((val) & (mask)) == (mask)) ? (false) : (true)) + +/****************************************************************************************************//** + * SL_MATH_IS_PWR2() + * + * @brief Determine if a value is a power of 2. + * + * @param val Value. + * + * @return true, 'val' is a power of 2. + * false, 'val' is not a power of 2. + *******************************************************************************************************/ + +#define SL_MATH_IS_PWR2(val) ((((val) != 0u) && (((val) & ((val) - 1u)) == 0u)) ? true : false) + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** @} (end addtogroup bit) */ + +#endif /* SL_BIT_H */ diff --git a/gecko/common/inc/sl_string.h b/gecko/common/inc/sl_string.h new file mode 100644 index 000000000..89782a3dc --- /dev/null +++ b/gecko/common/inc/sl_string.h @@ -0,0 +1,155 @@ +/******************************************************************************* + * @file + * @brief Implementation of safe string functions. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_STRING_H +#define SL_STRING_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * @addtogroup string String + * @brief String module provides APIs to handle string-related operations. + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Defines + +// ----------------------------------------------------------------------------- +// Prototypes + +/******************************************************************************* + * @brief + * Copy a string into a buffer. + * Normally, the complete source string including the '\0' termination will be + * copied to the destination. + * If the destination buffer doesn't have room to receive the + * complete source string, the source string will be truncated and the + * destination buffer will be '\0' terminated within the destination buffer. + * + * @param[in] dst Destination buffer. + * + * @param[in] dst_size The size of the destination buffer. + * + * @param[in] src Source string. + ******************************************************************************/ +void sl_strcpy_s(char *dst, size_t dst_size, const char *src); + +/******************************************************************************* + * @brief + * Append the source string to the end of destination string. + * Normally, the complete source string including the '\0' termination will be + * appended to the destination, starting at the source strings '\0' termination. + * If the destination buffer has no room to receive the + * complete source string, the source string will be truncated and the + * destination '\0' terminated within the destination buffer. + * + * @param[in] dst Destination string. + * + * @param[in] dst_size The size of the destination string buffer. + * + * @param[in] src Source string. + ******************************************************************************/ +void sl_strcat_s(char *dst, size_t dst_size, const char *src); + +/******************************************************************************* + * @brief + * Get the string length. + * + * @param[in] str The string to get the length for. + * + * @return String lenght. + ******************************************************************************/ +size_t sl_strlen(char *str); + +/******************************************************************************* + * @brief + * Get the string length, limited to given length. + * + * @param[in] str The string to get the length for. + * + * @param[in] max_len The input string is searched for at most max_lencharacters. + * + * @return String lenght. + ******************************************************************************/ +size_t sl_strnlen(char *str, size_t max_len); + +/******************************************************************************* + * @brief + * Check if the string is empty. + * + * @param[in] str The string to check. + * + * @return true if string is empty or null, else return false. + ******************************************************************************/ +bool sl_str_is_empty(const char *str); + +/******************************************************************************* + * @brief + * Compare two strings, ignoring case. + * + * @param[in] a String to compare. + * + * @param[in] b String to compare. + * + * @return An integer greater than, or less than 0 if the strings + * are not equal. 0 if the strings are equal. + ******************************************************************************/ +int sl_strcasecmp(char const *a, char const *b); + +/******************************************************************************* + * @brief + * Searches for the character in memory, in reverse order. + * + * @param[in] buff Address of the memory buffer. + * + * @param[in] c Character to look for. + * + * @param[in] buff_len Length of the memory buffer. + * + * @return The address of the character in the buffer if and only + * if it was found. + * NULL if no character was found. + ******************************************************************************/ +void* sl_memrchr(void const *buff, char c, size_t buff_len); + +/** @} (end addtogroup string) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_STRING_H */ diff --git a/scripts/.gitignore b/scripts/.gitignore index 1fcb1529f..1e4ded714 100644 --- a/scripts/.gitignore +++ b/scripts/.gitignore @@ -1 +1,2 @@ +cache out diff --git a/scripts/gen_acmp.py b/scripts/gen_acmp.py new file mode 100755 index 000000000..ea0cc298b --- /dev/null +++ b/scripts/gen_acmp.py @@ -0,0 +1,97 @@ +""" +Copyright (c) 2025 Silicon Laboratories Inc. + +SPDX-License-Identifier: Apache-2.0 +""" +import argparse +import re +import datetime +from pathlib import Path + +devices = { + "xg21": { + "bits": "platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_acmp.h", + }, + "xg23": { + "bits": "platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_acmp.h", + }, + "xg24": { + "bits": "platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h", + }, + "xg27": { + "bits": "platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_acmp.h", + }, + "xg29": { + "bits": "platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h", + }, +} + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Generate headers for Comparator for Series 2 " + "devices. The headers are used from DeviceTree, and represent " + "every ACMP input selection as a DT compatible macro.") + parser.add_argument("--out", "-o", type=Path, default=Path(__file__).parent / "out", + help="Output directory. Defaults to the directory ./out/ relative to the " + "script. Set to $ZEPHYR_BASE/include/zephyr/dt-bindings/comparator/ " + "to directly generate output into the expected location within the Zephyr " + "main tree.") + parser.add_argument("--sdk", "-s", type=Path, default=Path(__file__).parent.parent / "simplicity_sdk", + help="Path to Simplicity SDK to extract data from. Defaults to the directory " + "../simplicity_sdk relative to the script.") + args = parser.parse_args() + + args.out.mkdir(exist_ok=True) + + defines = {} + for device, data_sources in devices.items(): + bits_file = (args.sdk / data_sources["bits"]).resolve() + with bits_file.open() as f: + for line in f: + + if m := re.match(r"#define (_ACMP_INPUTCTRL_POSSEL_(?!SHIFT)(?!MASK)(?!DEFAULT).*)\s+(\dx[\dABCDEF]+)", line): + input_value = hex(int(m.group(2),16)) + input_name = f"#define ACMP_INPUT_{m.group(1).split('_')[-1]}" + # Detect any input definition collisions + if (input_value in defines): + if ( input_name == defines[input_value] ): + print(f"Inputs {input_name} and {defines[input_value]} share the same value {input_value}.") + defines.update({input_value : f"{input_name} {input_value}"}) + + if m := re.match(r"#define (_ACMP_INPUTCTRL_NEGSEL_(?!SHIFT)(?!MASK)(?!DEFAULT).*)\s+(\dx[\dABCDEF]+)", line): + input_value = hex(int(m.group(2),16)) + input_name = f"#define ACMP_INPUT_{m.group(1).split('_')[-1]}" + # Detect any input definition collisions + if (input_value in defines): + if ( input_name == defines[input_value] ): + print(f"Inputs {input_name} and {defines[input_value]} share the same value {input_value}.") + defines.update({input_value : f"{input_name} {input_value}"}) + + # Sort defines by key + defines = dict(sorted(defines.items())) + + file = [ + "/*", + f" * Copyright (c) {datetime.date.today().year} Silicon Laboratories Inc.", + " *", + " * SPDX-License-Identifier: Apache-2.0", + " *", + f" * This file was generated by the script {Path(__file__).name} in the hal_silabs module.", + " * Do not manually edit.", + " */", + "", + f"#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_SILABS_ACMP_H_", + f"#define ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_SILABS_ACMP_H_", + "", + f"/* ACMP Input Aliases */", + f"#define ACMP_INPUT_VDACOUT0 ACMP_INPUT_VDAC0OUT0", + f"#define ACMP_INPUT_VDACOUT1 ACMP_INPUT_VDAC0OUT1", + "", + f"/* ACMP Input Definitions */", + ] + list(defines.values()) + [ + "", + f"#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_SILABS_ACMP_H_ */", + "", + ] + + outfile = args.out / f"silabs-acmp.h" + outfile.write_text("\n".join(file)) diff --git a/scripts/gen_adc.py b/scripts/gen_adc.py new file mode 100755 index 000000000..5035840ed --- /dev/null +++ b/scripts/gen_adc.py @@ -0,0 +1,158 @@ +#!/usr/bin/env python + +""" +Copyright (c) 2025 Silicon Laboratories Inc. + +SPDX-License-Identifier: Apache-2.0 +""" +import argparse +import datetime +import re +from pathlib import Path + +devices = { + "xg21": { + "bits": "platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_iadc.h", + "values": { + "SUPPLY": { + 0: "AVDD", + 1: "IOVDD", + 4: "DVDD", + 7: "DECOUPLE" + } + } + }, + "xg22": { + "bits": "platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h", + "values": { + "SUPPLY": { + 0: "AVDD", + 1: "IOVDD", + 4: "DVDD", + 7: "DECOUPLE" + } + } + }, + "xg23": { + "bits": "platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_iadc.h", + "values": { + "SUPPLY": { + 0: "AVDD", + 1: "IOVDD", + 4: "DVDD", + 7: "DECOUPLE" + } + } + }, + "xg24": { + "bits": "platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h", + "values": { + "SUPPLY": { + 0: "AVDD", + 1: "IOVDD", + 4: "DVDD", + 7: "DECOUPLE" + } + } + }, + "xg27": { + "bits": "platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_iadc.h", + "values": { + "SUPPLY": { + 0: "AVDD", + 1: "IOVDD", + 2: "VBAT", + 4: "DVDD", + 7: "DECOUPLE" + } + } + }, + "xg29": { + "bits": "platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h", + "values": { + "SUPPLY": { + 0: "AVDD", + 1: "IOVDD", + 2: "VBAT", + 4: "DVDD", + 7: "DECOUPLE" + } + } + } +} + +alias = { + "PADANA0": "AIN0", + "PADANA1": "AIN1", + "PADANA2": "AIN2", + "PADANA3": "AIN3", +} + +def insert(values, key, val): + if key in values: + assert values[key] == val, f"{key} = {values[key]} from a previous device, new value = {val}" + else: + values[key] = val + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Generate headers for ADC for Series 2 " + "devices. The headers are used from DeviceTree, and represent " + "every ADC input as a DT compatible macro.") + parser.add_argument("--out", "-o", type=Path, default=Path(__file__).parent / "out", + help="Output directory. Defaults to the directory ./out/ relative to the " + "script. Set to $ZEPHYR_BASE/include/zephyr/dt-bindings/adc/ " + "to directly generate output into the expected location within the Zephyr " + "main tree.") + parser.add_argument("--sdk", "-s", type=Path, default=Path(__file__).parent.parent / "simplicity_sdk", + help="Path to Simplicity SDK to extract data from. Defaults to the directory " + "../simplicity_sdk relative to the script.") + args = parser.parse_args() + + args.out.mkdir(exist_ok=True) + + values = {} + for device, data_source in devices.items(): + print(f"Parse ADC data for {device}") + + with (args.sdk / data_source["bits"]).open() as f: + for line in f: + if m := re.match(r"#define _IADC_SINGLE_PORT(POS|NEG)_([^\s]+)\s+(0x[0-9A-F]*)UL", line): + port = m.group(2) + port_base = int(m.group(3), base=16) * 16 + if port in ["MASK", "DEFAULT"]: + continue + if port in data_source["values"]: + for value, key in data_source["values"][port].items(): + insert(values, key, port_base + value) + elif port.startswith("PORT"): + for pin in range(16): + insert(values, f"P{port[4]}{pin}", port_base + pin) + else: + insert(values, alias.get(port,port), port_base) + + file = [ + "/*", + f" * Copyright (c) {datetime.date.today().year} Silicon Laboratories Inc.", + " *", + " * SPDX-License-Identifier: Apache-2.0", + " *", + f" * This file was generated by the script {Path(__file__).name} in the hal_silabs module.", + " * Do not manually edit.", + " */", + "", + f"#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_", + f"#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_", + "", + ] + + max_key = max(len(k) for k in values) + for k, v in sorted(values.items(), key=lambda i: (i[1],i[0])): + file.append(f"#define IADC_INPUT_{k}{' ' * (max_key - len(k) + 1)}0x{v:x}") + + file.append("") + file.append(f"#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_ */") + file.append("") + + outfile = args.out / f"silabs-adc.h" + outfile.write_text("\n".join(file)) diff --git a/scripts/gen_clock_control.py b/scripts/gen_clock_control.py index bee5c8f31..affbb4f5e 100755 --- a/scripts/gen_clock_control.py +++ b/scripts/gen_clock_control.py @@ -28,6 +28,10 @@ "xg27": { "bits": "platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_cmu.h", "nodes": "platform/service/device_manager/clocks/sl_device_clock_efr32xg27.c" + }, + "xg29": { + "bits": "platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h", + "nodes": "platform/service/device_manager/clocks/sl_device_clock_efr32xg29.c" }, } @@ -55,6 +59,7 @@ args.out.mkdir(exist_ok=True) for device, data_sources in devices.items(): + print(f"Generate clock control binding for {device}") bits_file = (args.sdk / data_sources["bits"]).resolve() bits = {} with bits_file.open() as f: @@ -68,11 +73,14 @@ with node_file.open() as f: for line in f: if m := re.match(r".*uint32_t SL_BUS_(.*)_VALUE = \(([^\s]+).*(_CMU[^\s]+SHIFT)", line): - nodes.append(f"#define {m.group(1)}" - f"{' ' * (20 - len(m.group(1)))}" - f"(FIELD_PREP(CLOCK_REG_MASK, {clocks[m.group(2)]}) | " - f"FIELD_PREP(CLOCK_BIT_MASK, {bits[m.group(3)]}))" - ) + try: + nodes.append(f"#define {m.group(1)}" + f"{' ' * (20 - len(m.group(1)))}" + f"(FIELD_PREP(CLOCK_REG_MASK, {clocks[m.group(2)]}) | " + f"FIELD_PREP(CLOCK_BIT_MASK, {bits[m.group(3)]}))" + ) + except KeyError as e: + print(f"WARN: Failed to emit clock node: {e}") else: # xg21 has on-demand automatic clock requests, there are no enable bits nodes.append("#define CLOCK_AUTO 0xFFFFFFFFUL") diff --git a/scripts/gen_pinctrl.py b/scripts/gen_pinctrl.py new file mode 100755 index 000000000..7867fecef --- /dev/null +++ b/scripts/gen_pinctrl.py @@ -0,0 +1,373 @@ +#!/usr/bin/env python + +""" +Copyright (c) 2024 Silicon Laboratories Inc. + +SPDX-License-Identifier: Apache-2.0 +""" + +import argparse +import cmsis_svd +import datetime +import lxml +import re +import shutil +import tempfile +import urllib.request +import zipfile + +from pathlib import Path + +import cmsis_svd.parser + +PIN_TOOL_URL = "https://github.com/SiliconLabs/simplicity_sdk/releases/download/v2024.6.2/pintool.zip" +CMSIS_PACK_URL = "https://www.silabs.com/documents/public/cmsis-packs/SiliconLabs.GeckoPlatform_FAMILY_DFP.2024.6.0.pack" + +# Families to parse to produce generic pinout header +FAMILIES = { + "xg21": ["efr32mg21", "efr32bg21", "mgm21", "bgm21"], + "xg22": ["efr32mg22", "efr32bg22", "efr32fg22", "mgm22", "bgm22", "efm32pg22"], + "xg23": ["efr32fg23", "efr32sg23", "efr32zg23", "zgm23", "efm32pg23"], # "fgm23", + "xg24": ["efr32mg24", "efr32bg24", "mgm24", "bgm24"], + "xg25": ["efr32fg25"], + "xg26": ["efr32mg26", "efr32bg26"], + "xg27": ["efr32mg27", "efr32bg27"], + "xg28": ["efr32fg28", "efr32sg28", "efr32zg28", "efm32pg28"], + "xg29": ["efr32bg29"], +} +ABUSES = { + "xg21": "platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21_gpio.h", + "xg22": "platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h", + "xg23": "platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23_gpio.h", + "xg24": "platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h", + "xg25": "platform/Device/SiliconLabs/EFR32FG25/Include/efr32fg25_gpio.h", + "xg26": "platform/Device/SiliconLabs/EFR32MG26/Include/efr32mg26_gpio.h", + "xg27": "platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_gpio.h", + "xg28": "platform/Device/SiliconLabs/EFR32FG28/Include/efr32fg28_gpio.h", + "xg29": "platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h", +} + +# Certain peripherals have different names in SVD and Pin Tool data; rename the SVD peripheral +PERIPHERAL_ALIAS = { + "FRC": "PTI", + "LETIMER": "LETIMER0", + "SYXO0": "HFXO0", +} + +# Certain signals have different names in SVD and Pin Tool data; rename the SVD signal +SIGNAL_ALIAS = { + "CCC0": "CDTI0", + "CCC1": "CDTI1", + "CCC2": "CDTI2", + "CCC3": "CDTI3", + "USART1::SCLK": "CLK", +} + +# Certain signals have different names in SVD and Pin Tool data; rename the Pin Tool signal +PT_SIGNAL_ALIAS = { + "ACMPOUT": "DIGOUT", + "COLOUT0": "COL_OUT_0", + "COLOUT1": "COL_OUT_1", + "COLOUT2": "COL_OUT_2", + "COLOUT3": "COL_OUT_3", + "COLOUT4": "COL_OUT_4", + "COLOUT5": "COL_OUT_5", + "COLOUT6": "COL_OUT_6", + "COLOUT7": "COL_OUT_7", + "ROWSENSE0": "ROW_SENSE_0", + "ROWSENSE1": "ROW_SENSE_1", + "ROWSENSE2": "ROW_SENSE_2", + "ROWSENSE3": "ROW_SENSE_3", + "ROWSENSE4": "ROW_SENSE_4", + "ROWSENSE5": "ROW_SENSE_5", + "ANTROLLOVER": "ANT_ROLL_OVER", + "ANTRR0": "ANT_RR0", + "ANTRR1": "ANT_RR1", + "ANTRR2": "ANT_RR2", + "ANTRR3": "ANT_RR3", + "ANTRR4": "ANT_RR4", + "ANTRR5": "ANT_RR5", + "ANTSWEN": "ANT_SW_EN", + "ANTSWUS": "ANT_SW_US", + "ANTTRIG": "ANT_TRIG", + "ANTTRIGSTOP": "ANT_TRIG_STOP", + "BUFOUTREQINASYNC": "BUFOUT_REQ_IN_ASYNC", + "USBVBUSSENSE": "USB_VBUS_SENSE", +} + +# Expected offset of DBGROUTEPEN register across all of Series 2. +# Used as base address of pinctrl device tree node. +PINCTRL_GPIO_OFFSET = 1088 + + +class Peripheral: + def __init__(self, name, offset): + self.name = name + self.offset = offset + self.signals = [] + + def max_signal_len(self): + return max(len(s.name) for s in self.signals) + + def set_signal_enable(self, name, bit): + for signal in self.signals: + if signal.name == name: + break + else: + signal = Signal(name, self) + self.signals.append(signal) + + signal.have_enable = True + signal.enable = bit + + def set_signal_route(self, name, offset): + for signal in self.signals: + if signal.name == name: + break + else: + signal = Signal(name, self) + self.signals.append(signal) + + signal.route = offset - self.offset + + +class Signal: + def __init__(self, name, peripheral): + self.peripheral = peripheral + self.name = name + self.route = None + self.have_enable = False + self.enable = 0 + self.pinout = {} + + def display_name(self): + return f"{self.peripheral.name}_{self.name}" + + +def download_pin_tool_data(path: Path) -> None: + """ + Download Pin Tool zip file from SiSDK release artifact + """ + dst = path / "pin_tool" + if dst.exists(): + print("Skipping download of Pin Tool data, already exists") + return + print("Downloading Pin Tool data") + with urllib.request.urlopen(PIN_TOOL_URL) as response: + with tempfile.NamedTemporaryFile() as tmp_file: + shutil.copyfileobj(response, tmp_file) + + with zipfile.ZipFile(tmp_file, 'r') as zip: + zip.extractall(dst) + + +def download_cmsis_pack(path: Path, family: str) -> None: + """ + Download CMSIS Pack containing SVD files for a given family + """ + dst = path / "pack" / family + if dst.exists(): + print(f"Skipping download of CMSIS Pack for {family}, already exists") + return + print(f"Downloading CMSIS Pack for {family}") + with urllib.request.urlopen(CMSIS_PACK_URL.replace("FAMILY", family.upper())) as response: + with tempfile.NamedTemporaryFile() as tmp_file: + shutil.copyfileobj(response, tmp_file) + + with zipfile.ZipFile(tmp_file, 'r') as zip: + zip.extractall(dst) + + +def parse_svd(peripherals, path: Path, family: str) -> None: + for svd_path in (path / "pack" / family / "SVD" / family.upper()).glob("*.svd"): + print(f"Parsing SVD for {svd_path.stem}") + parser = cmsis_svd.parser.SVDParser.for_xml_file(svd_path) + gpio: cmsis_svd.parser.SVDPeripheral = next(filter(lambda p: p.name == "GPIO_NS", parser.get_device().peripherals)) + for reg in gpio.registers: + if reg.name == "DBGROUTEPEN": + assert PINCTRL_GPIO_OFFSET == reg.address_offset + + reg_offset_word = (reg.address_offset - PINCTRL_GPIO_OFFSET) // 4 + + if reg.name.endswith("_ROUTEEN"): + peripheral = reg.name[:-8] + peripheral = PERIPHERAL_ALIAS.get(peripheral, peripheral) + if peripheral not in peripherals: + peripherals[peripheral] = Peripheral(peripheral, reg_offset_word) + + for field in reg.fields: + if field.name.endswith("PEN"): + signal = field.name[:-3] + signal = SIGNAL_ALIAS.get(signal, signal) + signal = SIGNAL_ALIAS.get(f"{peripheral}::{signal}", signal) + peripherals[peripheral].set_signal_enable(signal, field.bit_offset) + + if reg.name.endswith("ROUTE"): + peripheral, signal = reg.name.split("_", 1) + peripheral = PERIPHERAL_ALIAS.get(peripheral, peripheral) + signal = signal[:-5] + signal = SIGNAL_ALIAS.get(signal, signal) + signal = SIGNAL_ALIAS.get(f"{peripheral}::{signal}", signal) + + if peripheral not in peripherals: + peripherals[peripheral] = Peripheral(peripheral, reg_offset_word) + + peripherals[peripheral].set_signal_route(signal, reg_offset_word) + + +def parse_pin_tool(peripherals, path: Path, family: str): + for pin_tool in (path / "pin_tool" / "platform" / "hwconf_data" / "pin_tool" / family).glob("*/PORTIO.portio"): + print(f"Parsing Pin Tool for {pin_tool.parent.stem}") + with open(pin_tool, 'r') as f: + tree = lxml.etree.parse(f) + + for peripheral in peripherals.values(): + for signal in peripheral.signals: + pt_signal = PT_SIGNAL_ALIAS.get(signal.name, signal.name) + + if peripheral.name == "PRS0": + pt_peripheral = f"PRS.{signal.name}" + pt_signal_prefix = "PRS" + else: + pt_peripheral = peripheral.name + pt_signal_prefix = peripheral.name + + for node in tree.getroot().xpath(f'portIo/pinRoutes/module[@name="{pt_peripheral}"]/selector[@name="{pt_signal_prefix}_{pt_signal}"]'): + for loc in node.xpath(f'route[@name="{pt_signal}"]/location'): + port = int(loc.attrib["portBankIndex"]) + pin = int(loc.attrib["pinIndex"]) + if port not in signal.pinout: + signal.pinout[port] = set() + signal.pinout[port].add(pin) + + break + else: + print(f"WARN: No Pin Tool match for {signal.display_name()} for {pin_tool.parent.stem}") + + +def write_header(path: Path, family, peripherals: dict, abuses: list) -> None: + """ + Write DT binding header containing DBUS routing data for pinctrl use + """ + lines = [ + "/*", + f" * Copyright (c) {datetime.date.today().year} Silicon Laboratories Inc.", + " * SPDX-License-Identifier: Apache-2.0", + " *", + f" * Pin Control for Silicon Labs {family.upper()} devices", + " *", + f" * This file was generated by the script {Path(__file__).name} in the hal_silabs module.", + " * Do not manually edit.", + " */", + "", + f"#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_{family.upper()}_PINCTRL_H_", + f"#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_{family.upper()}_PINCTRL_H_", + "", + "#include ", + "", + ] + + # Emit generic peripheral macros + for peripheral in peripherals.values(): + have_content = False + for signal in peripheral.signals: + if signal.route is not None: + pad = peripheral.max_signal_len() - len(signal.name) + 1 + lines.append(f"#define SILABS_DBUS_{signal.display_name()}(port, pin){' ' * pad}" + f"SILABS_DBUS(port, pin, {peripheral.offset}, {int(signal.have_enable)}, " + f"{signal.enable}, {signal.route})") + have_content = True + else: + print(f"WARN: No route register for {signal.display_name()}") + if have_content: + lines.append("") + + # Emit pin-specific macros using peripheral macros + for peripheral in peripherals.values(): + have_content = False + for signal in peripheral.signals: + for port, pins in signal.pinout.items(): + for pin in sorted(pins): + pad = peripheral.max_signal_len() - len(signal.name) + 1 + lines.append(f"#define {signal.display_name()}_P{chr(65 + port)}{pin}{' ' * pad}" + f"SILABS_DBUS_{signal.display_name()}(0x{port:x}, 0x{pin:x})") + have_content = True + if have_content: + lines.append("") + + # Emit analog buses + max_len = 0 + for abus in abuses: + curr_len = len(abus["bus_name"]) + len(abus["peripheral"]) + if curr_len > max_len: + max_len = curr_len + for abus in abuses: + curr_len = len(abus["bus_name"]) + len(abus["peripheral"]) + lines.append(f"#define ABUS_{abus["bus_name"]}_{abus["peripheral"]}{' ' * (max_len - curr_len + 1)}" + f"SILABS_ABUS(0x{abus["base_offset"]:x}, 0x{abus["parity"]:x}, 0x{abus["value"]:x})") + lines.append("") + + lines.append(f"#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_{family.upper()}_PINCTRL_H_ */") + lines.append("") + path.mkdir(parents=True, exist_ok=True) + (path / f"{family}-pinctrl.h").write_text("\n".join(lines)) + +def parse_abus(file: Path) -> list: + offset_map = { + "EVEN0": 0, + "EVEN1": 1, + "ODD0": 2, + "ODD1": 3, + } + peripheral_map = { + "ADC0": "IADC0", + } + abuses = [] + with file.open() as f: + for line in f: + if m := re.match(r"#define _GPIO_([A-Z])[A-Z]?BUSALLOC_([A-Z]+(EVEN\d|ODD\d))_([^\s]+)\s+0x(.+)UL", line): + if m.group(4) not in ["DEFAULT", "TRISTATE", "MASK"]: + abuses.append({ + "base_offset": ord(m.group(1)) - 65, + "bus_name": m.group(2), + "parity": offset_map[m.group(3)], + "peripheral": peripheral_map.get(m.group(4), m.group(4)), + "value": int(m.group(5), base=16), + }) + + return abuses + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Generate headers for Pinctrl for Series 2 devices. " + "The headers are used from DeviceTree, and represent every " + "allowed pin selection for every digital bus signal as a DT " + "compatible macro.") + parser.add_argument("--workdir", "-w", default=Path(__file__).parent.absolute() / "cache", + type=Path, help="Working directory to store downloaded Pin Tool and " + "CMSIS-Pack artifacts.") + parser.add_argument("--sdk", "-s", default=Path(__file__).parent.parent.absolute() / "simplicity_sdk", + type=Path, help="SDK directory.") + parser.add_argument("--out", "-o", default=(Path(__file__).parent.absolute() / "out"), type=Path, + help="Output directory for generated bindings. Defaults to the directory " + "./out relative to the script. Set to $ZEPHYR_BASE/include/zephyr/" + "dt-bindings/pinctrl/silabs/ to directly generate output into the expected " + "location within the Zephyr main tree.") + parser.add_argument("--family", "-f", default="xg24", choices=FAMILIES.keys(), + help="Device family to generate pinctrl bindings for. Defaults to xg24 if " + "not set.") + args = parser.parse_args() + + download_pin_tool_data(args.workdir) + + peripherals = {} + + for family in FAMILIES[args.family]: + download_cmsis_pack(args.workdir, family) + # Find DBUS register offsets for all peripheral signals from SVD + parse_svd(peripherals, args.workdir, family) + # Add available pins for all peripheral signals from Pin Tool data + parse_pin_tool(peripherals, args.workdir, family) + + abuses = parse_abus(args.sdk / ABUSES[args.family]) + + write_header(args.out, args.family, peripherals, abuses) diff --git a/scripts/import_simplicity_sdk.py b/scripts/import_simplicity_sdk.py index 78f511d39..d6413c1c5 100755 --- a/scripts/import_simplicity_sdk.py +++ b/scripts/import_simplicity_sdk.py @@ -7,8 +7,11 @@ """ import argparse +import re import shutil +import subprocess from pathlib import Path +from ruamel.yaml import YAML paths = [ "License.txt", @@ -17,12 +20,21 @@ "platform/common/src/sl_assert.c", "platform/common/src/sl_core_cortexm.c", "platform/common/src/sl_slist.c", - "platform/Device/SiliconLabs/EFR32BG2[27]/Include/*.h", - "platform/Device/SiliconLabs/EFR32BG2[27]/Source/system_*.c", + "platform/Device/SiliconLabs/EFR32BG2[279]/Include/*.h", + "platform/Device/SiliconLabs/EFR32BG2[279]/Source/system_*.c", "platform/Device/SiliconLabs/EFR32FG2[3]/Include/*.h", "platform/Device/SiliconLabs/EFR32FG2[3]/Source/system_*.c", - "platform/Device/SiliconLabs/EFR32MG2[14]/Include/*.h", - "platform/Device/SiliconLabs/EFR32MG2[14]/Source/system_*.c", + "platform/Device/SiliconLabs/EFR32MG2[149]/Include/*.h", + "platform/Device/SiliconLabs/EFR32MG2[149]/Source/system_*.c", + "platform/Device/SiliconLabs/EFR32ZG2[3]/Include/*.h", + "platform/Device/SiliconLabs/EFR32ZG2[3]/Source/system_*.c", + "platform/driver/gpio/inc/*.h", + "platform/driver/gpio/src/*.c", + "platform/emdrv/common/inc/*.h", + "platform/emdrv/dmadrv/config/s2_8ch/*.h", + "platform/emdrv/dmadrv/inc/*.h", + "platform/emdrv/dmadrv/inc/s2_signals/.h", + "platform/emdrv/dmadrv/src/*.c", "platform/emlib/inc/*.h", "platform/emlib/src/*.c", "platform/peripheral/inc/*.h", @@ -33,7 +45,13 @@ "platform/radio/rail_lib/plugin/rail_util_protocol/**/*.[ch]", "platform/radio/rail_lib/protocol/**/*.[ch]", "platform/security/sl_component/se_manager/**/*.[ch]", + "platform/security/sl_component/sl_mbedtls_support/config/*.[ch]", + "platform/security/sl_component/sl_mbedtls_support/inc/*.[ch]", + "platform/security/sl_component/sl_mbedtls_support/src/*.[ch]", "platform/security/sl_component/sl_protocol_crypto/**/*.[ch]", + "platform/security/sl_component/sl_psa_driver/*/*.[ch]", + "platform/security/sl_component/sli_crypto/**/*.[ch]", + "platform/security/sl_component/sli_psec_osal/**/*.[ch]", "platform/service/clock_manager/config/**/*.h", # TODO "platform/service/clock_manager/inc/*.h", "platform/service/clock_manager/src/*.[ch]", @@ -44,6 +62,7 @@ "platform/service/hfxo_manager/config/**/*.h", # TODO "platform/service/hfxo_manager/inc/*.h", "platform/service/hfxo_manager/src/*.[ch]", + "platform/service/interrupt_manager/inc/*.h", "platform/service/memory_manager/config/*.h", # TODO "platform/service/memory_manager/inc/*.h", "platform/service/memory_manager/src/*.[ch]", @@ -52,7 +71,7 @@ "platform/service/memory_manager/profiler/src/*.c", "platform/service/power_manager/config/**/*.h", # TODO "platform/service/power_manager/inc/*.h", - "platform/service/power_manager/src/*.[ch]", + "platform/service/power_manager/src/*/*.[ch]", "platform/service/sleeptimer/config/**/*.h", # TODO "platform/service/sleeptimer/inc/*.h", "platform/service/sleeptimer/src/*.[ch]", @@ -71,18 +90,55 @@ def copy_files(src: Path, dst: Path, paths: list[str]) -> None: shutil.copy(f, destfile) +def update_blobs(mod: Path, sdk: Path) -> None: + y = YAML(typ='rt') + y.default_flow_style = False + y.indent(mapping=2, sequence=4, offset=2) + y.preserve_quotes = True + y.width = 1024 + y.boolean_representation = ['False', 'True'] + + slcs = y.load(sdk / "simplicity_sdk.slcs") + + data = y.load(mod) + for blob in data.get('blobs'): + path = Path(blob["path"]) + if not path.is_relative_to(Path("simplicity_sdk")): + continue + + path = path.relative_to(Path("simplicity_sdk")) + lfs = subprocess.check_output(["git", "show", f"HEAD:{str(path)}"], cwd=sdk).decode() + sha = re.search(r"sha256:([0-9a-f]{64})\s", lfs).group(1) + + blob["sha256"] = sha + blob["url"] = f"https://artifacts.silabs.net/artifactory/gsdk/objects/{sha[0:2]}/{sha[2:4]}/{sha}" + blob["version"] = slcs["sdk_version"] + + y.dump(data, mod) + + if __name__ == "__main__": parser = argparse.ArgumentParser() parser.add_argument("--sdk", "-s", type=Path) + parser.add_argument("--blobs", "-b", action='store_true') args = parser.parse_args() dst = (Path(__file__).parent.parent / "simplicity_sdk").resolve() if args.sdk is not None: src = args.sdk.resolve(strict=True) + print(f"Import SDK from {src}") for dir in dst.iterdir(): if dir.is_dir(): shutil.rmtree(dir, ignore_errors=True) copy_files(src, dst, paths) + + print(f"Update module.yml with blobs from {src}") + mod = Path(__file__).parent.parent / "zephyr" / "module.yml" + update_blobs(mod, src) + + print("Done") + else: + print("No SDK to import from") diff --git a/scripts/import_wiseconnect.py b/scripts/import_wiseconnect.py new file mode 100755 index 000000000..b0c784f21 --- /dev/null +++ b/scripts/import_wiseconnect.py @@ -0,0 +1,213 @@ +#!/usr/bin/env python3 + +""" +Copyright (c) 2024 Silicon Laboratories Inc. + +SPDX-License-Identifier: Apache-2.0 +""" + +import argparse +import os +import shutil +import tempfile +import subprocess +from pathlib import Path + + +paths = [ + "components/common/inc/sl_additional_status.h", + "components/common/inc/sl_constants.h", + "components/common/inc/sl_ieee802_types.h", + "components/common/inc/sl_ip_types.h", + "components/common/inc/sl_utility.h", + "components/common/src/sl_utility.c", + "components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h", + "components/device/silabs/si91x/mcu/core/chip/inc/base_types.h", + "components/device/silabs/si91x/mcu/core/chip/inc/data_types.h", + "components/device/silabs/si91x/mcu/core/chip/inc/em_device.h", + "components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h", + "components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h", + "components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h", + "components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h", + "components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h", + "components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h", + "components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h", + "components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c", + "components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c", + "components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c", + "components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c", + "components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/config/RTE_Device_917.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h", + "components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.h", + "components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_rng.c", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_rng.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h", + "components/device/silabs/si91x/mcu/drivers/rom_driver/src/rsi_rom_table_si91x.c", + "components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h", + "components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_power_save.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h", + "components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c", + "components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c", + "components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c", + "components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h", + "components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h", + "components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c", + "components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h", + "components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h", + "components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h", + "components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c", + "components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h", + "components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h", + "components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h", + "components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h", + "components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h", + "components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h", + "components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h", + "components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c", + "components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c", + "components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c", + "components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c", + "components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c", + "components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c", + "components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h", + "components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c", + "components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_ble_common_config.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_config.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_common_apis.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_common.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_user.h", + "components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h", + "components/device/silabs/si91x/wireless/ble/inc/sl_si91x_ble.h", + "components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c", + "components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c", + "components/device/silabs/si91x/wireless/ble/src/rsi_utils.c", + "components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c", + "components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h", + "components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h", + "components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h", + "components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h", + "components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h", + "components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h", + "components/device/silabs/si91x/wireless/inc/sl_si91x_status.h", + "components/device/silabs/si91x/wireless/inc/sl_si91x_types.h", + "components/device/silabs/si91x/wireless/inc/sl_wifi_device.h", + "components/device/silabs/si91x/wireless/memory/malloc_buffers.c", + "components/device/silabs/si91x/wireless/sl_net/inc/sl_net_rsi_utility.h", + "components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x.h", + "components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x_integration_handler.h", + "components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c", + "components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_callback_framework.c", + "components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c", + "components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c", + "components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_internal_stack.c", + "components/device/silabs/si91x/wireless/socket/inc/sl_bsd_utility.h", + "components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_callback_framework.h", + "components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_constants.h", + "components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_types.h", + "components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_utility.h", + "components/device/silabs/si91x/wireless/socket/src/sl_si91x_socket_utility.c", + "components/device/silabs/si91x/wireless/src/sl_rsi_utility.c", + "components/device/silabs/si91x/wireless/src/sl_si91x_callback_framework.c", + "components/device/silabs/si91x/wireless/src/sl_si91x_driver.c", + "components/device/silabs/si91x/wireless/threading/sli_si91x_multithreaded.c", + "components/protocol/wifi/inc/sl_wifi_callback_framework.h", + "components/protocol/wifi/inc/sl_wifi_constants.h", + "components/protocol/wifi/inc/sl_wifi_credentials.h", + "components/protocol/wifi/inc/sl_wifi.h", + "components/protocol/wifi/inc/sl_wifi_host_interface.h", + "components/protocol/wifi/inc/sl_wifi_types.h", + "components/protocol/wifi/si91x/sl_wifi.c", + "components/protocol/wifi/src/sl_wifi_basic_credentials.c", + "components/protocol/wifi/src/sl_wifi_callback_framework.c", + "components/service/bsd_socket/si91x_socket/sl_si91x_socket_support.h", + "components/service/network_manager/inc/sl_net_constants.h", + "components/service/network_manager/inc/sl_net_dns.h", + "components/service/network_manager/inc/sl_net.h", + "components/service/network_manager/inc/sl_net_ip_types.h", + "components/service/network_manager/inc/sl_net_types.h", + "components/service/network_manager/inc/sl_net_wifi_types.h", + "components/service/network_manager/si91x/sl_net_si91x.c", + "components/service/network_manager/src/sl_net_basic_credentials.c", + "components/service/network_manager/src/sl_net_basic_profiles.c", + "components/service/network_manager/src/sl_net.c", + "components/service/network_manager/src/sl_net_credentials.c", + "resources/defaults/sl_net_default_values.h", + "resources/defaults/sl_wifi_region_db_config.h", +] + +def copy_files(src: Path, dst: Path, paths: list[str]) -> None: + for path in paths: + for f in src.glob(path): + if not os.path.exists(f): + print(f"Invalid path: {f}") + continue + destfile = dst / f.relative_to(src) + if os.path.exists(destfile): + continue + print(f"Import {f.relative_to(src)}") + destfile.parent.mkdir(parents=True, exist_ok=True) + shutil.copy(f, destfile) + +if __name__ == "__main__": + parser = argparse.ArgumentParser() + parser.add_argument("sdk", type=Path, + help="Source WiseConnect directory") + parser.add_argument("--dest", "-d", type=Path, + help="store the result somewhere else than \"wiseconnect/\" directory") + parser.add_argument("--overwrite", "-f", action="store_true", + help="Remove DEST before to continue") + args = parser.parse_args() + + if args.dest: + dst = args.dest + else: + dst = (Path(__file__).parent.parent / "wiseconnect").resolve() + + if args.overwrite: + shutil.rmtree(dst) + copy_files(args.sdk, dst, paths) + diff --git a/scripts/patch_simplicity_sdk.sh b/scripts/patch_simplicity_sdk.sh index 181e34632..91b242530 100755 --- a/scripts/patch_simplicity_sdk.sh +++ b/scripts/patch_simplicity_sdk.sh @@ -1,4 +1,19 @@ #!/bin/sh +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 # Add missing SecureFault interrupt number to device headers sed -i '' "s/\(UsageFault_IRQn.*\)/\1\n#if defined(CONFIG_ARM_SECURE_FIRMWARE)\n SecureFault_IRQn = -9,\n#endif/" simplicity_sdk/platform/Device/SiliconLabs/*/Include/*.h + +# Rename CONCAT macros conflicting with Zephyr macros +sed -i '' "s/ _CONCAT_/ _SL_CONCAT_/" simplicity_sdk/platform/common/inc/sl_common.h +sed -i '' "s/ first/first/" simplicity_sdk/platform/common/inc/sl_common.h + +# Replace legacy Kconfig option name +sed -i '' "s/CONFIG_SOC_FAMILY_EXX32/__ZEPHYR__/" simplicity_sdk/platform/emlib/inc/em_ramfunc.h + +# Rename MAX macro conflicting with Zephyr macro +sed -i '' "s/MAX(/_SL_MAX(/" simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c + +# Add Zephyr OS abstraction for crypto +sed -i '' "s/#\(if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT)\)/#if defined(__ZEPHYR__)\n #include \"sli_psec_osal_zephyr.h\"\n #define SLI_PSEC_THREADING\n#el\1/" simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal.h diff --git a/scripts/requirements.txt b/scripts/requirements.txt new file mode 100644 index 000000000..06dbe209c --- /dev/null +++ b/scripts/requirements.txt @@ -0,0 +1 @@ +git+https://github.com/cmsis-svd/cmsis-svd.git#egg=cmsis-svd&subdirectory=python diff --git a/simplicity_sdk/License.txt b/simplicity_sdk/License.txt index 8c3bc83be..b47373c39 100644 --- a/simplicity_sdk/License.txt +++ b/simplicity_sdk/License.txt @@ -1,6 +1,9 @@ # Simplicity SDK Licensing terms -Source code in this SDK is covered by one of several different licenses. +Source code in this SDK is licensed to you under the terms of a default license +from Silicon Laboratories Inc. This default license and exceptions to this +default licensing are set forth below. + The default license is the Master Software License Agreement (MSLA) (https://www.silabs.com/about-us/legal/master-software-license-agreement), which applies unless otherwise noted. diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h index 04e91addf..a6b12850b 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm32.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h index 85ca47f34..578900dcb 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c112f352gm40.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h index 7f40de9e4..acd1be784 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm32.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h index dc0616b10..ec34e07b8 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gm40.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h index 0ea06379e..5cdf550e8 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c222f352gn32.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h index fdef00fd0..624f71171 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm32.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h index 967f4e977..08c8749a9 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gm40.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h index 5976fae60..f8eb0f241 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512gn32.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h index be9018d73..a8a2994c5 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im32.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h index f5f9da30f..05bb143b4 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h index 889c19810..7480f160e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im32.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h index 8a25eec0a..3eedce469 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22e224f512im40.h @@ -135,6 +135,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h index 94706b09f..e971fcb7c 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h @@ -36,6 +36,7 @@ extern "C" { #endif #include +#include "sl_code_classification.h" /***************************************************************************//** * @addtogroup Parts @@ -165,6 +166,7 @@ void EUART0_TX_IRQHandler(void); /**< EUART0_TX IRQ Handler */ void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ #endif +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHCLKGet(void); /**************************************************************************//** @@ -181,6 +183,7 @@ uint32_t SystemHCLKGet(void); * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE uint32_t SystemCoreClockGet(void) { return SystemHCLKGet(); @@ -200,23 +203,33 @@ static __INLINE uint32_t SystemCoreClockGet(void) * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE void SystemCoreClockUpdate(void) { SystemHCLKGet(); } void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCODPLLClockGet(void); void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFXOClockGet(void); void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFXOClockGet(void); void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemULFRCOClockGet(void); /** @} End of group */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c index ab43f8bc3..e7273d112 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c @@ -31,6 +31,15 @@ #include #include "em_device.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ @@ -64,7 +73,10 @@ #endif // CLKIN0 input -#if !defined(CLKIN0_FREQ) +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) #define CLKIN0_FREQ (0UL) #endif @@ -204,12 +216,11 @@ void SystemInit(void) *****************************************************************************/ uint32_t SystemHFRCODPLLClockGet(void) { -#if defined(BOOTLOADER_SYSTEM_NO_STATIC_MEMORY) - return HFRCODPLL_STARTUP_FREQ; -#elif !defined(SYSTEM_NO_STATIC_MEMORY) +#if !defined(SYSTEM_NO_STATIC_MEMORY) return SystemHFRCODPLLClock; #else uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; // Get oscillator frequency band switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h index 5401dc23d..dcedb2df3 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27_syscfg.h @@ -361,7 +361,7 @@ typedef struct syscfg_typedef{ #define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ /* Bit fields for SYSCFG CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00010011UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00011011UL /**< Default value for SYSCFG_CHIPREVHW */ #define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ #define _SYSCFG_CHIPREVHW_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ #define _SYSCFG_CHIPREVHW_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ @@ -369,7 +369,7 @@ typedef struct syscfg_typedef{ #define SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ #define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ #define _SYSCFG_CHIPREVHW_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ #define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ #define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ #define _SYSCFG_CHIPREVHW_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h index be40709cc..753ba9fc4 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im32.h @@ -138,6 +138,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h index 31a495b02..60268a531 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c140f768im40.h @@ -138,6 +138,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h index 3c6adbd85..abbe0bb82 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im32.h @@ -138,6 +138,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h index 9f105c510..e80d77df2 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c230f768im40.h @@ -138,6 +138,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h index 6ff48232d..132fc7e22 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768gj39.h @@ -138,6 +138,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h index 670d436c4..c3aa69368 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/efr32bg27c320f768ij39.h @@ -138,6 +138,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h index cd86a7dc9..e5a853d99 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/system_efr32bg27.h @@ -36,6 +36,7 @@ extern "C" { #endif #include +#include "sl_code_classification.h" /***************************************************************************//** * @addtogroup Parts @@ -168,6 +169,7 @@ void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ #endif +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHCLKGet(void); /**************************************************************************//** @@ -184,6 +186,7 @@ uint32_t SystemHCLKGet(void); * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE uint32_t SystemCoreClockGet(void) { return SystemHCLKGet(); @@ -203,23 +206,33 @@ static __INLINE uint32_t SystemCoreClockGet(void) * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE void SystemCoreClockUpdate(void) { SystemHCLKGet(); } void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCODPLLClockGet(void); void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFXOClockGet(void); void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFXOClockGet(void); void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemULFRCOClockGet(void); /** @} End of group */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c index 0d493dd5c..59f7e551a 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Source/system_efr32bg27.c @@ -31,6 +31,15 @@ #include #include "em_device.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ @@ -64,7 +73,10 @@ #endif // CLKIN0 input -#if !defined(CLKIN0_FREQ) +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) #define CLKIN0_FREQ (0UL) #endif @@ -204,12 +216,11 @@ void SystemInit(void) *****************************************************************************/ uint32_t SystemHFRCODPLLClockGet(void) { -#if defined(BOOTLOADER_SYSTEM_NO_STATIC_MEMORY) - return HFRCODPLL_STARTUP_FREQ; -#elif !defined(SYSTEM_NO_STATIC_MEMORY) +#if !defined(SYSTEM_NO_STATIC_MEMORY) return SystemHFRCODPLLClock; #else uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; // Get oscillator frequency band switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_acmp.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_acmp.h new file mode 100644 index 000000000..dcf6e0f95 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_acmp.h @@ -0,0 +1,650 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 ACMP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_ACMP_H +#define EFR32BG29_ACMP_H +#define ACMP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_ACMP ACMP + * @{ + * @brief EFR32BG29 ACMP Register Declaration. + *****************************************************************************/ + +/** ACMP Register Declaration. */ +typedef struct acmp_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +} ACMP_TypeDef; +/** @} End of group EFR32BG29_ACMP */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_ACMP + * @{ + * @defgroup EFR32BG29_ACMP_BitFields ACMP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ + +/* Bit fields for ACMP EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ + +/* Bit fields for ACMP SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ + +/* Bit fields for ACMP CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 0x00000040UL /**< Mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 0x00000042UL /**< Mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 << 8) /**< Shifted mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 << 8) /**< Shifted mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ + +/** @} End of group EFR32BG29_ACMP_BitFields */ +/** @} End of group EFR32BG29_ACMP */ +/** @} End of group Parts */ + +#endif // EFR32BG29_ACMP_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_aes.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_aes.h new file mode 100644 index 000000000..8f973136a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_aes.h @@ -0,0 +1,453 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 AES register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_AES_H +#define EFR32BG29_AES_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_AES AES + * @{ + * @brief EFR32BG29 AES Register Declaration. + *****************************************************************************/ + +/** AES Register Declaration. */ +typedef struct aes_typedef{ + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +} AES_TypeDef; +/** @} End of group EFR32BG29_AES */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_AES + * @{ + * @defgroup EFR32BG29_AES_BitFields AES Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AES FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ + +/* Bit fields for AES FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ + +/* Bit fields for AES FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ + +/* Bit fields for AES PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ + +/* Bit fields for AES PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ + +/* Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ + +/* Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ + +/* Bit fields for AES BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ + +/* Bit fields for AES BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ + +/* Bit fields for AES BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ + +/* Bit fields for AES BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ + +/* Bit fields for AES BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ + +/** @} End of group EFR32BG29_AES_BitFields */ +/** @} End of group EFR32BG29_AES */ +/** @} End of group Parts */ + +#endif // EFR32BG29_AES_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_buram.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_buram.h new file mode 100644 index 000000000..9a9f287e6 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_buram.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 BURAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_BURAM_H +#define EFR32BG29_BURAM_H +#define BURAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_BURAM BURAM + * @{ + * @brief EFR32BG29 BURAM Register Declaration. + *****************************************************************************/ + +/** BURAM RET Register Group Declaration. */ +typedef struct buram_ret_typedef{ + __IOM uint32_t REG; /**< Retention Register */ +} BURAM_RET_TypeDef; + +/** BURAM Register Declaration. */ +typedef struct buram_typedef{ + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +} BURAM_TypeDef; +/** @} End of group EFR32BG29_BURAM */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_BURAM + * @{ + * @defgroup EFR32BG29_BURAM_BitFields BURAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURAM RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ + +/** @} End of group EFR32BG29_BURAM_BitFields */ +/** @} End of group EFR32BG29_BURAM */ +/** @} End of group Parts */ + +#endif // EFR32BG29_BURAM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_burtc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_burtc.h new file mode 100644 index 000000000..17dbf0dd0 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_burtc.h @@ -0,0 +1,332 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 BURTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_BURTC_H +#define EFR32BG29_BURTC_H +#define BURTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_BURTC BURTC + * @{ + * @brief EFR32BG29 BURTC Register Declaration. + *****************************************************************************/ + +/** BURTC Register Declaration. */ +typedef struct burtc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +} BURTC_TypeDef; +/** @} End of group EFR32BG29_BURTC */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_BURTC + * @{ + * @defgroup EFR32BG29_BURTC_BitFields BURTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURTC IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ + +/* Bit fields for BURTC EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000001UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ + +/* Bit fields for BURTC CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DISABLE (_BURTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_ENABLE (_BURTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ + +/* Bit fields for BURTC CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ + +/* Bit fields for BURTC IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ + +/* Bit fields for BURTC CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ + +/* Bit fields for BURTC SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000003FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_EN (0x1UL << 5) /**< Sync busy for EN */ +#define _BURTC_SYNCBUSY_EN_SHIFT 5 /**< Shift value for BURTC_EN */ +#define _BURTC_SYNCBUSY_EN_MASK 0x20UL /**< Bit mask for BURTC_EN */ +#define _BURTC_SYNCBUSY_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_EN_DEFAULT (_BURTC_SYNCBUSY_EN_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ + +/** @} End of group EFR32BG29_BURTC_BitFields */ +/** @} End of group EFR32BG29_BURTC */ +/** @} End of group Parts */ + +#endif // EFR32BG29_BURTC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h new file mode 100644 index 000000000..ee643125a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_cmu.h @@ -0,0 +1,1017 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 CMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_CMU_H +#define EFR32BG29_CMU_H +#define CMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_CMU CMU + * @{ + * @brief EFR32BG29 CMU Register Declaration. + *****************************************************************************/ + +/** CMU Register Declaration. */ +typedef struct cmu_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED11[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED13[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED14[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL; /**< RTCC Clock Control */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL; /**< Protocol RTC Clock Control */ + uint32_t RESERVED16[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[860U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED23[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED24[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED28[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_SET; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED31[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED32[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED33[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED34[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_SET; /**< RTCC Clock Control */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_SET; /**< Protocol RTC Clock Control */ + uint32_t RESERVED36[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[860U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED43[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED45[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED48[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED49[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_CLR; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED50[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED51[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED52[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED53[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_CLR; /**< RTCC Clock Control */ + uint32_t RESERVED55[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_CLR; /**< Protocol RTC Clock Control */ + uint32_t RESERVED56[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED57[1U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ + uint32_t RESERVED59[860U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED60[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED61[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED62[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED63[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED64[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED65[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED66[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED67[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED68[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED69[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_TGL; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED70[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED71[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED72[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED73[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED74[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_TGL; /**< RTCC Clock Control */ + uint32_t RESERVED75[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_TGL; /**< Protocol RTC Clock Control */ + uint32_t RESERVED76[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED77[1U]; /**< Reserved for future use */ + uint32_t RESERVED78[1U]; /**< Reserved for future use */ +} CMU_TypeDef; +/** @} End of group EFR32BG29_CMU */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_CMU + * @{ + * @defgroup EFR32BG29_CMU_BitFields CMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0030001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFEFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 8 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x100UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART1 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART1_SHIFT 9 /**< Shift value for CMU_USART1 */ +#define _CMU_CLKEN0_USART1_MASK 0x200UL /**< Bit mask for CMU_USART1 */ +#define _CMU_CLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART1_DEFAULT (_CMU_CLKEN0_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 19 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x80000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 20 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x100000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 21 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x200000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 22 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x400000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 23 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x800000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PDM (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PDM_SHIFT 25 /**< Shift value for CMU_PDM */ +#define _CMU_CLKEN0_PDM_MASK 0x2000000UL /**< Bit mask for CMU_PDM */ +#define _CMU_CLKEN0_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PDM_DEFAULT (_CMU_CLKEN0_PDM_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RTCC (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RTCC_SHIFT 30 /**< Shift value for CMU_RTCC */ +#define _CMU_CLKEN0_RTCC_MASK 0x40000000UL /**< Bit mask for CMU_RTCC */ +#define _CMU_CLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RTCC_DEFAULT (_CMU_CLKEN0_RTCC_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ + +/* Bit fields for CMU CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x10FFDFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RDSCRATCHPAD */ +#define _CMU_CLKEN1_RDSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RDSCRATCHPAD */ +#define _CMU_CLKEN1_RDSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RDSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX0 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDMAILBOX0_SHIFT 8 /**< Shift value for CMU_RDMAILBOX0 */ +#define _CMU_CLKEN1_RDMAILBOX0_MASK 0x100UL /**< Bit mask for CMU_RDMAILBOX0 */ +#define _CMU_CLKEN1_RDMAILBOX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX0_DEFAULT (_CMU_CLKEN1_RDMAILBOX0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX1 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDMAILBOX1_SHIFT 9 /**< Shift value for CMU_RDMAILBOX1 */ +#define _CMU_CLKEN1_RDMAILBOX1_MASK 0x200UL /**< Bit mask for CMU_RDMAILBOX1 */ +#define _CMU_CLKEN1_RDMAILBOX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX1_DEFAULT (_CMU_CLKEN1_RDMAILBOX1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PRORTC (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PRORTC_SHIFT 10 /**< Shift value for CMU_PRORTC */ +#define _CMU_CLKEN1_PRORTC_MASK 0x400UL /**< Bit mask for CMU_PRORTC */ +#define _CMU_CLKEN1_PRORTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PRORTC_DEFAULT (_CMU_CLKEN1_PRORTC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_IFADCDEBUG (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_IFADCDEBUG_SHIFT 12 /**< Shift value for CMU_IFADCDEBUG */ +#define _CMU_CLKEN1_IFADCDEBUG_MASK 0x1000UL /**< Bit mask for CMU_IFADCDEBUG */ +#define _CMU_CLKEN1_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_IFADCDEBUG_DEFAULT (_CMU_CLKEN1_IFADCDEBUG_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSENSE (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSENSE_SHIFT 14 /**< Shift value for CMU_RFSENSE */ +#define _CMU_CLKEN1_RFSENSE_MASK 0x4000UL /**< Bit mask for CMU_RFSENSE */ +#define _CMU_CLKEN1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSENSE_DEFAULT (_CMU_CLKEN1_RFSENSE_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 15 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x8000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 16 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x10000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 17 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x20000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_TIMER4 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_TIMER4_SHIFT 18 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN1_TIMER4_MASK 0x40000UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_TIMER4_DEFAULT (_CMU_CLKEN1_TIMER4_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 19 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x80000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 20 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x100000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 21 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x200000UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 22 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x400000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ETAMPDET (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ETAMPDET_SHIFT 28 /**< Shift value for CMU_ETAMPDET */ +#define _CMU_CLKEN1_ETAMPDET_MASK 0x10000000UL /**< Bit mask for CMU_ETAMPDET */ +#define _CMU_CLKEN1_ETAMPDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ETAMPDET_DEFAULT (_CMU_CLKEN1_ETAMPDET_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ + +/* Bit fields for CMU SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ + +/* Bit fields for CMU TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000002UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DISABLED (_CMU_TRACECLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ + +/* Bit fields for CMU EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ + +/* Bit fields for CMU DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ + +/* Bit fields for CMU EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ + +/* Bit fields for CMU EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 (_CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPBCLKCTRL */ + +/* Bit fields for CMU EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ + +/* Bit fields for CMU EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ + +/* Bit fields for CMU EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ + +/* Bit fields for CMU IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ + +/* Bit fields for CMU WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ + +/* Bit fields for CMU RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_DEFAULT (_CMU_RTCCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_LFRCO (_CMU_RTCCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_LFXO (_CMU_RTCCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_ULFRCO (_CMU_RTCCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_RTCCCLKCTRL */ + +/* Bit fields for CMU PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT (_CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_LFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_LFXO (_CMU_PRORTCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_PRORTCCLKCTRL */ + +/* Bit fields for CMU RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_FORCECLKENRADIO (0x1UL << 1) /**< Force Radio Clock Enable in EM1P */ +#define _CMU_RADIOCLKCTRL_FORCECLKENRADIO_SHIFT 1 /**< Shift value for CMU_FORCECLKENRADIO */ +#define _CMU_RADIOCLKCTRL_FORCECLKENRADIO_MASK 0x2UL /**< Bit mask for CMU_FORCECLKENRADIO */ +#define _CMU_RADIOCLKCTRL_FORCECLKENRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_FORCECLKENRADIO_DEFAULT (_CMU_RADIOCLKCTRL_FORCECLKENRADIO_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ + +/* Bit fields for CMU EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_FSRCO (_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EUSART0CLKCTRL */ + +/** @} End of group EFR32BG29_CMU_BitFields */ +/** @} End of group EFR32BG29_CMU */ +/** @} End of group Parts */ + +#endif // EFR32BG29_CMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dcdc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dcdc.h new file mode 100644 index 000000000..09dffc9a5 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dcdc.h @@ -0,0 +1,718 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 DCDC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_DCDC_H +#define EFR32BG29_DCDC_H +#define DCDC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_DCDC DCDC + * @{ + * @brief EFR32BG29 DCDC Register Declaration. + *****************************************************************************/ + +/** DCDC Register Declaration. */ +typedef struct dcdc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0; /**< EM23 Control */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL; /**< Boost Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL; /**< EM23 Boost Control */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS; /**< Coulomb Counter Status */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[7U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[967U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL_SET; /**< Boost Control Register */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL_SET; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL_SET; /**< EM23 Boost Control */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL_SET; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL_SET; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD_SET; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT_SET; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT_SET; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR_SET; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF_SET; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN_SET; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS_SET; /**< Coulomb Counter Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[967U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL_CLR; /**< Boost Control Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL_CLR; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL_CLR; /**< EM23 Boost Control */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + uint32_t RESERVED30[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL_CLR; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL_CLR; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD_CLR; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT_CLR; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT_CLR; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR_CLR; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF_CLR; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN_CLR; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS_CLR; /**< Coulomb Counter Status */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ + uint32_t RESERVED32[2U]; /**< Reserved for future use */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + uint32_t RESERVED36[7U]; /**< Reserved for future use */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + uint32_t RESERVED38[967U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL_TGL; /**< Boost Control Register */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL_TGL; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL_TGL; /**< EM23 Boost Control */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + uint32_t RESERVED43[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL_TGL; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL_TGL; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD_TGL; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT_TGL; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT_TGL; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR_TGL; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF_TGL; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN_TGL; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS_TGL; /**< Coulomb Counter Status */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ + uint32_t RESERVED45[2U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[7U]; /**< Reserved for future use */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + uint32_t RESERVED49[7U]; /**< Reserved for future use */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ +} DCDC_TypeDef; +/** @} End of group EFR32BG29_DCDC */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_DCDC + * @{ + * @defgroup EFR32BG29_DCDC_BitFields DCDC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DCDC IPVERSION */ +#define _DCDC_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for DCDC_IPVERSION */ +#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ + +/* Bit fields for DCDC CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000040UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x0000CF71UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_OFF (_DCDC_CTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_SHIFT 8 /**< Shift value for DCDC_DVDDBSTPRG */ +#define _DCDC_CTRL_DVDDBSTPRG_MASK 0xF00UL /**< Bit mask for DCDC_DVDDBSTPRG */ +#define _DCDC_CTRL_DVDDBSTPRG_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_1V8 0x00000000UL /**< Mode BOOST_1V8 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_1V9 0x00000001UL /**< Mode BOOST_1V9 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V 0x00000002UL /**< Mode BOOST_2V for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V1 0x00000003UL /**< Mode BOOST_2V1 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V2 0x00000004UL /**< Mode BOOST_2V2 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V3 0x00000005UL /**< Mode BOOST_2V3 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V4 0x00000006UL /**< Mode BOOST_2V4 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_DEFAULT (_DCDC_CTRL_DVDDBSTPRG_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_1V8 (_DCDC_CTRL_DVDDBSTPRG_BOOST_1V8 << 8) /**< Shifted mode BOOST_1V8 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_1V9 (_DCDC_CTRL_DVDDBSTPRG_BOOST_1V9 << 8) /**< Shifted mode BOOST_1V9 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V << 8) /**< Shifted mode BOOST_2V for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V1 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V1 << 8) /**< Shifted mode BOOST_2V1 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V2 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V2 << 8) /**< Shifted mode BOOST_2V2 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V3 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V3 << 8) /**< Shifted mode BOOST_2V3 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V4 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V4 << 8) /**< Shifted mode BOOST_2V4 for DCDC_CTRL */ +#define DCDC_CTRL_FORCEBIAS (0x1UL << 14) /**< Force Comparators to be biased */ +#define _DCDC_CTRL_FORCEBIAS_SHIFT 14 /**< Shift value for DCDC_FORCEBIAS */ +#define _DCDC_CTRL_FORCEBIAS_MASK 0x4000UL /**< Bit mask for DCDC_FORCEBIAS */ +#define _DCDC_CTRL_FORCEBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_FORCEBIAS_DEFAULT (_DCDC_CTRL_FORCEBIAS_DEFAULT << 14) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_FIXEDEMBIAS (0x1UL << 15) /**< Force EM2 config settings */ +#define _DCDC_CTRL_FIXEDEMBIAS_SHIFT 15 /**< Shift value for DCDC_FIXEDEMBIAS */ +#define _DCDC_CTRL_FIXEDEMBIAS_MASK 0x8000UL /**< Bit mask for DCDC_FIXEDEMBIAS */ +#define _DCDC_CTRL_FIXEDEMBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_FIXEDEMBIAS_DEFAULT (_DCDC_CTRL_FIXEDEMBIAS_DEFAULT << 15) /**< Shifted mode DEFAULT for DCDC_CTRL */ + +/* Bit fields for DCDC EM01CTRL0 */ +#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ + +/* Bit fields for DCDC EM23CTRL0 */ +#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ + +/* Bit fields for DCDC BSTCTRL */ +#define _DCDC_BSTCTRL_RESETVALUE 0x00000047UL /**< Default value for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_MASK 0x00000077UL /**< Mask for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_SHIFT 0 /**< Shift value for DCDC_BSTTOFFMAX */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_MASK 0x7UL /**< Bit mask for DCDC_BSTTOFFMAX */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT 0x00000007UL /**< Mode DEFAULT for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_OFF 0x00000000UL /**< Mode OFF for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT (_DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_OFF (_DCDC_BSTCTRL_BSTTOFFMAX_OFF << 0) /**< Shifted mode OFF for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us << 0) /**< Shifted mode TMAX_0P35us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us << 0) /**< Shifted mode TMAX_0P63us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us << 0) /**< Shifted mode TMAX_0P91us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us << 0) /**< Shifted mode TMAX_1P19us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us << 0) /**< Shifted mode TMAX_1P47us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us << 0) /**< Shifted mode TMAX_1P75us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us << 0) /**< Shifted mode TMAX_2P03us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_OFF (_DCDC_BSTCTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_BSTCTRL */ + +/* Bit fields for DCDC BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_RESETVALUE 0x0000010DUL /**< Default value for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_MASK 0x0000030FUL /**< Mask for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_DEFAULT 0x0000000DUL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load10mA 0x00000004UL /**< Mode Load10mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load11mA 0x00000005UL /**< Mode Load11mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load13mA 0x00000006UL /**< Mode Load13mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load15mA 0x00000007UL /**< Mode Load15mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load16mA 0x00000008UL /**< Mode Load16mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load18mA 0x00000009UL /**< Mode Load18mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load20mA 0x0000000AUL /**< Mode Load20mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load21mA 0x0000000BUL /**< Mode Load21mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load23mA 0x0000000CUL /**< Mode Load23mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load25mA 0x0000000DUL /**< Mode Load25mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load26mA 0x0000000EUL /**< Mode Load26mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM01CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load10mA (_DCDC_BSTEM01CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load11mA (_DCDC_BSTEM01CTRL_IPKVAL_Load11mA << 0) /**< Shifted mode Load11mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load13mA (_DCDC_BSTEM01CTRL_IPKVAL_Load13mA << 0) /**< Shifted mode Load13mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load15mA (_DCDC_BSTEM01CTRL_IPKVAL_Load15mA << 0) /**< Shifted mode Load15mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load16mA (_DCDC_BSTEM01CTRL_IPKVAL_Load16mA << 0) /**< Shifted mode Load16mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load18mA (_DCDC_BSTEM01CTRL_IPKVAL_Load18mA << 0) /**< Shifted mode Load18mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load20mA (_DCDC_BSTEM01CTRL_IPKVAL_Load20mA << 0) /**< Shifted mode Load20mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load21mA (_DCDC_BSTEM01CTRL_IPKVAL_Load21mA << 0) /**< Shifted mode Load21mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load23mA (_DCDC_BSTEM01CTRL_IPKVAL_Load23mA << 0) /**< Shifted mode Load23mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load25mA (_DCDC_BSTEM01CTRL_IPKVAL_Load25mA << 0) /**< Shifted mode Load25mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load26mA (_DCDC_BSTEM01CTRL_IPKVAL_Load26mA << 0) /**< Shifted mode Load26mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT (_DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING (_DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_BSTEM01CTRL*/ + +/* Bit fields for DCDC BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_RESETVALUE 0x0000010AUL /**< Default value for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_MASK 0x0000030FUL /**< Mask for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_DEFAULT 0x0000000AUL /**< Mode DEFAULT for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_Load5mA 0x00000004UL /**< Mode Load5mA for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_Load10mA 0x0000000AUL /**< Mode Load10mA for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM23CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_IPKVAL_Load5mA (_DCDC_BSTEM23CTRL_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_IPKVAL_Load10mA (_DCDC_BSTEM23CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT (_DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING (_DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_BSTEM23CTRL*/ + +/* Bit fields for DCDC IF */ +#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ +#define _DCDC_IF_MASK 0x000000FFUL /**< Mask for DCDC_IF */ +#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ +#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ +#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ +#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold */ +#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold */ +#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ +#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX (0x1UL << 6) /**< Buck Max Ton/Boost Max Toff reached */ +#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ +#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ + +/* Bit fields for DCDC IEN */ +#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ +#define _DCDC_IEN_MASK 0x000000FFUL /**< Mask for DCDC_IEN */ +#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ +#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ +#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ +#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ +#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ +#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ +#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ + +/* Bit fields for DCDC STATUS */ +#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ +#define _DCDC_STATUS_MASK 0x0000001FUL /**< Mask for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ +#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ +#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ +#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ +#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ +#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ + +/* Bit fields for DCDC SYNCBUSY */ +#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_MASK 0x00000001UL /**< Mask for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< Combined Sync Busy Status */ +#define _DCDC_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_SYNCBUSY_DEFAULT (_DCDC_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ + +/* Bit fields for DCDC CCCTRL */ +#define _DCDC_CCCTRL_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCTRL */ +#define _DCDC_CCCTRL_MASK 0x00000001UL /**< Mask for DCDC_CCCTRL */ +#define DCDC_CCCTRL_CCEN (0x1UL << 0) /**< Coulomb Counter Enable */ +#define _DCDC_CCCTRL_CCEN_SHIFT 0 /**< Shift value for DCDC_CCEN */ +#define _DCDC_CCCTRL_CCEN_MASK 0x1UL /**< Bit mask for DCDC_CCEN */ +#define _DCDC_CCCTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCTRL */ +#define DCDC_CCCTRL_CCEN_DEFAULT (_DCDC_CCCTRL_CCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCTRL */ + +/* Bit fields for DCDC CCCALCTRL */ +#define _DCDC_CCCALCTRL_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_MASK 0x0000030FUL /**< Mask for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLOADEN (0x1UL << 0) /**< CC Load Circuit Enable */ +#define _DCDC_CCCALCTRL_CCLOADEN_SHIFT 0 /**< Shift value for DCDC_CCLOADEN */ +#define _DCDC_CCCALCTRL_CCLOADEN_MASK 0x1UL /**< Bit mask for DCDC_CCLOADEN */ +#define _DCDC_CCCALCTRL_CCLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLOADEN_DEFAULT (_DCDC_CCCALCTRL_CCLOADEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_SHIFT 1 /**< Shift value for DCDC_CCLVL */ +#define _DCDC_CCCALCTRL_CCLVL_MASK 0xEUL /**< Bit mask for DCDC_CCLVL */ +#define _DCDC_CCCALCTRL_CCLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD0 0x00000000UL /**< Mode LOAD0 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD1 0x00000001UL /**< Mode LOAD1 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD2 0x00000002UL /**< Mode LOAD2 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD3 0x00000003UL /**< Mode LOAD3 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD4 0x00000004UL /**< Mode LOAD4 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD5 0x00000005UL /**< Mode LOAD5 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD6 0x00000006UL /**< Mode LOAD6 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD7 0x00000007UL /**< Mode LOAD7 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_DEFAULT (_DCDC_CCCALCTRL_CCLVL_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD0 (_DCDC_CCCALCTRL_CCLVL_LOAD0 << 1) /**< Shifted mode LOAD0 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD1 (_DCDC_CCCALCTRL_CCLVL_LOAD1 << 1) /**< Shifted mode LOAD1 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD2 (_DCDC_CCCALCTRL_CCLVL_LOAD2 << 1) /**< Shifted mode LOAD2 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD3 (_DCDC_CCCALCTRL_CCLVL_LOAD3 << 1) /**< Shifted mode LOAD3 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD4 (_DCDC_CCCALCTRL_CCLVL_LOAD4 << 1) /**< Shifted mode LOAD4 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD5 (_DCDC_CCCALCTRL_CCLVL_LOAD5 << 1) /**< Shifted mode LOAD5 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD6 (_DCDC_CCCALCTRL_CCLVL_LOAD6 << 1) /**< Shifted mode LOAD6 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD7 (_DCDC_CCCALCTRL_CCLVL_LOAD7 << 1) /**< Shifted mode LOAD7 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALEM2 (0x1UL << 8) /**< CC Calibrate EM2 */ +#define _DCDC_CCCALCTRL_CCCALEM2_SHIFT 8 /**< Shift value for DCDC_CCCALEM2 */ +#define _DCDC_CCCALCTRL_CCCALEM2_MASK 0x100UL /**< Bit mask for DCDC_CCCALEM2 */ +#define _DCDC_CCCALCTRL_CCCALEM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALEM2_DEFAULT (_DCDC_CCCALCTRL_CCCALEM2_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALHALT (0x1UL << 9) /**< CC Calibration Halt Req */ +#define _DCDC_CCCALCTRL_CCCALHALT_SHIFT 9 /**< Shift value for DCDC_CCCALHALT */ +#define _DCDC_CCCALCTRL_CCCALHALT_MASK 0x200UL /**< Bit mask for DCDC_CCCALHALT */ +#define _DCDC_CCCALCTRL_CCCALHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALHALT_DEFAULT (_DCDC_CCCALCTRL_CCCALHALT_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ + +/* Bit fields for DCDC CCCMD */ +#define _DCDC_CCCMD_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCMD */ +#define _DCDC_CCCMD_MASK 0x00000007UL /**< Mask for DCDC_CCCMD */ +#define DCDC_CCCMD_START (0x1UL << 0) /**< Start CC */ +#define _DCDC_CCCMD_START_SHIFT 0 /**< Shift value for DCDC_START */ +#define _DCDC_CCCMD_START_MASK 0x1UL /**< Bit mask for DCDC_START */ +#define _DCDC_CCCMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_START_DEFAULT (_DCDC_CCCMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_STOP (0x1UL << 1) /**< Stop CC */ +#define _DCDC_CCCMD_STOP_SHIFT 1 /**< Shift value for DCDC_STOP */ +#define _DCDC_CCCMD_STOP_MASK 0x2UL /**< Bit mask for DCDC_STOP */ +#define _DCDC_CCCMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_STOP_DEFAULT (_DCDC_CCCMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_CLR (0x1UL << 2) /**< Clear CC */ +#define _DCDC_CCCMD_CLR_SHIFT 2 /**< Shift value for DCDC_CLR */ +#define _DCDC_CCCMD_CLR_MASK 0x4UL /**< Bit mask for DCDC_CLR */ +#define _DCDC_CCCMD_CLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_CLR_DEFAULT (_DCDC_CCCMD_CLR_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCCMD */ + +/* Bit fields for DCDC CCEM0CNT */ +#define _DCDC_CCEM0CNT_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCEM0CNT */ +#define _DCDC_CCEM0CNT_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCEM0CNT */ +#define _DCDC_CCEM0CNT_CCCNT_SHIFT 0 /**< Shift value for DCDC_CCCNT */ +#define _DCDC_CCEM0CNT_CCCNT_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_CCCNT */ +#define _DCDC_CCEM0CNT_CCCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCEM0CNT */ +#define DCDC_CCEM0CNT_CCCNT_DEFAULT (_DCDC_CCEM0CNT_CCCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCEM0CNT */ + +/* Bit fields for DCDC CCEM2CNT */ +#define _DCDC_CCEM2CNT_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCEM2CNT */ +#define _DCDC_CCEM2CNT_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCEM2CNT */ +#define _DCDC_CCEM2CNT_CCCNT_SHIFT 0 /**< Shift value for DCDC_CCCNT */ +#define _DCDC_CCEM2CNT_CCCNT_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_CCCNT */ +#define _DCDC_CCEM2CNT_CCCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCEM2CNT */ +#define DCDC_CCEM2CNT_CCCNT_DEFAULT (_DCDC_CCEM2CNT_CCCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCEM2CNT */ + +/* Bit fields for DCDC CCTHR */ +#define _DCDC_CCTHR_RESETVALUE 0x00010001UL /**< Default value for DCDC_CCTHR */ +#define _DCDC_CCTHR_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCTHR */ +#define _DCDC_CCTHR_EM0CNT_SHIFT 0 /**< Shift value for DCDC_EM0CNT */ +#define _DCDC_CCTHR_EM0CNT_MASK 0xFFFFUL /**< Bit mask for DCDC_EM0CNT */ +#define _DCDC_CCTHR_EM0CNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CCTHR */ +#define DCDC_CCTHR_EM0CNT_DEFAULT (_DCDC_CCTHR_EM0CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCTHR */ +#define _DCDC_CCTHR_EM2CNT_SHIFT 16 /**< Shift value for DCDC_EM2CNT */ +#define _DCDC_CCTHR_EM2CNT_MASK 0xFFFF0000UL /**< Bit mask for DCDC_EM2CNT */ +#define _DCDC_CCTHR_EM2CNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CCTHR */ +#define DCDC_CCTHR_EM2CNT_DEFAULT (_DCDC_CCTHR_EM2CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DCDC_CCTHR */ + +/* Bit fields for DCDC CCIF */ +#define _DCDC_CCIF_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCIF */ +#define _DCDC_CCIF_MASK 0x0000000FUL /**< Mask for DCDC_CCIF */ +#define DCDC_CCIF_EM0OF (0x1UL << 0) /**< EM0 Counter Overflow */ +#define _DCDC_CCIF_EM0OF_SHIFT 0 /**< Shift value for DCDC_EM0OF */ +#define _DCDC_CCIF_EM0OF_MASK 0x1UL /**< Bit mask for DCDC_EM0OF */ +#define _DCDC_CCIF_EM0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM0OF_DEFAULT (_DCDC_CCIF_EM0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2OF (0x1UL << 1) /**< EM2 Counter Overflow */ +#define _DCDC_CCIF_EM2OF_SHIFT 1 /**< Shift value for DCDC_EM2OF */ +#define _DCDC_CCIF_EM2OF_MASK 0x2UL /**< Bit mask for DCDC_EM2OF */ +#define _DCDC_CCIF_EM2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2OF_DEFAULT (_DCDC_CCIF_EM2OF_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM0CMP (0x1UL << 2) /**< EM0 Counter Compare Match */ +#define _DCDC_CCIF_EM0CMP_SHIFT 2 /**< Shift value for DCDC_EM0CMP */ +#define _DCDC_CCIF_EM0CMP_MASK 0x4UL /**< Bit mask for DCDC_EM0CMP */ +#define _DCDC_CCIF_EM0CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM0CMP_DEFAULT (_DCDC_CCIF_EM0CMP_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2CMP (0x1UL << 3) /**< EM2 Counter Compare Match */ +#define _DCDC_CCIF_EM2CMP_SHIFT 3 /**< Shift value for DCDC_EM2CMP */ +#define _DCDC_CCIF_EM2CMP_MASK 0x8UL /**< Bit mask for DCDC_EM2CMP */ +#define _DCDC_CCIF_EM2CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2CMP_DEFAULT (_DCDC_CCIF_EM2CMP_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_CCIF */ + +/* Bit fields for DCDC CCIEN */ +#define _DCDC_CCIEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCIEN */ +#define _DCDC_CCIEN_MASK 0x0000000FUL /**< Mask for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0OF (0x1UL << 0) /**< Clmb Cntr EM0 Overflow Interrupt Enable */ +#define _DCDC_CCIEN_EM0OF_SHIFT 0 /**< Shift value for DCDC_EM0OF */ +#define _DCDC_CCIEN_EM0OF_MASK 0x1UL /**< Bit mask for DCDC_EM0OF */ +#define _DCDC_CCIEN_EM0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0OF_DEFAULT (_DCDC_CCIEN_EM0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2OF (0x1UL << 1) /**< Clmb Cntr EM2 Overflow Interrupt Enable */ +#define _DCDC_CCIEN_EM2OF_SHIFT 1 /**< Shift value for DCDC_EM2OF */ +#define _DCDC_CCIEN_EM2OF_MASK 0x2UL /**< Bit mask for DCDC_EM2OF */ +#define _DCDC_CCIEN_EM2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2OF_DEFAULT (_DCDC_CCIEN_EM2OF_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0CMP (0x1UL << 2) /**< Clmb Cntr EM0 Cmp Match Interrupt Enable */ +#define _DCDC_CCIEN_EM0CMP_SHIFT 2 /**< Shift value for DCDC_EM0CMP */ +#define _DCDC_CCIEN_EM0CMP_MASK 0x4UL /**< Bit mask for DCDC_EM0CMP */ +#define _DCDC_CCIEN_EM0CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0CMP_DEFAULT (_DCDC_CCIEN_EM0CMP_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2CMP (0x1UL << 3) /**< Clmb Cntr EM2 Cmp Match Interrupt Enable */ +#define _DCDC_CCIEN_EM2CMP_SHIFT 3 /**< Shift value for DCDC_EM2CMP */ +#define _DCDC_CCIEN_EM2CMP_MASK 0x8UL /**< Bit mask for DCDC_EM2CMP */ +#define _DCDC_CCIEN_EM2CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2CMP_DEFAULT (_DCDC_CCIEN_EM2CMP_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_CCIEN */ + +/* Bit fields for DCDC CCSTATUS */ +#define _DCDC_CCSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCSTATUS */ +#define _DCDC_CCSTATUS_MASK 0x00000003UL /**< Mask for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CLRBSY (0x1UL << 0) /**< Coulomb Counter Clear Busy */ +#define _DCDC_CCSTATUS_CLRBSY_SHIFT 0 /**< Shift value for DCDC_CLRBSY */ +#define _DCDC_CCSTATUS_CLRBSY_MASK 0x1UL /**< Bit mask for DCDC_CLRBSY */ +#define _DCDC_CCSTATUS_CLRBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CLRBSY_DEFAULT (_DCDC_CCSTATUS_CLRBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CCRUNNING (0x1UL << 1) /**< Coulomb Counter Running */ +#define _DCDC_CCSTATUS_CCRUNNING_SHIFT 1 /**< Shift value for DCDC_CCRUNNING */ +#define _DCDC_CCSTATUS_CCRUNNING_MASK 0x2UL /**< Bit mask for DCDC_CCRUNNING */ +#define _DCDC_CCSTATUS_CCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CCRUNNING_DEFAULT (_DCDC_CCSTATUS_CCRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCSTATUS */ + +/* Bit fields for DCDC LOCK */ +#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ +#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ + +/* Bit fields for DCDC LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ +#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ + +/** @} End of group EFR32BG29_DCDC_BitFields */ +/** @} End of group EFR32BG29_DCDC */ +/** @} End of group Parts */ + +#endif // EFR32BG29_DCDC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_devinfo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_devinfo.h new file mode 100644 index 000000000..6bbfdaedc --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_devinfo.h @@ -0,0 +1,954 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 DEVINFO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_DEVINFO_H +#define EFR32BG29_DEVINFO_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_DEVINFO DEVINFO + * @{ + * @brief EFR32BG29 DEVINFO Register Declaration. + *****************************************************************************/ + +/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ +typedef struct devinfo_hfrcodpllcal_typedef{ + __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ +} DEVINFO_HFRCODPLLCAL_TypeDef; + +/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ +typedef struct devinfo_hfrcoem23cal_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOEM23CAL_TypeDef; + +/** DEVINFO HFRCOSECAL Register Group Declaration. */ +typedef struct devinfo_hfrcosecal_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOSECAL_TypeDef; + +/** DEVINFO Register Declaration. */ +typedef struct devinfo_typedef{ + __IM uint32_t INFO; /**< DI Information */ + __IM uint32_t PART; /**< Part Info */ + __IM uint32_t MEMINFO; /**< Memory Info */ + __IM uint32_t MSIZE; /**< Memory Size */ + __IM uint32_t PKGINFO; /**< Misc Device Info */ + __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ + __IM uint32_t SWFIX; /**< SW Fix Register */ + __IM uint32_t SWCAPA0; /**< Software Restriction */ + __IM uint32_t SWCAPA1; /**< Software Restriction */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t EXTINFO; /**< External Component Info */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t EUI48L; /**< EUI 48 Low */ + __IM uint32_t EUI48H; /**< EUI 48 High */ + __IM uint32_t EUI64L; /**< EUI64 Low */ + __IM uint32_t EUI64H; /**< EUI64 High */ + __IM uint32_t CALTEMP; /**< Calibration temperature Information */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Sensor Calibration Information */ + DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ + DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ + DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ + __IM uint32_t MODULENAME0; /**< Module Name Information */ + __IM uint32_t MODULENAME1; /**< Module Name Information */ + __IM uint32_t MODULENAME2; /**< Module Name Information */ + __IM uint32_t MODULENAME3; /**< Module Name Information */ + __IM uint32_t MODULENAME4; /**< Module Name Information */ + __IM uint32_t MODULENAME5; /**< Module Name Information */ + __IM uint32_t MODULENAME6; /**< Module Name Information */ + __IM uint32_t MODULEINFO; /**< Module Information */ + __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ + __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ + __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ + uint32_t RESERVED4[24U]; /**< Reserved for future use */ + __IM uint32_t LEGACY; /**< Legacy Device Info */ + uint32_t RESERVED5[23U]; /**< Reserved for future use */ + __IM uint32_t RTHERM; /**< Thermistor Calibration */ + uint32_t RESERVED6[40U]; /**< Reserved for future use */ + __IM uint32_t CCLOAD10; /**< Current level 1 and 0 */ + __IM uint32_t CCLOAD32; /**< Current level 3 and 2 */ + __IM uint32_t CCLOAD54; /**< Current level 5 and 4 */ + __IM uint32_t CCLOAD76; /**< Current level 7 and 6 */ + uint32_t RESERVED7[36U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ +} DEVINFO_TypeDef; +/** @} End of group EFR32BG29_DEVINFO */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_DEVINFO + * @{ + * @defgroup EFR32BG29_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x14000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ +#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x00000014UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ +#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ + +/* Bit fields for DEVINFO PKGINFO */ +#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N20TO55 0x00000004UL /**< Mode N20TO55 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N20TO55 (_DEVINFO_PKGINFO_TEMPGRADE_N20TO55 << 0) /**< Shifted mode N20TO55 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ +#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ + +/* Bit fields for DEVINFO SWFIX */ +#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ +#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ + +/* Bit fields for DEVINFO SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_MASK 0x00333333UL /**< Mask for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ + +/* Bit fields for DEVINFO SWCAPA1 */ +#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ +#define _DEVINFO_SWCAPA1_MASK 0x00000007UL /**< Mask for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ +#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ +#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ +#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ + +/* Bit fields for DEVINFO EUI64L */ +#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ +#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ + +/* Bit fields for DEVINFO EUI64H */ +#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ + +/* Bit fields for DEVINFO CALTEMP */ +#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ +#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ +#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ + +/* Bit fields for DEVINFO HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ + +/* Bit fields for DEVINFO MODULENAME0 */ +#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ + +/* Bit fields for DEVINFO MODULENAME1 */ +#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ + +/* Bit fields for DEVINFO MODULENAME2 */ +#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ + +/* Bit fields for DEVINFO MODULENAME3 */ +#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ + +/* Bit fields for DEVINFO MODULENAME4 */ +#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ + +/* Bit fields for DEVINFO MODULENAME5 */ +#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ + +/* Bit fields for DEVINFO MODULENAME6 */ +#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ +#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ +#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ + +/* Bit fields for DEVINFO IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ + +/* Bit fields for DEVINFO IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ + +/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ + +/* Bit fields for DEVINFO LEGACY */ +#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ + +/* Bit fields for DEVINFO RTHERM */ +#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ +#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ + +/* Bit fields for DEVINFO CCLOAD10 */ +#define _DEVINFO_CCLOAD10_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD10 */ +#define _DEVINFO_CCLOAD10_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD10 */ +#define _DEVINFO_CCLOAD10_CCLOAD0_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD0 */ +#define _DEVINFO_CCLOAD10_CCLOAD0_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD0 */ +#define _DEVINFO_CCLOAD10_CCLOAD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD10 */ +#define DEVINFO_CCLOAD10_CCLOAD0_DEFAULT (_DEVINFO_CCLOAD10_CCLOAD0_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD10 */ +#define _DEVINFO_CCLOAD10_CCLOAD1_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD1 */ +#define _DEVINFO_CCLOAD10_CCLOAD1_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD1 */ +#define _DEVINFO_CCLOAD10_CCLOAD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD10 */ +#define DEVINFO_CCLOAD10_CCLOAD1_DEFAULT (_DEVINFO_CCLOAD10_CCLOAD1_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD10 */ + +/* Bit fields for DEVINFO CCLOAD32 */ +#define _DEVINFO_CCLOAD32_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD32 */ +#define _DEVINFO_CCLOAD32_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD32 */ +#define _DEVINFO_CCLOAD32_CCLOAD2_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD2 */ +#define _DEVINFO_CCLOAD32_CCLOAD2_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD2 */ +#define _DEVINFO_CCLOAD32_CCLOAD2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD32 */ +#define DEVINFO_CCLOAD32_CCLOAD2_DEFAULT (_DEVINFO_CCLOAD32_CCLOAD2_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD32 */ +#define _DEVINFO_CCLOAD32_CCLOAD3_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD3 */ +#define _DEVINFO_CCLOAD32_CCLOAD3_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD3 */ +#define _DEVINFO_CCLOAD32_CCLOAD3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD32 */ +#define DEVINFO_CCLOAD32_CCLOAD3_DEFAULT (_DEVINFO_CCLOAD32_CCLOAD3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD32 */ + +/* Bit fields for DEVINFO CCLOAD54 */ +#define _DEVINFO_CCLOAD54_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD54 */ +#define _DEVINFO_CCLOAD54_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD54 */ +#define _DEVINFO_CCLOAD54_CCLOAD4_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD4 */ +#define _DEVINFO_CCLOAD54_CCLOAD4_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD4 */ +#define _DEVINFO_CCLOAD54_CCLOAD4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD54 */ +#define DEVINFO_CCLOAD54_CCLOAD4_DEFAULT (_DEVINFO_CCLOAD54_CCLOAD4_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD54 */ +#define _DEVINFO_CCLOAD54_CCLOAD5_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD5 */ +#define _DEVINFO_CCLOAD54_CCLOAD5_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD5 */ +#define _DEVINFO_CCLOAD54_CCLOAD5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD54 */ +#define DEVINFO_CCLOAD54_CCLOAD5_DEFAULT (_DEVINFO_CCLOAD54_CCLOAD5_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD54 */ + +/* Bit fields for DEVINFO CCLOAD76 */ +#define _DEVINFO_CCLOAD76_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD76 */ +#define _DEVINFO_CCLOAD76_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD76 */ +#define _DEVINFO_CCLOAD76_CCLOAD6_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD6 */ +#define _DEVINFO_CCLOAD76_CCLOAD6_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD6 */ +#define _DEVINFO_CCLOAD76_CCLOAD6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD76 */ +#define DEVINFO_CCLOAD76_CCLOAD6_DEFAULT (_DEVINFO_CCLOAD76_CCLOAD6_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD76 */ +#define _DEVINFO_CCLOAD76_CCLOAD7_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD7 */ +#define _DEVINFO_CCLOAD76_CCLOAD7_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD7 */ +#define _DEVINFO_CCLOAD76_CCLOAD7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD76 */ +#define DEVINFO_CCLOAD76_CCLOAD7_DEFAULT (_DEVINFO_CCLOAD76_CCLOAD7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD76 */ + +/** @} End of group EFR32BG29_DEVINFO_BitFields */ +/** @} End of group EFR32BG29_DEVINFO */ +/** @} End of group Parts */ + +#endif // EFR32BG29_DEVINFO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dma_descriptor.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dma_descriptor.h new file mode 100644 index 000000000..2d825bb0b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dma_descriptor.h @@ -0,0 +1,59 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 DMA descriptor bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_DMA_DESCRIPTOR_H +#define EFR32BG29_DMA_DESCRIPTOR_H + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup DMA_DESCRIPTOR DMA Descriptor + * @{ + *****************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + +#endif // EFR32BG29_DMA_DESCRIPTOR_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dpll.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dpll.h new file mode 100644 index 000000000..244dbc362 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_dpll.h @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 DPLL register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_DPLL_H +#define EFR32BG29_DPLL_H +#define DPLL_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_DPLL DPLL + * @{ + * @brief EFR32BG29 DPLL Register Declaration. + *****************************************************************************/ + +/** DPLL Register Declaration. */ +typedef struct dpll_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ +} DPLL_TypeDef; +/** @} End of group EFR32BG29_DPLL */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_DPLL + * @{ + * @defgroup EFR32BG29_DPLL_BitFields DPLL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DPLL IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ + +/* Bit fields for DPLL EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ + +/* Bit fields for DPLL CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ + +/* Bit fields for DPLL CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ + +/* Bit fields for DPLL IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ + +/* Bit fields for DPLL IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ + +/* Bit fields for DPLL STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ + +/* Bit fields for DPLL LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ + +/** @} End of group EFR32BG29_DPLL_BitFields */ +/** @} End of group EFR32BG29_DPLL */ +/** @} End of group Parts */ + +#endif // EFR32BG29_DPLL_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_emu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_emu.h new file mode 100644 index 000000000..96d0c3812 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_emu.h @@ -0,0 +1,862 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 EMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_EMU_H +#define EFR32BG29_EMU_H +#define EMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_EMU EMU + * @{ + * @brief EFR32BG29 EMU Register Declaration. + *****************************************************************************/ + +/** EMU Register Declaration. */ +typedef struct emu_typedef{ + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL; /**< Boost Enable Control */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[27U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[926U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED17[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED19[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED23[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL_SET; /**< Boost Enable Control */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[27U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[926U]; /**< Reserved for future use */ + uint32_t RESERVED32[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED34[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED39[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL_CLR; /**< Boost Enable Control */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[27U]; /**< Reserved for future use */ + uint32_t RESERVED45[1U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[926U]; /**< Reserved for future use */ + uint32_t RESERVED48[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED49[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED50[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED51[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED52[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED55[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL_TGL; /**< Boost Enable Control */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED58[2U]; /**< Reserved for future use */ + uint32_t RESERVED59[1U]; /**< Reserved for future use */ + uint32_t RESERVED60[27U]; /**< Reserved for future use */ + uint32_t RESERVED61[1U]; /**< Reserved for future use */ + uint32_t RESERVED62[1U]; /**< Reserved for future use */ +} EMU_TypeDef; +/** @} End of group EFR32BG29_EMU */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_EMU + * @{ + * @defgroup EFR32BG29_EMU_BitFields EMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ + +/* Bit fields for EMU BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ + +/* Bit fields for EMU VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ + +/* Bit fields for EMU PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN 0x00000000UL /**< Mode RETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN << 0) /**< Shifted mode RETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ + +/* Bit fields for EMU IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x0000000AUL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x0000000AUL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB370000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTPOSEDGE (0x1UL << 20) /**< BOOST_EN Rising Edge Interrupt flag */ +#define _EMU_IF_BOOSTPOSEDGE_SHIFT 20 /**< Shift value for EMU_BOOSTPOSEDGE */ +#define _EMU_IF_BOOSTPOSEDGE_MASK 0x100000UL /**< Bit mask for EMU_BOOSTPOSEDGE */ +#define _EMU_IF_BOOSTPOSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTPOSEDGE_DEFAULT (_EMU_IF_BOOSTPOSEDGE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTNEGEDGE (0x1UL << 21) /**< BOOST_EN Falling Edge Interrupt flag */ +#define _EMU_IF_BOOSTNEGEDGE_SHIFT 21 /**< Shift value for EMU_BOOSTNEGEDGE */ +#define _EMU_IF_BOOSTNEGEDGE_MASK 0x200000UL /**< Bit mask for EMU_BOOSTNEGEDGE */ +#define _EMU_IF_BOOSTNEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTNEGEDGE_DEFAULT (_EMU_IF_BOOSTNEGEDGE_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB370000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTPOSEDGE (0x1UL << 20) /**< BOOST_EN Rising edge Interrupt enable */ +#define _EMU_IEN_BOOSTPOSEDGE_SHIFT 20 /**< Shift value for EMU_BOOSTPOSEDGE */ +#define _EMU_IEN_BOOSTPOSEDGE_MASK 0x100000UL /**< Bit mask for EMU_BOOSTPOSEDGE */ +#define _EMU_IEN_BOOSTPOSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTPOSEDGE_DEFAULT (_EMU_IEN_BOOSTPOSEDGE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTNEGEDGE (0x1UL << 21) /**< BOOST_EN Falling edge Interrupt enable */ +#define _EMU_IEN_BOOSTNEGEDGE_SHIFT 21 /**< Shift value for EMU_BOOSTNEGEDGE */ +#define _EMU_IEN_BOOSTNEGEDGE_MASK 0x200000UL /**< Bit mask for EMU_BOOSTNEGEDGE */ +#define _EMU_IEN_BOOSTNEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTNEGEDGE_DEFAULT (_EMU_IEN_BOOSTNEGEDGE_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ +#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00007200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0017B09UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_HDREGEM2EXITCLIM (0x1UL << 11) /**< HDREG EM2 Exit current limit */ +#define _EMU_CTRL_HDREGEM2EXITCLIM_SHIFT 11 /**< Shift value for EMU_HDREGEM2EXITCLIM */ +#define _EMU_CTRL_HDREGEM2EXITCLIM_MASK 0x800UL /**< Bit mask for EMU_HDREGEM2EXITCLIM */ +#define _EMU_CTRL_HDREGEM2EXITCLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_HDREGEM2EXITCLIM_DEFAULT (_EMU_CTRL_HDREGEM2EXITCLIM_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_SHIFT 12 /**< Shift value for EMU_HDREGSTOPGEAR */ +#define _EMU_CTRL_HDREGSTOPGEAR_MASK 0x7000UL /**< Bit mask for EMU_HDREGSTOPGEAR */ +#define _EMU_CTRL_HDREGSTOPGEAR_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA 0x00000000UL /**< Mode ILMT_4MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA 0x00000001UL /**< Mode ILMT_8MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA 0x00000002UL /**< Mode ILMT_12MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA 0x00000003UL /**< Mode ILMT_16MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA 0x00000004UL /**< Mode ILMT_24MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA 0x00000005UL /**< Mode ILMT_48MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA 0x00000006UL /**< Mode ILMT_64MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX 0x00000007UL /**< Mode ILMT_MAX for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_DEFAULT (_EMU_CTRL_HDREGSTOPGEAR_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA << 12) /**< Shifted mode ILMT_4MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA << 12) /**< Shifted mode ILMT_8MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA << 12) /**< Shifted mode ILMT_12MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA << 12) /**< Shifted mode ILMT_16MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA << 12) /**< Shifted mode ILMT_24MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA << 12) /**< Shifted mode ILMT_48MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA << 12) /**< Shifted mode ILMT_64MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX (_EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX << 12) /**< Shifted mode ILMT_MAX for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFE154FFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BOOSTENPIN (0x1UL << 16) /**< BOOST_EN pin status */ +#define _EMU_STATUS_BOOSTENPIN_SHIFT 16 /**< Shift value for EMU_BOOSTENPIN */ +#define _EMU_STATUS_BOOSTENPIN_MASK 0x10000UL /**< Bit mask for EMU_BOOSTENPIN */ +#define _EMU_STATUS_BOOSTENPIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BOOSTENPIN_DEFAULT (_EMU_STATUS_BOOSTENPIN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00070407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC007C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE (0x1UL << 16) /**< DCI System reset */ +#define _EMU_RSTCTRL_DCIRMODE_SHIFT 16 /**< Shift value for EMU_DCIRMODE */ +#define _EMU_RSTCTRL_DCIRMODE_MASK 0x10000UL /**< Bit mask for EMU_DCIRMODE */ +#define _EMU_RSTCTRL_DCIRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DCIRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DCIRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_DEFAULT (_EMU_RSTCTRL_DCIRMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_DISABLED (_EMU_RSTCTRL_DCIRMODE_DISABLED << 16) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_ENABLED (_EMU_RSTCTRL_DCIRMODE_ENABLED << 16) /**< Shifted mode ENABLED for EMU_RSTCTRL */ + +/* Bit fields for EMU RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8017FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ +#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DCI (0x1UL << 16) /**< DCI reset */ +#define _EMU_RSTCAUSE_DCI_SHIFT 16 /**< Shift value for EMU_DCI */ +#define _EMU_RSTCAUSE_DCI_MASK 0x10000UL /**< Bit mask for EMU_DCI */ +#define _EMU_RSTCAUSE_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DCI_DEFAULT (_EMU_RSTCAUSE_DCI_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_BOOSTON (0x1UL << 20) /**< BOOST_EN pin reset */ +#define _EMU_RSTCAUSE_BOOSTON_SHIFT 20 /**< Shift value for EMU_BOOSTON */ +#define _EMU_RSTCAUSE_BOOSTON_MASK 0x100000UL /**< Bit mask for EMU_BOOSTON */ +#define _EMU_RSTCAUSE_BOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_BOOSTON_DEFAULT (_EMU_RSTCAUSE_BOOSTON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ + +/* Bit fields for EMU TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ + +/* Bit fields for EMU DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ + +/* Bit fields for EMU DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ + +/* Bit fields for EMU BOOSTCTRL */ +#define _EMU_BOOSTCTRL_RESETVALUE 0x00000001UL /**< Default value for EMU_BOOSTCTRL */ +#define _EMU_BOOSTCTRL_MASK 0x00000001UL /**< Mask for EMU_BOOSTCTRL */ +#define EMU_BOOSTCTRL_BOOSTENCTRL (0x1UL << 0) /**< BOOST_EN Control */ +#define _EMU_BOOSTCTRL_BOOSTENCTRL_SHIFT 0 /**< Shift value for EMU_BOOSTENCTRL */ +#define _EMU_BOOSTCTRL_BOOSTENCTRL_MASK 0x1UL /**< Bit mask for EMU_BOOSTENCTRL */ +#define _EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BOOSTCTRL */ +#define EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT (_EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOOSTCTRL */ + +/* Bit fields for EMU EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ + +/* Bit fields for EMU EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ + +/** @} End of group EFR32BG29_EMU_BitFields */ +/** @} End of group EFR32BG29_EMU */ +/** @} End of group Parts */ + +#endif // EFR32BG29_EMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_etampdet.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_etampdet.h new file mode 100644 index 000000000..f456676a0 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_etampdet.h @@ -0,0 +1,646 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 ETAMPDET register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_ETAMPDET_H +#define EFR32BG29_ETAMPDET_H +#define ETAMPDET_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_ETAMPDET ETAMPDET + * @{ + * @brief EFR32BG29 ETAMPDET Register Declaration. + *****************************************************************************/ + +/** ETAMPDET Register Declaration. */ +typedef struct etampdet_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE; /**< Filter moving window size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL; /**< Prescaler Ctrl Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED2[1005U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX_SET; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE_SET; /**< Filter moving window size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0_SET; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1_SET; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL_SET; /**< Prescaler Ctrl Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED5[1005U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX_CLR; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE_CLR; /**< Filter moving window size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0_CLR; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1_CLR; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL_CLR; /**< Prescaler Ctrl Register */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED8[1005U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX_TGL; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE_TGL; /**< Filter moving window size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0_TGL; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1_TGL; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL_TGL; /**< Prescaler Ctrl Register */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} ETAMPDET_TypeDef; +/** @} End of group EFR32BG29_ETAMPDET */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_ETAMPDET + * @{ + * @defgroup EFR32BG29_ETAMPDET_BitFields ETAMPDET Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ETAMPDET IPVERSION */ +#define _ETAMPDET_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETAMPDET_IPVERSION */ +#define ETAMPDET_IPVERSION_IPVERSION_DEFAULT (_ETAMPDET_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_IPVERSION */ + +/* Bit fields for ETAMPDET EN */ +#define _ETAMPDET_EN_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_EN */ +#define _ETAMPDET_EN_MASK 0x00000001UL /**< Mask for ETAMPDET_EN */ +#define ETAMPDET_EN_EN (0x1UL << 0) /**< ETAMPDET Enable */ +#define _ETAMPDET_EN_EN_SHIFT 0 /**< Shift value for ETAMPDET_EN */ +#define _ETAMPDET_EN_EN_MASK 0x1UL /**< Bit mask for ETAMPDET_EN */ +#define _ETAMPDET_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_EN */ +#define ETAMPDET_EN_EN_DEFAULT (_ETAMPDET_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_EN */ + +/* Bit fields for ETAMPDET CFG */ +#define _ETAMPDET_CFG_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_MASK 0x0000003FUL /**< Mask for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0 (0x1UL << 0) /**< enable delay for comparison */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLCMPDLYEN0 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLCMPDLYEN0 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_X0 0x00000000UL /**< Mode X0 for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_X1 0x00000001UL /**< Mode X1 for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0_DEFAULT (_ETAMPDET_CFG_CHNLCMPDLYEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0_X0 (_ETAMPDET_CFG_CHNLCMPDLYEN0_X0 << 0) /**< Shifted mode X0 for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0_X1 (_ETAMPDET_CFG_CHNLCMPDLYEN0_X1 << 0) /**< Shifted mode X1 for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0 (0x1UL << 1) /**< enable detect filtering */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_SHIFT 1 /**< Shift value for ETAMPDET_CHNLTAMPDETFILTEN0 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLTAMPDETFILTEN0 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DEFAULT (_ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DISABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DISABLE << 1) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0_ENABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN0_ENABLE << 1) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0 (0x1UL << 2) /**< enable driving pad */ +#define _ETAMPDET_CFG_CHNLPADEN0_SHIFT 2 /**< Shift value for ETAMPDET_CHNLPADEN0 */ +#define _ETAMPDET_CFG_CHNLPADEN0_MASK 0x4UL /**< Bit mask for ETAMPDET_CHNLPADEN0 */ +#define _ETAMPDET_CFG_CHNLPADEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN0_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN0_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0_DEFAULT (_ETAMPDET_CFG_CHNLPADEN0_DEFAULT << 2) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0_DISABLE (_ETAMPDET_CFG_CHNLPADEN0_DISABLE << 2) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0_ENABLE (_ETAMPDET_CFG_CHNLPADEN0_ENABLE << 2) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1 (0x1UL << 3) /**< enable delay for comparison */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLCMPDLYEN1 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_MASK 0x8UL /**< Bit mask for ETAMPDET_CHNLCMPDLYEN1 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1_DEFAULT (_ETAMPDET_CFG_CHNLCMPDLYEN1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1_DISABLE (_ETAMPDET_CFG_CHNLCMPDLYEN1_DISABLE << 3) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1_ENABLE (_ETAMPDET_CFG_CHNLCMPDLYEN1_ENABLE << 3) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1 (0x1UL << 4) /**< enable detect filtering */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLTAMPDETFILTEN1 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_MASK 0x10UL /**< Bit mask for ETAMPDET_CHNLTAMPDETFILTEN1 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DEFAULT (_ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DISABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DISABLE << 4) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1_ENABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN1_ENABLE << 4) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1 (0x1UL << 5) /**< enable driving pad */ +#define _ETAMPDET_CFG_CHNLPADEN1_SHIFT 5 /**< Shift value for ETAMPDET_CHNLPADEN1 */ +#define _ETAMPDET_CFG_CHNLPADEN1_MASK 0x20UL /**< Bit mask for ETAMPDET_CHNLPADEN1 */ +#define _ETAMPDET_CFG_CHNLPADEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN1_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN1_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1_DEFAULT (_ETAMPDET_CFG_CHNLPADEN1_DEFAULT << 5) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1_DISABLE (_ETAMPDET_CFG_CHNLPADEN1_DISABLE << 5) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1_ENABLE (_ETAMPDET_CFG_CHNLPADEN1_ENABLE << 5) /**< Shifted mode ENABLE for ETAMPDET_CFG */ + +/* Bit fields for ETAMPDET CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_MASK 0x0000003FUL /**< Mask for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLCNTMISMATCHMAX0*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_MASK 0x7UL /**< Bit mask for ETAMPDET_CHNLCNTMISMATCHMAX0 */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold1 0x00000000UL /**< Mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold2 0x00000001UL /**< Mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold3 0x00000002UL /**< Mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold4 0x00000003UL /**< Mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold5 0x00000004UL /**< Mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold6 0x00000005UL /**< Mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold7 0x00000006UL /**< Mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold8 0x00000007UL /**< Mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DEFAULT (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold1 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold1 << 0) /**< Shifted mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold2 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold2 << 0) /**< Shifted mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold3 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold3 << 0) /**< Shifted mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold4 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold4 << 0) /**< Shifted mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold5 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold5 << 0) /**< Shifted mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold6 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold6 << 0) /**< Shifted mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold7 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold7 << 0) /**< Shifted mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold8 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold8 << 0) /**< Shifted mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLCNTMISMATCHMAX1*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_MASK 0x38UL /**< Bit mask for ETAMPDET_CHNLCNTMISMATCHMAX1 */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold1 0x00000000UL /**< Mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold2 0x00000001UL /**< Mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold3 0x00000002UL /**< Mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold4 0x00000003UL /**< Mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold5 0x00000004UL /**< Mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold6 0x00000005UL /**< Mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold7 0x00000006UL /**< Mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold8 0x00000007UL /**< Mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DEFAULT (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold1 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold1 << 3) /**< Shifted mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold2 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold2 << 3) /**< Shifted mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold3 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold3 << 3) /**< Shifted mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold4 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold4 << 3) /**< Shifted mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold5 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold5 << 3) /**< Shifted mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold6 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold6 << 3) /**< Shifted mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold7 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold7 << 3) /**< Shifted mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold8 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold8 << 3) /**< Shifted mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ + +/* Bit fields for ETAMPDET CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_MASK 0x000000FFUL /**< Mask for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLFILTWINSIZE0 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_MASK 0xFUL /**< Bit mask for ETAMPDET_CHNLFILTWINSIZE0 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_Reserved 0x00000000UL /**< Mode Reserved for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize2 0x00000001UL /**< Mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize3 0x00000002UL /**< Mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize4 0x00000003UL /**< Mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize5 0x00000004UL /**< Mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize6 0x00000005UL /**< Mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize7 0x00000006UL /**< Mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize8 0x00000007UL /**< Mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize9 0x00000008UL /**< Mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize10 0x00000009UL /**< Mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize11 0x0000000AUL /**< Mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize12 0x0000000BUL /**< Mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize13 0x0000000CUL /**< Mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize14 0x0000000DUL /**< Mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize15 0x0000000EUL /**< Mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize16 0x0000000FUL /**< Mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DEFAULT (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_Reserved (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_Reserved << 0) /**< Shifted mode Reserved for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize2 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize2 << 0) /**< Shifted mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize3 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize3 << 0) /**< Shifted mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize4 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize4 << 0) /**< Shifted mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize5 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize5 << 0) /**< Shifted mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize6 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize6 << 0) /**< Shifted mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize7 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize7 << 0) /**< Shifted mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize8 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize8 << 0) /**< Shifted mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize9 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize9 << 0) /**< Shifted mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize10 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize10 << 0) /**< Shifted mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize11 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize11 << 0) /**< Shifted mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize12 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize12 << 0) /**< Shifted mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize13 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize13 << 0) /**< Shifted mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize14 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize14 << 0) /**< Shifted mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize15 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize15 << 0) /**< Shifted mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize16 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize16 << 0) /**< Shifted mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLFILTWINSIZE1 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_MASK 0xF0UL /**< Bit mask for ETAMPDET_CHNLFILTWINSIZE1 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_Reserved 0x00000000UL /**< Mode Reserved for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize2 0x00000001UL /**< Mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize3 0x00000002UL /**< Mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize4 0x00000003UL /**< Mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize5 0x00000004UL /**< Mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize6 0x00000005UL /**< Mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize7 0x00000006UL /**< Mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize8 0x00000007UL /**< Mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize9 0x00000008UL /**< Mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize10 0x00000009UL /**< Mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize11 0x0000000AUL /**< Mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize12 0x0000000BUL /**< Mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize13 0x0000000CUL /**< Mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize14 0x0000000DUL /**< Mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize15 0x0000000EUL /**< Mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize16 0x0000000FUL /**< Mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DEFAULT (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_Reserved (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_Reserved << 4) /**< Shifted mode Reserved for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize2 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize2 << 4) /**< Shifted mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize3 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize3 << 4) /**< Shifted mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize4 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize4 << 4) /**< Shifted mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize5 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize5 << 4) /**< Shifted mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize6 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize6 << 4) /**< Shifted mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize7 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize7 << 4) /**< Shifted mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize8 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize8 << 4) /**< Shifted mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize9 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize9 << 4) /**< Shifted mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize10 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize10 << 4) /**< Shifted mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize11 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize11 << 4) /**< Shifted mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize12 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize12 << 4) /**< Shifted mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize13 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize13 << 4) /**< Shifted mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize14 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize14 << 4) /**< Shifted mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize15 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize15 << 4) /**< Shifted mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize16 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize16 << 4) /**< Shifted mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ + +/* Bit fields for ETAMPDET CMD */ +#define _ETAMPDET_CMD_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CMD */ +#define _ETAMPDET_CMD_MASK 0x0000003FUL /**< Mask for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART0 (0x1UL << 0) /**< Start channel 0 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTART0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_CMD_CHNLSTART0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_CMD_CHNLSTART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART0_DEFAULT (_ETAMPDET_CMD_CHNLSTART0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP0 (0x1UL << 1) /**< Stop channel 0 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTOP0_SHIFT 1 /**< Shift value for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_CMD_CHNLSTOP0_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_CMD_CHNLSTOP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP0_DEFAULT (_ETAMPDET_CMD_CHNLSTOP0_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD0 (0x1UL << 2) /**< Start channel 0 tamper detection */ +#define _ETAMPDET_CMD_CHNLLOAD0_SHIFT 2 /**< Shift value for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_CMD_CHNLLOAD0_MASK 0x4UL /**< Bit mask for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_CMD_CHNLLOAD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD0_DEFAULT (_ETAMPDET_CMD_CHNLLOAD0_DEFAULT << 2) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART1 (0x1UL << 3) /**< Start channel 1 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTART1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_CMD_CHNLSTART1_MASK 0x8UL /**< Bit mask for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_CMD_CHNLSTART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART1_DEFAULT (_ETAMPDET_CMD_CHNLSTART1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP1 (0x1UL << 4) /**< Stop channel 1 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTOP1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_CMD_CHNLSTOP1_MASK 0x10UL /**< Bit mask for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_CMD_CHNLSTOP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP1_DEFAULT (_ETAMPDET_CMD_CHNLSTOP1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD1 (0x1UL << 5) /**< Start channel 1 tamper detection */ +#define _ETAMPDET_CMD_CHNLLOAD1_SHIFT 5 /**< Shift value for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_CMD_CHNLLOAD1_MASK 0x20UL /**< Bit mask for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_CMD_CHNLLOAD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD1_DEFAULT (_ETAMPDET_CMD_CHNLLOAD1_DEFAULT << 5) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ + +/* Bit fields for ETAMPDET SYNCBUSY */ +#define _ETAMPDET_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_SYNCBUSY */ +#define _ETAMPDET_SYNCBUSY_MASK 0x0000007FUL /**< Mask for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART0 (0x1UL << 0) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART0_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTART0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP0 (0x1UL << 1) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP0_SHIFT 1 /**< Shift value for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP0_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP0_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTOP0_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD0 (0x1UL << 2) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD0_SHIFT 2 /**< Shift value for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD0_MASK 0x4UL /**< Bit mask for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD0_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLLOAD0_DEFAULT << 2) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART1 (0x1UL << 3) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART1_MASK 0x8UL /**< Bit mask for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART1_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTART1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP1 (0x1UL << 4) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP1_MASK 0x10UL /**< Bit mask for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP1_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTOP1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD1 (0x1UL << 5) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD1_SHIFT 5 /**< Shift value for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD1_MASK 0x20UL /**< Bit mask for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD1_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLLOAD1_DEFAULT << 5) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_EN (0x1UL << 6) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_EN_SHIFT 6 /**< Shift value for ETAMPDET_EN */ +#define _ETAMPDET_SYNCBUSY_EN_MASK 0x40UL /**< Bit mask for ETAMPDET_EN */ +#define _ETAMPDET_SYNCBUSY_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_EN_DEFAULT (_ETAMPDET_SYNCBUSY_EN_DEFAULT << 6) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ + +/* Bit fields for ETAMPDET IEN */ +#define _ETAMPDET_IEN_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_IEN */ +#define _ETAMPDET_IEN_MASK 0x00000003UL /**< Mask for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET0 (0x1UL << 0) /**< TAMPDET0 interrupt enable */ +#define _ETAMPDET_IEN_TAMPDET0_SHIFT 0 /**< Shift value for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IEN_TAMPDET0_MASK 0x1UL /**< Bit mask for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IEN_TAMPDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET0_DEFAULT (_ETAMPDET_IEN_TAMPDET0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET1 (0x1UL << 1) /**< TAMPDET1 interrupt enable */ +#define _ETAMPDET_IEN_TAMPDET1_SHIFT 1 /**< Shift value for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IEN_TAMPDET1_MASK 0x2UL /**< Bit mask for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IEN_TAMPDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET1_DEFAULT (_ETAMPDET_IEN_TAMPDET1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_IEN */ + +/* Bit fields for ETAMPDET IF */ +#define _ETAMPDET_IF_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_IF */ +#define _ETAMPDET_IF_MASK 0x00000003UL /**< Mask for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET0 (0x1UL << 0) /**< Tamper0 Detect Flag */ +#define _ETAMPDET_IF_TAMPDET0_SHIFT 0 /**< Shift value for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IF_TAMPDET0_MASK 0x1UL /**< Bit mask for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IF_TAMPDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET0_DEFAULT (_ETAMPDET_IF_TAMPDET0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET1 (0x1UL << 1) /**< Tamper1 Detect Flag */ +#define _ETAMPDET_IF_TAMPDET1_SHIFT 1 /**< Shift value for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IF_TAMPDET1_MASK 0x2UL /**< Bit mask for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IF_TAMPDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET1_DEFAULT (_ETAMPDET_IF_TAMPDET1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_IF */ + +/* Bit fields for ETAMPDET STATUS */ +#define _ETAMPDET_STATUS_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_STATUS */ +#define _ETAMPDET_STATUS_MASK 0x80000003UL /**< Mask for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING0 (0x1UL << 0) /**< Channel0 Running Status */ +#define _ETAMPDET_STATUS_CHNLRUNNING0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLRUNNING0 */ +#define _ETAMPDET_STATUS_CHNLRUNNING0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLRUNNING0 */ +#define _ETAMPDET_STATUS_CHNLRUNNING0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING0_DEFAULT (_ETAMPDET_STATUS_CHNLRUNNING0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING1 (0x1UL << 1) /**< Channel1 Running Status */ +#define _ETAMPDET_STATUS_CHNLRUNNING1_SHIFT 1 /**< Shift value for ETAMPDET_CHNLRUNNING1 */ +#define _ETAMPDET_STATUS_CHNLRUNNING1_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLRUNNING1 */ +#define _ETAMPDET_STATUS_CHNLRUNNING1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING1_DEFAULT (_ETAMPDET_STATUS_CHNLRUNNING1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS (0x1UL << 31) /**< Lock Status */ +#define _ETAMPDET_STATUS_LOCKSTATUS_SHIFT 31 /**< Shift value for ETAMPDET_LOCKSTATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_MASK 0x80000000UL /**< Bit mask for ETAMPDET_LOCKSTATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_STATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for ETAMPDET_STATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS_DEFAULT (_ETAMPDET_STATUS_LOCKSTATUS_DEFAULT << 31) /**< Shifted mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS_UNLOCKED (_ETAMPDET_STATUS_LOCKSTATUS_UNLOCKED << 31) /**< Shifted mode UNLOCKED for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS_LOCKED (_ETAMPDET_STATUS_LOCKSTATUS_LOCKED << 31) /**< Shifted mode LOCKED for ETAMPDET_STATUS */ + +/* Bit fields for ETAMPDET EM4WUEN */ +#define _ETAMPDET_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_EM4WUEN */ +#define _ETAMPDET_EM4WUEN_MASK 0x00000003UL /**< Mask for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN0 (0x1UL << 0) /**< Channel0 Tampdet EM4 Wakeup Enable */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLEM4WUEN0 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLEM4WUEN0 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN0_DEFAULT (_ETAMPDET_EM4WUEN_CHNLEM4WUEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN1 (0x1UL << 1) /**< Channel1 Tampdet EM4 Wakeup Enable */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN1_SHIFT 1 /**< Shift value for ETAMPDET_CHNLEM4WUEN1 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN1_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLEM4WUEN1 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN1_DEFAULT (_ETAMPDET_EM4WUEN_CHNLEM4WUEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_EM4WUEN */ + +/* Bit fields for ETAMPDET CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_MASK 0xFFFFFFFFUL /**< Mask for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_MASK 0xFFFFFFFFUL /**< Bit mask for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLSEEDVAL0 */ +#define ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_DEFAULT (_ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CHNLSEEDVAL0*/ + +/* Bit fields for ETAMPDET CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_MASK 0xFFFFFFFFUL /**< Mask for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_MASK 0xFFFFFFFFUL /**< Bit mask for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLSEEDVAL1 */ +#define ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_DEFAULT (_ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CHNLSEEDVAL1*/ + +/* Bit fields for ETAMPDET CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_MASK 0x0000073FUL /**< Mask for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_SHIFT 0 /**< Shift value for ETAMPDET_LOWERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_MASK 0x3FUL /**< Bit mask for ETAMPDET_LOWERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_Bypass 0x00000000UL /**< Mode Bypass for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy2 0x00000001UL /**< Mode DivideBy2 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy3 0x00000002UL /**< Mode DivideBy3 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy4 0x00000003UL /**< Mode DivideBy4 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy5 0x00000004UL /**< Mode DivideBy5 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy6 0x00000005UL /**< Mode DivideBy6 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy7 0x00000006UL /**< Mode DivideBy7 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy8 0x00000007UL /**< Mode DivideBy8 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy9 0x00000008UL /**< Mode DivideBy9 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy10 0x00000009UL /**< Mode DivideBy10 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy11 0x0000000AUL /**< Mode DivideBy11 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy12 0x0000000BUL /**< Mode DivideBy12 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy13 0x0000000CUL /**< Mode DivideBy13 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy14 0x0000000DUL /**< Mode DivideBy14 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy15 0x0000000EUL /**< Mode DivideBy15 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy16 0x0000000FUL /**< Mode DivideBy16 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy17 0x00000010UL /**< Mode DivideBy17 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy18 0x00000011UL /**< Mode DivideBy18 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy19 0x00000012UL /**< Mode DivideBy19 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy20 0x00000013UL /**< Mode DivideBy20 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy21 0x00000014UL /**< Mode DivideBy21 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy22 0x00000015UL /**< Mode DivideBy22 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy23 0x00000016UL /**< Mode DivideBy23 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy24 0x00000017UL /**< Mode DivideBy24 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy25 0x00000018UL /**< Mode DivideBy25 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy26 0x00000019UL /**< Mode DivideBy26 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy27 0x0000001AUL /**< Mode DivideBy27 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy28 0x0000001BUL /**< Mode DivideBy28 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy29 0x0000001CUL /**< Mode DivideBy29 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy30 0x0000001DUL /**< Mode DivideBy30 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy31 0x0000001EUL /**< Mode DivideBy31 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy32 0x0000001FUL /**< Mode DivideBy32 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy33 0x00000020UL /**< Mode DivideBy33 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy34 0x00000021UL /**< Mode DivideBy34 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy35 0x00000022UL /**< Mode DivideBy35 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy36 0x00000023UL /**< Mode DivideBy36 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy37 0x00000024UL /**< Mode DivideBy37 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy38 0x00000025UL /**< Mode DivideBy38 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy39 0x00000026UL /**< Mode DivideBy39 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy40 0x00000027UL /**< Mode DivideBy40 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy41 0x00000028UL /**< Mode DivideBy41 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy42 0x00000029UL /**< Mode DivideBy42 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy43 0x0000002AUL /**< Mode DivideBy43 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy44 0x0000002BUL /**< Mode DivideBy44 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy45 0x0000002CUL /**< Mode DivideBy45 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy46 0x0000002DUL /**< Mode DivideBy46 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy47 0x0000002EUL /**< Mode DivideBy47 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy48 0x0000002FUL /**< Mode DivideBy48 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy49 0x00000030UL /**< Mode DivideBy49 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy50 0x00000031UL /**< Mode DivideBy50 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy51 0x00000032UL /**< Mode DivideBy51 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy52 0x00000033UL /**< Mode DivideBy52 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy53 0x00000034UL /**< Mode DivideBy53 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy54 0x00000035UL /**< Mode DivideBy54 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy55 0x00000036UL /**< Mode DivideBy55 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy56 0x00000037UL /**< Mode DivideBy56 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy57 0x00000038UL /**< Mode DivideBy57 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy58 0x00000039UL /**< Mode DivideBy58 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy59 0x0000003AUL /**< Mode DivideBy59 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy60 0x0000003BUL /**< Mode DivideBy60 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy61 0x0000003CUL /**< Mode DivideBy61 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy62 0x0000003DUL /**< Mode DivideBy62 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy63 0x0000003EUL /**< Mode DivideBy63 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy64 0x0000003FUL /**< Mode DivideBy64 for ETAMPDET_CLKPRESCVAL */ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DEFAULT (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_Bypass (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_Bypass << 0) /**< Shifted mode Bypass for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy2 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy2 << 0) /**< Shifted mode DivideBy2 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy3 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy3 << 0) /**< Shifted mode DivideBy3 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy4 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy4 << 0) /**< Shifted mode DivideBy4 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy5 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy5 << 0) /**< Shifted mode DivideBy5 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy6 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy6 << 0) /**< Shifted mode DivideBy6 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy7 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy7 << 0) /**< Shifted mode DivideBy7 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy8 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy8 << 0) /**< Shifted mode DivideBy8 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy9 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy9 << 0) /**< Shifted mode DivideBy9 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy10 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy10 << 0) /**< Shifted mode DivideBy10 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy11 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy11 << 0) /**< Shifted mode DivideBy11 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy12 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy12 << 0) /**< Shifted mode DivideBy12 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy13 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy13 << 0) /**< Shifted mode DivideBy13 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy14 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy14 << 0) /**< Shifted mode DivideBy14 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy15 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy15 << 0) /**< Shifted mode DivideBy15 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy16 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy16 << 0) /**< Shifted mode DivideBy16 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy17 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy17 << 0) /**< Shifted mode DivideBy17 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy18 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy18 << 0) /**< Shifted mode DivideBy18 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy19 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy19 << 0) /**< Shifted mode DivideBy19 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy20 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy20 << 0) /**< Shifted mode DivideBy20 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy21 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy21 << 0) /**< Shifted mode DivideBy21 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy22 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy22 << 0) /**< Shifted mode DivideBy22 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy23 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy23 << 0) /**< Shifted mode DivideBy23 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy24 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy24 << 0) /**< Shifted mode DivideBy24 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy25 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy25 << 0) /**< Shifted mode DivideBy25 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy26 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy26 << 0) /**< Shifted mode DivideBy26 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy27 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy27 << 0) /**< Shifted mode DivideBy27 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy28 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy28 << 0) /**< Shifted mode DivideBy28 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy29 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy29 << 0) /**< Shifted mode DivideBy29 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy30 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy30 << 0) /**< Shifted mode DivideBy30 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy31 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy31 << 0) /**< Shifted mode DivideBy31 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy32 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy32 << 0) /**< Shifted mode DivideBy32 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy33 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy33 << 0) /**< Shifted mode DivideBy33 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy34 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy34 << 0) /**< Shifted mode DivideBy34 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy35 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy35 << 0) /**< Shifted mode DivideBy35 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy36 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy36 << 0) /**< Shifted mode DivideBy36 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy37 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy37 << 0) /**< Shifted mode DivideBy37 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy38 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy38 << 0) /**< Shifted mode DivideBy38 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy39 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy39 << 0) /**< Shifted mode DivideBy39 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy40 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy40 << 0) /**< Shifted mode DivideBy40 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy41 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy41 << 0) /**< Shifted mode DivideBy41 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy42 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy42 << 0) /**< Shifted mode DivideBy42 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy43 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy43 << 0) /**< Shifted mode DivideBy43 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy44 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy44 << 0) /**< Shifted mode DivideBy44 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy45 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy45 << 0) /**< Shifted mode DivideBy45 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy46 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy46 << 0) /**< Shifted mode DivideBy46 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy47 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy47 << 0) /**< Shifted mode DivideBy47 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy48 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy48 << 0) /**< Shifted mode DivideBy48 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy49 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy49 << 0) /**< Shifted mode DivideBy49 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy50 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy50 << 0) /**< Shifted mode DivideBy50 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy51 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy51 << 0) /**< Shifted mode DivideBy51 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy52 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy52 << 0) /**< Shifted mode DivideBy52 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy53 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy53 << 0) /**< Shifted mode DivideBy53 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy54 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy54 << 0) /**< Shifted mode DivideBy54 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy55 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy55 << 0) /**< Shifted mode DivideBy55 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy56 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy56 << 0) /**< Shifted mode DivideBy56 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy57 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy57 << 0) /**< Shifted mode DivideBy57 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy58 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy58 << 0) /**< Shifted mode DivideBy58 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy59 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy59 << 0) /**< Shifted mode DivideBy59 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy60 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy60 << 0) /**< Shifted mode DivideBy60 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy61 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy61 << 0) /**< Shifted mode DivideBy61 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy62 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy62 << 0) /**< Shifted mode DivideBy62 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy63 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy63 << 0) /**< Shifted mode DivideBy63 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy64 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy64 << 0) /**< Shifted mode DivideBy64 for ETAMPDET_CLKPRESCVAL*/ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_SHIFT 8 /**< Shift value for ETAMPDET_UPPERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_MASK 0x700UL /**< Bit mask for ETAMPDET_UPPERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_Bypass 0x00000000UL /**< Mode Bypass for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy2 0x00000001UL /**< Mode DivideBy2 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy4 0x00000002UL /**< Mode DivideBy4 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy8 0x00000003UL /**< Mode DivideBy8 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy16 0x00000004UL /**< Mode DivideBy16 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy32 0x00000005UL /**< Mode DivideBy32 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy64 0x00000006UL /**< Mode DivideBy64 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_Reserved 0x00000007UL /**< Mode Reserved for ETAMPDET_CLKPRESCVAL */ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DEFAULT (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_Bypass (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_Bypass << 8) /**< Shifted mode Bypass for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy2 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy2 << 8) /**< Shifted mode DivideBy2 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy4 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy4 << 8) /**< Shifted mode DivideBy4 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy8 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy8 << 8) /**< Shifted mode DivideBy8 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy16 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy16 << 8) /**< Shifted mode DivideBy16 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy32 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy32 << 8) /**< Shifted mode DivideBy32 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy64 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy64 << 8) /**< Shifted mode DivideBy64 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_Reserved (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_Reserved << 8) /**< Shifted mode Reserved for ETAMPDET_CLKPRESCVAL*/ + +/* Bit fields for ETAMPDET LOCK */ +#define _ETAMPDET_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for ETAMPDET_LOCK */ +#define _ETAMPDET_LOCK_MASK 0x0000FFFFUL /**< Mask for ETAMPDET_LOCK */ +#define _ETAMPDET_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for ETAMPDET_LOCKKEY */ +#define _ETAMPDET_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for ETAMPDET_LOCKKEY */ +#define _ETAMPDET_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for ETAMPDET_LOCK */ +#define _ETAMPDET_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for ETAMPDET_LOCK */ +#define ETAMPDET_LOCK_LOCKKEY_DEFAULT (_ETAMPDET_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_LOCK */ +#define ETAMPDET_LOCK_LOCKKEY_UNLOCK (_ETAMPDET_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for ETAMPDET_LOCK */ + +/** @} End of group EFR32BG29_ETAMPDET_BitFields */ +/** @} End of group EFR32BG29_ETAMPDET */ +/** @} End of group Parts */ + +#endif // EFR32BG29_ETAMPDET_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_eusart.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_eusart.h new file mode 100644 index 000000000..1858d7394 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_eusart.h @@ -0,0 +1,1193 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 EUSART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_EUSART_H +#define EFR32BG29_EUSART_H +#define EUSART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_EUSART EUSART + * @{ + * @brief EFR32BG29 EUSART Register Declaration. + *****************************************************************************/ + +/** EUSART Register Declaration. */ +typedef struct eusart_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[42U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[42U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED6[42U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED9[42U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} EUSART_TypeDef; +/** @} End of group EFR32BG29_EUSART */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_EUSART + * @{ + * @defgroup EFR32BG29_EUSART_BitFields EUSART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EUSART IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ + +/* Bit fields for EUSART EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ + +/* Bit fields for EUSART CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ + +/* Bit fields for EUSART CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ + +/* Bit fields for EUSART CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Master mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ + +/* Bit fields for EUSART FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ + +/* Bit fields for EUSART DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ + +/* Bit fields for EUSART IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ + +/* Bit fields for EUSART IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ + +/* Bit fields for EUSART TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ + +/* Bit fields for EUSART STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ + +/* Bit fields for EUSART SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ + +/* Bit fields for EUSART CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ + +/* Bit fields for EUSART TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ + +/* Bit fields for EUSART CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ + +/* Bit fields for EUSART RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ + +/* Bit fields for EUSART RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ + +/* Bit fields for EUSART TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ + +/* Bit fields for EUSART STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ + +/* Bit fields for EUSART IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ + +/* Bit fields for EUSART IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete IEN */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level IEN */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level IEN */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full IEN */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow IEN */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow IEN */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow IEN */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow IEN */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error IEN */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error IEN */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame IEN */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error IEN */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail IEN */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE IEN */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up IEN */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame IEN */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame IEN */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete IEN */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout IEN */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ + +/* Bit fields for EUSART SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ + +/** @} End of group EFR32BG29_EUSART_BitFields */ +/** @} End of group EFR32BG29_EUSART */ +/** @} End of group Parts */ + +#endif // EFR32BG29_EUSART_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_fsrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_fsrco.h new file mode 100644 index 000000000..1c38e1a91 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_fsrco.h @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 FSRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_FSRCO_H +#define EFR32BG29_FSRCO_H +#define FSRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_FSRCO FSRCO + * @{ + * @brief EFR32BG29 FSRCO Register Declaration. + *****************************************************************************/ + +/** FSRCO Register Declaration. */ +typedef struct fsrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ +} FSRCO_TypeDef; +/** @} End of group EFR32BG29_FSRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_FSRCO + * @{ + * @defgroup EFR32BG29_FSRCO_BitFields FSRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FSRCO IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ + +/** @} End of group EFR32BG29_FSRCO_BitFields */ +/** @} End of group EFR32BG29_FSRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG29_FSRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpcrc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpcrc.h new file mode 100644 index 000000000..a6c3559ff --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpcrc.h @@ -0,0 +1,246 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 GPCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_GPCRC_H +#define EFR32BG29_GPCRC_H +#define GPCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_GPCRC GPCRC + * @{ + * @brief EFR32BG29 GPCRC Register Declaration. + *****************************************************************************/ + +/** GPCRC Register Declaration. */ +typedef struct gpcrc_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; +/** @} End of group EFR32BG29_GPCRC */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_GPCRC + * @{ + * @defgroup EFR32BG29_GPCRC_BitFields GPCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ + +/* Bit fields for GPCRC EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32BG29_GPCRC_BitFields */ +/** @} End of group EFR32BG29_GPCRC */ +/** @} End of group Parts */ + +#endif // EFR32BG29_GPCRC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h new file mode 100644 index 000000000..69dee19da --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio.h @@ -0,0 +1,2200 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 GPIO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_GPIO_H +#define EFR32BG29_GPIO_H +#define GPIO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +#include "efr32bg29_gpio_port.h" + +typedef struct gpio_acmproute_typedef{ + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_ACMPROUTE_TypeDef; + +typedef struct gpio_cmuroute_typedef{ + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ +} GPIO_CMUROUTE_TypeDef; + +typedef struct gpio_eusartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_EUSARTROUTE_TypeDef; + +typedef struct gpio_frcroute_typedef{ + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_FRCROUTE_TypeDef; + +typedef struct gpio_i2croute_typedef{ + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_I2CROUTE_TypeDef; + +typedef struct gpio_letimerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LETIMERROUTE_TypeDef; + +typedef struct gpio_modemroute_typedef{ + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_MODEMROUTE_TypeDef; + +typedef struct gpio_pdmroute_typedef{ + __IOM uint32_t ROUTEEN; /**< PDM pin enable */ + __IOM uint32_t CLKROUTE; /**< CLK port/pin select */ + __IOM uint32_t DAT0ROUTE; /**< DAT0 port/pin select */ + __IOM uint32_t DAT1ROUTE; /**< DAT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PDMROUTE_TypeDef; + +typedef struct gpio_prsroute_typedef{ + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PRSROUTE_TypeDef; + +typedef struct gpio_timerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_TIMERROUTE_TypeDef; + +typedef struct gpio_usartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_USARTROUTE_TypeDef; + +typedef struct gpio_typedef{ + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED4[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED9[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED10[603U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED11[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED12[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED15[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED20[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_SET; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED21[603U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED22[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED23[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED26[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED31[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_CLR; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED32[603U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED33[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED34[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED35[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED37[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED38[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED42[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_TGL; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[2U]; /**< usart0 DBUS config registers */ +} GPIO_TypeDef; + +/* Bit fields for GPIO IPVERSION */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/* Bit fields for GPIO GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ + +/* Bit fields for GPIO ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ + +/* Bit fields for GPIO BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ + +/* Bit fields for GPIO CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ + +/* Bit fields for GPIO DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ + +/* Bit fields for GPIO TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ + +/* Bit fields for GPIO_ACMP ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ + +/* Bit fields for GPIO_ACMP ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ + +/* Bit fields for GPIO_CMU ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ + +/* Bit fields for GPIO_CMU CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ + +/* Bit fields for GPIO_EUSART ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ + +/* Bit fields for GPIO_EUSART CSROUTE */ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ + +/* Bit fields for GPIO_EUSART CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ + +/* Bit fields for GPIO_EUSART RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ + +/* Bit fields for GPIO_EUSART RXROUTE */ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ + +/* Bit fields for GPIO_EUSART SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ + +/* Bit fields for GPIO_EUSART TXROUTE */ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ + +/* Bit fields for GPIO_FRC ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ + +/* Bit fields for GPIO_FRC DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ + +/* Bit fields for GPIO_FRC DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ + +/* Bit fields for GPIO_FRC DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ + +/* Bit fields for GPIO_I2C ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ + +/* Bit fields for GPIO_I2C SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ + +/* Bit fields for GPIO_I2C SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ + +/* Bit fields for GPIO_LETIMER ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ + +/* Bit fields for GPIO_LETIMER OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ + +/* Bit fields for GPIO_LETIMER OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ + +/* Bit fields for GPIO_MODEM ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ + +/* Bit fields for GPIO_MODEM DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ + +/* Bit fields for GPIO_MODEM DINROUTE */ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ + +/* Bit fields for GPIO_MODEM DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ + +/* Bit fields for GPIO_PDM ROUTEEN */ +#define _GPIO_PDM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_ROUTEEN */ +#define _GPIO_PDM_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_PDM_ROUTEEN */ +#define GPIO_PDM_ROUTEEN_CLKPEN (0x1UL << 0) /**< CLK pin enable control bit */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_SHIFT 0 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_MASK 0x1UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_ROUTEEN */ +#define GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT (_GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_ROUTEEN */ + +/* Bit fields for GPIO_PDM CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define GPIO_PDM_CLKROUTE_PORT_DEFAULT (_GPIO_PDM_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define GPIO_PDM_CLKROUTE_PIN_DEFAULT (_GPIO_PDM_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ + +/* Bit fields for GPIO_PDM DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_DAT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_DAT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define GPIO_PDM_DAT0ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_DAT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_DAT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define GPIO_PDM_DAT0ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ + +/* Bit fields for GPIO_PDM DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_DAT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_DAT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define GPIO_PDM_DAT1ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_DAT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_DAT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define GPIO_PDM_DAT1ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ + +/* Bit fields for GPIO_PRS ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ + +/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ + +/* Bit fields for GPIO_TIMER ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ + +/* Bit fields for GPIO_TIMER CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ + +/* Bit fields for GPIO_TIMER CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ + +/* Bit fields for GPIO_TIMER CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ + +/* Bit fields for GPIO_USART ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ + +/* Bit fields for GPIO_USART CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ + +/* Bit fields for GPIO_USART CTSROUTE */ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ + +/* Bit fields for GPIO_USART RTSROUTE */ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ + +/* Bit fields for GPIO_USART RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ + +/* Bit fields for GPIO_USART CLKROUTE */ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ + +/* Bit fields for GPIO_USART TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +/** @} End of group Parts */ + +#endif // EFR32BG29_GPIO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio_port.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio_port.h new file mode 100644 index 000000000..c1432a0ab --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_gpio_port.h @@ -0,0 +1,421 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 GPIO Port register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef GPIO_PORT_H +#define GPIO_PORT_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief EFR32BG29 GPIO PORT + *****************************************************************************/ +typedef struct gpio_port_typedef{ + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ +} GPIO_PORT_TypeDef; + +/* Bit fields for GPIO_P CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO_P MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ + +/* Bit fields for GPIO_P MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x0000000FUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ + +/* Bit fields for GPIO_P DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x000001FFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x1FFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO_P DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x000001FFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x1FFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +/** @} End of group Parts */ + +#endif // GPIO_PORT_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfrco.h new file mode 100644 index 000000000..2f6356e5e --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfrco.h @@ -0,0 +1,226 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 HFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_HFRCO_H +#define EFR32BG29_HFRCO_H +#define HFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_HFRCO HFRCO + * @{ + * @brief EFR32BG29 HFRCO Register Declaration. + *****************************************************************************/ + +/** HFRCO Register Declaration. */ +typedef struct hfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ +} HFRCO_TypeDef; +/** @} End of group EFR32BG29_HFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_HFRCO + * @{ + * @defgroup EFR32BG29_HFRCO_BitFields HFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFRCO IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ + +/* Bit fields for HFRCO CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ + +/* Bit fields for HFRCO CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ + +/* Bit fields for HFRCO STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ + +/* Bit fields for HFRCO IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ + +/* Bit fields for HFRCO IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ + +/* Bit fields for HFRCO LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ + +/** @} End of group EFR32BG29_HFRCO_BitFields */ +/** @} End of group EFR32BG29_HFRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG29_HFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfxo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfxo.h new file mode 100644 index 000000000..6492bc553 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_hfxo.h @@ -0,0 +1,463 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 HFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_HFXO_H +#define EFR32BG29_HFXO_H +#define HFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_HFXO HFXO + * @{ + * @brief EFR32BG29 HFXO Register Declaration. + *****************************************************************************/ + +/** HFXO Register Declaration. */ +typedef struct hfxo_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED4[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED13[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED22[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED31[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} HFXO_TypeDef; +/** @} End of group EFR32BG29_HFXO */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_HFXO + * @{ + * @defgroup EFR32BG29_HFXO_BitFields HFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFXO IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ + +/* Bit fields for HFXO XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x044334CBUL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000013UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000000UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000001UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000002UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000003UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000004UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000005UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000006UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000007UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000008UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x00000009UL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000AUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000BUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000CUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000DUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000EUL /**< Mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US 0x0000000FUL /**< Mode T7500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T7500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US << 20) /**< Shifted mode T7500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ + +/* Bit fields for HFXO XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x0F8C8C10UL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x00000010UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ + +/* Bit fields for HFXO CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xF000000DUL /**< Mask for HFXO_CFG */ +#define HFXO_CFG_MODE (0x1UL << 0) /**< Crystal Oscillator Mode */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x1UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ + +/* Bit fields for HFXO CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x80000037UL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand Mode */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ + +/* Bit fields for HFXO CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000003UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_MANUALOVERRIDE (0x1UL << 1) /**< Manual Override */ +#define _HFXO_CMD_MANUALOVERRIDE_SHIFT 1 /**< Shift value for HFXO_MANUALOVERRIDE */ +#define _HFXO_CMD_MANUALOVERRIDE_MASK 0x2UL /**< Bit mask for HFXO_MANUALOVERRIDE */ +#define _HFXO_CMD_MANUALOVERRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_MANUALOVERRIDE_DEFAULT (_HFXO_CMD_MANUALOVERRIDE_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CMD */ + +/* Bit fields for HFXO STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC00F0003UL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Hardware */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK (0x1UL << 30) /**< FSM Lock Status */ +#define _HFXO_STATUS_FSMLOCK_SHIFT 30 /**< Shift value for HFXO_FSMLOCK */ +#define _HFXO_STATUS_FSMLOCK_MASK 0x40000000UL /**< Bit mask for HFXO_FSMLOCK */ +#define _HFXO_STATUS_FSMLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_FSMLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_FSMLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_DEFAULT (_HFXO_STATUS_FSMLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_UNLOCKED (_HFXO_STATUS_FSMLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_LOCKED (_HFXO_STATUS_FSMLOCK_LOCKED << 30) /**< Shifted mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ + +/* Bit fields for HFXO IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xE0000003UL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ + +/* Bit fields for HFXO IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xE0000003UL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ + +/* Bit fields for HFXO LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ + +/** @} End of group EFR32BG29_HFXO_BitFields */ +/** @} End of group EFR32BG29_HFXO */ +/** @} End of group Parts */ + +#endif // EFR32BG29_HFXO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_i2c.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_i2c.h new file mode 100644 index 000000000..abd5d9258 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_i2c.h @@ -0,0 +1,744 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 I2C register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_I2C_H +#define EFR32BG29_I2C_H +#define I2C_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_I2C I2C + * @{ + * @brief EFR32BG29 I2C Register Declaration. + *****************************************************************************/ + +/** I2C Register Declaration. */ +typedef struct i2c_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} I2C_TypeDef; +/** @} End of group EFR32BG29_I2C */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_I2C + * @{ + * @defgroup EFR32BG29_I2C_BitFields I2C Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ + +/* Bit fields for I2C EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ + +/** @} End of group EFR32BG29_I2C_BitFields */ +/** @} End of group EFR32BG29_I2C */ +/** @} End of group Parts */ + +#endif // EFR32BG29_I2C_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h new file mode 100644 index 000000000..7f25c71ea --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_iadc.h @@ -0,0 +1,1005 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 IADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_IADC_H +#define EFR32BG29_IADC_H +#define IADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_IADC IADC + * @{ + * @brief EFR32BG29 IADC Register Declaration. + *****************************************************************************/ + +/** IADC CFG Register Group Declaration. */ +typedef struct iadc_cfg_typedef{ + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ +} IADC_CFG_TypeDef; + +/** IADC SCANTABLE Register Group Declaration. */ +typedef struct iadc_scantable_typedef{ + __IOM uint32_t SCAN; /**< SCAN Entry */ +} IADC_SCANTABLE_TypeDef; + +/** IADC Register Declaration. */ +typedef struct iadc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ +} IADC_TypeDef; +/** @} End of group EFR32BG29_IADC */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_IADC + * @{ + * @defgroup EFR32BG29_IADC_BitFields IADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for IADC IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000004UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000004UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ + +/* Bit fields for IADC EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000001UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ + +/* Bit fields for IADC CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ + +/* Bit fields for IADC CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ + +/* Bit fields for IADC TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ + +/* Bit fields for IADC STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ + +/* Bit fields for IADC MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ + +/* Bit fields for IADC STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ + +/* Bit fields for IADC CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ + +/* Bit fields for IADC IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ + +/* Bit fields for IADC IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ + +/* Bit fields for IADC TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ + +/* Bit fields for IADC CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ + +/* Bit fields for IADC SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ + +/* Bit fields for IADC SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ + +/* Bit fields for IADC SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ + +/* Bit fields for IADC SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ + +/* Bit fields for IADC SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ + +/* Bit fields for IADC SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ + +/* Bit fields for IADC SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ + +/* Bit fields for IADC SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ + +/* Bit fields for IADC SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ + +/* Bit fields for IADC SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ + +/* Bit fields for IADC SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ + +/* Bit fields for IADC SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ + +/** @} End of group EFR32BG29_IADC_BitFields */ +/** @} End of group EFR32BG29_IADC */ +/** @} End of group Parts */ + +#endif // EFR32BG29_IADC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_icache.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_icache.h new file mode 100644 index 000000000..85fefe29f --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_icache.h @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 ICACHE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_ICACHE_H +#define EFR32BG29_ICACHE_H +#define ICACHE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_ICACHE ICACHE + * @{ + * @brief EFR32BG29 ICACHE Register Declaration. + *****************************************************************************/ + +/** ICACHE Register Declaration. */ +typedef struct icache_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +} ICACHE_TypeDef; +/** @} End of group EFR32BG29_ICACHE */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_ICACHE + * @{ + * @defgroup EFR32BG29_ICACHE_BitFields ICACHE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ICACHE IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ + +/* Bit fields for ICACHE CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ + +/* Bit fields for ICACHE PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ + +/* Bit fields for ICACHE PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ + +/* Bit fields for ICACHE PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ + +/* Bit fields for ICACHE STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ + +/* Bit fields for ICACHE CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ + +/* Bit fields for ICACHE LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ + +/* Bit fields for ICACHE IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ + +/* Bit fields for ICACHE IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ + +/** @} End of group EFR32BG29_ICACHE_BitFields */ +/** @} End of group EFR32BG29_ICACHE */ +/** @} End of group Parts */ + +#endif // EFR32BG29_ICACHE_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldma.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldma.h new file mode 100644 index 000000000..877b9a364 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldma.h @@ -0,0 +1,685 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 LDMA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_LDMA_H +#define EFR32BG29_LDMA_H +#define LDMA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_LDMA LDMA + * @{ + * @brief EFR32BG29 LDMA Register Declaration. + *****************************************************************************/ + +/** LDMA CH Register Group Declaration. */ +typedef struct ldma_ch_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ +} LDMA_CH_TypeDef; + +/** LDMA Register Declaration. */ +typedef struct ldma_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; +/** @} End of group EFR32BG29_LDMA */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_LDMA + * @{ + * @defgroup EFR32BG29_LDMA_BitFields LDMA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ + +/* Bit fields for LDMA EN */ +#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ +#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ +#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ +#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ +#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ +#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ +#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ +#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ + +/* Bit fields for LDMA SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ + +/* Bit fields for LDMA SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ + +/* Bit fields for LDMA SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ + +/* Bit fields for LDMA SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHDIS */ +#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ +#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ +#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ + +/* Bit fields for LDMA CHSTATUS */ +#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ +#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32BG29_LDMA_BitFields */ +/** @} End of group EFR32BG29_LDMA */ +/** @} End of group Parts */ + +#endif // EFR32BG29_LDMA_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar.h new file mode 100644 index 000000000..b27d962d1 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 LDMAXBAR register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_LDMAXBAR_H +#define EFR32BG29_LDMAXBAR_H +#define LDMAXBAR_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_LDMAXBAR LDMAXBAR + * @{ + * @brief EFR32BG29 LDMAXBAR Register Declaration. + *****************************************************************************/ + +/** LDMAXBAR CH Register Group Declaration. */ +typedef struct ldmaxbar_ch_typedef{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +} LDMAXBAR_CH_TypeDef; + +/** LDMAXBAR Register Declaration. */ +typedef struct ldmaxbar_typedef{ + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMAXBAR_TypeDef; +/** @} End of group EFR32BG29_LDMAXBAR */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_LDMAXBAR + * @{ + * @defgroup EFR32BG29_LDMAXBAR_BitFields LDMAXBAR Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMAXBAR IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ + +/* Bit fields for LDMAXBAR CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ + +/** @} End of group EFR32BG29_LDMAXBAR_BitFields */ +/** @} End of group EFR32BG29_LDMAXBAR */ +/** @} End of group Parts */ + +#endif // EFR32BG29_LDMAXBAR_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar_defines.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar_defines.h new file mode 100644 index 000000000..005dc0d71 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ldmaxbar_defines.h @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 LDMA XBAR channel request soruce definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_LDMAXBAR_DEFINES_H +#define EFR32BG29_LDMAXBAR_DEFINES_H + +// Module source selection indices +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 0x00000005UL /**< Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000006UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000007UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000bUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000cUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000dUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000eUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_PDM 0x0000000fUL /**< Mode PDM for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x00000010UL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x00000011UL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000012UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ + +// Shifted source selection indices +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_PDM (_LDMAXBAR_CH_REQSEL_SOURCESEL_PDM << 16) /**< Shifted Mode PDM for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ + +// Module signal selection indices +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /** Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000001UL /** Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL 0x00000002UL /** Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000003UL /** Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000004UL /** Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV 0x00000000UL /** Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ + +// Shifted Module signal selection indices +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /** Shifted Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /** Shifted Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL << 0) /** Shifted Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /** Shifted Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /** Shifted Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV << 0) /** Shifted Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ + +#endif // EFR32BG29_LDMAXBAR_DEFINES_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_letimer.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_letimer.h new file mode 100644 index 000000000..363d5287c --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_letimer.h @@ -0,0 +1,496 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 LETIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_LETIMER_H +#define EFR32BG29_LETIMER_H +#define LETIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_LETIMER LETIMER + * @{ + * @brief EFR32BG29 LETIMER Register Declaration. + *****************************************************************************/ + +/** LETIMER Register Declaration. */ +typedef struct letimer_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED7[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED11[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +} LETIMER_TypeDef; +/** @} End of group EFR32BG29_LETIMER */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_LETIMER + * @{ + * @defgroup EFR32BG29_LETIMER_BitFields LETIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ + +/* Bit fields for LETIMER EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000001UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ + +/* Bit fields for LETIMER TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ + +/** @} End of group EFR32BG29_LETIMER_BitFields */ +/** @} End of group EFR32BG29_LETIMER */ +/** @} End of group Parts */ + +#endif // EFR32BG29_LETIMER_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfrco.h new file mode 100644 index 000000000..f29cad9df --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfrco.h @@ -0,0 +1,304 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 LFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_LFRCO_H +#define EFR32BG29_LFRCO_H +#define LFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_LFRCO LFRCO + * @{ + * @brief EFR32BG29 LFRCO Register Declaration. + *****************************************************************************/ + +/** LFRCO Register Declaration. */ +typedef struct lfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED3[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED7[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED11[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ +} LFRCO_TypeDef; +/** @} End of group EFR32BG29_LFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_LFRCO + * @{ + * @defgroup EFR32BG29_LFRCO_BitFields LFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFRCO IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ + +/* Bit fields for LFRCO CTRL */ +#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ +#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ +#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ + +/* Bit fields for LFRCO STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ + +/* Bit fields for LFRCO IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ +#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ +#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ +#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ +#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ +#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ +#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ + +/* Bit fields for LFRCO IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ +#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ +#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ +#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ +#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ +#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ +#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ + +/* Bit fields for LFRCO LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ + +/* Bit fields for LFRCO CFG */ +#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ +#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ +#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ + +/* Bit fields for LFRCO NOMCAL */ +#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ +#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ + +/* Bit fields for LFRCO NOMCALINV */ +#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ +#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ + +/* Bit fields for LFRCO CMD */ +#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ +#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ +#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ + +/** @} End of group EFR32BG29_LFRCO_BitFields */ +/** @} End of group EFR32BG29_LFRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG29_LFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfxo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfxo.h new file mode 100644 index 000000000..0b27a680e --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_lfxo.h @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 LFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_LFXO_H +#define EFR32BG29_LFXO_H +#define LFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_LFXO LFXO + * @{ + * @brief EFR32BG29 LFXO Register Declaration. + *****************************************************************************/ + +/** LFXO Register Declaration. */ +typedef struct lfxo_typedef{ + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFXO_TypeDef; +/** @} End of group EFR32BG29_LFXO */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_LFXO + * @{ + * @defgroup EFR32BG29_LFXO_BitFields LFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFXO IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ + +/* Bit fields for LFXO CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ + +/* Bit fields for LFXO CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ + +/* Bit fields for LFXO STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ + +/* Bit fields for LFXO CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ + +/* Bit fields for LFXO IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ + +/* Bit fields for LFXO IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ + +/* Bit fields for LFXO SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ + +/* Bit fields for LFXO LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ + +/** @} End of group EFR32BG29_LFXO_BitFields */ +/** @} End of group EFR32BG29_LFXO */ +/** @} End of group Parts */ + +#endif // EFR32BG29_LFXO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_mpahbram.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_mpahbram.h new file mode 100644 index 000000000..ca23dfe33 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_mpahbram.h @@ -0,0 +1,246 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 MPAHBRAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_MPAHBRAM_H +#define EFR32BG29_MPAHBRAM_H +#define MPAHBRAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_MPAHBRAM MPAHBRAM + * @{ + * @brief EFR32BG29 MPAHBRAM Register Declaration. + *****************************************************************************/ + +/** MPAHBRAM Register Declaration. */ +typedef struct mpahbram_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t CTRL; /**< Control register */ + __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t CTRL_SET; /**< Control register */ + __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t CTRL_CLR; /**< Control register */ + __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t CTRL_TGL; /**< Control register */ + __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} MPAHBRAM_TypeDef; +/** @} End of group EFR32BG29_MPAHBRAM */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_MPAHBRAM + * @{ + * @defgroup EFR32BG29_MPAHBRAM_BitFields MPAHBRAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MPAHBRAM IPVERSION */ +#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ + +/* Bit fields for MPAHBRAM CMD */ +#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_MASK 0x00000003UL /**< Mask for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ + +/* Bit fields for MPAHBRAM CTRL */ +#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ +#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ +#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ +#define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ + +/* Bit fields for MPAHBRAM ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ +#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ + +/* Bit fields for MPAHBRAM ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ +#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ + +/* Bit fields for MPAHBRAM ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_MASK 0x00000003UL /**< Mask for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ +#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ +#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ + +/* Bit fields for MPAHBRAM IF */ +#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_MASK 0x00000033UL /**< Mask for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ + +/* Bit fields for MPAHBRAM IEN */ +#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_MASK 0x00000033UL /**< Mask for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ + +/** @} End of group EFR32BG29_MPAHBRAM_BitFields */ +/** @} End of group EFR32BG29_MPAHBRAM */ +/** @} End of group Parts */ + +#endif // EFR32BG29_MPAHBRAM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_msc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_msc.h new file mode 100644 index 000000000..bd4e9433a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_msc.h @@ -0,0 +1,522 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 MSC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_MSC_H +#define EFR32BG29_MSC_H +#define MSC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_MSC MSC + * @{ + * @brief EFR32BG29 MSC Register Declaration. + *****************************************************************************/ + +/** MSC Register Declaration. */ +typedef struct msc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED2[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ + uint32_t RESERVED3[4U]; /**< Reserved for future use */ + uint32_t RESERVED4[4U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[12U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED14[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + uint32_t RESERVED17[4U]; /**< Reserved for future use */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + uint32_t RESERVED19[12U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[8U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED26[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ + uint32_t RESERVED27[4U]; /**< Reserved for future use */ + uint32_t RESERVED28[4U]; /**< Reserved for future use */ + uint32_t RESERVED29[4U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + uint32_t RESERVED31[12U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[8U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + uint32_t RESERVED35[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED38[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ + uint32_t RESERVED39[4U]; /**< Reserved for future use */ + uint32_t RESERVED40[4U]; /**< Reserved for future use */ + uint32_t RESERVED41[4U]; /**< Reserved for future use */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + uint32_t RESERVED43[12U]; /**< Reserved for future use */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + uint32_t RESERVED45[8U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ +} MSC_TypeDef; +/** @} End of group EFR32BG29_MSC */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_MSC + * @{ + * @defgroup EFR32BG29_MSC_BitFields MSC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ + +/* Bit fields for MSC RDATACTRL */ +#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ +#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ +#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ +#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash Power On Status */ +#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ +#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ +#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ + +/* Bit fields for MSC PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ + +/* Bit fields for MSC PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ + +/* Bit fields for MSC PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ + +/* Bit fields for MSC PAGELOCK2 */ +#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ +#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ + +/* Bit fields for MSC PAGELOCK3 */ +#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ +#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ + +/** @} End of group EFR32BG29_MSC_BitFields */ +/** @} End of group EFR32BG29_MSC */ +/** @} End of group Parts */ + +#endif // EFR32BG29_MSC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_pdm.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_pdm.h new file mode 100644 index 000000000..646255d42 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_pdm.h @@ -0,0 +1,363 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 PDM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_PDM_H +#define EFR32BG29_PDM_H +#define PDM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_PDM PDM + * @{ + * @brief EFR32BG29 PDM Register Declaration. + *****************************************************************************/ + +/** PDM Register Declaration. */ +typedef struct pdm_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< PDM Module enable Register */ + __IOM uint32_t CTRL; /**< PDM Core Control Register */ + __IOM uint32_t CMD; /**< PDM Core Command Register */ + __IM uint32_t STATUS; /**< PDM Status register */ + __IOM uint32_t CFG0; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA; /**< PDM Received Data Register */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Flag Register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED3[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_SET; /**< PDM Core Control Register */ + __IOM uint32_t CMD_SET; /**< PDM Core Command Register */ + __IM uint32_t STATUS_SET; /**< PDM Status register */ + __IOM uint32_t CFG0_SET; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_SET; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_SET; /**< PDM Received Data Register */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Flag Register */ + uint32_t RESERVED6[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED7[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_CLR; /**< PDM Core Control Register */ + __IOM uint32_t CMD_CLR; /**< PDM Core Command Register */ + __IM uint32_t STATUS_CLR; /**< PDM Status register */ + __IOM uint32_t CFG0_CLR; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_CLR; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_CLR; /**< PDM Received Data Register */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Flag Register */ + uint32_t RESERVED10[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED11[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_TGL; /**< PDM Core Control Register */ + __IOM uint32_t CMD_TGL; /**< PDM Core Command Register */ + __IM uint32_t STATUS_TGL; /**< PDM Status register */ + __IOM uint32_t CFG0_TGL; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_TGL; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_TGL; /**< PDM Received Data Register */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Flag Register */ + uint32_t RESERVED14[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} PDM_TypeDef; +/** @} End of group EFR32BG29_PDM */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_PDM + * @{ + * @defgroup EFR32BG29_PDM_BitFields PDM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PDM IPVERSION */ +#define _PDM_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for PDM_IPVERSION */ +#define _PDM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IPVERSION */ +#define PDM_IPVERSION_IPVERSION_DEFAULT (_PDM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IPVERSION */ + +/* Bit fields for PDM EN */ +#define _PDM_EN_RESETVALUE 0x00000000UL /**< Default value for PDM_EN */ +#define _PDM_EN_MASK 0x00000001UL /**< Mask for PDM_EN */ +#define PDM_EN_EN (0x1UL << 0) /**< PDM enable */ +#define _PDM_EN_EN_SHIFT 0 /**< Shift value for PDM_EN */ +#define _PDM_EN_EN_MASK 0x1UL /**< Bit mask for PDM_EN */ +#define _PDM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_EN */ +#define _PDM_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_EN */ +#define _PDM_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for PDM_EN */ +#define PDM_EN_EN_DEFAULT (_PDM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_EN */ +#define PDM_EN_EN_DISABLE (_PDM_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for PDM_EN */ +#define PDM_EN_EN_ENABLE (_PDM_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for PDM_EN */ + +/* Bit fields for PDM CTRL */ +#define _PDM_CTRL_RESETVALUE 0x00000000UL /**< Default value for PDM_CTRL */ +#define _PDM_CTRL_MASK 0x000FFF1FUL /**< Mask for PDM_CTRL */ +#define _PDM_CTRL_GAIN_SHIFT 0 /**< Shift value for PDM_GAIN */ +#define _PDM_CTRL_GAIN_MASK 0x1FUL /**< Bit mask for PDM_GAIN */ +#define _PDM_CTRL_GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ +#define PDM_CTRL_GAIN_DEFAULT (_PDM_CTRL_GAIN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CTRL */ +#define _PDM_CTRL_DSR_SHIFT 8 /**< Shift value for PDM_DSR */ +#define _PDM_CTRL_DSR_MASK 0xFFF00UL /**< Bit mask for PDM_DSR */ +#define _PDM_CTRL_DSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ +#define PDM_CTRL_DSR_DEFAULT (_PDM_CTRL_DSR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CTRL */ + +/* Bit fields for PDM CMD */ +#define _PDM_CMD_RESETVALUE 0x00000000UL /**< Default value for PDM_CMD */ +#define _PDM_CMD_MASK 0x00010111UL /**< Mask for PDM_CMD */ +#define PDM_CMD_START (0x1UL << 0) /**< Start DCF */ +#define _PDM_CMD_START_SHIFT 0 /**< Shift value for PDM_START */ +#define _PDM_CMD_START_MASK 0x1UL /**< Bit mask for PDM_START */ +#define _PDM_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_START_DEFAULT (_PDM_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_STOP (0x1UL << 4) /**< Stop DCF */ +#define _PDM_CMD_STOP_SHIFT 4 /**< Shift value for PDM_STOP */ +#define _PDM_CMD_STOP_MASK 0x10UL /**< Bit mask for PDM_STOP */ +#define _PDM_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_STOP_DEFAULT (_PDM_CMD_STOP_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_CLEAR (0x1UL << 8) /**< Clear DCF */ +#define _PDM_CMD_CLEAR_SHIFT 8 /**< Shift value for PDM_CLEAR */ +#define _PDM_CMD_CLEAR_MASK 0x100UL /**< Bit mask for PDM_CLEAR */ +#define _PDM_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_CLEAR_DEFAULT (_PDM_CMD_CLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_FIFOFL (0x1UL << 16) /**< FIFO Flush */ +#define _PDM_CMD_FIFOFL_SHIFT 16 /**< Shift value for PDM_FIFOFL */ +#define _PDM_CMD_FIFOFL_MASK 0x10000UL /**< Bit mask for PDM_FIFOFL */ +#define _PDM_CMD_FIFOFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_FIFOFL_DEFAULT (_PDM_CMD_FIFOFL_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CMD */ + +/* Bit fields for PDM STATUS */ +#define _PDM_STATUS_RESETVALUE 0x00000020UL /**< Default value for PDM_STATUS */ +#define _PDM_STATUS_MASK 0x00000731UL /**< Mask for PDM_STATUS */ +#define PDM_STATUS_ACT (0x1UL << 0) /**< PDM is active */ +#define _PDM_STATUS_ACT_SHIFT 0 /**< Shift value for PDM_ACT */ +#define _PDM_STATUS_ACT_MASK 0x1UL /**< Bit mask for PDM_ACT */ +#define _PDM_STATUS_ACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_ACT_DEFAULT (_PDM_STATUS_ACT_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FULL (0x1UL << 4) /**< FIFO FULL Status */ +#define _PDM_STATUS_FULL_SHIFT 4 /**< Shift value for PDM_FULL */ +#define _PDM_STATUS_FULL_MASK 0x10UL /**< Bit mask for PDM_FULL */ +#define _PDM_STATUS_FULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FULL_DEFAULT (_PDM_STATUS_FULL_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_EMPTY (0x1UL << 5) /**< FIFO EMPTY Status */ +#define _PDM_STATUS_EMPTY_SHIFT 5 /**< Shift value for PDM_EMPTY */ +#define _PDM_STATUS_EMPTY_MASK 0x20UL /**< Bit mask for PDM_EMPTY */ +#define _PDM_STATUS_EMPTY_DEFAULT 0x00000001UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_EMPTY_DEFAULT (_PDM_STATUS_EMPTY_DEFAULT << 5) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define _PDM_STATUS_FIFOCNT_SHIFT 8 /**< Shift value for PDM_FIFOCNT */ +#define _PDM_STATUS_FIFOCNT_MASK 0x700UL /**< Bit mask for PDM_FIFOCNT */ +#define _PDM_STATUS_FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FIFOCNT_DEFAULT (_PDM_STATUS_FIFOCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_STATUS */ + +/* Bit fields for PDM CFG0 */ +#define _PDM_CFG0_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG0 */ +#define _PDM_CFG0_MASK 0x03013713UL /**< Mask for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_SHIFT 0 /**< Shift value for PDM_FORDER */ +#define _PDM_CFG0_FORDER_MASK 0x3UL /**< Bit mask for PDM_FORDER */ +#define _PDM_CFG0_FORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_SECOND 0x00000000UL /**< Mode SECOND for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_THIRD 0x00000001UL /**< Mode THIRD for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_FOURTH 0x00000002UL /**< Mode FOURTH for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_FIFTH 0x00000003UL /**< Mode FIFTH for PDM_CFG0 */ +#define PDM_CFG0_FORDER_DEFAULT (_PDM_CFG0_FORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_FORDER_SECOND (_PDM_CFG0_FORDER_SECOND << 0) /**< Shifted mode SECOND for PDM_CFG0 */ +#define PDM_CFG0_FORDER_THIRD (_PDM_CFG0_FORDER_THIRD << 0) /**< Shifted mode THIRD for PDM_CFG0 */ +#define PDM_CFG0_FORDER_FOURTH (_PDM_CFG0_FORDER_FOURTH << 0) /**< Shifted mode FOURTH for PDM_CFG0 */ +#define PDM_CFG0_FORDER_FIFTH (_PDM_CFG0_FORDER_FIFTH << 0) /**< Shifted mode FIFTH for PDM_CFG0 */ +#define PDM_CFG0_NUMCH (0x1UL << 4) /**< Number of Channels */ +#define _PDM_CFG0_NUMCH_SHIFT 4 /**< Shift value for PDM_NUMCH */ +#define _PDM_CFG0_NUMCH_MASK 0x10UL /**< Bit mask for PDM_NUMCH */ +#define _PDM_CFG0_NUMCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_NUMCH_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ +#define _PDM_CFG0_NUMCH_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_DEFAULT (_PDM_CFG0_NUMCH_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_ONE (_PDM_CFG0_NUMCH_ONE << 4) /**< Shifted mode ONE for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_TWO (_PDM_CFG0_NUMCH_TWO << 4) /**< Shifted mode TWO for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_SHIFT 8 /**< Shift value for PDM_DATAFORMAT */ +#define _PDM_CFG0_DATAFORMAT_MASK 0x700UL /**< Bit mask for PDM_DATAFORMAT */ +#define _PDM_CFG0_DATAFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RIGHT16 0x00000000UL /**< Mode RIGHT16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_DOUBLE16 0x00000001UL /**< Mode DOUBLE16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RIGHT24 0x00000002UL /**< Mode RIGHT24 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_FULL32BIT 0x00000003UL /**< Mode FULL32BIT for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_LEFT16 0x00000004UL /**< Mode LEFT16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_LEFT24 0x00000005UL /**< Mode LEFT24 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RAW32BIT 0x00000006UL /**< Mode RAW32BIT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_DEFAULT (_PDM_CFG0_DATAFORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RIGHT16 (_PDM_CFG0_DATAFORMAT_RIGHT16 << 8) /**< Shifted mode RIGHT16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_DOUBLE16 (_PDM_CFG0_DATAFORMAT_DOUBLE16 << 8) /**< Shifted mode DOUBLE16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RIGHT24 (_PDM_CFG0_DATAFORMAT_RIGHT24 << 8) /**< Shifted mode RIGHT24 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_FULL32BIT (_PDM_CFG0_DATAFORMAT_FULL32BIT << 8) /**< Shifted mode FULL32BIT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_LEFT16 (_PDM_CFG0_DATAFORMAT_LEFT16 << 8) /**< Shifted mode LEFT16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_LEFT24 (_PDM_CFG0_DATAFORMAT_LEFT24 << 8) /**< Shifted mode LEFT24 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RAW32BIT (_PDM_CFG0_DATAFORMAT_RAW32BIT << 8) /**< Shifted mode RAW32BIT for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_SHIFT 12 /**< Shift value for PDM_FIFODVL */ +#define _PDM_CFG0_FIFODVL_MASK 0x3000UL /**< Bit mask for PDM_FIFODVL */ +#define _PDM_CFG0_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_DEFAULT (_PDM_CFG0_FIFODVL_DEFAULT << 12) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_ONE (_PDM_CFG0_FIFODVL_ONE << 12) /**< Shifted mode ONE for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_TWO (_PDM_CFG0_FIFODVL_TWO << 12) /**< Shifted mode TWO for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_THREE (_PDM_CFG0_FIFODVL_THREE << 12) /**< Shifted mode THREE for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_FOUR (_PDM_CFG0_FIFODVL_FOUR << 12) /**< Shifted mode FOUR for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01 (0x1UL << 16) /**< Stereo mode CH01 */ +#define _PDM_CFG0_STEREOMODECH01_SHIFT 16 /**< Shift value for PDM_STEREOMODECH01 */ +#define _PDM_CFG0_STEREOMODECH01_MASK 0x10000UL /**< Bit mask for PDM_STEREOMODECH01 */ +#define _PDM_CFG0_STEREOMODECH01_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_STEREOMODECH01_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */ +#define _PDM_CFG0_STEREOMODECH01_CH01ENABLE 0x00000001UL /**< Mode CH01ENABLE for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_DEFAULT (_PDM_CFG0_STEREOMODECH01_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_DISABLE (_PDM_CFG0_STEREOMODECH01_DISABLE << 16) /**< Shifted mode DISABLE for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_CH01ENABLE (_PDM_CFG0_STEREOMODECH01_CH01ENABLE << 16) /**< Shifted mode CH01ENABLE for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL (0x1UL << 24) /**< CH0 CLK Polarity */ +#define _PDM_CFG0_CH0CLKPOL_SHIFT 24 /**< Shift value for PDM_CH0CLKPOL */ +#define _PDM_CFG0_CH0CLKPOL_MASK 0x1000000UL /**< Bit mask for PDM_CH0CLKPOL */ +#define _PDM_CFG0_CH0CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_CH0CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ +#define _PDM_CFG0_CH0CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_DEFAULT (_PDM_CFG0_CH0CLKPOL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_NORMAL (_PDM_CFG0_CH0CLKPOL_NORMAL << 24) /**< Shifted mode NORMAL for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_INVERT (_PDM_CFG0_CH0CLKPOL_INVERT << 24) /**< Shifted mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL (0x1UL << 25) /**< CH1 CLK Polarity */ +#define _PDM_CFG0_CH1CLKPOL_SHIFT 25 /**< Shift value for PDM_CH1CLKPOL */ +#define _PDM_CFG0_CH1CLKPOL_MASK 0x2000000UL /**< Bit mask for PDM_CH1CLKPOL */ +#define _PDM_CFG0_CH1CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ +#define _PDM_CFG0_CH1CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_DEFAULT (_PDM_CFG0_CH1CLKPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shifted mode NORMAL for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_INVERT (_PDM_CFG0_CH1CLKPOL_INVERT << 25) /**< Shifted mode INVERT for PDM_CFG0 */ + +/* Bit fields for PDM CFG1 */ +#define _PDM_CFG1_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG1 */ +#define _PDM_CFG1_MASK 0x030003FFUL /**< Mask for PDM_CFG1 */ +#define _PDM_CFG1_PRESC_SHIFT 0 /**< Shift value for PDM_PRESC */ +#define _PDM_CFG1_PRESC_MASK 0x3FFUL /**< Bit mask for PDM_PRESC */ +#define _PDM_CFG1_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ +#define PDM_CFG1_PRESC_DEFAULT (_PDM_CFG1_PRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG1 */ +#define _PDM_CFG1_DLYMUXSEL_SHIFT 24 /**< Shift value for PDM_DLYMUXSEL */ +#define _PDM_CFG1_DLYMUXSEL_MASK 0x3000000UL /**< Bit mask for PDM_DLYMUXSEL */ +#define _PDM_CFG1_DLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ +#define PDM_CFG1_DLYMUXSEL_DEFAULT (_PDM_CFG1_DLYMUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG1 */ + +/* Bit fields for PDM RXDATA */ +#define _PDM_RXDATA_RESETVALUE 0x00000000UL /**< Default value for PDM_RXDATA */ +#define _PDM_RXDATA_MASK 0xFFFFFFFFUL /**< Mask for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_SHIFT 0 /**< Shift value for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_RXDATA */ +#define PDM_RXDATA_RXDATA_DEFAULT (_PDM_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_RXDATA */ + +/* Bit fields for PDM IF */ +#define _PDM_IF_RESETVALUE 0x00000000UL /**< Default value for PDM_IF */ +#define _PDM_IF_MASK 0x0000000FUL /**< Mask for PDM_IF */ +#define PDM_IF_DV (0x1UL << 0) /**< Data Valid Interrupt Flag */ +#define _PDM_IF_DV_SHIFT 0 /**< Shift value for PDM_DV */ +#define _PDM_IF_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ +#define _PDM_IF_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_DV_DEFAULT (_PDM_IF_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Flag */ +#define _PDM_IF_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ +#define _PDM_IF_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ +#define _PDM_IF_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_DVL_DEFAULT (_PDM_IF_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Flag */ +#define _PDM_IF_OF_SHIFT 2 /**< Shift value for PDM_OF */ +#define _PDM_IF_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ +#define _PDM_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_OF_DEFAULT (_PDM_IF_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Flag */ +#define _PDM_IF_UF_SHIFT 3 /**< Shift value for PDM_UF */ +#define _PDM_IF_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ +#define _PDM_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_UF_DEFAULT (_PDM_IF_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IF */ + +/* Bit fields for PDM IEN */ +#define _PDM_IEN_RESETVALUE 0x00000000UL /**< Default value for PDM_IEN */ +#define _PDM_IEN_MASK 0x0000000FUL /**< Mask for PDM_IEN */ +#define PDM_IEN_DV (0x1UL << 0) /**< Data Valid Interrupt Enable */ +#define _PDM_IEN_DV_SHIFT 0 /**< Shift value for PDM_DV */ +#define _PDM_IEN_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ +#define _PDM_IEN_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DV_DEFAULT (_PDM_IEN_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Enable */ +#define _PDM_IEN_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ +#define _PDM_IEN_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ +#define _PDM_IEN_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DVL_DEFAULT (_PDM_IEN_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Enable */ +#define _PDM_IEN_OF_SHIFT 2 /**< Shift value for PDM_OF */ +#define _PDM_IEN_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ +#define _PDM_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_OF_DEFAULT (_PDM_IEN_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Enable */ +#define _PDM_IEN_UF_SHIFT 3 /**< Shift value for PDM_UF */ +#define _PDM_IEN_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ +#define _PDM_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_UF_DEFAULT (_PDM_IEN_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IEN */ + +/* Bit fields for PDM SYNCBUSY */ +#define _PDM_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_MASK 0x00000009UL /**< Mask for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< sync busy */ +#define _PDM_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_SYNCBUSY_DEFAULT (_PDM_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_FIFOFLBUSY (0x1UL << 3) /**< FIFO Flush Sync busy */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_SHIFT 3 /**< Shift value for PDM_FIFOFLBUSY */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_MASK 0x8UL /**< Bit mask for PDM_FIFOFLBUSY */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT (_PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ + +/** @} End of group EFR32BG29_PDM_BitFields */ +/** @} End of group EFR32BG29_PDM */ +/** @} End of group Parts */ + +#endif // EFR32BG29_PDM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs.h new file mode 100644 index 000000000..c065fda75 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs.h @@ -0,0 +1,1471 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 PRS register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_PRS_H +#define EFR32BG29_PRS_H +#define PRS_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_PRS PRS + * @{ + * @brief EFR32BG29 PRS Register Declaration. + *****************************************************************************/ + +/** PRS ASYNC_CH Register Group Declaration. */ +typedef struct prs_async_ch_typedef{ + __IOM uint32_t CTRL; /**< Async Channel Control Register */ +} PRS_ASYNC_CH_TypeDef; + +/** PRS SYNC_CH Register Group Declaration. */ +typedef struct prs_sync_ch_typedef{ + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +} PRS_SYNC_CH_TypeDef; + +/** PRS Register Declaration. */ +typedef struct prs_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1; /**< CC1 Consumer register */ + uint32_t RESERVED2[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2; /**< CC2 Consumer register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[900U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1_SET; /**< CC1 Consumer register */ + uint32_t RESERVED10[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ_SET; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2_SET; /**< CC2 Consumer register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[900U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1_CLR; /**< CC1 Consumer register */ + uint32_t RESERVED18[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ_CLR; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2_CLR; /**< CC2 Consumer register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[900U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1_TGL; /**< CC1 Consumer register */ + uint32_t RESERVED26[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ_TGL; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2_TGL; /**< CC2 Consumer register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED28[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} PRS_TypeDef; +/** @} End of group EFR32BG29_PRS */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_PRS + * @{ + * @defgroup EFR32BG29_PRS_BitFields PRS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000008UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000008UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ + +/* Bit fields for PRS ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ + +/* Bit fields for PRS ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ + +/* Bit fields for PRS ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ + +/* Bit fields for PRS SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ + +/* Bit fields for PRS ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ + +/* Bit fields for PRS SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ + +/* Bit fields for PRS CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ + +/* Bit fields for PRS CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ + +/* Bit fields for PRS CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ + +/* Bit fields for PRS CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ + +/* Bit fields for PRS CONSUMER_PRORTC_CC0 */ +#define _PRS_CONSUMER_PRORTC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PRORTC_CC0 */ +#define _PRS_CONSUMER_PRORTC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PRORTC_CC0 */ +#define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PRORTC_CC0 */ +#define PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PRORTC_CC0*/ + +/* Bit fields for PRS CONSUMER_PRORTC_CC1 */ +#define _PRS_CONSUMER_PRORTC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PRORTC_CC1 */ +#define _PRS_CONSUMER_PRORTC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PRORTC_CC1 */ +#define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PRORTC_CC1 */ +#define PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PRORTC_CC1*/ + +/* Bit fields for PRS CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ + +/* Bit fields for PRS CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ + +/* Bit fields for PRS CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ + +/* Bit fields for PRS CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_SEQ */ +#define PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_SEQ*/ + +/* Bit fields for PRS CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC0 */ +#define PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC0*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC1 */ +#define PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC1*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC2 */ +#define PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC2*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ + +/* Bit fields for PRS CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ + +/* Bit fields for PRS CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ + +/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_CLK */ +#define PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_CLK*/ + +/* Bit fields for PRS CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_IR */ +#define PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_IR*/ + +/* Bit fields for PRS CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_RX */ +#define PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_RX*/ + +/* Bit fields for PRS CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_TRIGGER*/ +#define _PRS_CONSUMER_USART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ +#define PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ + +/** @} End of group EFR32BG29_PRS_BitFields */ +/** @} End of group EFR32BG29_PRS */ +/** @} End of group Parts */ + +#endif // EFR32BG29_PRS_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs_signals.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs_signals.h new file mode 100644 index 000000000..bb4924127 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_prs_signals.h @@ -0,0 +1,930 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 PRS register signal bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_PRS_SIGNALS_H +#define EFR32BG29_PRS_SIGNALS_H + +/** Synchronous signal sources enumeration: */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) + +/** Synchronous signal sources enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) + +/** Synchronous signals enumeration: */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) + +/** Synchronous signals enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) + +/** Synchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) + +/** Asynchronous signal sources enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000008UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (0x00000009UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x0000000aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x0000000bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET (0x0000000cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x0000000eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x0000000fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC (0x00000010UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000011UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000012UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (0x00000013UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (0x00000021UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000022UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000023UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000024UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000025UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000026UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000027UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000028UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000029UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x0000002aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x00000030UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (0x00000031UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (0x00000032UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000033UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000034UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000035UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000036UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000037UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET (0x00000038UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO (0x00000039UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x0000003aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x0000003bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x0000003cUL) + +/** Asynchronous signal sources enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET (_PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC (_PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET (_PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (_PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE << 8) + +/** Asynchronous signals enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) + +/** Asynchronous signals enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (_PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET (_PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA (_PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) + +/** Asynchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) +#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) +#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) +#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) +#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) +#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) +#define PRS_ASYNC_USART1_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS) +#define PRS_ASYNC_USART1_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX) +#define PRS_ASYNC_USART1_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS) +#define PRS_ASYNC_USART1_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA) +#define PRS_ASYNC_USART1_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX) +#define PRS_ASYNC_USART1_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC) +#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) +#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) +#define PRS_ASYNC_RTCC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0) +#define PRS_ASYNC_RTCC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1) +#define PRS_ASYNC_RTCC_CCV2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2) +#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) +#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) +#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) +#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) +#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) +#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) +#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) +#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) +#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) +#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) +#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) +#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) +#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) +#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) +#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) +#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) +#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) +#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) +#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) +#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) +#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) +#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) +#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) +#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) +#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) +#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) +#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) +#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) +#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) +#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) +#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) +#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) +#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) +#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) +#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) +#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) +#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) +#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) +#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) +#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) +#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) +#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) +#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) +#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) +#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) +#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) +#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) +#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) +#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) +#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) +#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) +#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) +#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) +#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) +#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) +#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) +#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) +#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) +#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) +#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) +#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) +#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) +#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) +#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) +#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) +#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) +#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) +#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) +#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) +#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) +#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) +#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) +#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) +#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) +#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) +#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) +#define PRS_ASYNC_PRORTC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0) +#define PRS_ASYNC_PRORTC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1) +#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) +#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) +#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) +#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) +#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) +#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) +#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) +#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) +#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) +#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) +#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) +#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) +#define PRS_ASYNC_PDML_PDMDSRPULSE (PRS_ASYNC_CH_CTRL_SOURCESEL_PDML | PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE) +#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) +#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) +#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) +#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) +#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) +#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) +#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) +#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) +#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) +#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA) +#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID) +#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_ASYNC_ETAMPDET_TAMPERSRCETAMPDET (PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET | PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET) +#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT) +#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS) +#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX) +#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS) +#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV) +#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX) +#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC) +#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL) +#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL) +#define PRS_ASYNC_DCDC_MONO70NSANA (PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC | PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA) +#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS) +#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX) +#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS) +#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV) +#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL) +#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX) +#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC) +#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL) +#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) +#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) +#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) + +/** + * Asynchronous signals and sources combined and aligned with register bit fields + * without the '_ASYNCH_' infix in order for backward compatibility: + */ +#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) +#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) +#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) +#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) +#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) +#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) +#define PRS_USART1_CS (PRS_ASYNC_USART1_CS) +#define PRS_USART1_IRTX (PRS_ASYNC_USART1_IRTX) +#define PRS_USART1_RTS (PRS_ASYNC_USART1_RTS) +#define PRS_USART1_RXDATA (PRS_ASYNC_USART1_RXDATA) +#define PRS_USART1_TX (PRS_ASYNC_USART1_TX) +#define PRS_USART1_TXC (PRS_ASYNC_USART1_TXC) +#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) +#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) +#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) +#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) +#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) +#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) +#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) +#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) +#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) +#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) +#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) +#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) +#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) +#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) +#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) +#define PRS_RTCC_CCV0 (PRS_ASYNC_RTCC_CCV0) +#define PRS_RTCC_CCV1 (PRS_ASYNC_RTCC_CCV1) +#define PRS_RTCC_CCV2 (PRS_ASYNC_RTCC_CCV2) +#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) +#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) +#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) +#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) +#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) +#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) +#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) +#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) +#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) +#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) +#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) +#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) +#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) +#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) +#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) +#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) +#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) +#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) +#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) +#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) +#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) +#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) +#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) +#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) +#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) +#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) +#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) +#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) +#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) +#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) +#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) +#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) +#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) +#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) +#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) +#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) +#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) +#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) +#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) +#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) +#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) +#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) +#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) +#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) +#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) +#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) +#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) +#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) +#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) +#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) +#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) +#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) +#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) +#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) +#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) +#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) +#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) +#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) +#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) +#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) +#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) +#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) +#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) +#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) +#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) +#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) +#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) +#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) +#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) +#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) +#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) +#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) +#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) +#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) +#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) +#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) +#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) +#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) +#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) +#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) +#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) +#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) +#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) +#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) +#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) +#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) +#define PRS_PRORTC_CCV0 (PRS_ASYNC_PRORTC_CCV0) +#define PRS_PRORTC_CCV1 (PRS_ASYNC_PRORTC_CCV1) +#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) +#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) +#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) +#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) +#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) +#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) +#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) +#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) +#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) +#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) +#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) +#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) +#define PRS_PDML_PDMDSRPULSE (PRS_ASYNC_PDML_PDMDSRPULSE) +#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) +#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) +#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) +#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) +#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) +#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) +#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) +#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) +#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) +#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA) +#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID) +#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) +#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) +#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) +#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) +#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) +#define PRS_ETAMPDET_TAMPERSRCETAMPDET (PRS_ASYNC_ETAMPDET_TAMPERSRCETAMPDET) +#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT) +#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS) +#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX) +#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS) +#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV) +#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX) +#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC) +#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL) +#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL) +#define PRS_DCDC_MONO70NSANA (PRS_ASYNC_DCDC_MONO70NSANA) +#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS) +#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX) +#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS) +#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV) +#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL) +#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX) +#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC) +#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL) +#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) +#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) +#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif // EFR32BG29_PRS_SIGNALS_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_rtcc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_rtcc.h new file mode 100644 index 000000000..bf37da4eb --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_rtcc.h @@ -0,0 +1,422 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 RTCC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_RTCC_H +#define EFR32BG29_RTCC_H +#define RTCC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_RTCC RTCC + * @{ + * @brief EFR32BG29 RTCC Register Declaration. + *****************************************************************************/ + +/** RTCC CC Register Group Declaration. */ +typedef struct rtcc_cc_typedef{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OCVALUE; /**< Output Compare Value Register */ + __IM uint32_t ICVALUE; /**< Input Capture Value Register */ +} RTCC_CC_TypeDef; + +/** RTCC Register Declaration. */ +typedef struct rtcc_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED0[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t IF_SET; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t COMBCNT_SET; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_SET[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t IF_CLR; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t COMBCNT_CLR; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_CLR[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED2[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t IF_TGL; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t COMBCNT_TGL; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_TGL[3U]; /**< Capture/Compare Channel */ +} RTCC_TypeDef; +/** @} End of group EFR32BG29_RTCC */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_RTCC + * @{ + * @defgroup EFR32BG29_RTCC_BitFields RTCC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for RTCC IPVERSION */ +#define _RTCC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for RTCC_IPVERSION */ +#define RTCC_IPVERSION_IPVERSION_DEFAULT (_RTCC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IPVERSION */ + +/* Bit fields for RTCC EN */ +#define _RTCC_EN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EN */ +#define _RTCC_EN_MASK 0x00000001UL /**< Mask for RTCC_EN */ +#define RTCC_EN_EN (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_EN_EN_SHIFT 0 /**< Shift value for RTCC_EN */ +#define _RTCC_EN_EN_MASK 0x1UL /**< Bit mask for RTCC_EN */ +#define _RTCC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EN */ +#define RTCC_EN_EN_DEFAULT (_RTCC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EN */ + +/* Bit fields for RTCC CFG */ +#define _RTCC_CFG_RESETVALUE 0x00000000UL /**< Default value for RTCC_CFG */ +#define _RTCC_CFG_MASK 0x000000FFUL /**< Mask for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _RTCC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for RTCC_CFG */ +#define _RTCC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_DEFAULT (_RTCC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_X0 (_RTCC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_X1 (_RTCC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for RTCC_CFG */ +#define RTCC_CFG_PRECNTCCV0TOP (0x1UL << 1) /**< Pre-counter CCV0 top value enable. */ +#define _RTCC_CFG_PRECNTCCV0TOP_SHIFT 1 /**< Shift value for RTCC_PRECNTCCV0TOP */ +#define _RTCC_CFG_PRECNTCCV0TOP_MASK 0x2UL /**< Bit mask for RTCC_PRECNTCCV0TOP */ +#define _RTCC_CFG_PRECNTCCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_PRECNTCCV0TOP_DEFAULT (_RTCC_CFG_PRECNTCCV0TOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTCCV1TOP (0x1UL << 2) /**< CCV1 top value enable */ +#define _RTCC_CFG_CNTCCV1TOP_SHIFT 2 /**< Shift value for RTCC_CNTCCV1TOP */ +#define _RTCC_CFG_CNTCCV1TOP_MASK 0x4UL /**< Bit mask for RTCC_CNTCCV1TOP */ +#define _RTCC_CFG_CNTCCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTCCV1TOP_DEFAULT (_RTCC_CFG_CNTCCV1TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTTICK (0x1UL << 3) /**< Counter prescaler mode. */ +#define _RTCC_CFG_CNTTICK_SHIFT 3 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CFG_CNTTICK_MASK 0x8UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CFG_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CFG */ +#define _RTCC_CFG_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_DEFAULT (_RTCC_CFG_CNTTICK_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_PRESC (_RTCC_CFG_CNTTICK_PRESC << 3) /**< Shifted mode PRESC for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_CCV0MATCH (_RTCC_CFG_CNTTICK_CCV0MATCH << 3) /**< Shifted mode CCV0MATCH for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DEFAULT (_RTCC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV1 (_RTCC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV2 (_RTCC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV4 (_RTCC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV8 (_RTCC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV16 (_RTCC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV32 (_RTCC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV64 (_RTCC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV128 (_RTCC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV256 (_RTCC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV512 (_RTCC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV1024 (_RTCC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV2048 (_RTCC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV4096 (_RTCC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV8192 (_RTCC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV16384 (_RTCC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV32768 (_RTCC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for RTCC_CFG */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000003UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_START (0x1UL << 0) /**< Start RTCC main counter */ +#define _RTCC_CMD_START_SHIFT 0 /**< Shift value for RTCC_START */ +#define _RTCC_CMD_START_MASK 0x1UL /**< Bit mask for RTCC_START */ +#define _RTCC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_START_DEFAULT (_RTCC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_STOP (0x1UL << 1) /**< Stop RTCC main counter */ +#define _RTCC_CMD_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ +#define _RTCC_CMD_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ +#define _RTCC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_STOP_DEFAULT (_RTCC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000003UL /**< Mask for RTCC_STATUS */ +#define RTCC_STATUS_RUNNING (0x1UL << 0) /**< RTCC running status */ +#define _RTCC_STATUS_RUNNING_SHIFT 0 /**< Shift value for RTCC_RUNNING */ +#define _RTCC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for RTCC_RUNNING */ +#define _RTCC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RUNNING_DEFAULT (_RTCC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_SHIFT 1 /**< Shift value for RTCC_RTCCLOCKSTATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_MASK 0x2UL /**< Bit mask for RTCC_RTCCLOCKSTATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_STATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT (_RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_LOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for RTCC_STATUS */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000003FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 1) /**< Main counter tick */ +#define _RTCC_IF_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000003FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 1) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _RTCC_SYNCBUSY_START_SHIFT 0 /**< Shift value for RTCC_START */ +#define _RTCC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for RTCC_START */ +#define _RTCC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_START_DEFAULT (_RTCC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _RTCC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ +#define _RTCC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ +#define _RTCC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_STOP_DEFAULT (_RTCC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_PRECNT_DEFAULT (_RTCC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _RTCC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for RTCC_CNT */ +#define _RTCC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for RTCC_CNT */ +#define _RTCC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CNT_DEFAULT (_RTCC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x000000FFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for RTCC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for RTCC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for RTCC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for RTCC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 4) /**< Capture compare channel comparison base. */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 4 /**< Shift value for RTCC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x10UL /**< Bit mask for RTCC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 4) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 4) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 5 /**< Shift value for RTCC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x60UL /**< Bit mask for RTCC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 5) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 5) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 5) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 5) /**< Shifted mode NONE for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_OC_SHIFT 0 /**< Shift value for RTCC_OC */ +#define _RTCC_CC_OCVALUE_OC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_OC */ +#define _RTCC_CC_OCVALUE_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_OCVALUE */ +#define RTCC_CC_OCVALUE_OC_DEFAULT (_RTCC_CC_OCVALUE_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_OCVALUE */ + +/* Bit fields for RTCC CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_IC_SHIFT 0 /**< Shift value for RTCC_IC */ +#define _RTCC_CC_ICVALUE_IC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IC */ +#define _RTCC_CC_ICVALUE_IC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_ICVALUE */ +#define RTCC_CC_ICVALUE_IC_DEFAULT (_RTCC_CC_ICVALUE_IC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_ICVALUE */ + +/** @} End of group EFR32BG29_RTCC_BitFields */ +/** @} End of group EFR32BG29_RTCC */ +/** @} End of group Parts */ + +#endif // EFR32BG29_RTCC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_semailbox.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_semailbox.h new file mode 100644 index 000000000..008ecd0b5 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_semailbox.h @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 SEMAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_SEMAILBOX_H +#define EFR32BG29_SEMAILBOX_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_SEMAILBOX_HOST SEMAILBOX_HOST + * @{ + * @brief EFR32BG29 SEMAILBOX_HOST Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_HOST Register Declaration. */ +typedef struct semailbox_host_typedef{ + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_HOST_TypeDef; +/** @} End of group EFR32BG29_SEMAILBOX_HOST */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_SEMAILBOX_HOST + * @{ + * @defgroup EFR32BG29_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ + +/* Bit fields for SEMAILBOX TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ + +/* Bit fields for SEMAILBOX RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ + +/* Bit fields for SEMAILBOX TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ + +/* Bit fields for SEMAILBOX RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ + +/* Bit fields for SEMAILBOX TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ + +/* Bit fields for SEMAILBOX RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ + +/* Bit fields for SEMAILBOX CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ + +/** @} End of group EFR32BG29_SEMAILBOX_HOST_BitFields */ +/** @} End of group EFR32BG29_SEMAILBOX_HOST */ +/**************************************************************************//** + * @defgroup EFR32BG29_SEMAILBOX_APBSE SEMAILBOX_APBSE + * @{ + * @brief EFR32BG29 SEMAILBOX_APBSE Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_APBSE Register Declaration. */ +typedef struct semailbox_apbse_typedef{ + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_APBSE_TypeDef; +/** @} End of group EFR32BG29_SEMAILBOX_APBSE */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_SEMAILBOX_APBSE + * @{ + * @defgroup EFR32BG29_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ + +/** @} End of group EFR32BG29_SEMAILBOX_APBSE_BitFields */ +/** @} End of group EFR32BG29_SEMAILBOX_APBSE */ +/** @} End of group Parts */ + +#endif // EFR32BG29_SEMAILBOX_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_smu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_smu.h new file mode 100644 index 000000000..b90220571 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_smu.h @@ -0,0 +1,1358 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 SMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_SMU_H +#define EFR32BG29_SMU_H +#define SMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_SMU SMU + * @{ + * @brief EFR32BG29 SMU Register Declaration. + *****************************************************************************/ + +/** SMU Register Declaration. */ +typedef struct smu_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t LOCK; /**< Lock */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privileged Access 1 */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1; /**< PPU Secure Access 1 */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< PPU Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR; /**< BMPU Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< ESAU Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t LOCK_SET; /**< Lock */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1_SET; /**< PPU Privileged Access 1 */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1_SET; /**< PPU Secure Access 1 */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< PPU Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< BMPU Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< ESAU Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_SET; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_SET; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1_CLR; /**< PPU Privileged Access 1 */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1_CLR; /**< PPU Secure Access 1 */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< PPU Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< BMPU Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< ESAU Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_CLR; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_CLR; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t LOCK_TGL; /**< Lock */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1_TGL; /**< PPU Privileged Access 1 */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1_TGL; /**< PPU Secure Access 1 */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< PPU Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< BMPU Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< ESAU Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_TGL; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_TGL; /**< ESAU Movable Region Boundary 5-6 */ +} SMU_TypeDef; +/** @} End of group EFR32BG29_SMU */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_SMU + * @{ + * @defgroup EFR32BG29_SMU_BitFields SMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ + +/* Bit fields for SMU STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ + +/* Bit fields for SMU LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< LOCKSVTAIRCR control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< LOCKNSVTOR control of M33 CPU */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< LOCKSMPU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< LOCKNSMPU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< LOCKSAU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFXO0_DEFAULT (_SMU_PPUPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ +#define _SMU_PPUPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART1_DEFAULT (_SMU_PPUPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ +#define _SMU_PPUPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUPATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC (0x1UL << 31) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD0_DCDC_SHIFT 31 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_MASK 0x80000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x0003FFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x0003FFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PDM (0x1UL << 0) /**< PDM Privileged Access */ +#define _SMU_PPUPATD1_PDM_SHIFT 0 /**< Shift value for SMU_PDM */ +#define _SMU_PPUPATD1_PDM_MASK 0x1UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUPATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RFSENSE (0x1UL << 1) /**< RFSENSE Privileged Access */ +#define _SMU_PPUPATD1_RFSENSE_SHIFT 1 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUPATD1_RFSENSE_MASK 0x2UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUPATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RFSENSE_DEFAULT (_SMU_PPUPATD1_RFSENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ETAMPDET (0x1UL << 2) /**< ETAMPDET Privileged Access */ +#define _SMU_PPUPATD1_ETAMPDET_SHIFT 2 /**< Shift value for SMU_ETAMPDET */ +#define _SMU_PPUPATD1_ETAMPDET_MASK 0x4UL /**< Bit mask for SMU_ETAMPDET */ +#define _SMU_PPUPATD1_ETAMPDET_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ETAMPDET_DEFAULT (_SMU_PPUPATD1_ETAMPDET_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART1 (0x1UL << 4) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD1_EUSART1_SHIFT 4 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD1_EUSART1_MASK 0x10UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART1_DEFAULT (_SMU_PPUPATD1_EUSART1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 5) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 5 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x20UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 6) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 6 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x40UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 7) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 7 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x80UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 8) /**< RTCC Privileged Access */ +#define _SMU_PPUPATD1_RTCC_SHIFT 8 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x100UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 9) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 9 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x200UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 10) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 10 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x400UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 11) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 11 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x800UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 12) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 12 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x1000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 13) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 13 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x2000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 14) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 14 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x4000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0 (0x1UL << 15) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD1_EUSART0_SHIFT 15 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_MASK 0x8000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 16) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 16 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x10000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 17) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 17 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x20000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFXO0_DEFAULT (_SMU_PPUSATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 5) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 7) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 8) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 10) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 12) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 13) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 14) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 21) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART1 (0x1UL << 22) /**< USART1 Secure Access */ +#define _SMU_PPUSATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUSATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUSATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART1_DEFAULT (_SMU_PPUSATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 23) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 24) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Secure Access */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 28) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Secure Access */ +#define _SMU_PPUSATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUSATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUSATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_IFADCDEBUG_DEFAULT (_SMU_PPUSATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 30) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC (0x1UL << 31) /**< DCDC Secure Access */ +#define _SMU_PPUSATD0_DCDC_SHIFT 31 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_MASK 0x80000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ + +/* Bit fields for SMU PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x0003FFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x0003FFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PDM (0x1UL << 0) /**< PDM Secure Access */ +#define _SMU_PPUSATD1_PDM_SHIFT 0 /**< Shift value for SMU_PDM */ +#define _SMU_PPUSATD1_PDM_MASK 0x1UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUSATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PDM_DEFAULT (_SMU_PPUSATD1_PDM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RFSENSE (0x1UL << 1) /**< RFSENSE Secure Access */ +#define _SMU_PPUSATD1_RFSENSE_SHIFT 1 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUSATD1_RFSENSE_MASK 0x2UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUSATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RFSENSE_DEFAULT (_SMU_PPUSATD1_RFSENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ETAMPDET (0x1UL << 2) /**< ETAMPDET Secure Access */ +#define _SMU_PPUSATD1_ETAMPDET_SHIFT 2 /**< Shift value for SMU_ETAMPDET */ +#define _SMU_PPUSATD1_ETAMPDET_MASK 0x4UL /**< Bit mask for SMU_ETAMPDET */ +#define _SMU_PPUSATD1_ETAMPDET_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ETAMPDET_DEFAULT (_SMU_PPUSATD1_ETAMPDET_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM (0x1UL << 3) /**< DMEM Secure Access */ +#define _SMU_PPUSATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART1 (0x1UL << 4) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD1_EUSART1_SHIFT 4 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD1_EUSART1_MASK 0x10UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART1_DEFAULT (_SMU_PPUSATD1_EUSART1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 5) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 5 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x20UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 6) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 6 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x40UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 7) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 7 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x80UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RTCC (0x1UL << 8) /**< RTCC Secure Access */ +#define _SMU_PPUSATD1_RTCC_SHIFT 8 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUSATD1_RTCC_MASK 0x100UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUSATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RTCC_DEFAULT (_SMU_PPUSATD1_RTCC_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 9) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 9 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x200UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 10) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 10 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x400UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 11) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 11 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x800UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 12) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 12 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x1000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 13) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 13 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x2000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 14) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 14 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x4000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0 (0x1UL << 15) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD1_EUSART0_SHIFT 15 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_MASK 0x8000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 16) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 16 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x10000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 17) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 17 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x20000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ + +/* Bit fields for SMU BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOIFADCDEBUG (0x1UL << 2) /**< RADIOIFADCDEBUG Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_SHIFT 2 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_MASK 0x4UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 3) /**< LDMA Privileged Mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 3 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x8UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 4) /**< SEEXTDMA Privileged Mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 4 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x10UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ + +/* Bit fields for SMU BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Secure Mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Secure Mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOIFADCDEBUG (0x1UL << 2) /**< RADIOIFADCDEBUG Secure Mode */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_SHIFT 2 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_MASK 0x4UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 3) /**< LDMA Secure Mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 3 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x8UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 4) /**< SEEXTDMA Secure Mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 4 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x10UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ + +/* Bit fields for SMU BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ + +/* Bit fields for SMU BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ + +/* Bit fields for SMU ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ + +/* Bit fields for SMU ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ + +/* Bit fields for SMU ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ + +/* Bit fields for SMU ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ + +/* Bit fields for SMU ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ + +/* Bit fields for SMU ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ + +/** @} End of group EFR32BG29_SMU_BitFields */ +/** @} End of group EFR32BG29_SMU */ +/**************************************************************************//** + * @defgroup EFR32BG29_SMU_CFGNS SMU_CFGNS + * @{ + * @brief EFR32BG29 SMU_CFGNS Register Declaration. + *****************************************************************************/ + +/** SMU_CFGNS Register Declaration. */ +typedef struct smu_cfgns_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK; /**< Non-Secure Lock */ + __IOM uint32_t NSIF; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_SET; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_SET; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_SET; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1_SET; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_CLR; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_CLR; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_CLR; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1_CLR; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_TGL; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_TGL; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_TGL; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1_TGL; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ +} SMU_CFGNS_TypeDef; +/** @} End of group EFR32BG29_SMU_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_SMU_CFGNS + * @{ + * @defgroup EFR32BG29_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock Status */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ + +/* Bit fields for SMU NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ + +/* Bit fields for SMU NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ + +/* Bit fields for SMU NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ + +/* Bit fields for SMU PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFXO0_DEFAULT (_SMU_PPUNSPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ +#define _SMU_PPUNSPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUNSPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUNSPATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART1_DEFAULT (_SMU_PPUNSPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC (0x1UL << 31) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD0_DCDC_SHIFT 31 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_MASK 0x80000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ + +/* Bit fields for SMU PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x0003FFFFUL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x0003FFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PDM (0x1UL << 0) /**< PDM Privileged Access */ +#define _SMU_PPUNSPATD1_PDM_SHIFT 0 /**< Shift value for SMU_PDM */ +#define _SMU_PPUNSPATD1_PDM_MASK 0x1UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUNSPATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PDM_DEFAULT (_SMU_PPUNSPATD1_PDM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RFSENSE (0x1UL << 1) /**< RFSENSE Privileged Access */ +#define _SMU_PPUNSPATD1_RFSENSE_SHIFT 1 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUNSPATD1_RFSENSE_MASK 0x2UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUNSPATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RFSENSE_DEFAULT (_SMU_PPUNSPATD1_RFSENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ETAMPDET (0x1UL << 2) /**< ETAMPDET Privileged Access */ +#define _SMU_PPUNSPATD1_ETAMPDET_SHIFT 2 /**< Shift value for SMU_ETAMPDET */ +#define _SMU_PPUNSPATD1_ETAMPDET_MASK 0x4UL /**< Bit mask for SMU_ETAMPDET */ +#define _SMU_PPUNSPATD1_ETAMPDET_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ETAMPDET_DEFAULT (_SMU_PPUNSPATD1_ETAMPDET_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUNSPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART1 (0x1UL << 4) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART1_SHIFT 4 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD1_EUSART1_MASK 0x10UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART1_DEFAULT (_SMU_PPUNSPATD1_EUSART1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 5) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 5 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x20UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 6) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 6 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x40UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 7) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 7 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x80UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RTCC (0x1UL << 8) /**< RTCC Privileged Access */ +#define _SMU_PPUNSPATD1_RTCC_SHIFT 8 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUNSPATD1_RTCC_MASK 0x100UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUNSPATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RTCC_DEFAULT (_SMU_PPUNSPATD1_RTCC_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 9) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 9 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x200UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 10) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 10 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x400UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 11) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 11 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x800UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 12) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 12 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x1000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 13) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 13 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x2000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 14) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 14 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x4000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 15) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART0_SHIFT 15 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_MASK 0x8000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 16) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 16 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x10000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 17) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 17 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x20000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ + +/* Bit fields for SMU PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ + +/* Bit fields for SMU BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG (0x1UL << 2) /**< RADIOIFADCDEBUG Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_SHIFT 2 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_MASK 0x4UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 3) /**< LDMA Privileged Mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 3 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x8UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 4) /**< SEEXTDMA Privileged Mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 4 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x10UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ + +/** @} End of group EFR32BG29_SMU_CFGNS_BitFields */ +/** @} End of group EFR32BG29_SMU_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32BG29_SMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_syscfg.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_syscfg.h new file mode 100644 index 000000000..8014c4093 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_syscfg.h @@ -0,0 +1,739 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 SYSCFG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_SYSCFG_H +#define EFR32BG29_SYSCFG_H +#define SYSCFG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_SYSCFG SYSCFG + * @{ + * @brief EFR32BG29 SYSCFG Register Declaration. + *****************************************************************************/ + +/** SYSCFG Register Declaration. */ +typedef struct syscfg_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV; /**< Chip Revision */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ + uint32_t RESERVED2[55U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ + uint32_t RESERVED6[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ + uint32_t RESERVED7[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */ + uint32_t RESERVED10[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[635U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_SET; /**< Chip Revision */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ + uint32_t RESERVED15[55U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ + uint32_t RESERVED19[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ + uint32_t RESERVED20[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */ + uint32_t RESERVED23[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[635U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_CLR; /**< Chip Revision */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ + uint32_t RESERVED32[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ + uint32_t RESERVED33[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */ + uint32_t RESERVED36[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + uint32_t RESERVED38[635U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_TGL; /**< Chip Revision */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ + uint32_t RESERVED41[55U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + uint32_t RESERVED43[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ + uint32_t RESERVED45[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ + uint32_t RESERVED46[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED47[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */ + uint32_t RESERVED49[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ +} SYSCFG_TypeDef; +/** @} End of group EFR32BG29_SYSCFG */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_SYSCFG + * @{ + * @defgroup EFR32BG29_SYSCFG_BitFields SYSCFG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG IPVERSION */ +#define _SYSCFG_IPVERSION_RESETVALUE 0x0000000BUL /**< Default value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x0000000BUL /**< Mode DEFAULT for SYSCFG_IPVERSION */ +#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ + +/* Bit fields for SYSCFG IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x33003F0FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ +#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ +#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ +#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ +#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ +#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ +#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-Bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-Bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-Bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-Bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ + +/* Bit fields for SYSCFG IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x33003F0FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ +#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ +#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ +#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ +#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ +#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ +#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ + +/* Bit fields for SYSCFG CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00010014UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT 0x00000014UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ + +/* Bit fields for SYSCFG CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREV_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREV_PARTNUMBER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREV_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ + +/* Bit fields for SYSCFG CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ + +/* Bit fields for SYSCFG CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ + +/* Bit fields for SYSCFG DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0xFFFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00008000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x0000C000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x0000E000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x0000F000UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x0000F800UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x0000FC00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x0000FE00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x0000FF00UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x0000FF80UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x0000FFC0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x0000FFE0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x0000FFF0UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x0000FFF8UL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x0000FFFCUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x0000FFFEUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF 0x0000FFFFUL /**< Mode ALLOFF for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_DMEM0RETNCTRL*/ + +/* Bit fields for SYSCFG RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ + +/* Bit fields for SYSCFG RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ + +/* Bit fields for SYSCFG RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ + +/* Bit fields for SYSCFG SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ + +/* Bit fields for SYSCFG FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ + +/* Bit fields for SYSCFG ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ + +/* Bit fields for SYSCFG DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00000055UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x000000FFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_SHIFT 6 /**< Shift value for SYSCFG_IFADCDEBUGPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_IFADCDEBUGPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ + +/* Bit fields for SYSCFG ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ + +/* Bit fields for SYSCFG ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ + +/* Bit fields for SYSCFG ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0117UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK (0x1UL << 4) /**< Root Mode Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_SHIFT 4 /**< Shift value for SYSCFG_ROOTMODELOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_MASK 0x10UL /**< Bit mask for SYSCFG_ROOTMODELOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 16) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 17) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 18) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 19) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 20) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ + +/* Bit fields for SYSCFG ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ +#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ + +/** @} End of group EFR32BG29_SYSCFG_BitFields */ +/** @} End of group EFR32BG29_SYSCFG */ +/**************************************************************************//** + * @defgroup EFR32BG29_SYSCFG_CFGNS SYSCFG_CFGNS + * @{ + * @brief EFR32BG29 SYSCFG_CFGNS Register Declaration. + *****************************************************************************/ + +/** SYSCFG_CFGNS Register Declaration. */ +typedef struct syscfg_cfgns_typedef{ + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED1[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[637U]; /**< Reserved for future use */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED5[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[637U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED9[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[637U]; /**< Reserved for future use */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED13[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} SYSCFG_CFGNS_TypeDef; +/** @} End of group EFR32BG29_SYSCFG_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_SYSCFG_CFGNS + * @{ + * @defgroup EFR32BG29_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ +#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ +#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ + +/* Bit fields for SYSCFG ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ +#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ + +/* Bit fields for SYSCFG ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ +#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ + +/** @} End of group EFR32BG29_SYSCFG_CFGNS_BitFields */ +/** @} End of group EFR32BG29_SYSCFG_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32BG29_SYSCFG_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_timer.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_timer.h new file mode 100644 index 000000000..93a979d7a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_timer.h @@ -0,0 +1,1015 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 TIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_TIMER_H +#define EFR32BG29_TIMER_H +#define TIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_TIMER TIMER + * @{ + * @brief EFR32BG29 TIMER Register Declaration. + *****************************************************************************/ + +/** TIMER CC Register Group Declaration. */ +typedef struct timer_cc_typedef{ + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} TIMER_CC_TypeDef; + +/** TIMER Register Declaration. */ +typedef struct timer_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; +/** @} End of group EFR32BG29_TIMER */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_TIMER + * @{ + * @defgroup EFR32BG29_TIMER_BitFields TIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ + +/* Bit fields for TIMER CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000001UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ + +/* Bit fields for TIMER CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ + +/* Bit fields for TIMER CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ + +/* Bit fields for TIMER CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ + +/* Bit fields for TIMER CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ + +/* Bit fields for TIMER DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ + +/* Bit fields for TIMER DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ + +/* Bit fields for TIMER DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32BG29_TIMER_BitFields */ +/** @} End of group EFR32BG29_TIMER */ +/** @} End of group Parts */ + +#endif // EFR32BG29_TIMER_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ulfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ulfrco.h new file mode 100644 index 000000000..55207fca9 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_ulfrco.h @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 ULFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_ULFRCO_H +#define EFR32BG29_ULFRCO_H +#define ULFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_ULFRCO ULFRCO + * @{ + * @brief EFR32BG29 ULFRCO Register Declaration. + *****************************************************************************/ + +/** ULFRCO Register Declaration. */ +typedef struct ulfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} ULFRCO_TypeDef; +/** @} End of group EFR32BG29_ULFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_ULFRCO + * @{ + * @defgroup EFR32BG29_ULFRCO_BitFields ULFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ULFRCO IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ + +/* Bit fields for ULFRCO STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ + +/* Bit fields for ULFRCO IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ + +/* Bit fields for ULFRCO IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ + +/** @} End of group EFR32BG29_ULFRCO_BitFields */ +/** @} End of group EFR32BG29_ULFRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG29_ULFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_usart.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_usart.h new file mode 100644 index 000000000..7d7601bf7 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_usart.h @@ -0,0 +1,1431 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 USART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_USART_H +#define EFR32BG29_USART_H +#define USART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_USART USART + * @{ + * @brief EFR32BG29 USART Register Declaration. + *****************************************************************************/ + +/** USART Register Declaration. */ +typedef struct usart_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +} USART_TypeDef; +/** @} End of group EFR32BG29_USART */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_USART + * @{ + * @defgroup EFR32BG29_USART_BitFields USART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for USART IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ + +/* Bit fields for USART EN */ +#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ +#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ +#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ +#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ +#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ + +/** @} End of group EFR32BG29_USART_BitFields */ +/** @} End of group EFR32BG29_USART */ +/** @} End of group Parts */ + +#endif // EFR32BG29_USART_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_wdog.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_wdog.h new file mode 100644 index 000000000..fd3d20877 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29_wdog.h @@ -0,0 +1,361 @@ +/**************************************************************************//** + * @file + * @brief EFR32BG29 WDOG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29_WDOG_H +#define EFR32BG29_WDOG_H +#define WDOG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG29_WDOG WDOG + * @{ + * @brief EFR32BG29 WDOG Register Declaration. + *****************************************************************************/ + +/** WDOG Register Declaration. */ +typedef struct wdog_typedef{ + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} WDOG_TypeDef; +/** @} End of group EFR32BG29_WDOG */ + +/**************************************************************************//** + * @addtogroup EFR32BG29_WDOG + * @{ + * @defgroup EFR32BG29_WDOG_BitFields WDOG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ + +/* Bit fields for WDOG EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000001UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ + +/* Bit fields for WDOG CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F071FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 1) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 1 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x2UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 2) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 2 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x4UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 3) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 3 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x8UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 4) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 4 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x10UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/* Bit fields for WDOG LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/** @} End of group EFR32BG29_WDOG_BitFields */ +/** @} End of group EFR32BG29_WDOG */ +/** @} End of group Parts */ + +#endif // EFR32BG29_WDOG_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b140f1024im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b140f1024im40.h new file mode 100644 index 000000000..ea8aaaac3 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b140f1024im40.h @@ -0,0 +1,1471 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32BG29B140F1024IM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29B140F1024IM40_H +#define EFR32BG29B140F1024IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32BG29B140F1024IM40 EFR32BG29B140F1024IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32BG29 Peripheral Interrupt Numbers ******************************************/ + + SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ + SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ + EMUEFP_IRQn = 7, /*!< 7 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 8, /*!< 8 EFR32 DCDC Interrupt */ + ETAMPDET_IRQn = 9, /*!< 9 EFR32 ETAMPDET Interrupt */ + TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 11, /*!< 11 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 12, /*!< 12 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 13, /*!< 13 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 14, /*!< 14 EFR32 TIMER4 Interrupt */ + RTCC_IRQn = 15, /*!< 15 EFR32 RTCC Interrupt */ + USART0_RX_IRQn = 16, /*!< 16 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 17, /*!< 17 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 18, /*!< 18 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 19, /*!< 19 EFR32 USART1_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + ICACHE0_IRQn = 22, /*!< 22 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 23, /*!< 23 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 24, /*!< 24 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 25, /*!< 25 EFR32 SYSCFG Interrupt */ + LDMA_IRQn = 26, /*!< 26 EFR32 LDMA Interrupt */ + LFXO_IRQn = 27, /*!< 27 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 28, /*!< 28 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 29, /*!< 29 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 30, /*!< 30 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 31, /*!< 31 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 32, /*!< 32 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 33, /*!< 33 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 34, /*!< 34 EFR32 EMUDG Interrupt */ + EMUSE_IRQn = 35, /*!< 35 EFR32 EMUSE Interrupt */ + AGC_IRQn = 36, /*!< 36 EFR32 AGC Interrupt */ + BUFC_IRQn = 37, /*!< 37 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 38, /*!< 38 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 39, /*!< 39 EFR32 FRC Interrupt */ + MODEM_IRQn = 40, /*!< 40 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 41, /*!< 41 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 42, /*!< 42 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 43, /*!< 43 EFR32 RAC_SEQ Interrupt */ + RDMAILBOX_IRQn = 44, /*!< 44 EFR32 RDMAILBOX Interrupt */ + RFSENSE_IRQn = 45, /*!< 45 EFR32 RFSENSE Interrupt */ + SYNTH_IRQn = 46, /*!< 46 EFR32 SYNTH Interrupt */ + PRORTC_IRQn = 47, /*!< 47 EFR32 PRORTC Interrupt */ + ACMP0_IRQn = 48, /*!< 48 EFR32 ACMP0 Interrupt */ + WDOG0_IRQn = 49, /*!< 49 EFR32 WDOG0 Interrupt */ + HFXO0_IRQn = 50, /*!< 50 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 51, /*!< 51 EFR32 HFRCO0 Interrupt */ + CMU_IRQn = 52, /*!< 52 EFR32 CMU Interrupt */ + AES_IRQn = 53, /*!< 53 EFR32 AES Interrupt */ + IADC_IRQn = 54, /*!< 54 EFR32 IADC Interrupt */ + MSC_IRQn = 55, /*!< 55 EFR32 MSC Interrupt */ + DPLL0_IRQn = 56, /*!< 56 EFR32 DPLL0 Interrupt */ + PDM_IRQn = 57, /*!< 57 EFR32 PDM Interrupt */ + SW0_IRQn = 58, /*!< 58 EFR32 SW0 Interrupt */ + SW1_IRQn = 59, /*!< 59 EFR32 SW1 Interrupt */ + SW2_IRQn = 60, /*!< 60 EFR32 SW2 Interrupt */ + SW3_IRQn = 61, /*!< 61 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 62, /*!< 62 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 63, /*!< 63 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 64, /*!< 64 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 65, /*!< 65 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 66, /*!< 66 EFR32 FPUEXH Interrupt */ + MPAHBRAM_IRQn = 67, /*!< 67 EFR32 MPAHBRAM Interrupt */ + EUSART1_RX_IRQn = 68, /*!< 68 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 69, /*!< 69 EFR32 EUSART1_TX Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32BG29B140F1024IM40_Core EFR32BG29B140F1024IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32BG29B140F1024IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32BG29B140F1024IM40_Part EFR32BG29B140F1024IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32BG29B140F1024IM40) +#define EFR32BG29B140F1024IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32BG29B140F1024IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_9 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 9 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 8 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x080FFFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x080FFFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32BG29B140F1024IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define ETAMPDET_ETAMPIN0_PORT GPIO_PB_INDEX /**< Port of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN0_PIN 1U /**< Pin of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN1_PORT GPIO_PC_INDEX /**< Port of ETAMPIN1.*/ +#define ETAMPDET_ETAMPIN1_PIN 0U /**< Pin of ETAMPIN1.*/ +#define ETAMPDET_ETAMPOUT0_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT0_PIN 1U /**< Pin of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT1_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT1.*/ +#define ETAMPDET_ETAMPOUT1_PIN 2U /**< Pin of ETAMPOUT1.*/ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 0U /**< Pin of THMSW_HALFSWITCH.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 1 /** 1 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define ETAMPDET_PRESENT /** ETAMPDET is available in this part */ +#define ETAMPDET_COUNT 1 /** 1 ETAMPDETs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PDM_PRESENT /** PDM is available in this part */ +#define PDM_COUNT 1 /** 1 PDMs available */ +#define PRORTC_PRESENT /** PRORTC is available in this part */ +#define PRORTC_COUNT 1 /** 1 PRORTCs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define RTCC_PRESENT /** RTCC is available in this part */ +#define RTCC_COUNT 1 /** 1 RTCCs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 2 /** 2 USARTs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 1 /** 1 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32bg29.h" /* System Header File */ + +/** @} End of group EFR32BG29B140F1024IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32BG29B140F1024IM40_Peripheral_TypeDefs EFR32BG29B140F1024IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32bg29_emu.h" +#include "efr32bg29_cmu.h" +#include "efr32bg29_hfxo.h" +#include "efr32bg29_hfrco.h" +#include "efr32bg29_fsrco.h" +#include "efr32bg29_dpll.h" +#include "efr32bg29_lfxo.h" +#include "efr32bg29_lfrco.h" +#include "efr32bg29_ulfrco.h" +#include "efr32bg29_msc.h" +#include "efr32bg29_icache.h" +#include "efr32bg29_prs.h" +#include "efr32bg29_gpio.h" +#include "efr32bg29_ldma.h" +#include "efr32bg29_ldmaxbar.h" +#include "efr32bg29_timer.h" +#include "efr32bg29_usart.h" +#include "efr32bg29_burtc.h" +#include "efr32bg29_i2c.h" +#include "efr32bg29_syscfg.h" +#include "efr32bg29_buram.h" +#include "efr32bg29_gpcrc.h" +#include "efr32bg29_dcdc.h" +#include "efr32bg29_pdm.h" +#include "efr32bg29_etampdet.h" +#include "efr32bg29_mpahbram.h" +#include "efr32bg29_eusart.h" +#include "efr32bg29_aes.h" +#include "efr32bg29_smu.h" +#include "efr32bg29_rtcc.h" +#include "efr32bg29_wdog.h" +#include "efr32bg29_letimer.h" +#include "efr32bg29_iadc.h" +#include "efr32bg29_acmp.h" +#include "efr32bg29_semailbox.h" +#include "efr32bg29_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32bg29_prs_signals.h" +#include "efr32bg29_dma_descriptor.h" +#include "efr32bg29_ldmaxbar_defines.h" + +/** @} End of group EFR32BG29B140F1024IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32BG29B140F1024IM40_Peripheral_Base EFR32BG29B140F1024IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ +#define ETAMPDET_S_BASE (0x400A4000UL) /* ETAMPDET_S base address */ +#define DMEM_S_BASE (0x400B0000UL) /* DMEM_S base address */ +#define EUSART1_S_BASE (0x400B4000UL) /* EUSART1_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ +#define WDOG0_S_BASE (0x48018000UL) /* WDOG0_S base address */ +#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ +#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ +#define EUSART0_S_BASE (0x4A040000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ +#define ETAMPDET_NS_BASE (0x500A4000UL) /* ETAMPDET_NS base address */ +#define DMEM_NS_BASE (0x500B0000UL) /* DMEM_NS base address */ +#define EUSART1_NS_BASE (0x500B4000UL) /* EUSART1_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ +#define WDOG0_NS_BASE (0x58018000UL) /* WDOG0_NS base address */ +#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ +#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ +#define EUSART0_NS_BASE (0x5A040000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) +#define PDM_BASE (PDM_S_BASE) /* PDM base address */ +#else +#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) +#define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ +#else +#define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) +#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ +#else +#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) +#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ +#else +#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32BG29B140F1024IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32BG29B140F1024IM40_Peripheral_Declaration EFR32BG29B140F1024IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ +#define ETAMPDET_S ((ETAMPDET_TypeDef *) ETAMPDET_S_BASE) /**< ETAMPDET_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ +#define ETAMPDET_NS ((ETAMPDET_TypeDef *) ETAMPDET_NS_BASE) /**< ETAMPDET_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ +#define ETAMPDET ((ETAMPDET_TypeDef *) ETAMPDET_BASE) /**< ETAMPDET base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32BG29B140F1024IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32BG29B140F1024IM40_Peripheral_Parameters EFR32BG29B140F1024IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x90UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define HFRCO0_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x100000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x1UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x5UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x0UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x4UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_PARTNUMBER 0x4UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_RAM0_INST_COUNT 0x10UL /**> None */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define PDM_FIFO_LEN 0x4UL /**> New Param */ +#define PDM_NUM_CH 0x2UL /**> None */ +#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ +#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ +#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ +#define PDM_PIPELINE 0x0UL /**> None */ +#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ +#define ETAMPDET_NUM_CHNLS 0x2UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_EXCLUDE_DALI 0x0UL /**> Exclude DALI */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x32UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x12UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x12UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define RTCC_CC_NUM 0x3UL /**> None */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x0UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x0UL /**> None */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_EXCLUDE_DALI 0x1UL /**> Exclude DALI */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ +#define PRORTC_CC_NUM 0x2UL /**> None */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_EXCLUDE_DALI(n) (((n) == 0) ? EUSART0_EXCLUDE_DALI \ + : ((n) == 1) ? EUSART1_EXCLUDE_DALI \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for IADC */ +#define IADC(n) (((n) == 0) ? IADC0 \ + : 0x0UL) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 \ + : -1) +#define IADC_CONFIGNUM(n) (((n) == 0) ? IADC0_CONFIGNUM \ + : 0x0UL) +#define IADC_FULLRANGEUNIPOLAR(n) (((n) == 0) ? IADC0_FULLRANGEUNIPOLAR \ + : 0x0UL) +#define IADC_SCANBYTES(n) (((n) == 0) ? IADC0_SCANBYTES \ + : 0x0UL) +#define IADC_ENTRIES(n) (((n) == 0) ? IADC0_ENTRIES \ + : 0x0UL) + +/* Instance macros for LETIMER */ +#define LETIMER(n) (((n) == 0) ? LETIMER0 \ + : 0x0UL) +#define LETIMER_NUM(ref) (((ref) == LETIMER0) ? 0 \ + : -1) +#define LETIMER_CNT_WIDTH(n) (((n) == 0) ? LETIMER0_CNT_WIDTH \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32BG29B140F1024IM40_Peripheral_Parameters */ + +/** @} End of group EFR32BG29B140F1024IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b220f1024cj45.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b220f1024cj45.h new file mode 100644 index 000000000..94d4038dd --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b220f1024cj45.h @@ -0,0 +1,1456 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32BG29B220F1024CJ45 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29B220F1024CJ45_H +#define EFR32BG29B220F1024CJ45_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32BG29B220F1024CJ45 EFR32BG29B220F1024CJ45 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32BG29 Peripheral Interrupt Numbers ******************************************/ + + SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ + SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ + EMUEFP_IRQn = 7, /*!< 7 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 8, /*!< 8 EFR32 DCDC Interrupt */ + ETAMPDET_IRQn = 9, /*!< 9 EFR32 ETAMPDET Interrupt */ + TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 11, /*!< 11 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 12, /*!< 12 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 13, /*!< 13 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 14, /*!< 14 EFR32 TIMER4 Interrupt */ + RTCC_IRQn = 15, /*!< 15 EFR32 RTCC Interrupt */ + USART0_RX_IRQn = 16, /*!< 16 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 17, /*!< 17 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 18, /*!< 18 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 19, /*!< 19 EFR32 USART1_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + ICACHE0_IRQn = 22, /*!< 22 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 23, /*!< 23 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 24, /*!< 24 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 25, /*!< 25 EFR32 SYSCFG Interrupt */ + LDMA_IRQn = 26, /*!< 26 EFR32 LDMA Interrupt */ + LFXO_IRQn = 27, /*!< 27 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 28, /*!< 28 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 29, /*!< 29 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 30, /*!< 30 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 31, /*!< 31 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 32, /*!< 32 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 33, /*!< 33 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 34, /*!< 34 EFR32 EMUDG Interrupt */ + EMUSE_IRQn = 35, /*!< 35 EFR32 EMUSE Interrupt */ + AGC_IRQn = 36, /*!< 36 EFR32 AGC Interrupt */ + BUFC_IRQn = 37, /*!< 37 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 38, /*!< 38 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 39, /*!< 39 EFR32 FRC Interrupt */ + MODEM_IRQn = 40, /*!< 40 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 41, /*!< 41 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 42, /*!< 42 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 43, /*!< 43 EFR32 RAC_SEQ Interrupt */ + RDMAILBOX_IRQn = 44, /*!< 44 EFR32 RDMAILBOX Interrupt */ + RFSENSE_IRQn = 45, /*!< 45 EFR32 RFSENSE Interrupt */ + SYNTH_IRQn = 46, /*!< 46 EFR32 SYNTH Interrupt */ + PRORTC_IRQn = 47, /*!< 47 EFR32 PRORTC Interrupt */ + ACMP0_IRQn = 48, /*!< 48 EFR32 ACMP0 Interrupt */ + WDOG0_IRQn = 49, /*!< 49 EFR32 WDOG0 Interrupt */ + HFXO0_IRQn = 50, /*!< 50 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 51, /*!< 51 EFR32 HFRCO0 Interrupt */ + CMU_IRQn = 52, /*!< 52 EFR32 CMU Interrupt */ + AES_IRQn = 53, /*!< 53 EFR32 AES Interrupt */ + IADC_IRQn = 54, /*!< 54 EFR32 IADC Interrupt */ + MSC_IRQn = 55, /*!< 55 EFR32 MSC Interrupt */ + DPLL0_IRQn = 56, /*!< 56 EFR32 DPLL0 Interrupt */ + PDM_IRQn = 57, /*!< 57 EFR32 PDM Interrupt */ + SW0_IRQn = 58, /*!< 58 EFR32 SW0 Interrupt */ + SW1_IRQn = 59, /*!< 59 EFR32 SW1 Interrupt */ + SW2_IRQn = 60, /*!< 60 EFR32 SW2 Interrupt */ + SW3_IRQn = 61, /*!< 61 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 62, /*!< 62 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 63, /*!< 63 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 64, /*!< 64 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 65, /*!< 65 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 66, /*!< 66 EFR32 FPUEXH Interrupt */ + MPAHBRAM_IRQn = 67, /*!< 67 EFR32 MPAHBRAM Interrupt */ + EUSART1_RX_IRQn = 68, /*!< 68 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 69, /*!< 69 EFR32 EUSART1_TX Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32BG29B220F1024CJ45_Core EFR32BG29B220F1024CJ45 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32BG29B220F1024CJ45_Core */ + +/**************************************************************************//** +* @defgroup EFR32BG29B220F1024CJ45_Part EFR32BG29B220F1024CJ45 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32BG29B220F1024CJ45) +#define EFR32BG29B220F1024CJ45 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32BG29B220F1024CJ45" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_9 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 9 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 4 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x080FFFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x080FFFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32BG29B220F1024CJ45 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 7U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x007FUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 3U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0007UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 7U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x007FUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 2U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x0003UL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ + +/* Fixed Resource Locations */ +#define ETAMPDET_ETAMPIN0_PORT GPIO_PB_INDEX /**< Port of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN0_PIN 1U /**< Pin of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN1_PORT GPIO_PC_INDEX /**< Port of ETAMPIN1.*/ +#define ETAMPDET_ETAMPIN1_PIN 0U /**< Pin of ETAMPIN1.*/ +#define ETAMPDET_ETAMPOUT0_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT0_PIN 1U /**< Pin of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT1_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT1.*/ +#define ETAMPDET_ETAMPOUT1_PIN 2U /**< Pin of ETAMPOUT1.*/ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 0U /**< Pin of THMSW_HALFSWITCH.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 1 /** 1 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define ETAMPDET_PRESENT /** ETAMPDET is available in this part */ +#define ETAMPDET_COUNT 1 /** 1 ETAMPDETs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PDM_PRESENT /** PDM is available in this part */ +#define PDM_COUNT 1 /** 1 PDMs available */ +#define PRORTC_PRESENT /** PRORTC is available in this part */ +#define PRORTC_COUNT 1 /** 1 PRORTCs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define RTCC_PRESENT /** RTCC is available in this part */ +#define RTCC_COUNT 1 /** 1 RTCCs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 2 /** 2 USARTs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 1 /** 1 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32bg29.h" /* System Header File */ + +/** @} End of group EFR32BG29B220F1024CJ45_Part */ + +/**************************************************************************//** + * @defgroup EFR32BG29B220F1024CJ45_Peripheral_TypeDefs EFR32BG29B220F1024CJ45 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32bg29_emu.h" +#include "efr32bg29_cmu.h" +#include "efr32bg29_hfxo.h" +#include "efr32bg29_hfrco.h" +#include "efr32bg29_fsrco.h" +#include "efr32bg29_dpll.h" +#include "efr32bg29_lfxo.h" +#include "efr32bg29_lfrco.h" +#include "efr32bg29_ulfrco.h" +#include "efr32bg29_msc.h" +#include "efr32bg29_icache.h" +#include "efr32bg29_prs.h" +#include "efr32bg29_gpio.h" +#include "efr32bg29_ldma.h" +#include "efr32bg29_ldmaxbar.h" +#include "efr32bg29_timer.h" +#include "efr32bg29_usart.h" +#include "efr32bg29_burtc.h" +#include "efr32bg29_i2c.h" +#include "efr32bg29_syscfg.h" +#include "efr32bg29_buram.h" +#include "efr32bg29_gpcrc.h" +#include "efr32bg29_dcdc.h" +#include "efr32bg29_pdm.h" +#include "efr32bg29_etampdet.h" +#include "efr32bg29_mpahbram.h" +#include "efr32bg29_eusart.h" +#include "efr32bg29_aes.h" +#include "efr32bg29_smu.h" +#include "efr32bg29_rtcc.h" +#include "efr32bg29_wdog.h" +#include "efr32bg29_letimer.h" +#include "efr32bg29_iadc.h" +#include "efr32bg29_acmp.h" +#include "efr32bg29_semailbox.h" +#include "efr32bg29_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32bg29_prs_signals.h" +#include "efr32bg29_dma_descriptor.h" +#include "efr32bg29_ldmaxbar_defines.h" + +/** @} End of group EFR32BG29B220F1024CJ45_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32BG29B220F1024CJ45_Peripheral_Base EFR32BG29B220F1024CJ45 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ +#define ETAMPDET_S_BASE (0x400A4000UL) /* ETAMPDET_S base address */ +#define DMEM_S_BASE (0x400B0000UL) /* DMEM_S base address */ +#define EUSART1_S_BASE (0x400B4000UL) /* EUSART1_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ +#define WDOG0_S_BASE (0x48018000UL) /* WDOG0_S base address */ +#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ +#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ +#define EUSART0_S_BASE (0x4A040000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ +#define ETAMPDET_NS_BASE (0x500A4000UL) /* ETAMPDET_NS base address */ +#define DMEM_NS_BASE (0x500B0000UL) /* DMEM_NS base address */ +#define EUSART1_NS_BASE (0x500B4000UL) /* EUSART1_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ +#define WDOG0_NS_BASE (0x58018000UL) /* WDOG0_NS base address */ +#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ +#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ +#define EUSART0_NS_BASE (0x5A040000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) +#define PDM_BASE (PDM_S_BASE) /* PDM base address */ +#else +#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) +#define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ +#else +#define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) +#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ +#else +#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) +#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ +#else +#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32BG29B220F1024CJ45_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32BG29B220F1024CJ45_Peripheral_Declaration EFR32BG29B220F1024CJ45 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ +#define ETAMPDET_S ((ETAMPDET_TypeDef *) ETAMPDET_S_BASE) /**< ETAMPDET_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ +#define ETAMPDET_NS ((ETAMPDET_TypeDef *) ETAMPDET_NS_BASE) /**< ETAMPDET_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ +#define ETAMPDET ((ETAMPDET_TypeDef *) ETAMPDET_BASE) /**< ETAMPDET base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32BG29B220F1024CJ45_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32BG29B220F1024CJ45_Peripheral_Parameters EFR32BG29B220F1024CJ45 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x90UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define HFRCO0_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x100000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x1UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x5UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x0UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x4UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_PARTNUMBER 0x4UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_RAM0_INST_COUNT 0x10UL /**> None */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define PDM_FIFO_LEN 0x4UL /**> New Param */ +#define PDM_NUM_CH 0x2UL /**> None */ +#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ +#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ +#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ +#define PDM_PIPELINE 0x0UL /**> None */ +#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ +#define ETAMPDET_NUM_CHNLS 0x2UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_EXCLUDE_DALI 0x0UL /**> Exclude DALI */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x32UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x12UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x12UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define RTCC_CC_NUM 0x3UL /**> None */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x0UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x0UL /**> None */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_EXCLUDE_DALI 0x1UL /**> Exclude DALI */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ +#define PRORTC_CC_NUM 0x2UL /**> None */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_EXCLUDE_DALI(n) (((n) == 0) ? EUSART0_EXCLUDE_DALI \ + : ((n) == 1) ? EUSART1_EXCLUDE_DALI \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for IADC */ +#define IADC(n) (((n) == 0) ? IADC0 \ + : 0x0UL) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 \ + : -1) +#define IADC_CONFIGNUM(n) (((n) == 0) ? IADC0_CONFIGNUM \ + : 0x0UL) +#define IADC_FULLRANGEUNIPOLAR(n) (((n) == 0) ? IADC0_FULLRANGEUNIPOLAR \ + : 0x0UL) +#define IADC_SCANBYTES(n) (((n) == 0) ? IADC0_SCANBYTES \ + : 0x0UL) +#define IADC_ENTRIES(n) (((n) == 0) ? IADC0_ENTRIES \ + : 0x0UL) + +/* Instance macros for LETIMER */ +#define LETIMER(n) (((n) == 0) ? LETIMER0 \ + : 0x0UL) +#define LETIMER_NUM(ref) (((ref) == LETIMER0) ? 0 \ + : -1) +#define LETIMER_CNT_WIDTH(n) (((n) == 0) ? LETIMER0_CNT_WIDTH \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32BG29B220F1024CJ45_Peripheral_Parameters */ + +/** @} End of group EFR32BG29B220F1024CJ45 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b221f1024cj45.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b221f1024cj45.h new file mode 100644 index 000000000..c5aaf2770 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b221f1024cj45.h @@ -0,0 +1,1456 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32BG29B221F1024CJ45 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29B221F1024CJ45_H +#define EFR32BG29B221F1024CJ45_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32BG29B221F1024CJ45 EFR32BG29B221F1024CJ45 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32BG29 Peripheral Interrupt Numbers ******************************************/ + + SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ + SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ + EMUEFP_IRQn = 7, /*!< 7 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 8, /*!< 8 EFR32 DCDC Interrupt */ + ETAMPDET_IRQn = 9, /*!< 9 EFR32 ETAMPDET Interrupt */ + TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 11, /*!< 11 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 12, /*!< 12 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 13, /*!< 13 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 14, /*!< 14 EFR32 TIMER4 Interrupt */ + RTCC_IRQn = 15, /*!< 15 EFR32 RTCC Interrupt */ + USART0_RX_IRQn = 16, /*!< 16 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 17, /*!< 17 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 18, /*!< 18 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 19, /*!< 19 EFR32 USART1_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + ICACHE0_IRQn = 22, /*!< 22 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 23, /*!< 23 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 24, /*!< 24 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 25, /*!< 25 EFR32 SYSCFG Interrupt */ + LDMA_IRQn = 26, /*!< 26 EFR32 LDMA Interrupt */ + LFXO_IRQn = 27, /*!< 27 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 28, /*!< 28 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 29, /*!< 29 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 30, /*!< 30 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 31, /*!< 31 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 32, /*!< 32 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 33, /*!< 33 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 34, /*!< 34 EFR32 EMUDG Interrupt */ + EMUSE_IRQn = 35, /*!< 35 EFR32 EMUSE Interrupt */ + AGC_IRQn = 36, /*!< 36 EFR32 AGC Interrupt */ + BUFC_IRQn = 37, /*!< 37 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 38, /*!< 38 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 39, /*!< 39 EFR32 FRC Interrupt */ + MODEM_IRQn = 40, /*!< 40 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 41, /*!< 41 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 42, /*!< 42 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 43, /*!< 43 EFR32 RAC_SEQ Interrupt */ + RDMAILBOX_IRQn = 44, /*!< 44 EFR32 RDMAILBOX Interrupt */ + RFSENSE_IRQn = 45, /*!< 45 EFR32 RFSENSE Interrupt */ + SYNTH_IRQn = 46, /*!< 46 EFR32 SYNTH Interrupt */ + PRORTC_IRQn = 47, /*!< 47 EFR32 PRORTC Interrupt */ + ACMP0_IRQn = 48, /*!< 48 EFR32 ACMP0 Interrupt */ + WDOG0_IRQn = 49, /*!< 49 EFR32 WDOG0 Interrupt */ + HFXO0_IRQn = 50, /*!< 50 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 51, /*!< 51 EFR32 HFRCO0 Interrupt */ + CMU_IRQn = 52, /*!< 52 EFR32 CMU Interrupt */ + AES_IRQn = 53, /*!< 53 EFR32 AES Interrupt */ + IADC_IRQn = 54, /*!< 54 EFR32 IADC Interrupt */ + MSC_IRQn = 55, /*!< 55 EFR32 MSC Interrupt */ + DPLL0_IRQn = 56, /*!< 56 EFR32 DPLL0 Interrupt */ + PDM_IRQn = 57, /*!< 57 EFR32 PDM Interrupt */ + SW0_IRQn = 58, /*!< 58 EFR32 SW0 Interrupt */ + SW1_IRQn = 59, /*!< 59 EFR32 SW1 Interrupt */ + SW2_IRQn = 60, /*!< 60 EFR32 SW2 Interrupt */ + SW3_IRQn = 61, /*!< 61 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 62, /*!< 62 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 63, /*!< 63 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 64, /*!< 64 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 65, /*!< 65 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 66, /*!< 66 EFR32 FPUEXH Interrupt */ + MPAHBRAM_IRQn = 67, /*!< 67 EFR32 MPAHBRAM Interrupt */ + EUSART1_RX_IRQn = 68, /*!< 68 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 69, /*!< 69 EFR32 EUSART1_TX Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32BG29B221F1024CJ45_Core EFR32BG29B221F1024CJ45 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32BG29B221F1024CJ45_Core */ + +/**************************************************************************//** +* @defgroup EFR32BG29B221F1024CJ45_Part EFR32BG29B221F1024CJ45 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32BG29B221F1024CJ45) +#define EFR32BG29B221F1024CJ45 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32BG29B221F1024CJ45" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_9 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 9 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 4 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x080FFFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x080FFFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32BG29B221F1024CJ45 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00030000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 7U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x007FUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 3U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0007UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 7U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x007FUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 2U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x0003UL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ + +/* Fixed Resource Locations */ +#define ETAMPDET_ETAMPIN0_PORT GPIO_PB_INDEX /**< Port of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN0_PIN 1U /**< Pin of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN1_PORT GPIO_PC_INDEX /**< Port of ETAMPIN1.*/ +#define ETAMPDET_ETAMPIN1_PIN 0U /**< Pin of ETAMPIN1.*/ +#define ETAMPDET_ETAMPOUT0_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT0_PIN 1U /**< Pin of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT1_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT1.*/ +#define ETAMPDET_ETAMPOUT1_PIN 2U /**< Pin of ETAMPOUT1.*/ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 0U /**< Pin of THMSW_HALFSWITCH.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 1 /** 1 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define ETAMPDET_PRESENT /** ETAMPDET is available in this part */ +#define ETAMPDET_COUNT 1 /** 1 ETAMPDETs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PDM_PRESENT /** PDM is available in this part */ +#define PDM_COUNT 1 /** 1 PDMs available */ +#define PRORTC_PRESENT /** PRORTC is available in this part */ +#define PRORTC_COUNT 1 /** 1 PRORTCs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define RTCC_PRESENT /** RTCC is available in this part */ +#define RTCC_COUNT 1 /** 1 RTCCs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 2 /** 2 USARTs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 1 /** 1 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32bg29.h" /* System Header File */ + +/** @} End of group EFR32BG29B221F1024CJ45_Part */ + +/**************************************************************************//** + * @defgroup EFR32BG29B221F1024CJ45_Peripheral_TypeDefs EFR32BG29B221F1024CJ45 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32bg29_emu.h" +#include "efr32bg29_cmu.h" +#include "efr32bg29_hfxo.h" +#include "efr32bg29_hfrco.h" +#include "efr32bg29_fsrco.h" +#include "efr32bg29_dpll.h" +#include "efr32bg29_lfxo.h" +#include "efr32bg29_lfrco.h" +#include "efr32bg29_ulfrco.h" +#include "efr32bg29_msc.h" +#include "efr32bg29_icache.h" +#include "efr32bg29_prs.h" +#include "efr32bg29_gpio.h" +#include "efr32bg29_ldma.h" +#include "efr32bg29_ldmaxbar.h" +#include "efr32bg29_timer.h" +#include "efr32bg29_usart.h" +#include "efr32bg29_burtc.h" +#include "efr32bg29_i2c.h" +#include "efr32bg29_syscfg.h" +#include "efr32bg29_buram.h" +#include "efr32bg29_gpcrc.h" +#include "efr32bg29_dcdc.h" +#include "efr32bg29_pdm.h" +#include "efr32bg29_etampdet.h" +#include "efr32bg29_mpahbram.h" +#include "efr32bg29_eusart.h" +#include "efr32bg29_aes.h" +#include "efr32bg29_smu.h" +#include "efr32bg29_rtcc.h" +#include "efr32bg29_wdog.h" +#include "efr32bg29_letimer.h" +#include "efr32bg29_iadc.h" +#include "efr32bg29_acmp.h" +#include "efr32bg29_semailbox.h" +#include "efr32bg29_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32bg29_prs_signals.h" +#include "efr32bg29_dma_descriptor.h" +#include "efr32bg29_ldmaxbar_defines.h" + +/** @} End of group EFR32BG29B221F1024CJ45_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32BG29B221F1024CJ45_Peripheral_Base EFR32BG29B221F1024CJ45 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ +#define ETAMPDET_S_BASE (0x400A4000UL) /* ETAMPDET_S base address */ +#define DMEM_S_BASE (0x400B0000UL) /* DMEM_S base address */ +#define EUSART1_S_BASE (0x400B4000UL) /* EUSART1_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ +#define WDOG0_S_BASE (0x48018000UL) /* WDOG0_S base address */ +#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ +#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ +#define EUSART0_S_BASE (0x4A040000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ +#define ETAMPDET_NS_BASE (0x500A4000UL) /* ETAMPDET_NS base address */ +#define DMEM_NS_BASE (0x500B0000UL) /* DMEM_NS base address */ +#define EUSART1_NS_BASE (0x500B4000UL) /* EUSART1_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ +#define WDOG0_NS_BASE (0x58018000UL) /* WDOG0_NS base address */ +#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ +#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ +#define EUSART0_NS_BASE (0x5A040000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) +#define PDM_BASE (PDM_S_BASE) /* PDM base address */ +#else +#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) +#define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ +#else +#define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) +#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ +#else +#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) +#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ +#else +#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32BG29B221F1024CJ45_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32BG29B221F1024CJ45_Peripheral_Declaration EFR32BG29B221F1024CJ45 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ +#define ETAMPDET_S ((ETAMPDET_TypeDef *) ETAMPDET_S_BASE) /**< ETAMPDET_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ +#define ETAMPDET_NS ((ETAMPDET_TypeDef *) ETAMPDET_NS_BASE) /**< ETAMPDET_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ +#define ETAMPDET ((ETAMPDET_TypeDef *) ETAMPDET_BASE) /**< ETAMPDET base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32BG29B221F1024CJ45_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32BG29B221F1024CJ45_Peripheral_Parameters EFR32BG29B221F1024CJ45 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x90UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define HFRCO0_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x100000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x1UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x5UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x0UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x4UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_PARTNUMBER 0x4UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_RAM0_INST_COUNT 0x10UL /**> None */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define PDM_FIFO_LEN 0x4UL /**> New Param */ +#define PDM_NUM_CH 0x2UL /**> None */ +#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ +#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ +#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ +#define PDM_PIPELINE 0x0UL /**> None */ +#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ +#define ETAMPDET_NUM_CHNLS 0x2UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_EXCLUDE_DALI 0x0UL /**> Exclude DALI */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x32UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x12UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x12UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define RTCC_CC_NUM 0x3UL /**> None */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x0UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x0UL /**> None */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_EXCLUDE_DALI 0x1UL /**> Exclude DALI */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ +#define PRORTC_CC_NUM 0x2UL /**> None */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_EXCLUDE_DALI(n) (((n) == 0) ? EUSART0_EXCLUDE_DALI \ + : ((n) == 1) ? EUSART1_EXCLUDE_DALI \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for IADC */ +#define IADC(n) (((n) == 0) ? IADC0 \ + : 0x0UL) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 \ + : -1) +#define IADC_CONFIGNUM(n) (((n) == 0) ? IADC0_CONFIGNUM \ + : 0x0UL) +#define IADC_FULLRANGEUNIPOLAR(n) (((n) == 0) ? IADC0_FULLRANGEUNIPOLAR \ + : 0x0UL) +#define IADC_SCANBYTES(n) (((n) == 0) ? IADC0_SCANBYTES \ + : 0x0UL) +#define IADC_ENTRIES(n) (((n) == 0) ? IADC0_ENTRIES \ + : 0x0UL) + +/* Instance macros for LETIMER */ +#define LETIMER(n) (((n) == 0) ? LETIMER0 \ + : 0x0UL) +#define LETIMER_NUM(ref) (((ref) == LETIMER0) ? 0 \ + : -1) +#define LETIMER_CNT_WIDTH(n) (((n) == 0) ? LETIMER0_CNT_WIDTH \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32BG29B221F1024CJ45_Peripheral_Parameters */ + +/** @} End of group EFR32BG29B221F1024CJ45 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b230f1024cm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b230f1024cm40.h new file mode 100644 index 000000000..c2d0c3b95 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/efr32bg29b230f1024cm40.h @@ -0,0 +1,1470 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32BG29B230F1024CM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG29B230F1024CM40_H +#define EFR32BG29B230F1024CM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32BG29B230F1024CM40 EFR32BG29B230F1024CM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32BG29 Peripheral Interrupt Numbers ******************************************/ + + SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ + SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ + EMUEFP_IRQn = 7, /*!< 7 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 8, /*!< 8 EFR32 DCDC Interrupt */ + ETAMPDET_IRQn = 9, /*!< 9 EFR32 ETAMPDET Interrupt */ + TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 11, /*!< 11 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 12, /*!< 12 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 13, /*!< 13 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 14, /*!< 14 EFR32 TIMER4 Interrupt */ + RTCC_IRQn = 15, /*!< 15 EFR32 RTCC Interrupt */ + USART0_RX_IRQn = 16, /*!< 16 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 17, /*!< 17 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 18, /*!< 18 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 19, /*!< 19 EFR32 USART1_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + ICACHE0_IRQn = 22, /*!< 22 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 23, /*!< 23 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 24, /*!< 24 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 25, /*!< 25 EFR32 SYSCFG Interrupt */ + LDMA_IRQn = 26, /*!< 26 EFR32 LDMA Interrupt */ + LFXO_IRQn = 27, /*!< 27 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 28, /*!< 28 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 29, /*!< 29 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 30, /*!< 30 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 31, /*!< 31 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 32, /*!< 32 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 33, /*!< 33 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 34, /*!< 34 EFR32 EMUDG Interrupt */ + EMUSE_IRQn = 35, /*!< 35 EFR32 EMUSE Interrupt */ + AGC_IRQn = 36, /*!< 36 EFR32 AGC Interrupt */ + BUFC_IRQn = 37, /*!< 37 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 38, /*!< 38 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 39, /*!< 39 EFR32 FRC Interrupt */ + MODEM_IRQn = 40, /*!< 40 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 41, /*!< 41 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 42, /*!< 42 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 43, /*!< 43 EFR32 RAC_SEQ Interrupt */ + RDMAILBOX_IRQn = 44, /*!< 44 EFR32 RDMAILBOX Interrupt */ + RFSENSE_IRQn = 45, /*!< 45 EFR32 RFSENSE Interrupt */ + SYNTH_IRQn = 46, /*!< 46 EFR32 SYNTH Interrupt */ + PRORTC_IRQn = 47, /*!< 47 EFR32 PRORTC Interrupt */ + ACMP0_IRQn = 48, /*!< 48 EFR32 ACMP0 Interrupt */ + WDOG0_IRQn = 49, /*!< 49 EFR32 WDOG0 Interrupt */ + HFXO0_IRQn = 50, /*!< 50 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 51, /*!< 51 EFR32 HFRCO0 Interrupt */ + CMU_IRQn = 52, /*!< 52 EFR32 CMU Interrupt */ + AES_IRQn = 53, /*!< 53 EFR32 AES Interrupt */ + IADC_IRQn = 54, /*!< 54 EFR32 IADC Interrupt */ + MSC_IRQn = 55, /*!< 55 EFR32 MSC Interrupt */ + DPLL0_IRQn = 56, /*!< 56 EFR32 DPLL0 Interrupt */ + PDM_IRQn = 57, /*!< 57 EFR32 PDM Interrupt */ + SW0_IRQn = 58, /*!< 58 EFR32 SW0 Interrupt */ + SW1_IRQn = 59, /*!< 59 EFR32 SW1 Interrupt */ + SW2_IRQn = 60, /*!< 60 EFR32 SW2 Interrupt */ + SW3_IRQn = 61, /*!< 61 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 62, /*!< 62 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 63, /*!< 63 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 64, /*!< 64 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 65, /*!< 65 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 66, /*!< 66 EFR32 FPUEXH Interrupt */ + MPAHBRAM_IRQn = 67, /*!< 67 EFR32 MPAHBRAM Interrupt */ + EUSART1_RX_IRQn = 68, /*!< 68 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 69, /*!< 69 EFR32 EUSART1_TX Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32BG29B230F1024CM40_Core EFR32BG29B230F1024CM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32BG29B230F1024CM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32BG29B230F1024CM40_Part EFR32BG29B230F1024CM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32BG29B230F1024CM40) +#define EFR32BG29B230F1024CM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32BG29B230F1024CM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_9 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 9 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 6 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x080FFFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x080FFFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32BG29B230F1024CM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define ETAMPDET_ETAMPIN0_PORT GPIO_PB_INDEX /**< Port of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN0_PIN 1U /**< Pin of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN1_PORT GPIO_PC_INDEX /**< Port of ETAMPIN1.*/ +#define ETAMPDET_ETAMPIN1_PIN 0U /**< Pin of ETAMPIN1.*/ +#define ETAMPDET_ETAMPOUT0_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT0_PIN 1U /**< Pin of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT1_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT1.*/ +#define ETAMPDET_ETAMPOUT1_PIN 2U /**< Pin of ETAMPOUT1.*/ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 0U /**< Pin of THMSW_HALFSWITCH.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 1 /** 1 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define ETAMPDET_PRESENT /** ETAMPDET is available in this part */ +#define ETAMPDET_COUNT 1 /** 1 ETAMPDETs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PDM_PRESENT /** PDM is available in this part */ +#define PDM_COUNT 1 /** 1 PDMs available */ +#define PRORTC_PRESENT /** PRORTC is available in this part */ +#define PRORTC_COUNT 1 /** 1 PRORTCs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define RTCC_PRESENT /** RTCC is available in this part */ +#define RTCC_COUNT 1 /** 1 RTCCs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 2 /** 2 USARTs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 1 /** 1 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32bg29.h" /* System Header File */ + +/** @} End of group EFR32BG29B230F1024CM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32BG29B230F1024CM40_Peripheral_TypeDefs EFR32BG29B230F1024CM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32bg29_emu.h" +#include "efr32bg29_cmu.h" +#include "efr32bg29_hfxo.h" +#include "efr32bg29_hfrco.h" +#include "efr32bg29_fsrco.h" +#include "efr32bg29_dpll.h" +#include "efr32bg29_lfxo.h" +#include "efr32bg29_lfrco.h" +#include "efr32bg29_ulfrco.h" +#include "efr32bg29_msc.h" +#include "efr32bg29_icache.h" +#include "efr32bg29_prs.h" +#include "efr32bg29_gpio.h" +#include "efr32bg29_ldma.h" +#include "efr32bg29_ldmaxbar.h" +#include "efr32bg29_timer.h" +#include "efr32bg29_usart.h" +#include "efr32bg29_burtc.h" +#include "efr32bg29_i2c.h" +#include "efr32bg29_syscfg.h" +#include "efr32bg29_buram.h" +#include "efr32bg29_gpcrc.h" +#include "efr32bg29_dcdc.h" +#include "efr32bg29_pdm.h" +#include "efr32bg29_etampdet.h" +#include "efr32bg29_mpahbram.h" +#include "efr32bg29_eusart.h" +#include "efr32bg29_aes.h" +#include "efr32bg29_smu.h" +#include "efr32bg29_rtcc.h" +#include "efr32bg29_wdog.h" +#include "efr32bg29_letimer.h" +#include "efr32bg29_iadc.h" +#include "efr32bg29_acmp.h" +#include "efr32bg29_semailbox.h" +#include "efr32bg29_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32bg29_prs_signals.h" +#include "efr32bg29_dma_descriptor.h" +#include "efr32bg29_ldmaxbar_defines.h" + +/** @} End of group EFR32BG29B230F1024CM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32BG29B230F1024CM40_Peripheral_Base EFR32BG29B230F1024CM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ +#define ETAMPDET_S_BASE (0x400A4000UL) /* ETAMPDET_S base address */ +#define DMEM_S_BASE (0x400B0000UL) /* DMEM_S base address */ +#define EUSART1_S_BASE (0x400B4000UL) /* EUSART1_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ +#define WDOG0_S_BASE (0x48018000UL) /* WDOG0_S base address */ +#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ +#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ +#define EUSART0_S_BASE (0x4A040000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ +#define ETAMPDET_NS_BASE (0x500A4000UL) /* ETAMPDET_NS base address */ +#define DMEM_NS_BASE (0x500B0000UL) /* DMEM_NS base address */ +#define EUSART1_NS_BASE (0x500B4000UL) /* EUSART1_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ +#define WDOG0_NS_BASE (0x58018000UL) /* WDOG0_NS base address */ +#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ +#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ +#define EUSART0_NS_BASE (0x5A040000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) +#define PDM_BASE (PDM_S_BASE) /* PDM base address */ +#else +#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) +#define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ +#else +#define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) +#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ +#else +#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) +#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ +#else +#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32BG29B230F1024CM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32BG29B230F1024CM40_Peripheral_Declaration EFR32BG29B230F1024CM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ +#define ETAMPDET_S ((ETAMPDET_TypeDef *) ETAMPDET_S_BASE) /**< ETAMPDET_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ +#define ETAMPDET_NS ((ETAMPDET_TypeDef *) ETAMPDET_NS_BASE) /**< ETAMPDET_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ +#define ETAMPDET ((ETAMPDET_TypeDef *) ETAMPDET_BASE) /**< ETAMPDET base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32BG29B230F1024CM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32BG29B230F1024CM40_Peripheral_Parameters EFR32BG29B230F1024CM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x90UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define HFRCO0_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x100000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x1UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x5UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x0UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x4UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_PARTNUMBER 0x4UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_RAM0_INST_COUNT 0x10UL /**> None */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define PDM_FIFO_LEN 0x4UL /**> New Param */ +#define PDM_NUM_CH 0x2UL /**> None */ +#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ +#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ +#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ +#define PDM_PIPELINE 0x0UL /**> None */ +#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ +#define ETAMPDET_NUM_CHNLS 0x2UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_EXCLUDE_DALI 0x0UL /**> Exclude DALI */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x32UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x12UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x12UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define RTCC_CC_NUM 0x3UL /**> None */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x0UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x0UL /**> None */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_EXCLUDE_DALI 0x1UL /**> Exclude DALI */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ +#define PRORTC_CC_NUM 0x2UL /**> None */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_EXCLUDE_DALI(n) (((n) == 0) ? EUSART0_EXCLUDE_DALI \ + : ((n) == 1) ? EUSART1_EXCLUDE_DALI \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for IADC */ +#define IADC(n) (((n) == 0) ? IADC0 \ + : 0x0UL) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 \ + : -1) +#define IADC_CONFIGNUM(n) (((n) == 0) ? IADC0_CONFIGNUM \ + : 0x0UL) +#define IADC_FULLRANGEUNIPOLAR(n) (((n) == 0) ? IADC0_FULLRANGEUNIPOLAR \ + : 0x0UL) +#define IADC_SCANBYTES(n) (((n) == 0) ? IADC0_SCANBYTES \ + : 0x0UL) +#define IADC_ENTRIES(n) (((n) == 0) ? IADC0_ENTRIES \ + : 0x0UL) + +/* Instance macros for LETIMER */ +#define LETIMER(n) (((n) == 0) ? LETIMER0 \ + : 0x0UL) +#define LETIMER_NUM(ref) (((ref) == LETIMER0) ? 0 \ + : -1) +#define LETIMER_CNT_WIDTH(n) (((n) == 0) ? LETIMER0_CNT_WIDTH \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32BG29B230F1024CM40_Peripheral_Parameters */ + +/** @} End of group EFR32BG29B230F1024CM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/em_device.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/em_device.h new file mode 100644 index 000000000..afe035565 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/em_device.h @@ -0,0 +1,67 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H +#if defined(EFR32BG29B140F1024IM40) +#include "efr32bg29b140f1024im40.h" + +#elif defined(EFR32BG29B220F1024CJ45) +#include "efr32bg29b220f1024cj45.h" + +#elif defined(EFR32BG29B221F1024CJ45) +#include "efr32bg29b221f1024cj45.h" + +#elif defined(EFR32BG29B230F1024CM40) +#include "efr32bg29b230f1024cm40.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif + +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif + +#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif +#endif /* EM_DEVICE_H */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/system_efr32bg29.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/system_efr32bg29.h new file mode 100644 index 000000000..981c25e74 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/system_efr32bg29.h @@ -0,0 +1,247 @@ +/**************************************************************************//** + * @file + * @brief CMSIS system header file for EFR32BG29 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32BG29_H +#define SYSTEM_EFR32BG29_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "sl_code_classification.h" + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFR32BG29 EFR32BG29 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ +#endif + +/*Re-direction of IRQn.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn +#else +#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn +#endif /* SL_TRUSTZONE_SECURE */ + +/*Re-direction of IRQHandler.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler +#else +#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler +#endif /* SL_TRUSTZONE_SECURE */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SecureFault_Handler(void); /**< Secure Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +/* Part Specific Interrupts */ +void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */ +void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */ +void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */ +void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ +void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ +void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ +void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ +void ETAMPDET_IRQHandler(void); /**< ETAMPDET IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ +void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ +void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ +void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ +void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ +void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ +void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ +void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ +void EMUSE_IRQHandler(void); /**< EMUSE IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void RDMAILBOX_IRQHandler(void); /**< RDMAILBOX IRQ Handler */ +void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void PRORTC_IRQHandler(void); /**< PRORTC IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ +void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void AES_IRQHandler(void); /**< AES IRQ Handler */ +void IADC_IRQHandler(void); /**< IADC IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ +void PDM_IRQHandler(void); /**< PDM IRQ Handler */ +void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ +void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ +void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ +void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ +void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ +void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ +void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ +void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ +void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ +void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */ +void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ +void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ +#endif + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHCLKGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE uint32_t SystemCoreClockGet(void) +{ + return SystemHCLKGet(); +} + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemHCLKGet(); +} + +void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFRCODPLLClockGet(void); +void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemULFRCOClockGet(void); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32BG29_H */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Source/system_efr32bg29.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Source/system_efr32bg29.c new file mode 100644 index 000000000..3ba78ea4b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Source/system_efr32bg29.c @@ -0,0 +1,598 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M33 system support for EFR32BG29 devices. + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +// System oscillator frequencies. These frequencies are normally constant +// for a target, but they are made configurable in order to allow run-time +// handling of different boards. The crystal oscillator clocks can be set +// compile time to a non-default value by defining respective nFXO_FREQ +// values according to board design. By defining the nFXO_FREQ to 0, +// one indicates that the oscillator is not present, in order to save some +// SW footprint. + +#if !defined(FSRCO_FREQ) +// FSRCO frequency +#define FSRCO_FREQ (20000000UL) +#endif + +#if !defined(HFXO_FREQ) +// HFXO frequency +#define HFXO_FREQ (38400000UL) +#endif + +#if !defined(HFRCODPLL_STARTUP_FREQ) +// HFRCODPLL startup frequency +#define HFRCODPLL_STARTUP_FREQ (19000000UL) +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +// Maximum HFRCODPLL frequency +#define HFRCODPLL_MAX_FREQ (80000000UL) +#endif + +// CLKIN0 input +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) +#define CLKIN0_FREQ (0UL) +#endif + +#if !defined(LFRCO_MAX_FREQ) +// LFRCO frequency, tuned to below frequency during manufacturing. +#define LFRCO_FREQ (32768UL) +#endif + +#if !defined(ULFRCO_FREQ) +// ULFRCO frequency +#define ULFRCO_FREQ (1000UL) +#endif + +#if !defined(LFXO_FREQ) +// LFXO frequency +#define LFXO_FREQ (LFRCO_FREQ) +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// NOTE: Gecko bootloaders can't have static variable allocation. +// System HFXO clock frequency +static uint32_t SystemHFXOClock = HFXO_FREQ; +#endif + +#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// System LFXO clock frequency +static uint32_t SystemLFXOClock = LFXO_FREQ; +#endif + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +// System HFRCODPLL clock frequency +static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; + +#endif + +/*--------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *---------------------------------------------------------------------------*/ +extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ + | (3U << 11U * 2U)); /* set CP11 Full Access */ +#endif + +/* Secure app takes care of moving between the security states. + * SL_TRUSTZONE_SECURE MACRO is for secure access. + * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. + * When both the MACROS are not defined, during start-up below code makes sure + * that all the peripherals are accessed from non-secure address except SMU, + * as SMU is used to configure the trustzone state of the system. */ +#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ + && defined(__TZ_PRESENT) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; + + // config SMU to Secure and other peripherals to Non-Secure. + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; +#if defined (SEMAILBOX_PRESENT) + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); +#else + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); +#endif + + // SAU treats all accesses as non-secure +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + __DSB(); + __ISB(); +#else + #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." +#endif // __ARM_FEATURE_CMSE + +// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +#endif //SL_TRUSTZONE_SECURE +} + +/**************************************************************************//** + * @brief + * Get current HFRCODPLL frequency. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCODPLLClockGet(void) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + return SystemHFRCODPLLClock; +#else + uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +#endif +} + +/**************************************************************************//** + * @brief + * Set HFRCODPLL frequency value. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +void SystemHFRCODPLLClockSet(uint32_t freq) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFRCODPLLClock = freq; +#else + (void) freq; // Unused parameter +#endif +} + +/***************************************************************************//** + * @brief + * Get the current system clock frequency (SYSCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * hardware configuration. + * + * @note + * This is an EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * Current system clock (SYSCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemSYSCLKGet(void) +{ + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: +#if defined(SYSTEM_NO_STATIC_MEMORY) + ret = HFXO_FREQ; +#else + ret = SystemHFXOClock; +#endif + break; +#endif + +#if (CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = FSRCO_FREQ; + break; + + default: + // Unknown clock source. + while (1) { + } + } + return ret; +} + +/***************************************************************************//** + * @brief + * Get the current system core clock frequency (HCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * The current core clock (HCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemHCLKGet(void) +{ + uint32_t presc, ret; + + ret = SystemSYSCLKGet(); + + presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; + + ret /= presc + 1U; + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + // Keep CMSIS system clock variable up-to-date + SystemCoreClock = ret; +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ + ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + // The external crystal oscillator is not present if HFXO_FREQ==0 +#if (HFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return HFXO_FREQ; +#else + return SystemHFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFXOClock = freq; + + // Update core clock frequency if HFXO is used to clock core + if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) + == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { + // This function will update the global variable + SystemHCLKGet(); + } +#else + (void) freq; // Unused parameter +#endif +} + +/**************************************************************************//** + * @brief + * Get current CLKIN0 frequency. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * CLKIN0 frequency in Hz. + *****************************************************************************/ +uint32_t SystemCLKIN0Get(void) +{ + return CLKIN0_FREQ; +} + +/**************************************************************************//** + * @brief + * Get FSRCO frequency. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * FSRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemFSRCOClockGet(void) +{ + return FSRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + return LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + // The ULFRCO frequency is not tuned, and can be very inaccurate + return ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + // External crystal present? +#if (LFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return LFXO_FREQ; +#else + return SystemLFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32BG29 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemLFXOClock = freq; +#else + (void) freq; // Unused parameter +#endif +} diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h index ea5fb87fd..aacfec87e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f128gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1343,119 +1344,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A010F128GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h index 45276dc96..8fcce9b43 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1343,119 +1344,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A010F256GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h index 72fb94e56..1fa107069 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f256gm48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1440,119 +1441,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A010F256GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h index 0a579e596..5c3d576e4 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1343,119 +1344,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A010F512GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h index 758b0a86b..189bfc4e5 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a010f512gm48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1440,119 +1441,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A010F512GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h index bfc77c232..e7a860a10 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a011f512gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1340,119 +1341,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A011F512GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h index 0aecbe560..51d3b2b2e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f128gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1343,119 +1344,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A020F128GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h index 85462cf77..c144a6583 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1343,119 +1344,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A020F256GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h index 73cbb0610..55cba48d0 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f256gm48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1440,119 +1441,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A020F256GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h index 8e74855ce..73b05a04e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1343,119 +1344,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A020F512GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h index 0528f1b6e..41123e659 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a020f512gm48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1440,119 +1441,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A020F512GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h index cdd240918..bd25bb102 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23a021f512gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1340,119 +1341,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23A021F512GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h index 27c98f721..57f696e64 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f128gm40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1344,119 +1345,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B010F128GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h index 70c0a74ea..a507b61ff 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512gm48.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1441,119 +1442,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B010F512GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h index dcf91d95b..66cc12ba3 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1344,119 +1345,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B010F512IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h index 993bc3d50..35c8b514f 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b010f512im48.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1441,119 +1442,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B010F512IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h index 230cea932..ad6d557d7 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f128gm40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1344,119 +1345,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B020F128GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h index be70e9a62..309add85e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1344,119 +1345,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B020F512IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h index 7c0ef9d11..7a4dd804b 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b020f512im48.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1441,119 +1442,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B020F512IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h index d94aa9bb5..c1d4fe2cf 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1341,119 +1342,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B021F512IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h index 2a1197792..576edd9d7 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/efr32fg23b021f512im48.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1444,119 +1445,105 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : ((n) == 2) ? EUSART2 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : ((ref) == EUSART2) ? 2 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32FG23B021F512IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h index 8e79649db..04e928874 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/system_efr32fg23.h @@ -36,6 +36,7 @@ extern "C" { #endif #include +#include "sl_code_classification.h" /***************************************************************************//** * @addtogroup Parts @@ -177,6 +178,7 @@ void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */ void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ #endif +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHCLKGet(void); /**************************************************************************//** @@ -193,6 +195,7 @@ uint32_t SystemHCLKGet(void); * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE uint32_t SystemCoreClockGet(void) { return SystemHCLKGet(); @@ -212,24 +215,35 @@ static __INLINE uint32_t SystemCoreClockGet(void) * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE void SystemCoreClockUpdate(void) { SystemHCLKGet(); } void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCODPLLClockGet(void); void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFXOClockGet(void); void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCOEM23ClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFXOClockGet(void); void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemULFRCOClockGet(void); /** @} End of group */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c index cc8265676..86f20fa13 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Source/system_efr32fg23.c @@ -31,6 +31,15 @@ #include #include "em_device.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ @@ -64,7 +73,10 @@ #endif // CLKIN0 input -#if !defined(CLKIN0_FREQ) +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) #define CLKIN0_FREQ (0UL) #endif @@ -204,12 +216,11 @@ void SystemInit(void) *****************************************************************************/ uint32_t SystemHFRCODPLLClockGet(void) { -#if defined(BOOTLOADER_SYSTEM_NO_STATIC_MEMORY) - return HFRCODPLL_STARTUP_FREQ; -#elif !defined(SYSTEM_NO_STATIC_MEMORY) +#if !defined(SYSTEM_NO_STATIC_MEMORY) return SystemHFRCODPLLClock; #else uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; // Get oscillator frequency band switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) @@ -516,6 +527,7 @@ uint32_t SystemFSRCOClockGet(void) uint32_t SystemHFRCOEM23ClockGet(void) { uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; // Get oscillator frequency band switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h index a23c6f263..e5b7ac554 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f1024im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1174,14 +1175,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h index 8a0585c67..e597e8f4d 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f512im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1174,14 +1175,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h index bb413a5ac..5f84a0652 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a010f768im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1174,14 +1175,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h index 94eaf3f1f..a5c19bc24 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f1024im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1176,14 +1177,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h index 583889522..53745acf1 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f512im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1176,14 +1177,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h index c5262e441..e2acda177 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21a020f768im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1176,14 +1177,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h index ebcade29e..d53245420 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f1024im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1174,14 +1175,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h index 9f8a01f09..39db5a4ce 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f512im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1174,14 +1175,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h index ff7dfb2b1..46a1ec890 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b010f768im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1174,14 +1175,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h index d28c02ef7..56b7ba1ca 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f1024im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1176,14 +1177,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h index a994b8fd5..a80f9c66d 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f512im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1176,14 +1177,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h index 3e9b12f31..0d244e0dc 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/efr32mg21b020f768im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1176,14 +1177,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h index 721c99e58..7471285bd 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/rm21z000f1024im32.h @@ -132,6 +132,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0003U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1172,14 +1173,6 @@ typedef enum IRQn{ : ((n) == 1) ? ACMP1_EXT_OVR_IF \ : 0x0UL) -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) - /* Instance macros for I2C */ #define I2C(n) (((n) == 0) ? I2C0 \ : ((n) == 1) ? I2C1 \ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h index 6222190e4..d002283b4 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/system_efr32mg21.h @@ -36,6 +36,7 @@ extern "C" { #endif #include +#include "sl_code_classification.h" /***************************************************************************//** * @addtogroup Parts @@ -148,6 +149,7 @@ void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ #endif +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHCLKGet(void); /**************************************************************************//** @@ -164,6 +166,7 @@ uint32_t SystemHCLKGet(void); * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE uint32_t SystemCoreClockGet(void) { return SystemHCLKGet(); @@ -183,24 +186,35 @@ static __INLINE uint32_t SystemCoreClockGet(void) * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE void SystemCoreClockUpdate(void) { SystemHCLKGet(); } void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCODPLLClockGet(void); void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFXOClockGet(void); void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCOEM23ClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFXOClockGet(void); void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemULFRCOClockGet(void); /** @} End of group */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c index 0239a0c8b..347d42b22 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Source/system_efr32mg21.c @@ -31,6 +31,15 @@ #include #include "em_device.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ @@ -64,7 +73,10 @@ #endif // CLKIN0 input -#if !defined(CLKIN0_FREQ) +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) #define CLKIN0_FREQ (0UL) #endif @@ -203,13 +215,10 @@ void SystemInit(void) *****************************************************************************/ uint32_t SystemHFRCODPLLClockGet(void) { -#if defined(BOOTLOADER_SYSTEM_NO_STATIC_MEMORY) - return HFRCODPLL_STARTUP_FREQ; -#elif !defined(SYSTEM_NO_STATIC_MEMORY) +#if !defined(SYSTEM_NO_STATIC_MEMORY) return SystemHFRCODPLLClock; #else uint32_t ret = 0UL; - // Get oscillator frequency band switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) >> _HFRCO_CAL_FREQRANGE_SHIFT) { @@ -515,7 +524,6 @@ uint32_t SystemFSRCOClockGet(void) uint32_t SystemHFRCOEM23ClockGet(void) { uint32_t ret = 0UL; - // Get oscillator frequency band switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) >> _HFRCO_CAL_FREQRANGE_SHIFT) { diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h index d753c07a7..047a1891a 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F1024IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h index ff30c96b2..e3432ae49 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1024im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1364,141 +1365,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F1024IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h index 113787cad..5e6e2998e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F1536GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h index 9cae88956..e21bec61a 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536gm48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1364,141 +1365,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F1536GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h index 5b3e652ef..c1f99d754 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h index 419f045a3..9ea8bd490 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f1536im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1364,141 +1365,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h index 6a6de1882..026f3d2c9 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F768IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h index 9f7949a3b..6a0ab7682 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a010f768im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1364,141 +1365,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A010F768IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h index 904275a8d..c051bd429 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A020F1024IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h index b46c706e7..744b8cd32 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1024im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A020F1024IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h index 8b18ca2e4..f6f6f070b 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A020F1536GM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h index 3ca9e9a36..7798dbe4e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536gm48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A020F1536GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h index 939f28e78..bc71e578f 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A020F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h index 197321ca5..1365060a8 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f1536im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A020F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h index a0ffa2521..0db02dc46 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a020f768im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A020F768IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h index 8e3a371df..b3a23c743 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a021f1024im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1357,141 +1358,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A021F1024IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h index 5b4494700..6353b7f01 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1024im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A110F1024IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h index 37525e7c3..01ff228f7 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a110f1536gm48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A110F1536GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h index 102e6aa8a..df39e7c19 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a111f1536gm48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1359,141 +1360,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A111F1536GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h index 91f39e014..4ca7636c2 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a120f1536gm48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1358,141 +1359,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A120F1536GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h index 499fcc1db..c7f90cd01 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a121f1536gm48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1357,141 +1358,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A121F1536GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h index 7e451b63a..d1e72d8ca 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A410F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h index 6dfefc2b2..4c8f5bd6e 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a410f1536im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1364,141 +1365,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A410F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h index 80f829de6..17134d4d5 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A420F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h index c75e60b1e..e07e238f5 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a420f1536im48.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A420F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h index 0c3908fa1..4e7383155 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a610f1536im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1362,141 +1363,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A610F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h index 56e700fc7..c68de9603 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24a620f1536im40.h @@ -145,6 +145,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1360,141 +1361,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24A620F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h index 5d3ba86e6..bec976462 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1024im48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1365,141 +1366,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B010F1024IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h index a1cfe5869..052752d3c 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1363,141 +1364,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B010F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h index 678dc2005..db8625dca 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b010f1536im48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1365,141 +1366,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B010F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h index 9646aca2d..609e5fe16 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1024im48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1363,141 +1364,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B020F1024IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h index 4f3ad9e0a..8674db732 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1361,141 +1362,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B020F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h index 7a648e866..bfbfef459 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b020f1536im48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1363,141 +1364,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B020F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h index 628235677..96e8e82e6 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536gm48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1361,141 +1362,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B110F1536GM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h index 003a82387..e229efe71 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b110f1536im48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1361,141 +1362,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B110F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h index 1b217bfe4..3c07373e4 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b120f1536im48.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1359,141 +1360,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B120F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h index 1ddfa10c0..ddf74ceb2 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im40.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1377,141 +1378,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B210F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h index 37d7e4387..31ef6966d 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b210f1536im48.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1379,141 +1380,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B210F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h index 8eb064612..d8bc4efd7 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1377,141 +1378,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B220F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h index fd169f21b..81babb424 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b310f1536im48.h @@ -147,6 +147,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1375,141 +1376,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B310F1536IM48_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h index 229cb7df6..70bc32cc7 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b610f1536im40.h @@ -146,6 +146,7 @@ typedef enum IRQn{ * @brief Processor and Core Peripheral Section *****************************************************************************/ +#define __CORTEXM 1U /**< Core architecture */ #define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ #define __DSP_PRESENT 1U /**< Presence of DSP */ #define __FPU_PRESENT 1U /**< Presence of FPU */ @@ -1363,141 +1364,127 @@ typedef enum IRQn{ #define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ /* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) /* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) /* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) /* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) /* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) /* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) /** @} End of group EFR32MG24B610F1536IM40_Peripheral_Parameters */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h index 7271f9c38..a9764f2d8 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h @@ -36,6 +36,7 @@ extern "C" { #endif #include +#include "sl_code_classification.h" /***************************************************************************//** * @addtogroup Parts @@ -177,6 +178,7 @@ void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */ void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ #endif +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHCLKGet(void); /**************************************************************************//** @@ -193,6 +195,7 @@ uint32_t SystemHCLKGet(void); * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE uint32_t SystemCoreClockGet(void) { return SystemHCLKGet(); @@ -212,24 +215,35 @@ static __INLINE uint32_t SystemCoreClockGet(void) * provided for CMSIS compliance and if a user modifies the the core clock * outside the EMLIB CMU API. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) static __INLINE void SystemCoreClockUpdate(void) { SystemHCLKGet(); } void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCODPLLClockGet(void); void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFXOClockGet(void); void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemHFRCOEM23ClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFXOClockGet(void); void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) uint32_t SystemULFRCOClockGet(void); /** @} End of group */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c index 1fe9aa3fb..7a8dbfd19 100644 --- a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c @@ -31,6 +31,15 @@ #include #include "em_device.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + /******************************************************************************* ****************************** DEFINES ************************************ ******************************************************************************/ @@ -64,7 +73,10 @@ #endif // CLKIN0 input -#if !defined(CLKIN0_FREQ) +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) #define CLKIN0_FREQ (0UL) #endif @@ -204,12 +216,11 @@ void SystemInit(void) *****************************************************************************/ uint32_t SystemHFRCODPLLClockGet(void) { -#if defined(BOOTLOADER_SYSTEM_NO_STATIC_MEMORY) - return HFRCODPLL_STARTUP_FREQ; -#elif !defined(SYSTEM_NO_STATIC_MEMORY) +#if !defined(SYSTEM_NO_STATIC_MEMORY) return SystemHFRCODPLLClock; #else uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; // Get oscillator frequency band switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) @@ -516,6 +527,7 @@ uint32_t SystemFSRCOClockGet(void) uint32_t SystemHFRCOEM23ClockGet(void) { uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; // Get oscillator frequency band switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h new file mode 100644 index 000000000..e87ceef22 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_acmp.h @@ -0,0 +1,650 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 ACMP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_ACMP_H +#define EFR32MG29_ACMP_H +#define ACMP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_ACMP ACMP + * @{ + * @brief EFR32MG29 ACMP Register Declaration. + *****************************************************************************/ + +/** ACMP Register Declaration. */ +typedef struct acmp_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +} ACMP_TypeDef; +/** @} End of group EFR32MG29_ACMP */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_ACMP + * @{ + * @defgroup EFR32MG29_ACMP_BitFields ACMP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ + +/* Bit fields for ACMP EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ + +/* Bit fields for ACMP SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ + +/* Bit fields for ACMP CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 0x00000040UL /**< Mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 0x00000042UL /**< Mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 << 8) /**< Shifted mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 << 8) /**< Shifted mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ + +/** @} End of group EFR32MG29_ACMP_BitFields */ +/** @} End of group EFR32MG29_ACMP */ +/** @} End of group Parts */ + +#endif // EFR32MG29_ACMP_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_aes.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_aes.h new file mode 100644 index 000000000..56a3f1e2d --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_aes.h @@ -0,0 +1,453 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 AES register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_AES_H +#define EFR32MG29_AES_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_AES AES + * @{ + * @brief EFR32MG29 AES Register Declaration. + *****************************************************************************/ + +/** AES Register Declaration. */ +typedef struct aes_typedef{ + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +} AES_TypeDef; +/** @} End of group EFR32MG29_AES */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_AES + * @{ + * @defgroup EFR32MG29_AES_BitFields AES Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AES FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ + +/* Bit fields for AES FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ + +/* Bit fields for AES FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ + +/* Bit fields for AES PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ + +/* Bit fields for AES PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ + +/* Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ + +/* Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ + +/* Bit fields for AES BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ + +/* Bit fields for AES BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ + +/* Bit fields for AES BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ + +/* Bit fields for AES BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ + +/* Bit fields for AES BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ + +/** @} End of group EFR32MG29_AES_BitFields */ +/** @} End of group EFR32MG29_AES */ +/** @} End of group Parts */ + +#endif // EFR32MG29_AES_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_buram.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_buram.h new file mode 100644 index 000000000..929b00f63 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_buram.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 BURAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_BURAM_H +#define EFR32MG29_BURAM_H +#define BURAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_BURAM BURAM + * @{ + * @brief EFR32MG29 BURAM Register Declaration. + *****************************************************************************/ + +/** BURAM RET Register Group Declaration. */ +typedef struct buram_ret_typedef{ + __IOM uint32_t REG; /**< Retention Register */ +} BURAM_RET_TypeDef; + +/** BURAM Register Declaration. */ +typedef struct buram_typedef{ + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +} BURAM_TypeDef; +/** @} End of group EFR32MG29_BURAM */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_BURAM + * @{ + * @defgroup EFR32MG29_BURAM_BitFields BURAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURAM RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ + +/** @} End of group EFR32MG29_BURAM_BitFields */ +/** @} End of group EFR32MG29_BURAM */ +/** @} End of group Parts */ + +#endif // EFR32MG29_BURAM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_burtc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_burtc.h new file mode 100644 index 000000000..94ec1878b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_burtc.h @@ -0,0 +1,332 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 BURTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_BURTC_H +#define EFR32MG29_BURTC_H +#define BURTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_BURTC BURTC + * @{ + * @brief EFR32MG29 BURTC Register Declaration. + *****************************************************************************/ + +/** BURTC Register Declaration. */ +typedef struct burtc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +} BURTC_TypeDef; +/** @} End of group EFR32MG29_BURTC */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_BURTC + * @{ + * @defgroup EFR32MG29_BURTC_BitFields BURTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURTC IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ + +/* Bit fields for BURTC EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000001UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ + +/* Bit fields for BURTC CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DISABLE (_BURTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_ENABLE (_BURTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ + +/* Bit fields for BURTC CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ + +/* Bit fields for BURTC IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ + +/* Bit fields for BURTC CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ + +/* Bit fields for BURTC SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000003FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_EN (0x1UL << 5) /**< Sync busy for EN */ +#define _BURTC_SYNCBUSY_EN_SHIFT 5 /**< Shift value for BURTC_EN */ +#define _BURTC_SYNCBUSY_EN_MASK 0x20UL /**< Bit mask for BURTC_EN */ +#define _BURTC_SYNCBUSY_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_EN_DEFAULT (_BURTC_SYNCBUSY_EN_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ + +/** @} End of group EFR32MG29_BURTC_BitFields */ +/** @} End of group EFR32MG29_BURTC */ +/** @} End of group Parts */ + +#endif // EFR32MG29_BURTC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_cmu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_cmu.h new file mode 100644 index 000000000..2444dbcd2 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_cmu.h @@ -0,0 +1,1017 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 CMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_CMU_H +#define EFR32MG29_CMU_H +#define CMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_CMU CMU + * @{ + * @brief EFR32MG29 CMU Register Declaration. + *****************************************************************************/ + +/** CMU Register Declaration. */ +typedef struct cmu_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED11[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED13[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED14[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL; /**< RTCC Clock Control */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL; /**< Protocol RTC Clock Control */ + uint32_t RESERVED16[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[860U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED23[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED24[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED28[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_SET; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED31[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED32[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED33[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED34[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_SET; /**< RTCC Clock Control */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_SET; /**< Protocol RTC Clock Control */ + uint32_t RESERVED36[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[860U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED43[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED45[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED48[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED49[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_CLR; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED50[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED51[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED52[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED53[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_CLR; /**< RTCC Clock Control */ + uint32_t RESERVED55[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_CLR; /**< Protocol RTC Clock Control */ + uint32_t RESERVED56[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED57[1U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ + uint32_t RESERVED59[860U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED60[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED61[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED62[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED63[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED64[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED65[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED66[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED67[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED68[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED69[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_TGL; /**< EM01 Peripheral Group B Clock Control */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED70[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED71[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED72[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED73[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED74[15U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_TGL; /**< RTCC Clock Control */ + uint32_t RESERVED75[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_TGL; /**< Protocol RTC Clock Control */ + uint32_t RESERVED76[13U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED77[1U]; /**< Reserved for future use */ + uint32_t RESERVED78[1U]; /**< Reserved for future use */ +} CMU_TypeDef; +/** @} End of group EFR32MG29_CMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_CMU + * @{ + * @defgroup EFR32MG29_CMU_BitFields CMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0030001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFEFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 8 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x100UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART1 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART1_SHIFT 9 /**< Shift value for CMU_USART1 */ +#define _CMU_CLKEN0_USART1_MASK 0x200UL /**< Bit mask for CMU_USART1 */ +#define _CMU_CLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART1_DEFAULT (_CMU_CLKEN0_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 19 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x80000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 20 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x100000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 21 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x200000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 22 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x400000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 23 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x800000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PDM (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PDM_SHIFT 25 /**< Shift value for CMU_PDM */ +#define _CMU_CLKEN0_PDM_MASK 0x2000000UL /**< Bit mask for CMU_PDM */ +#define _CMU_CLKEN0_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PDM_DEFAULT (_CMU_CLKEN0_PDM_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RTCC (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RTCC_SHIFT 30 /**< Shift value for CMU_RTCC */ +#define _CMU_CLKEN0_RTCC_MASK 0x40000000UL /**< Bit mask for CMU_RTCC */ +#define _CMU_CLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RTCC_DEFAULT (_CMU_CLKEN0_RTCC_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ + +/* Bit fields for CMU CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x10FFDFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RDSCRATCHPAD */ +#define _CMU_CLKEN1_RDSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RDSCRATCHPAD */ +#define _CMU_CLKEN1_RDSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RDSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX0 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDMAILBOX0_SHIFT 8 /**< Shift value for CMU_RDMAILBOX0 */ +#define _CMU_CLKEN1_RDMAILBOX0_MASK 0x100UL /**< Bit mask for CMU_RDMAILBOX0 */ +#define _CMU_CLKEN1_RDMAILBOX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX0_DEFAULT (_CMU_CLKEN1_RDMAILBOX0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX1 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDMAILBOX1_SHIFT 9 /**< Shift value for CMU_RDMAILBOX1 */ +#define _CMU_CLKEN1_RDMAILBOX1_MASK 0x200UL /**< Bit mask for CMU_RDMAILBOX1 */ +#define _CMU_CLKEN1_RDMAILBOX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX1_DEFAULT (_CMU_CLKEN1_RDMAILBOX1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PRORTC (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PRORTC_SHIFT 10 /**< Shift value for CMU_PRORTC */ +#define _CMU_CLKEN1_PRORTC_MASK 0x400UL /**< Bit mask for CMU_PRORTC */ +#define _CMU_CLKEN1_PRORTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PRORTC_DEFAULT (_CMU_CLKEN1_PRORTC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_IFADCDEBUG (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_IFADCDEBUG_SHIFT 12 /**< Shift value for CMU_IFADCDEBUG */ +#define _CMU_CLKEN1_IFADCDEBUG_MASK 0x1000UL /**< Bit mask for CMU_IFADCDEBUG */ +#define _CMU_CLKEN1_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_IFADCDEBUG_DEFAULT (_CMU_CLKEN1_IFADCDEBUG_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSENSE (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSENSE_SHIFT 14 /**< Shift value for CMU_RFSENSE */ +#define _CMU_CLKEN1_RFSENSE_MASK 0x4000UL /**< Bit mask for CMU_RFSENSE */ +#define _CMU_CLKEN1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSENSE_DEFAULT (_CMU_CLKEN1_RFSENSE_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 15 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x8000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 16 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x10000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 17 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x20000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_TIMER4 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_TIMER4_SHIFT 18 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN1_TIMER4_MASK 0x40000UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_TIMER4_DEFAULT (_CMU_CLKEN1_TIMER4_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 19 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x80000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 20 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x100000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 21 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x200000UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 22 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x400000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ETAMPDET (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ETAMPDET_SHIFT 28 /**< Shift value for CMU_ETAMPDET */ +#define _CMU_CLKEN1_ETAMPDET_MASK 0x10000000UL /**< Bit mask for CMU_ETAMPDET */ +#define _CMU_CLKEN1_ETAMPDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ETAMPDET_DEFAULT (_CMU_CLKEN1_ETAMPDET_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ + +/* Bit fields for CMU SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ + +/* Bit fields for CMU TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000002UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DISABLED (_CMU_TRACECLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ + +/* Bit fields for CMU EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ + +/* Bit fields for CMU DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ + +/* Bit fields for CMU EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ + +/* Bit fields for CMU EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 (_CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPBCLKCTRL */ + +/* Bit fields for CMU EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ + +/* Bit fields for CMU EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ + +/* Bit fields for CMU EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ + +/* Bit fields for CMU IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ + +/* Bit fields for CMU WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ + +/* Bit fields for CMU RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_DEFAULT (_CMU_RTCCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_LFRCO (_CMU_RTCCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_LFXO (_CMU_RTCCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_ULFRCO (_CMU_RTCCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_RTCCCLKCTRL */ + +/* Bit fields for CMU PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT (_CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_LFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_LFXO (_CMU_PRORTCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_PRORTCCLKCTRL */ + +/* Bit fields for CMU RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_FORCECLKENRADIO (0x1UL << 1) /**< Force Radio Clock Enable in EM1P */ +#define _CMU_RADIOCLKCTRL_FORCECLKENRADIO_SHIFT 1 /**< Shift value for CMU_FORCECLKENRADIO */ +#define _CMU_RADIOCLKCTRL_FORCECLKENRADIO_MASK 0x2UL /**< Bit mask for CMU_FORCECLKENRADIO */ +#define _CMU_RADIOCLKCTRL_FORCECLKENRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_FORCECLKENRADIO_DEFAULT (_CMU_RADIOCLKCTRL_FORCECLKENRADIO_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ + +/* Bit fields for CMU EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_FSRCO (_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EUSART0CLKCTRL */ + +/** @} End of group EFR32MG29_CMU_BitFields */ +/** @} End of group EFR32MG29_CMU */ +/** @} End of group Parts */ + +#endif // EFR32MG29_CMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dcdc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dcdc.h new file mode 100644 index 000000000..8bbc8b0ca --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dcdc.h @@ -0,0 +1,718 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 DCDC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_DCDC_H +#define EFR32MG29_DCDC_H +#define DCDC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_DCDC DCDC + * @{ + * @brief EFR32MG29 DCDC Register Declaration. + *****************************************************************************/ + +/** DCDC Register Declaration. */ +typedef struct dcdc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0; /**< EM23 Control */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL; /**< Boost Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL; /**< EM23 Boost Control */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS; /**< Coulomb Counter Status */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[7U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[967U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL_SET; /**< Boost Control Register */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL_SET; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL_SET; /**< EM23 Boost Control */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL_SET; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL_SET; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD_SET; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT_SET; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT_SET; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR_SET; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF_SET; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN_SET; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS_SET; /**< Coulomb Counter Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[967U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL_CLR; /**< Boost Control Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL_CLR; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL_CLR; /**< EM23 Boost Control */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + uint32_t RESERVED30[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL_CLR; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL_CLR; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD_CLR; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT_CLR; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT_CLR; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR_CLR; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF_CLR; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN_CLR; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS_CLR; /**< Coulomb Counter Status */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ + uint32_t RESERVED32[2U]; /**< Reserved for future use */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + uint32_t RESERVED36[7U]; /**< Reserved for future use */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + uint32_t RESERVED38[967U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t BSTCTRL_TGL; /**< Boost Control Register */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t BSTEM01CTRL_TGL; /**< EM01 Boost Control */ + __IOM uint32_t BSTEM23CTRL_TGL; /**< EM23 Boost Control */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + uint32_t RESERVED43[7U]; /**< Reserved for future use */ + __IOM uint32_t CCCTRL_TGL; /**< Coulomb Counter Control */ + __IOM uint32_t CCCALCTRL_TGL; /**< Coulomb Counter Calibration Control */ + __IOM uint32_t CCCMD_TGL; /**< Coulomb Counter Command */ + __IM uint32_t CCEM0CNT_TGL; /**< Coulomb Counter EM0 Count Value */ + __IM uint32_t CCEM2CNT_TGL; /**< Coulomb Counter EM2 Count Value */ + __IOM uint32_t CCTHR_TGL; /**< Coulomb Counter Threshold */ + __IOM uint32_t CCIF_TGL; /**< Coulomb Counter Interrupt Flag */ + __IOM uint32_t CCIEN_TGL; /**< Coulomb Counter Interrupt Enable */ + __IM uint32_t CCSTATUS_TGL; /**< Coulomb Counter Status */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ + uint32_t RESERVED45[2U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[7U]; /**< Reserved for future use */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + uint32_t RESERVED49[7U]; /**< Reserved for future use */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ +} DCDC_TypeDef; +/** @} End of group EFR32MG29_DCDC */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_DCDC + * @{ + * @defgroup EFR32MG29_DCDC_BitFields DCDC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DCDC IPVERSION */ +#define _DCDC_IPVERSION_RESETVALUE 0x00000006UL /**< Default value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000006UL /**< Mode DEFAULT for DCDC_IPVERSION */ +#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ + +/* Bit fields for DCDC CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000040UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x0000CF71UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_OFF (_DCDC_CTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_SHIFT 8 /**< Shift value for DCDC_DVDDBSTPRG */ +#define _DCDC_CTRL_DVDDBSTPRG_MASK 0xF00UL /**< Bit mask for DCDC_DVDDBSTPRG */ +#define _DCDC_CTRL_DVDDBSTPRG_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_1V8 0x00000000UL /**< Mode BOOST_1V8 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_1V9 0x00000001UL /**< Mode BOOST_1V9 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V 0x00000002UL /**< Mode BOOST_2V for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V1 0x00000003UL /**< Mode BOOST_2V1 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V2 0x00000004UL /**< Mode BOOST_2V2 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V3 0x00000005UL /**< Mode BOOST_2V3 for DCDC_CTRL */ +#define _DCDC_CTRL_DVDDBSTPRG_BOOST_2V4 0x00000006UL /**< Mode BOOST_2V4 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_DEFAULT (_DCDC_CTRL_DVDDBSTPRG_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_1V8 (_DCDC_CTRL_DVDDBSTPRG_BOOST_1V8 << 8) /**< Shifted mode BOOST_1V8 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_1V9 (_DCDC_CTRL_DVDDBSTPRG_BOOST_1V9 << 8) /**< Shifted mode BOOST_1V9 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V << 8) /**< Shifted mode BOOST_2V for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V1 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V1 << 8) /**< Shifted mode BOOST_2V1 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V2 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V2 << 8) /**< Shifted mode BOOST_2V2 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V3 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V3 << 8) /**< Shifted mode BOOST_2V3 for DCDC_CTRL */ +#define DCDC_CTRL_DVDDBSTPRG_BOOST_2V4 (_DCDC_CTRL_DVDDBSTPRG_BOOST_2V4 << 8) /**< Shifted mode BOOST_2V4 for DCDC_CTRL */ +#define DCDC_CTRL_FORCEBIAS (0x1UL << 14) /**< Force Comparators to be biased */ +#define _DCDC_CTRL_FORCEBIAS_SHIFT 14 /**< Shift value for DCDC_FORCEBIAS */ +#define _DCDC_CTRL_FORCEBIAS_MASK 0x4000UL /**< Bit mask for DCDC_FORCEBIAS */ +#define _DCDC_CTRL_FORCEBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_FORCEBIAS_DEFAULT (_DCDC_CTRL_FORCEBIAS_DEFAULT << 14) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_FIXEDEMBIAS (0x1UL << 15) /**< Force EM2 config settings */ +#define _DCDC_CTRL_FIXEDEMBIAS_SHIFT 15 /**< Shift value for DCDC_FIXEDEMBIAS */ +#define _DCDC_CTRL_FIXEDEMBIAS_MASK 0x8000UL /**< Bit mask for DCDC_FIXEDEMBIAS */ +#define _DCDC_CTRL_FIXEDEMBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_FIXEDEMBIAS_DEFAULT (_DCDC_CTRL_FIXEDEMBIAS_DEFAULT << 15) /**< Shifted mode DEFAULT for DCDC_CTRL */ + +/* Bit fields for DCDC EM01CTRL0 */ +#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ + +/* Bit fields for DCDC EM23CTRL0 */ +#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ + +/* Bit fields for DCDC BSTCTRL */ +#define _DCDC_BSTCTRL_RESETVALUE 0x00000047UL /**< Default value for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_MASK 0x00000077UL /**< Mask for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_SHIFT 0 /**< Shift value for DCDC_BSTTOFFMAX */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_MASK 0x7UL /**< Bit mask for DCDC_BSTTOFFMAX */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT 0x00000007UL /**< Mode DEFAULT for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_OFF 0x00000000UL /**< Mode OFF for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT (_DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_OFF (_DCDC_BSTCTRL_BSTTOFFMAX_OFF << 0) /**< Shifted mode OFF for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us << 0) /**< Shifted mode TMAX_0P35us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us << 0) /**< Shifted mode TMAX_0P63us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us << 0) /**< Shifted mode TMAX_0P91us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us << 0) /**< Shifted mode TMAX_1P19us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us << 0) /**< Shifted mode TMAX_1P47us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us << 0) /**< Shifted mode TMAX_1P75us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us << 0) /**< Shifted mode TMAX_2P03us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_BSTCTRL */ +#define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_OFF (_DCDC_BSTCTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_BSTCTRL */ +#define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_BSTCTRL */ + +/* Bit fields for DCDC BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_RESETVALUE 0x0000010DUL /**< Default value for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_MASK 0x0000030FUL /**< Mask for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_DEFAULT 0x0000000DUL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load10mA 0x00000004UL /**< Mode Load10mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load11mA 0x00000005UL /**< Mode Load11mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load13mA 0x00000006UL /**< Mode Load13mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load15mA 0x00000007UL /**< Mode Load15mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load16mA 0x00000008UL /**< Mode Load16mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load18mA 0x00000009UL /**< Mode Load18mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load20mA 0x0000000AUL /**< Mode Load20mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load21mA 0x0000000BUL /**< Mode Load21mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load23mA 0x0000000CUL /**< Mode Load23mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load25mA 0x0000000DUL /**< Mode Load25mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_IPKVAL_Load26mA 0x0000000EUL /**< Mode Load26mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM01CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load10mA (_DCDC_BSTEM01CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load11mA (_DCDC_BSTEM01CTRL_IPKVAL_Load11mA << 0) /**< Shifted mode Load11mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load13mA (_DCDC_BSTEM01CTRL_IPKVAL_Load13mA << 0) /**< Shifted mode Load13mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load15mA (_DCDC_BSTEM01CTRL_IPKVAL_Load15mA << 0) /**< Shifted mode Load15mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load16mA (_DCDC_BSTEM01CTRL_IPKVAL_Load16mA << 0) /**< Shifted mode Load16mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load18mA (_DCDC_BSTEM01CTRL_IPKVAL_Load18mA << 0) /**< Shifted mode Load18mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load20mA (_DCDC_BSTEM01CTRL_IPKVAL_Load20mA << 0) /**< Shifted mode Load20mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load21mA (_DCDC_BSTEM01CTRL_IPKVAL_Load21mA << 0) /**< Shifted mode Load21mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load23mA (_DCDC_BSTEM01CTRL_IPKVAL_Load23mA << 0) /**< Shifted mode Load23mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load25mA (_DCDC_BSTEM01CTRL_IPKVAL_Load25mA << 0) /**< Shifted mode Load25mA for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_IPKVAL_Load26mA (_DCDC_BSTEM01CTRL_IPKVAL_Load26mA << 0) /**< Shifted mode Load26mA for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ +#define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT (_DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ +#define DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING (_DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_BSTEM01CTRL*/ + +/* Bit fields for DCDC BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_RESETVALUE 0x0000010AUL /**< Default value for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_MASK 0x0000030FUL /**< Mask for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_DEFAULT 0x0000000AUL /**< Mode DEFAULT for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_Load5mA 0x00000004UL /**< Mode Load5mA for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_IPKVAL_Load10mA 0x0000000AUL /**< Mode Load10mA for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM23CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_IPKVAL_Load5mA (_DCDC_BSTEM23CTRL_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_IPKVAL_Load10mA (_DCDC_BSTEM23CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM23CTRL */ +#define _DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT (_DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_BSTEM23CTRL */ +#define DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING (_DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_BSTEM23CTRL*/ + +/* Bit fields for DCDC IF */ +#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ +#define _DCDC_IF_MASK 0x000000FFUL /**< Mask for DCDC_IF */ +#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ +#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ +#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ +#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold */ +#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold */ +#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ +#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX (0x1UL << 6) /**< Buck Max Ton/Boost Max Toff reached */ +#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ +#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ + +/* Bit fields for DCDC IEN */ +#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ +#define _DCDC_IEN_MASK 0x000000FFUL /**< Mask for DCDC_IEN */ +#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ +#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ +#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ +#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ +#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ +#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ +#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ + +/* Bit fields for DCDC STATUS */ +#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ +#define _DCDC_STATUS_MASK 0x0000001FUL /**< Mask for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ +#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ +#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ +#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ +#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ +#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ + +/* Bit fields for DCDC SYNCBUSY */ +#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_MASK 0x00000001UL /**< Mask for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< Combined Sync Busy Status */ +#define _DCDC_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_SYNCBUSY_DEFAULT (_DCDC_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ + +/* Bit fields for DCDC CCCTRL */ +#define _DCDC_CCCTRL_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCTRL */ +#define _DCDC_CCCTRL_MASK 0x00000001UL /**< Mask for DCDC_CCCTRL */ +#define DCDC_CCCTRL_CCEN (0x1UL << 0) /**< Coulomb Counter Enable */ +#define _DCDC_CCCTRL_CCEN_SHIFT 0 /**< Shift value for DCDC_CCEN */ +#define _DCDC_CCCTRL_CCEN_MASK 0x1UL /**< Bit mask for DCDC_CCEN */ +#define _DCDC_CCCTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCTRL */ +#define DCDC_CCCTRL_CCEN_DEFAULT (_DCDC_CCCTRL_CCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCTRL */ + +/* Bit fields for DCDC CCCALCTRL */ +#define _DCDC_CCCALCTRL_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_MASK 0x0000030FUL /**< Mask for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLOADEN (0x1UL << 0) /**< CC Load Circuit Enable */ +#define _DCDC_CCCALCTRL_CCLOADEN_SHIFT 0 /**< Shift value for DCDC_CCLOADEN */ +#define _DCDC_CCCALCTRL_CCLOADEN_MASK 0x1UL /**< Bit mask for DCDC_CCLOADEN */ +#define _DCDC_CCCALCTRL_CCLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLOADEN_DEFAULT (_DCDC_CCCALCTRL_CCLOADEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_SHIFT 1 /**< Shift value for DCDC_CCLVL */ +#define _DCDC_CCCALCTRL_CCLVL_MASK 0xEUL /**< Bit mask for DCDC_CCLVL */ +#define _DCDC_CCCALCTRL_CCLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD0 0x00000000UL /**< Mode LOAD0 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD1 0x00000001UL /**< Mode LOAD1 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD2 0x00000002UL /**< Mode LOAD2 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD3 0x00000003UL /**< Mode LOAD3 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD4 0x00000004UL /**< Mode LOAD4 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD5 0x00000005UL /**< Mode LOAD5 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD6 0x00000006UL /**< Mode LOAD6 for DCDC_CCCALCTRL */ +#define _DCDC_CCCALCTRL_CCLVL_LOAD7 0x00000007UL /**< Mode LOAD7 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_DEFAULT (_DCDC_CCCALCTRL_CCLVL_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD0 (_DCDC_CCCALCTRL_CCLVL_LOAD0 << 1) /**< Shifted mode LOAD0 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD1 (_DCDC_CCCALCTRL_CCLVL_LOAD1 << 1) /**< Shifted mode LOAD1 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD2 (_DCDC_CCCALCTRL_CCLVL_LOAD2 << 1) /**< Shifted mode LOAD2 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD3 (_DCDC_CCCALCTRL_CCLVL_LOAD3 << 1) /**< Shifted mode LOAD3 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD4 (_DCDC_CCCALCTRL_CCLVL_LOAD4 << 1) /**< Shifted mode LOAD4 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD5 (_DCDC_CCCALCTRL_CCLVL_LOAD5 << 1) /**< Shifted mode LOAD5 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD6 (_DCDC_CCCALCTRL_CCLVL_LOAD6 << 1) /**< Shifted mode LOAD6 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCLVL_LOAD7 (_DCDC_CCCALCTRL_CCLVL_LOAD7 << 1) /**< Shifted mode LOAD7 for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALEM2 (0x1UL << 8) /**< CC Calibrate EM2 */ +#define _DCDC_CCCALCTRL_CCCALEM2_SHIFT 8 /**< Shift value for DCDC_CCCALEM2 */ +#define _DCDC_CCCALCTRL_CCCALEM2_MASK 0x100UL /**< Bit mask for DCDC_CCCALEM2 */ +#define _DCDC_CCCALCTRL_CCCALEM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALEM2_DEFAULT (_DCDC_CCCALCTRL_CCCALEM2_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALHALT (0x1UL << 9) /**< CC Calibration Halt Req */ +#define _DCDC_CCCALCTRL_CCCALHALT_SHIFT 9 /**< Shift value for DCDC_CCCALHALT */ +#define _DCDC_CCCALCTRL_CCCALHALT_MASK 0x200UL /**< Bit mask for DCDC_CCCALHALT */ +#define _DCDC_CCCALCTRL_CCCALHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ +#define DCDC_CCCALCTRL_CCCALHALT_DEFAULT (_DCDC_CCCALCTRL_CCCALHALT_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ + +/* Bit fields for DCDC CCCMD */ +#define _DCDC_CCCMD_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCMD */ +#define _DCDC_CCCMD_MASK 0x00000007UL /**< Mask for DCDC_CCCMD */ +#define DCDC_CCCMD_START (0x1UL << 0) /**< Start CC */ +#define _DCDC_CCCMD_START_SHIFT 0 /**< Shift value for DCDC_START */ +#define _DCDC_CCCMD_START_MASK 0x1UL /**< Bit mask for DCDC_START */ +#define _DCDC_CCCMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_START_DEFAULT (_DCDC_CCCMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_STOP (0x1UL << 1) /**< Stop CC */ +#define _DCDC_CCCMD_STOP_SHIFT 1 /**< Shift value for DCDC_STOP */ +#define _DCDC_CCCMD_STOP_MASK 0x2UL /**< Bit mask for DCDC_STOP */ +#define _DCDC_CCCMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_STOP_DEFAULT (_DCDC_CCCMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_CLR (0x1UL << 2) /**< Clear CC */ +#define _DCDC_CCCMD_CLR_SHIFT 2 /**< Shift value for DCDC_CLR */ +#define _DCDC_CCCMD_CLR_MASK 0x4UL /**< Bit mask for DCDC_CLR */ +#define _DCDC_CCCMD_CLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ +#define DCDC_CCCMD_CLR_DEFAULT (_DCDC_CCCMD_CLR_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCCMD */ + +/* Bit fields for DCDC CCEM0CNT */ +#define _DCDC_CCEM0CNT_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCEM0CNT */ +#define _DCDC_CCEM0CNT_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCEM0CNT */ +#define _DCDC_CCEM0CNT_CCCNT_SHIFT 0 /**< Shift value for DCDC_CCCNT */ +#define _DCDC_CCEM0CNT_CCCNT_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_CCCNT */ +#define _DCDC_CCEM0CNT_CCCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCEM0CNT */ +#define DCDC_CCEM0CNT_CCCNT_DEFAULT (_DCDC_CCEM0CNT_CCCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCEM0CNT */ + +/* Bit fields for DCDC CCEM2CNT */ +#define _DCDC_CCEM2CNT_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCEM2CNT */ +#define _DCDC_CCEM2CNT_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCEM2CNT */ +#define _DCDC_CCEM2CNT_CCCNT_SHIFT 0 /**< Shift value for DCDC_CCCNT */ +#define _DCDC_CCEM2CNT_CCCNT_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_CCCNT */ +#define _DCDC_CCEM2CNT_CCCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCEM2CNT */ +#define DCDC_CCEM2CNT_CCCNT_DEFAULT (_DCDC_CCEM2CNT_CCCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCEM2CNT */ + +/* Bit fields for DCDC CCTHR */ +#define _DCDC_CCTHR_RESETVALUE 0x00010001UL /**< Default value for DCDC_CCTHR */ +#define _DCDC_CCTHR_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCTHR */ +#define _DCDC_CCTHR_EM0CNT_SHIFT 0 /**< Shift value for DCDC_EM0CNT */ +#define _DCDC_CCTHR_EM0CNT_MASK 0xFFFFUL /**< Bit mask for DCDC_EM0CNT */ +#define _DCDC_CCTHR_EM0CNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CCTHR */ +#define DCDC_CCTHR_EM0CNT_DEFAULT (_DCDC_CCTHR_EM0CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCTHR */ +#define _DCDC_CCTHR_EM2CNT_SHIFT 16 /**< Shift value for DCDC_EM2CNT */ +#define _DCDC_CCTHR_EM2CNT_MASK 0xFFFF0000UL /**< Bit mask for DCDC_EM2CNT */ +#define _DCDC_CCTHR_EM2CNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CCTHR */ +#define DCDC_CCTHR_EM2CNT_DEFAULT (_DCDC_CCTHR_EM2CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DCDC_CCTHR */ + +/* Bit fields for DCDC CCIF */ +#define _DCDC_CCIF_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCIF */ +#define _DCDC_CCIF_MASK 0x0000000FUL /**< Mask for DCDC_CCIF */ +#define DCDC_CCIF_EM0OF (0x1UL << 0) /**< EM0 Counter Overflow */ +#define _DCDC_CCIF_EM0OF_SHIFT 0 /**< Shift value for DCDC_EM0OF */ +#define _DCDC_CCIF_EM0OF_MASK 0x1UL /**< Bit mask for DCDC_EM0OF */ +#define _DCDC_CCIF_EM0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM0OF_DEFAULT (_DCDC_CCIF_EM0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2OF (0x1UL << 1) /**< EM2 Counter Overflow */ +#define _DCDC_CCIF_EM2OF_SHIFT 1 /**< Shift value for DCDC_EM2OF */ +#define _DCDC_CCIF_EM2OF_MASK 0x2UL /**< Bit mask for DCDC_EM2OF */ +#define _DCDC_CCIF_EM2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2OF_DEFAULT (_DCDC_CCIF_EM2OF_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM0CMP (0x1UL << 2) /**< EM0 Counter Compare Match */ +#define _DCDC_CCIF_EM0CMP_SHIFT 2 /**< Shift value for DCDC_EM0CMP */ +#define _DCDC_CCIF_EM0CMP_MASK 0x4UL /**< Bit mask for DCDC_EM0CMP */ +#define _DCDC_CCIF_EM0CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM0CMP_DEFAULT (_DCDC_CCIF_EM0CMP_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2CMP (0x1UL << 3) /**< EM2 Counter Compare Match */ +#define _DCDC_CCIF_EM2CMP_SHIFT 3 /**< Shift value for DCDC_EM2CMP */ +#define _DCDC_CCIF_EM2CMP_MASK 0x8UL /**< Bit mask for DCDC_EM2CMP */ +#define _DCDC_CCIF_EM2CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ +#define DCDC_CCIF_EM2CMP_DEFAULT (_DCDC_CCIF_EM2CMP_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_CCIF */ + +/* Bit fields for DCDC CCIEN */ +#define _DCDC_CCIEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCIEN */ +#define _DCDC_CCIEN_MASK 0x0000000FUL /**< Mask for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0OF (0x1UL << 0) /**< Clmb Cntr EM0 Overflow Interrupt Enable */ +#define _DCDC_CCIEN_EM0OF_SHIFT 0 /**< Shift value for DCDC_EM0OF */ +#define _DCDC_CCIEN_EM0OF_MASK 0x1UL /**< Bit mask for DCDC_EM0OF */ +#define _DCDC_CCIEN_EM0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0OF_DEFAULT (_DCDC_CCIEN_EM0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2OF (0x1UL << 1) /**< Clmb Cntr EM2 Overflow Interrupt Enable */ +#define _DCDC_CCIEN_EM2OF_SHIFT 1 /**< Shift value for DCDC_EM2OF */ +#define _DCDC_CCIEN_EM2OF_MASK 0x2UL /**< Bit mask for DCDC_EM2OF */ +#define _DCDC_CCIEN_EM2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2OF_DEFAULT (_DCDC_CCIEN_EM2OF_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0CMP (0x1UL << 2) /**< Clmb Cntr EM0 Cmp Match Interrupt Enable */ +#define _DCDC_CCIEN_EM0CMP_SHIFT 2 /**< Shift value for DCDC_EM0CMP */ +#define _DCDC_CCIEN_EM0CMP_MASK 0x4UL /**< Bit mask for DCDC_EM0CMP */ +#define _DCDC_CCIEN_EM0CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM0CMP_DEFAULT (_DCDC_CCIEN_EM0CMP_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2CMP (0x1UL << 3) /**< Clmb Cntr EM2 Cmp Match Interrupt Enable */ +#define _DCDC_CCIEN_EM2CMP_SHIFT 3 /**< Shift value for DCDC_EM2CMP */ +#define _DCDC_CCIEN_EM2CMP_MASK 0x8UL /**< Bit mask for DCDC_EM2CMP */ +#define _DCDC_CCIEN_EM2CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ +#define DCDC_CCIEN_EM2CMP_DEFAULT (_DCDC_CCIEN_EM2CMP_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_CCIEN */ + +/* Bit fields for DCDC CCSTATUS */ +#define _DCDC_CCSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCSTATUS */ +#define _DCDC_CCSTATUS_MASK 0x00000003UL /**< Mask for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CLRBSY (0x1UL << 0) /**< Coulomb Counter Clear Busy */ +#define _DCDC_CCSTATUS_CLRBSY_SHIFT 0 /**< Shift value for DCDC_CLRBSY */ +#define _DCDC_CCSTATUS_CLRBSY_MASK 0x1UL /**< Bit mask for DCDC_CLRBSY */ +#define _DCDC_CCSTATUS_CLRBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CLRBSY_DEFAULT (_DCDC_CCSTATUS_CLRBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CCRUNNING (0x1UL << 1) /**< Coulomb Counter Running */ +#define _DCDC_CCSTATUS_CCRUNNING_SHIFT 1 /**< Shift value for DCDC_CCRUNNING */ +#define _DCDC_CCSTATUS_CCRUNNING_MASK 0x2UL /**< Bit mask for DCDC_CCRUNNING */ +#define _DCDC_CCSTATUS_CCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCSTATUS */ +#define DCDC_CCSTATUS_CCRUNNING_DEFAULT (_DCDC_CCSTATUS_CCRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCSTATUS */ + +/* Bit fields for DCDC LOCK */ +#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ +#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ + +/* Bit fields for DCDC LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ +#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ + +/** @} End of group EFR32MG29_DCDC_BitFields */ +/** @} End of group EFR32MG29_DCDC */ +/** @} End of group Parts */ + +#endif // EFR32MG29_DCDC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_devinfo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_devinfo.h new file mode 100644 index 000000000..f124cda1c --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_devinfo.h @@ -0,0 +1,954 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 DEVINFO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_DEVINFO_H +#define EFR32MG29_DEVINFO_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_DEVINFO DEVINFO + * @{ + * @brief EFR32MG29 DEVINFO Register Declaration. + *****************************************************************************/ + +/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ +typedef struct devinfo_hfrcodpllcal_typedef{ + __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ +} DEVINFO_HFRCODPLLCAL_TypeDef; + +/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ +typedef struct devinfo_hfrcoem23cal_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOEM23CAL_TypeDef; + +/** DEVINFO HFRCOSECAL Register Group Declaration. */ +typedef struct devinfo_hfrcosecal_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOSECAL_TypeDef; + +/** DEVINFO Register Declaration. */ +typedef struct devinfo_typedef{ + __IM uint32_t INFO; /**< DI Information */ + __IM uint32_t PART; /**< Part Info */ + __IM uint32_t MEMINFO; /**< Memory Info */ + __IM uint32_t MSIZE; /**< Memory Size */ + __IM uint32_t PKGINFO; /**< Misc Device Info */ + __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ + __IM uint32_t SWFIX; /**< SW Fix Register */ + __IM uint32_t SWCAPA0; /**< Software Restriction */ + __IM uint32_t SWCAPA1; /**< Software Restriction */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t EXTINFO; /**< External Component Info */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t EUI48L; /**< EUI 48 Low */ + __IM uint32_t EUI48H; /**< EUI 48 High */ + __IM uint32_t EUI64L; /**< EUI64 Low */ + __IM uint32_t EUI64H; /**< EUI64 High */ + __IM uint32_t CALTEMP; /**< Calibration temperature Information */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Sensor Calibration Information */ + DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ + DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ + DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ + __IM uint32_t MODULENAME0; /**< Module Name Information */ + __IM uint32_t MODULENAME1; /**< Module Name Information */ + __IM uint32_t MODULENAME2; /**< Module Name Information */ + __IM uint32_t MODULENAME3; /**< Module Name Information */ + __IM uint32_t MODULENAME4; /**< Module Name Information */ + __IM uint32_t MODULENAME5; /**< Module Name Information */ + __IM uint32_t MODULENAME6; /**< Module Name Information */ + __IM uint32_t MODULEINFO; /**< Module Information */ + __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ + __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ + __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ + uint32_t RESERVED4[24U]; /**< Reserved for future use */ + __IM uint32_t LEGACY; /**< Legacy Device Info */ + uint32_t RESERVED5[23U]; /**< Reserved for future use */ + __IM uint32_t RTHERM; /**< Thermistor Calibration */ + uint32_t RESERVED6[40U]; /**< Reserved for future use */ + __IM uint32_t CCLOAD10; /**< Current level 1 and 0 */ + __IM uint32_t CCLOAD32; /**< Current level 3 and 2 */ + __IM uint32_t CCLOAD54; /**< Current level 5 and 4 */ + __IM uint32_t CCLOAD76; /**< Current level 7 and 6 */ + uint32_t RESERVED7[36U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ +} DEVINFO_TypeDef; +/** @} End of group EFR32MG29_DEVINFO */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_DEVINFO + * @{ + * @defgroup EFR32MG29_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x14000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ +#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x00000014UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ +#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ + +/* Bit fields for DEVINFO PKGINFO */ +#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N20TO55 0x00000004UL /**< Mode N20TO55 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N20TO55 (_DEVINFO_PKGINFO_TEMPGRADE_N20TO55 << 0) /**< Shifted mode N20TO55 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ +#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ + +/* Bit fields for DEVINFO SWFIX */ +#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ +#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ + +/* Bit fields for DEVINFO SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_MASK 0x00333333UL /**< Mask for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ + +/* Bit fields for DEVINFO SWCAPA1 */ +#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ +#define _DEVINFO_SWCAPA1_MASK 0x00000007UL /**< Mask for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ +#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ +#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ +#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ + +/* Bit fields for DEVINFO EUI64L */ +#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ +#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ + +/* Bit fields for DEVINFO EUI64H */ +#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ + +/* Bit fields for DEVINFO CALTEMP */ +#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ +#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ +#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ + +/* Bit fields for DEVINFO HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ + +/* Bit fields for DEVINFO MODULENAME0 */ +#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ + +/* Bit fields for DEVINFO MODULENAME1 */ +#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ + +/* Bit fields for DEVINFO MODULENAME2 */ +#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ + +/* Bit fields for DEVINFO MODULENAME3 */ +#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ + +/* Bit fields for DEVINFO MODULENAME4 */ +#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ + +/* Bit fields for DEVINFO MODULENAME5 */ +#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ + +/* Bit fields for DEVINFO MODULENAME6 */ +#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ +#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ +#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ + +/* Bit fields for DEVINFO IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ + +/* Bit fields for DEVINFO IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ + +/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ + +/* Bit fields for DEVINFO LEGACY */ +#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ + +/* Bit fields for DEVINFO RTHERM */ +#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ +#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ + +/* Bit fields for DEVINFO CCLOAD10 */ +#define _DEVINFO_CCLOAD10_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD10 */ +#define _DEVINFO_CCLOAD10_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD10 */ +#define _DEVINFO_CCLOAD10_CCLOAD0_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD0 */ +#define _DEVINFO_CCLOAD10_CCLOAD0_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD0 */ +#define _DEVINFO_CCLOAD10_CCLOAD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD10 */ +#define DEVINFO_CCLOAD10_CCLOAD0_DEFAULT (_DEVINFO_CCLOAD10_CCLOAD0_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD10 */ +#define _DEVINFO_CCLOAD10_CCLOAD1_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD1 */ +#define _DEVINFO_CCLOAD10_CCLOAD1_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD1 */ +#define _DEVINFO_CCLOAD10_CCLOAD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD10 */ +#define DEVINFO_CCLOAD10_CCLOAD1_DEFAULT (_DEVINFO_CCLOAD10_CCLOAD1_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD10 */ + +/* Bit fields for DEVINFO CCLOAD32 */ +#define _DEVINFO_CCLOAD32_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD32 */ +#define _DEVINFO_CCLOAD32_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD32 */ +#define _DEVINFO_CCLOAD32_CCLOAD2_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD2 */ +#define _DEVINFO_CCLOAD32_CCLOAD2_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD2 */ +#define _DEVINFO_CCLOAD32_CCLOAD2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD32 */ +#define DEVINFO_CCLOAD32_CCLOAD2_DEFAULT (_DEVINFO_CCLOAD32_CCLOAD2_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD32 */ +#define _DEVINFO_CCLOAD32_CCLOAD3_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD3 */ +#define _DEVINFO_CCLOAD32_CCLOAD3_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD3 */ +#define _DEVINFO_CCLOAD32_CCLOAD3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD32 */ +#define DEVINFO_CCLOAD32_CCLOAD3_DEFAULT (_DEVINFO_CCLOAD32_CCLOAD3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD32 */ + +/* Bit fields for DEVINFO CCLOAD54 */ +#define _DEVINFO_CCLOAD54_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD54 */ +#define _DEVINFO_CCLOAD54_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD54 */ +#define _DEVINFO_CCLOAD54_CCLOAD4_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD4 */ +#define _DEVINFO_CCLOAD54_CCLOAD4_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD4 */ +#define _DEVINFO_CCLOAD54_CCLOAD4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD54 */ +#define DEVINFO_CCLOAD54_CCLOAD4_DEFAULT (_DEVINFO_CCLOAD54_CCLOAD4_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD54 */ +#define _DEVINFO_CCLOAD54_CCLOAD5_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD5 */ +#define _DEVINFO_CCLOAD54_CCLOAD5_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD5 */ +#define _DEVINFO_CCLOAD54_CCLOAD5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD54 */ +#define DEVINFO_CCLOAD54_CCLOAD5_DEFAULT (_DEVINFO_CCLOAD54_CCLOAD5_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD54 */ + +/* Bit fields for DEVINFO CCLOAD76 */ +#define _DEVINFO_CCLOAD76_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CCLOAD76 */ +#define _DEVINFO_CCLOAD76_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_CCLOAD76 */ +#define _DEVINFO_CCLOAD76_CCLOAD6_SHIFT 0 /**< Shift value for DEVINFO_CCLOAD6 */ +#define _DEVINFO_CCLOAD76_CCLOAD6_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CCLOAD6 */ +#define _DEVINFO_CCLOAD76_CCLOAD6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD76 */ +#define DEVINFO_CCLOAD76_CCLOAD6_DEFAULT (_DEVINFO_CCLOAD76_CCLOAD6_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD76 */ +#define _DEVINFO_CCLOAD76_CCLOAD7_SHIFT 16 /**< Shift value for DEVINFO_CCLOAD7 */ +#define _DEVINFO_CCLOAD76_CCLOAD7_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_CCLOAD7 */ +#define _DEVINFO_CCLOAD76_CCLOAD7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CCLOAD76 */ +#define DEVINFO_CCLOAD76_CCLOAD7_DEFAULT (_DEVINFO_CCLOAD76_CCLOAD7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CCLOAD76 */ + +/** @} End of group EFR32MG29_DEVINFO_BitFields */ +/** @} End of group EFR32MG29_DEVINFO */ +/** @} End of group Parts */ + +#endif // EFR32MG29_DEVINFO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dma_descriptor.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dma_descriptor.h new file mode 100644 index 000000000..b73022bf6 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dma_descriptor.h @@ -0,0 +1,59 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 DMA descriptor bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_DMA_DESCRIPTOR_H +#define EFR32MG29_DMA_DESCRIPTOR_H + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup DMA_DESCRIPTOR DMA Descriptor + * @{ + *****************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + +#endif // EFR32MG29_DMA_DESCRIPTOR_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dpll.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dpll.h new file mode 100644 index 000000000..c7fa6428b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_dpll.h @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 DPLL register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_DPLL_H +#define EFR32MG29_DPLL_H +#define DPLL_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_DPLL DPLL + * @{ + * @brief EFR32MG29 DPLL Register Declaration. + *****************************************************************************/ + +/** DPLL Register Declaration. */ +typedef struct dpll_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ +} DPLL_TypeDef; +/** @} End of group EFR32MG29_DPLL */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_DPLL + * @{ + * @defgroup EFR32MG29_DPLL_BitFields DPLL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DPLL IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ + +/* Bit fields for DPLL EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ + +/* Bit fields for DPLL CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ + +/* Bit fields for DPLL CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ + +/* Bit fields for DPLL IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ + +/* Bit fields for DPLL IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ + +/* Bit fields for DPLL STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ + +/* Bit fields for DPLL LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ + +/** @} End of group EFR32MG29_DPLL_BitFields */ +/** @} End of group EFR32MG29_DPLL */ +/** @} End of group Parts */ + +#endif // EFR32MG29_DPLL_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_emu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_emu.h new file mode 100644 index 000000000..4e2253c3c --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_emu.h @@ -0,0 +1,862 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 EMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_EMU_H +#define EFR32MG29_EMU_H +#define EMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_EMU EMU + * @{ + * @brief EFR32MG29 EMU Register Declaration. + *****************************************************************************/ + +/** EMU Register Declaration. */ +typedef struct emu_typedef{ + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL; /**< Boost Enable Control */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[27U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[926U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED17[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED19[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED23[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL_SET; /**< Boost Enable Control */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[27U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[926U]; /**< Reserved for future use */ + uint32_t RESERVED32[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED34[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED39[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL_CLR; /**< Boost Enable Control */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[27U]; /**< Reserved for future use */ + uint32_t RESERVED45[1U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[926U]; /**< Reserved for future use */ + uint32_t RESERVED48[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED49[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED50[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED51[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED52[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED55[5U]; /**< Reserved for future use */ + __IOM uint32_t BOOSTCTRL_TGL; /**< Boost Enable Control */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED58[2U]; /**< Reserved for future use */ + uint32_t RESERVED59[1U]; /**< Reserved for future use */ + uint32_t RESERVED60[27U]; /**< Reserved for future use */ + uint32_t RESERVED61[1U]; /**< Reserved for future use */ + uint32_t RESERVED62[1U]; /**< Reserved for future use */ +} EMU_TypeDef; +/** @} End of group EFR32MG29_EMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_EMU + * @{ + * @defgroup EFR32MG29_EMU_BitFields EMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ + +/* Bit fields for EMU BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ + +/* Bit fields for EMU VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ + +/* Bit fields for EMU PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN 0x00000000UL /**< Mode RETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN << 0) /**< Shifted mode RETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ + +/* Bit fields for EMU IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x0000000AUL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x0000000AUL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB370000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTPOSEDGE (0x1UL << 20) /**< BOOST_EN Rising Edge Interrupt flag */ +#define _EMU_IF_BOOSTPOSEDGE_SHIFT 20 /**< Shift value for EMU_BOOSTPOSEDGE */ +#define _EMU_IF_BOOSTPOSEDGE_MASK 0x100000UL /**< Bit mask for EMU_BOOSTPOSEDGE */ +#define _EMU_IF_BOOSTPOSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTPOSEDGE_DEFAULT (_EMU_IF_BOOSTPOSEDGE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTNEGEDGE (0x1UL << 21) /**< BOOST_EN Falling Edge Interrupt flag */ +#define _EMU_IF_BOOSTNEGEDGE_SHIFT 21 /**< Shift value for EMU_BOOSTNEGEDGE */ +#define _EMU_IF_BOOSTNEGEDGE_MASK 0x200000UL /**< Bit mask for EMU_BOOSTNEGEDGE */ +#define _EMU_IF_BOOSTNEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_BOOSTNEGEDGE_DEFAULT (_EMU_IF_BOOSTNEGEDGE_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB370000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTPOSEDGE (0x1UL << 20) /**< BOOST_EN Rising edge Interrupt enable */ +#define _EMU_IEN_BOOSTPOSEDGE_SHIFT 20 /**< Shift value for EMU_BOOSTPOSEDGE */ +#define _EMU_IEN_BOOSTPOSEDGE_MASK 0x100000UL /**< Bit mask for EMU_BOOSTPOSEDGE */ +#define _EMU_IEN_BOOSTPOSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTPOSEDGE_DEFAULT (_EMU_IEN_BOOSTPOSEDGE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTNEGEDGE (0x1UL << 21) /**< BOOST_EN Falling edge Interrupt enable */ +#define _EMU_IEN_BOOSTNEGEDGE_SHIFT 21 /**< Shift value for EMU_BOOSTNEGEDGE */ +#define _EMU_IEN_BOOSTNEGEDGE_MASK 0x200000UL /**< Bit mask for EMU_BOOSTNEGEDGE */ +#define _EMU_IEN_BOOSTNEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_BOOSTNEGEDGE_DEFAULT (_EMU_IEN_BOOSTNEGEDGE_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ +#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00007200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0017B09UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_HDREGEM2EXITCLIM (0x1UL << 11) /**< HDREG EM2 Exit current limit */ +#define _EMU_CTRL_HDREGEM2EXITCLIM_SHIFT 11 /**< Shift value for EMU_HDREGEM2EXITCLIM */ +#define _EMU_CTRL_HDREGEM2EXITCLIM_MASK 0x800UL /**< Bit mask for EMU_HDREGEM2EXITCLIM */ +#define _EMU_CTRL_HDREGEM2EXITCLIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_HDREGEM2EXITCLIM_DEFAULT (_EMU_CTRL_HDREGEM2EXITCLIM_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_SHIFT 12 /**< Shift value for EMU_HDREGSTOPGEAR */ +#define _EMU_CTRL_HDREGSTOPGEAR_MASK 0x7000UL /**< Bit mask for EMU_HDREGSTOPGEAR */ +#define _EMU_CTRL_HDREGSTOPGEAR_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA 0x00000000UL /**< Mode ILMT_4MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA 0x00000001UL /**< Mode ILMT_8MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA 0x00000002UL /**< Mode ILMT_12MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA 0x00000003UL /**< Mode ILMT_16MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA 0x00000004UL /**< Mode ILMT_24MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA 0x00000005UL /**< Mode ILMT_48MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA 0x00000006UL /**< Mode ILMT_64MA for EMU_CTRL */ +#define _EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX 0x00000007UL /**< Mode ILMT_MAX for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_DEFAULT (_EMU_CTRL_HDREGSTOPGEAR_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA << 12) /**< Shifted mode ILMT_4MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA << 12) /**< Shifted mode ILMT_8MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA << 12) /**< Shifted mode ILMT_12MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA << 12) /**< Shifted mode ILMT_16MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA << 12) /**< Shifted mode ILMT_24MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA << 12) /**< Shifted mode ILMT_48MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA (_EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA << 12) /**< Shifted mode ILMT_64MA for EMU_CTRL */ +#define EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX (_EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX << 12) /**< Shifted mode ILMT_MAX for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFE154FFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BOOSTENPIN (0x1UL << 16) /**< BOOST_EN pin status */ +#define _EMU_STATUS_BOOSTENPIN_SHIFT 16 /**< Shift value for EMU_BOOSTENPIN */ +#define _EMU_STATUS_BOOSTENPIN_MASK 0x10000UL /**< Bit mask for EMU_BOOSTENPIN */ +#define _EMU_STATUS_BOOSTENPIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_BOOSTENPIN_DEFAULT (_EMU_STATUS_BOOSTENPIN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00070407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC007C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE (0x1UL << 16) /**< DCI System reset */ +#define _EMU_RSTCTRL_DCIRMODE_SHIFT 16 /**< Shift value for EMU_DCIRMODE */ +#define _EMU_RSTCTRL_DCIRMODE_MASK 0x10000UL /**< Bit mask for EMU_DCIRMODE */ +#define _EMU_RSTCTRL_DCIRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DCIRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DCIRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_DEFAULT (_EMU_RSTCTRL_DCIRMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_DISABLED (_EMU_RSTCTRL_DCIRMODE_DISABLED << 16) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_ENABLED (_EMU_RSTCTRL_DCIRMODE_ENABLED << 16) /**< Shifted mode ENABLED for EMU_RSTCTRL */ + +/* Bit fields for EMU RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8017FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ +#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DCI (0x1UL << 16) /**< DCI reset */ +#define _EMU_RSTCAUSE_DCI_SHIFT 16 /**< Shift value for EMU_DCI */ +#define _EMU_RSTCAUSE_DCI_MASK 0x10000UL /**< Bit mask for EMU_DCI */ +#define _EMU_RSTCAUSE_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DCI_DEFAULT (_EMU_RSTCAUSE_DCI_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_BOOSTON (0x1UL << 20) /**< BOOST_EN pin reset */ +#define _EMU_RSTCAUSE_BOOSTON_SHIFT 20 /**< Shift value for EMU_BOOSTON */ +#define _EMU_RSTCAUSE_BOOSTON_MASK 0x100000UL /**< Bit mask for EMU_BOOSTON */ +#define _EMU_RSTCAUSE_BOOSTON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_BOOSTON_DEFAULT (_EMU_RSTCAUSE_BOOSTON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ + +/* Bit fields for EMU TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ + +/* Bit fields for EMU DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ + +/* Bit fields for EMU DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ + +/* Bit fields for EMU BOOSTCTRL */ +#define _EMU_BOOSTCTRL_RESETVALUE 0x00000001UL /**< Default value for EMU_BOOSTCTRL */ +#define _EMU_BOOSTCTRL_MASK 0x00000001UL /**< Mask for EMU_BOOSTCTRL */ +#define EMU_BOOSTCTRL_BOOSTENCTRL (0x1UL << 0) /**< BOOST_EN Control */ +#define _EMU_BOOSTCTRL_BOOSTENCTRL_SHIFT 0 /**< Shift value for EMU_BOOSTENCTRL */ +#define _EMU_BOOSTCTRL_BOOSTENCTRL_MASK 0x1UL /**< Bit mask for EMU_BOOSTENCTRL */ +#define _EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BOOSTCTRL */ +#define EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT (_EMU_BOOSTCTRL_BOOSTENCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOOSTCTRL */ + +/* Bit fields for EMU EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ + +/* Bit fields for EMU EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ + +/** @} End of group EFR32MG29_EMU_BitFields */ +/** @} End of group EFR32MG29_EMU */ +/** @} End of group Parts */ + +#endif // EFR32MG29_EMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_etampdet.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_etampdet.h new file mode 100644 index 000000000..e2089a721 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_etampdet.h @@ -0,0 +1,646 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 ETAMPDET register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_ETAMPDET_H +#define EFR32MG29_ETAMPDET_H +#define ETAMPDET_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_ETAMPDET ETAMPDET + * @{ + * @brief EFR32MG29 ETAMPDET Register Declaration. + *****************************************************************************/ + +/** ETAMPDET Register Declaration. */ +typedef struct etampdet_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE; /**< Filter moving window size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL; /**< Prescaler Ctrl Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED2[1005U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX_SET; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE_SET; /**< Filter moving window size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0_SET; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1_SET; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL_SET; /**< Prescaler Ctrl Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED5[1005U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX_CLR; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE_CLR; /**< Filter moving window size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0_CLR; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1_CLR; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL_CLR; /**< Prescaler Ctrl Register */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED8[1005U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CNTMISMATCHMAX_TGL; /**< Filter Threshold Register */ + __IOM uint32_t CHNLFILTWINSIZE_TGL; /**< Filter moving window size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IOM uint32_t CHNLSEEDVAL0_TGL; /**< CHNL0 LFSR Seed Ctrl Register */ + __IOM uint32_t CHNLSEEDVAL1_TGL; /**< CHNL1 LFSR Seed Ctrl Register */ + __IOM uint32_t CLKPRESCVAL_TGL; /**< Prescaler Ctrl Register */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} ETAMPDET_TypeDef; +/** @} End of group EFR32MG29_ETAMPDET */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_ETAMPDET + * @{ + * @defgroup EFR32MG29_ETAMPDET_BitFields ETAMPDET Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ETAMPDET IPVERSION */ +#define _ETAMPDET_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ETAMPDET_IPVERSION */ +#define _ETAMPDET_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETAMPDET_IPVERSION */ +#define ETAMPDET_IPVERSION_IPVERSION_DEFAULT (_ETAMPDET_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_IPVERSION */ + +/* Bit fields for ETAMPDET EN */ +#define _ETAMPDET_EN_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_EN */ +#define _ETAMPDET_EN_MASK 0x00000001UL /**< Mask for ETAMPDET_EN */ +#define ETAMPDET_EN_EN (0x1UL << 0) /**< ETAMPDET Enable */ +#define _ETAMPDET_EN_EN_SHIFT 0 /**< Shift value for ETAMPDET_EN */ +#define _ETAMPDET_EN_EN_MASK 0x1UL /**< Bit mask for ETAMPDET_EN */ +#define _ETAMPDET_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_EN */ +#define ETAMPDET_EN_EN_DEFAULT (_ETAMPDET_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_EN */ + +/* Bit fields for ETAMPDET CFG */ +#define _ETAMPDET_CFG_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_MASK 0x0000003FUL /**< Mask for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0 (0x1UL << 0) /**< enable delay for comparison */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLCMPDLYEN0 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLCMPDLYEN0 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_X0 0x00000000UL /**< Mode X0 for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN0_X1 0x00000001UL /**< Mode X1 for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0_DEFAULT (_ETAMPDET_CFG_CHNLCMPDLYEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0_X0 (_ETAMPDET_CFG_CHNLCMPDLYEN0_X0 << 0) /**< Shifted mode X0 for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN0_X1 (_ETAMPDET_CFG_CHNLCMPDLYEN0_X1 << 0) /**< Shifted mode X1 for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0 (0x1UL << 1) /**< enable detect filtering */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_SHIFT 1 /**< Shift value for ETAMPDET_CHNLTAMPDETFILTEN0 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLTAMPDETFILTEN0 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN0_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DEFAULT (_ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DISABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN0_DISABLE << 1) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN0_ENABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN0_ENABLE << 1) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0 (0x1UL << 2) /**< enable driving pad */ +#define _ETAMPDET_CFG_CHNLPADEN0_SHIFT 2 /**< Shift value for ETAMPDET_CHNLPADEN0 */ +#define _ETAMPDET_CFG_CHNLPADEN0_MASK 0x4UL /**< Bit mask for ETAMPDET_CHNLPADEN0 */ +#define _ETAMPDET_CFG_CHNLPADEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN0_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN0_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0_DEFAULT (_ETAMPDET_CFG_CHNLPADEN0_DEFAULT << 2) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0_DISABLE (_ETAMPDET_CFG_CHNLPADEN0_DISABLE << 2) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN0_ENABLE (_ETAMPDET_CFG_CHNLPADEN0_ENABLE << 2) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1 (0x1UL << 3) /**< enable delay for comparison */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLCMPDLYEN1 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_MASK 0x8UL /**< Bit mask for ETAMPDET_CHNLCMPDLYEN1 */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLCMPDLYEN1_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1_DEFAULT (_ETAMPDET_CFG_CHNLCMPDLYEN1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1_DISABLE (_ETAMPDET_CFG_CHNLCMPDLYEN1_DISABLE << 3) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLCMPDLYEN1_ENABLE (_ETAMPDET_CFG_CHNLCMPDLYEN1_ENABLE << 3) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1 (0x1UL << 4) /**< enable detect filtering */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLTAMPDETFILTEN1 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_MASK 0x10UL /**< Bit mask for ETAMPDET_CHNLTAMPDETFILTEN1 */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLTAMPDETFILTEN1_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DEFAULT (_ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DISABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN1_DISABLE << 4) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLTAMPDETFILTEN1_ENABLE (_ETAMPDET_CFG_CHNLTAMPDETFILTEN1_ENABLE << 4) /**< Shifted mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1 (0x1UL << 5) /**< enable driving pad */ +#define _ETAMPDET_CFG_CHNLPADEN1_SHIFT 5 /**< Shift value for ETAMPDET_CHNLPADEN1 */ +#define _ETAMPDET_CFG_CHNLPADEN1_MASK 0x20UL /**< Bit mask for ETAMPDET_CHNLPADEN1 */ +#define _ETAMPDET_CFG_CHNLPADEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN1_DISABLE 0x00000000UL /**< Mode DISABLE for ETAMPDET_CFG */ +#define _ETAMPDET_CFG_CHNLPADEN1_ENABLE 0x00000001UL /**< Mode ENABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1_DEFAULT (_ETAMPDET_CFG_CHNLPADEN1_DEFAULT << 5) /**< Shifted mode DEFAULT for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1_DISABLE (_ETAMPDET_CFG_CHNLPADEN1_DISABLE << 5) /**< Shifted mode DISABLE for ETAMPDET_CFG */ +#define ETAMPDET_CFG_CHNLPADEN1_ENABLE (_ETAMPDET_CFG_CHNLPADEN1_ENABLE << 5) /**< Shifted mode ENABLE for ETAMPDET_CFG */ + +/* Bit fields for ETAMPDET CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_MASK 0x0000003FUL /**< Mask for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLCNTMISMATCHMAX0*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_MASK 0x7UL /**< Bit mask for ETAMPDET_CHNLCNTMISMATCHMAX0 */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold1 0x00000000UL /**< Mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold2 0x00000001UL /**< Mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold3 0x00000002UL /**< Mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold4 0x00000003UL /**< Mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold5 0x00000004UL /**< Mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold6 0x00000005UL /**< Mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold7 0x00000006UL /**< Mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold8 0x00000007UL /**< Mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DEFAULT (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold1 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold1 << 0) /**< Shifted mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold2 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold2 << 0) /**< Shifted mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold3 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold3 << 0) /**< Shifted mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold4 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold4 << 0) /**< Shifted mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold5 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold5 << 0) /**< Shifted mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold6 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold6 << 0) /**< Shifted mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold7 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold7 << 0) /**< Shifted mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold8 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX0_DetectFilterThreshold8 << 0) /**< Shifted mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLCNTMISMATCHMAX1*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_MASK 0x38UL /**< Bit mask for ETAMPDET_CHNLCNTMISMATCHMAX1 */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CNTMISMATCHMAX */ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold1 0x00000000UL /**< Mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold2 0x00000001UL /**< Mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold3 0x00000002UL /**< Mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold4 0x00000003UL /**< Mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold5 0x00000004UL /**< Mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold6 0x00000005UL /**< Mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold7 0x00000006UL /**< Mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define _ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold8 0x00000007UL /**< Mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DEFAULT (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold1 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold1 << 3) /**< Shifted mode DetectFilterThreshold1 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold2 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold2 << 3) /**< Shifted mode DetectFilterThreshold2 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold3 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold3 << 3) /**< Shifted mode DetectFilterThreshold3 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold4 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold4 << 3) /**< Shifted mode DetectFilterThreshold4 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold5 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold5 << 3) /**< Shifted mode DetectFilterThreshold5 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold6 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold6 << 3) /**< Shifted mode DetectFilterThreshold6 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold7 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold7 << 3) /**< Shifted mode DetectFilterThreshold7 for ETAMPDET_CNTMISMATCHMAX*/ +#define ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold8 (_ETAMPDET_CNTMISMATCHMAX_CHNLCNTMISMATCHMAX1_DetectFilterThreshold8 << 3) /**< Shifted mode DetectFilterThreshold8 for ETAMPDET_CNTMISMATCHMAX*/ + +/* Bit fields for ETAMPDET CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_MASK 0x000000FFUL /**< Mask for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLFILTWINSIZE0 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_MASK 0xFUL /**< Bit mask for ETAMPDET_CHNLFILTWINSIZE0 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_Reserved 0x00000000UL /**< Mode Reserved for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize2 0x00000001UL /**< Mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize3 0x00000002UL /**< Mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize4 0x00000003UL /**< Mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize5 0x00000004UL /**< Mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize6 0x00000005UL /**< Mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize7 0x00000006UL /**< Mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize8 0x00000007UL /**< Mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize9 0x00000008UL /**< Mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize10 0x00000009UL /**< Mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize11 0x0000000AUL /**< Mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize12 0x0000000BUL /**< Mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize13 0x0000000CUL /**< Mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize14 0x0000000DUL /**< Mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize15 0x0000000EUL /**< Mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize16 0x0000000FUL /**< Mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DEFAULT (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_Reserved (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_Reserved << 0) /**< Shifted mode Reserved for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize2 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize2 << 0) /**< Shifted mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize3 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize3 << 0) /**< Shifted mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize4 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize4 << 0) /**< Shifted mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize5 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize5 << 0) /**< Shifted mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize6 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize6 << 0) /**< Shifted mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize7 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize7 << 0) /**< Shifted mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize8 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize8 << 0) /**< Shifted mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize9 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize9 << 0) /**< Shifted mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize10 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize10 << 0) /**< Shifted mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize11 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize11 << 0) /**< Shifted mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize12 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize12 << 0) /**< Shifted mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize13 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize13 << 0) /**< Shifted mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize14 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize14 << 0) /**< Shifted mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize15 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize15 << 0) /**< Shifted mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize16 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE0_DetectFilterMovingWinSize16 << 0) /**< Shifted mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLFILTWINSIZE1 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_MASK 0xF0UL /**< Bit mask for ETAMPDET_CHNLFILTWINSIZE1 */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_Reserved 0x00000000UL /**< Mode Reserved for ETAMPDET_CHNLFILTWINSIZE */ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize2 0x00000001UL /**< Mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize3 0x00000002UL /**< Mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize4 0x00000003UL /**< Mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize5 0x00000004UL /**< Mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize6 0x00000005UL /**< Mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize7 0x00000006UL /**< Mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize8 0x00000007UL /**< Mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize9 0x00000008UL /**< Mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize10 0x00000009UL /**< Mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize11 0x0000000AUL /**< Mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize12 0x0000000BUL /**< Mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize13 0x0000000CUL /**< Mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize14 0x0000000DUL /**< Mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize15 0x0000000EUL /**< Mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define _ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize16 0x0000000FUL /**< Mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DEFAULT (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_Reserved (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_Reserved << 4) /**< Shifted mode Reserved for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize2 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize2 << 4) /**< Shifted mode DetectFilterMovingWinSize2 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize3 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize3 << 4) /**< Shifted mode DetectFilterMovingWinSize3 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize4 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize4 << 4) /**< Shifted mode DetectFilterMovingWinSize4 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize5 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize5 << 4) /**< Shifted mode DetectFilterMovingWinSize5 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize6 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize6 << 4) /**< Shifted mode DetectFilterMovingWinSize6 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize7 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize7 << 4) /**< Shifted mode DetectFilterMovingWinSize7 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize8 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize8 << 4) /**< Shifted mode DetectFilterMovingWinSize8 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize9 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize9 << 4) /**< Shifted mode DetectFilterMovingWinSize9 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize10 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize10 << 4) /**< Shifted mode DetectFilterMovingWinSize10 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize11 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize11 << 4) /**< Shifted mode DetectFilterMovingWinSize11 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize12 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize12 << 4) /**< Shifted mode DetectFilterMovingWinSize12 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize13 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize13 << 4) /**< Shifted mode DetectFilterMovingWinSize13 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize14 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize14 << 4) /**< Shifted mode DetectFilterMovingWinSize14 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize15 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize15 << 4) /**< Shifted mode DetectFilterMovingWinSize15 for ETAMPDET_CHNLFILTWINSIZE*/ +#define ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize16 (_ETAMPDET_CHNLFILTWINSIZE_CHNLFILTWINSIZE1_DetectFilterMovingWinSize16 << 4) /**< Shifted mode DetectFilterMovingWinSize16 for ETAMPDET_CHNLFILTWINSIZE*/ + +/* Bit fields for ETAMPDET CMD */ +#define _ETAMPDET_CMD_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CMD */ +#define _ETAMPDET_CMD_MASK 0x0000003FUL /**< Mask for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART0 (0x1UL << 0) /**< Start channel 0 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTART0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_CMD_CHNLSTART0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_CMD_CHNLSTART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART0_DEFAULT (_ETAMPDET_CMD_CHNLSTART0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP0 (0x1UL << 1) /**< Stop channel 0 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTOP0_SHIFT 1 /**< Shift value for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_CMD_CHNLSTOP0_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_CMD_CHNLSTOP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP0_DEFAULT (_ETAMPDET_CMD_CHNLSTOP0_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD0 (0x1UL << 2) /**< Start channel 0 tamper detection */ +#define _ETAMPDET_CMD_CHNLLOAD0_SHIFT 2 /**< Shift value for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_CMD_CHNLLOAD0_MASK 0x4UL /**< Bit mask for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_CMD_CHNLLOAD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD0_DEFAULT (_ETAMPDET_CMD_CHNLLOAD0_DEFAULT << 2) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART1 (0x1UL << 3) /**< Start channel 1 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTART1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_CMD_CHNLSTART1_MASK 0x8UL /**< Bit mask for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_CMD_CHNLSTART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTART1_DEFAULT (_ETAMPDET_CMD_CHNLSTART1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP1 (0x1UL << 4) /**< Stop channel 1 tamper detection */ +#define _ETAMPDET_CMD_CHNLSTOP1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_CMD_CHNLSTOP1_MASK 0x10UL /**< Bit mask for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_CMD_CHNLSTOP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLSTOP1_DEFAULT (_ETAMPDET_CMD_CHNLSTOP1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD1 (0x1UL << 5) /**< Start channel 1 tamper detection */ +#define _ETAMPDET_CMD_CHNLLOAD1_SHIFT 5 /**< Shift value for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_CMD_CHNLLOAD1_MASK 0x20UL /**< Bit mask for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_CMD_CHNLLOAD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CMD */ +#define ETAMPDET_CMD_CHNLLOAD1_DEFAULT (_ETAMPDET_CMD_CHNLLOAD1_DEFAULT << 5) /**< Shifted mode DEFAULT for ETAMPDET_CMD */ + +/* Bit fields for ETAMPDET SYNCBUSY */ +#define _ETAMPDET_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_SYNCBUSY */ +#define _ETAMPDET_SYNCBUSY_MASK 0x0000007FUL /**< Mask for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART0 (0x1UL << 0) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLSTART0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART0_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTART0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP0 (0x1UL << 1) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP0_SHIFT 1 /**< Shift value for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP0_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLSTOP0 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP0_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTOP0_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD0 (0x1UL << 2) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD0_SHIFT 2 /**< Shift value for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD0_MASK 0x4UL /**< Bit mask for ETAMPDET_CHNLLOAD0 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD0_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLLOAD0_DEFAULT << 2) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART1 (0x1UL << 3) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART1_SHIFT 3 /**< Shift value for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART1_MASK 0x8UL /**< Bit mask for ETAMPDET_CHNLSTART1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTART1_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTART1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP1 (0x1UL << 4) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP1_SHIFT 4 /**< Shift value for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP1_MASK 0x10UL /**< Bit mask for ETAMPDET_CHNLSTOP1 */ +#define _ETAMPDET_SYNCBUSY_CHNLSTOP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLSTOP1_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLSTOP1_DEFAULT << 4) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD1 (0x1UL << 5) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD1_SHIFT 5 /**< Shift value for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD1_MASK 0x20UL /**< Bit mask for ETAMPDET_CHNLLOAD1 */ +#define _ETAMPDET_SYNCBUSY_CHNLLOAD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_CHNLLOAD1_DEFAULT (_ETAMPDET_SYNCBUSY_CHNLLOAD1_DEFAULT << 5) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_EN (0x1UL << 6) /**< Synchronizer busy status */ +#define _ETAMPDET_SYNCBUSY_EN_SHIFT 6 /**< Shift value for ETAMPDET_EN */ +#define _ETAMPDET_SYNCBUSY_EN_MASK 0x40UL /**< Bit mask for ETAMPDET_EN */ +#define _ETAMPDET_SYNCBUSY_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_SYNCBUSY */ +#define ETAMPDET_SYNCBUSY_EN_DEFAULT (_ETAMPDET_SYNCBUSY_EN_DEFAULT << 6) /**< Shifted mode DEFAULT for ETAMPDET_SYNCBUSY */ + +/* Bit fields for ETAMPDET IEN */ +#define _ETAMPDET_IEN_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_IEN */ +#define _ETAMPDET_IEN_MASK 0x00000003UL /**< Mask for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET0 (0x1UL << 0) /**< TAMPDET0 interrupt enable */ +#define _ETAMPDET_IEN_TAMPDET0_SHIFT 0 /**< Shift value for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IEN_TAMPDET0_MASK 0x1UL /**< Bit mask for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IEN_TAMPDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET0_DEFAULT (_ETAMPDET_IEN_TAMPDET0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET1 (0x1UL << 1) /**< TAMPDET1 interrupt enable */ +#define _ETAMPDET_IEN_TAMPDET1_SHIFT 1 /**< Shift value for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IEN_TAMPDET1_MASK 0x2UL /**< Bit mask for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IEN_TAMPDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IEN */ +#define ETAMPDET_IEN_TAMPDET1_DEFAULT (_ETAMPDET_IEN_TAMPDET1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_IEN */ + +/* Bit fields for ETAMPDET IF */ +#define _ETAMPDET_IF_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_IF */ +#define _ETAMPDET_IF_MASK 0x00000003UL /**< Mask for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET0 (0x1UL << 0) /**< Tamper0 Detect Flag */ +#define _ETAMPDET_IF_TAMPDET0_SHIFT 0 /**< Shift value for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IF_TAMPDET0_MASK 0x1UL /**< Bit mask for ETAMPDET_TAMPDET0 */ +#define _ETAMPDET_IF_TAMPDET0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET0_DEFAULT (_ETAMPDET_IF_TAMPDET0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET1 (0x1UL << 1) /**< Tamper1 Detect Flag */ +#define _ETAMPDET_IF_TAMPDET1_SHIFT 1 /**< Shift value for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IF_TAMPDET1_MASK 0x2UL /**< Bit mask for ETAMPDET_TAMPDET1 */ +#define _ETAMPDET_IF_TAMPDET1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_IF */ +#define ETAMPDET_IF_TAMPDET1_DEFAULT (_ETAMPDET_IF_TAMPDET1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_IF */ + +/* Bit fields for ETAMPDET STATUS */ +#define _ETAMPDET_STATUS_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_STATUS */ +#define _ETAMPDET_STATUS_MASK 0x80000003UL /**< Mask for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING0 (0x1UL << 0) /**< Channel0 Running Status */ +#define _ETAMPDET_STATUS_CHNLRUNNING0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLRUNNING0 */ +#define _ETAMPDET_STATUS_CHNLRUNNING0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLRUNNING0 */ +#define _ETAMPDET_STATUS_CHNLRUNNING0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING0_DEFAULT (_ETAMPDET_STATUS_CHNLRUNNING0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING1 (0x1UL << 1) /**< Channel1 Running Status */ +#define _ETAMPDET_STATUS_CHNLRUNNING1_SHIFT 1 /**< Shift value for ETAMPDET_CHNLRUNNING1 */ +#define _ETAMPDET_STATUS_CHNLRUNNING1_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLRUNNING1 */ +#define _ETAMPDET_STATUS_CHNLRUNNING1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_CHNLRUNNING1_DEFAULT (_ETAMPDET_STATUS_CHNLRUNNING1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS (0x1UL << 31) /**< Lock Status */ +#define _ETAMPDET_STATUS_LOCKSTATUS_SHIFT 31 /**< Shift value for ETAMPDET_LOCKSTATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_MASK 0x80000000UL /**< Bit mask for ETAMPDET_LOCKSTATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_STATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for ETAMPDET_STATUS */ +#define _ETAMPDET_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS_DEFAULT (_ETAMPDET_STATUS_LOCKSTATUS_DEFAULT << 31) /**< Shifted mode DEFAULT for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS_UNLOCKED (_ETAMPDET_STATUS_LOCKSTATUS_UNLOCKED << 31) /**< Shifted mode UNLOCKED for ETAMPDET_STATUS */ +#define ETAMPDET_STATUS_LOCKSTATUS_LOCKED (_ETAMPDET_STATUS_LOCKSTATUS_LOCKED << 31) /**< Shifted mode LOCKED for ETAMPDET_STATUS */ + +/* Bit fields for ETAMPDET EM4WUEN */ +#define _ETAMPDET_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_EM4WUEN */ +#define _ETAMPDET_EM4WUEN_MASK 0x00000003UL /**< Mask for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN0 (0x1UL << 0) /**< Channel0 Tampdet EM4 Wakeup Enable */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLEM4WUEN0 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN0_MASK 0x1UL /**< Bit mask for ETAMPDET_CHNLEM4WUEN0 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN0_DEFAULT (_ETAMPDET_EM4WUEN_CHNLEM4WUEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN1 (0x1UL << 1) /**< Channel1 Tampdet EM4 Wakeup Enable */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN1_SHIFT 1 /**< Shift value for ETAMPDET_CHNLEM4WUEN1 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN1_MASK 0x2UL /**< Bit mask for ETAMPDET_CHNLEM4WUEN1 */ +#define _ETAMPDET_EM4WUEN_CHNLEM4WUEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_EM4WUEN */ +#define ETAMPDET_EM4WUEN_CHNLEM4WUEN1_DEFAULT (_ETAMPDET_EM4WUEN_CHNLEM4WUEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for ETAMPDET_EM4WUEN */ + +/* Bit fields for ETAMPDET CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_MASK 0xFFFFFFFFUL /**< Mask for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_MASK 0xFFFFFFFFUL /**< Bit mask for ETAMPDET_CHNLSEEDVAL0 */ +#define _ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLSEEDVAL0 */ +#define ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_DEFAULT (_ETAMPDET_CHNLSEEDVAL0_CHNLSEEDVAL0_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CHNLSEEDVAL0*/ + +/* Bit fields for ETAMPDET CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_MASK 0xFFFFFFFFUL /**< Mask for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_SHIFT 0 /**< Shift value for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_MASK 0xFFFFFFFFUL /**< Bit mask for ETAMPDET_CHNLSEEDVAL1 */ +#define _ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CHNLSEEDVAL1 */ +#define ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_DEFAULT (_ETAMPDET_CHNLSEEDVAL1_CHNLSEEDVAL1_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CHNLSEEDVAL1*/ + +/* Bit fields for ETAMPDET CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_RESETVALUE 0x00000000UL /**< Default value for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_MASK 0x0000073FUL /**< Mask for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_SHIFT 0 /**< Shift value for ETAMPDET_LOWERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_MASK 0x3FUL /**< Bit mask for ETAMPDET_LOWERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_Bypass 0x00000000UL /**< Mode Bypass for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy2 0x00000001UL /**< Mode DivideBy2 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy3 0x00000002UL /**< Mode DivideBy3 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy4 0x00000003UL /**< Mode DivideBy4 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy5 0x00000004UL /**< Mode DivideBy5 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy6 0x00000005UL /**< Mode DivideBy6 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy7 0x00000006UL /**< Mode DivideBy7 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy8 0x00000007UL /**< Mode DivideBy8 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy9 0x00000008UL /**< Mode DivideBy9 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy10 0x00000009UL /**< Mode DivideBy10 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy11 0x0000000AUL /**< Mode DivideBy11 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy12 0x0000000BUL /**< Mode DivideBy12 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy13 0x0000000CUL /**< Mode DivideBy13 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy14 0x0000000DUL /**< Mode DivideBy14 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy15 0x0000000EUL /**< Mode DivideBy15 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy16 0x0000000FUL /**< Mode DivideBy16 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy17 0x00000010UL /**< Mode DivideBy17 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy18 0x00000011UL /**< Mode DivideBy18 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy19 0x00000012UL /**< Mode DivideBy19 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy20 0x00000013UL /**< Mode DivideBy20 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy21 0x00000014UL /**< Mode DivideBy21 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy22 0x00000015UL /**< Mode DivideBy22 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy23 0x00000016UL /**< Mode DivideBy23 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy24 0x00000017UL /**< Mode DivideBy24 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy25 0x00000018UL /**< Mode DivideBy25 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy26 0x00000019UL /**< Mode DivideBy26 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy27 0x0000001AUL /**< Mode DivideBy27 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy28 0x0000001BUL /**< Mode DivideBy28 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy29 0x0000001CUL /**< Mode DivideBy29 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy30 0x0000001DUL /**< Mode DivideBy30 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy31 0x0000001EUL /**< Mode DivideBy31 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy32 0x0000001FUL /**< Mode DivideBy32 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy33 0x00000020UL /**< Mode DivideBy33 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy34 0x00000021UL /**< Mode DivideBy34 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy35 0x00000022UL /**< Mode DivideBy35 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy36 0x00000023UL /**< Mode DivideBy36 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy37 0x00000024UL /**< Mode DivideBy37 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy38 0x00000025UL /**< Mode DivideBy38 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy39 0x00000026UL /**< Mode DivideBy39 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy40 0x00000027UL /**< Mode DivideBy40 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy41 0x00000028UL /**< Mode DivideBy41 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy42 0x00000029UL /**< Mode DivideBy42 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy43 0x0000002AUL /**< Mode DivideBy43 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy44 0x0000002BUL /**< Mode DivideBy44 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy45 0x0000002CUL /**< Mode DivideBy45 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy46 0x0000002DUL /**< Mode DivideBy46 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy47 0x0000002EUL /**< Mode DivideBy47 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy48 0x0000002FUL /**< Mode DivideBy48 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy49 0x00000030UL /**< Mode DivideBy49 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy50 0x00000031UL /**< Mode DivideBy50 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy51 0x00000032UL /**< Mode DivideBy51 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy52 0x00000033UL /**< Mode DivideBy52 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy53 0x00000034UL /**< Mode DivideBy53 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy54 0x00000035UL /**< Mode DivideBy54 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy55 0x00000036UL /**< Mode DivideBy55 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy56 0x00000037UL /**< Mode DivideBy56 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy57 0x00000038UL /**< Mode DivideBy57 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy58 0x00000039UL /**< Mode DivideBy58 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy59 0x0000003AUL /**< Mode DivideBy59 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy60 0x0000003BUL /**< Mode DivideBy60 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy61 0x0000003CUL /**< Mode DivideBy61 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy62 0x0000003DUL /**< Mode DivideBy62 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy63 0x0000003EUL /**< Mode DivideBy63 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy64 0x0000003FUL /**< Mode DivideBy64 for ETAMPDET_CLKPRESCVAL */ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DEFAULT (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_Bypass (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_Bypass << 0) /**< Shifted mode Bypass for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy2 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy2 << 0) /**< Shifted mode DivideBy2 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy3 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy3 << 0) /**< Shifted mode DivideBy3 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy4 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy4 << 0) /**< Shifted mode DivideBy4 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy5 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy5 << 0) /**< Shifted mode DivideBy5 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy6 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy6 << 0) /**< Shifted mode DivideBy6 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy7 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy7 << 0) /**< Shifted mode DivideBy7 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy8 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy8 << 0) /**< Shifted mode DivideBy8 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy9 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy9 << 0) /**< Shifted mode DivideBy9 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy10 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy10 << 0) /**< Shifted mode DivideBy10 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy11 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy11 << 0) /**< Shifted mode DivideBy11 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy12 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy12 << 0) /**< Shifted mode DivideBy12 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy13 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy13 << 0) /**< Shifted mode DivideBy13 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy14 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy14 << 0) /**< Shifted mode DivideBy14 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy15 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy15 << 0) /**< Shifted mode DivideBy15 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy16 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy16 << 0) /**< Shifted mode DivideBy16 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy17 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy17 << 0) /**< Shifted mode DivideBy17 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy18 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy18 << 0) /**< Shifted mode DivideBy18 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy19 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy19 << 0) /**< Shifted mode DivideBy19 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy20 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy20 << 0) /**< Shifted mode DivideBy20 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy21 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy21 << 0) /**< Shifted mode DivideBy21 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy22 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy22 << 0) /**< Shifted mode DivideBy22 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy23 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy23 << 0) /**< Shifted mode DivideBy23 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy24 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy24 << 0) /**< Shifted mode DivideBy24 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy25 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy25 << 0) /**< Shifted mode DivideBy25 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy26 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy26 << 0) /**< Shifted mode DivideBy26 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy27 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy27 << 0) /**< Shifted mode DivideBy27 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy28 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy28 << 0) /**< Shifted mode DivideBy28 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy29 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy29 << 0) /**< Shifted mode DivideBy29 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy30 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy30 << 0) /**< Shifted mode DivideBy30 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy31 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy31 << 0) /**< Shifted mode DivideBy31 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy32 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy32 << 0) /**< Shifted mode DivideBy32 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy33 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy33 << 0) /**< Shifted mode DivideBy33 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy34 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy34 << 0) /**< Shifted mode DivideBy34 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy35 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy35 << 0) /**< Shifted mode DivideBy35 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy36 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy36 << 0) /**< Shifted mode DivideBy36 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy37 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy37 << 0) /**< Shifted mode DivideBy37 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy38 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy38 << 0) /**< Shifted mode DivideBy38 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy39 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy39 << 0) /**< Shifted mode DivideBy39 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy40 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy40 << 0) /**< Shifted mode DivideBy40 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy41 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy41 << 0) /**< Shifted mode DivideBy41 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy42 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy42 << 0) /**< Shifted mode DivideBy42 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy43 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy43 << 0) /**< Shifted mode DivideBy43 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy44 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy44 << 0) /**< Shifted mode DivideBy44 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy45 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy45 << 0) /**< Shifted mode DivideBy45 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy46 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy46 << 0) /**< Shifted mode DivideBy46 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy47 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy47 << 0) /**< Shifted mode DivideBy47 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy48 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy48 << 0) /**< Shifted mode DivideBy48 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy49 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy49 << 0) /**< Shifted mode DivideBy49 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy50 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy50 << 0) /**< Shifted mode DivideBy50 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy51 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy51 << 0) /**< Shifted mode DivideBy51 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy52 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy52 << 0) /**< Shifted mode DivideBy52 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy53 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy53 << 0) /**< Shifted mode DivideBy53 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy54 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy54 << 0) /**< Shifted mode DivideBy54 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy55 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy55 << 0) /**< Shifted mode DivideBy55 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy56 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy56 << 0) /**< Shifted mode DivideBy56 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy57 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy57 << 0) /**< Shifted mode DivideBy57 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy58 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy58 << 0) /**< Shifted mode DivideBy58 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy59 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy59 << 0) /**< Shifted mode DivideBy59 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy60 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy60 << 0) /**< Shifted mode DivideBy60 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy61 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy61 << 0) /**< Shifted mode DivideBy61 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy62 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy62 << 0) /**< Shifted mode DivideBy62 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy63 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy63 << 0) /**< Shifted mode DivideBy63 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy64 (_ETAMPDET_CLKPRESCVAL_LOWERPRESC_DivideBy64 << 0) /**< Shifted mode DivideBy64 for ETAMPDET_CLKPRESCVAL*/ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_SHIFT 8 /**< Shift value for ETAMPDET_UPPERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_MASK 0x700UL /**< Bit mask for ETAMPDET_UPPERPRESC */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_Bypass 0x00000000UL /**< Mode Bypass for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy2 0x00000001UL /**< Mode DivideBy2 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy4 0x00000002UL /**< Mode DivideBy4 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy8 0x00000003UL /**< Mode DivideBy8 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy16 0x00000004UL /**< Mode DivideBy16 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy32 0x00000005UL /**< Mode DivideBy32 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy64 0x00000006UL /**< Mode DivideBy64 for ETAMPDET_CLKPRESCVAL */ +#define _ETAMPDET_CLKPRESCVAL_UPPERPRESC_Reserved 0x00000007UL /**< Mode Reserved for ETAMPDET_CLKPRESCVAL */ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DEFAULT (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_Bypass (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_Bypass << 8) /**< Shifted mode Bypass for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy2 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy2 << 8) /**< Shifted mode DivideBy2 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy4 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy4 << 8) /**< Shifted mode DivideBy4 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy8 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy8 << 8) /**< Shifted mode DivideBy8 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy16 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy16 << 8) /**< Shifted mode DivideBy16 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy32 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy32 << 8) /**< Shifted mode DivideBy32 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy64 (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_DivideBy64 << 8) /**< Shifted mode DivideBy64 for ETAMPDET_CLKPRESCVAL*/ +#define ETAMPDET_CLKPRESCVAL_UPPERPRESC_Reserved (_ETAMPDET_CLKPRESCVAL_UPPERPRESC_Reserved << 8) /**< Shifted mode Reserved for ETAMPDET_CLKPRESCVAL*/ + +/* Bit fields for ETAMPDET LOCK */ +#define _ETAMPDET_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for ETAMPDET_LOCK */ +#define _ETAMPDET_LOCK_MASK 0x0000FFFFUL /**< Mask for ETAMPDET_LOCK */ +#define _ETAMPDET_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for ETAMPDET_LOCKKEY */ +#define _ETAMPDET_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for ETAMPDET_LOCKKEY */ +#define _ETAMPDET_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for ETAMPDET_LOCK */ +#define _ETAMPDET_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for ETAMPDET_LOCK */ +#define ETAMPDET_LOCK_LOCKKEY_DEFAULT (_ETAMPDET_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETAMPDET_LOCK */ +#define ETAMPDET_LOCK_LOCKKEY_UNLOCK (_ETAMPDET_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for ETAMPDET_LOCK */ + +/** @} End of group EFR32MG29_ETAMPDET_BitFields */ +/** @} End of group EFR32MG29_ETAMPDET */ +/** @} End of group Parts */ + +#endif // EFR32MG29_ETAMPDET_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_eusart.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_eusart.h new file mode 100644 index 000000000..e2775c9d3 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_eusart.h @@ -0,0 +1,1193 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 EUSART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_EUSART_H +#define EFR32MG29_EUSART_H +#define EUSART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_EUSART EUSART + * @{ + * @brief EFR32MG29 EUSART Register Declaration. + *****************************************************************************/ + +/** EUSART Register Declaration. */ +typedef struct eusart_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[42U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[42U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED6[42U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED9[42U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} EUSART_TypeDef; +/** @} End of group EFR32MG29_EUSART */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_EUSART + * @{ + * @defgroup EFR32MG29_EUSART_BitFields EUSART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EUSART IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ + +/* Bit fields for EUSART EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ + +/* Bit fields for EUSART CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ + +/* Bit fields for EUSART CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ + +/* Bit fields for EUSART CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Master mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ + +/* Bit fields for EUSART FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ + +/* Bit fields for EUSART DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ + +/* Bit fields for EUSART IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ + +/* Bit fields for EUSART IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ + +/* Bit fields for EUSART TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ + +/* Bit fields for EUSART STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ + +/* Bit fields for EUSART SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ + +/* Bit fields for EUSART CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ + +/* Bit fields for EUSART TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ + +/* Bit fields for EUSART CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ + +/* Bit fields for EUSART RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ + +/* Bit fields for EUSART RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ + +/* Bit fields for EUSART TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ + +/* Bit fields for EUSART STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ + +/* Bit fields for EUSART IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ + +/* Bit fields for EUSART IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete IEN */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level IEN */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level IEN */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full IEN */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow IEN */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow IEN */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow IEN */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow IEN */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error IEN */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error IEN */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame IEN */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error IEN */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail IEN */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE IEN */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up IEN */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame IEN */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame IEN */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete IEN */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout IEN */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ + +/* Bit fields for EUSART SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ + +/** @} End of group EFR32MG29_EUSART_BitFields */ +/** @} End of group EFR32MG29_EUSART */ +/** @} End of group Parts */ + +#endif // EFR32MG29_EUSART_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_fsrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_fsrco.h new file mode 100644 index 000000000..d2c8df405 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_fsrco.h @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 FSRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_FSRCO_H +#define EFR32MG29_FSRCO_H +#define FSRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_FSRCO FSRCO + * @{ + * @brief EFR32MG29 FSRCO Register Declaration. + *****************************************************************************/ + +/** FSRCO Register Declaration. */ +typedef struct fsrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ +} FSRCO_TypeDef; +/** @} End of group EFR32MG29_FSRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_FSRCO + * @{ + * @defgroup EFR32MG29_FSRCO_BitFields FSRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FSRCO IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ + +/** @} End of group EFR32MG29_FSRCO_BitFields */ +/** @} End of group EFR32MG29_FSRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG29_FSRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpcrc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpcrc.h new file mode 100644 index 000000000..b7f7f1423 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpcrc.h @@ -0,0 +1,246 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 GPCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_GPCRC_H +#define EFR32MG29_GPCRC_H +#define GPCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_GPCRC GPCRC + * @{ + * @brief EFR32MG29 GPCRC Register Declaration. + *****************************************************************************/ + +/** GPCRC Register Declaration. */ +typedef struct gpcrc_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; +/** @} End of group EFR32MG29_GPCRC */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_GPCRC + * @{ + * @defgroup EFR32MG29_GPCRC_BitFields GPCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ + +/* Bit fields for GPCRC EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32MG29_GPCRC_BitFields */ +/** @} End of group EFR32MG29_GPCRC */ +/** @} End of group Parts */ + +#endif // EFR32MG29_GPCRC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio.h new file mode 100644 index 000000000..29b201a81 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio.h @@ -0,0 +1,2200 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 GPIO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_GPIO_H +#define EFR32MG29_GPIO_H +#define GPIO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +#include "efr32mg29_gpio_port.h" + +typedef struct gpio_acmproute_typedef{ + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_ACMPROUTE_TypeDef; + +typedef struct gpio_cmuroute_typedef{ + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ +} GPIO_CMUROUTE_TypeDef; + +typedef struct gpio_eusartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_EUSARTROUTE_TypeDef; + +typedef struct gpio_frcroute_typedef{ + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_FRCROUTE_TypeDef; + +typedef struct gpio_i2croute_typedef{ + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_I2CROUTE_TypeDef; + +typedef struct gpio_letimerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LETIMERROUTE_TypeDef; + +typedef struct gpio_modemroute_typedef{ + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_MODEMROUTE_TypeDef; + +typedef struct gpio_pdmroute_typedef{ + __IOM uint32_t ROUTEEN; /**< PDM pin enable */ + __IOM uint32_t CLKROUTE; /**< CLK port/pin select */ + __IOM uint32_t DAT0ROUTE; /**< DAT0 port/pin select */ + __IOM uint32_t DAT1ROUTE; /**< DAT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PDMROUTE_TypeDef; + +typedef struct gpio_prsroute_typedef{ + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PRSROUTE_TypeDef; + +typedef struct gpio_timerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_TIMERROUTE_TypeDef; + +typedef struct gpio_usartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_USARTROUTE_TypeDef; + +typedef struct gpio_typedef{ + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED4[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED9[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED10[603U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED11[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED12[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED15[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED20[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_SET; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED21[603U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED22[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED23[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED26[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED31[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_CLR; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED32[603U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED33[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED34[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED35[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED37[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED38[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[1U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED42[5U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_TGL; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[2U]; /**< usart0 DBUS config registers */ +} GPIO_TypeDef; + +/* Bit fields for GPIO IPVERSION */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/* Bit fields for GPIO GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ + +/* Bit fields for GPIO ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ + +/* Bit fields for GPIO BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ + +/* Bit fields for GPIO CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ + +/* Bit fields for GPIO DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ + +/* Bit fields for GPIO TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ + +/* Bit fields for GPIO_ACMP ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ + +/* Bit fields for GPIO_ACMP ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ + +/* Bit fields for GPIO_CMU ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ + +/* Bit fields for GPIO_CMU CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ + +/* Bit fields for GPIO_EUSART ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ + +/* Bit fields for GPIO_EUSART CSROUTE */ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ + +/* Bit fields for GPIO_EUSART CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ + +/* Bit fields for GPIO_EUSART RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ + +/* Bit fields for GPIO_EUSART RXROUTE */ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ + +/* Bit fields for GPIO_EUSART SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ + +/* Bit fields for GPIO_EUSART TXROUTE */ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ + +/* Bit fields for GPIO_FRC ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ + +/* Bit fields for GPIO_FRC DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ + +/* Bit fields for GPIO_FRC DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ + +/* Bit fields for GPIO_FRC DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ + +/* Bit fields for GPIO_I2C ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ + +/* Bit fields for GPIO_I2C SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ + +/* Bit fields for GPIO_I2C SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ + +/* Bit fields for GPIO_LETIMER ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ + +/* Bit fields for GPIO_LETIMER OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ + +/* Bit fields for GPIO_LETIMER OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ + +/* Bit fields for GPIO_MODEM ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ + +/* Bit fields for GPIO_MODEM DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ + +/* Bit fields for GPIO_MODEM DINROUTE */ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ + +/* Bit fields for GPIO_MODEM DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ + +/* Bit fields for GPIO_PDM ROUTEEN */ +#define _GPIO_PDM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_ROUTEEN */ +#define _GPIO_PDM_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_PDM_ROUTEEN */ +#define GPIO_PDM_ROUTEEN_CLKPEN (0x1UL << 0) /**< CLK pin enable control bit */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_SHIFT 0 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_MASK 0x1UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_ROUTEEN */ +#define GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT (_GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_ROUTEEN */ + +/* Bit fields for GPIO_PDM CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define GPIO_PDM_CLKROUTE_PORT_DEFAULT (_GPIO_PDM_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define GPIO_PDM_CLKROUTE_PIN_DEFAULT (_GPIO_PDM_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ + +/* Bit fields for GPIO_PDM DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_DAT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_DAT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define GPIO_PDM_DAT0ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_DAT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_DAT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define GPIO_PDM_DAT0ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ + +/* Bit fields for GPIO_PDM DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_DAT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_DAT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define GPIO_PDM_DAT1ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_DAT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_DAT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define GPIO_PDM_DAT1ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ + +/* Bit fields for GPIO_PRS ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ + +/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ + +/* Bit fields for GPIO_TIMER ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ + +/* Bit fields for GPIO_TIMER CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ + +/* Bit fields for GPIO_TIMER CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ + +/* Bit fields for GPIO_TIMER CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ + +/* Bit fields for GPIO_USART ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ + +/* Bit fields for GPIO_USART CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ + +/* Bit fields for GPIO_USART CTSROUTE */ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ + +/* Bit fields for GPIO_USART RTSROUTE */ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ + +/* Bit fields for GPIO_USART RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ + +/* Bit fields for GPIO_USART CLKROUTE */ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ + +/* Bit fields for GPIO_USART TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +/** @} End of group Parts */ + +#endif // EFR32MG29_GPIO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio_port.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio_port.h new file mode 100644 index 000000000..1fac848d1 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_gpio_port.h @@ -0,0 +1,421 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 GPIO Port register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef GPIO_PORT_H +#define GPIO_PORT_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief EFR32MG29 GPIO PORT + *****************************************************************************/ +typedef struct gpio_port_typedef{ + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ +} GPIO_PORT_TypeDef; + +/* Bit fields for GPIO_P CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO_P MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ + +/* Bit fields for GPIO_P MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x0000000FUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ + +/* Bit fields for GPIO_P DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x000001FFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x1FFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO_P DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x000001FFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x1FFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +/** @} End of group Parts */ + +#endif // GPIO_PORT_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfrco.h new file mode 100644 index 000000000..3e9908209 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfrco.h @@ -0,0 +1,226 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 HFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_HFRCO_H +#define EFR32MG29_HFRCO_H +#define HFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_HFRCO HFRCO + * @{ + * @brief EFR32MG29 HFRCO Register Declaration. + *****************************************************************************/ + +/** HFRCO Register Declaration. */ +typedef struct hfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ +} HFRCO_TypeDef; +/** @} End of group EFR32MG29_HFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_HFRCO + * @{ + * @defgroup EFR32MG29_HFRCO_BitFields HFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFRCO IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ + +/* Bit fields for HFRCO CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ + +/* Bit fields for HFRCO CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ + +/* Bit fields for HFRCO STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ + +/* Bit fields for HFRCO IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ + +/* Bit fields for HFRCO IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ + +/* Bit fields for HFRCO LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ + +/** @} End of group EFR32MG29_HFRCO_BitFields */ +/** @} End of group EFR32MG29_HFRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG29_HFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfxo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfxo.h new file mode 100644 index 000000000..1ded99f81 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_hfxo.h @@ -0,0 +1,463 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 HFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_HFXO_H +#define EFR32MG29_HFXO_H +#define HFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_HFXO HFXO + * @{ + * @brief EFR32MG29 HFXO Register Declaration. + *****************************************************************************/ + +/** HFXO Register Declaration. */ +typedef struct hfxo_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED4[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED13[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED22[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED31[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} HFXO_TypeDef; +/** @} End of group EFR32MG29_HFXO */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_HFXO + * @{ + * @defgroup EFR32MG29_HFXO_BitFields HFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFXO IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ + +/* Bit fields for HFXO XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x044334CBUL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000013UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000000UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000001UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000002UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000003UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000004UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000005UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000006UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000007UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000008UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x00000009UL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000AUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000BUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000CUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000DUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000EUL /**< Mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US 0x0000000FUL /**< Mode T7500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T7500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US << 20) /**< Shifted mode T7500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ + +/* Bit fields for HFXO XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x0F8C8C10UL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x00000010UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ + +/* Bit fields for HFXO CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xF000000DUL /**< Mask for HFXO_CFG */ +#define HFXO_CFG_MODE (0x1UL << 0) /**< Crystal Oscillator Mode */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x1UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ + +/* Bit fields for HFXO CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x80000037UL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand Mode */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ + +/* Bit fields for HFXO CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000003UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_MANUALOVERRIDE (0x1UL << 1) /**< Manual Override */ +#define _HFXO_CMD_MANUALOVERRIDE_SHIFT 1 /**< Shift value for HFXO_MANUALOVERRIDE */ +#define _HFXO_CMD_MANUALOVERRIDE_MASK 0x2UL /**< Bit mask for HFXO_MANUALOVERRIDE */ +#define _HFXO_CMD_MANUALOVERRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_MANUALOVERRIDE_DEFAULT (_HFXO_CMD_MANUALOVERRIDE_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CMD */ + +/* Bit fields for HFXO STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC00F0003UL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Hardware */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK (0x1UL << 30) /**< FSM Lock Status */ +#define _HFXO_STATUS_FSMLOCK_SHIFT 30 /**< Shift value for HFXO_FSMLOCK */ +#define _HFXO_STATUS_FSMLOCK_MASK 0x40000000UL /**< Bit mask for HFXO_FSMLOCK */ +#define _HFXO_STATUS_FSMLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_FSMLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_FSMLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_DEFAULT (_HFXO_STATUS_FSMLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_UNLOCKED (_HFXO_STATUS_FSMLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_LOCKED (_HFXO_STATUS_FSMLOCK_LOCKED << 30) /**< Shifted mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ + +/* Bit fields for HFXO IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xE0000003UL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ + +/* Bit fields for HFXO IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xE0000003UL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ + +/* Bit fields for HFXO LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ + +/** @} End of group EFR32MG29_HFXO_BitFields */ +/** @} End of group EFR32MG29_HFXO */ +/** @} End of group Parts */ + +#endif // EFR32MG29_HFXO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_i2c.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_i2c.h new file mode 100644 index 000000000..bae1b4e17 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_i2c.h @@ -0,0 +1,744 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 I2C register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_I2C_H +#define EFR32MG29_I2C_H +#define I2C_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_I2C I2C + * @{ + * @brief EFR32MG29 I2C Register Declaration. + *****************************************************************************/ + +/** I2C Register Declaration. */ +typedef struct i2c_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} I2C_TypeDef; +/** @} End of group EFR32MG29_I2C */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_I2C + * @{ + * @defgroup EFR32MG29_I2C_BitFields I2C Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ + +/* Bit fields for I2C EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ + +/** @} End of group EFR32MG29_I2C_BitFields */ +/** @} End of group EFR32MG29_I2C */ +/** @} End of group Parts */ + +#endif // EFR32MG29_I2C_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_iadc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_iadc.h new file mode 100644 index 000000000..a089cd813 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_iadc.h @@ -0,0 +1,1005 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 IADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_IADC_H +#define EFR32MG29_IADC_H +#define IADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_IADC IADC + * @{ + * @brief EFR32MG29 IADC Register Declaration. + *****************************************************************************/ + +/** IADC CFG Register Group Declaration. */ +typedef struct iadc_cfg_typedef{ + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ +} IADC_CFG_TypeDef; + +/** IADC SCANTABLE Register Group Declaration. */ +typedef struct iadc_scantable_typedef{ + __IOM uint32_t SCAN; /**< SCAN Entry */ +} IADC_SCANTABLE_TypeDef; + +/** IADC Register Declaration. */ +typedef struct iadc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ +} IADC_TypeDef; +/** @} End of group EFR32MG29_IADC */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_IADC + * @{ + * @defgroup EFR32MG29_IADC_BitFields IADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for IADC IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000004UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000004UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ + +/* Bit fields for IADC EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000001UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ + +/* Bit fields for IADC CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ + +/* Bit fields for IADC CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ + +/* Bit fields for IADC TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ + +/* Bit fields for IADC STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ + +/* Bit fields for IADC MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ + +/* Bit fields for IADC STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ + +/* Bit fields for IADC CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ + +/* Bit fields for IADC IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ + +/* Bit fields for IADC IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ + +/* Bit fields for IADC TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ + +/* Bit fields for IADC CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ + +/* Bit fields for IADC SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ + +/* Bit fields for IADC SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ + +/* Bit fields for IADC SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ + +/* Bit fields for IADC SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ + +/* Bit fields for IADC SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ + +/* Bit fields for IADC SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ + +/* Bit fields for IADC SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ + +/* Bit fields for IADC SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ + +/* Bit fields for IADC SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ + +/* Bit fields for IADC SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ + +/* Bit fields for IADC SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ + +/* Bit fields for IADC SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ + +/** @} End of group EFR32MG29_IADC_BitFields */ +/** @} End of group EFR32MG29_IADC */ +/** @} End of group Parts */ + +#endif // EFR32MG29_IADC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_icache.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_icache.h new file mode 100644 index 000000000..c80611945 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_icache.h @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 ICACHE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_ICACHE_H +#define EFR32MG29_ICACHE_H +#define ICACHE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_ICACHE ICACHE + * @{ + * @brief EFR32MG29 ICACHE Register Declaration. + *****************************************************************************/ + +/** ICACHE Register Declaration. */ +typedef struct icache_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +} ICACHE_TypeDef; +/** @} End of group EFR32MG29_ICACHE */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_ICACHE + * @{ + * @defgroup EFR32MG29_ICACHE_BitFields ICACHE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ICACHE IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ + +/* Bit fields for ICACHE CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ + +/* Bit fields for ICACHE PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ + +/* Bit fields for ICACHE PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ + +/* Bit fields for ICACHE PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ + +/* Bit fields for ICACHE STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ + +/* Bit fields for ICACHE CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ + +/* Bit fields for ICACHE LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ + +/* Bit fields for ICACHE IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ + +/* Bit fields for ICACHE IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ + +/** @} End of group EFR32MG29_ICACHE_BitFields */ +/** @} End of group EFR32MG29_ICACHE */ +/** @} End of group Parts */ + +#endif // EFR32MG29_ICACHE_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldma.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldma.h new file mode 100644 index 000000000..d2f8b9d81 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldma.h @@ -0,0 +1,685 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 LDMA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_LDMA_H +#define EFR32MG29_LDMA_H +#define LDMA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_LDMA LDMA + * @{ + * @brief EFR32MG29 LDMA Register Declaration. + *****************************************************************************/ + +/** LDMA CH Register Group Declaration. */ +typedef struct ldma_ch_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ +} LDMA_CH_TypeDef; + +/** LDMA Register Declaration. */ +typedef struct ldma_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; +/** @} End of group EFR32MG29_LDMA */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_LDMA + * @{ + * @defgroup EFR32MG29_LDMA_BitFields LDMA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ + +/* Bit fields for LDMA EN */ +#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ +#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ +#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ +#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ +#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ +#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ +#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ +#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ + +/* Bit fields for LDMA SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ + +/* Bit fields for LDMA SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ + +/* Bit fields for LDMA SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ + +/* Bit fields for LDMA SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHDIS */ +#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ +#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ +#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ + +/* Bit fields for LDMA CHSTATUS */ +#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ +#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32MG29_LDMA_BitFields */ +/** @} End of group EFR32MG29_LDMA */ +/** @} End of group Parts */ + +#endif // EFR32MG29_LDMA_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar.h new file mode 100644 index 000000000..024bb4815 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 LDMAXBAR register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_LDMAXBAR_H +#define EFR32MG29_LDMAXBAR_H +#define LDMAXBAR_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_LDMAXBAR LDMAXBAR + * @{ + * @brief EFR32MG29 LDMAXBAR Register Declaration. + *****************************************************************************/ + +/** LDMAXBAR CH Register Group Declaration. */ +typedef struct ldmaxbar_ch_typedef{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +} LDMAXBAR_CH_TypeDef; + +/** LDMAXBAR Register Declaration. */ +typedef struct ldmaxbar_typedef{ + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMAXBAR_TypeDef; +/** @} End of group EFR32MG29_LDMAXBAR */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_LDMAXBAR + * @{ + * @defgroup EFR32MG29_LDMAXBAR_BitFields LDMAXBAR Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMAXBAR IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ + +/* Bit fields for LDMAXBAR CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ + +/** @} End of group EFR32MG29_LDMAXBAR_BitFields */ +/** @} End of group EFR32MG29_LDMAXBAR */ +/** @} End of group Parts */ + +#endif // EFR32MG29_LDMAXBAR_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar_defines.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar_defines.h new file mode 100644 index 000000000..7f8bfd9a2 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ldmaxbar_defines.h @@ -0,0 +1,161 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 LDMA XBAR channel request soruce definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_LDMAXBAR_DEFINES_H +#define EFR32MG29_LDMAXBAR_DEFINES_H + +// Module source selection indices +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 0x00000005UL /**< Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000006UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000007UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000bUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000cUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000dUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000eUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_PDM 0x0000000fUL /**< Mode PDM for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x00000010UL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x00000011UL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000012UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ + +// Shifted source selection indices +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_PDM (_LDMAXBAR_CH_REQSEL_SOURCESEL_PDM << 16) /**< Shifted Mode PDM for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ + +// Module signal selection indices +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /** Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000001UL /** Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL 0x00000002UL /** Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000003UL /** Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000004UL /** Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV 0x00000000UL /** Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ + +// Shifted Module signal selection indices +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /** Shifted Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /** Shifted Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL << 0) /** Shifted Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /** Shifted Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /** Shifted Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV << 0) /** Shifted Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ + +#endif // EFR32MG29_LDMAXBAR_DEFINES_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_letimer.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_letimer.h new file mode 100644 index 000000000..9c33c752b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_letimer.h @@ -0,0 +1,496 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 LETIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_LETIMER_H +#define EFR32MG29_LETIMER_H +#define LETIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_LETIMER LETIMER + * @{ + * @brief EFR32MG29 LETIMER Register Declaration. + *****************************************************************************/ + +/** LETIMER Register Declaration. */ +typedef struct letimer_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED7[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED11[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +} LETIMER_TypeDef; +/** @} End of group EFR32MG29_LETIMER */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_LETIMER + * @{ + * @defgroup EFR32MG29_LETIMER_BitFields LETIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ + +/* Bit fields for LETIMER EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000001UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ + +/* Bit fields for LETIMER TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ + +/** @} End of group EFR32MG29_LETIMER_BitFields */ +/** @} End of group EFR32MG29_LETIMER */ +/** @} End of group Parts */ + +#endif // EFR32MG29_LETIMER_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfrco.h new file mode 100644 index 000000000..2e626404b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfrco.h @@ -0,0 +1,304 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 LFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_LFRCO_H +#define EFR32MG29_LFRCO_H +#define LFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_LFRCO LFRCO + * @{ + * @brief EFR32MG29 LFRCO Register Declaration. + *****************************************************************************/ + +/** LFRCO Register Declaration. */ +typedef struct lfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED3[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED7[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED11[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ +} LFRCO_TypeDef; +/** @} End of group EFR32MG29_LFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_LFRCO + * @{ + * @defgroup EFR32MG29_LFRCO_BitFields LFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFRCO IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ + +/* Bit fields for LFRCO CTRL */ +#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ +#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ +#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ + +/* Bit fields for LFRCO STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ + +/* Bit fields for LFRCO IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ +#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ +#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ +#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ +#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ +#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ +#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ + +/* Bit fields for LFRCO IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ +#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ +#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ +#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ +#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ +#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ +#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ + +/* Bit fields for LFRCO LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ + +/* Bit fields for LFRCO CFG */ +#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ +#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ +#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ + +/* Bit fields for LFRCO NOMCAL */ +#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ +#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ + +/* Bit fields for LFRCO NOMCALINV */ +#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ +#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ + +/* Bit fields for LFRCO CMD */ +#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ +#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ +#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ + +/** @} End of group EFR32MG29_LFRCO_BitFields */ +/** @} End of group EFR32MG29_LFRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG29_LFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfxo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfxo.h new file mode 100644 index 000000000..9884a7cb7 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_lfxo.h @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 LFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_LFXO_H +#define EFR32MG29_LFXO_H +#define LFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_LFXO LFXO + * @{ + * @brief EFR32MG29 LFXO Register Declaration. + *****************************************************************************/ + +/** LFXO Register Declaration. */ +typedef struct lfxo_typedef{ + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFXO_TypeDef; +/** @} End of group EFR32MG29_LFXO */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_LFXO + * @{ + * @defgroup EFR32MG29_LFXO_BitFields LFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFXO IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ + +/* Bit fields for LFXO CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ + +/* Bit fields for LFXO CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ + +/* Bit fields for LFXO STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ + +/* Bit fields for LFXO CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ + +/* Bit fields for LFXO IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ + +/* Bit fields for LFXO IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ + +/* Bit fields for LFXO SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ + +/* Bit fields for LFXO LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ + +/** @} End of group EFR32MG29_LFXO_BitFields */ +/** @} End of group EFR32MG29_LFXO */ +/** @} End of group Parts */ + +#endif // EFR32MG29_LFXO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_mpahbram.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_mpahbram.h new file mode 100644 index 000000000..1874d03d5 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_mpahbram.h @@ -0,0 +1,246 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 MPAHBRAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_MPAHBRAM_H +#define EFR32MG29_MPAHBRAM_H +#define MPAHBRAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_MPAHBRAM MPAHBRAM + * @{ + * @brief EFR32MG29 MPAHBRAM Register Declaration. + *****************************************************************************/ + +/** MPAHBRAM Register Declaration. */ +typedef struct mpahbram_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t CTRL; /**< Control register */ + __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t CTRL_SET; /**< Control register */ + __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t CTRL_CLR; /**< Control register */ + __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t CTRL_TGL; /**< Control register */ + __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} MPAHBRAM_TypeDef; +/** @} End of group EFR32MG29_MPAHBRAM */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_MPAHBRAM + * @{ + * @defgroup EFR32MG29_MPAHBRAM_BitFields MPAHBRAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MPAHBRAM IPVERSION */ +#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ + +/* Bit fields for MPAHBRAM CMD */ +#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_MASK 0x00000003UL /**< Mask for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ + +/* Bit fields for MPAHBRAM CTRL */ +#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ +#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ +#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ +#define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ + +/* Bit fields for MPAHBRAM ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ +#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ + +/* Bit fields for MPAHBRAM ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ +#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ + +/* Bit fields for MPAHBRAM ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_MASK 0x00000003UL /**< Mask for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ +#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ +#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ + +/* Bit fields for MPAHBRAM IF */ +#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_MASK 0x00000033UL /**< Mask for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ + +/* Bit fields for MPAHBRAM IEN */ +#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_MASK 0x00000033UL /**< Mask for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ + +/** @} End of group EFR32MG29_MPAHBRAM_BitFields */ +/** @} End of group EFR32MG29_MPAHBRAM */ +/** @} End of group Parts */ + +#endif // EFR32MG29_MPAHBRAM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_msc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_msc.h new file mode 100644 index 000000000..a519a2692 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_msc.h @@ -0,0 +1,522 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 MSC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_MSC_H +#define EFR32MG29_MSC_H +#define MSC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_MSC MSC + * @{ + * @brief EFR32MG29 MSC Register Declaration. + *****************************************************************************/ + +/** MSC Register Declaration. */ +typedef struct msc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED2[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ + uint32_t RESERVED3[4U]; /**< Reserved for future use */ + uint32_t RESERVED4[4U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[12U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED14[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + uint32_t RESERVED17[4U]; /**< Reserved for future use */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + uint32_t RESERVED19[12U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[8U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED26[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ + uint32_t RESERVED27[4U]; /**< Reserved for future use */ + uint32_t RESERVED28[4U]; /**< Reserved for future use */ + uint32_t RESERVED29[4U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + uint32_t RESERVED31[12U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[8U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + uint32_t RESERVED35[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED38[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ + uint32_t RESERVED39[4U]; /**< Reserved for future use */ + uint32_t RESERVED40[4U]; /**< Reserved for future use */ + uint32_t RESERVED41[4U]; /**< Reserved for future use */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + uint32_t RESERVED43[12U]; /**< Reserved for future use */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + uint32_t RESERVED45[8U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ +} MSC_TypeDef; +/** @} End of group EFR32MG29_MSC */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_MSC + * @{ + * @defgroup EFR32MG29_MSC_BitFields MSC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000007UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000007UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ + +/* Bit fields for MSC RDATACTRL */ +#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ +#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ +#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ +#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash Power On Status */ +#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ +#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ +#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ + +/* Bit fields for MSC PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ + +/* Bit fields for MSC PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ + +/* Bit fields for MSC PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ + +/* Bit fields for MSC PAGELOCK2 */ +#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ +#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ + +/* Bit fields for MSC PAGELOCK3 */ +#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ +#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ + +/** @} End of group EFR32MG29_MSC_BitFields */ +/** @} End of group EFR32MG29_MSC */ +/** @} End of group Parts */ + +#endif // EFR32MG29_MSC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_pdm.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_pdm.h new file mode 100644 index 000000000..914fef64d --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_pdm.h @@ -0,0 +1,363 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 PDM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_PDM_H +#define EFR32MG29_PDM_H +#define PDM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_PDM PDM + * @{ + * @brief EFR32MG29 PDM Register Declaration. + *****************************************************************************/ + +/** PDM Register Declaration. */ +typedef struct pdm_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< PDM Module enable Register */ + __IOM uint32_t CTRL; /**< PDM Core Control Register */ + __IOM uint32_t CMD; /**< PDM Core Command Register */ + __IM uint32_t STATUS; /**< PDM Status register */ + __IOM uint32_t CFG0; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA; /**< PDM Received Data Register */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Flag Register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED3[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_SET; /**< PDM Core Control Register */ + __IOM uint32_t CMD_SET; /**< PDM Core Command Register */ + __IM uint32_t STATUS_SET; /**< PDM Status register */ + __IOM uint32_t CFG0_SET; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_SET; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_SET; /**< PDM Received Data Register */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Flag Register */ + uint32_t RESERVED6[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED7[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_CLR; /**< PDM Core Control Register */ + __IOM uint32_t CMD_CLR; /**< PDM Core Command Register */ + __IM uint32_t STATUS_CLR; /**< PDM Status register */ + __IOM uint32_t CFG0_CLR; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_CLR; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_CLR; /**< PDM Received Data Register */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Flag Register */ + uint32_t RESERVED10[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED11[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_TGL; /**< PDM Core Control Register */ + __IOM uint32_t CMD_TGL; /**< PDM Core Command Register */ + __IM uint32_t STATUS_TGL; /**< PDM Status register */ + __IOM uint32_t CFG0_TGL; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_TGL; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_TGL; /**< PDM Received Data Register */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Flag Register */ + uint32_t RESERVED14[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} PDM_TypeDef; +/** @} End of group EFR32MG29_PDM */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_PDM + * @{ + * @defgroup EFR32MG29_PDM_BitFields PDM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PDM IPVERSION */ +#define _PDM_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for PDM_IPVERSION */ +#define _PDM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IPVERSION */ +#define PDM_IPVERSION_IPVERSION_DEFAULT (_PDM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IPVERSION */ + +/* Bit fields for PDM EN */ +#define _PDM_EN_RESETVALUE 0x00000000UL /**< Default value for PDM_EN */ +#define _PDM_EN_MASK 0x00000001UL /**< Mask for PDM_EN */ +#define PDM_EN_EN (0x1UL << 0) /**< PDM enable */ +#define _PDM_EN_EN_SHIFT 0 /**< Shift value for PDM_EN */ +#define _PDM_EN_EN_MASK 0x1UL /**< Bit mask for PDM_EN */ +#define _PDM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_EN */ +#define _PDM_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_EN */ +#define _PDM_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for PDM_EN */ +#define PDM_EN_EN_DEFAULT (_PDM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_EN */ +#define PDM_EN_EN_DISABLE (_PDM_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for PDM_EN */ +#define PDM_EN_EN_ENABLE (_PDM_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for PDM_EN */ + +/* Bit fields for PDM CTRL */ +#define _PDM_CTRL_RESETVALUE 0x00000000UL /**< Default value for PDM_CTRL */ +#define _PDM_CTRL_MASK 0x000FFF1FUL /**< Mask for PDM_CTRL */ +#define _PDM_CTRL_GAIN_SHIFT 0 /**< Shift value for PDM_GAIN */ +#define _PDM_CTRL_GAIN_MASK 0x1FUL /**< Bit mask for PDM_GAIN */ +#define _PDM_CTRL_GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ +#define PDM_CTRL_GAIN_DEFAULT (_PDM_CTRL_GAIN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CTRL */ +#define _PDM_CTRL_DSR_SHIFT 8 /**< Shift value for PDM_DSR */ +#define _PDM_CTRL_DSR_MASK 0xFFF00UL /**< Bit mask for PDM_DSR */ +#define _PDM_CTRL_DSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ +#define PDM_CTRL_DSR_DEFAULT (_PDM_CTRL_DSR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CTRL */ + +/* Bit fields for PDM CMD */ +#define _PDM_CMD_RESETVALUE 0x00000000UL /**< Default value for PDM_CMD */ +#define _PDM_CMD_MASK 0x00010111UL /**< Mask for PDM_CMD */ +#define PDM_CMD_START (0x1UL << 0) /**< Start DCF */ +#define _PDM_CMD_START_SHIFT 0 /**< Shift value for PDM_START */ +#define _PDM_CMD_START_MASK 0x1UL /**< Bit mask for PDM_START */ +#define _PDM_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_START_DEFAULT (_PDM_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_STOP (0x1UL << 4) /**< Stop DCF */ +#define _PDM_CMD_STOP_SHIFT 4 /**< Shift value for PDM_STOP */ +#define _PDM_CMD_STOP_MASK 0x10UL /**< Bit mask for PDM_STOP */ +#define _PDM_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_STOP_DEFAULT (_PDM_CMD_STOP_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_CLEAR (0x1UL << 8) /**< Clear DCF */ +#define _PDM_CMD_CLEAR_SHIFT 8 /**< Shift value for PDM_CLEAR */ +#define _PDM_CMD_CLEAR_MASK 0x100UL /**< Bit mask for PDM_CLEAR */ +#define _PDM_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_CLEAR_DEFAULT (_PDM_CMD_CLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_FIFOFL (0x1UL << 16) /**< FIFO Flush */ +#define _PDM_CMD_FIFOFL_SHIFT 16 /**< Shift value for PDM_FIFOFL */ +#define _PDM_CMD_FIFOFL_MASK 0x10000UL /**< Bit mask for PDM_FIFOFL */ +#define _PDM_CMD_FIFOFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_FIFOFL_DEFAULT (_PDM_CMD_FIFOFL_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CMD */ + +/* Bit fields for PDM STATUS */ +#define _PDM_STATUS_RESETVALUE 0x00000020UL /**< Default value for PDM_STATUS */ +#define _PDM_STATUS_MASK 0x00000731UL /**< Mask for PDM_STATUS */ +#define PDM_STATUS_ACT (0x1UL << 0) /**< PDM is active */ +#define _PDM_STATUS_ACT_SHIFT 0 /**< Shift value for PDM_ACT */ +#define _PDM_STATUS_ACT_MASK 0x1UL /**< Bit mask for PDM_ACT */ +#define _PDM_STATUS_ACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_ACT_DEFAULT (_PDM_STATUS_ACT_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FULL (0x1UL << 4) /**< FIFO FULL Status */ +#define _PDM_STATUS_FULL_SHIFT 4 /**< Shift value for PDM_FULL */ +#define _PDM_STATUS_FULL_MASK 0x10UL /**< Bit mask for PDM_FULL */ +#define _PDM_STATUS_FULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FULL_DEFAULT (_PDM_STATUS_FULL_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_EMPTY (0x1UL << 5) /**< FIFO EMPTY Status */ +#define _PDM_STATUS_EMPTY_SHIFT 5 /**< Shift value for PDM_EMPTY */ +#define _PDM_STATUS_EMPTY_MASK 0x20UL /**< Bit mask for PDM_EMPTY */ +#define _PDM_STATUS_EMPTY_DEFAULT 0x00000001UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_EMPTY_DEFAULT (_PDM_STATUS_EMPTY_DEFAULT << 5) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define _PDM_STATUS_FIFOCNT_SHIFT 8 /**< Shift value for PDM_FIFOCNT */ +#define _PDM_STATUS_FIFOCNT_MASK 0x700UL /**< Bit mask for PDM_FIFOCNT */ +#define _PDM_STATUS_FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FIFOCNT_DEFAULT (_PDM_STATUS_FIFOCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_STATUS */ + +/* Bit fields for PDM CFG0 */ +#define _PDM_CFG0_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG0 */ +#define _PDM_CFG0_MASK 0x03013713UL /**< Mask for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_SHIFT 0 /**< Shift value for PDM_FORDER */ +#define _PDM_CFG0_FORDER_MASK 0x3UL /**< Bit mask for PDM_FORDER */ +#define _PDM_CFG0_FORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_SECOND 0x00000000UL /**< Mode SECOND for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_THIRD 0x00000001UL /**< Mode THIRD for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_FOURTH 0x00000002UL /**< Mode FOURTH for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_FIFTH 0x00000003UL /**< Mode FIFTH for PDM_CFG0 */ +#define PDM_CFG0_FORDER_DEFAULT (_PDM_CFG0_FORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_FORDER_SECOND (_PDM_CFG0_FORDER_SECOND << 0) /**< Shifted mode SECOND for PDM_CFG0 */ +#define PDM_CFG0_FORDER_THIRD (_PDM_CFG0_FORDER_THIRD << 0) /**< Shifted mode THIRD for PDM_CFG0 */ +#define PDM_CFG0_FORDER_FOURTH (_PDM_CFG0_FORDER_FOURTH << 0) /**< Shifted mode FOURTH for PDM_CFG0 */ +#define PDM_CFG0_FORDER_FIFTH (_PDM_CFG0_FORDER_FIFTH << 0) /**< Shifted mode FIFTH for PDM_CFG0 */ +#define PDM_CFG0_NUMCH (0x1UL << 4) /**< Number of Channels */ +#define _PDM_CFG0_NUMCH_SHIFT 4 /**< Shift value for PDM_NUMCH */ +#define _PDM_CFG0_NUMCH_MASK 0x10UL /**< Bit mask for PDM_NUMCH */ +#define _PDM_CFG0_NUMCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_NUMCH_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ +#define _PDM_CFG0_NUMCH_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_DEFAULT (_PDM_CFG0_NUMCH_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_ONE (_PDM_CFG0_NUMCH_ONE << 4) /**< Shifted mode ONE for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_TWO (_PDM_CFG0_NUMCH_TWO << 4) /**< Shifted mode TWO for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_SHIFT 8 /**< Shift value for PDM_DATAFORMAT */ +#define _PDM_CFG0_DATAFORMAT_MASK 0x700UL /**< Bit mask for PDM_DATAFORMAT */ +#define _PDM_CFG0_DATAFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RIGHT16 0x00000000UL /**< Mode RIGHT16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_DOUBLE16 0x00000001UL /**< Mode DOUBLE16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RIGHT24 0x00000002UL /**< Mode RIGHT24 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_FULL32BIT 0x00000003UL /**< Mode FULL32BIT for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_LEFT16 0x00000004UL /**< Mode LEFT16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_LEFT24 0x00000005UL /**< Mode LEFT24 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RAW32BIT 0x00000006UL /**< Mode RAW32BIT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_DEFAULT (_PDM_CFG0_DATAFORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RIGHT16 (_PDM_CFG0_DATAFORMAT_RIGHT16 << 8) /**< Shifted mode RIGHT16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_DOUBLE16 (_PDM_CFG0_DATAFORMAT_DOUBLE16 << 8) /**< Shifted mode DOUBLE16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RIGHT24 (_PDM_CFG0_DATAFORMAT_RIGHT24 << 8) /**< Shifted mode RIGHT24 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_FULL32BIT (_PDM_CFG0_DATAFORMAT_FULL32BIT << 8) /**< Shifted mode FULL32BIT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_LEFT16 (_PDM_CFG0_DATAFORMAT_LEFT16 << 8) /**< Shifted mode LEFT16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_LEFT24 (_PDM_CFG0_DATAFORMAT_LEFT24 << 8) /**< Shifted mode LEFT24 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RAW32BIT (_PDM_CFG0_DATAFORMAT_RAW32BIT << 8) /**< Shifted mode RAW32BIT for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_SHIFT 12 /**< Shift value for PDM_FIFODVL */ +#define _PDM_CFG0_FIFODVL_MASK 0x3000UL /**< Bit mask for PDM_FIFODVL */ +#define _PDM_CFG0_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_DEFAULT (_PDM_CFG0_FIFODVL_DEFAULT << 12) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_ONE (_PDM_CFG0_FIFODVL_ONE << 12) /**< Shifted mode ONE for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_TWO (_PDM_CFG0_FIFODVL_TWO << 12) /**< Shifted mode TWO for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_THREE (_PDM_CFG0_FIFODVL_THREE << 12) /**< Shifted mode THREE for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_FOUR (_PDM_CFG0_FIFODVL_FOUR << 12) /**< Shifted mode FOUR for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01 (0x1UL << 16) /**< Stereo mode CH01 */ +#define _PDM_CFG0_STEREOMODECH01_SHIFT 16 /**< Shift value for PDM_STEREOMODECH01 */ +#define _PDM_CFG0_STEREOMODECH01_MASK 0x10000UL /**< Bit mask for PDM_STEREOMODECH01 */ +#define _PDM_CFG0_STEREOMODECH01_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_STEREOMODECH01_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */ +#define _PDM_CFG0_STEREOMODECH01_CH01ENABLE 0x00000001UL /**< Mode CH01ENABLE for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_DEFAULT (_PDM_CFG0_STEREOMODECH01_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_DISABLE (_PDM_CFG0_STEREOMODECH01_DISABLE << 16) /**< Shifted mode DISABLE for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_CH01ENABLE (_PDM_CFG0_STEREOMODECH01_CH01ENABLE << 16) /**< Shifted mode CH01ENABLE for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL (0x1UL << 24) /**< CH0 CLK Polarity */ +#define _PDM_CFG0_CH0CLKPOL_SHIFT 24 /**< Shift value for PDM_CH0CLKPOL */ +#define _PDM_CFG0_CH0CLKPOL_MASK 0x1000000UL /**< Bit mask for PDM_CH0CLKPOL */ +#define _PDM_CFG0_CH0CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_CH0CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ +#define _PDM_CFG0_CH0CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_DEFAULT (_PDM_CFG0_CH0CLKPOL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_NORMAL (_PDM_CFG0_CH0CLKPOL_NORMAL << 24) /**< Shifted mode NORMAL for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_INVERT (_PDM_CFG0_CH0CLKPOL_INVERT << 24) /**< Shifted mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL (0x1UL << 25) /**< CH1 CLK Polarity */ +#define _PDM_CFG0_CH1CLKPOL_SHIFT 25 /**< Shift value for PDM_CH1CLKPOL */ +#define _PDM_CFG0_CH1CLKPOL_MASK 0x2000000UL /**< Bit mask for PDM_CH1CLKPOL */ +#define _PDM_CFG0_CH1CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ +#define _PDM_CFG0_CH1CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_DEFAULT (_PDM_CFG0_CH1CLKPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shifted mode NORMAL for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_INVERT (_PDM_CFG0_CH1CLKPOL_INVERT << 25) /**< Shifted mode INVERT for PDM_CFG0 */ + +/* Bit fields for PDM CFG1 */ +#define _PDM_CFG1_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG1 */ +#define _PDM_CFG1_MASK 0x030003FFUL /**< Mask for PDM_CFG1 */ +#define _PDM_CFG1_PRESC_SHIFT 0 /**< Shift value for PDM_PRESC */ +#define _PDM_CFG1_PRESC_MASK 0x3FFUL /**< Bit mask for PDM_PRESC */ +#define _PDM_CFG1_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ +#define PDM_CFG1_PRESC_DEFAULT (_PDM_CFG1_PRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG1 */ +#define _PDM_CFG1_DLYMUXSEL_SHIFT 24 /**< Shift value for PDM_DLYMUXSEL */ +#define _PDM_CFG1_DLYMUXSEL_MASK 0x3000000UL /**< Bit mask for PDM_DLYMUXSEL */ +#define _PDM_CFG1_DLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ +#define PDM_CFG1_DLYMUXSEL_DEFAULT (_PDM_CFG1_DLYMUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG1 */ + +/* Bit fields for PDM RXDATA */ +#define _PDM_RXDATA_RESETVALUE 0x00000000UL /**< Default value for PDM_RXDATA */ +#define _PDM_RXDATA_MASK 0xFFFFFFFFUL /**< Mask for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_SHIFT 0 /**< Shift value for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_RXDATA */ +#define PDM_RXDATA_RXDATA_DEFAULT (_PDM_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_RXDATA */ + +/* Bit fields for PDM IF */ +#define _PDM_IF_RESETVALUE 0x00000000UL /**< Default value for PDM_IF */ +#define _PDM_IF_MASK 0x0000000FUL /**< Mask for PDM_IF */ +#define PDM_IF_DV (0x1UL << 0) /**< Data Valid Interrupt Flag */ +#define _PDM_IF_DV_SHIFT 0 /**< Shift value for PDM_DV */ +#define _PDM_IF_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ +#define _PDM_IF_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_DV_DEFAULT (_PDM_IF_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Flag */ +#define _PDM_IF_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ +#define _PDM_IF_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ +#define _PDM_IF_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_DVL_DEFAULT (_PDM_IF_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Flag */ +#define _PDM_IF_OF_SHIFT 2 /**< Shift value for PDM_OF */ +#define _PDM_IF_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ +#define _PDM_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_OF_DEFAULT (_PDM_IF_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Flag */ +#define _PDM_IF_UF_SHIFT 3 /**< Shift value for PDM_UF */ +#define _PDM_IF_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ +#define _PDM_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_UF_DEFAULT (_PDM_IF_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IF */ + +/* Bit fields for PDM IEN */ +#define _PDM_IEN_RESETVALUE 0x00000000UL /**< Default value for PDM_IEN */ +#define _PDM_IEN_MASK 0x0000000FUL /**< Mask for PDM_IEN */ +#define PDM_IEN_DV (0x1UL << 0) /**< Data Valid Interrupt Enable */ +#define _PDM_IEN_DV_SHIFT 0 /**< Shift value for PDM_DV */ +#define _PDM_IEN_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ +#define _PDM_IEN_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DV_DEFAULT (_PDM_IEN_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Enable */ +#define _PDM_IEN_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ +#define _PDM_IEN_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ +#define _PDM_IEN_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DVL_DEFAULT (_PDM_IEN_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Enable */ +#define _PDM_IEN_OF_SHIFT 2 /**< Shift value for PDM_OF */ +#define _PDM_IEN_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ +#define _PDM_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_OF_DEFAULT (_PDM_IEN_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Enable */ +#define _PDM_IEN_UF_SHIFT 3 /**< Shift value for PDM_UF */ +#define _PDM_IEN_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ +#define _PDM_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_UF_DEFAULT (_PDM_IEN_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IEN */ + +/* Bit fields for PDM SYNCBUSY */ +#define _PDM_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_MASK 0x00000009UL /**< Mask for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< sync busy */ +#define _PDM_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_SYNCBUSY_DEFAULT (_PDM_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_FIFOFLBUSY (0x1UL << 3) /**< FIFO Flush Sync busy */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_SHIFT 3 /**< Shift value for PDM_FIFOFLBUSY */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_MASK 0x8UL /**< Bit mask for PDM_FIFOFLBUSY */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT (_PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ + +/** @} End of group EFR32MG29_PDM_BitFields */ +/** @} End of group EFR32MG29_PDM */ +/** @} End of group Parts */ + +#endif // EFR32MG29_PDM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs.h new file mode 100644 index 000000000..c0c97e9c4 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs.h @@ -0,0 +1,1471 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 PRS register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_PRS_H +#define EFR32MG29_PRS_H +#define PRS_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_PRS PRS + * @{ + * @brief EFR32MG29 PRS Register Declaration. + *****************************************************************************/ + +/** PRS ASYNC_CH Register Group Declaration. */ +typedef struct prs_async_ch_typedef{ + __IOM uint32_t CTRL; /**< Async Channel Control Register */ +} PRS_ASYNC_CH_TypeDef; + +/** PRS SYNC_CH Register Group Declaration. */ +typedef struct prs_sync_ch_typedef{ + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +} PRS_SYNC_CH_TypeDef; + +/** PRS Register Declaration. */ +typedef struct prs_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1; /**< CC1 Consumer register */ + uint32_t RESERVED2[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2; /**< CC2 Consumer register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[900U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1_SET; /**< CC1 Consumer register */ + uint32_t RESERVED10[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ_SET; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2_SET; /**< CC2 Consumer register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[900U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1_CLR; /**< CC1 Consumer register */ + uint32_t RESERVED18[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ_CLR; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2_CLR; /**< CC2 Consumer register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[900U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_PRORTC_CC1_TGL; /**< CC1 Consumer register */ + uint32_t RESERVED26[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_SEQ_TGL; /**< SEQ Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_RTCC_CC2_TGL; /**< CC2 Consumer register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer register */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED28[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_USART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART1_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} PRS_TypeDef; +/** @} End of group EFR32MG29_PRS */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_PRS + * @{ + * @defgroup EFR32MG29_PRS_BitFields PRS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000008UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000008UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ + +/* Bit fields for PRS ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ + +/* Bit fields for PRS ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ + +/* Bit fields for PRS ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ + +/* Bit fields for PRS SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ + +/* Bit fields for PRS ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ + +/* Bit fields for PRS SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ + +/* Bit fields for PRS CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ + +/* Bit fields for PRS CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ + +/* Bit fields for PRS CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ + +/* Bit fields for PRS CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ + +/* Bit fields for PRS CONSUMER_PRORTC_CC0 */ +#define _PRS_CONSUMER_PRORTC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PRORTC_CC0 */ +#define _PRS_CONSUMER_PRORTC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PRORTC_CC0 */ +#define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PRORTC_CC0 */ +#define PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_PRORTC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PRORTC_CC0*/ + +/* Bit fields for PRS CONSUMER_PRORTC_CC1 */ +#define _PRS_CONSUMER_PRORTC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PRORTC_CC1 */ +#define _PRS_CONSUMER_PRORTC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PRORTC_CC1 */ +#define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PRORTC_CC1 */ +#define PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_PRORTC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PRORTC_CC1*/ + +/* Bit fields for PRS CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ + +/* Bit fields for PRS CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ + +/* Bit fields for PRS CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ + +/* Bit fields for PRS CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_SEQ */ +#define PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_SEQ*/ + +/* Bit fields for PRS CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC0 */ +#define PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC0*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC1 */ +#define PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC1*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC2 */ +#define PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC2*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ + +/* Bit fields for PRS CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ + +/* Bit fields for PRS CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ + +/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_CLK */ +#define PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_CLK*/ + +/* Bit fields for PRS CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_IR */ +#define PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_IR*/ + +/* Bit fields for PRS CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_RX */ +#define PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_RX*/ + +/* Bit fields for PRS CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_TRIGGER*/ +#define _PRS_CONSUMER_USART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ +#define PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ + +/** @} End of group EFR32MG29_PRS_BitFields */ +/** @} End of group EFR32MG29_PRS */ +/** @} End of group Parts */ + +#endif // EFR32MG29_PRS_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs_signals.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs_signals.h new file mode 100644 index 000000000..656167142 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_prs_signals.h @@ -0,0 +1,930 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 PRS register signal bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_PRS_SIGNALS_H +#define EFR32MG29_PRS_SIGNALS_H + +/** Synchronous signal sources enumeration: */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) + +/** Synchronous signal sources enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) + +/** Synchronous signals enumeration: */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) + +/** Synchronous signals enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) + +/** Synchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) + +/** Asynchronous signal sources enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000008UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (0x00000009UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x0000000aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x0000000bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET (0x0000000cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x0000000eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x0000000fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC (0x00000010UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000011UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000012UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (0x00000013UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (0x00000021UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000022UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000023UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000024UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000025UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000026UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000027UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000028UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000029UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x0000002aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x00000030UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (0x00000031UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (0x00000032UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000033UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000034UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000035UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000036UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000037UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET (0x00000038UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO (0x00000039UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x0000003aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x0000003bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x0000003cUL) + +/** Asynchronous signal sources enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET (_PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC (_PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET (_PRS_ASYNC_CH_CTRL_SOURCESEL_SEATAMPDET << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_SEHFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (_PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE << 8) + +/** Asynchronous signals enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) + +/** Asynchronous signals enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (_PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET (_PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA (_PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) + +/** Asynchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) +#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) +#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) +#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) +#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) +#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) +#define PRS_ASYNC_USART1_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS) +#define PRS_ASYNC_USART1_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX) +#define PRS_ASYNC_USART1_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS) +#define PRS_ASYNC_USART1_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA) +#define PRS_ASYNC_USART1_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX) +#define PRS_ASYNC_USART1_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC) +#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) +#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) +#define PRS_ASYNC_RTCC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0) +#define PRS_ASYNC_RTCC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1) +#define PRS_ASYNC_RTCC_CCV2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2) +#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) +#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) +#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) +#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) +#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) +#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) +#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) +#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) +#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) +#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) +#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) +#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) +#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) +#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) +#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) +#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) +#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) +#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) +#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) +#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) +#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) +#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) +#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) +#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) +#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) +#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) +#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) +#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) +#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) +#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) +#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) +#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) +#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) +#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) +#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) +#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) +#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) +#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) +#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) +#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) +#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) +#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) +#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) +#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) +#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) +#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) +#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) +#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) +#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) +#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) +#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) +#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) +#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) +#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) +#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) +#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) +#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) +#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) +#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) +#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) +#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) +#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) +#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) +#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) +#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) +#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) +#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) +#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) +#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) +#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) +#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) +#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) +#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) +#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) +#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) +#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) +#define PRS_ASYNC_PRORTC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0) +#define PRS_ASYNC_PRORTC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1) +#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) +#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) +#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) +#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) +#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) +#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) +#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) +#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) +#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) +#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) +#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) +#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) +#define PRS_ASYNC_PDML_PDMDSRPULSE (PRS_ASYNC_CH_CTRL_SOURCESEL_PDML | PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE) +#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) +#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) +#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) +#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) +#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) +#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) +#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) +#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) +#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) +#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA) +#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID) +#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_ASYNC_ETAMPDET_TAMPERSRCETAMPDET (PRS_ASYNC_CH_CTRL_SOURCESEL_ETAMPDET | PRS_ASYNC_CH_CTRL_SIGSEL_ETAMPDETTAMPERSRCETAMPDET) +#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT) +#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS) +#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX) +#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS) +#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV) +#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX) +#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC) +#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL) +#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL) +#define PRS_ASYNC_DCDC_MONO70NSANA (PRS_ASYNC_CH_CTRL_SOURCESEL_DCDC | PRS_ASYNC_CH_CTRL_SIGSEL_DCDCMONO70NSANA) +#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS) +#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX) +#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS) +#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV) +#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL) +#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX) +#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC) +#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL) +#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) +#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) +#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) + +/** + * Asynchronous signals and sources combined and aligned with register bit fields + * without the '_ASYNCH_' infix in order for backward compatibility: + */ +#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) +#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) +#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) +#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) +#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) +#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) +#define PRS_USART1_CS (PRS_ASYNC_USART1_CS) +#define PRS_USART1_IRTX (PRS_ASYNC_USART1_IRTX) +#define PRS_USART1_RTS (PRS_ASYNC_USART1_RTS) +#define PRS_USART1_RXDATA (PRS_ASYNC_USART1_RXDATA) +#define PRS_USART1_TX (PRS_ASYNC_USART1_TX) +#define PRS_USART1_TXC (PRS_ASYNC_USART1_TXC) +#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) +#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) +#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) +#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) +#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) +#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) +#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) +#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) +#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) +#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) +#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) +#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) +#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) +#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) +#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) +#define PRS_RTCC_CCV0 (PRS_ASYNC_RTCC_CCV0) +#define PRS_RTCC_CCV1 (PRS_ASYNC_RTCC_CCV1) +#define PRS_RTCC_CCV2 (PRS_ASYNC_RTCC_CCV2) +#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) +#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) +#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) +#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) +#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) +#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) +#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) +#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) +#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) +#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) +#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) +#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) +#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) +#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) +#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) +#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) +#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) +#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) +#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) +#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) +#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) +#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) +#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) +#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) +#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) +#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) +#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) +#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) +#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) +#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) +#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) +#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) +#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) +#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) +#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) +#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) +#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) +#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) +#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) +#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) +#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) +#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) +#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) +#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) +#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) +#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) +#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) +#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) +#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) +#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) +#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) +#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) +#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) +#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) +#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) +#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) +#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) +#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) +#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) +#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) +#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) +#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) +#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) +#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) +#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) +#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) +#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) +#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) +#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) +#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) +#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) +#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) +#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) +#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) +#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) +#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) +#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) +#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) +#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) +#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) +#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) +#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) +#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) +#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) +#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) +#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) +#define PRS_PRORTC_CCV0 (PRS_ASYNC_PRORTC_CCV0) +#define PRS_PRORTC_CCV1 (PRS_ASYNC_PRORTC_CCV1) +#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) +#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) +#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) +#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) +#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) +#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) +#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) +#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) +#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) +#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) +#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) +#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) +#define PRS_PDML_PDMDSRPULSE (PRS_ASYNC_PDML_PDMDSRPULSE) +#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) +#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) +#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) +#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) +#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) +#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) +#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) +#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) +#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) +#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA) +#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID) +#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) +#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) +#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) +#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) +#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) +#define PRS_ETAMPDET_TAMPERSRCETAMPDET (PRS_ASYNC_ETAMPDET_TAMPERSRCETAMPDET) +#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT) +#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS) +#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX) +#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS) +#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV) +#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX) +#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC) +#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL) +#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL) +#define PRS_DCDC_MONO70NSANA (PRS_ASYNC_DCDC_MONO70NSANA) +#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS) +#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX) +#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS) +#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV) +#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL) +#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX) +#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC) +#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL) +#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) +#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) +#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif // EFR32MG29_PRS_SIGNALS_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_rtcc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_rtcc.h new file mode 100644 index 000000000..ce19257f6 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_rtcc.h @@ -0,0 +1,422 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 RTCC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_RTCC_H +#define EFR32MG29_RTCC_H +#define RTCC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_RTCC RTCC + * @{ + * @brief EFR32MG29 RTCC Register Declaration. + *****************************************************************************/ + +/** RTCC CC Register Group Declaration. */ +typedef struct rtcc_cc_typedef{ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OCVALUE; /**< Output Compare Value Register */ + __IM uint32_t ICVALUE; /**< Input Capture Value Register */ +} RTCC_CC_TypeDef; + +/** RTCC Register Declaration. */ +typedef struct rtcc_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED0[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t IF_SET; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t COMBCNT_SET; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_SET[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t IF_CLR; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t COMBCNT_CLR; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_CLR[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED2[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t IF_TGL; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t COMBCNT_TGL; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_TGL[3U]; /**< Capture/Compare Channel */ +} RTCC_TypeDef; +/** @} End of group EFR32MG29_RTCC */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_RTCC + * @{ + * @defgroup EFR32MG29_RTCC_BitFields RTCC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for RTCC IPVERSION */ +#define _RTCC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for RTCC_IPVERSION */ +#define RTCC_IPVERSION_IPVERSION_DEFAULT (_RTCC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IPVERSION */ + +/* Bit fields for RTCC EN */ +#define _RTCC_EN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EN */ +#define _RTCC_EN_MASK 0x00000001UL /**< Mask for RTCC_EN */ +#define RTCC_EN_EN (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_EN_EN_SHIFT 0 /**< Shift value for RTCC_EN */ +#define _RTCC_EN_EN_MASK 0x1UL /**< Bit mask for RTCC_EN */ +#define _RTCC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EN */ +#define RTCC_EN_EN_DEFAULT (_RTCC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EN */ + +/* Bit fields for RTCC CFG */ +#define _RTCC_CFG_RESETVALUE 0x00000000UL /**< Default value for RTCC_CFG */ +#define _RTCC_CFG_MASK 0x000000FFUL /**< Mask for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _RTCC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for RTCC_CFG */ +#define _RTCC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_DEFAULT (_RTCC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_X0 (_RTCC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_X1 (_RTCC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for RTCC_CFG */ +#define RTCC_CFG_PRECNTCCV0TOP (0x1UL << 1) /**< Pre-counter CCV0 top value enable. */ +#define _RTCC_CFG_PRECNTCCV0TOP_SHIFT 1 /**< Shift value for RTCC_PRECNTCCV0TOP */ +#define _RTCC_CFG_PRECNTCCV0TOP_MASK 0x2UL /**< Bit mask for RTCC_PRECNTCCV0TOP */ +#define _RTCC_CFG_PRECNTCCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_PRECNTCCV0TOP_DEFAULT (_RTCC_CFG_PRECNTCCV0TOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTCCV1TOP (0x1UL << 2) /**< CCV1 top value enable */ +#define _RTCC_CFG_CNTCCV1TOP_SHIFT 2 /**< Shift value for RTCC_CNTCCV1TOP */ +#define _RTCC_CFG_CNTCCV1TOP_MASK 0x4UL /**< Bit mask for RTCC_CNTCCV1TOP */ +#define _RTCC_CFG_CNTCCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTCCV1TOP_DEFAULT (_RTCC_CFG_CNTCCV1TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTTICK (0x1UL << 3) /**< Counter prescaler mode. */ +#define _RTCC_CFG_CNTTICK_SHIFT 3 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CFG_CNTTICK_MASK 0x8UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CFG_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CFG */ +#define _RTCC_CFG_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_DEFAULT (_RTCC_CFG_CNTTICK_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_PRESC (_RTCC_CFG_CNTTICK_PRESC << 3) /**< Shifted mode PRESC for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_CCV0MATCH (_RTCC_CFG_CNTTICK_CCV0MATCH << 3) /**< Shifted mode CCV0MATCH for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DEFAULT (_RTCC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV1 (_RTCC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV2 (_RTCC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV4 (_RTCC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV8 (_RTCC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV16 (_RTCC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV32 (_RTCC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV64 (_RTCC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV128 (_RTCC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV256 (_RTCC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV512 (_RTCC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV1024 (_RTCC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV2048 (_RTCC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV4096 (_RTCC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV8192 (_RTCC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV16384 (_RTCC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV32768 (_RTCC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for RTCC_CFG */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000003UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_START (0x1UL << 0) /**< Start RTCC main counter */ +#define _RTCC_CMD_START_SHIFT 0 /**< Shift value for RTCC_START */ +#define _RTCC_CMD_START_MASK 0x1UL /**< Bit mask for RTCC_START */ +#define _RTCC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_START_DEFAULT (_RTCC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_STOP (0x1UL << 1) /**< Stop RTCC main counter */ +#define _RTCC_CMD_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ +#define _RTCC_CMD_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ +#define _RTCC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_STOP_DEFAULT (_RTCC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000003UL /**< Mask for RTCC_STATUS */ +#define RTCC_STATUS_RUNNING (0x1UL << 0) /**< RTCC running status */ +#define _RTCC_STATUS_RUNNING_SHIFT 0 /**< Shift value for RTCC_RUNNING */ +#define _RTCC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for RTCC_RUNNING */ +#define _RTCC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RUNNING_DEFAULT (_RTCC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_SHIFT 1 /**< Shift value for RTCC_RTCCLOCKSTATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_MASK 0x2UL /**< Bit mask for RTCC_RTCCLOCKSTATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_STATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT (_RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_LOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for RTCC_STATUS */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000003FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 1) /**< Main counter tick */ +#define _RTCC_IF_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000003FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 1) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _RTCC_SYNCBUSY_START_SHIFT 0 /**< Shift value for RTCC_START */ +#define _RTCC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for RTCC_START */ +#define _RTCC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_START_DEFAULT (_RTCC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _RTCC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ +#define _RTCC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ +#define _RTCC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_STOP_DEFAULT (_RTCC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_PRECNT_DEFAULT (_RTCC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _RTCC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for RTCC_CNT */ +#define _RTCC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for RTCC_CNT */ +#define _RTCC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CNT_DEFAULT (_RTCC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x000000FFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for RTCC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for RTCC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for RTCC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for RTCC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 4) /**< Capture compare channel comparison base. */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 4 /**< Shift value for RTCC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x10UL /**< Bit mask for RTCC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 4) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 4) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 5 /**< Shift value for RTCC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x60UL /**< Bit mask for RTCC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 5) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 5) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 5) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 5) /**< Shifted mode NONE for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_OC_SHIFT 0 /**< Shift value for RTCC_OC */ +#define _RTCC_CC_OCVALUE_OC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_OC */ +#define _RTCC_CC_OCVALUE_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_OCVALUE */ +#define RTCC_CC_OCVALUE_OC_DEFAULT (_RTCC_CC_OCVALUE_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_OCVALUE */ + +/* Bit fields for RTCC CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_IC_SHIFT 0 /**< Shift value for RTCC_IC */ +#define _RTCC_CC_ICVALUE_IC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IC */ +#define _RTCC_CC_ICVALUE_IC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_ICVALUE */ +#define RTCC_CC_ICVALUE_IC_DEFAULT (_RTCC_CC_ICVALUE_IC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_ICVALUE */ + +/** @} End of group EFR32MG29_RTCC_BitFields */ +/** @} End of group EFR32MG29_RTCC */ +/** @} End of group Parts */ + +#endif // EFR32MG29_RTCC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_semailbox.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_semailbox.h new file mode 100644 index 000000000..887770751 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_semailbox.h @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 SEMAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_SEMAILBOX_H +#define EFR32MG29_SEMAILBOX_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_SEMAILBOX_HOST SEMAILBOX_HOST + * @{ + * @brief EFR32MG29 SEMAILBOX_HOST Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_HOST Register Declaration. */ +typedef struct semailbox_host_typedef{ + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_HOST_TypeDef; +/** @} End of group EFR32MG29_SEMAILBOX_HOST */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_SEMAILBOX_HOST + * @{ + * @defgroup EFR32MG29_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ + +/* Bit fields for SEMAILBOX TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ + +/* Bit fields for SEMAILBOX RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ + +/* Bit fields for SEMAILBOX TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ + +/* Bit fields for SEMAILBOX RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ + +/* Bit fields for SEMAILBOX TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ + +/* Bit fields for SEMAILBOX RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ + +/* Bit fields for SEMAILBOX CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ + +/** @} End of group EFR32MG29_SEMAILBOX_HOST_BitFields */ +/** @} End of group EFR32MG29_SEMAILBOX_HOST */ +/**************************************************************************//** + * @defgroup EFR32MG29_SEMAILBOX_APBSE SEMAILBOX_APBSE + * @{ + * @brief EFR32MG29 SEMAILBOX_APBSE Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_APBSE Register Declaration. */ +typedef struct semailbox_apbse_typedef{ + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_APBSE_TypeDef; +/** @} End of group EFR32MG29_SEMAILBOX_APBSE */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_SEMAILBOX_APBSE + * @{ + * @defgroup EFR32MG29_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ + +/** @} End of group EFR32MG29_SEMAILBOX_APBSE_BitFields */ +/** @} End of group EFR32MG29_SEMAILBOX_APBSE */ +/** @} End of group Parts */ + +#endif // EFR32MG29_SEMAILBOX_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_smu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_smu.h new file mode 100644 index 000000000..131e35caa --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_smu.h @@ -0,0 +1,1358 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 SMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_SMU_H +#define EFR32MG29_SMU_H +#define SMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_SMU SMU + * @{ + * @brief EFR32MG29 SMU Register Declaration. + *****************************************************************************/ + +/** SMU Register Declaration. */ +typedef struct smu_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t LOCK; /**< Lock */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1; /**< PPU Privileged Access 1 */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1; /**< PPU Secure Access 1 */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< PPU Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR; /**< BMPU Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< ESAU Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t LOCK_SET; /**< Lock */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1_SET; /**< PPU Privileged Access 1 */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1_SET; /**< PPU Secure Access 1 */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< PPU Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< BMPU Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< ESAU Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_SET; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_SET; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1_CLR; /**< PPU Privileged Access 1 */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1_CLR; /**< PPU Secure Access 1 */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< PPU Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< BMPU Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< ESAU Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_CLR; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_CLR; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t LOCK_TGL; /**< Lock */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< PPU Privileged Access 0 */ + __IOM uint32_t PPUPATD1_TGL; /**< PPU Privileged Access 1 */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< PPU Secure Access 0 */ + __IOM uint32_t PPUSATD1_TGL; /**< PPU Secure Access 1 */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< PPU Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< BMPU Privileged Attribute 0 */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< BMPU Secure Attribute 0 */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< BMPU Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< ESAU Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< ESAU Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_TGL; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_TGL; /**< ESAU Movable Region Boundary 5-6 */ +} SMU_TypeDef; +/** @} End of group EFR32MG29_SMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_SMU + * @{ + * @defgroup EFR32MG29_SMU_BitFields SMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000009UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000009UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ + +/* Bit fields for SMU STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ + +/* Bit fields for SMU LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< LOCKSVTAIRCR control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< LOCKNSVTOR control of M33 CPU */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< LOCKSMPU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< LOCKNSMPU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< LOCKSAU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFXO0_DEFAULT (_SMU_PPUPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ +#define _SMU_PPUPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART1_DEFAULT (_SMU_PPUPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ +#define _SMU_PPUPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUPATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC (0x1UL << 31) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD0_DCDC_SHIFT 31 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_MASK 0x80000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x0003FFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x0003FFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PDM (0x1UL << 0) /**< PDM Privileged Access */ +#define _SMU_PPUPATD1_PDM_SHIFT 0 /**< Shift value for SMU_PDM */ +#define _SMU_PPUPATD1_PDM_MASK 0x1UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUPATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RFSENSE (0x1UL << 1) /**< RFSENSE Privileged Access */ +#define _SMU_PPUPATD1_RFSENSE_SHIFT 1 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUPATD1_RFSENSE_MASK 0x2UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUPATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RFSENSE_DEFAULT (_SMU_PPUPATD1_RFSENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ETAMPDET (0x1UL << 2) /**< ETAMPDET Privileged Access */ +#define _SMU_PPUPATD1_ETAMPDET_SHIFT 2 /**< Shift value for SMU_ETAMPDET */ +#define _SMU_PPUPATD1_ETAMPDET_MASK 0x4UL /**< Bit mask for SMU_ETAMPDET */ +#define _SMU_PPUPATD1_ETAMPDET_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ETAMPDET_DEFAULT (_SMU_PPUPATD1_ETAMPDET_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART1 (0x1UL << 4) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD1_EUSART1_SHIFT 4 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD1_EUSART1_MASK 0x10UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART1_DEFAULT (_SMU_PPUPATD1_EUSART1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 5) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 5 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x20UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 6) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 6 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x40UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 7) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 7 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x80UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 8) /**< RTCC Privileged Access */ +#define _SMU_PPUPATD1_RTCC_SHIFT 8 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x100UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 9) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 9 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x200UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 10) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 10 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x400UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 11) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 11 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x800UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 12) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 12 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x1000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 13) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 13 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x2000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 14) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 14 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x4000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0 (0x1UL << 15) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD1_EUSART0_SHIFT 15 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_MASK 0x8000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 16) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 16 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x10000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 17) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 17 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x20000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFXO0_DEFAULT (_SMU_PPUSATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 5) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 7) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 8) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 10) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 12) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 13) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 14) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 21) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART1 (0x1UL << 22) /**< USART1 Secure Access */ +#define _SMU_PPUSATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUSATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUSATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART1_DEFAULT (_SMU_PPUSATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 23) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 24) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Secure Access */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 28) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Secure Access */ +#define _SMU_PPUSATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUSATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUSATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_IFADCDEBUG_DEFAULT (_SMU_PPUSATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 30) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC (0x1UL << 31) /**< DCDC Secure Access */ +#define _SMU_PPUSATD0_DCDC_SHIFT 31 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_MASK 0x80000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ + +/* Bit fields for SMU PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x0003FFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x0003FFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PDM (0x1UL << 0) /**< PDM Secure Access */ +#define _SMU_PPUSATD1_PDM_SHIFT 0 /**< Shift value for SMU_PDM */ +#define _SMU_PPUSATD1_PDM_MASK 0x1UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUSATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PDM_DEFAULT (_SMU_PPUSATD1_PDM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RFSENSE (0x1UL << 1) /**< RFSENSE Secure Access */ +#define _SMU_PPUSATD1_RFSENSE_SHIFT 1 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUSATD1_RFSENSE_MASK 0x2UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUSATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RFSENSE_DEFAULT (_SMU_PPUSATD1_RFSENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ETAMPDET (0x1UL << 2) /**< ETAMPDET Secure Access */ +#define _SMU_PPUSATD1_ETAMPDET_SHIFT 2 /**< Shift value for SMU_ETAMPDET */ +#define _SMU_PPUSATD1_ETAMPDET_MASK 0x4UL /**< Bit mask for SMU_ETAMPDET */ +#define _SMU_PPUSATD1_ETAMPDET_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ETAMPDET_DEFAULT (_SMU_PPUSATD1_ETAMPDET_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM (0x1UL << 3) /**< DMEM Secure Access */ +#define _SMU_PPUSATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART1 (0x1UL << 4) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD1_EUSART1_SHIFT 4 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD1_EUSART1_MASK 0x10UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART1_DEFAULT (_SMU_PPUSATD1_EUSART1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 5) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 5 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x20UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 6) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 6 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x40UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 7) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 7 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x80UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RTCC (0x1UL << 8) /**< RTCC Secure Access */ +#define _SMU_PPUSATD1_RTCC_SHIFT 8 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUSATD1_RTCC_MASK 0x100UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUSATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RTCC_DEFAULT (_SMU_PPUSATD1_RTCC_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 9) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 9 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x200UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 10) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 10 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x400UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 11) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 11 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x800UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 12) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 12 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x1000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 13) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 13 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x2000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 14) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 14 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x4000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0 (0x1UL << 15) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD1_EUSART0_SHIFT 15 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_MASK 0x8000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 16) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 16 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x10000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 17) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 17 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x20000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ + +/* Bit fields for SMU BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOIFADCDEBUG (0x1UL << 2) /**< RADIOIFADCDEBUG Privileged Mode */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_SHIFT 2 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_MASK 0x4UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 3) /**< LDMA Privileged Mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 3 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x8UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 4) /**< SEEXTDMA Privileged Mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 4 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x10UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ + +/* Bit fields for SMU BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Secure Mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Secure Mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOIFADCDEBUG (0x1UL << 2) /**< RADIOIFADCDEBUG Secure Mode */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_SHIFT 2 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_MASK 0x4UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 3) /**< LDMA Secure Mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 3 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x8UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 4) /**< SEEXTDMA Secure Mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 4 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x10UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ + +/* Bit fields for SMU BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ + +/* Bit fields for SMU BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ + +/* Bit fields for SMU ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ + +/* Bit fields for SMU ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ + +/* Bit fields for SMU ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ + +/* Bit fields for SMU ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ + +/* Bit fields for SMU ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ + +/* Bit fields for SMU ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ + +/** @} End of group EFR32MG29_SMU_BitFields */ +/** @} End of group EFR32MG29_SMU */ +/**************************************************************************//** + * @defgroup EFR32MG29_SMU_CFGNS SMU_CFGNS + * @{ + * @brief EFR32MG29 SMU_CFGNS Register Declaration. + *****************************************************************************/ + +/** SMU_CFGNS Register Declaration. */ +typedef struct smu_cfgns_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK; /**< Non-Secure Lock */ + __IOM uint32_t NSIF; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_SET; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_SET; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_SET; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1_SET; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_CLR; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_CLR; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_CLR; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1_CLR; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_TGL; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_TGL; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_TGL; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< PPU Non-Secure Privileged Access 0 */ + __IOM uint32_t PPUNSPATD1_TGL; /**< PPU Non-Secure Privileged Access 1 */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< BMPU Non-Secure Privileged Attribute 0 */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ +} SMU_CFGNS_TypeDef; +/** @} End of group EFR32MG29_SMU_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_SMU_CFGNS + * @{ + * @defgroup EFR32MG29_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock Status */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ + +/* Bit fields for SMU NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ + +/* Bit fields for SMU NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ + +/* Bit fields for SMU NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ + +/* Bit fields for SMU PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFXO0_DEFAULT (_SMU_PPUNSPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ +#define _SMU_PPUNSPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUNSPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUNSPATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART1_DEFAULT (_SMU_PPUNSPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC (0x1UL << 31) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD0_DCDC_SHIFT 31 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_MASK 0x80000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ + +/* Bit fields for SMU PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x0003FFFFUL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x0003FFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PDM (0x1UL << 0) /**< PDM Privileged Access */ +#define _SMU_PPUNSPATD1_PDM_SHIFT 0 /**< Shift value for SMU_PDM */ +#define _SMU_PPUNSPATD1_PDM_MASK 0x1UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUNSPATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PDM_DEFAULT (_SMU_PPUNSPATD1_PDM_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RFSENSE (0x1UL << 1) /**< RFSENSE Privileged Access */ +#define _SMU_PPUNSPATD1_RFSENSE_SHIFT 1 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUNSPATD1_RFSENSE_MASK 0x2UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUNSPATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RFSENSE_DEFAULT (_SMU_PPUNSPATD1_RFSENSE_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ETAMPDET (0x1UL << 2) /**< ETAMPDET Privileged Access */ +#define _SMU_PPUNSPATD1_ETAMPDET_SHIFT 2 /**< Shift value for SMU_ETAMPDET */ +#define _SMU_PPUNSPATD1_ETAMPDET_MASK 0x4UL /**< Bit mask for SMU_ETAMPDET */ +#define _SMU_PPUNSPATD1_ETAMPDET_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ETAMPDET_DEFAULT (_SMU_PPUNSPATD1_ETAMPDET_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUNSPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART1 (0x1UL << 4) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART1_SHIFT 4 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD1_EUSART1_MASK 0x10UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD1_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART1_DEFAULT (_SMU_PPUNSPATD1_EUSART1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 5) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 5 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x20UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 6) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 6 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x40UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 7) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 7 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x80UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RTCC (0x1UL << 8) /**< RTCC Privileged Access */ +#define _SMU_PPUNSPATD1_RTCC_SHIFT 8 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUNSPATD1_RTCC_MASK 0x100UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUNSPATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RTCC_DEFAULT (_SMU_PPUNSPATD1_RTCC_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 9) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 9 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x200UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 10) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 10 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x400UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 11) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 11 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x800UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 12) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 12 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x1000UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 13) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 13 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x2000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 14) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 14 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x4000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 15) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART0_SHIFT 15 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_MASK 0x8000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 16) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 16 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x10000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 17) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 17 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x20000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ + +/* Bit fields for SMU PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ + +/* Bit fields for SMU BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIOAES Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIOSUBSYSTEM Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG (0x1UL << 2) /**< RADIOIFADCDEBUG Privileged Mode */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_SHIFT 2 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_MASK 0x4UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 3) /**< LDMA Privileged Mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 3 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x8UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 4) /**< SEEXTDMA Privileged Mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 4 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x10UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ + +/** @} End of group EFR32MG29_SMU_CFGNS_BitFields */ +/** @} End of group EFR32MG29_SMU_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32MG29_SMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_syscfg.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_syscfg.h new file mode 100644 index 000000000..3a1a0cead --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_syscfg.h @@ -0,0 +1,739 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 SYSCFG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_SYSCFG_H +#define EFR32MG29_SYSCFG_H +#define SYSCFG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_SYSCFG SYSCFG + * @{ + * @brief EFR32MG29 SYSCFG Register Declaration. + *****************************************************************************/ + +/** SYSCFG Register Declaration. */ +typedef struct syscfg_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV; /**< Chip Revision */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ + uint32_t RESERVED2[55U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ + uint32_t RESERVED6[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ + uint32_t RESERVED7[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */ + uint32_t RESERVED10[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[635U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_SET; /**< Chip Revision */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ + uint32_t RESERVED15[55U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ + uint32_t RESERVED19[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ + uint32_t RESERVED20[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */ + uint32_t RESERVED23[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[635U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_CLR; /**< Chip Revision */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ + uint32_t RESERVED32[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ + uint32_t RESERVED33[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */ + uint32_t RESERVED36[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + uint32_t RESERVED38[635U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_TGL; /**< Chip Revision */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ + uint32_t RESERVED41[55U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + uint32_t RESERVED43[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ + uint32_t RESERVED45[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ + uint32_t RESERVED46[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO SEQRAM Retention Control */ + uint32_t RESERVED47[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO SEQRAM ECC Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */ + uint32_t RESERVED49[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ +} SYSCFG_TypeDef; +/** @} End of group EFR32MG29_SYSCFG */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_SYSCFG + * @{ + * @defgroup EFR32MG29_SYSCFG_BitFields SYSCFG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG IPVERSION */ +#define _SYSCFG_IPVERSION_RESETVALUE 0x0000000BUL /**< Default value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x0000000BUL /**< Mode DEFAULT for SYSCFG_IPVERSION */ +#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ + +/* Bit fields for SYSCFG IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x33003F0FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ +#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ +#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ +#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ +#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ +#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ +#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-Bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-Bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-Bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-Bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ + +/* Bit fields for SYSCFG IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x33003F0FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ +#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ +#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ +#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ +#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ +#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ +#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ + +/* Bit fields for SYSCFG CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00010014UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT 0x00000014UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREVHW_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ + +/* Bit fields for SYSCFG CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_PARTNUMBER_SHIFT 0 /**< Shift value for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREV_PARTNUMBER_MASK 0xFFFUL /**< Bit mask for SYSCFG_PARTNUMBER */ +#define _SYSCFG_CHIPREV_PARTNUMBER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_PARTNUMBER_DEFAULT (_SYSCFG_CHIPREV_PARTNUMBER_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 16 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0xF0000UL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ + +/* Bit fields for SYSCFG CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ + +/* Bit fields for SYSCFG CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ + +/* Bit fields for SYSCFG DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0xFFFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00008000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x0000C000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x0000E000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x0000F000UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x0000F800UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x0000FC00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x0000FE00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x0000FF00UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x0000FF80UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x0000FFC0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x0000FFE0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x0000FFF0UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x0000FFF8UL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x0000FFFCUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x0000FFFEUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF 0x0000FFFFUL /**< Mode ALLOFF for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_DMEM0RETNCTRL*/ + +/* Bit fields for SYSCFG RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ + +/* Bit fields for SYSCFG RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ + +/* Bit fields for SYSCFG RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ + +/* Bit fields for SYSCFG SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ + +/* Bit fields for SYSCFG FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ + +/* Bit fields for SYSCFG ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ + +/* Bit fields for SYSCFG DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00000055UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x000000FFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_SHIFT 6 /**< Shift value for SYSCFG_IFADCDEBUGPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_IFADCDEBUGPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ + +/* Bit fields for SYSCFG ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ + +/* Bit fields for SYSCFG ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ + +/* Bit fields for SYSCFG ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0117UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK (0x1UL << 4) /**< Root Mode Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_SHIFT 4 /**< Shift value for SYSCFG_ROOTMODELOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_MASK 0x10UL /**< Bit mask for SYSCFG_ROOTMODELOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 16) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 17) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 18) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 19) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 20) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ + +/* Bit fields for SYSCFG ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ +#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ + +/** @} End of group EFR32MG29_SYSCFG_BitFields */ +/** @} End of group EFR32MG29_SYSCFG */ +/**************************************************************************//** + * @defgroup EFR32MG29_SYSCFG_CFGNS SYSCFG_CFGNS + * @{ + * @brief EFR32MG29 SYSCFG_CFGNS Register Declaration. + *****************************************************************************/ + +/** SYSCFG_CFGNS Register Declaration. */ +typedef struct syscfg_cfgns_typedef{ + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED1[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[637U]; /**< Reserved for future use */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED5[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[637U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED9[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[637U]; /**< Reserved for future use */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED13[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} SYSCFG_CFGNS_TypeDef; +/** @} End of group EFR32MG29_SYSCFG_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_SYSCFG_CFGNS + * @{ + * @defgroup EFR32MG29_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ +#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ +#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ + +/* Bit fields for SYSCFG ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ +#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ + +/* Bit fields for SYSCFG ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ +#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ + +/** @} End of group EFR32MG29_SYSCFG_CFGNS_BitFields */ +/** @} End of group EFR32MG29_SYSCFG_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32MG29_SYSCFG_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_timer.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_timer.h new file mode 100644 index 000000000..d0bd0c0dc --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_timer.h @@ -0,0 +1,1015 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 TIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_TIMER_H +#define EFR32MG29_TIMER_H +#define TIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_TIMER TIMER + * @{ + * @brief EFR32MG29 TIMER Register Declaration. + *****************************************************************************/ + +/** TIMER CC Register Group Declaration. */ +typedef struct timer_cc_typedef{ + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} TIMER_CC_TypeDef; + +/** TIMER Register Declaration. */ +typedef struct timer_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; +/** @} End of group EFR32MG29_TIMER */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_TIMER + * @{ + * @defgroup EFR32MG29_TIMER_BitFields TIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ + +/* Bit fields for TIMER CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000001UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ + +/* Bit fields for TIMER CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ + +/* Bit fields for TIMER CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ + +/* Bit fields for TIMER CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ + +/* Bit fields for TIMER CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ + +/* Bit fields for TIMER DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ + +/* Bit fields for TIMER DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ + +/* Bit fields for TIMER DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32MG29_TIMER_BitFields */ +/** @} End of group EFR32MG29_TIMER */ +/** @} End of group Parts */ + +#endif // EFR32MG29_TIMER_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ulfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ulfrco.h new file mode 100644 index 000000000..67041f944 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_ulfrco.h @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 ULFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_ULFRCO_H +#define EFR32MG29_ULFRCO_H +#define ULFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_ULFRCO ULFRCO + * @{ + * @brief EFR32MG29 ULFRCO Register Declaration. + *****************************************************************************/ + +/** ULFRCO Register Declaration. */ +typedef struct ulfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} ULFRCO_TypeDef; +/** @} End of group EFR32MG29_ULFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_ULFRCO + * @{ + * @defgroup EFR32MG29_ULFRCO_BitFields ULFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ULFRCO IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ + +/* Bit fields for ULFRCO STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ + +/* Bit fields for ULFRCO IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ + +/* Bit fields for ULFRCO IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ + +/** @} End of group EFR32MG29_ULFRCO_BitFields */ +/** @} End of group EFR32MG29_ULFRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG29_ULFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_usart.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_usart.h new file mode 100644 index 000000000..af87e1a6d --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_usart.h @@ -0,0 +1,1431 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 USART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_USART_H +#define EFR32MG29_USART_H +#define USART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_USART USART + * @{ + * @brief EFR32MG29 USART Register Declaration. + *****************************************************************************/ + +/** USART Register Declaration. */ +typedef struct usart_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +} USART_TypeDef; +/** @} End of group EFR32MG29_USART */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_USART + * @{ + * @defgroup EFR32MG29_USART_BitFields USART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for USART IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ + +/* Bit fields for USART EN */ +#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ +#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ +#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ +#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ +#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ + +/** @} End of group EFR32MG29_USART_BitFields */ +/** @} End of group EFR32MG29_USART */ +/** @} End of group Parts */ + +#endif // EFR32MG29_USART_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_wdog.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_wdog.h new file mode 100644 index 000000000..3a063251a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29_wdog.h @@ -0,0 +1,361 @@ +/**************************************************************************//** + * @file + * @brief EFR32MG29 WDOG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29_WDOG_H +#define EFR32MG29_WDOG_H +#define WDOG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG29_WDOG WDOG + * @{ + * @brief EFR32MG29 WDOG Register Declaration. + *****************************************************************************/ + +/** WDOG Register Declaration. */ +typedef struct wdog_typedef{ + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} WDOG_TypeDef; +/** @} End of group EFR32MG29_WDOG */ + +/**************************************************************************//** + * @addtogroup EFR32MG29_WDOG + * @{ + * @defgroup EFR32MG29_WDOG_BitFields WDOG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ + +/* Bit fields for WDOG EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000001UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ + +/* Bit fields for WDOG CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F071FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 1) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 1 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x2UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 2) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 2 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x4UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 3) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 3 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x8UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 4) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 4 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x10UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/* Bit fields for WDOG LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/** @} End of group EFR32MG29_WDOG_BitFields */ +/** @} End of group EFR32MG29_WDOG */ +/** @} End of group Parts */ + +#endif // EFR32MG29_WDOG_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b140f1024im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b140f1024im40.h new file mode 100644 index 000000000..5a323ecc8 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b140f1024im40.h @@ -0,0 +1,1471 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG29B140F1024IM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29B140F1024IM40_H +#define EFR32MG29B140F1024IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG29B140F1024IM40 EFR32MG29B140F1024IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG29 Peripheral Interrupt Numbers ******************************************/ + + SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ + SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ + EMUEFP_IRQn = 7, /*!< 7 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 8, /*!< 8 EFR32 DCDC Interrupt */ + ETAMPDET_IRQn = 9, /*!< 9 EFR32 ETAMPDET Interrupt */ + TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 11, /*!< 11 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 12, /*!< 12 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 13, /*!< 13 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 14, /*!< 14 EFR32 TIMER4 Interrupt */ + RTCC_IRQn = 15, /*!< 15 EFR32 RTCC Interrupt */ + USART0_RX_IRQn = 16, /*!< 16 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 17, /*!< 17 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 18, /*!< 18 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 19, /*!< 19 EFR32 USART1_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + ICACHE0_IRQn = 22, /*!< 22 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 23, /*!< 23 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 24, /*!< 24 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 25, /*!< 25 EFR32 SYSCFG Interrupt */ + LDMA_IRQn = 26, /*!< 26 EFR32 LDMA Interrupt */ + LFXO_IRQn = 27, /*!< 27 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 28, /*!< 28 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 29, /*!< 29 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 30, /*!< 30 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 31, /*!< 31 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 32, /*!< 32 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 33, /*!< 33 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 34, /*!< 34 EFR32 EMUDG Interrupt */ + EMUSE_IRQn = 35, /*!< 35 EFR32 EMUSE Interrupt */ + AGC_IRQn = 36, /*!< 36 EFR32 AGC Interrupt */ + BUFC_IRQn = 37, /*!< 37 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 38, /*!< 38 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 39, /*!< 39 EFR32 FRC Interrupt */ + MODEM_IRQn = 40, /*!< 40 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 41, /*!< 41 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 42, /*!< 42 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 43, /*!< 43 EFR32 RAC_SEQ Interrupt */ + RDMAILBOX_IRQn = 44, /*!< 44 EFR32 RDMAILBOX Interrupt */ + RFSENSE_IRQn = 45, /*!< 45 EFR32 RFSENSE Interrupt */ + SYNTH_IRQn = 46, /*!< 46 EFR32 SYNTH Interrupt */ + PRORTC_IRQn = 47, /*!< 47 EFR32 PRORTC Interrupt */ + ACMP0_IRQn = 48, /*!< 48 EFR32 ACMP0 Interrupt */ + WDOG0_IRQn = 49, /*!< 49 EFR32 WDOG0 Interrupt */ + HFXO0_IRQn = 50, /*!< 50 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 51, /*!< 51 EFR32 HFRCO0 Interrupt */ + CMU_IRQn = 52, /*!< 52 EFR32 CMU Interrupt */ + AES_IRQn = 53, /*!< 53 EFR32 AES Interrupt */ + IADC_IRQn = 54, /*!< 54 EFR32 IADC Interrupt */ + MSC_IRQn = 55, /*!< 55 EFR32 MSC Interrupt */ + DPLL0_IRQn = 56, /*!< 56 EFR32 DPLL0 Interrupt */ + PDM_IRQn = 57, /*!< 57 EFR32 PDM Interrupt */ + SW0_IRQn = 58, /*!< 58 EFR32 SW0 Interrupt */ + SW1_IRQn = 59, /*!< 59 EFR32 SW1 Interrupt */ + SW2_IRQn = 60, /*!< 60 EFR32 SW2 Interrupt */ + SW3_IRQn = 61, /*!< 61 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 62, /*!< 62 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 63, /*!< 63 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 64, /*!< 64 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 65, /*!< 65 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 66, /*!< 66 EFR32 FPUEXH Interrupt */ + MPAHBRAM_IRQn = 67, /*!< 67 EFR32 MPAHBRAM Interrupt */ + EUSART1_RX_IRQn = 68, /*!< 68 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 69, /*!< 69 EFR32 EUSART1_TX Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG29B140F1024IM40_Core EFR32MG29B140F1024IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG29B140F1024IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG29B140F1024IM40_Part EFR32MG29B140F1024IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG29B140F1024IM40) +#define EFR32MG29B140F1024IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG29B140F1024IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_9 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 9 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 8 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x080FFFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x080FFFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG29B140F1024IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define ETAMPDET_ETAMPIN0_PORT GPIO_PB_INDEX /**< Port of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN0_PIN 1U /**< Pin of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN1_PORT GPIO_PC_INDEX /**< Port of ETAMPIN1.*/ +#define ETAMPDET_ETAMPIN1_PIN 0U /**< Pin of ETAMPIN1.*/ +#define ETAMPDET_ETAMPOUT0_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT0_PIN 1U /**< Pin of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT1_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT1.*/ +#define ETAMPDET_ETAMPOUT1_PIN 2U /**< Pin of ETAMPOUT1.*/ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 0U /**< Pin of THMSW_HALFSWITCH.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 1 /** 1 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define ETAMPDET_PRESENT /** ETAMPDET is available in this part */ +#define ETAMPDET_COUNT 1 /** 1 ETAMPDETs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PDM_PRESENT /** PDM is available in this part */ +#define PDM_COUNT 1 /** 1 PDMs available */ +#define PRORTC_PRESENT /** PRORTC is available in this part */ +#define PRORTC_COUNT 1 /** 1 PRORTCs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define RTCC_PRESENT /** RTCC is available in this part */ +#define RTCC_COUNT 1 /** 1 RTCCs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 2 /** 2 USARTs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 1 /** 1 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg29.h" /* System Header File */ + +/** @} End of group EFR32MG29B140F1024IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG29B140F1024IM40_Peripheral_TypeDefs EFR32MG29B140F1024IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg29_emu.h" +#include "efr32mg29_cmu.h" +#include "efr32mg29_hfxo.h" +#include "efr32mg29_hfrco.h" +#include "efr32mg29_fsrco.h" +#include "efr32mg29_dpll.h" +#include "efr32mg29_lfxo.h" +#include "efr32mg29_lfrco.h" +#include "efr32mg29_ulfrco.h" +#include "efr32mg29_msc.h" +#include "efr32mg29_icache.h" +#include "efr32mg29_prs.h" +#include "efr32mg29_gpio.h" +#include "efr32mg29_ldma.h" +#include "efr32mg29_ldmaxbar.h" +#include "efr32mg29_timer.h" +#include "efr32mg29_usart.h" +#include "efr32mg29_burtc.h" +#include "efr32mg29_i2c.h" +#include "efr32mg29_syscfg.h" +#include "efr32mg29_buram.h" +#include "efr32mg29_gpcrc.h" +#include "efr32mg29_dcdc.h" +#include "efr32mg29_pdm.h" +#include "efr32mg29_etampdet.h" +#include "efr32mg29_mpahbram.h" +#include "efr32mg29_eusart.h" +#include "efr32mg29_aes.h" +#include "efr32mg29_smu.h" +#include "efr32mg29_rtcc.h" +#include "efr32mg29_wdog.h" +#include "efr32mg29_letimer.h" +#include "efr32mg29_iadc.h" +#include "efr32mg29_acmp.h" +#include "efr32mg29_semailbox.h" +#include "efr32mg29_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg29_prs_signals.h" +#include "efr32mg29_dma_descriptor.h" +#include "efr32mg29_ldmaxbar_defines.h" + +/** @} End of group EFR32MG29B140F1024IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG29B140F1024IM40_Peripheral_Base EFR32MG29B140F1024IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ +#define ETAMPDET_S_BASE (0x400A4000UL) /* ETAMPDET_S base address */ +#define DMEM_S_BASE (0x400B0000UL) /* DMEM_S base address */ +#define EUSART1_S_BASE (0x400B4000UL) /* EUSART1_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ +#define WDOG0_S_BASE (0x48018000UL) /* WDOG0_S base address */ +#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ +#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ +#define EUSART0_S_BASE (0x4A040000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ +#define ETAMPDET_NS_BASE (0x500A4000UL) /* ETAMPDET_NS base address */ +#define DMEM_NS_BASE (0x500B0000UL) /* DMEM_NS base address */ +#define EUSART1_NS_BASE (0x500B4000UL) /* EUSART1_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ +#define WDOG0_NS_BASE (0x58018000UL) /* WDOG0_NS base address */ +#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ +#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ +#define EUSART0_NS_BASE (0x5A040000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) +#define PDM_BASE (PDM_S_BASE) /* PDM base address */ +#else +#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) +#define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ +#else +#define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) +#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ +#else +#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) +#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ +#else +#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG29B140F1024IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG29B140F1024IM40_Peripheral_Declaration EFR32MG29B140F1024IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ +#define ETAMPDET_S ((ETAMPDET_TypeDef *) ETAMPDET_S_BASE) /**< ETAMPDET_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ +#define ETAMPDET_NS ((ETAMPDET_TypeDef *) ETAMPDET_NS_BASE) /**< ETAMPDET_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ +#define ETAMPDET ((ETAMPDET_TypeDef *) ETAMPDET_BASE) /**< ETAMPDET base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG29B140F1024IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG29B140F1024IM40_Peripheral_Parameters EFR32MG29B140F1024IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x90UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define HFRCO0_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x100000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x1UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x5UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x0UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x4UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_PARTNUMBER 0x4UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_RAM0_INST_COUNT 0x10UL /**> None */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define PDM_FIFO_LEN 0x4UL /**> New Param */ +#define PDM_NUM_CH 0x2UL /**> None */ +#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ +#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ +#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ +#define PDM_PIPELINE 0x0UL /**> None */ +#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ +#define ETAMPDET_NUM_CHNLS 0x2UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_EXCLUDE_DALI 0x0UL /**> Exclude DALI */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x32UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x12UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x12UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define RTCC_CC_NUM 0x3UL /**> None */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x0UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x0UL /**> None */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_EXCLUDE_DALI 0x1UL /**> Exclude DALI */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ +#define PRORTC_CC_NUM 0x2UL /**> None */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_EXCLUDE_DALI(n) (((n) == 0) ? EUSART0_EXCLUDE_DALI \ + : ((n) == 1) ? EUSART1_EXCLUDE_DALI \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for IADC */ +#define IADC(n) (((n) == 0) ? IADC0 \ + : 0x0UL) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 \ + : -1) +#define IADC_CONFIGNUM(n) (((n) == 0) ? IADC0_CONFIGNUM \ + : 0x0UL) +#define IADC_FULLRANGEUNIPOLAR(n) (((n) == 0) ? IADC0_FULLRANGEUNIPOLAR \ + : 0x0UL) +#define IADC_SCANBYTES(n) (((n) == 0) ? IADC0_SCANBYTES \ + : 0x0UL) +#define IADC_ENTRIES(n) (((n) == 0) ? IADC0_ENTRIES \ + : 0x0UL) + +/* Instance macros for LETIMER */ +#define LETIMER(n) (((n) == 0) ? LETIMER0 \ + : 0x0UL) +#define LETIMER_NUM(ref) (((ref) == LETIMER0) ? 0 \ + : -1) +#define LETIMER_CNT_WIDTH(n) (((n) == 0) ? LETIMER0_CNT_WIDTH \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG29B140F1024IM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG29B140F1024IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b230f1024cm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b230f1024cm40.h new file mode 100644 index 000000000..7aacce8e6 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/efr32mg29b230f1024cm40.h @@ -0,0 +1,1470 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG29B230F1024CM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG29B230F1024CM40_H +#define EFR32MG29B230F1024CM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG29B230F1024CM40 EFR32MG29B230F1024CM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG29 Peripheral Interrupt Numbers ******************************************/ + + SETAMPERHOST_IRQn = 0, /*!< 0 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 1, /*!< 1 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 2, /*!< 2 EFR32 SEMBTX Interrupt */ + SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ + EMUEFP_IRQn = 7, /*!< 7 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 8, /*!< 8 EFR32 DCDC Interrupt */ + ETAMPDET_IRQn = 9, /*!< 9 EFR32 ETAMPDET Interrupt */ + TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 11, /*!< 11 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 12, /*!< 12 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 13, /*!< 13 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 14, /*!< 14 EFR32 TIMER4 Interrupt */ + RTCC_IRQn = 15, /*!< 15 EFR32 RTCC Interrupt */ + USART0_RX_IRQn = 16, /*!< 16 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 17, /*!< 17 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 18, /*!< 18 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 19, /*!< 19 EFR32 USART1_TX Interrupt */ + EUSART0_RX_IRQn = 20, /*!< 20 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 21, /*!< 21 EFR32 EUSART0_TX Interrupt */ + ICACHE0_IRQn = 22, /*!< 22 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 23, /*!< 23 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 24, /*!< 24 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 25, /*!< 25 EFR32 SYSCFG Interrupt */ + LDMA_IRQn = 26, /*!< 26 EFR32 LDMA Interrupt */ + LFXO_IRQn = 27, /*!< 27 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 28, /*!< 28 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 29, /*!< 29 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 30, /*!< 30 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 31, /*!< 31 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 32, /*!< 32 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 33, /*!< 33 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 34, /*!< 34 EFR32 EMUDG Interrupt */ + EMUSE_IRQn = 35, /*!< 35 EFR32 EMUSE Interrupt */ + AGC_IRQn = 36, /*!< 36 EFR32 AGC Interrupt */ + BUFC_IRQn = 37, /*!< 37 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 38, /*!< 38 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 39, /*!< 39 EFR32 FRC Interrupt */ + MODEM_IRQn = 40, /*!< 40 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 41, /*!< 41 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 42, /*!< 42 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 43, /*!< 43 EFR32 RAC_SEQ Interrupt */ + RDMAILBOX_IRQn = 44, /*!< 44 EFR32 RDMAILBOX Interrupt */ + RFSENSE_IRQn = 45, /*!< 45 EFR32 RFSENSE Interrupt */ + SYNTH_IRQn = 46, /*!< 46 EFR32 SYNTH Interrupt */ + PRORTC_IRQn = 47, /*!< 47 EFR32 PRORTC Interrupt */ + ACMP0_IRQn = 48, /*!< 48 EFR32 ACMP0 Interrupt */ + WDOG0_IRQn = 49, /*!< 49 EFR32 WDOG0 Interrupt */ + HFXO0_IRQn = 50, /*!< 50 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 51, /*!< 51 EFR32 HFRCO0 Interrupt */ + CMU_IRQn = 52, /*!< 52 EFR32 CMU Interrupt */ + AES_IRQn = 53, /*!< 53 EFR32 AES Interrupt */ + IADC_IRQn = 54, /*!< 54 EFR32 IADC Interrupt */ + MSC_IRQn = 55, /*!< 55 EFR32 MSC Interrupt */ + DPLL0_IRQn = 56, /*!< 56 EFR32 DPLL0 Interrupt */ + PDM_IRQn = 57, /*!< 57 EFR32 PDM Interrupt */ + SW0_IRQn = 58, /*!< 58 EFR32 SW0 Interrupt */ + SW1_IRQn = 59, /*!< 59 EFR32 SW1 Interrupt */ + SW2_IRQn = 60, /*!< 60 EFR32 SW2 Interrupt */ + SW3_IRQn = 61, /*!< 61 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 62, /*!< 62 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 63, /*!< 63 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 64, /*!< 64 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 65, /*!< 65 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 66, /*!< 66 EFR32 FPUEXH Interrupt */ + MPAHBRAM_IRQn = 67, /*!< 67 EFR32 MPAHBRAM Interrupt */ + EUSART1_RX_IRQn = 68, /*!< 68 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 69, /*!< 69 EFR32 EUSART1_TX Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG29B230F1024CM40_Core EFR32MG29B230F1024CM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG29B230F1024CM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG29B230F1024CM40_Part EFR32MG29B230F1024CM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG29B230F1024CM40) +#define EFR32MG29B230F1024CM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG29B230F1024CM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_9 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 9 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_240 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 6 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00100000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x080FFFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00100000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x080FFFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG29B230F1024CM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 70 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 8U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x00FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define ETAMPDET_ETAMPIN0_PORT GPIO_PB_INDEX /**< Port of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN0_PIN 1U /**< Pin of ETAMPIN0.*/ +#define ETAMPDET_ETAMPIN1_PORT GPIO_PC_INDEX /**< Port of ETAMPIN1.*/ +#define ETAMPDET_ETAMPIN1_PIN 0U /**< Pin of ETAMPIN1.*/ +#define ETAMPDET_ETAMPOUT0_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT0_PIN 1U /**< Pin of ETAMPOUT0.*/ +#define ETAMPDET_ETAMPOUT1_PORT GPIO_PC_INDEX /**< Port of ETAMPOUT1.*/ +#define ETAMPDET_ETAMPOUT1_PIN 2U /**< Pin of ETAMPOUT1.*/ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 0U /**< Pin of THMSW_HALFSWITCH.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 1 /** 1 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define ETAMPDET_PRESENT /** ETAMPDET is available in this part */ +#define ETAMPDET_COUNT 1 /** 1 ETAMPDETs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PDM_PRESENT /** PDM is available in this part */ +#define PDM_COUNT 1 /** 1 PDMs available */ +#define PRORTC_PRESENT /** PRORTC is available in this part */ +#define PRORTC_COUNT 1 /** 1 PRORTCs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define RTCC_PRESENT /** RTCC is available in this part */ +#define RTCC_COUNT 1 /** 1 RTCCs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 2 /** 2 USARTs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 1 /** 1 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg29.h" /* System Header File */ + +/** @} End of group EFR32MG29B230F1024CM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG29B230F1024CM40_Peripheral_TypeDefs EFR32MG29B230F1024CM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg29_emu.h" +#include "efr32mg29_cmu.h" +#include "efr32mg29_hfxo.h" +#include "efr32mg29_hfrco.h" +#include "efr32mg29_fsrco.h" +#include "efr32mg29_dpll.h" +#include "efr32mg29_lfxo.h" +#include "efr32mg29_lfrco.h" +#include "efr32mg29_ulfrco.h" +#include "efr32mg29_msc.h" +#include "efr32mg29_icache.h" +#include "efr32mg29_prs.h" +#include "efr32mg29_gpio.h" +#include "efr32mg29_ldma.h" +#include "efr32mg29_ldmaxbar.h" +#include "efr32mg29_timer.h" +#include "efr32mg29_usart.h" +#include "efr32mg29_burtc.h" +#include "efr32mg29_i2c.h" +#include "efr32mg29_syscfg.h" +#include "efr32mg29_buram.h" +#include "efr32mg29_gpcrc.h" +#include "efr32mg29_dcdc.h" +#include "efr32mg29_pdm.h" +#include "efr32mg29_etampdet.h" +#include "efr32mg29_mpahbram.h" +#include "efr32mg29_eusart.h" +#include "efr32mg29_aes.h" +#include "efr32mg29_smu.h" +#include "efr32mg29_rtcc.h" +#include "efr32mg29_wdog.h" +#include "efr32mg29_letimer.h" +#include "efr32mg29_iadc.h" +#include "efr32mg29_acmp.h" +#include "efr32mg29_semailbox.h" +#include "efr32mg29_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg29_prs_signals.h" +#include "efr32mg29_dma_descriptor.h" +#include "efr32mg29_ldmaxbar_defines.h" + +/** @} End of group EFR32MG29B230F1024CM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG29B230F1024CM40_Peripheral_Base EFR32MG29B230F1024CM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ +#define ETAMPDET_S_BASE (0x400A4000UL) /* ETAMPDET_S base address */ +#define DMEM_S_BASE (0x400B0000UL) /* DMEM_S base address */ +#define EUSART1_S_BASE (0x400B4000UL) /* EUSART1_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ +#define WDOG0_S_BASE (0x48018000UL) /* WDOG0_S base address */ +#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x4A008000UL) /* ACMP0_S base address */ +#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ +#define EUSART0_S_BASE (0x4A040000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ +#define ETAMPDET_NS_BASE (0x500A4000UL) /* ETAMPDET_NS base address */ +#define DMEM_NS_BASE (0x500B0000UL) /* DMEM_NS base address */ +#define EUSART1_NS_BASE (0x500B4000UL) /* EUSART1_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ +#define WDOG0_NS_BASE (0x58018000UL) /* WDOG0_NS base address */ +#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x5A008000UL) /* ACMP0_NS base address */ +#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ +#define EUSART0_NS_BASE (0x5A040000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) +#define PDM_BASE (PDM_S_BASE) /* PDM base address */ +#else +#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S) && (SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S != 0))) +#define ETAMPDET_BASE (ETAMPDET_S_BASE) /* ETAMPDET base address */ +#else +#define ETAMPDET_BASE (ETAMPDET_NS_BASE) /* ETAMPDET base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ETAMPDET_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) +#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ +#else +#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) +#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ +#else +#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG29B230F1024CM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG29B230F1024CM40_Peripheral_Declaration EFR32MG29B230F1024CM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ +#define ETAMPDET_S ((ETAMPDET_TypeDef *) ETAMPDET_S_BASE) /**< ETAMPDET_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ +#define ETAMPDET_NS ((ETAMPDET_TypeDef *) ETAMPDET_NS_BASE) /**< ETAMPDET_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ +#define ETAMPDET ((ETAMPDET_TypeDef *) ETAMPDET_BASE) /**< ETAMPDET base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG29B230F1024CM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG29B230F1024CM40_Peripheral_Parameters EFR32MG29B230F1024CM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x90UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define HFRCO0_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x100000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x100000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x1UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x5UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x0UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x4UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_PARTNUMBER 0x4UL /**> Chip Part Number */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_RAM0_INST_COUNT 0x10UL /**> None */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define PDM_FIFO_LEN 0x4UL /**> New Param */ +#define PDM_NUM_CH 0x2UL /**> None */ +#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ +#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ +#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ +#define PDM_PIPELINE 0x0UL /**> None */ +#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ +#define ETAMPDET_NUM_CHNLS 0x2UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_EXCLUDE_DALI 0x0UL /**> Exclude DALI */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x32UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x12UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x12UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define RTCC_CC_NUM 0x3UL /**> None */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x0UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x0UL /**> None */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_EXCLUDE_DALI 0x1UL /**> Exclude DALI */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ +#define PRORTC_CC_NUM 0x2UL /**> None */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_EXCLUDE_DALI(n) (((n) == 0) ? EUSART0_EXCLUDE_DALI \ + : ((n) == 1) ? EUSART1_EXCLUDE_DALI \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for IADC */ +#define IADC(n) (((n) == 0) ? IADC0 \ + : 0x0UL) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 \ + : -1) +#define IADC_CONFIGNUM(n) (((n) == 0) ? IADC0_CONFIGNUM \ + : 0x0UL) +#define IADC_FULLRANGEUNIPOLAR(n) (((n) == 0) ? IADC0_FULLRANGEUNIPOLAR \ + : 0x0UL) +#define IADC_SCANBYTES(n) (((n) == 0) ? IADC0_SCANBYTES \ + : 0x0UL) +#define IADC_ENTRIES(n) (((n) == 0) ? IADC0_ENTRIES \ + : 0x0UL) + +/* Instance macros for LETIMER */ +#define LETIMER(n) (((n) == 0) ? LETIMER0 \ + : 0x0UL) +#define LETIMER_NUM(ref) (((ref) == LETIMER0) ? 0 \ + : -1) +#define LETIMER_CNT_WIDTH(n) (((n) == 0) ? LETIMER0_CNT_WIDTH \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG29B230F1024CM40_Peripheral_Parameters */ + +/** @} End of group EFR32MG29B230F1024CM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/em_device.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/em_device.h new file mode 100644 index 000000000..3f2cec628 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/em_device.h @@ -0,0 +1,61 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H +#if defined(EFR32MG29B140F1024IM40) +#include "efr32mg29b140f1024im40.h" + +#elif defined(EFR32MG29B230F1024CM40) +#include "efr32mg29b230f1024cm40.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif + +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif + +#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif +#endif /* EM_DEVICE_H */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/system_efr32mg29.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/system_efr32mg29.h new file mode 100644 index 000000000..9eb90cba5 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/system_efr32mg29.h @@ -0,0 +1,247 @@ +/**************************************************************************//** + * @file + * @brief CMSIS system header file for EFR32MG29 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32MG29_H +#define SYSTEM_EFR32MG29_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "sl_code_classification.h" + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFR32MG29 EFR32MG29 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ +#endif + +/*Re-direction of IRQn.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn +#else +#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn +#endif /* SL_TRUSTZONE_SECURE */ + +/*Re-direction of IRQHandler.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler +#else +#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler +#endif /* SL_TRUSTZONE_SECURE */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SecureFault_Handler(void); /**< Secure Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +/* Part Specific Interrupts */ +void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */ +void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */ +void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */ +void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ +void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ +void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ +void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ +void ETAMPDET_IRQHandler(void); /**< ETAMPDET IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ +void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ +void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ +void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ +void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ +void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ +void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ +void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ +void EMUSE_IRQHandler(void); /**< EMUSE IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void RDMAILBOX_IRQHandler(void); /**< RDMAILBOX IRQ Handler */ +void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void PRORTC_IRQHandler(void); /**< PRORTC IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ +void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void AES_IRQHandler(void); /**< AES IRQ Handler */ +void IADC_IRQHandler(void); /**< IADC IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ +void PDM_IRQHandler(void); /**< PDM IRQ Handler */ +void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ +void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ +void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ +void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ +void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ +void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ +void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ +void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ +void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ +void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */ +void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ +void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ +#endif + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHCLKGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE uint32_t SystemCoreClockGet(void) +{ + return SystemHCLKGet(); +} + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemHCLKGet(); +} + +void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFRCODPLLClockGet(void); +void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemULFRCOClockGet(void); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32MG29_H */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Source/system_efr32mg29.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Source/system_efr32mg29.c new file mode 100644 index 000000000..eac647830 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Source/system_efr32mg29.c @@ -0,0 +1,598 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M33 system support for EFR32MG29 devices. + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +// System oscillator frequencies. These frequencies are normally constant +// for a target, but they are made configurable in order to allow run-time +// handling of different boards. The crystal oscillator clocks can be set +// compile time to a non-default value by defining respective nFXO_FREQ +// values according to board design. By defining the nFXO_FREQ to 0, +// one indicates that the oscillator is not present, in order to save some +// SW footprint. + +#if !defined(FSRCO_FREQ) +// FSRCO frequency +#define FSRCO_FREQ (20000000UL) +#endif + +#if !defined(HFXO_FREQ) +// HFXO frequency +#define HFXO_FREQ (38400000UL) +#endif + +#if !defined(HFRCODPLL_STARTUP_FREQ) +// HFRCODPLL startup frequency +#define HFRCODPLL_STARTUP_FREQ (19000000UL) +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +// Maximum HFRCODPLL frequency +#define HFRCODPLL_MAX_FREQ (80000000UL) +#endif + +// CLKIN0 input +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) +#define CLKIN0_FREQ (0UL) +#endif + +#if !defined(LFRCO_MAX_FREQ) +// LFRCO frequency, tuned to below frequency during manufacturing. +#define LFRCO_FREQ (32768UL) +#endif + +#if !defined(ULFRCO_FREQ) +// ULFRCO frequency +#define ULFRCO_FREQ (1000UL) +#endif + +#if !defined(LFXO_FREQ) +// LFXO frequency +#define LFXO_FREQ (LFRCO_FREQ) +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// NOTE: Gecko bootloaders can't have static variable allocation. +// System HFXO clock frequency +static uint32_t SystemHFXOClock = HFXO_FREQ; +#endif + +#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// System LFXO clock frequency +static uint32_t SystemLFXOClock = LFXO_FREQ; +#endif + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +// System HFRCODPLL clock frequency +static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; + +#endif + +/*--------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *---------------------------------------------------------------------------*/ +extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ + | (3U << 11U * 2U)); /* set CP11 Full Access */ +#endif + +/* Secure app takes care of moving between the security states. + * SL_TRUSTZONE_SECURE MACRO is for secure access. + * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. + * When both the MACROS are not defined, during start-up below code makes sure + * that all the peripherals are accessed from non-secure address except SMU, + * as SMU is used to configure the trustzone state of the system. */ +#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ + && defined(__TZ_PRESENT) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; + + // config SMU to Secure and other peripherals to Non-Secure. + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; +#if defined (SEMAILBOX_PRESENT) + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); +#else + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); +#endif + + // SAU treats all accesses as non-secure +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + __DSB(); + __ISB(); +#else + #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." +#endif // __ARM_FEATURE_CMSE + +// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +#endif //SL_TRUSTZONE_SECURE +} + +/**************************************************************************//** + * @brief + * Get current HFRCODPLL frequency. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCODPLLClockGet(void) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + return SystemHFRCODPLLClock; +#else + uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +#endif +} + +/**************************************************************************//** + * @brief + * Set HFRCODPLL frequency value. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +void SystemHFRCODPLLClockSet(uint32_t freq) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFRCODPLLClock = freq; +#else + (void) freq; // Unused parameter +#endif +} + +/***************************************************************************//** + * @brief + * Get the current system clock frequency (SYSCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * hardware configuration. + * + * @note + * This is an EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * Current system clock (SYSCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemSYSCLKGet(void) +{ + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: +#if defined(SYSTEM_NO_STATIC_MEMORY) + ret = HFXO_FREQ; +#else + ret = SystemHFXOClock; +#endif + break; +#endif + +#if (CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = FSRCO_FREQ; + break; + + default: + // Unknown clock source. + while (1) { + } + } + return ret; +} + +/***************************************************************************//** + * @brief + * Get the current system core clock frequency (HCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * The current core clock (HCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemHCLKGet(void) +{ + uint32_t presc, ret; + + ret = SystemSYSCLKGet(); + + presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; + + ret /= presc + 1U; + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + // Keep CMSIS system clock variable up-to-date + SystemCoreClock = ret; +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ + ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + // The external crystal oscillator is not present if HFXO_FREQ==0 +#if (HFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return HFXO_FREQ; +#else + return SystemHFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFXOClock = freq; + + // Update core clock frequency if HFXO is used to clock core + if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) + == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { + // This function will update the global variable + SystemHCLKGet(); + } +#else + (void) freq; // Unused parameter +#endif +} + +/**************************************************************************//** + * @brief + * Get current CLKIN0 frequency. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * CLKIN0 frequency in Hz. + *****************************************************************************/ +uint32_t SystemCLKIN0Get(void) +{ + return CLKIN0_FREQ; +} + +/**************************************************************************//** + * @brief + * Get FSRCO frequency. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * FSRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemFSRCOClockGet(void) +{ + return FSRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + return LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + // The ULFRCO frequency is not tuned, and can be very inaccurate + return ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + // External crystal present? +#if (LFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return LFXO_FREQ; +#else + return SystemLFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32MG29 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemLFXOClock = freq; +#else + (void) freq; // Unused parameter +#endif +} diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h new file mode 100644 index 000000000..96c92057a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_acmp.h @@ -0,0 +1,654 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 ACMP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_ACMP_H +#define EFR32ZG23_ACMP_H +#define ACMP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_ACMP ACMP + * @{ + * @brief EFR32ZG23 ACMP Register Declaration. + *****************************************************************************/ + +/** ACMP Register Declaration. */ +typedef struct acmp_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +} ACMP_TypeDef; +/** @} End of group EFR32ZG23_ACMP */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_ACMP + * @{ + * @defgroup EFR32ZG23_ACMP_BitFields ACMP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ + +/* Bit fields for ACMP EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ + +/* Bit fields for ACMP SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ + +/* Bit fields for ACMP CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VDACOUT0 (_ACMP_INPUTCTRL_POSSEL_VDACOUT0 << 0) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VDACOUT1 (_ACMP_INPUTCTRL_POSSEL_VDACOUT1 << 0) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT0 0x00000040UL /**< Mode VDACOUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDACOUT1 0x00000041UL /**< Mode VDACOUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDACOUT0 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT0 << 8) /**< Shifted mode VDACOUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDACOUT1 (_ACMP_INPUTCTRL_NEGSEL_VDACOUT1 << 8) /**< Shifted mode VDACOUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ + +/** @} End of group EFR32ZG23_ACMP_BitFields */ +/** @} End of group EFR32ZG23_ACMP */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_ACMP_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h new file mode 100644 index 000000000..1aa8f207f --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_aes.h @@ -0,0 +1,453 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 AES register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_AES_H +#define EFR32ZG23_AES_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_AES AES + * @{ + * @brief EFR32ZG23 AES Register Declaration. + *****************************************************************************/ + +/** AES Register Declaration. */ +typedef struct aes_typedef{ + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +} AES_TypeDef; +/** @} End of group EFR32ZG23_AES */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_AES + * @{ + * @defgroup EFR32ZG23_AES_BitFields AES Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AES FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ + +/* Bit fields for AES FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ + +/* Bit fields for AES FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ + +/* Bit fields for AES PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ + +/* Bit fields for AES PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ + +/* Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ + +/* Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ + +/* Bit fields for AES BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ + +/* Bit fields for AES BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ + +/* Bit fields for AES BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ + +/* Bit fields for AES BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ + +/* Bit fields for AES BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ + +/** @} End of group EFR32ZG23_AES_BitFields */ +/** @} End of group EFR32ZG23_AES */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_AES_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h new file mode 100644 index 000000000..fe4fb54c7 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_buram.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 BURAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_BURAM_H +#define EFR32ZG23_BURAM_H +#define BURAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_BURAM BURAM + * @{ + * @brief EFR32ZG23 BURAM Register Declaration. + *****************************************************************************/ + +/** BURAM RET Register Group Declaration. */ +typedef struct buram_ret_typedef{ + __IOM uint32_t REG; /**< Retention Register */ +} BURAM_RET_TypeDef; + +/** BURAM Register Declaration. */ +typedef struct buram_typedef{ + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +} BURAM_TypeDef; +/** @} End of group EFR32ZG23_BURAM */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_BURAM + * @{ + * @defgroup EFR32ZG23_BURAM_BitFields BURAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURAM RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ + +/** @} End of group EFR32ZG23_BURAM_BitFields */ +/** @} End of group EFR32ZG23_BURAM */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_BURAM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h new file mode 100644 index 000000000..5390ff393 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_burtc.h @@ -0,0 +1,332 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 BURTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_BURTC_H +#define EFR32ZG23_BURTC_H +#define BURTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_BURTC BURTC + * @{ + * @brief EFR32ZG23 BURTC Register Declaration. + *****************************************************************************/ + +/** BURTC Register Declaration. */ +typedef struct burtc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +} BURTC_TypeDef; +/** @} End of group EFR32ZG23_BURTC */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_BURTC + * @{ + * @defgroup EFR32ZG23_BURTC_BitFields BURTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURTC IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ + +/* Bit fields for BURTC EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ + +/* Bit fields for BURTC CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ + +/* Bit fields for BURTC CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ + +/* Bit fields for BURTC IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ + +/* Bit fields for BURTC CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ + +/* Bit fields for BURTC SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ + +/** @} End of group EFR32ZG23_BURTC_BitFields */ +/** @} End of group EFR32ZG23_BURTC */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_BURTC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h new file mode 100644 index 000000000..13ee3a9d4 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_cmu.h @@ -0,0 +1,1128 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 CMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_CMU_H +#define EFR32ZG23_CMU_H +#define CMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_CMU CMU + * @{ + * @brief EFR32ZG23 CMU Register Declaration. + *****************************************************************************/ + +/** CMU Register Declaration. */ +typedef struct cmu_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED11[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED14[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED16[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL; /**< LCD Clock Control */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL; /**< LESENSE HF Clock Control */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[858U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED28[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED32[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED33[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED36[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED37[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED39[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ + uint32_t RESERVED41[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED42[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_SET; /**< LCD Clock Control */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ + uint32_t RESERVED45[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_SET; /**< LESENSE HF Clock Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + uint32_t RESERVED49[858U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED52[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED53[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED54[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED55[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED56[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED57[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED58[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED59[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED60[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED61[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED62[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED63[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED64[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED65[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ + uint32_t RESERVED66[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED67[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ + uint32_t RESERVED68[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_CLR; /**< LCD Clock Control */ + uint32_t RESERVED69[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ + uint32_t RESERVED70[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED71[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + uint32_t RESERVED72[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_CLR; /**< LESENSE HF Clock Control */ + uint32_t RESERVED73[1U]; /**< Reserved for future use */ + uint32_t RESERVED74[858U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED75[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED76[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED77[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED78[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED79[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED80[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED81[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED82[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED83[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED84[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED85[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED86[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED87[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED88[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED89[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED90[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED91[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED92[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ + uint32_t RESERVED93[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCLKCTRL_TGL; /**< LCD Clock Control */ + uint32_t RESERVED94[3U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ + uint32_t RESERVED95[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED96[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + uint32_t RESERVED97[3U]; /**< Reserved for future use */ + __IOM uint32_t LESENSEHFCLKCTRL_TGL; /**< LESENSE HF Clock Control */ + uint32_t RESERVED98[1U]; /**< Reserved for future use */ +} CMU_TypeDef; +/** @} End of group EFR32ZG23_CMU */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_CMU + * @{ + * @defgroup EFR32ZG23_CMU_BitFields CMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LESENSE (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LESENSE_SHIFT 25 /**< Shift value for CMU_LESENSE */ +#define _CMU_CLKEN0_LESENSE_MASK 0x2000000UL /**< Bit mask for CMU_LESENSE */ +#define _CMU_CLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LESENSE_DEFAULT (_CMU_CLKEN0_LESENSE_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ + +/* Bit fields for CMU CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x1FFFFFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_LCD_SHIFT 12 /**< Shift value for CMU_LCD */ +#define _CMU_CLKEN1_LCD_MASK 0x1000UL /**< Bit mask for CMU_LCD */ +#define _CMU_CLKEN1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_LCD_DEFAULT (_CMU_CLKEN1_LCD_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART2 (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART2_SHIFT 24 /**< Shift value for CMU_EUSART2 */ +#define _CMU_CLKEN1_EUSART2_MASK 0x1000000UL /**< Bit mask for CMU_EUSART2 */ +#define _CMU_CLKEN1_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART2_DEFAULT (_CMU_CLKEN1_EUSART2_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ + +/* Bit fields for CMU SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ + +/* Bit fields for CMU TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000030UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ + +/* Bit fields for CMU EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ + +/* Bit fields for CMU DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ + +/* Bit fields for CMU EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ + +/* Bit fields for CMU EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ + +/* Bit fields for CMU EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ + +/* Bit fields for CMU EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ + +/* Bit fields for CMU IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ + +/* Bit fields for CMU WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ + +/* Bit fields for CMU WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ + +/* Bit fields for CMU EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ + +/* Bit fields for CMU SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ + +/* Bit fields for CMU LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_LCDCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_LCDCLKCTRL */ +#define _CMU_LCDCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_DEFAULT (_CMU_LCDCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFRCO (_CMU_LCDCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_LFXO (_CMU_LCDCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_LCDCLKCTRL */ +#define CMU_LCDCLKCTRL_CLKSEL_ULFRCO (_CMU_LCDCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_LCDCLKCTRL */ + +/* Bit fields for CMU VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ + +/* Bit fields for CMU PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ +#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ + +/* Bit fields for CMU RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ + +/* Bit fields for CMU LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_LESENSEHFCLKCTRL */ +#define _CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL */ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT (_CMU_LESENSEHFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LESENSEHFCLKCTRL*/ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO (_CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_LESENSEHFCLKCTRL */ +#define CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_LESENSEHFCLKCTRL*/ + +/** @} End of group EFR32ZG23_CMU_BitFields */ +/** @} End of group EFR32ZG23_CMU */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_CMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h new file mode 100644 index 000000000..493acefe9 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dcdc.h @@ -0,0 +1,461 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 DCDC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_DCDC_H +#define EFR32ZG23_DCDC_H +#define DCDC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_DCDC DCDC + * @{ + * @brief EFR32ZG23 DCDC Register Declaration. + *****************************************************************************/ + +/** DCDC Register Declaration. */ +typedef struct dcdc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t EM01CTRL0; /**< EM01 Control */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0; /**< EM23 Control */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL; /**< PFMX Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + uint32_t RESERVED6[7U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ + uint32_t RESERVED15[2U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[7U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ + uint32_t RESERVED23[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[7U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[7U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + uint32_t RESERVED32[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ + uint32_t RESERVED34[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ + uint32_t RESERVED37[2U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[7U]; /**< Reserved for future use */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[7U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ +} DCDC_TypeDef; +/** @} End of group EFR32ZG23_DCDC */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_DCDC + * @{ + * @defgroup EFR32ZG23_DCDC_BitFields DCDC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DCDC IPVERSION */ +#define _DCDC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_IPVERSION */ +#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ + +/* Bit fields for DCDC CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ + +/* Bit fields for DCDC EM01CTRL0 */ +#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ + +/* Bit fields for DCDC EM23CTRL0 */ +#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ + +/* Bit fields for DCDC PFMXCTRL */ +#define _DCDC_PFMXCTRL_RESETVALUE 0x00000C0CUL /**< Default value for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD50MA 0x00000003UL /**< Mode LOAD50MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD65MA 0x00000004UL /**< Mode LOAD65MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD73MA 0x00000005UL /**< Mode LOAD73MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD80MA 0x00000006UL /**< Mode LOAD80MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD86MA 0x00000007UL /**< Mode LOAD86MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD93MA 0x00000008UL /**< Mode LOAD93MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD100MA 0x00000009UL /**< Mode LOAD100MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD106MA 0x0000000AUL /**< Mode LOAD106MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD113MA 0x0000000BUL /**< Mode LOAD113MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD120MA 0x0000000CUL /**< Mode LOAD120MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD50MA (_DCDC_PFMXCTRL_IPKVAL_LOAD50MA << 0) /**< Shifted mode LOAD50MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD65MA (_DCDC_PFMXCTRL_IPKVAL_LOAD65MA << 0) /**< Shifted mode LOAD65MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD73MA (_DCDC_PFMXCTRL_IPKVAL_LOAD73MA << 0) /**< Shifted mode LOAD73MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD80MA (_DCDC_PFMXCTRL_IPKVAL_LOAD80MA << 0) /**< Shifted mode LOAD80MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD86MA (_DCDC_PFMXCTRL_IPKVAL_LOAD86MA << 0) /**< Shifted mode LOAD86MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD93MA (_DCDC_PFMXCTRL_IPKVAL_LOAD93MA << 0) /**< Shifted mode LOAD93MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD100MA (_DCDC_PFMXCTRL_IPKVAL_LOAD100MA << 0) /**< Shifted mode LOAD100MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD106MA (_DCDC_PFMXCTRL_IPKVAL_LOAD106MA << 0) /**< Shifted mode LOAD106MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD113MA (_DCDC_PFMXCTRL_IPKVAL_LOAD113MA << 0) /**< Shifted mode LOAD113MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD120MA (_DCDC_PFMXCTRL_IPKVAL_LOAD120MA << 0) /**< Shifted mode LOAD120MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ + +/* Bit fields for DCDC IF */ +#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ +#define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */ +#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ +#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ +#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ +#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */ +#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */ +#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ +#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ +#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ +#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PPMODE (0x1UL << 8) /**< Entered Pulse Pairing mode */ +#define _DCDC_IF_PPMODE_SHIFT 8 /**< Shift value for DCDC_PPMODE */ +#define _DCDC_IF_PPMODE_MASK 0x100UL /**< Bit mask for DCDC_PPMODE */ +#define _DCDC_IF_PPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PPMODE_DEFAULT (_DCDC_IF_PPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */ +#define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */ + +/* Bit fields for DCDC IEN */ +#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ +#define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */ +#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ +#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ +#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ +#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ +#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ +#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ +#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PPMODE (0x1UL << 8) /**< Pulse Pairing Mode Interrupt Enable */ +#define _DCDC_IEN_PPMODE_SHIFT 8 /**< Shift value for DCDC_PPMODE */ +#define _DCDC_IEN_PPMODE_MASK 0x100UL /**< Bit mask for DCDC_PPMODE */ +#define _DCDC_IEN_PPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PPMODE_DEFAULT (_DCDC_IEN_PPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */ +#define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */ + +/* Bit fields for DCDC STATUS */ +#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ +#define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ +#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ +#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ +#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ +#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ +#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PPMODE (0x1UL << 8) /**< DCDC in pulse-pairing mode */ +#define _DCDC_STATUS_PPMODE_SHIFT 8 /**< Shift value for DCDC_PPMODE */ +#define _DCDC_STATUS_PPMODE_MASK 0x100UL /**< Bit mask for DCDC_PPMODE */ +#define _DCDC_STATUS_PPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PPMODE_DEFAULT (_DCDC_STATUS_PPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */ +#define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */ + +/* Bit fields for DCDC SYNCBUSY */ +#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */ +#define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ + +/* Bit fields for DCDC LOCK */ +#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ +#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ + +/* Bit fields for DCDC LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ +#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ + +/** @} End of group EFR32ZG23_DCDC_BitFields */ +/** @} End of group EFR32ZG23_DCDC */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_DCDC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h new file mode 100644 index 000000000..7db9611d8 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_devinfo.h @@ -0,0 +1,1008 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 DEVINFO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_DEVINFO_H +#define EFR32ZG23_DEVINFO_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_DEVINFO DEVINFO + * @{ + * @brief EFR32ZG23 DEVINFO Register Declaration. + *****************************************************************************/ + +/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ +typedef struct devinfo_hfrcodpllcal_typedef{ + __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ +} DEVINFO_HFRCODPLLCAL_TypeDef; + +/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ +typedef struct devinfo_hfrcoem23cal_typedef{ + __IM uint32_t HFRCOEM23CAL; /**< HFRCOEM23 Calibration */ +} DEVINFO_HFRCOEM23CAL_TypeDef; + +/** DEVINFO HFRCOSECAL Register Group Declaration. */ +typedef struct devinfo_hfrcosecal_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOSECAL_TypeDef; + +/** DEVINFO Register Declaration. */ +typedef struct devinfo_typedef{ + __IM uint32_t INFO; /**< DI Information */ + __IM uint32_t PART; /**< Part Info */ + __IM uint32_t MEMINFO; /**< Memory Info */ + __IM uint32_t MSIZE; /**< Memory Size */ + __IM uint32_t PKGINFO; /**< Misc Device Info */ + __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ + __IM uint32_t SWFIX; /**< SW Fix Register */ + __IM uint32_t SWCAPA0; /**< Software Restriction */ + __IM uint32_t SWCAPA1; /**< Software Restriction */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t EXTINFO; /**< External Component Info */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t EUI48L; /**< EUI 48 Low */ + __IM uint32_t EUI48H; /**< EUI 48 High */ + __IM uint32_t EUI64L; /**< EUI64 Low */ + __IM uint32_t EUI64H; /**< EUI64 High */ + __IM uint32_t CALTEMP; /**< Calibration temperature */ + __IM uint32_t EMUTEMP; /**< EMU Temp */ + DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ + DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ + DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ + __IM uint32_t MODULENAME0; /**< Module Name Information */ + __IM uint32_t MODULENAME1; /**< Module Name Information */ + __IM uint32_t MODULENAME2; /**< Module Name Information */ + __IM uint32_t MODULENAME3; /**< Module Name Information */ + __IM uint32_t MODULENAME4; /**< Module Name Information */ + __IM uint32_t MODULENAME5; /**< Module Name Information */ + __IM uint32_t MODULENAME6; /**< Module Name Information */ + __IM uint32_t MODULEINFO; /**< Module Information */ + __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IM uint32_t HFXOCAL; /**< High Frequency Crystal Oscillator Calibration data */ + __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ + __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ + __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ + uint32_t RESERVED4[24U]; /**< Reserved for future use */ + __IM uint32_t LEGACY; /**< Legacy Device Info */ + uint32_t RESERVED5[23U]; /**< Reserved for future use */ + __IM uint32_t RTHERM; /**< */ + uint32_t RESERVED6[80U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ +} DEVINFO_TypeDef; +/** @} End of group EFR32ZG23_DEVINFO */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_DEVINFO + * @{ + * @defgroup EFR32ZG23_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x0C000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ +#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ +#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_FG 0x00000000UL /**< Mode FG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_ZG 0x00000003UL /**< Mode ZG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_PG 0x00000005UL /**< Mode PG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SG 0x00000008UL /**< Mode SG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_FG (_DEVINFO_PART_FAMILY_FG << 24) /**< Shifted mode FG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_ZG (_DEVINFO_PART_FAMILY_ZG << 24) /**< Shifted mode ZG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_PG (_DEVINFO_PART_FAMILY_PG << 24) /**< Shifted mode PG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_SG (_DEVINFO_PART_FAMILY_SG << 24) /**< Shifted mode SG for DEVINFO_PART */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ + +/* Bit fields for DEVINFO PKGINFO */ +#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ +#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ + +/* Bit fields for DEVINFO SWFIX */ +#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ +#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ + +/* Bit fields for DEVINFO SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_MASK 0x07333333UL /**< Mask for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_SHIFT 24 /**< Shift value for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_MASK 0x7000000UL /**< Bit mask for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL4 0x00000004UL /**< Mode LEVEL4 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_DEFAULT (_DEVINFO_SWCAPA0_ZWAVE_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL0 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL0 << 24) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL1 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL1 << 24) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL2 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL2 << 24) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL3 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL3 << 24) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL4 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL4 << 24) /**< Shifted mode LEVEL4 for DEVINFO_SWCAPA0 */ + +/* Bit fields for DEVINFO SWCAPA1 */ +#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ +#define _DEVINFO_SWCAPA1_MASK 0x0000001FUL /**< Mask for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ +#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ +#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ +#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT (0x1UL << 3) /**< XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_SHIFT 3 /**< Shift value for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_MASK 0x8UL /**< Bit mask for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT_DEFAULT (_DEVINFO_SWCAPA1_XOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ + +/* Bit fields for DEVINFO EUI64L */ +#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ +#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ + +/* Bit fields for DEVINFO EUI64H */ +#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ + +/* Bit fields for DEVINFO CALTEMP */ +#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ +#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ +#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ + +/* Bit fields for DEVINFO HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ + +/* Bit fields for DEVINFO HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define DEVINFO_HFRCOEM23CAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT (_DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT (_DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT (_DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ + +/* Bit fields for DEVINFO MODULENAME0 */ +#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ + +/* Bit fields for DEVINFO MODULENAME1 */ +#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ + +/* Bit fields for DEVINFO MODULENAME2 */ +#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ + +/* Bit fields for DEVINFO MODULENAME3 */ +#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ + +/* Bit fields for DEVINFO MODULENAME4 */ +#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ + +/* Bit fields for DEVINFO MODULENAME5 */ +#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ + +/* Bit fields for DEVINFO MODULENAME6 */ +#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ +#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ +#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ + +/* Bit fields for DEVINFO HFXOCAL */ +#define _DEVINFO_HFXOCAL_RESETVALUE 0xFFFFFF00UL /**< Default value for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_SHIFT 0 /**< Shift value for DEVINFO_SHUNTBIASANA */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_MASK 0xFUL /**< Bit mask for DEVINFO_SHUNTBIASANA */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I20UA 0x00000000UL /**< Mode I20UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I30UA 0x00000001UL /**< Mode I30UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I40UA 0x00000002UL /**< Mode I40UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I50UA 0x00000003UL /**< Mode I50UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I60UA 0x00000004UL /**< Mode I60UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I70UA 0x00000005UL /**< Mode I70UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I80UA 0x00000006UL /**< Mode I80UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I90UA 0x00000007UL /**< Mode I90UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I100UA 0x00000008UL /**< Mode I100UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I110UA 0x00000009UL /**< Mode I110UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I120UA 0x0000000AUL /**< Mode I120UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I130UA 0x0000000BUL /**< Mode I130UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I140UA 0x0000000CUL /**< Mode I140UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I150UA 0x0000000DUL /**< Mode I150UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I160UA 0x0000000EUL /**< Mode I160UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_SHUNTBIASANA_I170UA 0x0000000FUL /**< Mode I170UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_DEFAULT (_DEVINFO_HFXOCAL_SHUNTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I20UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I20UA << 0) /**< Shifted mode I20UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I30UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I30UA << 0) /**< Shifted mode I30UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I40UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I40UA << 0) /**< Shifted mode I40UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I50UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I50UA << 0) /**< Shifted mode I50UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I60UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I60UA << 0) /**< Shifted mode I60UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I70UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I70UA << 0) /**< Shifted mode I70UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I80UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I80UA << 0) /**< Shifted mode I80UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I90UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I90UA << 0) /**< Shifted mode I90UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I100UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I100UA << 0) /**< Shifted mode I100UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I110UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I110UA << 0) /**< Shifted mode I110UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I120UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I120UA << 0) /**< Shifted mode I120UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I130UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I130UA << 0) /**< Shifted mode I130UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I140UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I140UA << 0) /**< Shifted mode I140UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I150UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I150UA << 0) /**< Shifted mode I150UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I160UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I160UA << 0) /**< Shifted mode I160UA for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_SHUNTBIASANA_I170UA (_DEVINFO_HFXOCAL_SHUNTBIASANA_I170UA << 0) /**< Shifted mode I170UA for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_VTRTRIMANA_SHIFT 4 /**< Shift value for DEVINFO_VTRTRIMANA */ +#define _DEVINFO_HFXOCAL_VTRTRIMANA_MASK 0xF0UL /**< Bit mask for DEVINFO_VTRTRIMANA */ +#define _DEVINFO_HFXOCAL_VTRTRIMANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_VTRTRIMANA_DEFAULT (_DEVINFO_HFXOCAL_VTRTRIMANA_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_HFXOCAL */ +#define _DEVINFO_HFXOCAL_RESERVED_SHIFT 8 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_HFXOCAL_RESERVED_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_HFXOCAL_RESERVED_DEFAULT 0x00FFFFFFUL /**< Mode DEFAULT for DEVINFO_HFXOCAL */ +#define DEVINFO_HFXOCAL_RESERVED_DEFAULT (_DEVINFO_HFXOCAL_RESERVED_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFXOCAL */ + +/* Bit fields for DEVINFO IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ + +/* Bit fields for DEVINFO IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ + +/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ + +/* Bit fields for DEVINFO LEGACY */ +#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ + +/* Bit fields for DEVINFO RTHERM */ +#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ +#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ + +/** @} End of group EFR32ZG23_DEVINFO_BitFields */ +/** @} End of group EFR32ZG23_DEVINFO */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_DEVINFO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h new file mode 100644 index 000000000..2299a1b49 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dma_descriptor.h @@ -0,0 +1,59 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 DMA descriptor bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_DMA_DESCRIPTOR_H +#define EFR32ZG23_DMA_DESCRIPTOR_H + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup DMA_DESCRIPTOR DMA Descriptor + * @{ + *****************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + +#endif // EFR32ZG23_DMA_DESCRIPTOR_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h new file mode 100644 index 000000000..234a43d0f --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_dpll.h @@ -0,0 +1,232 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 DPLL register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_DPLL_H +#define EFR32ZG23_DPLL_H +#define DPLL_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_DPLL DPLL + * @{ + * @brief EFR32ZG23 DPLL Register Declaration. + *****************************************************************************/ + +/** DPLL Register Declaration. */ +typedef struct dpll_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ +} DPLL_TypeDef; +/** @} End of group EFR32ZG23_DPLL */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_DPLL + * @{ + * @defgroup EFR32ZG23_DPLL_BitFields DPLL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DPLL IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ + +/* Bit fields for DPLL EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ + +/* Bit fields for DPLL CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ + +/* Bit fields for DPLL CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ + +/* Bit fields for DPLL IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ + +/* Bit fields for DPLL IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ + +/* Bit fields for DPLL STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ + +/* Bit fields for DPLL LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ + +/** @} End of group EFR32ZG23_DPLL_BitFields */ +/** @} End of group EFR32ZG23_DPLL */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_DPLL_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h new file mode 100644 index 000000000..5ada862da --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_emu.h @@ -0,0 +1,779 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 EMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_EMU_H +#define EFR32ZG23_EMU_H +#define EMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_EMU EMU + * @{ + * @brief EFR32ZG23 EMU Register Declaration. + *****************************************************************************/ + +/** EMU Register Declaration. */ +typedef struct emu_typedef{ + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[6U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[14U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[18U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[924U]; /**< Reserved for future use */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED17[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED22[6U]; /**< Reserved for future use */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED25[14U]; /**< Reserved for future use */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[18U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[924U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED32[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED33[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED37[6U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED40[14U]; /**< Reserved for future use */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + uint32_t RESERVED42[18U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[924U]; /**< Reserved for future use */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED47[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED48[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED49[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED52[6U]; /**< Reserved for future use */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED55[14U]; /**< Reserved for future use */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[18U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ +} EMU_TypeDef; +/** @} End of group EFR32ZG23_EMU */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_EMU + * @{ + * @defgroup EFR32ZG23_EMU_BitFields EMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ + +/* Bit fields for EMU BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ + +/* Bit fields for EMU VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ + +/* Bit fields for EMU PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ + +/* Bit fields for EMU IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ +#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFFFD4FFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ + +/* Bit fields for EMU RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ +#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ +#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ + +/* Bit fields for EMU TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ + +/* Bit fields for EMU DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ + +/* Bit fields for EMU DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ + +/* Bit fields for EMU EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ + +/* Bit fields for EMU EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ + +/** @} End of group EFR32ZG23_EMU_BitFields */ +/** @} End of group EFR32ZG23_EMU */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_EMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h new file mode 100644 index 000000000..956f9256a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_eusart.h @@ -0,0 +1,1193 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 EUSART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_EUSART_H +#define EFR32ZG23_EUSART_H +#define EUSART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_EUSART EUSART + * @{ + * @brief EFR32ZG23 EUSART Register Declaration. + *****************************************************************************/ + +/** EUSART Register Declaration. */ +typedef struct eusart_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[42U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[42U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED6[42U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED9[42U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} EUSART_TypeDef; +/** @} End of group EFR32ZG23_EUSART */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_EUSART + * @{ + * @defgroup EFR32ZG23_EUSART_BitFields EUSART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EUSART IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ + +/* Bit fields for EUSART EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ + +/* Bit fields for EUSART CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ + +/* Bit fields for EUSART CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ + +/* Bit fields for EUSART CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ + +/* Bit fields for EUSART FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ + +/* Bit fields for EUSART DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ + +/* Bit fields for EUSART IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ + +/* Bit fields for EUSART IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ + +/* Bit fields for EUSART TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ + +/* Bit fields for EUSART STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ + +/* Bit fields for EUSART SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ + +/* Bit fields for EUSART CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ + +/* Bit fields for EUSART TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ + +/* Bit fields for EUSART CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ + +/* Bit fields for EUSART RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ + +/* Bit fields for EUSART RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ + +/* Bit fields for EUSART TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ + +/* Bit fields for EUSART STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ + +/* Bit fields for EUSART IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ + +/* Bit fields for EUSART IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ + +/* Bit fields for EUSART SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ + +/** @} End of group EFR32ZG23_EUSART_BitFields */ +/** @} End of group EFR32ZG23_EUSART */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_EUSART_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h new file mode 100644 index 000000000..149865580 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_fsrco.h @@ -0,0 +1,75 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 FSRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_FSRCO_H +#define EFR32ZG23_FSRCO_H +#define FSRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_FSRCO FSRCO + * @{ + * @brief EFR32ZG23 FSRCO Register Declaration. + *****************************************************************************/ + +/** FSRCO Register Declaration. */ +typedef struct fsrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ +} FSRCO_TypeDef; +/** @} End of group EFR32ZG23_FSRCO */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_FSRCO + * @{ + * @defgroup EFR32ZG23_FSRCO_BitFields FSRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FSRCO IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ + +/** @} End of group EFR32ZG23_FSRCO_BitFields */ +/** @} End of group EFR32ZG23_FSRCO */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_FSRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h new file mode 100644 index 000000000..d9fed2abf --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpcrc.h @@ -0,0 +1,246 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 GPCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_GPCRC_H +#define EFR32ZG23_GPCRC_H +#define GPCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_GPCRC GPCRC + * @{ + * @brief EFR32ZG23 GPCRC Register Declaration. + *****************************************************************************/ + +/** GPCRC Register Declaration. */ +typedef struct gpcrc_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; +/** @} End of group EFR32ZG23_GPCRC */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_GPCRC + * @{ + * @defgroup EFR32ZG23_GPCRC_BitFields GPCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ + +/* Bit fields for GPCRC EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32ZG23_GPCRC_BitFields */ +/** @} End of group EFR32ZG23_GPCRC */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_GPCRC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h new file mode 100644 index 000000000..aac7b214e --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio.h @@ -0,0 +1,2824 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 GPIO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_GPIO_H +#define EFR32ZG23_GPIO_H +#define GPIO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +#include "efr32zg23_gpio_port.h" + +typedef struct gpio_acmproute_typedef{ + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_ACMPROUTE_TypeDef; + +typedef struct gpio_cmuroute_typedef{ + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ +} GPIO_CMUROUTE_TypeDef; + +typedef struct gpio_eusartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_EUSARTROUTE_TypeDef; + +typedef struct gpio_frcroute_typedef{ + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_FRCROUTE_TypeDef; + +typedef struct gpio_i2croute_typedef{ + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_I2CROUTE_TypeDef; + +typedef struct gpio_keyscanroute_typedef{ + __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ + __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ + __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ + __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ + __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ + __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ + __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ + __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ + __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ + __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ + __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ + __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ + __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ + __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ + __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_KEYSCANROUTE_TypeDef; + +typedef struct gpio_lesenseroute_typedef{ + __IOM uint32_t ROUTEEN; /**< LESENSE pin enable */ + __IOM uint32_t CH0OUTROUTE; /**< CH0OUT port/pin select */ + __IOM uint32_t CH1OUTROUTE; /**< CH1OUT port/pin select */ + __IOM uint32_t CH2OUTROUTE; /**< CH2OUT port/pin select */ + __IOM uint32_t CH3OUTROUTE; /**< CH3OUT port/pin select */ + __IOM uint32_t CH4OUTROUTE; /**< CH4OUT port/pin select */ + __IOM uint32_t CH5OUTROUTE; /**< CH5OUT port/pin select */ + __IOM uint32_t CH6OUTROUTE; /**< CH6OUT port/pin select */ + __IOM uint32_t CH7OUTROUTE; /**< CH7OUT port/pin select */ + __IOM uint32_t CH8OUTROUTE; /**< CH8OUT port/pin select */ + __IOM uint32_t CH9OUTROUTE; /**< CH9OUT port/pin select */ + __IOM uint32_t CH10OUTROUTE; /**< CH10OUT port/pin select */ + __IOM uint32_t CH11OUTROUTE; /**< CH11OUT port/pin select */ + __IOM uint32_t CH12OUTROUTE; /**< CH12OUT port/pin select */ + __IOM uint32_t CH13OUTROUTE; /**< CH13OUT port/pin select */ + __IOM uint32_t CH14OUTROUTE; /**< CH14OUT port/pin select */ + __IOM uint32_t CH15OUTROUTE; /**< CH15OUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LESENSEROUTE_TypeDef; + +typedef struct gpio_letimerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LETIMERROUTE_TypeDef; + +typedef struct gpio_modemroute_typedef{ + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_MODEMROUTE_TypeDef; + +typedef struct gpio_pcntroute_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ + __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_PCNTROUTE_TypeDef; + +typedef struct gpio_prsroute_typedef{ + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PRSROUTE_TypeDef; + +typedef struct gpio_syxoroute_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_SYXOROUTE_TypeDef; + +typedef struct gpio_timerroute_typedef{ + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_TIMERROUTE_TypeDef; + +typedef struct gpio_usartroute_typedef{ + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_USARTROUTE_TypeDef; + +typedef struct gpio_typedef{ + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED4[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG; /**< LCD Segment Enable */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM; /**< LCD Common Enable */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED12[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED13[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED14[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED15[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED16[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED17[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED19[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED23[2U]; /**< Reserved for future use */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_SET; /**< LCD Segment Enable */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_SET; /**< LCD Common Enable */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED27[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_SET; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED28[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED29[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED30[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED31[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED32[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED34[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED35[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED38[2U]; /**< Reserved for future use */ + uint32_t RESERVED39[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_CLR; /**< LCD Segment Enable */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_CLR; /**< LCD Common Enable */ + uint32_t RESERVED41[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_CLR; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED43[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED44[530U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED45[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED46[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED48[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED49[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED50[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED52[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED53[2U]; /**< Reserved for future use */ + uint32_t RESERVED54[4U]; /**< Reserved for future use */ + __IOM uint32_t LCDSEG_TGL; /**< LCD Segment Enable */ + uint32_t RESERVED55[3U]; /**< Reserved for future use */ + __IOM uint32_t LCDCOM_TGL; /**< LCD Common Enable */ + uint32_t RESERVED56[3U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED57[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[3U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keyscan DBUS config registers */ + GPIO_LESENSEROUTE_TypeDef LESENSEROUTE_TGL; /**< lesense DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + uint32_t RESERVED58[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ +} GPIO_TypeDef; + +/* Bit fields for GPIO IPVERSION */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/* Bit fields for GPIO GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ + +/* Bit fields for GPIO ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ + +/* Bit fields for GPIO BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ + +/* Bit fields for GPIO CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ + +/* Bit fields for GPIO DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ + +/* Bit fields for GPIO TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ + +/* Bit fields for GPIO LCDSEG */ +#define _GPIO_LCDSEG_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_MASK 0x000FFFFFUL /**< Mask for GPIO_LCDSEG */ +#define _GPIO_LCDSEG_LCDSEGALLOC_SHIFT 0 /**< Shift value for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEG_LCDSEGALLOC_MASK 0xFFFFFUL /**< Bit mask for GPIO_LCDSEGALLOC */ +#define _GPIO_LCDSEG_LCDSEGALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDSEG */ +#define GPIO_LCDSEG_LCDSEGALLOC_DEFAULT (_GPIO_LCDSEG_LCDSEGALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDSEG */ + +/* Bit fields for GPIO LCDCOM */ +#define _GPIO_LCDCOM_RESETVALUE 0x00000000UL /**< Default value for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_MASK 0x0000000FUL /**< Mask for GPIO_LCDCOM */ +#define _GPIO_LCDCOM_LCDCOMALLOC_SHIFT 0 /**< Shift value for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_MASK 0xFUL /**< Bit mask for GPIO_LCDCOMALLOC */ +#define _GPIO_LCDCOM_LCDCOMALLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LCDCOM */ +#define GPIO_LCDCOM_LCDCOMALLOC_DEFAULT (_GPIO_LCDCOM_LCDCOMALLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LCDCOM */ + +/* Bit fields for GPIO_ACMP ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ + +/* Bit fields for GPIO_ACMP ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ + +/* Bit fields for GPIO_CMU ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ + +/* Bit fields for GPIO_CMU CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ + +/* Bit fields for GPIO_EUSART ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ + +/* Bit fields for GPIO_EUSART CSROUTE */ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ + +/* Bit fields for GPIO_EUSART CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ + +/* Bit fields for GPIO_EUSART RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ + +/* Bit fields for GPIO_EUSART RXROUTE */ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ + +/* Bit fields for GPIO_EUSART SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ + +/* Bit fields for GPIO_EUSART TXROUTE */ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ + +/* Bit fields for GPIO_FRC ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ + +/* Bit fields for GPIO_FRC DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ + +/* Bit fields for GPIO_FRC DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ + +/* Bit fields for GPIO_FRC DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ + +/* Bit fields for GPIO_I2C ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ + +/* Bit fields for GPIO_I2C SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ + +/* Bit fields for GPIO_I2C SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ + +/* Bit fields for GPIO_KEYSCAN ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ + +/* Bit fields for GPIO_LESENSE ROUTEEN */ +#define _GPIO_LESENSE_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_ROUTEEN */ +#define _GPIO_LESENSE_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN (0x1UL << 0) /**< CH0OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_SHIFT 0 /**< Shift value for GPIO_CH0OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_MASK 0x1UL /**< Bit mask for GPIO_CH0OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH0OUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN (0x1UL << 1) /**< CH1OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_SHIFT 1 /**< Shift value for GPIO_CH1OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_MASK 0x2UL /**< Bit mask for GPIO_CH1OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH1OUTPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN (0x1UL << 2) /**< CH2OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_SHIFT 2 /**< Shift value for GPIO_CH2OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_MASK 0x4UL /**< Bit mask for GPIO_CH2OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH2OUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN (0x1UL << 3) /**< CH3OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_SHIFT 3 /**< Shift value for GPIO_CH3OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_MASK 0x8UL /**< Bit mask for GPIO_CH3OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH3OUTPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN (0x1UL << 4) /**< CH4OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_SHIFT 4 /**< Shift value for GPIO_CH4OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_MASK 0x10UL /**< Bit mask for GPIO_CH4OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH4OUTPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN (0x1UL << 5) /**< CH5OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_SHIFT 5 /**< Shift value for GPIO_CH5OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_MASK 0x20UL /**< Bit mask for GPIO_CH5OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH5OUTPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN (0x1UL << 6) /**< CH6OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_SHIFT 6 /**< Shift value for GPIO_CH6OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_MASK 0x40UL /**< Bit mask for GPIO_CH6OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH6OUTPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN (0x1UL << 7) /**< CH7OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_SHIFT 7 /**< Shift value for GPIO_CH7OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_MASK 0x80UL /**< Bit mask for GPIO_CH7OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH7OUTPEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN (0x1UL << 8) /**< CH8OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_SHIFT 8 /**< Shift value for GPIO_CH8OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_MASK 0x100UL /**< Bit mask for GPIO_CH8OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH8OUTPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN (0x1UL << 9) /**< CH9OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_SHIFT 9 /**< Shift value for GPIO_CH9OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_MASK 0x200UL /**< Bit mask for GPIO_CH9OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH9OUTPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN (0x1UL << 10) /**< CH10OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_SHIFT 10 /**< Shift value for GPIO_CH10OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_MASK 0x400UL /**< Bit mask for GPIO_CH10OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH10OUTPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN (0x1UL << 11) /**< CH11OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_SHIFT 11 /**< Shift value for GPIO_CH11OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_MASK 0x800UL /**< Bit mask for GPIO_CH11OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH11OUTPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN (0x1UL << 12) /**< CH12OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_SHIFT 12 /**< Shift value for GPIO_CH12OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_MASK 0x1000UL /**< Bit mask for GPIO_CH12OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH12OUTPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN (0x1UL << 13) /**< CH13OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_SHIFT 13 /**< Shift value for GPIO_CH13OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_MASK 0x2000UL /**< Bit mask for GPIO_CH13OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH13OUTPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN (0x1UL << 14) /**< CH14OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_SHIFT 14 /**< Shift value for GPIO_CH14OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_CH14OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH14OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ +#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN (0x1UL << 15) /**< CH15OUT pin enable control bit */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_SHIFT 15 /**< Shift value for GPIO_CH15OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_MASK 0x8000UL /**< Bit mask for GPIO_CH15OUTPEN */ +#define _GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_ROUTEEN */ +#define GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT (_GPIO_LESENSE_ROUTEEN_CH15OUTPEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_LESENSE_ROUTEEN*/ + +/* Bit fields for GPIO_LESENSE CH0OUTROUTE */ +#define _GPIO_LESENSE_CH0OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH0OUTROUTE */ +#define _GPIO_LESENSE_CH0OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH0OUTROUTE */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ +#define GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE */ +#define GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH0OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH0OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH1OUTROUTE */ +#define _GPIO_LESENSE_CH1OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH1OUTROUTE */ +#define _GPIO_LESENSE_CH1OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH1OUTROUTE */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ +#define GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE */ +#define GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH1OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH1OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH2OUTROUTE */ +#define _GPIO_LESENSE_CH2OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH2OUTROUTE */ +#define _GPIO_LESENSE_CH2OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH2OUTROUTE */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ +#define GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE */ +#define GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH2OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH2OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH3OUTROUTE */ +#define _GPIO_LESENSE_CH3OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH3OUTROUTE */ +#define _GPIO_LESENSE_CH3OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH3OUTROUTE */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ +#define GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE */ +#define GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH3OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH3OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH4OUTROUTE */ +#define _GPIO_LESENSE_CH4OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH4OUTROUTE */ +#define _GPIO_LESENSE_CH4OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH4OUTROUTE */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ +#define GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE */ +#define GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH4OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH4OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH5OUTROUTE */ +#define _GPIO_LESENSE_CH5OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH5OUTROUTE */ +#define _GPIO_LESENSE_CH5OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH5OUTROUTE */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ +#define GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE */ +#define GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH5OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH5OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH6OUTROUTE */ +#define _GPIO_LESENSE_CH6OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH6OUTROUTE */ +#define _GPIO_LESENSE_CH6OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH6OUTROUTE */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ +#define GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE */ +#define GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH6OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH6OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH7OUTROUTE */ +#define _GPIO_LESENSE_CH7OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH7OUTROUTE */ +#define _GPIO_LESENSE_CH7OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH7OUTROUTE */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ +#define GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE */ +#define GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH7OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH7OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH8OUTROUTE */ +#define _GPIO_LESENSE_CH8OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH8OUTROUTE */ +#define _GPIO_LESENSE_CH8OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH8OUTROUTE */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ +#define GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE */ +#define GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH8OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH8OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH9OUTROUTE */ +#define _GPIO_LESENSE_CH9OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH9OUTROUTE */ +#define _GPIO_LESENSE_CH9OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH9OUTROUTE */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ +#define GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE */ +#define GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH9OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH9OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH10OUTROUTE */ +#define _GPIO_LESENSE_CH10OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH10OUTROUTE */ +#define _GPIO_LESENSE_CH10OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH10OUTROUTE */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ +#define GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE */ +#define GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH10OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH10OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH11OUTROUTE */ +#define _GPIO_LESENSE_CH11OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH11OUTROUTE */ +#define _GPIO_LESENSE_CH11OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH11OUTROUTE */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ +#define GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE */ +#define GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH11OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH11OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH12OUTROUTE */ +#define _GPIO_LESENSE_CH12OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH12OUTROUTE */ +#define _GPIO_LESENSE_CH12OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH12OUTROUTE */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ +#define GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE */ +#define GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH12OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH12OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH13OUTROUTE */ +#define _GPIO_LESENSE_CH13OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH13OUTROUTE */ +#define _GPIO_LESENSE_CH13OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH13OUTROUTE */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ +#define GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE */ +#define GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH13OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH13OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH14OUTROUTE */ +#define _GPIO_LESENSE_CH14OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH14OUTROUTE */ +#define _GPIO_LESENSE_CH14OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH14OUTROUTE */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ +#define GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE */ +#define GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH14OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH14OUTROUTE*/ + +/* Bit fields for GPIO_LESENSE CH15OUTROUTE */ +#define _GPIO_LESENSE_CH15OUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LESENSE_CH15OUTROUTE */ +#define _GPIO_LESENSE_CH15OUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LESENSE_CH15OUTROUTE */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ +#define GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE */ +#define GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT (_GPIO_LESENSE_CH15OUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LESENSE_CH15OUTROUTE*/ + +/* Bit fields for GPIO_LETIMER ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ + +/* Bit fields for GPIO_LETIMER OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ + +/* Bit fields for GPIO_LETIMER OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ + +/* Bit fields for GPIO_MODEM ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ + +/* Bit fields for GPIO_MODEM DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ + +/* Bit fields for GPIO_MODEM DINROUTE */ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ + +/* Bit fields for GPIO_MODEM DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ + +/* Bit fields for GPIO_PCNT S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ + +/* Bit fields for GPIO_PCNT S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ + +/* Bit fields for GPIO_PRS ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ + +/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ + +/* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ + +/* Bit fields for GPIO_TIMER ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ + +/* Bit fields for GPIO_TIMER CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ + +/* Bit fields for GPIO_TIMER CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ + +/* Bit fields for GPIO_TIMER CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ + +/* Bit fields for GPIO_USART ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ + +/* Bit fields for GPIO_USART CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ + +/* Bit fields for GPIO_USART CTSROUTE */ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ + +/* Bit fields for GPIO_USART RTSROUTE */ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ + +/* Bit fields for GPIO_USART RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ + +/* Bit fields for GPIO_USART CLKROUTE */ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ + +/* Bit fields for GPIO_USART TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_GPIO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h new file mode 100644 index 000000000..4fac32a75 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_gpio_port.h @@ -0,0 +1,493 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 GPIO Port register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef GPIO_PORT_H +#define GPIO_PORT_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief EFR32ZG23 GPIO PORT + *****************************************************************************/ +typedef struct gpio_port_typedef{ + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ +} GPIO_PORT_TypeDef; + +/* Bit fields for GPIO_P CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO_P MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ + +/* Bit fields for GPIO_P MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x00000FFFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEH_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_DEFAULT (_GPIO_P_MODEH_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_DISABLED (_GPIO_P_MODEH_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUT (_GPIO_P_MODEH_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULL (_GPIO_P_MODEH_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_INPUTPULLFILTER (_GPIO_P_MODEH_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_PUSHPULL (_GPIO_P_MODEH_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_PUSHPULLALT (_GPIO_P_MODEH_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDOR (_GPIO_P_MODEH_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDAND (_GPIO_P_MODEH_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDFILTER (_GPIO_P_MODEH_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALT (_GPIO_P_MODEH_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ + +/* Bit fields for GPIO_P DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x000007FFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x7FFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO_P DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x000007FFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x7FFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +/** @} End of group Parts */ + +#endif // GPIO_PORT_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h new file mode 100644 index 000000000..777b53a0e --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfrco.h @@ -0,0 +1,226 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 HFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_HFRCO_H +#define EFR32ZG23_HFRCO_H +#define HFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_HFRCO HFRCO + * @{ + * @brief EFR32ZG23 HFRCO Register Declaration. + *****************************************************************************/ + +/** HFRCO Register Declaration. */ +typedef struct hfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ +} HFRCO_TypeDef; +/** @} End of group EFR32ZG23_HFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_HFRCO + * @{ + * @defgroup EFR32ZG23_HFRCO_BitFields HFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFRCO IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ + +/* Bit fields for HFRCO CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ + +/* Bit fields for HFRCO CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ + +/* Bit fields for HFRCO STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ + +/* Bit fields for HFRCO IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ + +/* Bit fields for HFRCO IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ + +/* Bit fields for HFRCO LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ + +/** @} End of group EFR32ZG23_HFRCO_BitFields */ +/** @} End of group EFR32ZG23_HFRCO */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_HFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h new file mode 100644 index 000000000..0630ad9f3 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_hfxo.h @@ -0,0 +1,801 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 HFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_HFXO_H +#define EFR32ZG23_HFXO_H +#define HFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_HFXO HFXO + * @{ + * @brief EFR32ZG23 HFXO Register Declaration. + *****************************************************************************/ + +/** HFXO Register Declaration. */ +typedef struct hfxo_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED3[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED12[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED21[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} HFXO_TypeDef; +/** @} End of group EFR32ZG23_HFXO */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_HFXO + * @{ + * @defgroup EFR32ZG23_HFXO_BitFields HFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFXO IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ + +/* Bit fields for HFXO XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ + +/* Bit fields for HFXO XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ + +/* Bit fields for HFXO XTALCTRL1 */ +#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ +#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ + +/* Bit fields for HFXO CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ +#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ + +/* Bit fields for HFXO CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ +#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ +#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ +#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ +#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ +#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ +#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ + +/* Bit fields for HFXO BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ +#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ + +/* Bit fields for HFXO BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ + +/* Bit fields for HFXO CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ + +/* Bit fields for HFXO STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ +#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ +#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ +#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ +#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ +#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ +#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ + +/* Bit fields for HFXO IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ + +/* Bit fields for HFXO IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ + +/* Bit fields for HFXO LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ + +/** @} End of group EFR32ZG23_HFXO_BitFields */ +/** @} End of group EFR32ZG23_HFXO */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_HFXO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h new file mode 100644 index 000000000..064b8bf7b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_i2c.h @@ -0,0 +1,744 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 I2C register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_I2C_H +#define EFR32ZG23_I2C_H +#define I2C_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_I2C I2C + * @{ + * @brief EFR32ZG23 I2C Register Declaration. + *****************************************************************************/ + +/** I2C Register Declaration. */ +typedef struct i2c_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} I2C_TypeDef; +/** @} End of group EFR32ZG23_I2C */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_I2C + * @{ + * @defgroup EFR32ZG23_I2C_BitFields I2C Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ + +/* Bit fields for I2C EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ + +/** @} End of group EFR32ZG23_I2C_BitFields */ +/** @} End of group EFR32ZG23_I2C */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_I2C_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h new file mode 100644 index 000000000..4aa2c3129 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_iadc.h @@ -0,0 +1,1036 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 IADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_IADC_H +#define EFR32ZG23_IADC_H +#define IADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_IADC IADC + * @{ + * @brief EFR32ZG23 IADC Register Declaration. + *****************************************************************************/ + +/** IADC CFG Register Group Declaration. */ +typedef struct iadc_cfg_typedef{ + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ +} IADC_CFG_TypeDef; + +/** IADC SCANTABLE Register Group Declaration. */ +typedef struct iadc_scantable_typedef{ + __IOM uint32_t SCAN; /**< SCAN Entry */ +} IADC_SCANTABLE_TypeDef; + +/** IADC Register Declaration. */ +typedef struct iadc_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ +} IADC_TypeDef; +/** @} End of group EFR32ZG23_IADC */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_IADC + * @{ + * @defgroup EFR32ZG23_IADC_BitFields IADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for IADC IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ + +/* Bit fields for IADC EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ +#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ +#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ +#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ + +/* Bit fields for IADC CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ + +/* Bit fields for IADC CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ + +/* Bit fields for IADC TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ + +/* Bit fields for IADC STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ + +/* Bit fields for IADC MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ + +/* Bit fields for IADC STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ + +/* Bit fields for IADC CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ + +/* Bit fields for IADC IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ + +/* Bit fields for IADC IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ + +/* Bit fields for IADC TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_LESENSE 0x00000005UL /**< Mode LESENSE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_LESENSE (_IADC_TRIGGER_SCANTRIGSEL_LESENSE << 0) /**< Shifted mode LESENSE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ + +/* Bit fields for IADC CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ + +/* Bit fields for IADC SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ + +/* Bit fields for IADC SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ + +/* Bit fields for IADC SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ + +/* Bit fields for IADC SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ + +/* Bit fields for IADC SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ + +/* Bit fields for IADC SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ + +/* Bit fields for IADC SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ + +/* Bit fields for IADC SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ + +/* Bit fields for IADC SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ + +/* Bit fields for IADC SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ + +/* Bit fields for IADC SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ + +/* Bit fields for IADC SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ + +/** @} End of group EFR32ZG23_IADC_BitFields */ +/** @} End of group EFR32ZG23_IADC */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_IADC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h new file mode 100644 index 000000000..c28c7cfb8 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_icache.h @@ -0,0 +1,248 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 ICACHE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_ICACHE_H +#define EFR32ZG23_ICACHE_H +#define ICACHE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_ICACHE ICACHE + * @{ + * @brief EFR32ZG23 ICACHE Register Declaration. + *****************************************************************************/ + +/** ICACHE Register Declaration. */ +typedef struct icache_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +} ICACHE_TypeDef; +/** @} End of group EFR32ZG23_ICACHE */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_ICACHE + * @{ + * @defgroup EFR32ZG23_ICACHE_BitFields ICACHE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ICACHE IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ + +/* Bit fields for ICACHE CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ + +/* Bit fields for ICACHE PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ + +/* Bit fields for ICACHE PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ + +/* Bit fields for ICACHE PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ + +/* Bit fields for ICACHE STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ + +/* Bit fields for ICACHE CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ + +/* Bit fields for ICACHE LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ + +/* Bit fields for ICACHE IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ + +/* Bit fields for ICACHE IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ + +/** @} End of group EFR32ZG23_ICACHE_BitFields */ +/** @} End of group EFR32ZG23_ICACHE */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_ICACHE_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h new file mode 100644 index 000000000..d598f7e5f --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_keyscan.h @@ -0,0 +1,386 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 KEYSCAN register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_KEYSCAN_H +#define EFR32ZG23_KEYSCAN_H +#define KEYSCAN_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_KEYSCAN KEYSCAN + * @{ + * @brief EFR32ZG23 KEYSCAN Register Declaration. + *****************************************************************************/ + +/** KEYSCAN Register Declaration. */ +typedef struct keyscan_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t DELAY; /**< Delay */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t DELAY_SET; /**< Delay */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t DELAY_CLR; /**< Delay */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t DELAY_TGL; /**< Delay */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ +} KEYSCAN_TypeDef; +/** @} End of group EFR32ZG23_KEYSCAN */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_KEYSCAN + * @{ + * @defgroup EFR32ZG23_KEYSCAN_BitFields KEYSCAN Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for KEYSCAN IPVERSION */ +#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ +#define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */ + +/* Bit fields for KEYSCAN EN */ +#define _KEYSCAN_EN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_EN */ +#define _KEYSCAN_EN_MASK 0x00000003UL /**< Mask for KEYSCAN_EN */ +#define KEYSCAN_EN_EN (0x1UL << 0) /**< Enable */ +#define _KEYSCAN_EN_EN_SHIFT 0 /**< Shift value for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_MASK 0x1UL /**< Bit mask for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DEFAULT (_KEYSCAN_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DISABLE (_KEYSCAN_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_ENABLE (_KEYSCAN_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _KEYSCAN_EN_DISABLING_SHIFT 1 /**< Shift value for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_MASK 0x2UL /**< Bit mask for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING_DEFAULT (_KEYSCAN_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_EN */ + +/* Bit fields for KEYSCAN SWRST */ +#define _KEYSCAN_SWRST_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_MASK 0x00000003UL /**< Mask for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _KEYSCAN_SWRST_SWRST_SHIFT 0 /**< Shift value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_MASK 0x1UL /**< Bit mask for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST_DEFAULT (_KEYSCAN_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _KEYSCAN_SWRST_RESETTING_SHIFT 1 /**< Shift value for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ + +/* Bit fields for KEYSCAN CFG */ +#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ +#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ +#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ + +/* Bit fields for KEYSCAN CMD */ +#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ +#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ +#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ + +/* Bit fields for KEYSCAN DELAY */ +#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY16 (_KEYSCAN_DELAY_STABDLY_STABDLY16 << 24) /**< Shifted mode STABDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY18 (_KEYSCAN_DELAY_STABDLY_STABDLY18 << 24) /**< Shifted mode STABDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY20 (_KEYSCAN_DELAY_STABDLY_STABDLY20 << 24) /**< Shifted mode STABDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY22 (_KEYSCAN_DELAY_STABDLY_STABDLY22 << 24) /**< Shifted mode STABDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY24 (_KEYSCAN_DELAY_STABDLY_STABDLY24 << 24) /**< Shifted mode STABDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY26 (_KEYSCAN_DELAY_STABDLY_STABDLY26 << 24) /**< Shifted mode STABDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY28 (_KEYSCAN_DELAY_STABDLY_STABDLY28 << 24) /**< Shifted mode STABDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY30 (_KEYSCAN_DELAY_STABDLY_STABDLY30 << 24) /**< Shifted mode STABDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */ + +/* Bit fields for KEYSCAN STATUS */ +#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ +#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ +#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ +#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ + +/* Bit fields for KEYSCAN IF */ +#define _KEYSCAN_IF_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IF */ +#define _KEYSCAN_IF_MASK 0x0000000FUL /**< Mask for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY (0x1UL << 0) /**< No key was pressed */ +#define _KEYSCAN_IF_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY_DEFAULT (_KEYSCAN_IF_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY (0x1UL << 1) /**< A key was pressed */ +#define _KEYSCAN_IF_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY_DEFAULT (_KEYSCAN_IF_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED (0x1UL << 2) /**< Completed scan */ +#define _KEYSCAN_IF_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED_DEFAULT (_KEYSCAN_IF_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IF_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP_DEFAULT (_KEYSCAN_IF_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IF */ + +/* Bit fields for KEYSCAN IEN */ +#define _KEYSCAN_IEN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IEN */ +#define _KEYSCAN_IEN_MASK 0x0000000FUL /**< Mask for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY (0x1UL << 0) /**< No Key was pressed */ +#define _KEYSCAN_IEN_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY_DEFAULT (_KEYSCAN_IEN_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY (0x1UL << 1) /**< A Key was pressed */ +#define _KEYSCAN_IEN_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY_DEFAULT (_KEYSCAN_IEN_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED (0x1UL << 2) /**< Completed Scanning */ +#define _KEYSCAN_IEN_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED_DEFAULT (_KEYSCAN_IEN_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IEN_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP_DEFAULT (_KEYSCAN_IEN_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ + +/** @} End of group EFR32ZG23_KEYSCAN_BitFields */ +/** @} End of group EFR32ZG23_KEYSCAN */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_KEYSCAN_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h new file mode 100644 index 000000000..f786d9698 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcd.h @@ -0,0 +1,632 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LCD register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LCD_H +#define EFR32ZG23_LCD_H +#define LCD_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LCD LCD + * @{ + * @brief EFR32ZG23 LCD Register Declaration. + *****************************************************************************/ + +/** LCD Register Declaration. */ +typedef struct lcd_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t DISPCTRL; /**< Display Control Register */ + __IOM uint32_t BACFG; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t AREGA; /**< Animation Register A */ + __IOM uint32_t AREGB; /**< Animation Register B */ + __IOM uint32_t IF; /**< Interrupt Enable Register */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX; /**< Display Control Extended */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0; /**< Segment Data Register 0 */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1; /**< Segment Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2; /**< Segment Data Register 2 */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3; /**< Segment Data Register 3 */ + uint32_t RESERVED4[25U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL; /**< Update Control */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE; /**< Frame Rate */ + uint32_t RESERVED6[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t DISPCTRL_SET; /**< Display Control Register */ + __IOM uint32_t BACFG_SET; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_SET; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t AREGA_SET; /**< Animation Register A */ + __IOM uint32_t AREGB_SET; /**< Animation Register B */ + __IOM uint32_t IF_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_SET; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_SET; /**< Display Control Extended */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_SET; /**< Segment Data Register 0 */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1_SET; /**< Segment Data Register 1 */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2_SET; /**< Segment Data Register 2 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3_SET; /**< Segment Data Register 3 */ + uint32_t RESERVED11[25U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_SET; /**< Update Control */ + uint32_t RESERVED12[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_SET; /**< Frame Rate */ + uint32_t RESERVED13[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t DISPCTRL_CLR; /**< Display Control Register */ + __IOM uint32_t BACFG_CLR; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_CLR; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t AREGA_CLR; /**< Animation Register A */ + __IOM uint32_t AREGB_CLR; /**< Animation Register B */ + __IOM uint32_t IF_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_CLR; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_CLR; /**< Display Control Extended */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_CLR; /**< Segment Data Register 0 */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1_CLR; /**< Segment Data Register 1 */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2_CLR; /**< Segment Data Register 2 */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3_CLR; /**< Segment Data Register 3 */ + uint32_t RESERVED18[25U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_CLR; /**< Update Control */ + uint32_t RESERVED19[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_CLR; /**< Frame Rate */ + uint32_t RESERVED20[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t DISPCTRL_TGL; /**< Display Control Register */ + __IOM uint32_t BACFG_TGL; /**< Blink and Animation Config Register */ + __IOM uint32_t BACTRL_TGL; /**< Blink and Animation Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t AREGA_TGL; /**< Animation Register A */ + __IOM uint32_t AREGB_TGL; /**< Animation Register B */ + __IOM uint32_t IF_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t BIASCTRL_TGL; /**< Analog BIAS Control */ + __IOM uint32_t DISPCTRLX_TGL; /**< Display Control Extended */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD0_TGL; /**< Segment Data Register 0 */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD1_TGL; /**< Segment Data Register 1 */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD2_TGL; /**< Segment Data Register 2 */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t SEGD3_TGL; /**< Segment Data Register 3 */ + uint32_t RESERVED25[25U]; /**< Reserved for future use */ + __IOM uint32_t UPDATECTRL_TGL; /**< Update Control */ + uint32_t RESERVED26[11U]; /**< Reserved for future use */ + __IOM uint32_t FRAMERATE_TGL; /**< Frame Rate */ +} LCD_TypeDef; +/** @} End of group EFR32ZG23_LCD */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LCD + * @{ + * @defgroup EFR32ZG23_LCD_BitFields LCD Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LCD IPVERSION */ +#define _LCD_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LCD_IPVERSION */ +#define _LCD_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_IPVERSION */ +#define _LCD_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_IPVERSION */ +#define LCD_IPVERSION_IPVERSION_DEFAULT (_LCD_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IPVERSION */ + +/* Bit fields for LCD EN */ +#define _LCD_EN_RESETVALUE 0x00000000UL /**< Default value for LCD_EN */ +#define _LCD_EN_MASK 0x00000003UL /**< Mask for LCD_EN */ +#define LCD_EN_EN (0x1UL << 0) /**< Enable */ +#define _LCD_EN_EN_SHIFT 0 /**< Shift value for LCD_EN */ +#define _LCD_EN_EN_MASK 0x1UL /**< Bit mask for LCD_EN */ +#define _LCD_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ +#define _LCD_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_EN */ +#define _LCD_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_EN */ +#define LCD_EN_EN_DEFAULT (_LCD_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_EN */ +#define LCD_EN_EN_DISABLE (_LCD_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LCD_EN */ +#define LCD_EN_EN_ENABLE (_LCD_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LCD_EN */ +#define LCD_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LCD_EN_DISABLING_SHIFT 1 /**< Shift value for LCD_DISABLING */ +#define _LCD_EN_DISABLING_MASK 0x2UL /**< Bit mask for LCD_DISABLING */ +#define _LCD_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_EN */ +#define LCD_EN_DISABLING_DEFAULT (_LCD_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_EN */ + +/* Bit fields for LCD SWRST */ +#define _LCD_SWRST_RESETVALUE 0x00000000UL /**< Default value for LCD_SWRST */ +#define _LCD_SWRST_MASK 0x00000003UL /**< Mask for LCD_SWRST */ +#define LCD_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LCD_SWRST_SWRST_SHIFT 0 /**< Shift value for LCD_SWRST */ +#define _LCD_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LCD_SWRST */ +#define _LCD_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_SWRST_DEFAULT (_LCD_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LCD_SWRST_RESETTING_SHIFT 1 /**< Shift value for LCD_RESETTING */ +#define _LCD_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LCD_RESETTING */ +#define _LCD_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SWRST */ +#define LCD_SWRST_RESETTING_DEFAULT (_LCD_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SWRST */ + +/* Bit fields for LCD CTRL */ +#define _LCD_CTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_CTRL */ +#define _LCD_CTRL_MASK 0x7F1D0006UL /**< Mask for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */ +#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000001UL /**< Mode FRAMESTART for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000002UL /**< Mode FCEVENT for LCD_CTRL */ +#define _LCD_CTRL_UDCTRL_DISPLAYEVENT 0x00000003UL /**< Mode DISPLAYEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */ +#define LCD_CTRL_UDCTRL_DISPLAYEVENT (_LCD_CTRL_UDCTRL_DISPLAYEVENT << 1) /**< Shifted mode DISPLAYEVENT for LCD_CTRL */ +#define LCD_CTRL_DSC (0x1UL << 16) /**< Direct Segment Control */ +#define _LCD_CTRL_DSC_SHIFT 16 /**< Shift value for LCD_DSC */ +#define _LCD_CTRL_DSC_MASK 0x10000UL /**< Bit mask for LCD_DSC */ +#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_DSC_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_CTRL */ +#define _LCD_CTRL_DSC_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_CTRL */ +#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_DSC_DISABLE (_LCD_CTRL_DSC_DISABLE << 16) /**< Shifted mode DISABLE for LCD_CTRL */ +#define LCD_CTRL_DSC_ENABLE (_LCD_CTRL_DSC_ENABLE << 16) /**< Shifted mode ENABLE for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_SHIFT 18 /**< Shift value for LCD_WARMUPDLY */ +#define _LCD_CTRL_WARMUPDLY_MASK 0x1C0000UL /**< Bit mask for LCD_WARMUPDLY */ +#define _LCD_CTRL_WARMUPDLY_DEFAULT 0x00000004UL /**< Mode DEFAULT for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP1 0x00000000UL /**< Mode WARMUP1 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP31 0x00000001UL /**< Mode WARMUP31 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP63 0x00000002UL /**< Mode WARMUP63 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP125 0x00000003UL /**< Mode WARMUP125 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP250 0x00000004UL /**< Mode WARMUP250 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP500 0x00000005UL /**< Mode WARMUP500 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP1000 0x00000006UL /**< Mode WARMUP1000 for LCD_CTRL */ +#define _LCD_CTRL_WARMUPDLY_WARMUP2000 0x00000007UL /**< Mode WARMUP2000 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_DEFAULT (_LCD_CTRL_WARMUPDLY_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP1 (_LCD_CTRL_WARMUPDLY_WARMUP1 << 18) /**< Shifted mode WARMUP1 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP31 (_LCD_CTRL_WARMUPDLY_WARMUP31 << 18) /**< Shifted mode WARMUP31 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP63 (_LCD_CTRL_WARMUPDLY_WARMUP63 << 18) /**< Shifted mode WARMUP63 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP125 (_LCD_CTRL_WARMUPDLY_WARMUP125 << 18) /**< Shifted mode WARMUP125 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP250 (_LCD_CTRL_WARMUPDLY_WARMUP250 << 18) /**< Shifted mode WARMUP250 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP500 (_LCD_CTRL_WARMUPDLY_WARMUP500 << 18) /**< Shifted mode WARMUP500 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP1000 (_LCD_CTRL_WARMUPDLY_WARMUP1000 << 18) /**< Shifted mode WARMUP1000 for LCD_CTRL */ +#define LCD_CTRL_WARMUPDLY_WARMUP2000 (_LCD_CTRL_WARMUPDLY_WARMUP2000 << 18) /**< Shifted mode WARMUP2000 for LCD_CTRL */ +#define _LCD_CTRL_PRESCALE_SHIFT 24 /**< Shift value for LCD_PRESCALE */ +#define _LCD_CTRL_PRESCALE_MASK 0x7F000000UL /**< Bit mask for LCD_PRESCALE */ +#define _LCD_CTRL_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */ +#define LCD_CTRL_PRESCALE_DEFAULT (_LCD_CTRL_PRESCALE_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_CTRL */ + +/* Bit fields for LCD CMD */ +#define _LCD_CMD_RESETVALUE 0x00000000UL /**< Default value for LCD_CMD */ +#define _LCD_CMD_MASK 0x00000003UL /**< Mask for LCD_CMD */ +#define LCD_CMD_LOAD (0x1UL << 0) /**< Load command */ +#define _LCD_CMD_LOAD_SHIFT 0 /**< Shift value for LCD_LOAD */ +#define _LCD_CMD_LOAD_MASK 0x1UL /**< Bit mask for LCD_LOAD */ +#define _LCD_CMD_LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ +#define LCD_CMD_LOAD_DEFAULT (_LCD_CMD_LOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CMD */ +#define LCD_CMD_CLEAR (0x1UL << 1) /**< Clear command */ +#define _LCD_CMD_CLEAR_SHIFT 1 /**< Shift value for LCD_CLEAR */ +#define _LCD_CMD_CLEAR_MASK 0x2UL /**< Bit mask for LCD_CLEAR */ +#define _LCD_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CMD */ +#define LCD_CMD_CLEAR_DEFAULT (_LCD_CMD_CLEAR_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CMD */ + +/* Bit fields for LCD DISPCTRL */ +#define _LCD_DISPCTRL_RESETVALUE 0x00100000UL /**< Default value for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MASK 0x03700017UL /**< Mask for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */ +#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */ +#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */ +#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_TYPEB 0x00000000UL /**< Mode TYPEB for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_WAVE_TYPEA 0x00000001UL /**< Mode TYPEA for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_TYPEB (_LCD_DISPCTRL_WAVE_TYPEB << 4) /**< Shifted mode TYPEB for LCD_DISPCTRL */ +#define LCD_DISPCTRL_WAVE_TYPEA (_LCD_DISPCTRL_WAVE_TYPEA << 4) /**< Shifted mode TYPEA for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */ +#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */ +#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */ +#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */ +#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */ +#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */ + +/* Bit fields for LCD BACFG */ +#define _LCD_BACFG_RESETVALUE 0x00000007UL /**< Default value for LCD_BACFG */ +#define _LCD_BACFG_MASK 0x00FF0007UL /**< Mask for LCD_BACFG */ +#define _LCD_BACFG_ASTATETOP_SHIFT 0 /**< Shift value for LCD_ASTATETOP */ +#define _LCD_BACFG_ASTATETOP_MASK 0x7UL /**< Bit mask for LCD_ASTATETOP */ +#define _LCD_BACFG_ASTATETOP_DEFAULT 0x00000007UL /**< Mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_ASTATETOP_DEFAULT (_LCD_BACFG_ASTATETOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */ +#define _LCD_BACFG_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */ +#define _LCD_BACFG_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACFG */ +#define _LCD_BACFG_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DEFAULT (_LCD_BACFG_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV1 (_LCD_BACFG_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV2 (_LCD_BACFG_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV4 (_LCD_BACFG_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACFG */ +#define LCD_BACFG_FCPRESC_DIV8 (_LCD_BACFG_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACFG */ +#define _LCD_BACFG_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */ +#define _LCD_BACFG_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */ +#define _LCD_BACFG_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACFG */ +#define LCD_BACFG_FCTOP_DEFAULT (_LCD_BACFG_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACFG */ + +/* Bit fields for LCD BACTRL */ +#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */ +#define _LCD_BACTRL_MASK 0x100003FFUL /**< Mask for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */ +#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */ +#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */ +#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */ +#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_BLANK_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ +#define _LCD_BACTRL_BLANK_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_DISABLE (_LCD_BACTRL_BLANK_DISABLE << 1) /**< Shifted mode DISABLE for LCD_BACTRL */ +#define LCD_BACTRL_BLANK_ENABLE (_LCD_BACTRL_BLANK_ENABLE << 1) /**< Shifted mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */ +#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */ +#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */ +#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */ +#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */ +#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */ +#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */ +#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */ +#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */ +#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */ +#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */ +#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */ +#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */ +#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */ +#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN (0x1UL << 9) /**< Display Counter Enable */ +#define _LCD_BACTRL_DISPLAYCNTEN_SHIFT 9 /**< Shift value for LCD_DISPLAYCNTEN */ +#define _LCD_BACTRL_DISPLAYCNTEN_MASK 0x200UL /**< Bit mask for LCD_DISPLAYCNTEN */ +#define _LCD_BACTRL_DISPLAYCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_DISPLAYCNTEN_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_BACTRL */ +#define _LCD_BACTRL_DISPLAYCNTEN_ENABLE 0x00000001UL /**< Mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_DEFAULT (_LCD_BACTRL_DISPLAYCNTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_DISABLE (_LCD_BACTRL_DISPLAYCNTEN_DISABLE << 9) /**< Shifted mode DISABLE for LCD_BACTRL */ +#define LCD_BACTRL_DISPLAYCNTEN_ENABLE (_LCD_BACTRL_DISPLAYCNTEN_ENABLE << 9) /**< Shifted mode ENABLE for LCD_BACTRL */ +#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */ +#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */ +#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */ +#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */ +#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */ + +/* Bit fields for LCD STATUS */ +#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */ +#define _LCD_STATUS_MASK 0x0000090FUL /**< Mask for LCD_STATUS */ +#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */ +#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */ +#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */ +#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */ +#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_LOADBUSY (0x1UL << 11) /**< Load Synchronization is busy */ +#define _LCD_STATUS_LOADBUSY_SHIFT 11 /**< Shift value for LCD_LOADBUSY */ +#define _LCD_STATUS_LOADBUSY_MASK 0x800UL /**< Bit mask for LCD_LOADBUSY */ +#define _LCD_STATUS_LOADBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */ +#define LCD_STATUS_LOADBUSY_DEFAULT (_LCD_STATUS_LOADBUSY_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_STATUS */ + +/* Bit fields for LCD AREGA */ +#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */ +#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */ +#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */ +#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */ +#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */ + +/* Bit fields for LCD AREGB */ +#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */ +#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */ +#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */ +#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */ +#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */ + +/* Bit fields for LCD IF */ +#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */ +#define _LCD_IF_MASK 0x00000007UL /**< Mask for LCD_IF */ +#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter */ +#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */ +#define LCD_IF_DISPLAY (0x1UL << 1) /**< Display Update Event */ +#define _LCD_IF_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ +#define _LCD_IF_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ +#define _LCD_IF_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_DISPLAY_DEFAULT (_LCD_IF_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IF */ +#define LCD_IF_SYNCBUSYDONE (0x1UL << 2) /**< Synchronization is Done */ +#define _LCD_IF_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ +#define _LCD_IF_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ +#define _LCD_IF_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */ +#define LCD_IF_SYNCBUSYDONE_DEFAULT (_LCD_IF_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IF */ + +/* Bit fields for LCD IEN */ +#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */ +#define _LCD_IEN_MASK 0x00000007UL /**< Mask for LCD_IEN */ +#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter */ +#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */ +#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */ +#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */ +#define LCD_IEN_DISPLAY (0x1UL << 1) /**< Display Update Event */ +#define _LCD_IEN_DISPLAY_SHIFT 1 /**< Shift value for LCD_DISPLAY */ +#define _LCD_IEN_DISPLAY_MASK 0x2UL /**< Bit mask for LCD_DISPLAY */ +#define _LCD_IEN_DISPLAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_DISPLAY_DEFAULT (_LCD_IEN_DISPLAY_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_IEN */ +#define LCD_IEN_SYNCBUSYDONE (0x1UL << 2) /**< Sync Busy Done */ +#define _LCD_IEN_SYNCBUSYDONE_SHIFT 2 /**< Shift value for LCD_SYNCBUSYDONE */ +#define _LCD_IEN_SYNCBUSYDONE_MASK 0x4UL /**< Bit mask for LCD_SYNCBUSYDONE */ +#define _LCD_IEN_SYNCBUSYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */ +#define LCD_IEN_SYNCBUSYDONE_DEFAULT (_LCD_IEN_SYNCBUSYDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_IEN */ + +/* Bit fields for LCD BIASCTRL */ +#define _LCD_BIASCTRL_RESETVALUE 0x001F0000UL /**< Default value for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MASK 0xC45F137FUL /**< Mask for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_RESISTOR_SHIFT 0 /**< Shift value for LCD_RESISTOR */ +#define _LCD_BIASCTRL_RESISTOR_MASK 0xFUL /**< Bit mask for LCD_RESISTOR */ +#define _LCD_BIASCTRL_RESISTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_RESISTOR_DEFAULT (_LCD_BIASCTRL_RESISTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_MASK 0x70UL /**< Bit mask for LCD_BUFDRV */ +#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_BUFBIAS_SHIFT 8 /**< Shift value for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_MASK 0x300UL /**< Bit mask for LCD_BUFBIAS */ +#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE (0x1UL << 12) /**< Mode Setting */ +#define _LCD_BIASCTRL_MODE_SHIFT 12 /**< Shift value for LCD_MODE */ +#define _LCD_BIASCTRL_MODE_MASK 0x1000UL /**< Bit mask for LCD_MODE */ +#define _LCD_BIASCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MODE_STEPDOWN 0x00000000UL /**< Mode STEPDOWN for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_MODE_CHARGEPUMP 0x00000001UL /**< Mode CHARGEPUMP for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_DEFAULT (_LCD_BIASCTRL_MODE_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_STEPDOWN (_LCD_BIASCTRL_MODE_STEPDOWN << 12) /**< Shifted mode STEPDOWN for LCD_BIASCTRL */ +#define LCD_BIASCTRL_MODE_CHARGEPUMP (_LCD_BIASCTRL_MODE_CHARGEPUMP << 12) /**< Shifted mode CHARGEPUMP for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VLCD_SHIFT 16 /**< Shift value for LCD_VLCD */ +#define _LCD_BIASCTRL_VLCD_MASK 0x1F0000UL /**< Bit mask for LCD_VLCD */ +#define _LCD_BIASCTRL_VLCD_DEFAULT 0x0000001FUL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VLCD_DEFAULT (_LCD_BIASCTRL_VLCD_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL (0x1UL << 22) /**< VDDX select */ +#define _LCD_BIASCTRL_VDDXSEL_SHIFT 22 /**< Shift value for LCD_VDDXSEL */ +#define _LCD_BIASCTRL_VDDXSEL_MASK 0x400000UL /**< Bit mask for LCD_VDDXSEL */ +#define _LCD_BIASCTRL_VDDXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VDDXSEL_DVDD 0x00000000UL /**< Mode DVDD for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_VDDXSEL_AVDD 0x00000001UL /**< Mode AVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_DEFAULT (_LCD_BIASCTRL_VDDXSEL_DEFAULT << 22) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_DVDD (_LCD_BIASCTRL_VDDXSEL_DVDD << 22) /**< Shifted mode DVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_VDDXSEL_AVDD (_LCD_BIASCTRL_VDDXSEL_AVDD << 22) /**< Shifted mode AVDD for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE (0x1UL << 26) /**< LCD Gate */ +#define _LCD_BIASCTRL_LCDGATE_SHIFT 26 /**< Shift value for LCD_LCDGATE */ +#define _LCD_BIASCTRL_LCDGATE_MASK 0x4000000UL /**< Bit mask for LCD_LCDGATE */ +#define _LCD_BIASCTRL_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_DEFAULT (_LCD_BIASCTRL_LCDGATE_DEFAULT << 26) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_UNGATE (_LCD_BIASCTRL_LCDGATE_UNGATE << 26) /**< Shifted mode UNGATE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_LCDGATE_GATE (_LCD_BIASCTRL_LCDGATE_GATE << 26) /**< Shifted mode GATE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_SHIFT 30 /**< Shift value for LCD_DMAMODE */ +#define _LCD_BIASCTRL_DMAMODE_MASK 0xC0000000UL /**< Bit mask for LCD_DMAMODE */ +#define _LCD_BIASCTRL_DMAMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMADISABLE 0x00000000UL /**< Mode DMADISABLE for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMAFC 0x00000001UL /**< Mode DMAFC for LCD_BIASCTRL */ +#define _LCD_BIASCTRL_DMAMODE_DMADISPLAY 0x00000002UL /**< Mode DMADISPLAY for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DEFAULT (_LCD_BIASCTRL_DMAMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMADISABLE (_LCD_BIASCTRL_DMAMODE_DMADISABLE << 30) /**< Shifted mode DMADISABLE for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMAFC (_LCD_BIASCTRL_DMAMODE_DMAFC << 30) /**< Shifted mode DMAFC for LCD_BIASCTRL */ +#define LCD_BIASCTRL_DMAMODE_DMADISPLAY (_LCD_BIASCTRL_DMAMODE_DMADISPLAY << 30) /**< Shifted mode DMADISPLAY for LCD_BIASCTRL */ + +/* Bit fields for LCD DISPCTRLX */ +#define _LCD_DISPCTRLX_RESETVALUE 0x00000000UL /**< Default value for LCD_DISPCTRLX */ +#define _LCD_DISPCTRLX_MASK 0x000003FFUL /**< Mask for LCD_DISPCTRLX */ +#define _LCD_DISPCTRLX_DISPLAYDIV_SHIFT 0 /**< Shift value for LCD_DISPLAYDIV */ +#define _LCD_DISPCTRLX_DISPLAYDIV_MASK 0x3FFUL /**< Bit mask for LCD_DISPLAYDIV */ +#define _LCD_DISPCTRLX_DISPLAYDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRLX */ +#define LCD_DISPCTRLX_DISPLAYDIV_DEFAULT (_LCD_DISPCTRLX_DISPLAYDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRLX */ + +/* Bit fields for LCD SEGD0 */ +#define _LCD_SEGD0_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0 */ +#define _LCD_SEGD0_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_SHIFT 0 /**< Shift value for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD0 */ +#define _LCD_SEGD0_SEGD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0 */ +#define LCD_SEGD0_SEGD0_DEFAULT (_LCD_SEGD0_SEGD0_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0 */ + +/* Bit fields for LCD SEGD1 */ +#define _LCD_SEGD1_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1 */ +#define _LCD_SEGD1_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_SHIFT 0 /**< Shift value for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD1 */ +#define _LCD_SEGD1_SEGD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1 */ +#define LCD_SEGD1_SEGD1_DEFAULT (_LCD_SEGD1_SEGD1_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1 */ + +/* Bit fields for LCD SEGD2 */ +#define _LCD_SEGD2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2 */ +#define _LCD_SEGD2_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_SHIFT 0 /**< Shift value for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD2 */ +#define _LCD_SEGD2_SEGD2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2 */ +#define LCD_SEGD2_SEGD2_DEFAULT (_LCD_SEGD2_SEGD2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2 */ + +/* Bit fields for LCD SEGD3 */ +#define _LCD_SEGD3_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3 */ +#define _LCD_SEGD3_MASK 0x000FFFFFUL /**< Mask for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_SHIFT 0 /**< Shift value for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_MASK 0xFFFFFUL /**< Bit mask for LCD_SEGD3 */ +#define _LCD_SEGD3_SEGD3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3 */ +#define LCD_SEGD3_SEGD3_DEFAULT (_LCD_SEGD3_SEGD3_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3 */ + +/* Bit fields for LCD UPDATECTRL */ +#define _LCD_UPDATECTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_MASK 0x0001E100UL /**< Mask for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD (0x1UL << 8) /**< Auto Load */ +#define _LCD_UPDATECTRL_AUTOLOAD_SHIFT 8 /**< Shift value for LCD_AUTOLOAD */ +#define _LCD_UPDATECTRL_AUTOLOAD_MASK 0x100UL /**< Bit mask for LCD_AUTOLOAD */ +#define _LCD_UPDATECTRL_AUTOLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_AUTOLOAD_MANUAL 0x00000000UL /**< Mode MANUAL for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_AUTOLOAD_AUTO 0x00000001UL /**< Mode AUTO for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_DEFAULT (_LCD_UPDATECTRL_AUTOLOAD_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_MANUAL (_LCD_UPDATECTRL_AUTOLOAD_MANUAL << 8) /**< Shifted mode MANUAL for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_AUTOLOAD_AUTO (_LCD_UPDATECTRL_AUTOLOAD_AUTO << 8) /**< Shifted mode AUTO for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SHIFT 13 /**< Shift value for LCD_LOADADDR */ +#define _LCD_UPDATECTRL_LOADADDR_MASK 0x1E000UL /**< Bit mask for LCD_LOADADDR */ +#define _LCD_UPDATECTRL_LOADADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_BACTRLWR 0x00000000UL /**< Mode BACTRLWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_AREGAWR 0x00000001UL /**< Mode AREGAWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_AREGBWR 0x00000002UL /**< Mode AREGBWR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD0WR 0x00000003UL /**< Mode SEGD0WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD1WR 0x00000004UL /**< Mode SEGD1WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD2WR 0x00000005UL /**< Mode SEGD2WR for LCD_UPDATECTRL */ +#define _LCD_UPDATECTRL_LOADADDR_SEGD3WR 0x00000006UL /**< Mode SEGD3WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_DEFAULT (_LCD_UPDATECTRL_LOADADDR_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_BACTRLWR (_LCD_UPDATECTRL_LOADADDR_BACTRLWR << 13) /**< Shifted mode BACTRLWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_AREGAWR (_LCD_UPDATECTRL_LOADADDR_AREGAWR << 13) /**< Shifted mode AREGAWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_AREGBWR (_LCD_UPDATECTRL_LOADADDR_AREGBWR << 13) /**< Shifted mode AREGBWR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD0WR (_LCD_UPDATECTRL_LOADADDR_SEGD0WR << 13) /**< Shifted mode SEGD0WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD1WR (_LCD_UPDATECTRL_LOADADDR_SEGD1WR << 13) /**< Shifted mode SEGD1WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD2WR (_LCD_UPDATECTRL_LOADADDR_SEGD2WR << 13) /**< Shifted mode SEGD2WR for LCD_UPDATECTRL */ +#define LCD_UPDATECTRL_LOADADDR_SEGD3WR (_LCD_UPDATECTRL_LOADADDR_SEGD3WR << 13) /**< Shifted mode SEGD3WR for LCD_UPDATECTRL */ + +/* Bit fields for LCD FRAMERATE */ +#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */ +#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */ +#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */ +#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */ + +/** @} End of group EFR32ZG23_LCD_BitFields */ +/** @} End of group EFR32ZG23_LCD */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LCD_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h new file mode 100644 index 000000000..1e13003b3 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lcdrf.h @@ -0,0 +1,104 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LCDRF register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LCDRF_H +#define EFR32ZG23_LCDRF_H +#define LCDRF_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LCDRF LCDRF + * @{ + * @brief EFR32ZG23 LCDRF Register Declaration. + *****************************************************************************/ + +/** LCDRF Register Declaration. */ +typedef struct lcdrf_typedef{ + __IOM uint32_t RFIMLCDCTRL; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_SET; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_CLR; /**< RF Interference Mitigation LCD Control */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IOM uint32_t RFIMLCDCTRL_TGL; /**< RF Interference Mitigation LCD Control */ +} LCDRF_TypeDef; +/** @} End of group EFR32ZG23_LCDRF */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LCDRF + * @{ + * @defgroup EFR32ZG23_LCDRF_BitFields LCDRF Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LCDRF RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_RESETVALUE 0x00000000UL /**< Default value for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_MASK 0x0000001FUL /**< Mask for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOEN (0x1UL << 0) /**< LCD Charge Pump XO Clock Enable */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_SHIFT 0 /**< Shift value for LCDRF_LCDCPXOEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_MASK 0x1UL /**< Bit mask for LCDRF_LCDCPXOEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL (0x1UL << 1) /**< LCD Charge Pump XO Select */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_SHIFT 1 /**< Shift value for LCDRF_LCDCPXOSEL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_MASK 0x2UL /**< Bit mask for LCDRF_LCDCPXOSEL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO 0x00000000UL /**< Mode INTRCO for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV 0x00000001UL /**< Mode HFXODIV for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_INTRCO << 1) /**< Shifted mode INTRCO for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV (_LCDRF_RFIMLCDCTRL_LCDCPXOSEL_HFXODIV << 1) /**< Shifted mode HFXODIV for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN (0x1UL << 2) /**< LCD Charge Pump XO Retime Enable */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_SHIFT 2 /**< Shift value for LCDRF_LCDCPXORETIMEEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_MASK 0x4UL /**< Bit mask for LCDRF_LCDCPXORETIMEEN */ +#define _LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCPXORETIMEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE (0x1UL << 3) /**< LCD Low Noise */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SHIFT 3 /**< Shift value for LCDRF_LCDLOWNOISE */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_MASK 0x8UL /**< Bit mask for LCDRF_LCDLOWNOISE */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL 0x00000000UL /**< Mode NORMAL for LCDRF_RFIMLCDCTRL */ +#define _LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW 0x00000001UL /**< Mode SLOW for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_DEFAULT << 3) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_NORMAL << 3) /**< Shifted mode NORMAL for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW (_LCDRF_RFIMLCDCTRL_LCDLOWNOISE_SLOW << 3) /**< Shifted mode SLOW for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT (0x1UL << 4) /**< LCD Comparator Dout */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_SHIFT 4 /**< Shift value for LCDRF_LCDCMPDOUT */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_MASK 0x10UL /**< Bit mask for LCDRF_LCDCMPDOUT */ +#define _LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCDRF_RFIMLCDCTRL */ +#define LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT (_LCDRF_RFIMLCDCTRL_LCDCMPDOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for LCDRF_RFIMLCDCTRL */ + +/** @} End of group EFR32ZG23_LCDRF_BitFields */ +/** @} End of group EFR32ZG23_LCDRF */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LCDRF_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h new file mode 100644 index 000000000..0fdee72f1 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldma.h @@ -0,0 +1,685 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LDMA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LDMA_H +#define EFR32ZG23_LDMA_H +#define LDMA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LDMA LDMA + * @{ + * @brief EFR32ZG23 LDMA Register Declaration. + *****************************************************************************/ + +/** LDMA CH Register Group Declaration. */ +typedef struct ldma_ch_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ +} LDMA_CH_TypeDef; + +/** LDMA Register Declaration. */ +typedef struct ldma_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; +/** @} End of group EFR32ZG23_LDMA */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LDMA + * @{ + * @defgroup EFR32ZG23_LDMA_BitFields LDMA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ + +/* Bit fields for LDMA EN */ +#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ +#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ +#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ +#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ +#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ +#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ +#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ +#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ + +/* Bit fields for LDMA SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ + +/* Bit fields for LDMA SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ + +/* Bit fields for LDMA SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ + +/* Bit fields for LDMA SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHDIS */ +#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ +#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ +#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ + +/* Bit fields for LDMA CHSTATUS */ +#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ +#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32ZG23_LDMA_BitFields */ +/** @} End of group EFR32ZG23_LDMA */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LDMA_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h new file mode 100644 index 000000000..66fd91c38 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LDMAXBAR register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LDMAXBAR_H +#define EFR32ZG23_LDMAXBAR_H +#define LDMAXBAR_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LDMAXBAR LDMAXBAR + * @{ + * @brief EFR32ZG23 LDMAXBAR Register Declaration. + *****************************************************************************/ + +/** LDMAXBAR CH Register Group Declaration. */ +typedef struct ldmaxbar_ch_typedef{ + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +} LDMAXBAR_CH_TypeDef; + +/** LDMAXBAR Register Declaration. */ +typedef struct ldmaxbar_typedef{ + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMAXBAR_TypeDef; +/** @} End of group EFR32ZG23_LDMAXBAR */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LDMAXBAR + * @{ + * @defgroup EFR32ZG23_LDMAXBAR_BitFields LDMAXBAR Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMAXBAR IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ + +/* Bit fields for LDMAXBAR CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ + +/** @} End of group EFR32ZG23_LDMAXBAR_BitFields */ +/** @} End of group EFR32ZG23_LDMAXBAR */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LDMAXBAR_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h new file mode 100644 index 000000000..f3b7ab882 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ldmaxbar_defines.h @@ -0,0 +1,165 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LDMA XBAR channel request soruce definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LDMAXBAR_DEFINES_H +#define EFR32ZG23_LDMAXBAR_DEFINES_H + +// Module source selection indices +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x0000000fUL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x00000010UL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000011UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 0x00000012UL /**< Mode EUSART2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE 0x00000013UL /**< Mode LESENSE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LCD 0x00000014UL /**< Mode LCD for LDMAXBAR_CH_REQSEL */ + +// Shifted source selection indices +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2 << 16) /**< Shifted Mode EUSART2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE (_LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted Mode LESENSE for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LCD (_LDMAXBAR_CH_REQSEL_SOURCESEL_LCD << 16) /**< Shifted Mode LCD for LDMAXBAR_CH_REQSEL */ + +// Module signal selection indices +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL 0x00000000UL /** Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL 0x00000001UL /** Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO 0x00000000UL /** Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LCD 0x00000000UL /** Mode LCD for LDMAXBAR_CH_REQSEL**/ + +// Shifted Module signal selection indices +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL << 0) /** Shifted Mode EUSART2RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL << 0) /** Shifted Mode EUSART2TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO (_LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO << 0) /** Shifted Mode LESENSEFIFO for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LCD (_LDMAXBAR_CH_REQSEL_SIGSEL_LCD << 0) /** Shifted Mode LCD for LDMAXBAR_CH_REQSEL**/ + +#endif // EFR32ZG23_LDMAXBAR_DEFINES_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h new file mode 100644 index 000000000..d2fe29010 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lesense.h @@ -0,0 +1,1222 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LESENSE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LESENSE_H +#define EFR32ZG23_LESENSE_H +#define LESENSE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LESENSE LESENSE + * @{ + * @brief EFR32ZG23 LESENSE Register Declaration. + *****************************************************************************/ + +/** LESENSE CH Register Group Declaration. */ +typedef struct lesense_ch_typedef{ + __IOM uint32_t TIMING; /**< Scan configuration */ + __IOM uint32_t INTERACT; /**< Scan configuration */ + __IOM uint32_t EVALCFG; /**< Scan configuration */ + __IOM uint32_t EVALTHRES; /**< Scan confguration */ +} LESENSE_CH_TypeDef; + +/** LESENSE ST Register Group Declaration. */ +typedef struct lesense_st_typedef{ + __IOM uint32_t ARC; /**< State transition Arc */ +} LESENSE_ST_TypeDef; + +/** LESENSE Register Declaration. */ +typedef struct lesense_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration */ + __IOM uint32_t TIMCTRL; /**< Timing Control */ + __IOM uint32_t PERCTRL; /**< Peripheral Control */ + __IOM uint32_t DECCTRL; /**< Decoder control */ + __IOM uint32_t EVALCTRL; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL; /**< PRS control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t CHEN; /**< Channel enable */ + __IM uint32_t SCANRES; /**< Scan result */ + __IM uint32_t STATUS; /**< Status */ + __IM uint32_t RESCOUNT; /**< Result FIFO Count */ + __IM uint32_t RESFIFO; /**< Result Fifo */ + __IM uint32_t CURCH; /**< Current channel index */ + __IM uint32_t DECSTATE; /**< Current decoder state */ + __IM uint32_t SENSORSTATE; /**< Sensor State */ + __IOM uint32_t IDLECONF; /**< IDLE Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED2[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED3[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IOM uint32_t TIMCTRL_SET; /**< Timing Control */ + __IOM uint32_t PERCTRL_SET; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_SET; /**< Decoder control */ + __IOM uint32_t EVALCTRL_SET; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_SET; /**< PRS control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t CHEN_SET; /**< Channel enable */ + __IM uint32_t SCANRES_SET; /**< Scan result */ + __IM uint32_t STATUS_SET; /**< Status */ + __IM uint32_t RESCOUNT_SET; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_SET; /**< Result Fifo */ + __IM uint32_t CURCH_SET; /**< Current channel index */ + __IM uint32_t DECSTATE_SET; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_SET; /**< Sensor State */ + __IOM uint32_t IDLECONF_SET; /**< IDLE Configuration */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization */ + uint32_t RESERVED5[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED6[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_SET[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_SET[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED7[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IOM uint32_t TIMCTRL_CLR; /**< Timing Control */ + __IOM uint32_t PERCTRL_CLR; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_CLR; /**< Decoder control */ + __IOM uint32_t EVALCTRL_CLR; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_CLR; /**< PRS control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t CHEN_CLR; /**< Channel enable */ + __IM uint32_t SCANRES_CLR; /**< Scan result */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IM uint32_t RESCOUNT_CLR; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_CLR; /**< Result Fifo */ + __IM uint32_t CURCH_CLR; /**< Current channel index */ + __IM uint32_t DECSTATE_CLR; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_CLR; /**< Sensor State */ + __IOM uint32_t IDLECONF_CLR; /**< IDLE Configuration */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED10[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_CLR[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_CLR[64U]; /**< Decoding FSM Arcs */ + uint32_t RESERVED11[832U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IOM uint32_t TIMCTRL_TGL; /**< Timing Control */ + __IOM uint32_t PERCTRL_TGL; /**< Peripheral Control */ + __IOM uint32_t DECCTRL_TGL; /**< Decoder control */ + __IOM uint32_t EVALCTRL_TGL; /**< LESENSE evaluation */ + __IOM uint32_t PRSCTRL_TGL; /**< PRS control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t CHEN_TGL; /**< Channel enable */ + __IM uint32_t SCANRES_TGL; /**< Scan result */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IM uint32_t RESCOUNT_TGL; /**< Result FIFO Count */ + __IM uint32_t RESFIFO_TGL; /**< Result Fifo */ + __IM uint32_t CURCH_TGL; /**< Current channel index */ + __IM uint32_t DECSTATE_TGL; /**< Current decoder state */ + __IM uint32_t SENSORSTATE_TGL; /**< Sensor State */ + __IOM uint32_t IDLECONF_TGL; /**< IDLE Configuration */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + uint32_t RESERVED14[38U]; /**< Reserved for future use */ + LESENSE_CH_TypeDef CH_TGL[16U]; /**< Channels */ + LESENSE_ST_TypeDef ST_TGL[64U]; /**< Decoding FSM Arcs */ +} LESENSE_TypeDef; +/** @} End of group EFR32ZG23_LESENSE */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LESENSE + * @{ + * @defgroup EFR32ZG23_LESENSE_BitFields LESENSE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LESENSE IPVERSION */ +#define _LESENSE_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LESENSE_IPVERSION */ +#define _LESENSE_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LESENSE_IPVERSION */ +#define LESENSE_IPVERSION_IPVERSION_DEFAULT (_LESENSE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IPVERSION */ + +/* Bit fields for LESENSE EN */ +#define _LESENSE_EN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EN */ +#define _LESENSE_EN_MASK 0x00000003UL /**< Mask for LESENSE_EN */ +#define LESENSE_EN_EN (0x1UL << 0) /**< Enable */ +#define _LESENSE_EN_EN_SHIFT 0 /**< Shift value for LESENSE_EN */ +#define _LESENSE_EN_EN_MASK 0x1UL /**< Bit mask for LESENSE_EN */ +#define _LESENSE_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ +#define _LESENSE_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_EN */ +#define _LESENSE_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_EN */ +#define LESENSE_EN_EN_DEFAULT (_LESENSE_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EN */ +#define LESENSE_EN_EN_DISABLE (_LESENSE_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_EN */ +#define LESENSE_EN_EN_ENABLE (_LESENSE_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for LESENSE_EN */ +#define LESENSE_EN_DISABLING (0x1UL << 1) /**< Disabling */ +#define _LESENSE_EN_DISABLING_SHIFT 1 /**< Shift value for LESENSE_DISABLING */ +#define _LESENSE_EN_DISABLING_MASK 0x2UL /**< Bit mask for LESENSE_DISABLING */ +#define _LESENSE_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EN */ +#define LESENSE_EN_DISABLING_DEFAULT (_LESENSE_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_EN */ + +/* Bit fields for LESENSE SWRST */ +#define _LESENSE_SWRST_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SWRST */ +#define _LESENSE_SWRST_MASK 0x00000003UL /**< Mask for LESENSE_SWRST */ +#define LESENSE_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LESENSE_SWRST_SWRST_SHIFT 0 /**< Shift value for LESENSE_SWRST */ +#define _LESENSE_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LESENSE_SWRST */ +#define _LESENSE_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_SWRST_DEFAULT (_LESENSE_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LESENSE_SWRST_RESETTING_SHIFT 1 /**< Shift value for LESENSE_RESETTING */ +#define _LESENSE_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LESENSE_RESETTING */ +#define _LESENSE_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SWRST */ +#define LESENSE_SWRST_RESETTING_DEFAULT (_LESENSE_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_SWRST */ + +/* Bit fields for LESENSE CFG */ +#define _LESENSE_CFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CFG */ +#define _LESENSE_CFG_MASK 0x00020FEFUL /**< Mask for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_SHIFT 0 /**< Shift value for LESENSE_SCANMODE */ +#define _LESENSE_CFG_SCANMODE_MASK 0x3UL /**< Bit mask for LESENSE_SCANMODE */ +#define _LESENSE_CFG_SCANMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_PERIODIC 0x00000000UL /**< Mode PERIODIC for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANMODE_PRS 0x00000002UL /**< Mode PRS for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_DEFAULT (_LESENSE_CFG_SCANMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_PERIODIC (_LESENSE_CFG_SCANMODE_PERIODIC << 0) /**< Shifted mode PERIODIC for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_ONESHOT (_LESENSE_CFG_SCANMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LESENSE_CFG */ +#define LESENSE_CFG_SCANMODE_PRS (_LESENSE_CFG_SCANMODE_PRS << 0) /**< Shifted mode PRS for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_SHIFT 2 /**< Shift value for LESENSE_SCANCONF */ +#define _LESENSE_CFG_SCANCONF_MASK 0xCUL /**< Bit mask for LESENSE_SCANCONF */ +#define _LESENSE_CFG_SCANCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_DIRMAP 0x00000000UL /**< Mode DIRMAP for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_INVMAP 0x00000001UL /**< Mode INVMAP for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_TOGGLE 0x00000002UL /**< Mode TOGGLE for LESENSE_CFG */ +#define _LESENSE_CFG_SCANCONF_DECDEF 0x00000003UL /**< Mode DECDEF for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DEFAULT (_LESENSE_CFG_SCANCONF_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DIRMAP (_LESENSE_CFG_SCANCONF_DIRMAP << 2) /**< Shifted mode DIRMAP for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_INVMAP (_LESENSE_CFG_SCANCONF_INVMAP << 2) /**< Shifted mode INVMAP for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_TOGGLE (_LESENSE_CFG_SCANCONF_TOGGLE << 2) /**< Shifted mode TOGGLE for LESENSE_CFG */ +#define LESENSE_CFG_SCANCONF_DECDEF (_LESENSE_CFG_SCANCONF_DECDEF << 2) /**< Shifted mode DECDEF for LESENSE_CFG */ +#define LESENSE_CFG_DUALSAMPLE (0x1UL << 5) /**< Enable dual sample mode */ +#define _LESENSE_CFG_DUALSAMPLE_SHIFT 5 /**< Shift value for LESENSE_DUALSAMPLE */ +#define _LESENSE_CFG_DUALSAMPLE_MASK 0x20UL /**< Bit mask for LESENSE_DUALSAMPLE */ +#define _LESENSE_CFG_DUALSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DUALSAMPLE_DEFAULT (_LESENSE_CFG_DUALSAMPLE_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_STRSCANRES (0x1UL << 6) /**< Enable storing of SCANRES */ +#define _LESENSE_CFG_STRSCANRES_SHIFT 6 /**< Shift value for LESENSE_STRSCANRES */ +#define _LESENSE_CFG_STRSCANRES_MASK 0x40UL /**< Bit mask for LESENSE_STRSCANRES */ +#define _LESENSE_CFG_STRSCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_STRSCANRES_DEFAULT (_LESENSE_CFG_STRSCANRES_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU (0x1UL << 7) /**< DMA wake-up from EM2 */ +#define _LESENSE_CFG_DMAWU_SHIFT 7 /**< Shift value for LESENSE_DMAWU */ +#define _LESENSE_CFG_DMAWU_MASK 0x80UL /**< Bit mask for LESENSE_DMAWU */ +#define _LESENSE_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_DMAWU_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CFG */ +#define _LESENSE_CFG_DMAWU_ENABLE 0x00000001UL /**< Mode ENABLE for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_DEFAULT (_LESENSE_CFG_DMAWU_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_DISABLE (_LESENSE_CFG_DMAWU_DISABLE << 7) /**< Shifted mode DISABLE for LESENSE_CFG */ +#define LESENSE_CFG_DMAWU_ENABLE (_LESENSE_CFG_DMAWU_ENABLE << 7) /**< Shifted mode ENABLE for LESENSE_CFG */ +#define _LESENSE_CFG_RESFIDL_SHIFT 8 /**< Shift value for LESENSE_RESFIDL */ +#define _LESENSE_CFG_RESFIDL_MASK 0xF00UL /**< Bit mask for LESENSE_RESFIDL */ +#define _LESENSE_CFG_RESFIDL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_RESFIDL_DEFAULT (_LESENSE_CFG_RESFIDL_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN (0x1UL << 17) /**< Debug Mode Run Enable */ +#define _LESENSE_CFG_DEBUGRUN_SHIFT 17 /**< Shift value for LESENSE_DEBUGRUN */ +#define _LESENSE_CFG_DEBUGRUN_MASK 0x20000UL /**< Bit mask for LESENSE_DEBUGRUN */ +#define _LESENSE_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CFG */ +#define _LESENSE_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for LESENSE_CFG */ +#define _LESENSE_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_DEFAULT (_LESENSE_CFG_DEBUGRUN_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_X0 (_LESENSE_CFG_DEBUGRUN_X0 << 17) /**< Shifted mode X0 for LESENSE_CFG */ +#define LESENSE_CFG_DEBUGRUN_X1 (_LESENSE_CFG_DEBUGRUN_X1 << 17) /**< Shifted mode X1 for LESENSE_CFG */ + +/* Bit fields for LESENSE TIMCTRL */ +#define _LESENSE_TIMCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_MASK 0x10CFF773UL /**< Mask for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_SHIFT 0 /**< Shift value for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_MASK 0x3UL /**< Bit mask for LESENSE_AUXPRESC */ +#define _LESENSE_TIMCTRL_AUXPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DEFAULT (_LESENSE_TIMCTRL_AUXPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV1 (_LESENSE_TIMCTRL_AUXPRESC_DIV1 << 0) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV2 (_LESENSE_TIMCTRL_AUXPRESC_DIV2 << 0) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV4 (_LESENSE_TIMCTRL_AUXPRESC_DIV4 << 0) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXPRESC_DIV8 (_LESENSE_TIMCTRL_AUXPRESC_DIV8 << 0) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_SHIFT 4 /**< Shift value for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_MASK 0x70UL /**< Bit mask for LESENSE_LFPRESC */ +#define _LESENSE_TIMCTRL_LFPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_LFPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DEFAULT (_LESENSE_TIMCTRL_LFPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV1 (_LESENSE_TIMCTRL_LFPRESC_DIV1 << 4) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV2 (_LESENSE_TIMCTRL_LFPRESC_DIV2 << 4) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV4 (_LESENSE_TIMCTRL_LFPRESC_DIV4 << 4) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV8 (_LESENSE_TIMCTRL_LFPRESC_DIV8 << 4) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV16 (_LESENSE_TIMCTRL_LFPRESC_DIV16 << 4) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV32 (_LESENSE_TIMCTRL_LFPRESC_DIV32 << 4) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV64 (_LESENSE_TIMCTRL_LFPRESC_DIV64 << 4) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_LFPRESC_DIV128 (_LESENSE_TIMCTRL_LFPRESC_DIV128 << 4) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_SHIFT 8 /**< Shift value for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_MASK 0x700UL /**< Bit mask for LESENSE_PCPRESC */ +#define _LESENSE_TIMCTRL_PCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DEFAULT (_LESENSE_TIMCTRL_PCPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV1 (_LESENSE_TIMCTRL_PCPRESC_DIV1 << 8) /**< Shifted mode DIV1 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV2 (_LESENSE_TIMCTRL_PCPRESC_DIV2 << 8) /**< Shifted mode DIV2 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV4 (_LESENSE_TIMCTRL_PCPRESC_DIV4 << 8) /**< Shifted mode DIV4 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV8 (_LESENSE_TIMCTRL_PCPRESC_DIV8 << 8) /**< Shifted mode DIV8 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV16 (_LESENSE_TIMCTRL_PCPRESC_DIV16 << 8) /**< Shifted mode DIV16 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV32 (_LESENSE_TIMCTRL_PCPRESC_DIV32 << 8) /**< Shifted mode DIV32 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV64 (_LESENSE_TIMCTRL_PCPRESC_DIV64 << 8) /**< Shifted mode DIV64 for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCPRESC_DIV128 (_LESENSE_TIMCTRL_PCPRESC_DIV128 << 8) /**< Shifted mode DIV128 for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_PCTOP_SHIFT 12 /**< Shift value for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_MASK 0xFF000UL /**< Bit mask for LESENSE_PCTOP */ +#define _LESENSE_TIMCTRL_PCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_PCTOP_DEFAULT (_LESENSE_TIMCTRL_PCTOP_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_STARTDLY_SHIFT 22 /**< Shift value for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_MASK 0xC00000UL /**< Bit mask for LESENSE_STARTDLY */ +#define _LESENSE_TIMCTRL_STARTDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_STARTDLY_DEFAULT (_LESENSE_TIMCTRL_STARTDLY_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP (0x1UL << 28) /**< AUX startup config */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_SHIFT 28 /**< Shift value for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_MASK 0x10000000UL /**< Bit mask for LESENSE_AUXSTARTUP */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND 0x00000000UL /**< Mode PREDEMAND for LESENSE_TIMCTRL */ +#define _LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND 0x00000001UL /**< Mode ONDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT (_LESENSE_TIMCTRL_AUXSTARTUP_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_PREDEMAND << 28) /**< Shifted mode PREDEMAND for LESENSE_TIMCTRL */ +#define LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND (_LESENSE_TIMCTRL_AUXSTARTUP_ONDEMAND << 28) /**< Shifted mode ONDEMAND for LESENSE_TIMCTRL */ + +/* Bit fields for LESENSE PERCTRL */ +#define _LESENSE_PERCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_MASK 0x03500144UL /**< Mask for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA (0x1UL << 2) /**< DAC CH0 data selection. */ +#define _LESENSE_PERCTRL_DACCH0DATA_SHIFT 2 /**< Shift value for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_MASK 0x4UL /**< Bit mask for LESENSE_DACCH0DATA */ +#define _LESENSE_PERCTRL_DACCH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_DACDATA 0x00000000UL /**< Mode DACDATA for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCH0DATA_THRES 0x00000001UL /**< Mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DEFAULT (_LESENSE_PERCTRL_DACCH0DATA_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_DACDATA (_LESENSE_PERCTRL_DACCH0DATA_DACDATA << 2) /**< Shifted mode DACDATA for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCH0DATA_THRES (_LESENSE_PERCTRL_DACCH0DATA_THRES << 2) /**< Shifted mode THRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP (0x1UL << 6) /**< DAC startup configuration */ +#define _LESENSE_PERCTRL_DACSTARTUP_SHIFT 6 /**< Shift value for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_MASK 0x40UL /**< Bit mask for LESENSE_DACSTARTUP */ +#define _LESENSE_PERCTRL_DACSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE 0x00000000UL /**< Mode FULLCYCLE for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE 0x00000001UL /**< Mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_DEFAULT (_LESENSE_PERCTRL_DACSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE (_LESENSE_PERCTRL_DACSTARTUP_FULLCYCLE << 6) /**< Shifted mode FULLCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE (_LESENSE_PERCTRL_DACSTARTUP_HALFCYCLE << 6) /**< Shifted mode HALFCYCLE for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG (0x1UL << 8) /**< DAC conversion trigger configuration */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SHIFT 8 /**< Shift value for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_MASK 0x100UL /**< Bit mask for LESENSE_DACCONVTRIG */ +#define _LESENSE_PERCTRL_DACCONVTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART 0x00000000UL /**< Mode CHANNELSTART for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_DACCONVTRIG_SCANSTART 0x00000001UL /**< Mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_DEFAULT (_LESENSE_PERCTRL_DACCONVTRIG_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART (_LESENSE_PERCTRL_DACCONVTRIG_CHANNELSTART << 8) /**< Shifted mode CHANNELSTART for LESENSE_PERCTRL*/ +#define LESENSE_PERCTRL_DACCONVTRIG_SCANSTART (_LESENSE_PERCTRL_DACCONVTRIG_SCANSTART << 8) /**< Shifted mode SCANSTART for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE (0x1UL << 20) /**< ACMP0 mode */ +#define _LESENSE_PERCTRL_ACMP0MODE_SHIFT 20 /**< Shift value for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_MASK 0x100000UL /**< Bit mask for LESENSE_ACMP0MODE */ +#define _LESENSE_PERCTRL_ACMP0MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP0MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_DEFAULT (_LESENSE_PERCTRL_ACMP0MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUX (_LESENSE_PERCTRL_ACMP0MODE_MUX << 20) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP0MODE_MUXTHRES << 20) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE (0x1UL << 22) /**< ACMP1 mode */ +#define _LESENSE_PERCTRL_ACMP1MODE_SHIFT 22 /**< Shift value for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_MASK 0x400000UL /**< Bit mask for LESENSE_ACMP1MODE */ +#define _LESENSE_PERCTRL_ACMP1MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUX 0x00000000UL /**< Mode MUX for LESENSE_PERCTRL */ +#define _LESENSE_PERCTRL_ACMP1MODE_MUXTHRES 0x00000001UL /**< Mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_DEFAULT (_LESENSE_PERCTRL_ACMP1MODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUX (_LESENSE_PERCTRL_ACMP1MODE_MUX << 22) /**< Shifted mode MUX for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1MODE_MUXTHRES (_LESENSE_PERCTRL_ACMP1MODE_MUXTHRES << 22) /**< Shifted mode MUXTHRES for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV (0x1UL << 24) /**< Invert analog comparator 0 output */ +#define _LESENSE_PERCTRL_ACMP0INV_SHIFT 24 /**< Shift value for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_MASK 0x1000000UL /**< Bit mask for LESENSE_ACMP0INV */ +#define _LESENSE_PERCTRL_ACMP0INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP0INV_DEFAULT (_LESENSE_PERCTRL_ACMP0INV_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV (0x1UL << 25) /**< Invert analog comparator 1 output */ +#define _LESENSE_PERCTRL_ACMP1INV_SHIFT 25 /**< Shift value for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_MASK 0x2000000UL /**< Bit mask for LESENSE_ACMP1INV */ +#define _LESENSE_PERCTRL_ACMP1INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PERCTRL */ +#define LESENSE_PERCTRL_ACMP1INV_DEFAULT (_LESENSE_PERCTRL_ACMP1INV_DEFAULT << 25) /**< Shifted mode DEFAULT for LESENSE_PERCTRL */ + +/* Bit fields for LESENSE DECCTRL */ +#define _LESENSE_DECCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECCTRL */ +#define _LESENSE_DECCTRL_MASK 0x000000FDUL /**< Mask for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DECDIS (0x1UL << 0) /**< Disable the decoder */ +#define _LESENSE_DECCTRL_DECDIS_SHIFT 0 /**< Shift value for LESENSE_DECDIS */ +#define _LESENSE_DECCTRL_DECDIS_MASK 0x1UL /**< Bit mask for LESENSE_DECDIS */ +#define _LESENSE_DECCTRL_DECDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_DECDIS_DEFAULT (_LESENSE_DECCTRL_DECDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP (0x1UL << 2) /**< Enable decoder to channel interrupt map */ +#define _LESENSE_DECCTRL_INTMAP_SHIFT 2 /**< Shift value for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_MASK 0x4UL /**< Bit mask for LESENSE_INTMAP */ +#define _LESENSE_DECCTRL_INTMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_INTMAP_DEFAULT (_LESENSE_DECCTRL_INTMAP_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0 (0x1UL << 3) /**< Enable decoder hysteresis on PRS0 output */ +#define _LESENSE_DECCTRL_HYSTPRS0_SHIFT 3 /**< Shift value for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_MASK 0x8UL /**< Bit mask for LESENSE_HYSTPRS0 */ +#define _LESENSE_DECCTRL_HYSTPRS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS0_DEFAULT (_LESENSE_DECCTRL_HYSTPRS0_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1 (0x1UL << 4) /**< Enable decoder hysteresis on PRS1 output */ +#define _LESENSE_DECCTRL_HYSTPRS1_SHIFT 4 /**< Shift value for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_MASK 0x10UL /**< Bit mask for LESENSE_HYSTPRS1 */ +#define _LESENSE_DECCTRL_HYSTPRS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS1_DEFAULT (_LESENSE_DECCTRL_HYSTPRS1_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2 (0x1UL << 5) /**< Enable decoder hysteresis on PRS2 output */ +#define _LESENSE_DECCTRL_HYSTPRS2_SHIFT 5 /**< Shift value for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_MASK 0x20UL /**< Bit mask for LESENSE_HYSTPRS2 */ +#define _LESENSE_DECCTRL_HYSTPRS2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTPRS2_DEFAULT (_LESENSE_DECCTRL_HYSTPRS2_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ (0x1UL << 6) /**< Enable decoder hysteresis on interrupt r */ +#define _LESENSE_DECCTRL_HYSTIRQ_SHIFT 6 /**< Shift value for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_MASK 0x40UL /**< Bit mask for LESENSE_HYSTIRQ */ +#define _LESENSE_DECCTRL_HYSTIRQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_HYSTIRQ_DEFAULT (_LESENSE_DECCTRL_HYSTIRQ_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT (0x1UL << 7) /**< Enable count mode on decoder PRS channel */ +#define _LESENSE_DECCTRL_PRSCNT_SHIFT 7 /**< Shift value for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_MASK 0x80UL /**< Bit mask for LESENSE_PRSCNT */ +#define _LESENSE_DECCTRL_PRSCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECCTRL */ +#define LESENSE_DECCTRL_PRSCNT_DEFAULT (_LESENSE_DECCTRL_PRSCNT_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_DECCTRL */ + +/* Bit fields for LESENSE EVALCTRL */ +#define _LESENSE_EVALCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_MASK 0x0000FFFFUL /**< Mask for LESENSE_EVALCTRL */ +#define _LESENSE_EVALCTRL_WINSIZE_SHIFT 0 /**< Shift value for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_MASK 0xFFFFUL /**< Bit mask for LESENSE_WINSIZE */ +#define _LESENSE_EVALCTRL_WINSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_EVALCTRL */ +#define LESENSE_EVALCTRL_WINSIZE_DEFAULT (_LESENSE_EVALCTRL_WINSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_EVALCTRL */ + +/* Bit fields for LESENSE PRSCTRL */ +#define _LESENSE_PRSCTRL_RESETVALUE 0x00000000UL /**< Default value for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_MASK 0x00011F1FUL /**< Mask for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_SHIFT 0 /**< Shift value for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_MASK 0x1FUL /**< Bit mask for LESENSE_DECCMPVAL */ +#define _LESENSE_PRSCTRL_DECCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPVAL_DEFAULT (_LESENSE_PRSCTRL_DECCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define _LESENSE_PRSCTRL_DECCMPMASK_SHIFT 8 /**< Shift value for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_MASK 0x1F00UL /**< Bit mask for LESENSE_DECCMPMASK */ +#define _LESENSE_PRSCTRL_DECCMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPMASK_DEFAULT (_LESENSE_PRSCTRL_DECCMPMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN (0x1UL << 16) /**< Enable PRS output DECCMP */ +#define _LESENSE_PRSCTRL_DECCMPEN_SHIFT 16 /**< Shift value for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_MASK 0x10000UL /**< Bit mask for LESENSE_DECCMPEN */ +#define _LESENSE_PRSCTRL_DECCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_PRSCTRL */ +#define LESENSE_PRSCTRL_DECCMPEN_DEFAULT (_LESENSE_PRSCTRL_DECCMPEN_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_PRSCTRL */ + +/* Bit fields for LESENSE CMD */ +#define _LESENSE_CMD_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CMD */ +#define _LESENSE_CMD_MASK 0x0000000FUL /**< Mask for LESENSE_CMD */ +#define LESENSE_CMD_START (0x1UL << 0) /**< Start scanning of sensors. */ +#define _LESENSE_CMD_START_SHIFT 0 /**< Shift value for LESENSE_START */ +#define _LESENSE_CMD_START_MASK 0x1UL /**< Bit mask for LESENSE_START */ +#define _LESENSE_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_START_DEFAULT (_LESENSE_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP (0x1UL << 1) /**< Stop scanning of sensors */ +#define _LESENSE_CMD_STOP_SHIFT 1 /**< Shift value for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_MASK 0x2UL /**< Bit mask for LESENSE_STOP */ +#define _LESENSE_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_STOP_DEFAULT (_LESENSE_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE (0x1UL << 2) /**< Start decoder */ +#define _LESENSE_CMD_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CMD_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_DECODE_DEFAULT (_LESENSE_CMD_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF (0x1UL << 3) /**< Clear result buffer */ +#define _LESENSE_CMD_CLEARBUF_SHIFT 3 /**< Shift value for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_MASK 0x8UL /**< Bit mask for LESENSE_CLEARBUF */ +#define _LESENSE_CMD_CLEARBUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CMD */ +#define LESENSE_CMD_CLEARBUF_DEFAULT (_LESENSE_CMD_CLEARBUF_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CMD */ + +/* Bit fields for LESENSE CHEN */ +#define _LESENSE_CHEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CHEN */ +#define _LESENSE_CHEN_MASK 0x0000FFFFUL /**< Mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_SHIFT 0 /**< Shift value for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_MASK 0xFFFFUL /**< Bit mask for LESENSE_CHEN */ +#define _LESENSE_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CHEN */ +#define LESENSE_CHEN_CHEN_DEFAULT (_LESENSE_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CHEN */ + +/* Bit fields for LESENSE SCANRES */ +#define _LESENSE_SCANRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_SHIFT 0 /**< Shift value for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_SCANRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_SCANRES_DEFAULT (_LESENSE_SCANRES_SCANRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ +#define _LESENSE_SCANRES_STEPDIR_SHIFT 16 /**< Shift value for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_MASK 0xFFFF0000UL /**< Bit mask for LESENSE_STEPDIR */ +#define _LESENSE_SCANRES_STEPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SCANRES */ +#define LESENSE_SCANRES_STEPDIR_DEFAULT (_LESENSE_SCANRES_STEPDIR_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_SCANRES */ + +/* Bit fields for LESENSE STATUS */ +#define _LESENSE_STATUS_RESETVALUE 0x00000000UL /**< Default value for LESENSE_STATUS */ +#define _LESENSE_STATUS_MASK 0x0000007BUL /**< Mask for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOV (0x1UL << 0) /**< Result fifo valid */ +#define _LESENSE_STATUS_RESFIFOV_SHIFT 0 /**< Shift value for LESENSE_RESFIFOV */ +#define _LESENSE_STATUS_RESFIFOV_MASK 0x1UL /**< Bit mask for LESENSE_RESFIFOV */ +#define _LESENSE_STATUS_RESFIFOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOV_DEFAULT (_LESENSE_STATUS_RESFIFOV_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOFULL (0x1UL << 1) /**< Result fifo full */ +#define _LESENSE_STATUS_RESFIFOFULL_SHIFT 1 /**< Shift value for LESENSE_RESFIFOFULL */ +#define _LESENSE_STATUS_RESFIFOFULL_MASK 0x2UL /**< Bit mask for LESENSE_RESFIFOFULL */ +#define _LESENSE_STATUS_RESFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RESFIFOFULL_DEFAULT (_LESENSE_STATUS_RESFIFOFULL_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE (0x1UL << 3) /**< LESENSE scan active */ +#define _LESENSE_STATUS_SCANACTIVE_SHIFT 3 /**< Shift value for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_MASK 0x8UL /**< Bit mask for LESENSE_SCANACTIVE */ +#define _LESENSE_STATUS_SCANACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_SCANACTIVE_DEFAULT (_LESENSE_STATUS_SCANACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING (0x1UL << 4) /**< LESENSE periodic counter running */ +#define _LESENSE_STATUS_RUNNING_SHIFT 4 /**< Shift value for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_MASK 0x10UL /**< Bit mask for LESENSE_RUNNING */ +#define _LESENSE_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_RUNNING_DEFAULT (_LESENSE_STATUS_RUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_READBUSY (0x1UL << 5) /**< FIFO Read Busy */ +#define _LESENSE_STATUS_READBUSY_SHIFT 5 /**< Shift value for LESENSE_READBUSY */ +#define _LESENSE_STATUS_READBUSY_MASK 0x20UL /**< Bit mask for LESENSE_READBUSY */ +#define _LESENSE_STATUS_READBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_READBUSY_DEFAULT (_LESENSE_STATUS_READBUSY_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_FLUSHING (0x1UL << 6) /**< FIFO Flushing */ +#define _LESENSE_STATUS_FLUSHING_SHIFT 6 /**< Shift value for LESENSE_FLUSHING */ +#define _LESENSE_STATUS_FLUSHING_MASK 0x40UL /**< Bit mask for LESENSE_FLUSHING */ +#define _LESENSE_STATUS_FLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_STATUS */ +#define LESENSE_STATUS_FLUSHING_DEFAULT (_LESENSE_STATUS_FLUSHING_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_STATUS */ + +/* Bit fields for LESENSE RESCOUNT */ +#define _LESENSE_RESCOUNT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_MASK 0x0000001FUL /**< Mask for LESENSE_RESCOUNT */ +#define _LESENSE_RESCOUNT_COUNT_SHIFT 0 /**< Shift value for LESENSE_COUNT */ +#define _LESENSE_RESCOUNT_COUNT_MASK 0x1FUL /**< Bit mask for LESENSE_COUNT */ +#define _LESENSE_RESCOUNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESCOUNT */ +#define LESENSE_RESCOUNT_COUNT_DEFAULT (_LESENSE_RESCOUNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESCOUNT */ + +/* Bit fields for LESENSE RESFIFO */ +#define _LESENSE_RESFIFO_RESETVALUE 0x00000000UL /**< Default value for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_MASK 0x000FFFFFUL /**< Mask for LESENSE_RESFIFO */ +#define _LESENSE_RESFIFO_BUFDATASRC_SHIFT 0 /**< Shift value for LESENSE_BUFDATASRC */ +#define _LESENSE_RESFIFO_BUFDATASRC_MASK 0xFFFFFUL /**< Bit mask for LESENSE_BUFDATASRC */ +#define _LESENSE_RESFIFO_BUFDATASRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_RESFIFO */ +#define LESENSE_RESFIFO_BUFDATASRC_DEFAULT (_LESENSE_RESFIFO_BUFDATASRC_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_RESFIFO */ + +/* Bit fields for LESENSE CURCH */ +#define _LESENSE_CURCH_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CURCH */ +#define _LESENSE_CURCH_MASK 0x0000000FUL /**< Mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_SHIFT 0 /**< Shift value for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_MASK 0xFUL /**< Bit mask for LESENSE_CURCH */ +#define _LESENSE_CURCH_CURCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CURCH */ +#define LESENSE_CURCH_CURCH_DEFAULT (_LESENSE_CURCH_CURCH_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CURCH */ + +/* Bit fields for LESENSE DECSTATE */ +#define _LESENSE_DECSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_MASK 0x0000001FUL /**< Mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_SHIFT 0 /**< Shift value for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_MASK 0x1FUL /**< Bit mask for LESENSE_DECSTATE */ +#define _LESENSE_DECSTATE_DECSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_DECSTATE */ +#define LESENSE_DECSTATE_DECSTATE_DEFAULT (_LESENSE_DECSTATE_DECSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_DECSTATE */ + +/* Bit fields for LESENSE SENSORSTATE */ +#define _LESENSE_SENSORSTATE_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_MASK 0x0000000FUL /**< Mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_SHIFT 0 /**< Shift value for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_MASK 0xFUL /**< Bit mask for LESENSE_SENSORSTATE */ +#define _LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SENSORSTATE */ +#define LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT (_LESENSE_SENSORSTATE_SENSORSTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SENSORSTATE*/ + +/* Bit fields for LESENSE IDLECONF */ +#define _LESENSE_IDLECONF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_MASK 0xFFFFFFFFUL /**< Mask for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_SHIFT 0 /**< Shift value for LESENSE_CHIDLE0 */ +#define _LESENSE_IDLECONF_CHIDLE0_MASK 0x3UL /**< Bit mask for LESENSE_CHIDLE0 */ +#define _LESENSE_IDLECONF_CHIDLE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE0_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DEFAULT (_LESENSE_IDLECONF_CHIDLE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DISABLE (_LESENSE_IDLECONF_CHIDLE0_DISABLE << 0) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_HIGH (_LESENSE_IDLECONF_CHIDLE0_HIGH << 0) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_LOW (_LESENSE_IDLECONF_CHIDLE0_LOW << 0) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE0_DAC (_LESENSE_IDLECONF_CHIDLE0_DAC << 0) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_SHIFT 2 /**< Shift value for LESENSE_CHIDLE1 */ +#define _LESENSE_IDLECONF_CHIDLE1_MASK 0xCUL /**< Bit mask for LESENSE_CHIDLE1 */ +#define _LESENSE_IDLECONF_CHIDLE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE1_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DEFAULT (_LESENSE_IDLECONF_CHIDLE1_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DISABLE (_LESENSE_IDLECONF_CHIDLE1_DISABLE << 2) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_HIGH (_LESENSE_IDLECONF_CHIDLE1_HIGH << 2) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_LOW (_LESENSE_IDLECONF_CHIDLE1_LOW << 2) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE1_DAC (_LESENSE_IDLECONF_CHIDLE1_DAC << 2) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_SHIFT 4 /**< Shift value for LESENSE_CHIDLE2 */ +#define _LESENSE_IDLECONF_CHIDLE2_MASK 0x30UL /**< Bit mask for LESENSE_CHIDLE2 */ +#define _LESENSE_IDLECONF_CHIDLE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE2_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DEFAULT (_LESENSE_IDLECONF_CHIDLE2_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DISABLE (_LESENSE_IDLECONF_CHIDLE2_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_HIGH (_LESENSE_IDLECONF_CHIDLE2_HIGH << 4) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_LOW (_LESENSE_IDLECONF_CHIDLE2_LOW << 4) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE2_DAC (_LESENSE_IDLECONF_CHIDLE2_DAC << 4) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_SHIFT 6 /**< Shift value for LESENSE_CHIDLE3 */ +#define _LESENSE_IDLECONF_CHIDLE3_MASK 0xC0UL /**< Bit mask for LESENSE_CHIDLE3 */ +#define _LESENSE_IDLECONF_CHIDLE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE3_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DEFAULT (_LESENSE_IDLECONF_CHIDLE3_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DISABLE (_LESENSE_IDLECONF_CHIDLE3_DISABLE << 6) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_HIGH (_LESENSE_IDLECONF_CHIDLE3_HIGH << 6) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_LOW (_LESENSE_IDLECONF_CHIDLE3_LOW << 6) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE3_DAC (_LESENSE_IDLECONF_CHIDLE3_DAC << 6) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_SHIFT 8 /**< Shift value for LESENSE_CHIDLE4 */ +#define _LESENSE_IDLECONF_CHIDLE4_MASK 0x300UL /**< Bit mask for LESENSE_CHIDLE4 */ +#define _LESENSE_IDLECONF_CHIDLE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE4_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DEFAULT (_LESENSE_IDLECONF_CHIDLE4_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DISABLE (_LESENSE_IDLECONF_CHIDLE4_DISABLE << 8) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_HIGH (_LESENSE_IDLECONF_CHIDLE4_HIGH << 8) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_LOW (_LESENSE_IDLECONF_CHIDLE4_LOW << 8) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE4_DAC (_LESENSE_IDLECONF_CHIDLE4_DAC << 8) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_SHIFT 10 /**< Shift value for LESENSE_CHIDLE5 */ +#define _LESENSE_IDLECONF_CHIDLE5_MASK 0xC00UL /**< Bit mask for LESENSE_CHIDLE5 */ +#define _LESENSE_IDLECONF_CHIDLE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE5_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DEFAULT (_LESENSE_IDLECONF_CHIDLE5_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DISABLE (_LESENSE_IDLECONF_CHIDLE5_DISABLE << 10) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_HIGH (_LESENSE_IDLECONF_CHIDLE5_HIGH << 10) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_LOW (_LESENSE_IDLECONF_CHIDLE5_LOW << 10) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE5_DAC (_LESENSE_IDLECONF_CHIDLE5_DAC << 10) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_SHIFT 12 /**< Shift value for LESENSE_CHIDLE6 */ +#define _LESENSE_IDLECONF_CHIDLE6_MASK 0x3000UL /**< Bit mask for LESENSE_CHIDLE6 */ +#define _LESENSE_IDLECONF_CHIDLE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE6_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DEFAULT (_LESENSE_IDLECONF_CHIDLE6_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DISABLE (_LESENSE_IDLECONF_CHIDLE6_DISABLE << 12) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_HIGH (_LESENSE_IDLECONF_CHIDLE6_HIGH << 12) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_LOW (_LESENSE_IDLECONF_CHIDLE6_LOW << 12) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE6_DAC (_LESENSE_IDLECONF_CHIDLE6_DAC << 12) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_SHIFT 14 /**< Shift value for LESENSE_CHIDLE7 */ +#define _LESENSE_IDLECONF_CHIDLE7_MASK 0xC000UL /**< Bit mask for LESENSE_CHIDLE7 */ +#define _LESENSE_IDLECONF_CHIDLE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE7_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DEFAULT (_LESENSE_IDLECONF_CHIDLE7_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DISABLE (_LESENSE_IDLECONF_CHIDLE7_DISABLE << 14) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_HIGH (_LESENSE_IDLECONF_CHIDLE7_HIGH << 14) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_LOW (_LESENSE_IDLECONF_CHIDLE7_LOW << 14) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE7_DAC (_LESENSE_IDLECONF_CHIDLE7_DAC << 14) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_SHIFT 16 /**< Shift value for LESENSE_CHIDLE8 */ +#define _LESENSE_IDLECONF_CHIDLE8_MASK 0x30000UL /**< Bit mask for LESENSE_CHIDLE8 */ +#define _LESENSE_IDLECONF_CHIDLE8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE8_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DEFAULT (_LESENSE_IDLECONF_CHIDLE8_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DISABLE (_LESENSE_IDLECONF_CHIDLE8_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_HIGH (_LESENSE_IDLECONF_CHIDLE8_HIGH << 16) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_LOW (_LESENSE_IDLECONF_CHIDLE8_LOW << 16) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE8_DAC (_LESENSE_IDLECONF_CHIDLE8_DAC << 16) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_SHIFT 18 /**< Shift value for LESENSE_CHIDLE9 */ +#define _LESENSE_IDLECONF_CHIDLE9_MASK 0xC0000UL /**< Bit mask for LESENSE_CHIDLE9 */ +#define _LESENSE_IDLECONF_CHIDLE9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE9_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DEFAULT (_LESENSE_IDLECONF_CHIDLE9_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DISABLE (_LESENSE_IDLECONF_CHIDLE9_DISABLE << 18) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_HIGH (_LESENSE_IDLECONF_CHIDLE9_HIGH << 18) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_LOW (_LESENSE_IDLECONF_CHIDLE9_LOW << 18) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE9_DAC (_LESENSE_IDLECONF_CHIDLE9_DAC << 18) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_SHIFT 20 /**< Shift value for LESENSE_CHIDLE10 */ +#define _LESENSE_IDLECONF_CHIDLE10_MASK 0x300000UL /**< Bit mask for LESENSE_CHIDLE10 */ +#define _LESENSE_IDLECONF_CHIDLE10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE10_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DEFAULT (_LESENSE_IDLECONF_CHIDLE10_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DISABLE (_LESENSE_IDLECONF_CHIDLE10_DISABLE << 20) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_HIGH (_LESENSE_IDLECONF_CHIDLE10_HIGH << 20) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_LOW (_LESENSE_IDLECONF_CHIDLE10_LOW << 20) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE10_DAC (_LESENSE_IDLECONF_CHIDLE10_DAC << 20) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_SHIFT 22 /**< Shift value for LESENSE_CHIDLE11 */ +#define _LESENSE_IDLECONF_CHIDLE11_MASK 0xC00000UL /**< Bit mask for LESENSE_CHIDLE11 */ +#define _LESENSE_IDLECONF_CHIDLE11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE11_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DEFAULT (_LESENSE_IDLECONF_CHIDLE11_DEFAULT << 22) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DISABLE (_LESENSE_IDLECONF_CHIDLE11_DISABLE << 22) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_HIGH (_LESENSE_IDLECONF_CHIDLE11_HIGH << 22) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_LOW (_LESENSE_IDLECONF_CHIDLE11_LOW << 22) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE11_DAC (_LESENSE_IDLECONF_CHIDLE11_DAC << 22) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_SHIFT 24 /**< Shift value for LESENSE_CHIDLE12 */ +#define _LESENSE_IDLECONF_CHIDLE12_MASK 0x3000000UL /**< Bit mask for LESENSE_CHIDLE12 */ +#define _LESENSE_IDLECONF_CHIDLE12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE12_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DEFAULT (_LESENSE_IDLECONF_CHIDLE12_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DISABLE (_LESENSE_IDLECONF_CHIDLE12_DISABLE << 24) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_HIGH (_LESENSE_IDLECONF_CHIDLE12_HIGH << 24) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_LOW (_LESENSE_IDLECONF_CHIDLE12_LOW << 24) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE12_DAC (_LESENSE_IDLECONF_CHIDLE12_DAC << 24) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_SHIFT 26 /**< Shift value for LESENSE_CHIDLE13 */ +#define _LESENSE_IDLECONF_CHIDLE13_MASK 0xC000000UL /**< Bit mask for LESENSE_CHIDLE13 */ +#define _LESENSE_IDLECONF_CHIDLE13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE13_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DEFAULT (_LESENSE_IDLECONF_CHIDLE13_DEFAULT << 26) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DISABLE (_LESENSE_IDLECONF_CHIDLE13_DISABLE << 26) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_HIGH (_LESENSE_IDLECONF_CHIDLE13_HIGH << 26) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_LOW (_LESENSE_IDLECONF_CHIDLE13_LOW << 26) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE13_DAC (_LESENSE_IDLECONF_CHIDLE13_DAC << 26) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_SHIFT 28 /**< Shift value for LESENSE_CHIDLE14 */ +#define _LESENSE_IDLECONF_CHIDLE14_MASK 0x30000000UL /**< Bit mask for LESENSE_CHIDLE14 */ +#define _LESENSE_IDLECONF_CHIDLE14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE14_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DEFAULT (_LESENSE_IDLECONF_CHIDLE14_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DISABLE (_LESENSE_IDLECONF_CHIDLE14_DISABLE << 28) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_HIGH (_LESENSE_IDLECONF_CHIDLE14_HIGH << 28) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_LOW (_LESENSE_IDLECONF_CHIDLE14_LOW << 28) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE14_DAC (_LESENSE_IDLECONF_CHIDLE14_DAC << 28) /**< Shifted mode DAC for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_SHIFT 30 /**< Shift value for LESENSE_CHIDLE15 */ +#define _LESENSE_IDLECONF_CHIDLE15_MASK 0xC0000000UL /**< Bit mask for LESENSE_CHIDLE15 */ +#define _LESENSE_IDLECONF_CHIDLE15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_LOW 0x00000002UL /**< Mode LOW for LESENSE_IDLECONF */ +#define _LESENSE_IDLECONF_CHIDLE15_DAC 0x00000003UL /**< Mode DAC for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DEFAULT (_LESENSE_IDLECONF_CHIDLE15_DEFAULT << 30) /**< Shifted mode DEFAULT for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DISABLE (_LESENSE_IDLECONF_CHIDLE15_DISABLE << 30) /**< Shifted mode DISABLE for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_HIGH (_LESENSE_IDLECONF_CHIDLE15_HIGH << 30) /**< Shifted mode HIGH for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_LOW (_LESENSE_IDLECONF_CHIDLE15_LOW << 30) /**< Shifted mode LOW for LESENSE_IDLECONF */ +#define LESENSE_IDLECONF_CHIDLE15_DAC (_LESENSE_IDLECONF_CHIDLE15_DAC << 30) /**< Shifted mode DAC for LESENSE_IDLECONF */ + +/* Bit fields for LESENSE SYNCBUSY */ +#define _LESENSE_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LESENSE_SYNCBUSY */ +#define _LESENSE_SYNCBUSY_MASK 0x00000001UL /**< Mask for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD (0x1UL << 0) /**< Command */ +#define _LESENSE_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for LESENSE_CMD */ +#define _LESENSE_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_SYNCBUSY */ +#define LESENSE_SYNCBUSY_CMD_DEFAULT (_LESENSE_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_SYNCBUSY */ + +/* Bit fields for LESENSE IF */ +#define _LESENSE_IF_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IF */ +#define _LESENSE_IF_MASK 0x003FFFFFUL /**< Mask for LESENSE_IF */ +#define LESENSE_IF_CH0 (0x1UL << 0) /**< Channel */ +#define _LESENSE_IF_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH0_DEFAULT (_LESENSE_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1 (0x1UL << 1) /**< Channel */ +#define _LESENSE_IF_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH1_DEFAULT (_LESENSE_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2 (0x1UL << 2) /**< Channel */ +#define _LESENSE_IF_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IF_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH2_DEFAULT (_LESENSE_IF_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3 (0x1UL << 3) /**< Channel */ +#define _LESENSE_IF_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IF_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH3_DEFAULT (_LESENSE_IF_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4 (0x1UL << 4) /**< Channel */ +#define _LESENSE_IF_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IF_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH4_DEFAULT (_LESENSE_IF_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5 (0x1UL << 5) /**< Channel */ +#define _LESENSE_IF_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IF_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH5_DEFAULT (_LESENSE_IF_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6 (0x1UL << 6) /**< Channel */ +#define _LESENSE_IF_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IF_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH6_DEFAULT (_LESENSE_IF_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7 (0x1UL << 7) /**< Channel */ +#define _LESENSE_IF_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IF_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH7_DEFAULT (_LESENSE_IF_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8 (0x1UL << 8) /**< Channel */ +#define _LESENSE_IF_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IF_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH8_DEFAULT (_LESENSE_IF_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9 (0x1UL << 9) /**< Channel */ +#define _LESENSE_IF_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IF_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH9_DEFAULT (_LESENSE_IF_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10 (0x1UL << 10) /**< Channel */ +#define _LESENSE_IF_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IF_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH10_DEFAULT (_LESENSE_IF_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11 (0x1UL << 11) /**< Channel */ +#define _LESENSE_IF_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IF_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH11_DEFAULT (_LESENSE_IF_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12 (0x1UL << 12) /**< Channel */ +#define _LESENSE_IF_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IF_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH12_DEFAULT (_LESENSE_IF_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13 (0x1UL << 13) /**< Channel */ +#define _LESENSE_IF_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IF_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH13_DEFAULT (_LESENSE_IF_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14 (0x1UL << 14) /**< Channel */ +#define _LESENSE_IF_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IF_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH14_DEFAULT (_LESENSE_IF_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15 (0x1UL << 15) /**< Channel */ +#define _LESENSE_IF_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IF_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CH15_DEFAULT (_LESENSE_IF_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANDONE (0x1UL << 16) /**< Scan Done */ +#define _LESENSE_IF_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ +#define _LESENSE_IF_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ +#define _LESENSE_IF_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_SCANDONE_DEFAULT (_LESENSE_IF_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC (0x1UL << 17) /**< Decoder */ +#define _LESENSE_IF_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IF_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IF_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_DEC_DEFAULT (_LESENSE_IF_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESWL (0x1UL << 18) /**< Result Watermark Level */ +#define _LESENSE_IF_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ +#define _LESENSE_IF_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ +#define _LESENSE_IF_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESWL_DEFAULT (_LESENSE_IF_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESOF (0x1UL << 19) /**< Result Overflow */ +#define _LESENSE_IF_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ +#define _LESENSE_IF_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ +#define _LESENSE_IF_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESOF_DEFAULT (_LESENSE_IF_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF (0x1UL << 20) /**< Counter Overflow */ +#define _LESENSE_IF_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IF_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_CNTOF_DEFAULT (_LESENSE_IF_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESUF (0x1UL << 21) /**< Result Underflow */ +#define _LESENSE_IF_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ +#define _LESENSE_IF_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ +#define _LESENSE_IF_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IF */ +#define LESENSE_IF_RESUF_DEFAULT (_LESENSE_IF_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IF */ + +/* Bit fields for LESENSE IEN */ +#define _LESENSE_IEN_RESETVALUE 0x00000000UL /**< Default value for LESENSE_IEN */ +#define _LESENSE_IEN_MASK 0x003FFFFFUL /**< Mask for LESENSE_IEN */ +#define LESENSE_IEN_CH0 (0x1UL << 0) /**< Channel */ +#define _LESENSE_IEN_CH0_SHIFT 0 /**< Shift value for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_MASK 0x1UL /**< Bit mask for LESENSE_CH0 */ +#define _LESENSE_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH0_DEFAULT (_LESENSE_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1 (0x1UL << 1) /**< Channel */ +#define _LESENSE_IEN_CH1_SHIFT 1 /**< Shift value for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_MASK 0x2UL /**< Bit mask for LESENSE_CH1 */ +#define _LESENSE_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH1_DEFAULT (_LESENSE_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2 (0x1UL << 2) /**< Channel */ +#define _LESENSE_IEN_CH2_SHIFT 2 /**< Shift value for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_MASK 0x4UL /**< Bit mask for LESENSE_CH2 */ +#define _LESENSE_IEN_CH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH2_DEFAULT (_LESENSE_IEN_CH2_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3 (0x1UL << 3) /**< Channel */ +#define _LESENSE_IEN_CH3_SHIFT 3 /**< Shift value for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_MASK 0x8UL /**< Bit mask for LESENSE_CH3 */ +#define _LESENSE_IEN_CH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH3_DEFAULT (_LESENSE_IEN_CH3_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4 (0x1UL << 4) /**< Channel */ +#define _LESENSE_IEN_CH4_SHIFT 4 /**< Shift value for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_MASK 0x10UL /**< Bit mask for LESENSE_CH4 */ +#define _LESENSE_IEN_CH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH4_DEFAULT (_LESENSE_IEN_CH4_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5 (0x1UL << 5) /**< Channel */ +#define _LESENSE_IEN_CH5_SHIFT 5 /**< Shift value for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_MASK 0x20UL /**< Bit mask for LESENSE_CH5 */ +#define _LESENSE_IEN_CH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH5_DEFAULT (_LESENSE_IEN_CH5_DEFAULT << 5) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6 (0x1UL << 6) /**< Channel */ +#define _LESENSE_IEN_CH6_SHIFT 6 /**< Shift value for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_MASK 0x40UL /**< Bit mask for LESENSE_CH6 */ +#define _LESENSE_IEN_CH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH6_DEFAULT (_LESENSE_IEN_CH6_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7 (0x1UL << 7) /**< Channel */ +#define _LESENSE_IEN_CH7_SHIFT 7 /**< Shift value for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_MASK 0x80UL /**< Bit mask for LESENSE_CH7 */ +#define _LESENSE_IEN_CH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH7_DEFAULT (_LESENSE_IEN_CH7_DEFAULT << 7) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8 (0x1UL << 8) /**< Channel */ +#define _LESENSE_IEN_CH8_SHIFT 8 /**< Shift value for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_MASK 0x100UL /**< Bit mask for LESENSE_CH8 */ +#define _LESENSE_IEN_CH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH8_DEFAULT (_LESENSE_IEN_CH8_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9 (0x1UL << 9) /**< Channel */ +#define _LESENSE_IEN_CH9_SHIFT 9 /**< Shift value for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_MASK 0x200UL /**< Bit mask for LESENSE_CH9 */ +#define _LESENSE_IEN_CH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH9_DEFAULT (_LESENSE_IEN_CH9_DEFAULT << 9) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10 (0x1UL << 10) /**< Channel */ +#define _LESENSE_IEN_CH10_SHIFT 10 /**< Shift value for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_MASK 0x400UL /**< Bit mask for LESENSE_CH10 */ +#define _LESENSE_IEN_CH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH10_DEFAULT (_LESENSE_IEN_CH10_DEFAULT << 10) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11 (0x1UL << 11) /**< Channel */ +#define _LESENSE_IEN_CH11_SHIFT 11 /**< Shift value for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_MASK 0x800UL /**< Bit mask for LESENSE_CH11 */ +#define _LESENSE_IEN_CH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH11_DEFAULT (_LESENSE_IEN_CH11_DEFAULT << 11) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12 (0x1UL << 12) /**< Channel */ +#define _LESENSE_IEN_CH12_SHIFT 12 /**< Shift value for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_MASK 0x1000UL /**< Bit mask for LESENSE_CH12 */ +#define _LESENSE_IEN_CH12_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH12_DEFAULT (_LESENSE_IEN_CH12_DEFAULT << 12) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13 (0x1UL << 13) /**< Channel */ +#define _LESENSE_IEN_CH13_SHIFT 13 /**< Shift value for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_MASK 0x2000UL /**< Bit mask for LESENSE_CH13 */ +#define _LESENSE_IEN_CH13_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH13_DEFAULT (_LESENSE_IEN_CH13_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14 (0x1UL << 14) /**< Channel */ +#define _LESENSE_IEN_CH14_SHIFT 14 /**< Shift value for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_MASK 0x4000UL /**< Bit mask for LESENSE_CH14 */ +#define _LESENSE_IEN_CH14_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH14_DEFAULT (_LESENSE_IEN_CH14_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15 (0x1UL << 15) /**< Channel */ +#define _LESENSE_IEN_CH15_SHIFT 15 /**< Shift value for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_MASK 0x8000UL /**< Bit mask for LESENSE_CH15 */ +#define _LESENSE_IEN_CH15_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CH15_DEFAULT (_LESENSE_IEN_CH15_DEFAULT << 15) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANDONE (0x1UL << 16) /**< Scan Complete */ +#define _LESENSE_IEN_SCANDONE_SHIFT 16 /**< Shift value for LESENSE_SCANDONE */ +#define _LESENSE_IEN_SCANDONE_MASK 0x10000UL /**< Bit mask for LESENSE_SCANDONE */ +#define _LESENSE_IEN_SCANDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_SCANDONE_DEFAULT (_LESENSE_IEN_SCANDONE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC (0x1UL << 17) /**< Decoder */ +#define _LESENSE_IEN_DEC_SHIFT 17 /**< Shift value for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_MASK 0x20000UL /**< Bit mask for LESENSE_DEC */ +#define _LESENSE_IEN_DEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_DEC_DEFAULT (_LESENSE_IEN_DEC_DEFAULT << 17) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESWL (0x1UL << 18) /**< Result Watermark Level */ +#define _LESENSE_IEN_RESWL_SHIFT 18 /**< Shift value for LESENSE_RESWL */ +#define _LESENSE_IEN_RESWL_MASK 0x40000UL /**< Bit mask for LESENSE_RESWL */ +#define _LESENSE_IEN_RESWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESWL_DEFAULT (_LESENSE_IEN_RESWL_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESOF (0x1UL << 19) /**< Result Overflow */ +#define _LESENSE_IEN_RESOF_SHIFT 19 /**< Shift value for LESENSE_RESOF */ +#define _LESENSE_IEN_RESOF_MASK 0x80000UL /**< Bit mask for LESENSE_RESOF */ +#define _LESENSE_IEN_RESOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESOF_DEFAULT (_LESENSE_IEN_RESOF_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF (0x1UL << 20) /**< Counter Overflow */ +#define _LESENSE_IEN_CNTOF_SHIFT 20 /**< Shift value for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_MASK 0x100000UL /**< Bit mask for LESENSE_CNTOF */ +#define _LESENSE_IEN_CNTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_CNTOF_DEFAULT (_LESENSE_IEN_CNTOF_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESUF (0x1UL << 21) /**< Result Underflow */ +#define _LESENSE_IEN_RESUF_SHIFT 21 /**< Shift value for LESENSE_RESUF */ +#define _LESENSE_IEN_RESUF_MASK 0x200000UL /**< Bit mask for LESENSE_RESUF */ +#define _LESENSE_IEN_RESUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_IEN */ +#define LESENSE_IEN_RESUF_DEFAULT (_LESENSE_IEN_RESUF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_IEN */ + +/* Bit fields for LESENSE CH_TIMING */ +#define _LESENSE_CH_TIMING_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MASK 0x00FFFFFFUL /**< Mask for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_EXTIME_SHIFT 0 /**< Shift value for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_MASK 0x3FUL /**< Bit mask for LESENSE_EXTIME */ +#define _LESENSE_CH_TIMING_EXTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_EXTIME_DEFAULT (_LESENSE_CH_TIMING_EXTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_SHIFT 6 /**< Shift value for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_MASK 0x3FC0UL /**< Bit mask for LESENSE_SAMPLEDLY */ +#define _LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT (_LESENSE_CH_TIMING_SAMPLEDLY_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ +#define _LESENSE_CH_TIMING_MEASUREDLY_SHIFT 14 /**< Shift value for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_MASK 0xFFC000UL /**< Bit mask for LESENSE_MEASUREDLY */ +#define _LESENSE_CH_TIMING_MEASUREDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_TIMING */ +#define LESENSE_CH_TIMING_MEASUREDLY_DEFAULT (_LESENSE_CH_TIMING_MEASUREDLY_DEFAULT << 14) /**< Shifted mode DEFAULT for LESENSE_CH_TIMING */ + +/* Bit fields for LESENSE CH_INTERACT */ +#define _LESENSE_CH_INTERACT_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_MASK 0x3FFF0FFFUL /**< Mask for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_THRES_SHIFT 0 /**< Shift value for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_MASK 0xFFFUL /**< Bit mask for LESENSE_THRES */ +#define _LESENSE_CH_INTERACT_THRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_THRES_DEFAULT (_LESENSE_CH_INTERACT_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_EXMODE_SHIFT 16 /**< Shift value for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_MASK 0x30000UL /**< Bit mask for LESENSE_EXMODE */ +#define _LESENSE_CH_INTERACT_EXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_HIGH 0x00000001UL /**< Mode HIGH for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_LOW 0x00000002UL /**< Mode LOW for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXMODE_DACOUT 0x00000003UL /**< Mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DEFAULT (_LESENSE_CH_INTERACT_EXMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXMODE_DISABLE (_LESENSE_CH_INTERACT_EXMODE_DISABLE << 16) /**< Shifted mode DISABLE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXMODE_HIGH (_LESENSE_CH_INTERACT_EXMODE_HIGH << 16) /**< Shifted mode HIGH for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_LOW (_LESENSE_CH_INTERACT_EXMODE_LOW << 16) /**< Shifted mode LOW for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXMODE_DACOUT (_LESENSE_CH_INTERACT_EXMODE_DACOUT << 16) /**< Shifted mode DACOUT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX (0x1UL << 18) /**< Use alternative excite pin */ +#define _LESENSE_CH_INTERACT_ALTEX_SHIFT 18 /**< Shift value for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_MASK 0x40000UL /**< Bit mask for LESENSE_ALTEX */ +#define _LESENSE_CH_INTERACT_ALTEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_ALTEX_DEFAULT (_LESENSE_CH_INTERACT_ALTEX_DEFAULT << 18) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLECLK (0x1UL << 19) /**< Select clock used for timing of sample d */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT 19 /**< Shift value for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_MASK 0x80000UL /**< Bit mask for LESENSE_SAMPLECLK */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT (_LESENSE_CH_INTERACT_SAMPLECLK_DEFAULT << 19) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLECLK_LFACLK (_LESENSE_CH_INTERACT_SAMPLECLK_LFACLK << 19) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO (_LESENSE_CH_INTERACT_SAMPLECLK_AUXHFRCO << 19) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXCLK (0x1UL << 20) /**< Select clock used for excitation timing */ +#define _LESENSE_CH_INTERACT_EXCLK_SHIFT 20 /**< Shift value for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_MASK 0x100000UL /**< Bit mask for LESENSE_EXCLK */ +#define _LESENSE_CH_INTERACT_EXCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_LFACLK 0x00000000UL /**< Mode LFACLK for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_EXCLK_AUXHFRCO 0x00000001UL /**< Mode AUXHFRCO for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_DEFAULT (_LESENSE_CH_INTERACT_EXCLK_DEFAULT << 20) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_EXCLK_LFACLK (_LESENSE_CH_INTERACT_EXCLK_LFACLK << 20) /**< Shifted mode LFACLK for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_EXCLK_AUXHFRCO (_LESENSE_CH_INTERACT_EXCLK_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_MASK 0xE00000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_CH_INTERACT_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NONE 0x00000000UL /**< Mode NONE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_LEVEL 0x00000001UL /**< Mode LEVEL for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_POSEDGE 0x00000002UL /**< Mode POSEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_NEGEDGE 0x00000003UL /**< Mode NEGEDGE for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SETIF_BOTHEDGES 0x00000004UL /**< Mode BOTHEDGES for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_DEFAULT (_LESENSE_CH_INTERACT_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_NONE (_LESENSE_CH_INTERACT_SETIF_NONE << 21) /**< Shifted mode NONE for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_LEVEL (_LESENSE_CH_INTERACT_SETIF_LEVEL << 21) /**< Shifted mode LEVEL for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SETIF_POSEDGE (_LESENSE_CH_INTERACT_SETIF_POSEDGE << 21) /**< Shifted mode POSEDGE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_NEGEDGE (_LESENSE_CH_INTERACT_SETIF_NEGEDGE << 21) /**< Shifted mode NEGEDGE for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SETIF_BOTHEDGES (_LESENSE_CH_INTERACT_SETIF_BOTHEDGES << 21) /**< Shifted mode BOTHEDGES for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_OFFSET_SHIFT 24 /**< Shift value for LESENSE_OFFSET */ +#define _LESENSE_CH_INTERACT_OFFSET_MASK 0xF000000UL /**< Bit mask for LESENSE_OFFSET */ +#define _LESENSE_CH_INTERACT_OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_OFFSET_DEFAULT (_LESENSE_CH_INTERACT_OFFSET_DEFAULT << 24) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define _LESENSE_CH_INTERACT_SAMPLE_SHIFT 28 /**< Shift value for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_MASK 0x30000000UL /**< Bit mask for LESENSE_SAMPLE */ +#define _LESENSE_CH_INTERACT_SAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT 0x00000000UL /**< Mode ACMPCOUNT for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ACMP 0x00000001UL /**< Mode ACMP for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADC 0x00000002UL /**< Mode ADC for LESENSE_CH_INTERACT */ +#define _LESENSE_CH_INTERACT_SAMPLE_ADCDIFF 0x00000003UL /**< Mode ADCDIFF for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_DEFAULT (_LESENSE_CH_INTERACT_SAMPLE_DEFAULT << 28) /**< Shifted mode DEFAULT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT (_LESENSE_CH_INTERACT_SAMPLE_ACMPCOUNT << 28) /**< Shifted mode ACMPCOUNT for LESENSE_CH_INTERACT*/ +#define LESENSE_CH_INTERACT_SAMPLE_ACMP (_LESENSE_CH_INTERACT_SAMPLE_ACMP << 28) /**< Shifted mode ACMP for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADC (_LESENSE_CH_INTERACT_SAMPLE_ADC << 28) /**< Shifted mode ADC for LESENSE_CH_INTERACT */ +#define LESENSE_CH_INTERACT_SAMPLE_ADCDIFF (_LESENSE_CH_INTERACT_SAMPLE_ADCDIFF << 28) /**< Shifted mode ADCDIFF for LESENSE_CH_INTERACT*/ + +/* Bit fields for LESENSE CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MASK 0x0000037CUL /**< Mask for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_DECODE (0x1UL << 2) /**< Send result to decoder */ +#define _LESENSE_CH_EVALCFG_DECODE_SHIFT 2 /**< Shift value for LESENSE_DECODE */ +#define _LESENSE_CH_EVALCFG_DECODE_MASK 0x4UL /**< Bit mask for LESENSE_DECODE */ +#define _LESENSE_CH_EVALCFG_DECODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_DECODE_DEFAULT (_LESENSE_CH_EVALCFG_DECODE_DEFAULT << 2) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP (0x1UL << 3) /**< Select mode for threshold comparison */ +#define _LESENSE_CH_EVALCFG_COMP_SHIFT 3 /**< Shift value for LESENSE_COMP */ +#define _LESENSE_CH_EVALCFG_COMP_MASK 0x8UL /**< Bit mask for LESENSE_COMP */ +#define _LESENSE_CH_EVALCFG_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_COMP_LESS 0x00000000UL /**< Mode LESS for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_COMP_GE 0x00000001UL /**< Mode GE for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_DEFAULT (_LESENSE_CH_EVALCFG_COMP_DEFAULT << 3) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_LESS (_LESENSE_CH_EVALCFG_COMP_LESS << 3) /**< Shifted mode LESS for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_COMP_GE (_LESENSE_CH_EVALCFG_COMP_GE << 3) /**< Shifted mode GE for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_SHIFT 4 /**< Shift value for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_MASK 0x30UL /**< Bit mask for LESENSE_STRSAMPLE */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE 0x00000000UL /**< Mode DISABLE for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATA 0x00000001UL /**< Mode DATA for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC 0x00000002UL /**< Mode DATASRC for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT (_LESENSE_CH_EVALCFG_STRSAMPLE_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE (_LESENSE_CH_EVALCFG_STRSAMPLE_DISABLE << 4) /**< Shifted mode DISABLE for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DATA (_LESENSE_CH_EVALCFG_STRSAMPLE_DATA << 4) /**< Shifted mode DATA for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC (_LESENSE_CH_EVALCFG_STRSAMPLE_DATASRC << 4) /**< Shifted mode DATASRC for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_SCANRESINV (0x1UL << 6) /**< Enable inversion of result */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_SHIFT 6 /**< Shift value for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_MASK 0x40UL /**< Bit mask for LESENSE_SCANRESINV */ +#define _LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT (_LESENSE_CH_EVALCFG_SCANRESINV_DEFAULT << 6) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_SHIFT 8 /**< Shift value for LESENSE_MODE */ +#define _LESENSE_CH_EVALCFG_MODE_MASK 0x300UL /**< Bit mask for LESENSE_MODE */ +#define _LESENSE_CH_EVALCFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_THRES 0x00000000UL /**< Mode THRES for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_SLIDINGWIN 0x00000001UL /**< Mode SLIDINGWIN for LESENSE_CH_EVALCFG */ +#define _LESENSE_CH_EVALCFG_MODE_STEPDET 0x00000002UL /**< Mode STEPDET for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_DEFAULT (_LESENSE_CH_EVALCFG_MODE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_THRES (_LESENSE_CH_EVALCFG_MODE_THRES << 8) /**< Shifted mode THRES for LESENSE_CH_EVALCFG */ +#define LESENSE_CH_EVALCFG_MODE_SLIDINGWIN (_LESENSE_CH_EVALCFG_MODE_SLIDINGWIN << 8) /**< Shifted mode SLIDINGWIN for LESENSE_CH_EVALCFG*/ +#define LESENSE_CH_EVALCFG_MODE_STEPDET (_LESENSE_CH_EVALCFG_MODE_STEPDET << 8) /**< Shifted mode STEPDET for LESENSE_CH_EVALCFG */ + +/* Bit fields for LESENSE CH_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_RESETVALUE 0x00000000UL /**< Default value for LESENSE_CH_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_MASK 0x0000FFFFUL /**< Mask for LESENSE_CH_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_SHIFT 0 /**< Shift value for LESENSE_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_MASK 0xFFFFUL /**< Bit mask for LESENSE_EVALTHRES */ +#define _LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_CH_EVALTHRES */ +#define LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT (_LESENSE_CH_EVALTHRES_EVALTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_CH_EVALTHRES*/ + +/* Bit fields for LESENSE ST_ARC */ +#define _LESENSE_ST_ARC_RESETVALUE 0x00000000UL /**< Default value for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_MASK 0x003FFFFFUL /**< Mask for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_SCOMP_SHIFT 0 /**< Shift value for LESENSE_SCOMP */ +#define _LESENSE_ST_ARC_SCOMP_MASK 0xFUL /**< Bit mask for LESENSE_SCOMP */ +#define _LESENSE_ST_ARC_SCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SCOMP_DEFAULT (_LESENSE_ST_ARC_SCOMP_DEFAULT << 0) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_SMASK_SHIFT 4 /**< Shift value for LESENSE_SMASK */ +#define _LESENSE_ST_ARC_SMASK_MASK 0xF0UL /**< Bit mask for LESENSE_SMASK */ +#define _LESENSE_ST_ARC_SMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SMASK_DEFAULT (_LESENSE_ST_ARC_SMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_CURSTATE_SHIFT 8 /**< Shift value for LESENSE_CURSTATE */ +#define _LESENSE_ST_ARC_CURSTATE_MASK 0x1F00UL /**< Bit mask for LESENSE_CURSTATE */ +#define _LESENSE_ST_ARC_CURSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_CURSTATE_DEFAULT (_LESENSE_ST_ARC_CURSTATE_DEFAULT << 8) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_SHIFT 13 /**< Shift value for LESENSE_PRSACT */ +#define _LESENSE_ST_ARC_PRSACT_MASK 0xE000UL /**< Bit mask for LESENSE_PRSACT */ +#define _LESENSE_ST_ARC_PRSACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_NONE 0x00000000UL /**< Mode NONE for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS0 0x00000001UL /**< Mode PRS0 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_UP 0x00000001UL /**< Mode UP for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS1 0x00000002UL /**< Mode PRS1 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_DOWN 0x00000002UL /**< Mode DOWN for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS01 0x00000003UL /**< Mode PRS01 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS2 0x00000004UL /**< Mode PRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS02 0x00000005UL /**< Mode PRS02 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_UPANDPRS2 0x00000005UL /**< Mode UPANDPRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS12 0x00000006UL /**< Mode PRS12 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 0x00000006UL /**< Mode DOWNANDPRS2 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_PRSACT_PRS012 0x00000007UL /**< Mode PRS012 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DEFAULT (_LESENSE_ST_ARC_PRSACT_DEFAULT << 13) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_NONE (_LESENSE_ST_ARC_PRSACT_NONE << 13) /**< Shifted mode NONE for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS0 (_LESENSE_ST_ARC_PRSACT_PRS0 << 13) /**< Shifted mode PRS0 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_UP (_LESENSE_ST_ARC_PRSACT_UP << 13) /**< Shifted mode UP for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS1 (_LESENSE_ST_ARC_PRSACT_PRS1 << 13) /**< Shifted mode PRS1 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DOWN (_LESENSE_ST_ARC_PRSACT_DOWN << 13) /**< Shifted mode DOWN for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS01 (_LESENSE_ST_ARC_PRSACT_PRS01 << 13) /**< Shifted mode PRS01 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS2 (_LESENSE_ST_ARC_PRSACT_PRS2 << 13) /**< Shifted mode PRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS02 (_LESENSE_ST_ARC_PRSACT_PRS02 << 13) /**< Shifted mode PRS02 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_UPANDPRS2 (_LESENSE_ST_ARC_PRSACT_UPANDPRS2 << 13) /**< Shifted mode UPANDPRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS12 (_LESENSE_ST_ARC_PRSACT_PRS12 << 13) /**< Shifted mode PRS12 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 (_LESENSE_ST_ARC_PRSACT_DOWNANDPRS2 << 13) /**< Shifted mode DOWNANDPRS2 for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_PRSACT_PRS012 (_LESENSE_ST_ARC_PRSACT_PRS012 << 13) /**< Shifted mode PRS012 for LESENSE_ST_ARC */ +#define _LESENSE_ST_ARC_NEXTSTATE_SHIFT 16 /**< Shift value for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_ARC_NEXTSTATE_MASK 0x1F0000UL /**< Bit mask for LESENSE_NEXTSTATE */ +#define _LESENSE_ST_ARC_NEXTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_NEXTSTATE_DEFAULT (_LESENSE_ST_ARC_NEXTSTATE_DEFAULT << 16) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SETIF (0x1UL << 21) /**< Set interrupt flag */ +#define _LESENSE_ST_ARC_SETIF_SHIFT 21 /**< Shift value for LESENSE_SETIF */ +#define _LESENSE_ST_ARC_SETIF_MASK 0x200000UL /**< Bit mask for LESENSE_SETIF */ +#define _LESENSE_ST_ARC_SETIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LESENSE_ST_ARC */ +#define LESENSE_ST_ARC_SETIF_DEFAULT (_LESENSE_ST_ARC_SETIF_DEFAULT << 21) /**< Shifted mode DEFAULT for LESENSE_ST_ARC */ + +/** @} End of group EFR32ZG23_LESENSE_BitFields */ +/** @} End of group EFR32ZG23_LESENSE */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LESENSE_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h new file mode 100644 index 000000000..c7b71b050 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_letimer.h @@ -0,0 +1,534 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LETIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LETIMER_H +#define EFR32ZG23_LETIMER_H +#define LETIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LETIMER LETIMER + * @{ + * @brief EFR32ZG23 LETIMER Register Declaration. + *****************************************************************************/ + +/** LETIMER Register Declaration. */ +typedef struct letimer_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED5[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +} LETIMER_TypeDef; +/** @} End of group EFR32ZG23_LETIMER */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LETIMER + * @{ + * @defgroup EFR32ZG23_LETIMER_BitFields LETIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ + +/* Bit fields for LETIMER EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ + +/* Bit fields for LETIMER SWRST */ +#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ +#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ + +/* Bit fields for LETIMER TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER LOCK */ +#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ +#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ + +/** @} End of group EFR32ZG23_LETIMER_BitFields */ +/** @} End of group EFR32ZG23_LETIMER */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LETIMER_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h new file mode 100644 index 000000000..62593ea36 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfrco.h @@ -0,0 +1,197 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LFRCO_H +#define EFR32ZG23_LFRCO_H +#define LFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LFRCO LFRCO + * @{ + * @brief EFR32ZG23 LFRCO Register Declaration. + *****************************************************************************/ + +/** LFRCO Register Declaration. */ +typedef struct lfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED5[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED8[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFRCO_TypeDef; +/** @} End of group EFR32ZG23_LFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LFRCO + * @{ + * @defgroup EFR32ZG23_LFRCO_BitFields LFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFRCO IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ + +/* Bit fields for LFRCO STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ + +/* Bit fields for LFRCO CAL */ +#define _LFRCO_CAL_RESETVALUE 0x000000A5UL /**< Default value for LFRCO_CAL */ +#define _LFRCO_CAL_MASK 0x000000FFUL /**< Mask for LFRCO_CAL */ +#define _LFRCO_CAL_FREQTRIM_SHIFT 0 /**< Shift value for LFRCO_FREQTRIM */ +#define _LFRCO_CAL_FREQTRIM_MASK 0xFFUL /**< Bit mask for LFRCO_FREQTRIM */ +#define _LFRCO_CAL_FREQTRIM_DEFAULT 0x000000A5UL /**< Mode DEFAULT for LFRCO_CAL */ +#define LFRCO_CAL_FREQTRIM_DEFAULT (_LFRCO_CAL_FREQTRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CAL */ + +/* Bit fields for LFRCO IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00000007UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ + +/* Bit fields for LFRCO IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00000007UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ + +/* Bit fields for LFRCO SYNCBUSY */ +#define _LFRCO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFRCO_SYNCBUSY */ +#define _LFRCO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFRCO_SYNCBUSY */ +#define LFRCO_SYNCBUSY_CAL (0x1UL << 0) /**< CAL Busy */ +#define _LFRCO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFRCO_CAL */ +#define _LFRCO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFRCO_CAL */ +#define _LFRCO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_SYNCBUSY */ +#define LFRCO_SYNCBUSY_CAL_DEFAULT (_LFRCO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_SYNCBUSY */ + +/* Bit fields for LFRCO LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00002603UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00002603UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00002603UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ + +/** @} End of group EFR32ZG23_LFRCO_BitFields */ +/** @} End of group EFR32ZG23_LFRCO */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h new file mode 100644 index 000000000..4b4dc2f7b --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_lfxo.h @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 LFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_LFXO_H +#define EFR32ZG23_LFXO_H +#define LFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_LFXO LFXO + * @{ + * @brief EFR32ZG23 LFXO Register Declaration. + *****************************************************************************/ + +/** LFXO Register Declaration. */ +typedef struct lfxo_typedef{ + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFXO_TypeDef; +/** @} End of group EFR32ZG23_LFXO */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_LFXO + * @{ + * @defgroup EFR32ZG23_LFXO_BitFields LFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFXO IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ + +/* Bit fields for LFXO CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ + +/* Bit fields for LFXO CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ + +/* Bit fields for LFXO STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ + +/* Bit fields for LFXO CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000200UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ + +/* Bit fields for LFXO IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ + +/* Bit fields for LFXO IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ + +/* Bit fields for LFXO SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ + +/* Bit fields for LFXO LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ + +/** @} End of group EFR32ZG23_LFXO_BitFields */ +/** @} End of group EFR32ZG23_LFXO */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_LFXO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h new file mode 100644 index 000000000..15839a223 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mailbox.h @@ -0,0 +1,140 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 MAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_MAILBOX_H +#define EFR32ZG23_MAILBOX_H +#define MAILBOX_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_MAILBOX MAILBOX + * @{ + * @brief EFR32ZG23 MAILBOX Register Declaration. + *****************************************************************************/ + +/** MAILBOX MSGPTRS Register Group Declaration. */ +typedef struct mailbox_msgptrs_typedef{ + __IOM uint32_t MSGPTR; /**< Message Pointer */ +} MAILBOX_MSGPTRS_TypeDef; + +/** MAILBOX Register Declaration. */ +typedef struct mailbox_typedef{ + MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ + uint32_t RESERVED0[12U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + uint32_t RESERVED1[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ + uint32_t RESERVED2[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ + uint32_t RESERVED4[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ + uint32_t RESERVED6[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ +} MAILBOX_TypeDef; +/** @} End of group EFR32ZG23_MAILBOX */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_MAILBOX + * @{ + * @defgroup EFR32ZG23_MAILBOX_BitFields MAILBOX Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MAILBOX MSGPTR */ +#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ +#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ + +/* Bit fields for MAILBOX IF */ +#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ +#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ + +/* Bit fields for MAILBOX IEN */ +#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ +#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ + +/** @} End of group EFR32ZG23_MAILBOX_BitFields */ +/** @} End of group EFR32ZG23_MAILBOX */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_MAILBOX_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h new file mode 100644 index 000000000..234d49ac9 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_mpahbram.h @@ -0,0 +1,242 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 MPAHBRAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_MPAHBRAM_H +#define EFR32ZG23_MPAHBRAM_H +#define MPAHBRAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_MPAHBRAM MPAHBRAM + * @{ + * @brief EFR32ZG23 MPAHBRAM Register Declaration. + *****************************************************************************/ + +/** MPAHBRAM Register Declaration. */ +typedef struct mpahbram_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t CTRL; /**< Control register */ + __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t CTRL_SET; /**< Control register */ + __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t CTRL_CLR; /**< Control register */ + __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t CTRL_TGL; /**< Control register */ + __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} MPAHBRAM_TypeDef; +/** @} End of group EFR32ZG23_MPAHBRAM */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_MPAHBRAM + * @{ + * @defgroup EFR32ZG23_MPAHBRAM_BitFields MPAHBRAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MPAHBRAM IPVERSION */ +#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_MASK 0x00000001UL /**< Mask for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION (0x1UL << 0) /**< New BitField */ +#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x1UL /**< Bit mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ + +/* Bit fields for MPAHBRAM CMD */ +#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_MASK 0x00000003UL /**< Mask for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ + +/* Bit fields for MPAHBRAM CTRL */ +#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_MASK 0x0000007FUL /**< Mask for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ +#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ +#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ + +/* Bit fields for MPAHBRAM ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ +#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ + +/* Bit fields for MPAHBRAM ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ +#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ + +/* Bit fields for MPAHBRAM ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_MASK 0x00000003UL /**< Mask for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ +#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ +#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ + +/* Bit fields for MPAHBRAM IF */ +#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_MASK 0x00000033UL /**< Mask for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ + +/* Bit fields for MPAHBRAM IEN */ +#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_MASK 0x00000033UL /**< Mask for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ + +/** @} End of group EFR32ZG23_MPAHBRAM_BitFields */ +/** @} End of group EFR32ZG23_MPAHBRAM */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_MPAHBRAM_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h new file mode 100644 index 000000000..1ca11ffaa --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_msc.h @@ -0,0 +1,502 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 MSC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_MSC_H +#define EFR32ZG23_MSC_H +#define MSC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_MSC MSC + * @{ + * @brief EFR32ZG23 MSC Register Declaration. + *****************************************************************************/ + +/** MSC Register Declaration. */ +typedef struct msc_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED2[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + uint32_t RESERVED4[4U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[4U]; /**< Reserved for future use */ + uint32_t RESERVED8[12U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED15[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + uint32_t RESERVED17[4U]; /**< Reserved for future use */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + uint32_t RESERVED19[4U]; /**< Reserved for future use */ + uint32_t RESERVED20[4U]; /**< Reserved for future use */ + uint32_t RESERVED21[12U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED28[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + uint32_t RESERVED31[4U]; /**< Reserved for future use */ + uint32_t RESERVED32[4U]; /**< Reserved for future use */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[12U]; /**< Reserved for future use */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + uint32_t RESERVED36[8U]; /**< Reserved for future use */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + uint32_t RESERVED38[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED39[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED40[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED41[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + uint32_t RESERVED43[4U]; /**< Reserved for future use */ + uint32_t RESERVED44[4U]; /**< Reserved for future use */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + uint32_t RESERVED46[4U]; /**< Reserved for future use */ + uint32_t RESERVED47[12U]; /**< Reserved for future use */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + uint32_t RESERVED49[8U]; /**< Reserved for future use */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ +} MSC_TypeDef; +/** @} End of group EFR32ZG23_MSC */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_MSC + * @{ + * @defgroup EFR32ZG23_MSC_BitFields MSC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ + +/* Bit fields for MSC RDATACTRL */ +#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ +#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x00FF000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_MASK 0xFF0000UL /**< Bit mask for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ +#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ +#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash power on status */ +#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ +#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ +#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ + +/* Bit fields for MSC PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ + +/* Bit fields for MSC PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ + +/* Bit fields for MSC PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ + +/** @} End of group EFR32ZG23_MSC_BitFields */ +/** @} End of group EFR32ZG23_MSC */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_MSC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h new file mode 100644 index 000000000..bd42bed17 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pcnt.h @@ -0,0 +1,482 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 PCNT register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_PCNT_H +#define EFR32ZG23_PCNT_H +#define PCNT_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_PCNT PCNT + * @{ + * @brief EFR32ZG23 PCNT Register Declaration. + *****************************************************************************/ + +/** PCNT Register Declaration. */ +typedef struct pcnt_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_SET; /**< Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED1[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_CLR; /**< Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED2[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_TGL; /**< Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} PCNT_TypeDef; +/** @} End of group EFR32ZG23_PCNT */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_PCNT + * @{ + * @defgroup EFR32ZG23_PCNT_BitFields PCNT Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT IPVERSION */ +#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ +#define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ + +/* Bit fields for PCNT EN */ +#define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */ +#define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */ +#define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */ +#define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */ +#define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */ +#define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */ + +/* Bit fields for PCNT SWRST */ +#define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */ +#define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */ +#define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */ + +/* Bit fields for PCNT CFG */ +#define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */ +#define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */ +#define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */ +#define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */ +#define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */ +#define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */ +#define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */ +#define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */ +#define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */ +#define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */ +#define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */ +#define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */ +#define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */ +#define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */ +#define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */ +#define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ +#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ +#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ +#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT OVSCTRL */ +#define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */ +#define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */ +#define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT LOCK */ +#define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */ +#define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */ + +/** @} End of group EFR32ZG23_PCNT_BitFields */ +/** @} End of group EFR32ZG23_PCNT */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_PCNT_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h new file mode 100644 index 000000000..418598da6 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_pfmxpprf.h @@ -0,0 +1,215 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 PFMXPPRF register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_PFMXPPRF_H +#define EFR32ZG23_PFMXPPRF_H +#define PFMXPPRF_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_PFMXPPRF PFMXPPRF + * @{ + * @brief EFR32ZG23 PFMXPPRF Register Declaration. + *****************************************************************************/ + +/** PFMXPPRF Register Declaration. */ +typedef struct pfmxpprf_typedef{ + __IOM uint32_t RFIMDCDCCTRL0; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS; /**< New Register */ + __IOM uint32_t RPURATD0; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED0[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_SET; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_SET; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_SET; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_SET; /**< New Register */ + __IOM uint32_t RPURATD0_SET; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED1[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_CLR; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_CLR; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_CLR; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_CLR; /**< New Register */ + __IOM uint32_t RPURATD0_CLR; /**< Root Access Type Descriptor Register */ + uint32_t RESERVED2[1019U]; /**< Reserved for future use */ + __IOM uint32_t RFIMDCDCCTRL0_TGL; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL1_TGL; /**< New Register */ + __IOM uint32_t RFIMDCDCCTRL2_TGL; /**< New Register */ + __IM uint32_t RFIMDCDCSTATUS_TGL; /**< New Register */ + __IOM uint32_t RPURATD0_TGL; /**< Root Access Type Descriptor Register */ +} PFMXPPRF_TypeDef; +/** @} End of group EFR32ZG23_PFMXPPRF */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_PFMXPPRF + * @{ + * @defgroup EFR32ZG23_PFMXPPRF_BitFields PFMXPPRF Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PFMXPPRF RFIMDCDCCTRL0 */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL0 */ +#define _PFMXPPRF_RFIMDCDCCTRL0_MASK 0x80000003UL /**< Mask for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ (0x1UL << 0) /**< TX Max Req */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_SHIFT 0 /**< Shift value for PFMXPPRF_TXMAXREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_MASK 0x1UL /**< Bit mask for PFMXPPRF_TXMAXREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ +#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ (0x1UL << 1) /**< RX PP Req */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_SHIFT 1 /**< Shift value for PFMXPPRF_RXPPREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_MASK 0x2UL /**< Bit mask for PFMXPPRF_RXPPREQ */ +#define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ +#define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ + +/* Bit fields for PFMXPPRF RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_RESETVALUE 0x00000014UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_MASK 0x0000003FUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN (0x1UL << 0) /**< DCDC DIV Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCDIVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCDIVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN (0x1UL << 1) /**< DCDC DIV Inverter Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_SHIFT 1 /**< Shift value for PFMXPPRF_DCDCDIVINVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_MASK 0x2UL /**< Bit mask for PFMXPPRF_DCDCDIVINVEN */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_SHIFT 2 /**< Shift value for PFMXPPRF_DCDCDIVRATIO */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_MASK 0x3CUL /**< Bit mask for PFMXPPRF_DCDCDIVRATIO */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT 0x00000005UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 0x00000000UL /**< Mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 0x00000001UL /**< Mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 0x00000002UL /**< Mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 0x00000003UL /**< Mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 0x00000004UL /**< Mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 0x00000005UL /**< Mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 0x00000006UL /**< Mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 0x00000007UL /**< Mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 0x00000008UL /**< Mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 0x00000009UL /**< Mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 0x0000000AUL /**< Mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 0x0000000BUL /**< Mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 0x0000000CUL /**< Mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 0x0000000DUL /**< Mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 0x0000000EUL /**< Mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 0x0000000FUL /**< Mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1 */ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 << 2) /**< Shifted mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 << 2) /**< Shifted mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 << 2) /**< Shifted mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 << 2) /**< Shifted mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 << 2) /**< Shifted mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 << 2) /**< Shifted mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 << 2) /**< Shifted mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 << 2) /**< Shifted mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 << 2) /**< Shifted mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 << 2) /**< Shifted mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 << 2) /**< Shifted mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 << 2) /**< Shifted mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 << 2) /**< Shifted mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 << 2) /**< Shifted mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 << 2) /**< Shifted mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1*/ +#define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 << 2) /**< Shifted mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1*/ + +/* Bit fields for PFMXPPRF RFIMDCDCCTRL2 */ +#define _PFMXPPRF_RFIMDCDCCTRL2_RESETVALUE 0x0AD0B4A0UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL2 */ +#define _PFMXPPRF_RFIMDCDCCTRL2_MASK 0x9FFFFFFFUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL2 */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_SHIFT 0 /**< Shift value for PFMXPPRF_PPTMAX */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_MASK 0x1FFUL /**< Bit mask for PFMXPPRF_PPTMAX */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT 0x000000A0UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_SHIFT 9 /**< Shift value for PFMXPPRF_PPTMIN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_MASK 0x3FE00UL /**< Bit mask for PFMXPPRF_PPTMIN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT 0x0000005AUL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT << 9) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_SHIFT 18 /**< Shift value for PFMXPPRF_PPND */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_MASK 0x7FC0000UL /**< Bit mask for PFMXPPRF_PPND */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT 0x000000B4UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT << 18) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN (0x1UL << 27) /**< Pulse Pairing Calibration Loop Enable */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_SHIFT 27 /**< Shift value for PFMXPPRF_PPCALEN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_MASK 0x8000000UL /**< Bit mask for PFMXPPRF_PPCALEN */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT << 27) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ +#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY (0x1UL << 28) /**< Pulse Pairing Sync Only */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_SHIFT 28 /**< Shift value for PFMXPPRF_PPSYNCONLY */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_MASK 0x10000000UL /**< Bit mask for PFMXPPRF_PPSYNCONLY */ +#define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ +#define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT << 28) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ + +/* Bit fields for PFMXPPRF RFIMDCDCSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_MASK 0x0001FF07UL /**< Mask for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN (0x1UL << 0) /**< DCDC Enable Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCEN */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCEN */ +#define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS (0x1UL << 1) /**< TX MAX Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_SHIFT 1 /**< Shift value for PFMXPPRF_TXMAXSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_MASK 0x2UL /**< Bit mask for PFMXPPRF_TXMAXSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS (0x1UL << 2) /**< RX PP Status */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_SHIFT 2 /**< Shift value for PFMXPPRF_RXPPSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_MASK 0x4UL /**< Bit mask for PFMXPPRF_RXPPSTATUS */ +#define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_SHIFT 8 /**< Shift value for PFMXPPRF_WNO1 */ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_MASK 0x1FF00UL /**< Bit mask for PFMXPPRF_WNO1 */ +#define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ +#define PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT << 8) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ + +/* Bit fields for PFMXPPRF RPURATD0 */ +#define _PFMXPPRF_RPURATD0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RPURATD0 */ +#define _PFMXPPRF_RPURATD0_MASK 0x00000007UL /**< Mask for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0 (0x1UL << 0) /**< RFIMDCDCCTRL0 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_SHIFT 0 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL0 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_MASK 0x1UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL0 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1 (0x1UL << 1) /**< RFIMDCDCCTRL1 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_SHIFT 1 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL1 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_MASK 0x2UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL1 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2 (0x1UL << 2) /**< RFIMDCDCCTRL2 Protection Bit */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_SHIFT 2 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL2 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_MASK 0x4UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL2 */ +#define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ +#define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ + +/** @} End of group EFR32ZG23_PFMXPPRF_BitFields */ +/** @} End of group EFR32ZG23_PFMXPPRF */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_PFMXPPRF_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h new file mode 100644 index 000000000..410677b29 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs.h @@ -0,0 +1,1553 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 PRS register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_PRS_H +#define EFR32ZG23_PRS_H +#define PRS_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_PRS PRS + * @{ + * @brief EFR32ZG23 PRS Register Declaration. + *****************************************************************************/ + +/** PRS ASYNC_CH Register Group Declaration. */ +typedef struct prs_async_ch_typedef{ + __IOM uint32_t CTRL; /**< Async Channel Control Register */ +} PRS_ASYNC_CH_TypeDef; + +/** PRS SYNC_CH Register Group Declaration. */ +typedef struct prs_sync_ch_typedef{ + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +} PRS_SYNC_CH_TypeDef; + +/** PRS Register Declaration. */ +typedef struct prs_typedef{ + __IM uint32_t IPVERSION; /**< PRS IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED2[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + uint32_t RESERVED6[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */ + uint32_t RESERVED10[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */ + uint32_t RESERVED17[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[893U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART2_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART2_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + uint32_t RESERVED23[4U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_LESENSE_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */ + uint32_t RESERVED24[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ +} PRS_TypeDef; +/** @} End of group EFR32ZG23_PRS */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_PRS + * @{ + * @defgroup EFR32ZG23_PRS_BitFields PRS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ + +/* Bit fields for PRS ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ + +/* Bit fields for PRS ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ + +/* Bit fields for PRS ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ + +/* Bit fields for PRS SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ + +/* Bit fields for PRS ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ + +/* Bit fields for PRS SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ + +/* Bit fields for PRS CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ + +/* Bit fields for PRS CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ + +/* Bit fields for PRS CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_CLK */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_CLK */ +#define PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_RX */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_RX */ +#define PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART2_TRIGGER */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define _PRS_CONSUMER_EUSART2_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART2_TRIGGER */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ +#define PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART2_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART2_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ + +/* Bit fields for PRS CONSUMER_LESENSE_START */ +#define _PRS_CONSUMER_LESENSE_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LESENSE_START*/ +#define _PRS_CONSUMER_LESENSE_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LESENSE_START */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LESENSE_START */ +#define PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LESENSE_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LESENSE_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ + +/* Bit fields for PRS CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ +#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ +#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ + +/* Bit fields for PRS CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ + +/* Bit fields for PRS CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ + +/* Bit fields for PRS CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ + +/* Bit fields for PRS CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ +#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ +#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ + +/* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ +#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ + +/* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ + +/* Bit fields for PRS CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ + +/* Bit fields for PRS CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ + +/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ +#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ +#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ + +/** @} End of group EFR32ZG23_PRS_BitFields */ +/** @} End of group EFR32ZG23_PRS */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_PRS_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h new file mode 100644 index 000000000..49d1defa4 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_prs_signals.h @@ -0,0 +1,978 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 PRS register signal bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_PRS_SIGNALS_H +#define EFR32ZG23_PRS_SIGNALS_H + +/** Synchronous signal sources enumeration: */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000007UL) + +/** Synchronous signal sources enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) + +/** Synchronous signals enumeration: */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (0x00000001UL) + +/** Synchronous signals enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC << 0) + +/** Synchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_SYNC_VDAC0_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC) +#define PRS_SYNC_VDAC0_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC) + +/** Asynchronous signal sources enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x00000008UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x00000009UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (0x0000000bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (0x0000000cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (0x0000000dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (0x0000000eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (0x0000000fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE (0x00000010UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (0x00000011UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x00000012UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x00000013UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x00000014UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000015UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000016UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (0x00000017UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LCD (0x00000018UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000021UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000022UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000023UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000024UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000025UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000026UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000027UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000028UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x00000029UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x0000002fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000030UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000031UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000032UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000033UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000034UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L (0x00000035UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 (0x00000036UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000037UL) + +/** Asynchronous signal sources enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE (_PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LCD (_PRS_ASYNC_CH_CTRL_SOURCESEL_LCD << 8) + +/** Asynchronous signals enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL (0x00000007UL) + +/** Asynchronous signals enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP (_PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL << 0) + +/** Asynchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) +#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) +#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) +#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) +#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) +#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) +#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) +#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) +#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) +#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) +#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) +#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) +#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) +#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) +#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) +#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) +#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) +#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) +#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) +#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) +#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) +#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) +#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) +#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) +#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) +#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) +#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) +#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) +#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) +#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) +#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) +#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) +#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) +#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) +#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) +#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) +#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) +#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) +#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) +#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) +#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) +#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) +#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) +#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) +#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) +#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) +#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) +#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) +#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) +#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) +#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) +#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) +#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) +#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) +#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) +#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) +#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) +#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) +#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) +#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) +#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) +#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) +#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) +#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) +#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) +#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) +#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) +#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) +#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) +#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) +#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) +#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) +#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) +#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) +#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) +#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) +#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) +#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) +#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) +#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) +#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) +#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) +#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) +#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) +#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) +#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) +#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) +#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) +#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) +#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) +#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) +#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) +#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) +#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) +#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) +#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) +#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) +#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) +#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) +#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) +#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) +#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) +#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) +#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) +#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) +#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA) +#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID) +#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT) +#define PRS_ASYNC_ACMP1_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT) +#define PRS_ASYNC_VDAC0L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM) +#define PRS_ASYNC_VDAC0L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM) +#define PRS_ASYNC_VDAC0L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC) +#define PRS_ASYNC_VDAC0L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC) +#define PRS_ASYNC_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF) +#define PRS_ASYNC_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF) +#define PRS_ASYNC_PCNT0_DIR (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR) +#define PRS_ASYNC_PCNT0_UFOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF) +#define PRS_ASYNC_SYSRTC0_GRP0OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0) +#define PRS_ASYNC_SYSRTC0_GRP0OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1) +#define PRS_ASYNC_SYSRTC0_GRP1OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0) +#define PRS_ASYNC_SYSRTC0_GRP1OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1) +#define PRS_ASYNC_LESENSE_DECOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT0) +#define PRS_ASYNC_LESENSE_DECOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT1) +#define PRS_ASYNC_LESENSE_DECOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECOUT2) +#define PRS_ASYNC_LESENSE_DECCMP (PRS_ASYNC_CH_CTRL_SOURCESEL_LESENSE | PRS_ASYNC_CH_CTRL_SIGSEL_LESENSEDECCMP) +#define PRS_ASYNC_HFXO0L_STATUS (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS) +#define PRS_ASYNC_HFXO0L_STATUS1 (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1) +#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS) +#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX) +#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS) +#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV) +#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX) +#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC) +#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL) +#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL) +#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS) +#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX) +#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS) +#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV) +#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX) +#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC) +#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL) +#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL) +#define PRS_ASYNC_EUSART2L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LCS) +#define PRS_ASYNC_EUSART2L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LIRDATX) +#define PRS_ASYNC_EUSART2L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRTS) +#define PRS_ASYNC_EUSART2L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXDATAV) +#define PRS_ASYNC_EUSART2L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTX) +#define PRS_ASYNC_EUSART2L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXC) +#define PRS_ASYNC_EUSART2L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LRXFL) +#define PRS_ASYNC_EUSART2L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART2L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART2LTXFL) + +/** + * Asynchronous signals and sources combined and aligned with register bit fields + * without the '_ASYNCH_' infix in order for backward compatibility: + */ +#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) +#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) +#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) +#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) +#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) +#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) +#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) +#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) +#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) +#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) +#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) +#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) +#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) +#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) +#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) +#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) +#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) +#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) +#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) +#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) +#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) +#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) +#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) +#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) +#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) +#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) +#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) +#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) +#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) +#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) +#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) +#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) +#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) +#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) +#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) +#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) +#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) +#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) +#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) +#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) +#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) +#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) +#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) +#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) +#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) +#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) +#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) +#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) +#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) +#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) +#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) +#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) +#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) +#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) +#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) +#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) +#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) +#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) +#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) +#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) +#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) +#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) +#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) +#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) +#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) +#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) +#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) +#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) +#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) +#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) +#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) +#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) +#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) +#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) +#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) +#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) +#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) +#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) +#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) +#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) +#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) +#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) +#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) +#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) +#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) +#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) +#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) +#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) +#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) +#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) +#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) +#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) +#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) +#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) +#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) +#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) +#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) +#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) +#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) +#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) +#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) +#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) +#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) +#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) +#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) +#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) +#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) +#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) +#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) +#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) +#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) +#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) +#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) +#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) +#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) +#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) +#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) +#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) +#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) +#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) +#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) +#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) +#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) +#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) +#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) +#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) +#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) +#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) +#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA) +#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID) +#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) +#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) +#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) +#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) +#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) +#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT) +#define PRS_ACMP1_OUT (PRS_ASYNC_ACMP1_OUT) +#define PRS_VDAC0L_CH0WARM (PRS_ASYNC_VDAC0L_CH0WARM) +#define PRS_VDAC0L_CH1WARM (PRS_ASYNC_VDAC0L_CH1WARM) +#define PRS_VDAC0L_CH0DONEASYNC (PRS_ASYNC_VDAC0L_CH0DONEASYNC) +#define PRS_VDAC0L_CH1DONEASYNC (PRS_ASYNC_VDAC0L_CH1DONEASYNC) +#define PRS_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_VDAC0L_INTERNALTIMEROF) +#define PRS_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_VDAC0L_REFRESHTIMEROF) +#define PRS_PCNT0_DIR (PRS_ASYNC_PCNT0_DIR) +#define PRS_PCNT0_UFOF (PRS_ASYNC_PCNT0_UFOF) +#define PRS_SYSRTC0_GRP0OUT0 (PRS_ASYNC_SYSRTC0_GRP0OUT0) +#define PRS_SYSRTC0_GRP0OUT1 (PRS_ASYNC_SYSRTC0_GRP0OUT1) +#define PRS_SYSRTC0_GRP1OUT0 (PRS_ASYNC_SYSRTC0_GRP1OUT0) +#define PRS_SYSRTC0_GRP1OUT1 (PRS_ASYNC_SYSRTC0_GRP1OUT1) +#define PRS_LESENSE_DECOUT0 (PRS_ASYNC_LESENSE_DECOUT0) +#define PRS_LESENSE_DECOUT1 (PRS_ASYNC_LESENSE_DECOUT1) +#define PRS_LESENSE_DECOUT2 (PRS_ASYNC_LESENSE_DECOUT2) +#define PRS_LESENSE_DECCMP (PRS_ASYNC_LESENSE_DECCMP) +#define PRS_HFXO0L_STATUS (PRS_ASYNC_HFXO0L_STATUS) +#define PRS_HFXO0L_STATUS1 (PRS_ASYNC_HFXO0L_STATUS1) +#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS) +#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX) +#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS) +#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV) +#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX) +#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC) +#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL) +#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL) +#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS) +#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX) +#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS) +#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV) +#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX) +#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC) +#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL) +#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL) +#define PRS_EUSART2L_CS (PRS_ASYNC_EUSART2L_CS) +#define PRS_EUSART2L_IRDATX (PRS_ASYNC_EUSART2L_IRDATX) +#define PRS_EUSART2L_RTS (PRS_ASYNC_EUSART2L_RTS) +#define PRS_EUSART2L_RXDATAV (PRS_ASYNC_EUSART2L_RXDATAV) +#define PRS_EUSART2L_TX (PRS_ASYNC_EUSART2L_TX) +#define PRS_EUSART2L_TXC (PRS_ASYNC_EUSART2L_TXC) +#define PRS_EUSART2L_RXFL (PRS_ASYNC_EUSART2L_RXFL) +#define PRS_EUSART2L_TXFL (PRS_ASYNC_EUSART2L_TXFL) + +#endif // EFR32ZG23_PRS_SIGNALS_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h new file mode 100644 index 000000000..ae5ad6f5f --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_scratchpad.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 SCRATCHPAD register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_SCRATCHPAD_H +#define EFR32ZG23_SCRATCHPAD_H +#define SCRATCHPAD_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_SCRATCHPAD SCRATCHPAD + * @{ + * @brief EFR32ZG23 SCRATCHPAD Register Declaration. + *****************************************************************************/ + +/** SCRATCHPAD Register Declaration. */ +typedef struct scratchpad_typedef{ + __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ + uint32_t RESERVED0[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ + uint32_t RESERVED1[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ + uint32_t RESERVED2[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ +} SCRATCHPAD_TypeDef; +/** @} End of group EFR32ZG23_SCRATCHPAD */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SCRATCHPAD + * @{ + * @defgroup EFR32ZG23_SCRATCHPAD_BitFields SCRATCHPAD Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SCRATCHPAD SREG0 */ +#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ +#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ + +/* Bit fields for SCRATCHPAD SREG1 */ +#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ +#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ + +/** @} End of group EFR32ZG23_SCRATCHPAD_BitFields */ +/** @} End of group EFR32ZG23_SCRATCHPAD */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_SCRATCHPAD_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h new file mode 100644 index 000000000..86bcba1c0 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_semailbox.h @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 SEMAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_SEMAILBOX_H +#define EFR32ZG23_SEMAILBOX_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_SEMAILBOX_HOST SEMAILBOX_HOST + * @{ + * @brief EFR32ZG23 SEMAILBOX_HOST Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_HOST Register Declaration. */ +typedef struct semailbox_host_typedef{ + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_HOST_TypeDef; +/** @} End of group EFR32ZG23_SEMAILBOX_HOST */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SEMAILBOX_HOST + * @{ + * @defgroup EFR32ZG23_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ + +/* Bit fields for SEMAILBOX TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ + +/* Bit fields for SEMAILBOX RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ + +/* Bit fields for SEMAILBOX TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ + +/* Bit fields for SEMAILBOX RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ + +/* Bit fields for SEMAILBOX TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ + +/* Bit fields for SEMAILBOX RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ + +/* Bit fields for SEMAILBOX CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ + +/** @} End of group EFR32ZG23_SEMAILBOX_HOST_BitFields */ +/** @} End of group EFR32ZG23_SEMAILBOX_HOST */ +/**************************************************************************//** + * @defgroup EFR32ZG23_SEMAILBOX_APBSE SEMAILBOX_APBSE + * @{ + * @brief EFR32ZG23 SEMAILBOX_APBSE Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_APBSE Register Declaration. */ +typedef struct semailbox_apbse_typedef{ + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_APBSE_TypeDef; +/** @} End of group EFR32ZG23_SEMAILBOX_APBSE */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SEMAILBOX_APBSE + * @{ + * @defgroup EFR32ZG23_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ + +/** @} End of group EFR32ZG23_SEMAILBOX_APBSE_BitFields */ +/** @} End of group EFR32ZG23_SEMAILBOX_APBSE */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_SEMAILBOX_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h new file mode 100644 index 000000000..dd1483d7a --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_smu.h @@ -0,0 +1,1483 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 SMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_SMU_H +#define EFR32ZG23_SMU_H +#define SMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_SMU SMU + * @{ + * @brief EFR32ZG23 SMU Register Declaration. + *****************************************************************************/ + +/** SMU Register Declaration. */ +typedef struct smu_typedef{ + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control Settings */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< Privileged Access */ + __IOM uint32_t PPUPATD1; /**< Privileged Access */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< Secure Access */ + __IOM uint32_t PPUSATD1; /**< Secure Access */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< Fault Status */ + __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ + __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ + __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ + __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ +} SMU_TypeDef; +/** @} End of group EFR32ZG23_SMU */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SMU + * @{ + * @defgroup EFR32ZG23_SMU_BitFields SMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ + +/* Bit fields for SMU STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ + +/* Bit fields for SMU LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ +#define _SMU_PPUPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUPATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART2_DEFAULT (_SMU_PPUPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x01FFFFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ +#define _SMU_PPUPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUPATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SYSRTC_DEFAULT (_SMU_PPUPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ +#define _SMU_PPUPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUPATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCD_DEFAULT (_SMU_PPUPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ +#define _SMU_PPUPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUPATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LCDRF_DEFAULT (_SMU_PPUPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ +#define _SMU_PPUPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUPATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PFMXPPRF_DEFAULT (_SMU_PPUPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ +#define _SMU_PPUPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ +#define _SMU_PPUPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ +#define _SMU_PPUPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ +#define _SMU_PPUPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUPATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LESENSE_DEFAULT (_SMU_PPUPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Secure Access */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ +#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ +#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Secure Access */ +#define _SMU_PPUSATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUSATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUSATD0_EUSART2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART2_DEFAULT (_SMU_PPUSATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ + +/* Bit fields for SMU PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x01FFFFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Secure Access */ +#define _SMU_PPUSATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUSATD1_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SYSRTC_DEFAULT (_SMU_PPUSATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD (0x1UL << 1) /**< LCD Secure Access */ +#define _SMU_PPUSATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUSATD1_LCD_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCD_DEFAULT (_SMU_PPUSATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Secure Access */ +#define _SMU_PPUSATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM (0x1UL << 3) /**< DMEM Secure Access */ +#define _SMU_PPUSATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF (0x1UL << 4) /**< LCDRF Secure Access */ +#define _SMU_PPUSATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUSATD1_LCDRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LCDRF_DEFAULT (_SMU_PPUSATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Secure Access */ +#define _SMU_PPUSATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUSATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUSATD1_PFMXPPRF_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PFMXPPRF_DEFAULT (_SMU_PPUSATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 7) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 10) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Secure Access */ +#define _SMU_PPUSATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Secure Access */ +#define _SMU_PPUSATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT (0x1UL << 15) /**< PCNT Secure Access */ +#define _SMU_PPUSATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LESENSE (0x1UL << 16) /**< LESENSE Secure Access */ +#define _SMU_PPUSATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUSATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUSATD1_LESENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LESENSE_DEFAULT (_SMU_PPUSATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Secure Access */ +#define _SMU_PPUSATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 19) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Secure Access */ +#define _SMU_PPUSATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ + +/* Bit fields for SMU BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0 (0x1UL << 3) /**< RFECA0 privileged mode */ +#define _SMU_BMPUPATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1 (0x1UL << 4) /**< RFECA1 privileged mode */ +#define _SMU_BMPUPATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ + +/* Bit fields for SMU BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0 (0x1UL << 3) /**< RFECA0 secure mode */ +#define _SMU_BMPUSATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1 (0x1UL << 4) /**< RFECA1 secure mode */ +#define _SMU_BMPUSATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA secure mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ + +/* Bit fields for SMU BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ + +/* Bit fields for SMU BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ + +/* Bit fields for SMU ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ + +/* Bit fields for SMU ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ + +/* Bit fields for SMU ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ + +/* Bit fields for SMU ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ + +/* Bit fields for SMU ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ + +/* Bit fields for SMU ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ + +/** @} End of group EFR32ZG23_SMU_BitFields */ +/** @} End of group EFR32ZG23_SMU */ +/**************************************************************************//** + * @defgroup EFR32ZG23_SMU_CFGNS SMU_CFGNS + * @{ + * @brief EFR32ZG23 SMU_CFGNS Register Declaration. + *****************************************************************************/ + +/** SMU_CFGNS Register Declaration. */ +typedef struct smu_cfgns_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Status Register */ + __IOM uint32_t NSLOCK; /**< Lock Register */ + __IOM uint32_t NSIF; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Status Register */ + __IOM uint32_t NSLOCK_SET; /**< Lock Register */ + __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Status Register */ + __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ + __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Status Register */ + __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ + __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ +} SMU_CFGNS_TypeDef; +/** @} End of group EFR32ZG23_SMU_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SMU_CFGNS + * @{ + * @defgroup EFR32ZG23_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ + +/* Bit fields for SMU NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ + +/* Bit fields for SMU NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ + +/* Bit fields for SMU NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ + +/* Bit fields for SMU PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART2 (0x1UL << 31) /**< EUSART2 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART2_SHIFT 31 /**< Shift value for SMU_EUSART2 */ +#define _SMU_PPUNSPATD0_EUSART2_MASK 0x80000000UL /**< Bit mask for SMU_EUSART2 */ +#define _SMU_PPUNSPATD0_EUSART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART2_DEFAULT (_SMU_PPUNSPATD0_EUSART2_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ + +/* Bit fields for SMU PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x01FFFFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC (0x1UL << 0) /**< SYSRTC Privileged Access */ +#define _SMU_PPUNSPATD1_SYSRTC_SHIFT 0 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_MASK 0x1UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUNSPATD1_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SYSRTC_DEFAULT (_SMU_PPUNSPATD1_SYSRTC_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD (0x1UL << 1) /**< LCD Privileged Access */ +#define _SMU_PPUNSPATD1_LCD_SHIFT 1 /**< Shift value for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_MASK 0x2UL /**< Bit mask for SMU_LCD */ +#define _SMU_PPUNSPATD1_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCD_DEFAULT (_SMU_PPUNSPATD1_LCD_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 2) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 2 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x4UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM (0x1UL << 3) /**< DMEM Privileged Access */ +#define _SMU_PPUNSPATD1_DMEM_SHIFT 3 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_MASK 0x8UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF (0x1UL << 4) /**< LCDRF Privileged Access */ +#define _SMU_PPUNSPATD1_LCDRF_SHIFT 4 /**< Shift value for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_MASK 0x10UL /**< Bit mask for SMU_LCDRF */ +#define _SMU_PPUNSPATD1_LCDRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LCDRF_DEFAULT (_SMU_PPUNSPATD1_LCDRF_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PFMXPPRF (0x1UL << 5) /**< PFMXPPRF Privileged Access */ +#define _SMU_PPUNSPATD1_PFMXPPRF_SHIFT 5 /**< Shift value for SMU_PFMXPPRF */ +#define _SMU_PPUNSPATD1_PFMXPPRF_MASK 0x20UL /**< Bit mask for SMU_PFMXPPRF */ +#define _SMU_PPUNSPATD1_PFMXPPRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PFMXPPRF_DEFAULT (_SMU_PPUNSPATD1_PFMXPPRF_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 6) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 6 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x40UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 7) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 7 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x80UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 8) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 8 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x100UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 9) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 9 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x200UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 10) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 10 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x400UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 11) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 11 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x800UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 12) /**< ACMP1 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP1_SHIFT 12 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_MASK 0x1000UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 13) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 13 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x2000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 14) /**< VDAC0 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC0_SHIFT 14 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_MASK 0x4000UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT (0x1UL << 15) /**< PCNT Privileged Access */ +#define _SMU_PPUNSPATD1_PCNT_SHIFT 15 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_MASK 0x8000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LESENSE (0x1UL << 16) /**< LESENSE Privileged Access */ +#define _SMU_PPUNSPATD1_LESENSE_SHIFT 16 /**< Shift value for SMU_LESENSE */ +#define _SMU_PPUNSPATD1_LESENSE_MASK 0x10000UL /**< Bit mask for SMU_LESENSE */ +#define _SMU_PPUNSPATD1_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LESENSE_DEFAULT (_SMU_PPUNSPATD1_LESENSE_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 17) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 17 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x20000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 18) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD1_HFXO0_SHIFT 18 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_MASK 0x40000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 19) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 19 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x80000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 20) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 20 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x100000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 21) /**< WDOG1 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG1_SHIFT 21 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_MASK 0x200000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 22) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART0_SHIFT 22 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_MASK 0x400000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 23) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 23 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x800000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 24) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 24 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x1000000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ + +/* Bit fields for SMU PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ + +/* Bit fields for SMU BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x0000003FUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 3) /**< RFECA0 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 3 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x8UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 4) /**< RFECA1 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 4 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x10UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 5) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 5 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x20UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ + +/** @} End of group EFR32ZG23_SMU_CFGNS_BitFields */ +/** @} End of group EFR32ZG23_SMU_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_SMU_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h new file mode 100644 index 000000000..dc990a512 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_syscfg.h @@ -0,0 +1,729 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 SYSCFG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_SYSCFG_H +#define EFR32ZG23_SYSCFG_H +#define SYSCFG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_SYSCFG SYSCFG + * @{ + * @brief EFR32ZG23 SYSCFG Register Declaration. + *****************************************************************************/ + +/** SYSCFG Register Declaration. */ +typedef struct syscfg_typedef{ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ + uint32_t RESERVED7[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ + uint32_t RESERVED8[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */ + uint32_t RESERVED11[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[635U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ + uint32_t RESERVED17[54U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ + uint32_t RESERVED21[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ + uint32_t RESERVED22[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */ + uint32_t RESERVED25[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[635U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ + uint32_t RESERVED31[54U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ + uint32_t RESERVED35[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ + uint32_t RESERVED36[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */ + uint32_t RESERVED39[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[635U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ + uint32_t RESERVED45[54U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ + uint32_t RESERVED49[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ + uint32_t RESERVED50[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED52[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */ + uint32_t RESERVED53[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ +} SYSCFG_TypeDef; +/** @} End of group EFR32ZG23_SYSCFG */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SYSCFG + * @{ + * @defgroup EFR32ZG23_SYSCFG_BitFields SYSCFG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG IPVERSION */ +#define _SYSCFG_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ +#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ + +/* Bit fields for SYSCFG IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x33003F0FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ +#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ +#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ +#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ +#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ +#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ +#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ + +/* Bit fields for SYSCFG IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x33003F0FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ +#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ +#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ +#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ +#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ +#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ +#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ + +/* Bit fields for SYSCFG CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000E01UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000038UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ + +/* Bit fields for SYSCFG CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_PG23 0x0000001AUL /**< Mode PG23 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_FG23 0x00000038UL /**< Mode FG23 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_ZG23 0x00000039UL /**< Mode ZG23 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_SG23 0x0000003AUL /**< Mode SG23 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_PG23 (_SYSCFG_CHIPREV_FAMILY_PG23 << 6) /**< Shifted mode PG23 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_FG23 (_SYSCFG_CHIPREV_FAMILY_FG23 << 6) /**< Shifted mode FG23 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_ZG23 (_SYSCFG_CHIPREV_FAMILY_ZG23 << 6) /**< Shifted mode ZG23 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_SG23 (_SYSCFG_CHIPREV_FAMILY_SG23 << 6) /**< Shifted mode SG23 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ + +/* Bit fields for SYSCFG CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ + +/* Bit fields for SYSCFG CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ + +/* Bit fields for SYSCFG DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00000007UL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3 0x00000004UL /**< Mode BLK3 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO3 0x00000006UL /**< Mode BLK2TO3 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO3 0x00000007UL /**< Mode BLK1TO3 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3 << 0) /**< Shifted mode BLK3 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO3 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO3 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for SYSCFG_DMEM0RETNCTRL*/ + +/* Bit fields for SYSCFG RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ + +/* Bit fields for SYSCFG RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ + +/* Bit fields for SYSCFG RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ + +/* Bit fields for SYSCFG SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ + +/* Bit fields for SYSCFG FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ + +/* Bit fields for SYSCFG ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ + +/* Bit fields for SYSCFG DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00000013UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000001FUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL (0x1UL << 0) /**< LDMA portmap selection */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x1UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL (0x1UL << 1) /**< SRWAES portmap selection */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 1 /**< Shift value for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0x2UL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL (0x1UL << 2) /**< AHBSRW portmap selection */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x4UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL (0x1UL << 3) /**< SRWECA0 portmap selection */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 3 /**< Shift value for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0x8UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL (0x1UL << 4) /**< SRWECA1 portmap selection */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 4 /**< Shift value for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x10UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ + +/* Bit fields for SYSCFG ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ + +/* Bit fields for SYSCFG ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ + +/* Bit fields for SYSCFG ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ + +/* Bit fields for SYSCFG ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ +#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ + +/** @} End of group EFR32ZG23_SYSCFG_BitFields */ +/** @} End of group EFR32ZG23_SYSCFG */ +/**************************************************************************//** + * @defgroup EFR32ZG23_SYSCFG_CFGNS SYSCFG_CFGNS + * @{ + * @brief EFR32ZG23 SYSCFG_CFGNS Register Declaration. + *****************************************************************************/ + +/** SYSCFG_CFGNS Register Declaration. */ +typedef struct syscfg_cfgns_typedef{ + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED1[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[637U]; /**< Reserved for future use */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED5[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[637U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED9[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[637U]; /**< Reserved for future use */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED13[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} SYSCFG_CFGNS_TypeDef; +/** @} End of group EFR32ZG23_SYSCFG_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SYSCFG_CFGNS + * @{ + * @defgroup EFR32ZG23_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ +#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ +#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ + +/* Bit fields for SYSCFG ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ +#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ + +/* Bit fields for SYSCFG ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ +#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ + +/** @} End of group EFR32ZG23_SYSCFG_CFGNS_BitFields */ +/** @} End of group EFR32ZG23_SYSCFG_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_SYSCFG_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h new file mode 100644 index 000000000..b0126007d --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_sysrtc.h @@ -0,0 +1,421 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 SYSRTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_SYSRTC_H +#define EFR32ZG23_SYSRTC_H +#define SYSRTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_SYSRTC SYSRTC + * @{ + * @brief EFR32ZG23 SYSRTC Register Declaration. + *****************************************************************************/ + +/** SYSRTC Register Declaration. */ +typedef struct sysrtc_typedef{ + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} SYSRTC_TypeDef; +/** @} End of group EFR32ZG23_SYSRTC */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_SYSRTC + * @{ + * @defgroup EFR32ZG23_SYSRTC_BitFields SYSRTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSRTC IPVERSION */ +#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ +#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ + +/* Bit fields for SYSRTC EN */ +#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ +#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ +#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ +#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ +#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ +#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ + +/* Bit fields for SYSRTC SWRST */ +#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ + +/* Bit fields for SYSRTC CFG */ +#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ +#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ + +/* Bit fields for SYSRTC CMD */ +#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ +#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ +#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ +#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ +#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ + +/* Bit fields for SYSRTC STATUS */ +#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ +#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ + +/* Bit fields for SYSRTC CNT */ +#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ +#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ +#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ + +/* Bit fields for SYSRTC SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ +#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ +#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ +#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ + +/* Bit fields for SYSRTC LOCK */ +#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ + +/* Bit fields for SYSRTC GRP0_IF */ +#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ + +/* Bit fields for SYSRTC GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ + +/* Bit fields for SYSRTC GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ + +/* Bit fields for SYSRTC GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ +#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ +#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ + +/* Bit fields for SYSRTC GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ +#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ + +/** @} End of group EFR32ZG23_SYSRTC_BitFields */ +/** @} End of group EFR32ZG23_SYSRTC */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_SYSRTC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h new file mode 100644 index 000000000..e0d479e97 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_timer.h @@ -0,0 +1,1020 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 TIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_TIMER_H +#define EFR32ZG23_TIMER_H +#define TIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_TIMER TIMER + * @{ + * @brief EFR32ZG23 TIMER Register Declaration. + *****************************************************************************/ + +/** TIMER CC Register Group Declaration. */ +typedef struct timer_cc_typedef{ + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} TIMER_CC_TypeDef; + +/** TIMER Register Declaration. */ +typedef struct timer_typedef{ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; +/** @} End of group EFR32ZG23_TIMER */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_TIMER + * @{ + * @defgroup EFR32ZG23_TIMER_BitFields TIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ + +/* Bit fields for TIMER CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ + +/* Bit fields for TIMER CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ + +/* Bit fields for TIMER CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ + +/* Bit fields for TIMER CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ + +/* Bit fields for TIMER CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ + +/* Bit fields for TIMER DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ + +/* Bit fields for TIMER DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ + +/* Bit fields for TIMER DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32ZG23_TIMER_BitFields */ +/** @} End of group EFR32ZG23_TIMER */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_TIMER_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h new file mode 100644 index 000000000..b63839088 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_ulfrco.h @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 ULFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_ULFRCO_H +#define EFR32ZG23_ULFRCO_H +#define ULFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_ULFRCO ULFRCO + * @{ + * @brief EFR32ZG23 ULFRCO Register Declaration. + *****************************************************************************/ + +/** ULFRCO Register Declaration. */ +typedef struct ulfrco_typedef{ + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} ULFRCO_TypeDef; +/** @} End of group EFR32ZG23_ULFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_ULFRCO + * @{ + * @defgroup EFR32ZG23_ULFRCO_BitFields ULFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ULFRCO IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ + +/* Bit fields for ULFRCO STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ + +/* Bit fields for ULFRCO IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ + +/* Bit fields for ULFRCO IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ + +/** @} End of group EFR32ZG23_ULFRCO_BitFields */ +/** @} End of group EFR32ZG23_ULFRCO */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_ULFRCO_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h new file mode 100644 index 000000000..eee5ca287 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_usart.h @@ -0,0 +1,1431 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 USART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_USART_H +#define EFR32ZG23_USART_H +#define USART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_USART USART + * @{ + * @brief EFR32ZG23 USART Register Declaration. + *****************************************************************************/ + +/** USART Register Declaration. */ +typedef struct usart_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +} USART_TypeDef; +/** @} End of group EFR32ZG23_USART */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_USART + * @{ + * @defgroup EFR32ZG23_USART_BitFields USART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for USART IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ + +/* Bit fields for USART EN */ +#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ +#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ +#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ +#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ +#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ + +/** @} End of group EFR32ZG23_USART_BitFields */ +/** @} End of group EFR32ZG23_USART */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_USART_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h new file mode 100644 index 000000000..a384e3d68 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_vdac.h @@ -0,0 +1,759 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 VDAC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_VDAC_H +#define EFR32ZG23_VDAC_H +#define VDAC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_VDAC VDAC + * @{ + * @brief EFR32ZG23 VDAC Register Declaration. + *****************************************************************************/ + +/** VDAC Register Declaration. */ +typedef struct vdac_typedef{ + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Module Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Config Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ + uint32_t RESERVED0[50U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[63U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Module Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Config Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ + uint32_t RESERVED5[50U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[63U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Config Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ + uint32_t RESERVED10[50U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Config Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ + uint32_t RESERVED15[50U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ +} VDAC_TypeDef; +/** @} End of group EFR32ZG23_VDAC */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_VDAC + * @{ + * @defgroup EFR32ZG23_VDAC_BitFields VDAC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC IPVERSION */ +#define _VDAC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_IPVERSION */ +#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ + +/* Bit fields for VDAC EN */ +#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ +#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ +#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ +#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ +#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ +#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ +#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ +#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ +#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ +#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ +#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ + +/* Bit fields for VDAC SWRST */ +#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ +#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ +#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ + +/* Bit fields for VDAC CFG */ +#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ +#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */ +#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ +#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ +#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ +#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ +#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ +#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ +#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ +#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ +#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ +#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ +#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ +#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ +#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ +#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ +#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ +#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ +#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ +#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ +#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ +#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CFG */ +#define _VDAC_CH0CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ +#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ +#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_LESENSE 0x00000003UL /**< Mode LESENSE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_LESENSE (_VDAC_CH0CFG_TRIGMODE_LESENSE << 4) /**< Shifted mode LESENSE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ +#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ + +/* Bit fields for VDAC CH1CFG */ +#define _VDAC_CH1CFG_RESETVALUE 0x00000010UL /**< Default value for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ +#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ +#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ +#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ +#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ +#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ +#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ +#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ +#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0F */ +#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ +#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ +#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ +#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ + +/* Bit fields for VDAC CH1F */ +#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ +#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ +#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ +#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ + +/* Bit fields for VDAC OUTCTRL */ +#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ + +/* Bit fields for VDAC OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ + +/** @} End of group EFR32ZG23_VDAC_BitFields */ +/** @} End of group EFR32ZG23_VDAC */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_VDAC_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h new file mode 100644 index 000000000..b00b461a7 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23_wdog.h @@ -0,0 +1,375 @@ +/**************************************************************************//** + * @file + * @brief EFR32ZG23 WDOG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23_WDOG_H +#define EFR32ZG23_WDOG_H +#define WDOG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32ZG23_WDOG WDOG + * @{ + * @brief EFR32ZG23 WDOG Register Declaration. + *****************************************************************************/ + +/** WDOG Register Declaration. */ +typedef struct wdog_typedef{ + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} WDOG_TypeDef; +/** @} End of group EFR32ZG23_WDOG */ + +/**************************************************************************//** + * @addtogroup EFR32ZG23_WDOG + * @{ + * @defgroup EFR32ZG23_WDOG_BitFields WDOG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ + +/* Bit fields for WDOG EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ +#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ + +/* Bit fields for WDOG CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ +#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/* Bit fields for WDOG LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/** @} End of group EFR32ZG23_WDOG_BitFields */ +/** @} End of group EFR32ZG23_WDOG */ +/** @} End of group Parts */ + +#endif // EFR32ZG23_WDOG_H diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h new file mode 100644 index 000000000..5ecd560ed --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm40.h @@ -0,0 +1,1455 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23A010F512GM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23A010F512GM40_H +#define EFR32ZG23A010F512GM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM40 EFR32ZG23A010F512GM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM40_Core EFR32ZG23A010F512GM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23A010F512GM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23A010F512GM40_Part EFR32ZG23A010F512GM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23A010F512GM40) +#define EFR32ZG23A010F512GM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23A010F512GM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23A010F512GM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23A010F512GM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM40_Peripheral_TypeDefs EFR32ZG23A010F512GM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23A010F512GM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM40_Peripheral_Base EFR32ZG23A010F512GM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23A010F512GM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM40_Peripheral_Declaration EFR32ZG23A010F512GM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23A010F512GM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM40_Peripheral_Parameters EFR32ZG23A010F512GM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23A010F512GM40_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23A010F512GM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h new file mode 100644 index 000000000..37771dd62 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a010f512gm48.h @@ -0,0 +1,1552 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23A010F512GM48 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23A010F512GM48_H +#define EFR32ZG23A010F512GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM48 EFR32ZG23A010F512GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + LCD_IRQn = 72, /*!< 72 EFR32 LCD Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM48_Core EFR32ZG23A010F512GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23A010F512GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23A010F512GM48_Part EFR32ZG23A010F512GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23A010F512GM48) +#define EFR32ZG23A010F512GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23A010F512GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23A010F512GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 11U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x07FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PA_PIN10 1U /**< GPIO pin PA10 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23A010F512GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM48_Peripheral_TypeDefs EFR32ZG23A010F512GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_lcd.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_lcdrf.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23A010F512GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM48_Peripheral_Base EFR32ZG23A010F512GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define LCD_S_BASE (0x400AC000UL) /* LCD_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define LCD_NS_BASE (0x500AC000UL) /* LCD_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23A010F512GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM48_Peripheral_Declaration EFR32ZG23A010F512GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23A010F512GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A010F512GM48_Peripheral_Parameters EFR32ZG23A010F512GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x1UL /**> */ +#define LCD_OCTAPLEX 0x0UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_SEG_NUM 0x14UL /**> None */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23A010F512GM48_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23A010F512GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h new file mode 100644 index 000000000..285dca077 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm40.h @@ -0,0 +1,1455 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23A020F512GM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23A020F512GM40_H +#define EFR32ZG23A020F512GM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM40 EFR32ZG23A020F512GM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM40_Core EFR32ZG23A020F512GM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23A020F512GM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23A020F512GM40_Part EFR32ZG23A020F512GM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23A020F512GM40) +#define EFR32ZG23A020F512GM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23A020F512GM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23A020F512GM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23A020F512GM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM40_Peripheral_TypeDefs EFR32ZG23A020F512GM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23A020F512GM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM40_Peripheral_Base EFR32ZG23A020F512GM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23A020F512GM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM40_Peripheral_Declaration EFR32ZG23A020F512GM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23A020F512GM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM40_Peripheral_Parameters EFR32ZG23A020F512GM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23A020F512GM40_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23A020F512GM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h new file mode 100644 index 000000000..3d3a4610f --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23a020f512gm48.h @@ -0,0 +1,1552 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23A020F512GM48 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23A020F512GM48_H +#define EFR32ZG23A020F512GM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM48 EFR32ZG23A020F512GM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + LCD_IRQn = 72, /*!< 72 EFR32 LCD Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM48_Core EFR32ZG23A020F512GM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23A020F512GM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23A020F512GM48_Part EFR32ZG23A020F512GM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23A020F512GM48) +#define EFR32ZG23A020F512GM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23A020F512GM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_SE /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23A020F512GM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 11U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x07FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PA_PIN10 1U /**< GPIO pin PA10 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23A020F512GM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM48_Peripheral_TypeDefs EFR32ZG23A020F512GM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_lcd.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_lcdrf.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23A020F512GM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM48_Peripheral_Base EFR32ZG23A020F512GM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define LCD_S_BASE (0x400AC000UL) /* LCD_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define LCD_NS_BASE (0x500AC000UL) /* LCD_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23A020F512GM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM48_Peripheral_Declaration EFR32ZG23A020F512GM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23A020F512GM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23A020F512GM48_Peripheral_Parameters EFR32ZG23A020F512GM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x1UL /**> */ +#define LCD_OCTAPLEX 0x0UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_SEG_NUM 0x14UL /**> None */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23A020F512GM48_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23A020F512GM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h new file mode 100644 index 000000000..6d31c464f --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im40.h @@ -0,0 +1,1456 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23B010F512IM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23B010F512IM40_H +#define EFR32ZG23B010F512IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM40 EFR32ZG23B010F512IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM40_Core EFR32ZG23B010F512IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23B010F512IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23B010F512IM40_Part EFR32ZG23B010F512IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23B010F512IM40) +#define EFR32ZG23B010F512IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23B010F512IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23B010F512IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23B010F512IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM40_Peripheral_TypeDefs EFR32ZG23B010F512IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23B010F512IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM40_Peripheral_Base EFR32ZG23B010F512IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23B010F512IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM40_Peripheral_Declaration EFR32ZG23B010F512IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23B010F512IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM40_Peripheral_Parameters EFR32ZG23B010F512IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23B010F512IM40_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23B010F512IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h new file mode 100644 index 000000000..583532406 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b010f512im48.h @@ -0,0 +1,1553 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23B010F512IM48 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23B010F512IM48_H +#define EFR32ZG23B010F512IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM48 EFR32ZG23B010F512IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + LCD_IRQn = 72, /*!< 72 EFR32 LCD Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM48_Core EFR32ZG23B010F512IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23B010F512IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23B010F512IM48_Part EFR32ZG23B010F512IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23B010F512IM48) +#define EFR32ZG23B010F512IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23B010F512IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23B010F512IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 11U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x07FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PA_PIN10 1U /**< GPIO pin PA10 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23B010F512IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM48_Peripheral_TypeDefs EFR32ZG23B010F512IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_lcd.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_lcdrf.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23B010F512IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM48_Peripheral_Base EFR32ZG23B010F512IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define LCD_S_BASE (0x400AC000UL) /* LCD_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define LCD_NS_BASE (0x500AC000UL) /* LCD_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23B010F512IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM48_Peripheral_Declaration EFR32ZG23B010F512IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23B010F512IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B010F512IM48_Peripheral_Parameters EFR32ZG23B010F512IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x1UL /**> */ +#define LCD_OCTAPLEX 0x0UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_SEG_NUM 0x14UL /**> None */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23B010F512IM48_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23B010F512IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h new file mode 100644 index 000000000..cdc6881e8 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b011f512im40.h @@ -0,0 +1,1453 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23B011F512IM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23B011F512IM40_H +#define EFR32ZG23B011F512IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23B011F512IM40 EFR32ZG23B011F512IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23B011F512IM40_Core EFR32ZG23B011F512IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23B011F512IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23B011F512IM40_Part EFR32ZG23B011F512IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23B011F512IM40) +#define EFR32ZG23B011F512IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23B011F512IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 14 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23B011F512IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 7U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x007FUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 6U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23B011F512IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B011F512IM40_Peripheral_TypeDefs EFR32ZG23B011F512IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23B011F512IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B011F512IM40_Peripheral_Base EFR32ZG23B011F512IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23B011F512IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B011F512IM40_Peripheral_Declaration EFR32ZG23B011F512IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23B011F512IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B011F512IM40_Peripheral_Parameters EFR32ZG23B011F512IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23B011F512IM40_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23B011F512IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h new file mode 100644 index 000000000..1f081c440 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im40.h @@ -0,0 +1,1456 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23B020F512IM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23B020F512IM40_H +#define EFR32ZG23B020F512IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM40 EFR32ZG23B020F512IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM40_Core EFR32ZG23B020F512IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23B020F512IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23B020F512IM40_Part EFR32ZG23B020F512IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23B020F512IM40) +#define EFR32ZG23B020F512IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23B020F512IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23B020F512IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 7U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23B020F512IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM40_Peripheral_TypeDefs EFR32ZG23B020F512IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23B020F512IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM40_Peripheral_Base EFR32ZG23B020F512IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23B020F512IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM40_Peripheral_Declaration EFR32ZG23B020F512IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23B020F512IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM40_Peripheral_Parameters EFR32ZG23B020F512IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23B020F512IM40_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23B020F512IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h new file mode 100644 index 000000000..be86ec9ea --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b020f512im48.h @@ -0,0 +1,1553 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23B020F512IM48 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23B020F512IM48_H +#define EFR32ZG23B020F512IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM48 EFR32ZG23B020F512IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + LCD_IRQn = 72, /*!< 72 EFR32 LCD Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM48_Core EFR32ZG23B020F512IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23B020F512IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23B020F512IM48_Part EFR32ZG23B020F512IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23B020F512IM48) +#define EFR32ZG23B020F512IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23B020F512IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23B020F512IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 11U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x07FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PA_PIN10 1U /**< GPIO pin PA10 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 4U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x000FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LCD_COM0_PORT GPIO_PD_INDEX /**< Port of COM0.*/ +#define LCD_COM0_PIN 2U /**< Pin of COM0.*/ +#define LCD_COM1_PORT GPIO_PD_INDEX /**< Port of COM1.*/ +#define LCD_COM1_PIN 3U /**< Pin of COM1.*/ +#define LCD_COM2_PORT GPIO_PD_INDEX /**< Port of COM2.*/ +#define LCD_COM2_PIN 4U /**< Pin of COM2.*/ +#define LCD_COM3_PORT GPIO_PD_INDEX /**< Port of COM3.*/ +#define LCD_COM3_PIN 5U /**< Pin of COM3.*/ +#define LCD_LCD_CP_PORT GPIO_PA_INDEX /**< Port of LCD_CP.*/ +#define LCD_LCD_CP_PIN 6U /**< Pin of LCD_CP.*/ +#define LCD_SEG0_PORT GPIO_PC_INDEX /**< Port of SEG0.*/ +#define LCD_SEG0_PIN 0U /**< Pin of SEG0.*/ +#define LCD_SEG1_PORT GPIO_PC_INDEX /**< Port of SEG1.*/ +#define LCD_SEG1_PIN 1U /**< Pin of SEG1.*/ +#define LCD_SEG10_PORT GPIO_PA_INDEX /**< Port of SEG10.*/ +#define LCD_SEG10_PIN 4U /**< Pin of SEG10.*/ +#define LCD_SEG11_PORT GPIO_PA_INDEX /**< Port of SEG11.*/ +#define LCD_SEG11_PIN 5U /**< Pin of SEG11.*/ +#define LCD_SEG12_PORT GPIO_PA_INDEX /**< Port of SEG12.*/ +#define LCD_SEG12_PIN 7U /**< Pin of SEG12.*/ +#define LCD_SEG13_PORT GPIO_PA_INDEX /**< Port of SEG13.*/ +#define LCD_SEG13_PIN 8U /**< Pin of SEG13.*/ +#define LCD_SEG14_PORT GPIO_PB_INDEX /**< Port of SEG14.*/ +#define LCD_SEG14_PIN 0U /**< Pin of SEG14.*/ +#define LCD_SEG15_PORT GPIO_PB_INDEX /**< Port of SEG15.*/ +#define LCD_SEG15_PIN 1U /**< Pin of SEG15.*/ +#define LCD_SEG16_PORT GPIO_PB_INDEX /**< Port of SEG16.*/ +#define LCD_SEG16_PIN 2U /**< Pin of SEG16.*/ +#define LCD_SEG17_PORT GPIO_PB_INDEX /**< Port of SEG17.*/ +#define LCD_SEG17_PIN 3U /**< Pin of SEG17.*/ +#define LCD_SEG18_PORT GPIO_PC_INDEX /**< Port of SEG18.*/ +#define LCD_SEG18_PIN 8U /**< Pin of SEG18.*/ +#define LCD_SEG19_PORT GPIO_PC_INDEX /**< Port of SEG19.*/ +#define LCD_SEG19_PIN 9U /**< Pin of SEG19.*/ +#define LCD_SEG2_PORT GPIO_PC_INDEX /**< Port of SEG2.*/ +#define LCD_SEG2_PIN 2U /**< Pin of SEG2.*/ +#define LCD_SEG3_PORT GPIO_PC_INDEX /**< Port of SEG3.*/ +#define LCD_SEG3_PIN 3U /**< Pin of SEG3.*/ +#define LCD_SEG4_PORT GPIO_PC_INDEX /**< Port of SEG4.*/ +#define LCD_SEG4_PIN 4U /**< Pin of SEG4.*/ +#define LCD_SEG5_PORT GPIO_PC_INDEX /**< Port of SEG5.*/ +#define LCD_SEG5_PIN 5U /**< Pin of SEG5.*/ +#define LCD_SEG6_PORT GPIO_PC_INDEX /**< Port of SEG6.*/ +#define LCD_SEG6_PIN 6U /**< Pin of SEG6.*/ +#define LCD_SEG7_PORT GPIO_PC_INDEX /**< Port of SEG7.*/ +#define LCD_SEG7_PIN 7U /**< Pin of SEG7.*/ +#define LCD_SEG8_PORT GPIO_PA_INDEX /**< Port of SEG8.*/ +#define LCD_SEG8_PIN 0U /**< Pin of SEG8.*/ +#define LCD_SEG9_PORT GPIO_PA_INDEX /**< Port of SEG9.*/ +#define LCD_SEG9_PIN 1U /**< Pin of SEG9.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LCD_PRESENT /** LCD is available in this part */ +#define LCD_COUNT 1 /** 1 LCDs available */ +#define LCDRF_PRESENT /** LCDRF is available in this part */ +#define LCDRF_COUNT 1 /** 1 LCDRFs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23B020F512IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM48_Peripheral_TypeDefs EFR32ZG23B020F512IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_lcd.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_lcdrf.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23B020F512IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM48_Peripheral_Base EFR32ZG23B020F512IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define LCD_S_BASE (0x400AC000UL) /* LCD_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define LCDRF_S_BASE (0x400C0000UL) /* LCDRF_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define LCD_NS_BASE (0x500AC000UL) /* LCD_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define LCDRF_NS_BASE (0x500C0000UL) /* LCDRF_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCD_S) && (SL_TRUSTZONE_PERIPHERAL_LCD_S != 0))) +#define LCD_BASE (LCD_S_BASE) /* LCD base address */ +#else +#define LCD_BASE (LCD_NS_BASE) /* LCD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LCDRF_S) && (SL_TRUSTZONE_PERIPHERAL_LCDRF_S != 0))) +#define LCDRF_BASE (LCDRF_S_BASE) /* LCDRF base address */ +#else +#define LCDRF_BASE (LCDRF_NS_BASE) /* LCDRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LCDRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23B020F512IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM48_Peripheral_Declaration EFR32ZG23B020F512IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define LCD_S ((LCD_TypeDef *) LCD_S_BASE) /**< LCD_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define LCDRF_S ((LCDRF_TypeDef *) LCDRF_S_BASE) /**< LCDRF_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define LCD_NS ((LCD_TypeDef *) LCD_NS_BASE) /**< LCD_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define LCDRF_NS ((LCDRF_TypeDef *) LCDRF_NS_BASE) /**< LCDRF_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define LCDRF ((LCDRF_TypeDef *) LCDRF_BASE) /**< LCDRF base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23B020F512IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B020F512IM48_Peripheral_Parameters EFR32ZG23B020F512IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define LCD_COM_NUM 0x4UL /**> None */ +#define LCD_NO_ANIM_LOCS 0x1UL /**> None */ +#define LCD_NO_BANKED_SEG 0x1UL /**> */ +#define LCD_NO_DSC 0x0UL /**> None */ +#define LCD_NO_EXTOSC 0x0UL /**> None */ +#define LCD_NO_UPPER_SEGMENTS 0x1UL /**> */ +#define LCD_OCTAPLEX 0x0UL /**> None */ +#define LCD_SEGASCOM_NUM 0x4UL /**> None */ +#define LCD_SEG_NUM 0x14UL /**> None */ +#define LCD_SEL_WIDTH 0x3UL /**> None */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23B020F512IM48_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23B020F512IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h new file mode 100644 index 000000000..c372fe321 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/efr32zg23b021f512im40.h @@ -0,0 +1,1453 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32ZG23B021F512IM40 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32ZG23B021F512IM40_H +#define EFR32ZG23B021F512IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32ZG23B021F512IM40 EFR32ZG23B021F512IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + SecureFault_IRQn = -9, +#endif + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32ZG23 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + EUSART2_RX_IRQn = 15, /*!< 15 EFR32 EUSART2_RX Interrupt */ + EUSART2_TX_IRQn = 16, /*!< 16 EFR32 EUSART2_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 21, /*!< 21 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 22, /*!< 22 EFR32 LDMA Interrupt */ + LFXO_IRQn = 23, /*!< 23 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 24, /*!< 24 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 25, /*!< 25 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 26, /*!< 26 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 27, /*!< 27 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 28, /*!< 28 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 29, /*!< 29 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 30, /*!< 30 EFR32 EMUDG Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 39, /*!< 39 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 40, /*!< 40 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 41, /*!< 41 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 42, /*!< 42 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 44, /*!< 44 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 45, /*!< 45 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 46, /*!< 46 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 47, /*!< 47 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 48, /*!< 48 EFR32 CMU Interrupt */ + AES_IRQn = 49, /*!< 49 EFR32 AES Interrupt */ + IADC_IRQn = 50, /*!< 50 EFR32 IADC Interrupt */ + MSC_IRQn = 51, /*!< 51 EFR32 MSC Interrupt */ + DPLL0_IRQn = 52, /*!< 52 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 53, /*!< 53 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 54, /*!< 54 EFR32 DCDC Interrupt */ + VDAC_IRQn = 55, /*!< 55 EFR32 VDAC Interrupt */ + PCNT0_IRQn = 56, /*!< 56 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 57, /*!< 57 EFR32 SW0 Interrupt */ + SW1_IRQn = 58, /*!< 58 EFR32 SW1 Interrupt */ + SW2_IRQn = 59, /*!< 59 EFR32 SW2 Interrupt */ + SW3_IRQn = 60, /*!< 60 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 61, /*!< 61 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 62, /*!< 62 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 63, /*!< 63 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 64, /*!< 64 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 65, /*!< 65 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 66, /*!< 66 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 67, /*!< 67 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 68, /*!< 68 EFR32 SEMBTX Interrupt */ + LESENSE_IRQn = 69, /*!< 69 EFR32 LESENSE Interrupt */ + SYSRTC_APP_IRQn = 70, /*!< 70 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 71, /*!< 71 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 73, /*!< 73 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 74, /*!< 74 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 75, /*!< 75 EFR32 RFECA1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32ZG23B021F512IM40_Core EFR32ZG23B021F512IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CORTEXM 1U /**< Core architecture */ +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32ZG23B021F512IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32ZG23B021F512IM40_Part EFR32ZG23B021F512IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32ZG23B021F512IM40) +#define EFR32ZG23B021F512IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32ZG23B021F512IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_ZWAVE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_ZG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_3 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 3 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_210 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE_BASE 3 /** Base */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_SUBGHZ /** Radio type */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio SUBGHZ HP PA output power */ +#define _SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT /** Radio SUBGHZ HP PA is present */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0807FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0807FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00010000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2000FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x11UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00010000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2000FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x11UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32ZG23B021F512IM40 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00010000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 2U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x0003UL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 7U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x007FUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 6U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_EN_PRIMARY_PORT GPIO_PC_INDEX /**< Port of THMSW_EN_PRIMARY.*/ +#define GPIO_THMSW_EN_PRIMARY_PIN 9U /**< Pin of THMSW_EN_PRIMARY.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LESENSE_EN_0_PORT GPIO_PA_INDEX /**< Port of EN_0.*/ +#define LESENSE_EN_0_PIN 3U /**< Pin of EN_0.*/ +#define LESENSE_EN_1_PORT GPIO_PA_INDEX /**< Port of EN_1.*/ +#define LESENSE_EN_1_PIN 4U /**< Pin of EN_1.*/ +#define LESENSE_EN_2_PORT GPIO_PA_INDEX /**< Port of EN_2.*/ +#define LESENSE_EN_2_PIN 5U /**< Pin of EN_2.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 3 /** 3 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LESENSE_PRESENT /** LESENSE is available in this part */ +#define LESENSE_COUNT 1 /** 1 LESENSEs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PFMXPPRF_PRESENT /** PFMXPPRF is available in this part */ +#define PFMXPPRF_COUNT 1 /** 1 PFMXPPRFs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 1 /** 1 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32zg23.h" /* System Header File */ + +/** @} End of group EFR32ZG23B021F512IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B021F512IM40_Peripheral_TypeDefs EFR32ZG23B021F512IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32zg23_scratchpad.h" +#include "efr32zg23_emu.h" +#include "efr32zg23_cmu.h" +#include "efr32zg23_hfrco.h" +#include "efr32zg23_fsrco.h" +#include "efr32zg23_dpll.h" +#include "efr32zg23_lfxo.h" +#include "efr32zg23_lfrco.h" +#include "efr32zg23_ulfrco.h" +#include "efr32zg23_msc.h" +#include "efr32zg23_icache.h" +#include "efr32zg23_prs.h" +#include "efr32zg23_gpio.h" +#include "efr32zg23_ldma.h" +#include "efr32zg23_ldmaxbar.h" +#include "efr32zg23_timer.h" +#include "efr32zg23_usart.h" +#include "efr32zg23_burtc.h" +#include "efr32zg23_i2c.h" +#include "efr32zg23_syscfg.h" +#include "efr32zg23_buram.h" +#include "efr32zg23_gpcrc.h" +#include "efr32zg23_dcdc.h" +#include "efr32zg23_mailbox.h" +#include "efr32zg23_eusart.h" +#include "efr32zg23_sysrtc.h" +#include "efr32zg23_keyscan.h" +#include "efr32zg23_mpahbram.h" +#include "efr32zg23_pfmxpprf.h" +#include "efr32zg23_aes.h" +#include "efr32zg23_smu.h" +#include "efr32zg23_letimer.h" +#include "efr32zg23_iadc.h" +#include "efr32zg23_acmp.h" +#include "efr32zg23_vdac.h" +#include "efr32zg23_pcnt.h" +#include "efr32zg23_lesense.h" +#include "efr32zg23_hfxo.h" +#include "efr32zg23_wdog.h" +#include "efr32zg23_semailbox.h" +#include "efr32zg23_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32zg23_prs_signals.h" +#include "efr32zg23_dma_descriptor.h" +#include "efr32zg23_ldmaxbar_defines.h" + +/** @} End of group EFR32ZG23B021F512IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B021F512IM40_Peripheral_Base EFR32ZG23B021F512IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define EUSART2_S_BASE (0x400A4000UL) /* EUSART2_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define PFMXPPRF_S_BASE (0x400C4000UL) /* PFMXPPRF_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define LESENSE_S_BASE (0x49038000UL) /* LESENSE_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define EUSART2_NS_BASE (0x500A4000UL) /* EUSART2_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define PFMXPPRF_NS_BASE (0x500C4000UL) /* PFMXPPRF_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define LESENSE_NS_BASE (0x59038000UL) /* LESENSE_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART2_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART2_S != 0))) +#define EUSART2_BASE (EUSART2_S_BASE) /* EUSART2 base address */ +#else +#define EUSART2_BASE (EUSART2_NS_BASE) /* EUSART2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S) && (SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S != 0))) +#define PFMXPPRF_BASE (PFMXPPRF_S_BASE) /* PFMXPPRF base address */ +#else +#define PFMXPPRF_BASE (PFMXPPRF_NS_BASE) /* PFMXPPRF base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PFMXPPRF_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LESENSE_S) && (SL_TRUSTZONE_PERIPHERAL_LESENSE_S != 0))) +#define LESENSE_BASE (LESENSE_S_BASE) /* LESENSE base address */ +#else +#define LESENSE_BASE (LESENSE_NS_BASE) /* LESENSE base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LESENSE_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32ZG23B021F512IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B021F512IM40_Peripheral_Declaration EFR32ZG23B021F512IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define EUSART2_S ((EUSART_TypeDef *) EUSART2_S_BASE) /**< EUSART2_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define PFMXPPRF_S ((PFMXPPRF_TypeDef *) PFMXPPRF_S_BASE) /**< PFMXPPRF_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define LESENSE_S ((LESENSE_TypeDef *) LESENSE_S_BASE) /**< LESENSE_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define EUSART2_NS ((EUSART_TypeDef *) EUSART2_NS_BASE) /**< EUSART2_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define PFMXPPRF_NS ((PFMXPPRF_TypeDef *) PFMXPPRF_NS_BASE) /**< PFMXPPRF_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define LESENSE_NS ((LESENSE_TypeDef *) LESENSE_NS_BASE) /**< LESENSE_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define EUSART2 ((EUSART_TypeDef *) EUSART2_BASE) /**< EUSART2 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define PFMXPPRF ((PFMXPPRF_TypeDef *) PFMXPPRF_BASE) /**< PFMXPPRF base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32ZG23B021F512IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32ZG23B021F512IM40_Peripheral_Parameters EFR32ZG23B021F512IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x14UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x14UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0x50UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x2000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x2000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x2000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x2000UL /**> Bank7 size */ +#define DMEM_NUM_BANKS 0x4UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x2UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x1UL /**> Boolean indicating if NUM_PORTS=2 */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x80000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_COMALLOC_WIDTH 0x4UL /**> New Param */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x6UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x4UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xBUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x3UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x7UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x7UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SEGALLOC_WIDTH 0x14UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x38UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define EUSART2_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART2_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define PFMXPPRF_COUNT_WIDTH 0x9UL /**> Width of counters for pulse-pairing */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x7UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x39UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x19UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x19UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_CHANNEL_NUM 0x10UL /**> None */ +#define LESENSE_RIPCNT_WIDTH 0x10UL /**> None */ +#define LESENSE_STATE_NUM 0x20UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : ((n) == 2) ? EUSART2 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : ((ref) == EUSART2) ? 2 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : ((n) == 2) ? EUSART2_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32ZG23B021F512IM40_Peripheral_Parameters */ + +/** @} End of group EFR32ZG23B021F512IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h new file mode 100644 index 000000000..5d395cdd8 --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/em_device.h @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H +#if defined(EFR32ZG23A010F512GM40) +#include "efr32zg23a010f512gm40.h" + +#elif defined(EFR32ZG23A010F512GM48) +#include "efr32zg23a010f512gm48.h" + +#elif defined(EFR32ZG23A020F512GM40) +#include "efr32zg23a020f512gm40.h" + +#elif defined(EFR32ZG23A020F512GM48) +#include "efr32zg23a020f512gm48.h" + +#elif defined(EFR32ZG23B010F512IM40) +#include "efr32zg23b010f512im40.h" + +#elif defined(EFR32ZG23B010F512IM48) +#include "efr32zg23b010f512im48.h" + +#elif defined(EFR32ZG23B011F512IM40) +#include "efr32zg23b011f512im40.h" + +#elif defined(EFR32ZG23B020F512IM40) +#include "efr32zg23b020f512im40.h" + +#elif defined(EFR32ZG23B020F512IM48) +#include "efr32zg23b020f512im48.h" + +#elif defined(EFR32ZG23B021F512IM40) +#include "efr32zg23b021f512im40.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif + +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif + +#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif +#endif /* EM_DEVICE_H */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h new file mode 100644 index 000000000..f1c27aeed --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/system_efr32zg23.h @@ -0,0 +1,255 @@ +/**************************************************************************//** + * @file + * @brief CMSIS system header file for EFR32ZG23 + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32ZG23_H +#define SYSTEM_EFR32ZG23_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "sl_code_classification.h" + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFR32ZG23 EFR32ZG23 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ +#endif + +/*Re-direction of IRQn.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn +#else +#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn +#endif /* SL_TRUSTZONE_SECURE */ + +/*Re-direction of IRQHandler.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler +#else +#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler +#endif /* SL_TRUSTZONE_SECURE */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SecureFault_Handler(void); /**< Secure Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +/* Part Specific Interrupts */ +void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ +void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ +void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ +void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ +void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ +void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ +void EUSART2_RX_IRQHandler(void); /**< EUSART2_RX IRQ Handler */ +void EUSART2_TX_IRQHandler(void); /**< EUSART2_TX IRQ Handler */ +void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ +void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ +void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ +void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ +void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ +void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ +void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ +void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void AES_IRQHandler(void); /**< AES IRQ Handler */ +void IADC_IRQHandler(void); /**< IADC IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ +void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ +void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ +void VDAC_IRQHandler(void); /**< VDAC IRQ Handler */ +void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ +void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ +void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ +void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ +void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ +void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ +void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ +void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ +void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ +void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ +void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */ +void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */ +void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */ +void LESENSE_IRQHandler(void); /**< LESENSE IRQ Handler */ +void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */ +void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */ +void LCD_IRQHandler(void); /**< LCD IRQ Handler */ +void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */ +void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */ +void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */ + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ +#endif + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHCLKGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE uint32_t SystemCoreClockGet(void) +{ + return SystemHCLKGet(); +} + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemHCLKGet(); +} + +void SystemInit(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFRCODPLLClockGet(void); +void SystemHFRCODPLLClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemSYSCLKGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemMaxCoreClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemFSRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemCLKIN0Get(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemHFRCOEM23ClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemLFRCOClockGet(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SYSTEM, SL_CODE_CLASS_TIME_CRITICAL) +uint32_t SystemULFRCOClockGet(void); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32ZG23_H */ diff --git a/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c new file mode 100644 index 000000000..83e9fc2fe --- /dev/null +++ b/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Source/system_efr32zg23.c @@ -0,0 +1,667 @@ +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M33 system support for EFR32ZG23 devices. + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_CLOCK_MANAGER_PRESENT) +#include "sl_clock_manager_oscillator_config.h" + +#endif + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +// System oscillator frequencies. These frequencies are normally constant +// for a target, but they are made configurable in order to allow run-time +// handling of different boards. The crystal oscillator clocks can be set +// compile time to a non-default value by defining respective nFXO_FREQ +// values according to board design. By defining the nFXO_FREQ to 0, +// one indicates that the oscillator is not present, in order to save some +// SW footprint. + +#if !defined(FSRCO_FREQ) +// FSRCO frequency +#define FSRCO_FREQ (20000000UL) +#endif + +#if !defined(HFXO_FREQ) +// HFXO frequency +#define HFXO_FREQ (39000000UL) +#endif + +#if !defined(HFRCODPLL_STARTUP_FREQ) +// HFRCODPLL startup frequency +#define HFRCODPLL_STARTUP_FREQ (19000000UL) +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +// Maximum HFRCODPLL frequency +#define HFRCODPLL_MAX_FREQ (80000000UL) +#endif + +// CLKIN0 input +#if defined(SL_CLOCK_MANAGER_CLKIN0_FREQ) +// Clock Manager takes control of this define when present. +#define CLKIN0_FREQ (SL_CLOCK_MANAGER_CLKIN0_FREQ) +#elif !defined(CLKIN0_FREQ) +#define CLKIN0_FREQ (0UL) +#endif + +#if !defined(LFRCO_MAX_FREQ) +// LFRCO frequency, tuned to below frequency during manufacturing. +#define LFRCO_FREQ (32768UL) +#endif + +#if !defined(ULFRCO_FREQ) +// ULFRCO frequency +#define ULFRCO_FREQ (1000UL) +#endif + +#if !defined(LFXO_FREQ) +// LFXO frequency +#define LFXO_FREQ (LFRCO_FREQ) +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// NOTE: Gecko bootloaders can't have static variable allocation. +// System HFXO clock frequency +static uint32_t SystemHFXOClock = HFXO_FREQ; +#endif + +#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// System LFXO clock frequency +static uint32_t SystemLFXOClock = LFXO_FREQ; +#endif + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +// System HFRCODPLL clock frequency +static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; + +#endif + +/*--------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *---------------------------------------------------------------------------*/ +extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if (__FPU_PRESENT == 1) + SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ + | (3U << 11U * 2U)); /* set CP11 Full Access */ +#endif + +/* Secure app takes care of moving between the security states. + * SL_TRUSTZONE_SECURE MACRO is for secure access. + * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. + * When both the MACROS are not defined, during start-up below code makes sure + * that all the peripherals are accessed from non-secure address except SMU, + * as SMU is used to configure the trustzone state of the system. */ +#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ + && defined(__TZ_PRESENT) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; + + // config SMU to Secure and other peripherals to Non-Secure. + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; +#if defined (SEMAILBOX_PRESENT) + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); +#else + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); +#endif + + // SAU treats all accesses as non-secure +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + __DSB(); + __ISB(); +#else + #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." +#endif // __ARM_FEATURE_CMSE + +// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +#endif //SL_TRUSTZONE_SECURE +} + +/**************************************************************************//** + * @brief + * Get current HFRCODPLL frequency. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCODPLLClockGet(void) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + return SystemHFRCODPLLClock; +#else + uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +#endif +} + +/**************************************************************************//** + * @brief + * Set HFRCODPLL frequency value. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +void SystemHFRCODPLLClockSet(uint32_t freq) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFRCODPLLClock = freq; +#else + (void) freq; // Unused parameter +#endif +} + +/***************************************************************************//** + * @brief + * Get the current system clock frequency (SYSCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * hardware configuration. + * + * @note + * This is an EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * Current system clock (SYSCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemSYSCLKGet(void) +{ + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: +#if defined(SYSTEM_NO_STATIC_MEMORY) + ret = HFXO_FREQ; +#else + ret = SystemHFXOClock; +#endif + break; +#endif + +#if (CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = FSRCO_FREQ; + break; + + default: + // Unknown clock source. + while (1) { + } + } + return ret; +} + +/***************************************************************************//** + * @brief + * Get the current system core clock frequency (HCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * The current core clock (HCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemHCLKGet(void) +{ + uint32_t presc, ret; + + ret = SystemSYSCLKGet(); + + presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; + + ret /= presc + 1U; + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + // Keep CMSIS system clock variable up-to-date + SystemCoreClock = ret; +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ + ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + // The external crystal oscillator is not present if HFXO_FREQ==0 +#if (HFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return HFXO_FREQ; +#else + return SystemHFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFXOClock = freq; + + // Update core clock frequency if HFXO is used to clock core + if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) + == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { + // This function will update the global variable + SystemHCLKGet(); + } +#else + (void) freq; // Unused parameter +#endif +} + +/**************************************************************************//** + * @brief + * Get current CLKIN0 frequency. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * CLKIN0 frequency in Hz. + *****************************************************************************/ +uint32_t SystemCLKIN0Get(void) +{ + return CLKIN0_FREQ; +} + +/**************************************************************************//** + * @brief + * Get FSRCO frequency. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * FSRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemFSRCOClockGet(void) +{ + return FSRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get current HFRCOEM23 frequency. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCOEM23 frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCOEM23ClockGet(void) +{ + uint32_t ret = 0UL; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; + + // Get oscillator frequency band + switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCOEM23->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 40000000UL; + break; + + default: + break; + } + return ret; +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + return LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + // The ULFRCO frequency is not tuned, and can be very inaccurate + return ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + // External crystal present? +#if (LFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return LFXO_FREQ; +#else + return SystemLFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32ZG23 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemLFXOClock = freq; +#else + (void) freq; // Unused parameter +#endif +} diff --git a/simplicity_sdk/platform/common/inc/sl_cmsis_os2_common.h b/simplicity_sdk/platform/common/inc/sl_cmsis_os2_common.h index 1673b5d1b..781c8af92 100644 --- a/simplicity_sdk/platform/common/inc/sl_cmsis_os2_common.h +++ b/simplicity_sdk/platform/common/inc/sl_cmsis_os2_common.h @@ -33,6 +33,8 @@ #define SL_CMSIS_OS2_COMMON_H #include +#include "cmsis_os2.h" +#include "sl_status.h" #if defined(SL_COMPONENT_CATALOG_PRESENT) #include "sl_component_catalog.h" @@ -47,10 +49,6 @@ #include "FreeRTOS.h" #elif defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) #include "os.h" -#if (CMSIS_RTOS2_TIMER_TASK_EN == DEF_ENABLED) -// needed for osTimer_t struct -#include "cmsis_os2.h" -#endif #endif #if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) @@ -175,7 +173,28 @@ typedef struct { #endif #define osAlignment sizeof(CPU_ALIGN) - #endif // SL_CATALOG_MICRIUMOS_KERNEL_PRESENT +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************************************** + * sl_cmsis_os_convert_status() + * + * @brief Convert OsStatus from CMSIS-RTOS2 to sl_status type. + * + * @param os_status The OS status code returned by CMSIS-RTOS2 API. + * + * @return Status code converted to sl_status. + *******************************************************************************************************/ +sl_status_t sl_cmsis_os_convert_status(osStatus_t os_status); + +#ifdef __cplusplus +} +#endif + #endif // SL_CMSIS_OS2_COMMON_H diff --git a/simplicity_sdk/platform/common/inc/sl_code_classification.h b/simplicity_sdk/platform/common/inc/sl_code_classification.h index fa78bf375..04e9d218d 100644 --- a/simplicity_sdk/platform/common/inc/sl_code_classification.h +++ b/simplicity_sdk/platform/common/inc/sl_code_classification.h @@ -51,7 +51,7 @@ /// Prepend a function definition with this macro to place it in RAM. #define SL_CODE_RAM \ - __attribute__((section(".ramfunc"))) + __attribute__((section("text_application_ram"))) #elif defined(__ICCARM__) diff --git a/simplicity_sdk/platform/common/inc/sl_common.h b/simplicity_sdk/platform/common/inc/sl_common.h index 9ccd8fc9d..b48503be5 100644 --- a/simplicity_sdk/platform/common/inc/sl_common.h +++ b/simplicity_sdk/platform/common/inc/sl_common.h @@ -393,6 +393,24 @@ __STATIC_INLINE uint32_t SL_Log2ToDiv(uint32_t log2) return 1UL << log2; } +/***************************************************************************//** + * @brief + * Count the number of bits that are set to 1 in a 32-bit bitfield. + * + * @param[in] bitfield + * 32-bit bitfield. + * + * @return + * The number of bits that are set to 1 in the bitfield. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_POPCOUNT32(uint32_t bitfield) +{ + bitfield = bitfield - ((bitfield >> 1) & 0x55555555); + bitfield = (bitfield & 0x33333333) + ((bitfield >> 2) & 0x33333333); + bitfield = (bitfield + (bitfield >> 4)) & 0x0F0F0F0F; + return (bitfield * 0x01010101) >> 24; +} + /** @} (end addtogroup common) */ #ifdef __cplusplus diff --git a/simplicity_sdk/platform/common/inc/sl_compiler.h b/simplicity_sdk/platform/common/inc/sl_compiler.h new file mode 100644 index 000000000..74f2e8787 --- /dev/null +++ b/simplicity_sdk/platform/common/inc/sl_compiler.h @@ -0,0 +1,210 @@ +/***************************************************************************//** + * @file + * @brief Silabs Compiler definitions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_COMPILER_H +#define SL_COMPILER_H + +/***************************************************************************//** + * @addtogroup compiler Compiler definitions + * @brief Compiler definitions + * @{ + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__GNUC__) + +// Fallback for __has_builtin. + #ifndef __has_builtin + #define __has_builtin(x) (0) + #endif + +// Compiler specific defines. + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + +#elif defined(__IAR_SYSTEMS_ICC__) + + #pragma system_include + + #if (__VER__ >= 8000000) + #define __ICCARM_V8 1 + #else + #define __ICCARM_V8 0 + #endif + + #ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #endif + + #ifndef __ASM + #define __ASM __asm + #endif + + #ifndef __INLINE + #define __INLINE inline + #endif + + #ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif + #endif + + #ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else +/* Needs IAR language extensions */ + #define __PACKED __packed + #endif + #endif + + #ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else +/* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif + #endif + + #ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else +/* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif + #endif + + #ifndef __RESTRICT + #define __RESTRICT restrict + #endif + + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + + #ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") + #endif + + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE + #endif + + #ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif + #endif + + #ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif + #endif + +#else + #error "Unknown compiler." +#endif + +// IO definitions (access restrictions to peripheral registers). +#ifdef __cplusplus + #define __I volatile ///< Defines 'read only' permissions +#else + #define __I volatile const ///< Defines 'read only' permissions +#endif +#define __O volatile ///< Defines 'write only' permissions +#define __IO volatile ///< Defines 'read / write' permissions + +// The following defines should be used for structure members. +#define __IM volatile const ///< Defines 'read only' structure member permissions +#define __OM volatile ///< Defines 'write only' structure member permissions +#define __IOM volatile ///< Defines 'read / write' structure member permissions + +#ifdef __cplusplus +} +#endif + +/** @} (end group compiler) */ + +#endif // SL_COMPILER_H diff --git a/simplicity_sdk/platform/common/inc/sl_core.h b/simplicity_sdk/platform/common/inc/sl_core.h index fb8f923b9..a52562e7b 100644 --- a/simplicity_sdk/platform/common/inc/sl_core.h +++ b/simplicity_sdk/platform/common/inc/sl_core.h @@ -271,6 +271,9 @@ extern "C" { /// Check if inside an IRQ handler. #define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext() +// Reset System. +#define CORE_RESET_SYSTEM() CORE_ResetSystem() + /******************************************************************************* ************************* TYPEDEFS **************************************** ******************************************************************************/ @@ -481,6 +484,12 @@ void CORE_clear_max_time_critical_section(void); SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CORE, SL_CODE_CLASS_TIME_CRITICAL) void CORE_clear_max_time_atomic_section(void); +/***************************************************************************//** + * @brief + * Reset chip routine. + ******************************************************************************/ +void CORE_ResetSystem(void); + /** @} (end addtogroup sl_core) */ #ifdef __cplusplus diff --git a/simplicity_sdk/platform/common/inc/sl_event_system.h b/simplicity_sdk/platform/common/inc/sl_event_system.h index d6d8cea63..4dff8aaf6 100644 --- a/simplicity_sdk/platform/common/inc/sl_event_system.h +++ b/simplicity_sdk/platform/common/inc/sl_event_system.h @@ -99,6 +99,7 @@ SL_ENUM(sl_event_class_t) { SL_EVENT_CLASS_IRQ, SL_EVENT_CLASS_BLUETOOTH, SL_EVENT_CLASS_ZIGBEE, + SL_EVENT_CLASS_BLUETOOTH_MESH, SL_EVENT_CLASS_MAX, }; @@ -114,12 +115,14 @@ typedef struct { sl_event_free_data_cb_t free_data_callback; uint8_t subscriber_count; sl_slist_node_t *subscribers; + bool is_registered; } sl_event_publisher_t; typedef struct { - sl_event_publisher_t *publisher; - uint8_t reference_count; - void* event_data; + sl_event_free_data_cb_t free_data_callback; + uint8_t reference_count; + void* event_data; + bool pre_allocated; } sl_event_t; /******************************************************************************* @@ -151,6 +154,22 @@ sl_status_t sl_event_publisher_register(sl_event_publisher_t *publisher, sl_event_class_t event_class, sl_event_free_data_cb_t free_data_callback); +/******************************************************************************* + * @brief + * Unregister a publisher context from its event class. + * + * @description + * When a publisher context is unregistered, it can no longer publish messages + * until it is registered again. After a publisher context is unregistered, the + * event class it was registered with can be reused. + * + * @param[in] publisher Pointer to a publisher context. + * + * @return + * SL_STATUS_OK if successful, otherwise an error code is returned. + ******************************************************************************/ +sl_status_t sl_event_publisher_unregister(sl_event_publisher_t *publisher); + /******************************************************************************* * @brief * Publish an event, with data, within the event class of the publisher. @@ -168,6 +187,26 @@ sl_status_t sl_event_publish(sl_event_publisher_t *publisher, uint8_t event_prio, void *event_data); +/******************************************************************************* + * @brief + * Publish an event, with data, with a pre-allocated event handle, within the + * event class of the publisher. + * + * @param[in] publisher Pointer to a publisher context. + * @param[in] event_mask Event mask corresponding to the type of event. + * @param[in] event_prio The priority of the event published. + * @param[in] event The pre-allocated event structure handle + * @param[in] event_data The event data. + * + * @return + * SL_STATUS_OK if successful, otherwise an error code is returned. + ******************************************************************************/ +sl_status_t sl_event_publish_static(sl_event_publisher_t *publisher, + uint32_t event_mask, + uint8_t event_prio, + sl_event_t* event, + void *event_data); + /******************************************************************************* * @brief * Subscribe to one or more events for a given event class. @@ -186,6 +225,25 @@ sl_status_t sl_event_subscribe(sl_event_class_t event_class, uint32_t event_mask, sl_event_queue_t event_queue); +/******************************************************************************* + * @brief + * Unsubscribe from one or more events for a given event class. + * + * @description + * The unsubscribed event(s) will no longer be placed in the queue identified + * by event_queue. + * + * @param[in] event_class The class of events to subscribe to. + * @param[in] event_mask The event(s) to subscribe to. + * @param[in] event_queue The identifier of an event queue. + * + * @return + * SL_STATUS_OK if successful, otherwise an error code is returned. + ******************************************************************************/ +sl_status_t sl_event_unsubscribe(sl_event_class_t event_class, + uint32_t event_mask, + sl_event_queue_t event_queue); + /******************************************************************************* * @brief * Signal to the event system that a subscriber has processed an event. @@ -215,6 +273,21 @@ sl_status_t sl_event_process(sl_event_t **event); sl_status_t sl_event_queue_create(uint32_t event_count, sl_event_queue_t *event_queue); +/******************************************************************************* + * @brief + * Delete an event queue. + * + * @param[in] event_queue The event queue to delete. + * + * @return + * SL_STATUS_OK if successful, otherwise an error code is returned. + * + * @note + * In the process of deleting an event queue, all events that the queue + * was subscribed to will be unsubscribed from. + ******************************************************************************/ +sl_status_t sl_event_queue_delete(sl_event_queue_t event_queue); + /******************************************************************************* * @brief * Get an event from an event queue. @@ -252,6 +325,58 @@ size_t sl_event_publisher_get_size(void); ******************************************************************************/ sl_status_t sl_event_publisher_alloc(sl_event_publisher_t **publisher); +/******************************************************************************* + * @brief + * Free a publisher context structure from the heap, as well as its list of + * subscriber entries using the common memory manager. + * + * @description + * Using this function to free a publisher context will also free its list of + * subscribers, which will cause subscribers to no longer receive events from + * the publisher context's event class. + * + * @param[in] publisher address of a pointer to a publisher context + * + * @return + * SL_STATUS_OK if successful, otherwise an error code is returned. + ******************************************************************************/ +sl_status_t sl_event_publisher_free(sl_event_publisher_t *publisher); + +/******************************************************************************* + * @brief + * Get the size of the event structure. + * + * @return Size of the event structure. + ******************************************************************************/ +size_t sl_event_get_size(void); + +/******************************************************************************* + * @brief + * Allocate the event structure to the heap using the common memory + * manager with a long-term lifespan. + * + * @param[in] event address of a pointer to an event struct + * + * @return + * SL_STATUS_OK if successful, otherwise an error code is returned. + ******************************************************************************/ +sl_status_t sl_event_alloc(sl_event_t **event); + +/******************************************************************************* + * @brief + * Free an event structure from the heap using the common memory manager. + * + * @note + * Freeing an event structure that has not yet been processed by all + * subscribers will + * + * @param[in] event address of a pointer to an event struct + * + * @return + * SL_STATUS_OK if successful, otherwise an error code is returned. + ******************************************************************************/ +sl_status_t sl_event_free(sl_event_t *event); + /** @} (end addtogroup event-system) */ #ifdef __cplusplus diff --git a/simplicity_sdk/platform/common/inc/sl_platform_version.h b/simplicity_sdk/platform/common/inc/sl_platform_version.h index d68064885..bc2438943 100644 --- a/simplicity_sdk/platform/common/inc/sl_platform_version.h +++ b/simplicity_sdk/platform/common/inc/sl_platform_version.h @@ -31,8 +31,8 @@ #define SL_PLATFORM_VERSION_H #define SL_PLATFORM_MAJOR_VERSION 5 -#define SL_PLATFORM_MINOR_VERSION 0 -#define SL_PLATFORM_PATCH_VERSION 2 +#define SL_PLATFORM_MINOR_VERSION 1 +#define SL_PLATFORM_PATCH_VERSION 0 #define SL_PLATFORM_VERSION ((SL_PLATFORM_MAJOR_VERSION << 8) \ | (SL_PLATFORM_MINOR_VERSION << 4) \ diff --git a/simplicity_sdk/platform/common/inc/sl_slist.h b/simplicity_sdk/platform/common/inc/sl_slist.h index de785fe30..bcbd30100 100644 --- a/simplicity_sdk/platform/common/inc/sl_slist.h +++ b/simplicity_sdk/platform/common/inc/sl_slist.h @@ -118,6 +118,18 @@ sl_slist_node_t *sl_slist_pop(sl_slist_node_t **head); void sl_slist_insert(sl_slist_node_t *item, sl_slist_node_t *pos); +/******************************************************************************* + * Join two lists together. + * + * @param head_list_1 Pointer to the pointer of a head element of the list. + * + * @param head_list_2 Pointer to the pointer of a head element of the list + * to be appended. After the call, this pointer will be + * invalidated (set to NULL). + ******************************************************************************/ +void sl_slist_join(sl_slist_node_t **head_list_1, + sl_slist_node_t **head_list_2); + /******************************************************************************* * Remove an item from the list. * diff --git a/simplicity_sdk/platform/common/inc/sl_status.h b/simplicity_sdk/platform/common/inc/sl_status.h index bfd2d2f31..f89704d13 100644 --- a/simplicity_sdk/platform/common/inc/sl_status.h +++ b/simplicity_sdk/platform/common/inc/sl_status.h @@ -202,6 +202,28 @@ #define SL_STATUS_NVM3_PAGE_SIZE_NOT_SUPPORTED ((sl_status_t)0x005B) ///< The initialization was aborted as the NVM3 page size is not supported #define SL_STATUS_NVM3_TOKEN_INIT_FAILED ((sl_status_t)0x005C) ///< The application that there was an error initializing some of the tokens #define SL_STATUS_NVM3_OPENED_WITH_OTHER_PARAMETERS ((sl_status_t)0x005D) ///< The initialization was aborted as the NVM3 instance was already opened with other parameters +#define SL_STATUS_NVM3_NO_VALID_PAGES ((sl_status_t)0x005E) ///< Initialization aborted, no valid page found +#define SL_STATUS_NVM3_OBJECT_SIZE_NOT_SUPPORTED ((sl_status_t)0x005F) ///< The object size is not supported +#define SL_STATUS_NVM3_OBJECT_IS_NOT_DATA ((sl_status_t)0x0060) ///< Trying to access a data object which is currently a counter object +#define SL_STATUS_NVM3_OBJECT_IS_NOT_A_COUNTER ((sl_status_t)0x0061) ///< Trying to access a counter object which is currently a data object +#define SL_STATUS_NVM3_WRITE_DATA_SIZE ((sl_status_t)0x0062) ///< The object is too large +#define SL_STATUS_NVM3_READ_DATA_SIZE ((sl_status_t)0x0063) ///< Trying to read with a length different from actual object size +#define SL_STATUS_NVM3_INIT_WITH_FULL_NVM ((sl_status_t)0x0064) ///< The module was opened with a full NVM +#define SL_STATUS_NVM3_RESIZE_PARAMETER ((sl_status_t)0x0065) ///< Illegal parameter +#define SL_STATUS_NVM3_RESIZE_NOT_ENOUGH_SPACE ((sl_status_t)0x0066) ///< Not enough NVM to complete resize +#define SL_STATUS_NVM3_ERASE_COUNT_ERROR ((sl_status_t)0x0067) ///< Erase counts are not valid +#define SL_STATUS_NVM3_NVM_ACCESS ((sl_status_t)0x0068) ///< A NVM function call was failing +#define SL_STATUS_NVM3_CRYPTO_INIT_FAILED ((sl_status_t)0x0069) ///< Crypto initialization failed +#define SL_STATUS_NVM3_ENCRYPTION_KEY_ERROR ((sl_status_t)0x006A) ///< Error in obtaining encryption key +#define SL_STATUS_NVM3_RANDOM_NUM_GENERATION_FAILED ((sl_status_t)0x006B) ///< Error in obtaining random number +#define SL_STATUS_NVM3_ENCRYPTION_FAILED ((sl_status_t)0x006C) ///< Encryption failed +#define SL_STATUS_NVM3_WRITE_TO_NOT_ERASED ((sl_status_t)0x006D) ///< Write to memory that is not erased +#define SL_STATUS_NVM3_INVALID_ADDR ((sl_status_t)0x006E) ///< Invalid NVM address +#define SL_STATUS_NVM3_KEY_MISMATCH ((sl_status_t)0x006F) ///< Key validation failure +#define SL_STATUS_NVM3_SIZE_ERROR ((sl_status_t)0x0070) ///< Size mismatch error +#define SL_STATUS_NVM3_EMULATOR ((sl_status_t)0x0071) ///< Emulator error +#define SL_STATUS_NVM3_SECURITY_INIT_FAILED ((sl_status_t)0x0072) ///< Security init failed +#define SL_STATUS_NVM3_GET_REGION_LOCATION_FAILED ((sl_status_t)0x0073) ///< Get data region location failed // Bluetooth status codes #define SL_STATUS_BT_OUT_OF_BONDS ((sl_status_t)0x0402) ///< Bonding procedure can't be started because device has no space left for bond. @@ -251,6 +273,7 @@ #define SL_STATUS_BT_CTRL_REPEATED_ATTEMPTS ((sl_status_t)0x1017) ///< The Controller is disallowing an authentication or pairing procedure because too little time has elapsed since the last authentication or pairing attempt failed. #define SL_STATUS_BT_CTRL_PAIRING_NOT_ALLOWED ((sl_status_t)0x1018) ///< The device does not allow pairing. This can be for example, when a device only allows pairing during a certain time window after some user input allows pairing #define SL_STATUS_BT_CTRL_UNSUPPORTED_REMOTE_FEATURE ((sl_status_t)0x101A) ///< The remote device does not support the feature associated with the issued command. +#define SL_STATUS_BT_CTRL_INVALID_LL_PARAMETERS ((sl_status_t)0x101E) ///< Indicates that some LMP PDU / LL Control PDU parameters were invalid #define SL_STATUS_BT_CTRL_UNSPECIFIED_ERROR ((sl_status_t)0x101F) ///< No other error code specified is appropriate to use. #define SL_STATUS_BT_CTRL_LL_RESPONSE_TIMEOUT ((sl_status_t)0x1022) ///< Connection terminated due to link-layer procedure timeout. #define SL_STATUS_BT_CTRL_LL_PROCEDURE_COLLISION ((sl_status_t)0x1023) ///< LL procedure has collided with the same transaction or procedure that is already in progress. @@ -278,6 +301,7 @@ #define SL_STATUS_BT_CTRL_PACKET_TOO_LONG ((sl_status_t)0x1045) ///< An attempt was made to send or receive a packet that exceeds the maximum allowed packet length. #define SL_STATUS_BT_CTRL_TOO_LATE ((sl_status_t)0x1046) ///< Information was provided too late to the controller. #define SL_STATUS_BT_CTRL_TOO_EARLY ((sl_status_t)0x1047) ///< Information was provided too early to the controller. +#define SL_STATUS_BT_CTRL_INSUFFICIENT_CHANNELS ((sl_status_t)0x1048) ///< Indicates that the result of the requested operation would yield too few physical channels. // Bluetooth attribute status codes #define SL_STATUS_BT_ATT_INVALID_HANDLE ((sl_status_t)0x1101) ///< The attribute handle given was not valid on this server diff --git a/simplicity_sdk/platform/common/inc/sli_code_classification.h b/simplicity_sdk/platform/common/inc/sli_code_classification.h index 924b42bc8..f4729c682 100644 --- a/simplicity_sdk/platform/common/inc/sli_code_classification.h +++ b/simplicity_sdk/platform/common/inc/sli_code_classification.h @@ -52,23 +52,40 @@ // appended with an identifier generated from __COUNTER__ and __LINE__ so that // functions are more likely to be separated into unique sections. Doing this // allows the linker to discard unused functions with more granularity. -#if defined(__GNUC__) && !defined(__llvm__) +#if defined(__GNUC__) && !(defined(__llvm__) || defined(SLI_CODE_CLASSIFICATION_DISABLE)) // With GCC, __attribute__ can be used to specify the input section of // functions. #define _SL_CC_SECTION(section_name, count, line) \ __attribute__((section(_SL_CC_CONCAT3(_SL_CC_XSTRINGIZE(section_name), _SL_CC_XSTRINGIZE(count), _SL_CC_XSTRINGIZE(line))))) -#elif defined(__ICCARM__) +#elif defined(__ICCARM__) && !defined(SLI_CODE_CLASSIFICATION_DISABLE) // With IAR, _Pragma can be used to specify the input section of // functions. #define _SL_CC_SECTION(section_name, count, line) \ _Pragma(_SL_CC_XSTRINGIZE(_SL_CC_CONCAT4(location =, _SL_CC_XSTRINGIZE(section_name), _SL_CC_XSTRINGIZE(count), _SL_CC_XSTRINGIZE(line)))) -#elif defined(__llvm__) +#elif defined(__llvm__) && !defined(SLI_CODE_CLASSIFICATION_DISABLE) -#define _SL_CC_SECTION(section_name) +// With llvm, __attribute__ can be used to specify the input section of +// functions. + +// However the syntax of the string within the section directive is +// dependent on the specifics of the target backend (e.g. osx) +#if defined(__MACH__) && defined(SLI_CODE_CLASSIFICATION_OSX_ENABLE) +// code classifcation is not supported on OSX and can have weird +// interactions for executable code so it is disabled by default +// since it can be useful for code analysis allow it as an opt-in feature +#define _SL_CC_SECTION(section_name, count, line) \ + __attribute__((section("sl_cc,code_class" _SL_CC_XSTRINGIZE(count) _SL_CC_XSTRINGIZE(line)))) +#else +#define _SL_CC_SECTION(section_name, count, line) +#endif // defined(__MACH__) + +#elif defined(SLI_CODE_CLASSIFICATION_DISABLE) + +#define _SL_CC_SECTION(section_name, count, line) #else #error "(sli_code_classification.h): Code classification does not support \ @@ -108,12 +125,7 @@ /******************************************************************************/ // Variadic macro to specify the code class membership of a function. -#if defined(SL_CODE_CLASSIFY) -#undef SL_CODE_CLASSIFY #define SL_CODE_CLASSIFY(component, ...) \ _SL_CC_IDENTITY(_SL_CC_APPLY(_SL_CC_DISPATCH, _SL_CC_COUNT(__VA_ARGS__)))(component, __VA_ARGS__) -#else -#define SL_CODE_CLASSIFY(component, ...) -#endif #endif // _SLI_CODE_CLASSIFICATION_H_ diff --git a/simplicity_sdk/platform/common/src/sl_core_cortexm.c b/simplicity_sdk/platform/common/src/sl_core_cortexm.c index 31a97c030..3b8b56e3b 100644 --- a/simplicity_sdk/platform/common/src/sl_core_cortexm.c +++ b/simplicity_sdk/platform/common/src/sl_core_cortexm.c @@ -88,10 +88,15 @@ SL_WEAK void CORE_CriticalDisableIrq(void) /***************************************************************************//** * @brief * Enable interrupts. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. ******************************************************************************/ SL_WEAK void CORE_CriticalEnableIrq(void) { __enable_irq(); + __ISB(); } /***************************************************************************//** @@ -113,6 +118,10 @@ SL_WEAK CORE_irqState_t CORE_EnterCritical(void) /***************************************************************************//** * @brief * Exit a CRITICAL section. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. ******************************************************************************/ SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) { @@ -121,6 +130,7 @@ SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) cycle_counter_stop(&critical_cycle_counter); #endif __enable_irq(); + __ISB(); } } @@ -154,6 +164,10 @@ SL_WEAK void CORE_AtomicDisableIrq(void) /***************************************************************************//** * @brief * Enable interrupts. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. ******************************************************************************/ SL_WEAK void CORE_AtomicEnableIrq(void) { @@ -162,6 +176,7 @@ SL_WEAK void CORE_AtomicEnableIrq(void) #else __enable_irq(); #endif + __ISB(); } /***************************************************************************//** @@ -195,6 +210,10 @@ SL_WEAK CORE_irqState_t CORE_EnterAtomic(void) /***************************************************************************//** * @brief * Exit an ATOMIC section. + * @note + * __ISB() makes sure pending interrupts are executed before returning. + * This can be a problem if the first instruction after changing the BASEPRI + * or PRIMASK assumes that the pending interrupts have already been processed. ******************************************************************************/ SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) { @@ -206,12 +225,14 @@ SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) } #endif __set_BASEPRI(irqState); + __ISB(); #else if (irqState == 0U) { #if (SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) cycle_counter_stop(&critical_cycle_counter); #endif __enable_irq(); + __ISB(); } #endif } @@ -347,4 +368,28 @@ void CORE_clear_max_time_atomic_section(void) #endif //(SL_CORE_DEBUG_INTERRUPTS_MASKED_TIMING == 1) } +/***************************************************************************//** + * @brief + * Reset chip routine. + ******************************************************************************/ +void CORE_ResetSystem(void) +{ + // Ensure all outstanding memory accesses including buffered writes are + // completed before reset + __DSB(); + + // Keep priority group unchanged + SCB->AIRCR = (0x5FAUL << SCB_AIRCR_VECTKEY_Pos) + | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) + | SCB_AIRCR_SYSRESETREQ_Msk; + + // Ensure completion of memory access + __DSB(); + + // Wait until reset + for (;; ) { + __NOP(); + } +} + /** @} (end addtogroup sl_core) */ diff --git a/simplicity_sdk/platform/common/src/sl_slist.c b/simplicity_sdk/platform/common/src/sl_slist.c index d74a72ae8..8e9d11740 100644 --- a/simplicity_sdk/platform/common/src/sl_slist.c +++ b/simplicity_sdk/platform/common/src/sl_slist.c @@ -109,6 +109,25 @@ void sl_slist_insert(sl_slist_node_t *item, pos->node = item; } +/***************************************************************************//** + * Add item at end of list. + ******************************************************************************/ +void sl_slist_join(sl_slist_node_t **head_list_1, + sl_slist_node_t **head_list_2) +{ + sl_slist_node_t **node_ptr = head_list_1; + + EFM_ASSERT((head_list_2 != NULL) + && (head_list_1 != NULL)); + + while (*node_ptr != NULL) { + node_ptr = &((*node_ptr)->node); + } + + *node_ptr = *head_list_2; + *head_list_2 = NULL; +} + /***************************************************************************//** * Remove item from list. ******************************************************************************/ diff --git a/simplicity_sdk/platform/driver/gpio/inc/sl_gpio.h b/simplicity_sdk/platform/driver/gpio/inc/sl_gpio.h new file mode 100644 index 000000000..758a47602 --- /dev/null +++ b/simplicity_sdk/platform/driver/gpio/inc/sl_gpio.h @@ -0,0 +1,521 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) driver API + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_GPIO_H +#define SL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "sl_status.h" +#include "sl_device_gpio.h" + +#ifndef EM_GPIO_H +#define gpioPortA 0 +#define gpioPortB 1 +#define gpioPortC 2 +#define gpioPortD 3 +#define gpioPortE 4 +#define gpioPortF 5 +#define gpioPortG 6 +#define gpioPortH 7 +#define gpioPortI 8 +#define gpioPortJ 9 +#define gpioPortK 10 +#endif + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup gpio GPIO - General Purpose Input Output +/// @brief General Purpose Input Output driver +/// +/// @li @ref gpio_intro +/// +///@n @section gpio_intro Introduction +/// This module contains functions to control the GPIO peripheral of Silicon Labs 32-bit MCUs and SoCs. +/// The GPIO driver is used for external and EM4 interrupt configuration, port and pin configuration. +/// as well as manages the interrupt handler. +/// +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// GPIO Pin directions. +SL_ENUM(sl_gpio_pin_direction_t) { + /// Input direction. + SL_GPIO_PIN_DIRECTION_IN = 0, + /// Output direction. + SL_GPIO_PIN_DIRECTION_OUT +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Structure for GPIO port and pin configuration. + ******************************************************************************/ +typedef struct { + sl_gpio_mode_t mode; + sl_gpio_pin_direction_t direction; +} sl_gpio_pin_config_t; + +/******************************************************************************* + ******************************* TYPEDEFS ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * GPIO interrupt callback function pointer. + * + * @param int_no The pin interrupt number to which the callback function is invoked for. + * @param context Pointer to callback context. + ******************************************************************************/ +typedef void (*sl_gpio_irq_callback_t)(uint8_t int_no, void *context); + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialization of GPIO driver module. + * + * @return SL_STATUS_OK if initialization is successful. + ******************************************************************************/ +sl_status_t sl_gpio_init(void); + +/***************************************************************************//** + * Sets the pin direction of GPIO pin. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in] pin_dir Pin direction of GPIO pin. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin, direction parameters are invalid. + * SL_STATUS_INVALID_STATE if GPIO configuration is in lock state. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_direction(const sl_gpio_t *gpio, + sl_gpio_pin_direction_t pin_dir); + +/***************************************************************************//** + * Set the pin mode and set/clear the pin for GPIO pin. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in] mode The desired pin mode. + * @param[in] output_value Value to set/clear for pin output on the port. + * Determines the pull-up/pull-down direction of the pin for + * some input mode configurations. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin, mode parameters are invalid. + * SL_STATUS_INVALID_STATE if GPIO configuration is in locked state. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_mode(const sl_gpio_t *gpio, + sl_gpio_mode_t mode, + bool output_value); + +/***************************************************************************//** + * Gets the current configuration selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[out] pin_config Pointer to pin configuration such as mode and direction. + * Pointer acts as an output and returns the configuration of + * selected pin on selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if pin_config is passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_config(const sl_gpio_t *gpio, + sl_gpio_pin_config_t *pin_config); + +/***************************************************************************//** + * Sets the selected pin of the selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin(const sl_gpio_t *gpio); + +/***************************************************************************//** + * Clears the selected pin of the selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + ******************************************************************************/ +sl_status_t sl_gpio_clear_pin(const sl_gpio_t *gpio); + +/***************************************************************************//** + * Toggles the state of selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + ******************************************************************************/ +sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio); + +/***************************************************************************//** + * Gets the output state of selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[out] pin_value Pointer to return output state of selected pin on selected port + * when configured to output mode. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if pin_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_output(const sl_gpio_t *gpio, + bool *pin_value); + +/***************************************************************************//** + * Gets the input state of selected pin on selected port. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[out] pin_value Pointer to return input state of selected pin on selected port + * when configured to input mode. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMATER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if pin_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_input(const sl_gpio_t *gpio, + bool *pin_value); + +/***************************************************************************//** + * Sets the selected pin(s) of selected port. + * + * @param[in] port The GPIO port to access. + * @param[in] pins Bit mask for pins to set. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_set_port(sl_gpio_port_t port, + uint32_t pins); + +/***************************************************************************//** + * Clears the selected pin(s) of selected port. + * + * @param[in] port The GPIO Port to access. + * @param[in] pins Bit mask for bits to clear. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_clear_port(sl_gpio_port_t port, + uint32_t pins); + +/***************************************************************************//** + * Gets the output state of pins of selected port. + * + * @param[in] gpio The GPIO Port to access. + * @param[out] port_value Pointer to return output state of pins on selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + * SL_STATUS_NULL_POINTER if port_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_output(sl_gpio_port_t port, + uint32_t *port_value); + +/***************************************************************************//** + * Gets the input state of pins of selected port. + * + * @param[in] gpio The GPIO Port to access. + * @param[out] port_value Pointer to return output state of pins on selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + * SL_STATUS_NULL_POINTER if port_value passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_input(sl_gpio_port_t port, + uint32_t *port_value); + +/***************************************************************************//** + * Configures the GPIO pin interrupt. + * + * @details By default, this function can be used to register a callback which shall be called upon + * interrupt generated for a given pin interrupt number and enables interrupt. + * This function configures and enables the external interrupt and performs + * callback registration. + * It is recommended to use sl_gpio_deconfigure_external_interrupt() + * to disable the interrupt and unregister the callback. + * see @ref sl_gpio_deconfigure_external_interrupt for more information. + * If a valid interrupt number is provided, operation will proceed accordingly. + * Otherwise, a valid interrupt number will be generated based on provided port and + * pin and used for subsequent operations. + * + * @note If the user has a valid interrupt number to provide as input, it can be used. + * If the user does not have an interrupt number, they can pass -1 (SL_GPIO_INTERRUPT_UNAVAILABLE) + * as value to variable int_no. + * The int_no parameter serves even as an output, a pointer to convey the interrupt number + * for cases where user lacks an interrupt number. + * @note the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (int_no / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in/out] int_no Pointer to interrupt number to trigger. + * Pointer that serves as both an input and an output to return int_no + * when the user lacks an int_no. + * @param[in] flags Interrupt flags for interrupt configuration. + * Determines the interrupt to get trigger based on rising/falling edge. + * @param[in] gpio_callback A pointer to gpio callback function. + * @param[in] context A pointer to the callback context. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin, flag parameters are invalid. + * SL_STATUS_NULL_POINTER if the int_no is passed as NULL. + * SL_STATUS_NOT_FOUND if there's no available interrupt number. + ******************************************************************************/ +sl_status_t sl_gpio_configure_external_interrupt(const sl_gpio_t *gpio, + int32_t *int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + void *context); + +/***************************************************************************//** + * Deconfigures the GPIO external pin interrupt. + * + * @details This function can be used to deconfigure the external GPIO interrupt. + * This function performs callback unregistration, clears and disables the + * given interrupt. + * + * @note the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (int_no / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * + * @param[in] int_no Interrupt number to unregister and disable. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if int_no is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_external_interrupt(int32_t int_no); + +/***************************************************************************//** + * Enables one or more GPIO Interrupts. + * + * @param[in] int_mask Mask for GPIO Interrupt sources to enable. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_enable_interrupts(uint32_t int_mask); + +/***************************************************************************//** + * Disables one or more GPIO Interrupts. + * + * @param[in] int_mask Mask for GPIO Interrupt sources to disable. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_disable_interrupts(uint32_t int_mask); + +/***************************************************************************//** + * Configuration EM4WU pins as external level-sensitive interrupts. + * + * @details By default, this function performs callback registration, enables GPIO pin wake-up from EM4, + * sets the wake-up polarity, enables GPIO pin retention and enables the EM4 wake-up interrupt. + * It is recommended to use sl_gpio_deconfigure_wakeup_em4_interrupt() + * to unregister the callback and disable the em4 interrupt as well as GPIO pin wake-up from EM4. + * It is recommended to use sl_gpio_set_pin_em4_retention() to enable/disable the GPIO pin retention. + * see @ref sl_gpio_deconfigure_wakeup_em4_interrupt() and @ref sl_gpio_set_pin_em4_retention(). + * If a valid EM4 wake-up interrupt number is provided, operation will proceed accordingly. + * Otherwise, a valid EM4 interrupt number will be generated based on provided EM4 configured + * port and pin and used for subsequent operations. + * + * @note If the user has a valid em4 interrupt number to provide as input, it can be used. + * If the user does not have an interrupt number, they can pass -1 (SL_GPIO_INTERRUPT_UNAVAILABLE) + * as value to variable em4_int_no. + * The em4_int_no parameter serves even as an output, a pointer to convey the em4 interrupt number + * for cases where user lacks an em4 interrupt number. + * @note There are specific ports and pins mapped to an existent EM4WU interrupt + * Each EM4WU signal is connected to a fixed pin and port. + * Based on chip, EM4 wake up interrupts configured port and pin might vary. + * + * @param[in] gpio Pointer to GPIO structure with port and pin + * @param[in/out] em4_int_no Pointer to interrupt number to trigger. + * Pointer that serves as both an input and an output to return em4_int_no + * when the user lacks an em4_int_no. + * @param[in] polarity Determines the wakeup polarity. + * true = Active high level-sensitive interrupt. + * false = Active low level-sensitive interrupt. + * @param[in] gpio_callback A pointer to callback. + * @param[in] context A pointer to callback context. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if any of the port, pin parameters are invalid. + * SL_STATUS_NULL_POINTER if the int_no is passed as NULL. + * SL_STATUS_NOT_FOUND if there's no available interrupt number. + ******************************************************************************/ +sl_status_t sl_gpio_configure_wakeup_em4_interrupt(const sl_gpio_t *gpio, + int32_t *em4_int_no, + bool polarity, + sl_gpio_irq_callback_t gpio_callback, + void *context); + +/***************************************************************************//** + * Utilize this function to deconfigure the EM4 GPIO pin interrupt. + * It serves to unregister a callback, disable/clear interrupt and clear em4 wakeup source. + * + * @details This function performs callback unregistration, clears and disables given em4 + * interrupt and disables GPIO pin wake-up from EM4. + * + * @param[in] em4_int_no EM4 wakeup interrupt number. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if em4_int_no is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_wakeup_em4_interrupt(int32_t em4_int_no); + +/***************************************************************************//** + * Enable EM4 GPIO pin Wake-up bit. + * Sets the wakeup and polarity of the EM4 wakeup. + * + * @param[in] em4_int_mask Mask for setting desired EM4 wake up interrupt to enable. + * Mask contains the bitwise logic OR of which EM4 wake up interrupt to + * enable. + * @param[in] em4_polarity_mask Mask for setting the wake up polarity for the EM4 wake up interrupt. + * Mask contains the bitwise logic OR of EM4 wake-up interrupt polarity. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_enable_pin_em4_wakeup(uint32_t em4_int_mask, + uint32_t em4_polarity_mask); + +/***************************************************************************//** + * Disabled the GPIO wake up from EM4. + * + * @param[in] pinmask Mask for clearing desired EM4 wake up interrupt to disable. + * Mask contains the bitwise logic OR of which EM4 wake up interrupt to + * disable. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_disable_pin_em4_wakeup(uint32_t em4_int_mask); + +/***************************************************************************//** + * Enable/Disable GPIO pin retention of output enable, output value, pull enable, and pull direction in EM4. + * + * @param[in] enable true - enables EM4 pin retention. + * false - disables EM4 pin retention. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_em4_retention(bool enable); + +/***************************************************************************//** + * Sets slewrate for selected port. + * + * @param[in] port The GPIO port to configure. + * @param[in] slewrate The slewrate to configure the GPIO port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + ******************************************************************************/ +sl_status_t sl_gpio_set_slew_rate(sl_gpio_port_t port, + uint8_t slewrate); + +/***************************************************************************//** + * Gets slewrate for selected port. + * + * @param[in] port The GPIO port to get slewrate. + * @param[out] slewrate Pointer to store the slewrate of selected port. + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_INVALID_PARAMETER if port is invalid. + * SL_STATUS_NULL_POINTER if slewrate is passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_get_slew_rate(sl_gpio_port_t port, + uint8_t *slewrate); + +/***************************************************************************//** + * Locks the GPIO Configuration. + * + * @note This API locks the functionalities such as sl_gpio_set_pin_mode(), + * sl_gpio_configure_external_interrupt() and sl_gpio_configure_wakeup_em4_interrupt(). + * After locking the GPIO configuration, use sl_gpio_unlock API to unlock + * the GPIO configuration to use mentioned functionalities. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_lock(void); + +/***************************************************************************//** + * Unlocks the GPIO Configuration. + * + * @note After locking the GPIO configuration it is recommended to unlock the GPIO configuration + * using sl_gpio_unlock(). You can determine if the GPIO configuration is locked or unlocked + * by using the sl_gpio_is_locked() function. + * Before using certain functions like sl_gpio_set_pin_mode(), + * sl_gpio_configure_external_interrupt(), and sl_gpio_configure_wakeup_em4_interrupt(), + * it's important to check if the GPIO configuration lock is unlocked. + * + * @return SL_STATUS_OK if there's no error. + ******************************************************************************/ +sl_status_t sl_gpio_unlock(void); + +/***************************************************************************//** + * Gets current GPIO Lock status. + * + * @note This function helps check the current status of GPIO configuration. + * + * @param[out] state Pointer to current state of GPIO configuration (lock/unlock). + * + * @return SL_STATUS_OK if there's no error. + * SL_STATUS_NULL_POINTER if state is passed as null. + ******************************************************************************/ +sl_status_t sl_gpio_is_locked(bool *state); + +/** @} (end addtogroup gpio driver) */ +#ifdef __cplusplus +} +#endif + +#endif /* SL_GPIO_H */ diff --git a/simplicity_sdk/platform/driver/gpio/src/sl_gpio.c b/simplicity_sdk/platform/driver/gpio/src/sl_gpio.c new file mode 100644 index 000000000..07e58ef5e --- /dev/null +++ b/simplicity_sdk/platform/driver/gpio/src/sl_gpio.c @@ -0,0 +1,824 @@ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) driver API + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_core.h" +#include "sl_common.h" +#include "sl_interrupt_manager.h" +#include "sl_clock_manager.h" +#include "sl_hal_gpio.h" +#include "sl_gpio.h" + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/// Define for supporting gpiointerrupt porting +#define SL_GPIO_PORT_INTERRUPT (0xFF) + +/// Pin direction validation. +#define SL_GPIO_DIRECTION_IS_VALID(direction) (direction <= SL_GPIO_PIN_DIRECTION_OUT) + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +typedef struct { + // Pin interrupt number in range 0 to 15. + uint32_t int_no; + // Pointer to callback function. + void *callback; + // Pointer to callback context. + void *context; +} sl_gpio_callback_desc_t; + +typedef struct { + // An array of user callbacks for external interrupts. + // We have external interrupts configured from 0 to 15 bits. + sl_gpio_callback_desc_t callback_ext[SL_HAL_GPIO_INTERRUPT_MAX]; + // An array of user callbacks for EM4 interrupts. + // We have EM4 interrupts configured from 16 to 31 bits. + sl_gpio_callback_desc_t callback_em4[SL_HAL_GPIO_INTERRUPT_MAX]; +} sl_gpio_callbacks_t; + +/******************************************************************************* + ******************************** GLOBALS ********************************** + ******************************************************************************/ + +// Variable to manage and organize the callback functions for External and EM4 interrupts. +static sl_gpio_callbacks_t gpio_interrupts = { 0 }; + +/******************************************************************************* + ****************************** LOCAL FUCTIONS ***************************** + ******************************************************************************/ +static void sl_gpio_dispatch_interrupt(uint32_t iflags); + +/***************************************************************************//** + * Driver GPIO Initialization. + ******************************************************************************/ +sl_status_t sl_gpio_init() +{ + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); + + if (sl_interrupt_manager_is_irq_disabled(GPIO_ODD_IRQn)) { + sl_interrupt_manager_clear_irq_pending(GPIO_ODD_IRQn); + sl_interrupt_manager_enable_irq(GPIO_ODD_IRQn); + } + if (sl_interrupt_manager_is_irq_disabled(GPIO_EVEN_IRQn)) { + sl_interrupt_manager_clear_irq_pending(GPIO_EVEN_IRQn); + sl_interrupt_manager_enable_irq(GPIO_EVEN_IRQn); + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the pin direction for GPIO pin. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_direction(const sl_gpio_t *gpio, + sl_gpio_pin_direction_t pin_direction) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin) || !SL_GPIO_DIRECTION_IS_VALID(pin_direction)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (sl_hal_gpio_get_lock_status() != 0) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_STATE; + } + + CORE_ENTER_ATOMIC(); + + if (pin_direction == SL_GPIO_PIN_DIRECTION_OUT) { + sl_hal_gpio_set_pin_mode(gpio, SL_GPIO_MODE_PUSH_PULL, 1); + } else if (pin_direction == SL_GPIO_PIN_DIRECTION_IN) { + sl_hal_gpio_set_pin_mode(gpio, SL_GPIO_MODE_INPUT, 0); + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the mode for GPIO pin and pin direction. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_mode(const sl_gpio_t *gpio, + sl_gpio_mode_t mode, + bool output_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_MODE_IS_VALID(mode) || !SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (sl_hal_gpio_get_lock_status() != 0) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_STATE; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_pin_mode(gpio, mode, output_value); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the current configuration selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_config(const sl_gpio_t *gpio, + sl_gpio_pin_config_t *pin_config) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || pin_config == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + pin_config->mode = sl_hal_gpio_get_pin_mode(gpio); + switch (pin_config->mode) { + case SL_GPIO_MODE_INPUT: + case SL_GPIO_MODE_INPUT_PULL: + case SL_GPIO_MODE_INPUT_PULL_FILTER: + pin_config->direction = SL_GPIO_PIN_DIRECTION_IN; + break; + + case SL_GPIO_MODE_DISABLED: + case SL_GPIO_MODE_PUSH_PULL: + case SL_GPIO_MODE_PUSH_PULL_ALTERNATE: + case SL_GPIO_MODE_WIRED_OR: + case SL_GPIO_MODE_WIRED_OR_PULL_DOWN: + case SL_GPIO_MODE_WIRED_AND: + case SL_GPIO_MODE_WIRED_AND_FILTER: + case SL_GPIO_MODE_WIRED_AND_PULLUP: + case SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP: + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER: + pin_config->direction = SL_GPIO_PIN_DIRECTION_OUT; + break; + + default: + CORE_EXIT_ATOMIC(); + EFM_ASSERT(false); + return SL_STATUS_INVALID_MODE; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the DOUT of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_set_pin(const sl_gpio_t *gpio) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_pin(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Clears the DOUT of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_clear_pin(const sl_gpio_t *gpio) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_clear_pin(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Toggles the DOUT of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_toggle_pin(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the output state of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_output(const sl_gpio_t *gpio, + bool *pin_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || pin_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + *pin_value = sl_hal_gpio_get_pin_output(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the input state of selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_pin_input(const sl_gpio_t *gpio, + bool *pin_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || pin_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + *pin_value = sl_hal_gpio_get_pin_input(gpio); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets the selected pin(s) on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_set_port(sl_gpio_port_t port, + uint32_t pins) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_port(port, pins); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Clears the selected pin on selected port. + ******************************************************************************/ +sl_status_t sl_gpio_clear_port(sl_gpio_port_t port, + uint32_t pins) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_clear_port(port, pins); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the output state of pins of selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_output(sl_gpio_port_t port, + uint32_t *port_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (port_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + *port_value = sl_hal_gpio_get_port_output(port); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the input state of pins of selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_port_input(sl_gpio_port_t port, + uint32_t *port_value) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (port_value == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + *port_value = sl_hal_gpio_get_port_input(port); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Configuring the GPIO external pin interrupt. + * This API can be used to configure interrupt and to register the callback. + ******************************************************************************/ +sl_status_t sl_gpio_configure_external_interrupt(const sl_gpio_t *gpio, + int32_t *int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + void *context) +{ + uint32_t enabled_interrupts; + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || int_no == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin) && (gpio->port != SL_GPIO_PORT_INTERRUPT)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (!SL_GPIO_FLAG_IS_VALID(flags)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + *int_no = sl_hal_gpio_configure_external_interrupt(gpio, *int_no, flags); + } + + if (*int_no == SL_GPIO_INTERRUPT_UNAVAILABLE && gpio->port == SL_GPIO_PORT_INTERRUPT) { + enabled_interrupts = sl_hal_gpio_get_enabled_interrupts(); + *int_no = sl_hal_gpio_get_external_interrupt_number(gpio->pin, enabled_interrupts); + } + + if (*int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { + // Callback registration. + gpio_interrupts.callback_ext[*int_no].callback = (void *)gpio_callback; + gpio_interrupts.callback_ext[*int_no].context = context; + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + sl_hal_gpio_enable_interrupts(1 << *int_no); + } + } else { + CORE_EXIT_ATOMIC(); + return SL_STATUS_NOT_FOUND; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Deconfigures the GPIO external pin interrupt. + * This API can be used to deconfigure the interrupt and to unregister the callback. + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_external_interrupt(int32_t int_no) +{ + CORE_DECLARE_IRQ_STATE; + + if (!((int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) && (int_no <= SL_HAL_GPIO_INTERRUPT_MAX) && (int_no >= 0))) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + // Clear pending interrupt. + sl_hal_gpio_clear_interrupts(1 << int_no); + sl_hal_gpio_disable_interrupts(1 << int_no); + + // Callback deregistration. + gpio_interrupts.callback_ext[int_no].callback = NULL; + gpio_interrupts.callback_ext[int_no].context = NULL; + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Enables one or more GPIO interrupts. + ******************************************************************************/ +sl_status_t sl_gpio_enable_interrupts(uint32_t flags) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_enable_interrupts(flags); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Disables one or more GPIO interrupts. + ******************************************************************************/ +sl_status_t sl_gpio_disable_interrupts(uint32_t flags) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_disable_interrupts(flags); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Configures the EM4WU pin as external level interrupts for waking up from EM mode. + * Registering/unregistering the callbacks and Configuring the EM4 interrupts to enable/disable + ******************************************************************************/ +sl_status_t sl_gpio_configure_wakeup_em4_interrupt(const sl_gpio_t *gpio, + int32_t *em4_int_no, + bool polarity, + sl_gpio_irq_callback_t gpio_callback, + void *context) +{ + CORE_DECLARE_IRQ_STATE; + + if (gpio == NULL || em4_int_no == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + if (!SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin) && (gpio->port != SL_GPIO_PORT_INTERRUPT)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + *em4_int_no = sl_hal_gpio_configure_wakeup_em4_external_interrupt(gpio, *em4_int_no, polarity); + } + + if (*em4_int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { + // Callback registration. + gpio_interrupts.callback_em4[*em4_int_no].callback = (void *)gpio_callback; + gpio_interrupts.callback_em4[*em4_int_no].context = context; + + if (gpio->port != SL_GPIO_PORT_INTERRUPT) { + sl_hal_gpio_enable_interrupts(1 << (*em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + } + } else { + CORE_EXIT_ATOMIC(); + return SL_STATUS_NOT_FOUND; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Deconfigures the EM4 GPIO pin interrupt. + * Unregisters a callback, disable/clear interrupt and clear em4 wakeup source + ******************************************************************************/ +sl_status_t sl_gpio_deconfigure_wakeup_em4_interrupt(int32_t em4_int_no) +{ + CORE_DECLARE_IRQ_STATE; + + if (!((em4_int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) && (em4_int_no <= SL_HAL_GPIO_INTERRUPT_MAX) && (em4_int_no >= 0))) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + // Clear any pending interrupt. + sl_hal_gpio_clear_interrupts(1 << (em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + sl_hal_gpio_disable_pin_em4_wakeup(1 << (em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + sl_hal_gpio_disable_interrupts(1 << (em4_int_no + SL_HAL_GPIO_EM4WUEN_SHIFT)); + + /* Callback deregistration */ + gpio_interrupts.callback_em4[em4_int_no].callback = NULL; + gpio_interrupts.callback_em4[em4_int_no].context = NULL; + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets GPIO EM4 Wake up interrupt to Enable and EM4 Wake up interrupt polarity + ******************************************************************************/ +sl_status_t sl_gpio_enable_pin_em4_wakeup(uint32_t em4_int_mask, + uint32_t em4_polarity_mask) +{ + uint32_t int_mask = 0; + uint32_t polarity_mask = 0; + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // Enable EM4WU function and set polarity. + int_mask |= (em4_int_mask << _GPIO_EM4WUEN_EM4WUEN_SHIFT); + polarity_mask |= (em4_polarity_mask << _GPIO_EM4WUEN_EM4WUEN_SHIFT); + sl_hal_gpio_enable_pin_em4_wakeup(int_mask, polarity_mask); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Clears GPIO EM4 Wake up enable + ******************************************************************************/ +sl_status_t sl_gpio_disable_pin_em4_wakeup(uint32_t em4_int_mask) +{ + uint32_t int_mask = 0; + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // Disable EM4WU function. + int_mask |= (em4_int_mask << _GPIO_EM4WUEN_EM4WUEN_SHIFT); + sl_hal_gpio_disable_pin_em4_wakeup(int_mask); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Enable GPIO pin retention of output enable, output value, pull direction, pull enable in EM4 + ******************************************************************************/ +sl_status_t sl_gpio_set_pin_em4_retention(bool enable) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_pin_em4_retention(enable); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sets slewrate for selected port. + ******************************************************************************/ +sl_status_t sl_gpio_set_slew_rate(sl_gpio_port_t port, + uint8_t slewrate) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + sl_hal_gpio_set_slew_rate(port, slewrate); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets slewrate for selected port. + ******************************************************************************/ +sl_status_t sl_gpio_get_slew_rate(sl_gpio_port_t port, + uint8_t *slewrate) +{ + CORE_DECLARE_IRQ_STATE; + + if (!SL_HAL_GPIO_PORT_IS_VALID(port)) { + EFM_ASSERT(false); + return SL_STATUS_INVALID_PARAMETER; + } + if (slewrate == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + *slewrate = sl_hal_gpio_get_slew_rate(port); + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Locks the GPIO Configuration + ******************************************************************************/ +sl_status_t sl_gpio_lock(void) +{ + sl_hal_gpio_lock(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Unlocks the GPIO Configuration + ******************************************************************************/ +sl_status_t sl_gpio_unlock(void) +{ + sl_hal_gpio_unlock(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets the GPIO State + ******************************************************************************/ +sl_status_t sl_gpio_is_locked(bool *state) +{ + uint32_t status; + CORE_DECLARE_IRQ_STATE; + + if (state == NULL) { + EFM_ASSERT(false); + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + status = sl_hal_gpio_get_lock_status(); + if (status) { + // true - GPIO configuration registers are locked. + *state = true; + } else { + // false - GPIO configuration registers are unlocked. + *state = false; + } + + CORE_EXIT_ATOMIC(); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Function calls users callback for registered pin interrupts. + * + * @details This function is called when GPIO interrupts are handled by the IRQHandlers. + * Function gets even or odd interrupt flags and calls user callback + * registered for that pin. Function iterates on flags starting from MSB. + * + * @param iflags Interrupt flags which shall be handled by the dispatcher. + ******************************************************************************/ +static void sl_gpio_dispatch_interrupt(uint32_t iflags) +{ + uint32_t irq_idx; + sl_gpio_callback_desc_t *callback; + sl_gpio_irq_callback_t func; + + // Check for flags set in IF register. + while (iflags != 0) { + irq_idx = SL_CTZ(iflags); + iflags &= ~(1UL << irq_idx); + + if (irq_idx <= SL_HAL_GPIO_INTERRUPT_MAX) { + callback = &gpio_interrupts.callback_ext[irq_idx]; + } else { + callback = &gpio_interrupts.callback_em4[irq_idx - SL_HAL_GPIO_EM4WUEN_SHIFT]; + irq_idx = irq_idx - SL_HAL_GPIO_EM4WUEN_SHIFT; + } + // Call user callback. + if (callback->callback) { + func = (sl_gpio_irq_callback_t)(callback->callback); + func((uint8_t)irq_idx, callback->context); + } + } +} + +/***************************************************************************//** + * GPIO EVEN interrupt handler. Interrupt handler clears all IF even flags and + * call the dispatcher passing the flags which triggered the interrupt. + ******************************************************************************/ +void GPIO_EVEN_IRQHandler(void) +{ + uint32_t even_flags; + + // Gets all enabled and pending even interrupts. + even_flags = sl_hal_gpio_get_enabled_pending_interrupts() & SL_HAL_GPIO_INT_IF_EVEN_MASK; + // Clears only even interrupts. + sl_hal_gpio_clear_interrupts(even_flags); + + sl_gpio_dispatch_interrupt(even_flags); +} + +/***************************************************************************//** + * @brief + * GPIO ODD interrupt handler. Interrupt handler clears all IF odd flags and + * call the dispatcher passing the flags which triggered the interrupt. + ******************************************************************************/ +void GPIO_ODD_IRQHandler(void) +{ + uint32_t odd_flags; + + // Gets all enabled and pending odd interrupts. + odd_flags = sl_hal_gpio_get_enabled_pending_interrupts() & SL_HAL_GPIO_INT_IF_ODD_MASK; + // Clears only odd interrupts. + sl_hal_gpio_clear_interrupts(odd_flags); + + sl_gpio_dispatch_interrupt(odd_flags); +} diff --git a/simplicity_sdk/platform/emdrv/common/inc/ecode.h b/simplicity_sdk/platform/emdrv/common/inc/ecode.h new file mode 100644 index 000000000..033400bad --- /dev/null +++ b/simplicity_sdk/platform/emdrv/common/inc/ecode.h @@ -0,0 +1,70 @@ +/***************************************************************************//** + * @file + * @brief Energy Aware drivers error code definitions. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_ECODE_H__ +#define __SILICON_LABS_ECODE_H__ + +#include + +/***************************************************************************//** + * @addtogroup ecode ECODE - Error Codes + * @details ECODE is set of error and status codes related to DMA, RTC, SPI, + * NVM, USTIMER, UARTDRV, EZRADIO, TEMP, and NVM3 drivers. These error and + * status codes are used by the above listed drivers to update the layer + * (using the driver) about an error or status. + * + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Typedef for API function error code return values. + * + * @details + * Bit 24-31: Component, for example emdrv @n + * Bit 16-23: Module, for example @ref uartdrv or @ref spidrv @n + * Bit 0-15: Error code + ******************************************************************************/ +typedef uint32_t Ecode_t; + +#define ECODE_EMDRV_BASE (0xF0000000U) ///< Base value for all EMDRV errorcodes. + +#define ECODE_OK (0U) ///< Generic success return value. + +#define ECODE_EMDRV_SPIDRV_BASE (ECODE_EMDRV_BASE | 0x00002000U) ///< Base value for SPIDRV error codes. +#define ECODE_EMDRV_NVM_BASE (ECODE_EMDRV_BASE | 0x00003000U) ///< Base value for NVM error codes. +#define ECODE_EMDRV_USTIMER_BASE (ECODE_EMDRV_BASE | 0x00004000U) ///< Base value for USTIMER error codes. +#define ECODE_EMDRV_UARTDRV_BASE (ECODE_EMDRV_BASE | 0x00007000U) ///< Base value for UARTDRV error codes. +#define ECODE_EMDRV_DMADRV_BASE (ECODE_EMDRV_BASE | 0x00008000U) ///< Base value for DMADRV error codes. +#define ECODE_EMDRV_EZRADIODRV_BASE (ECODE_EMDRV_BASE | 0x00009000U) ///< Base value for EZRADIODRV error codes. +#define ECODE_EMDRV_TEMPDRV_BASE (ECODE_EMDRV_BASE | 0x0000D000U) ///< Base value for TEMPDRV error codes. +#define ECODE_EMDRV_NVM3_BASE (ECODE_EMDRV_BASE | 0x0000E000U) ///< Base value for NVM3 error codes. + +/** @} (end addtogroup ecode) */ + +#endif // __SILICON_LABS_ECODE_H__ diff --git a/simplicity_sdk/platform/emdrv/dmadrv/config/s2_8ch/dmadrv_config.h b/simplicity_sdk/platform/emdrv/dmadrv/config/s2_8ch/dmadrv_config.h new file mode 100644 index 000000000..ed105e4f3 --- /dev/null +++ b/simplicity_sdk/platform/emdrv/dmadrv/config/s2_8ch/dmadrv_config.h @@ -0,0 +1,26 @@ +#ifndef DMADRV_CONFIG_H +#define DMADRV_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMA interrupt priority <0-15> +// Priority of the DMA interrupt. Smaller number equals higher priority. +// Default: 8 +#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 8 + +// Number of available channels <1-8> +// Number of DMA channels supported by the driver. A lower channel count +// will reduce RAM memory footprint. The default is to support all channels +// on the device. +// Default: 8 +#define EMDRV_DMADRV_DMA_CH_COUNT 8 + +// Number of fixed priority channels +// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, +// and channels [CH_PRIORITY, CH_COUNT] as round-robin. +// Default: 0 +#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 + +// <<< end of configuration section >>> + +#endif // DMADRV_CONFIG_H diff --git a/simplicity_sdk/platform/emdrv/dmadrv/inc/dmadrv.h b/simplicity_sdk/platform/emdrv/dmadrv/inc/dmadrv.h new file mode 100644 index 000000000..522c86801 --- /dev/null +++ b/simplicity_sdk/platform/emdrv/dmadrv/inc/dmadrv.h @@ -0,0 +1,187 @@ +/***************************************************************************//** + * @file + * @brief DMADRV API definition. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __SILICON_LABS_DMADRV_H__ +#define __SILICON_LABS_DMADRV_H__ + +#include "em_device.h" + +#include "ecode.h" + +#include "dmadrv_signals.h" + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) +#if (_SILICON_LABS_32B_SERIES > 2) +#define EMDRV_DMADRV_LDMA_S3 +#else +#define EMDRV_DMADRV_DMA_PRESENT +#define EMDRV_DMADRV_LDMA +#endif +#else +#error "No valid DMA engine defined." +#endif + +#include "dmadrv_config.h" +#include "sl_code_classification.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup dmadrv + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup dmadrv_error_codes Error Codes + * @{ + ******************************************************************************/ + +#define ECODE_EMDRV_DMADRV_OK (ECODE_OK) ///< A successful return value. +#define ECODE_EMDRV_DMADRV_PARAM_ERROR (ECODE_EMDRV_DMADRV_BASE | 0x00000001) ///< An illegal input parameter. +#define ECODE_EMDRV_DMADRV_NOT_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000002) ///< DMA is not initialized. +#define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000003) ///< DMA has already been initialized. +#define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED (ECODE_EMDRV_DMADRV_BASE | 0x00000004) ///< No DMA channels available. +#define ECODE_EMDRV_DMADRV_IN_USE (ECODE_EMDRV_DMADRV_BASE | 0x00000005) ///< DMA is in use. +#define ECODE_EMDRV_DMADRV_ALREADY_FREED (ECODE_EMDRV_DMADRV_BASE | 0x00000006) ///< A DMA channel was free. +#define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED (ECODE_EMDRV_DMADRV_BASE | 0x00000007) ///< A channel is not reserved. + +/** @} (end addtogroup error codes) */ +/***************************************************************************//** + * @brief + * DMADRV transfer completion callback function. + * + * @details + * The callback function is called when a transfer is complete. + * + * @param[in] channel + * The DMA channel number. + * + * @param[in] sequenceNo + * The number of times the callback was called. Useful on long chains of + * linked transfers or on endless ping-pong type transfers. + * + * @param[in] userParam + * Optional user parameter supplied on DMA invocation. + * + * @return + * When doing ping-pong transfers, return true to continue or false to + * stop transfers. + ******************************************************************************/ +typedef bool (*DMADRV_Callback_t)(unsigned int channel, + unsigned int sequenceNo, + void *userParam); + +Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, + void *capabilities); +Ecode_t DMADRV_AllocateChannelById(unsigned int channelId, + void *capabilities); +Ecode_t DMADRV_DeInit(void); +Ecode_t DMADRV_FreeChannel(unsigned int channelId); +Ecode_t DMADRV_Init(void); + +Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src0, + void *src1, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst0, + void *dst1, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); + +#if defined(EMDRV_DMADRV_LDMA) +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + LDMA_TransferCfg_t *transfer, + LDMA_Descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam); +#elif defined(EMDRV_DMADRV_LDMA_S3) +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + sl_hal_ldma_transfer_config_t *transfer, + sl_hal_ldma_descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam); +#endif + +Ecode_t DMADRV_PauseTransfer(unsigned int channelId); +Ecode_t DMADRV_ResumeTransfer(unsigned int channelId); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL) +Ecode_t DMADRV_StopTransfer(unsigned int channelId); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL) +Ecode_t DMADRV_TransferActive(unsigned int channelId, + bool *active); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL) +Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, + bool *pending); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL) +Ecode_t DMADRV_TransferDone(unsigned int channelId, + bool *done); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DMADRV, SL_CODE_CLASS_TIME_CRITICAL) +Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, + int *remaining); + +/** @} (end addtogroup dmadrv) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SILICON_LABS_DMADRV_H__ */ diff --git a/simplicity_sdk/platform/emdrv/dmadrv/inc/s2_signals/dmadrv_signals.h b/simplicity_sdk/platform/emdrv/dmadrv/inc/s2_signals/dmadrv_signals.h new file mode 100644 index 000000000..b02653193 --- /dev/null +++ b/simplicity_sdk/platform/emdrv/dmadrv/inc/s2_signals/dmadrv_signals.h @@ -0,0 +1,223 @@ +#ifndef __SILICON_LABS_DMADRV_SIGNALS_S2_H__ +#define __SILICON_LABS_DMADRV_SIGNALS_S2_H__ + +#include "em_device.h" +#include "ecode.h" +#include "sl_enum.h" +#include "em_ldma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup dmadrv + * @{ + ******************************************************************************/ + +#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) + +/// Maximum length of one DMA transfer. +#define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) + +/// Peripherals that can trigger LDMA transfers. +SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { + dmadrvPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 + dmadrvPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 + dmadrvPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 + dmadrvPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF + dmadrvPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 + dmadrvPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 + dmadrvPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 + dmadrvPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF + dmadrvPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV + dmadrvPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT + dmadrvPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL + dmadrvPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT + dmadrvPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY + dmadrvPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV + dmadrvPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT + dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL + dmadrvPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT + dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY + dmadrvPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV + dmadrvPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT + dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL + dmadrvPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT + dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY + dmadrvPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV + dmadrvPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL + dmadrvPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV + dmadrvPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL + dmadrvPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI + dmadrvPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF + dmadrvPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 + dmadrvPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 + dmadrvPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 + dmadrvPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 + dmadrvPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 + dmadrvPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF + dmadrvPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF + dmadrvPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG + dmadrvPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN + dmadrvPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE + dmadrvPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA + dmadrvPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 + dmadrvPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 + dmadrvPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 + dmadrvPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF + dmadrvPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 + dmadrvPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 + dmadrvPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 + dmadrvPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF + dmadrvPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL + dmadrvPeripheralSignal_EUART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL + dmadrvPeripheralSignal_EUART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL + dmadrvPeripheralSignal_EUSART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL + dmadrvPeripheralSignal_EUSART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL + dmadrvPeripheralSignal_EUSART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL + dmadrvPeripheralSignal_EUSART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL + dmadrvPeripheralSignal_EUSART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL + dmadrvPeripheralSignal_EUSART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL + dmadrvPeripheralSignal_EUSART3_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL + dmadrvPeripheralSignal_EUSART3_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART3_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL + dmadrvPeripheralSignal_EUSART4_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL + dmadrvPeripheralSignal_EUSART4_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_RXBL. + #endif +}; + +/// Data size of one LDMA transfer item. +SL_ENUM(DMADRV_DataSize_t) { + dmadrvDataSize1 = ldmaCtrlSizeByte, ///< Byte + dmadrvDataSize2 = ldmaCtrlSizeHalf, ///< Halfword + dmadrvDataSize4 = ldmaCtrlSizeWord ///< Word +}; + +#endif /* defined( LDMAXBAR_COUNT ) && ( LDMAXBAR_COUNT == 1 ) */ + +/** @} (end addtogroup dmadrv) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SILICON_LABS_DMADRV_SIGNALS_S2_H__ */ diff --git a/simplicity_sdk/platform/emdrv/dmadrv/src/dmadrv.c b/simplicity_sdk/platform/emdrv/dmadrv/src/dmadrv.c new file mode 100644 index 000000000..c4b27cffc --- /dev/null +++ b/simplicity_sdk/platform/emdrv/dmadrv/src/dmadrv.c @@ -0,0 +1,1745 @@ +/***************************************************************************//** + * @file + * @brief DMADRV API implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include + +#include "em_device.h" +#include "sl_core.h" + +#include "dmadrv.h" + +#if defined(EMDRV_DMADRV_LDMA_S3) +#include "sl_clock_manager.h" +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if !defined(EMDRV_DMADRV_DMA_CH_COUNT) \ + || (EMDRV_DMADRV_DMA_CH_COUNT > DMA_CHAN_COUNT) + +#if defined(_SILICON_LABS_32B_SERIES_3) +#define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT(0) +#else +#define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT +#endif +#endif + +typedef enum { + dmaDirectionMemToPeripheral, + dmaDirectionPeripheralToMem +} DmaDirection_t; + +typedef enum { + dmaModeBasic, + dmaModePingPong +} DmaMode_t; + +typedef struct { + DMADRV_Callback_t callback; + void *userParam; + unsigned int callbackCount; +#if defined(EMDRV_DMADRV_UDMA) + int length; +#endif + bool allocated; +#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) + DmaMode_t mode; +#endif +} ChTable_t; + +static bool initialized = false; +static ChTable_t chTable[EMDRV_DMADRV_DMA_CH_COUNT]; + +#if defined(EMDRV_DMADRV_UDMA) +static DMA_CB_TypeDef dmaCallBack[EMDRV_DMADRV_DMA_CH_COUNT]; +#endif + +#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) +#if defined(EMDRV_DMADRV_LDMA) +const LDMA_TransferCfg_t xferCfgPeripheral = LDMA_TRANSFER_CFG_PERIPHERAL(0); +const LDMA_Descriptor_t m2p = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(NULL, NULL, 1UL); +const LDMA_Descriptor_t p2m = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(NULL, NULL, 1UL); + +typedef struct { + LDMA_Descriptor_t desc[2]; +} DmaXfer_t; +#else +const sl_hal_ldma_transfer_config_t xferCfgPeripheral = SL_HAL_LDMA_TRANSFER_CFG_PERIPHERAL(0); +const sl_hal_ldma_descriptor_t m2p = SL_HAL_LDMA_DESCRIPTOR_SINGLE_M2P(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); +const sl_hal_ldma_descriptor_t p2m = SL_HAL_LDMA_DESCRIPTOR_SINGLE_P2M(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); + +typedef struct { + sl_hal_ldma_descriptor_t desc[2]; +} DmaXfer_t; +#endif + +static DmaXfer_t dmaXfer[EMDRV_DMADRV_DMA_CH_COUNT]; +#endif + +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); + +#if defined(EMDRV_DMADRV_LDMA_S3) +static void LDMA_IRQHandlerDefault(uint8_t chnum); +#endif + +/// @endcond + +/***************************************************************************//** + * @brief + * Allocate (reserve) a DMA channel. + * + * @param[out] channelId + * The channel ID assigned by DMADRV. + * + * @param[in] capabilities + * Not used. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities) +{ + unsigned int i; + (void)capabilities; + CORE_DECLARE_IRQ_STATE; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId == NULL ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + CORE_ENTER_ATOMIC(); + for ( i = 0U; i < (unsigned int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + if ( !chTable[i].allocated ) { + *channelId = i; + chTable[i].allocated = true; + chTable[i].callback = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + } + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED; +} + +/***************************************************************************//** + * @brief + * Allocate (reserve) the given DMA channel if he is free. + * + * @param[out] channelId + * The channel ID to be assigned by DMADRV. + * + * @param[in] capabilities + * Not used. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_AllocateChannelById(unsigned int channelId, void *capabilities) +{ + (void)capabilities; + CORE_DECLARE_IRQ_STATE; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + CORE_ENTER_ATOMIC(); + if ( !chTable[channelId].allocated ) { + chTable[channelId].allocated = true; + chTable[channelId].callback = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_IN_USE; +} + +/***************************************************************************//** + * @brief + * Deinitialize DMADRV. + * + * @details + * If DMA channels are not currently allocated, it will disable DMA hardware + * and mask associated interrupts. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_DeInit(void) +{ + int i; + bool inUse; + CORE_DECLARE_IRQ_STATE; + + inUse = false; + + CORE_ENTER_ATOMIC(); + for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + if ( chTable[i].allocated ) { + inUse = true; + break; + } + } + + if ( !inUse ) { +#if defined(EMDRV_DMADRV_LDMA) + LDMA_DeInit(); +#elif defined(EMDRV_DMADRV_LDMA_S3) + NVIC_DisableIRQ(LDMA0_CHNL0_IRQn); + NVIC_DisableIRQ(LDMA0_CHNL1_IRQn); + NVIC_DisableIRQ(LDMA0_CHNL2_IRQn); + NVIC_DisableIRQ(LDMA0_CHNL3_IRQn); + NVIC_DisableIRQ(LDMA0_CHNL4_IRQn); + NVIC_DisableIRQ(LDMA0_CHNL5_IRQn); + NVIC_DisableIRQ(LDMA0_CHNL6_IRQn); + NVIC_DisableIRQ(LDMA0_CHNL7_IRQn); + + sl_hal_ldma_reset(LDMA0); + + sl_clock_manager_disable_bus_clock(SL_BUS_CLOCK_LDMA0); + sl_clock_manager_disable_bus_clock(SL_BUS_CLOCK_LDMAXBAR0); +#endif + + initialized = false; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_DMADRV_IN_USE; +} + +/***************************************************************************//** + * @brief + * Free an allocated (reserved) DMA channel. + * + * @param[in] channelId + * The channel ID to free. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_FreeChannel(unsigned int channelId) +{ + CORE_DECLARE_IRQ_STATE; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + CORE_ENTER_ATOMIC(); + if ( chTable[channelId].allocated ) { + chTable[channelId].allocated = false; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_DMADRV_ALREADY_FREED; +} + +/***************************************************************************//** + * @brief + * Initialize DMADRV. + * + * @details + * The DMA hardware is initialized. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_Init(void) +{ + int i; + CORE_DECLARE_IRQ_STATE; +#if defined(EMDRV_DMADRV_UDMA) + DMA_Init_TypeDef dmaInit; +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_Init_t dmaInit = LDMA_INIT_DEFAULT; + dmaInit.ldmaInitCtrlNumFixed = EMDRV_DMADRV_DMA_CH_PRIORITY; +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_config_t dmaInit = SL_HAL_LDMA_INIT_DEFAULT; + dmaInit.num_fixed_priority = EMDRV_DMADRV_DMA_CH_PRIORITY; +#endif + + CORE_ENTER_ATOMIC(); + if ( initialized ) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED; + } + initialized = true; + CORE_EXIT_ATOMIC(); + + if ( EMDRV_DMADRV_DMA_IRQ_PRIORITY >= (1 << __NVIC_PRIO_BITS) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + chTable[i].allocated = false; + } + +#if defined(EMDRV_DMADRV_UDMA) + NVIC_SetPriority(DMA_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + dmaInit.hprot = 0; + dmaInit.controlBlock = dmaControlBlock; + DMA_Init(&dmaInit); +#elif defined(EMDRV_DMADRV_LDMA) + dmaInit.ldmaInitIrqPriority = EMDRV_DMADRV_DMA_IRQ_PRIORITY; + LDMA_Init(&dmaInit); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_LDMA0); + sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_LDMAXBAR0); + sl_hal_ldma_init(LDMA0, &dmaInit); + + NVIC_ClearPendingIRQ(LDMA0_CHNL0_IRQn); + NVIC_ClearPendingIRQ(LDMA0_CHNL1_IRQn); + NVIC_ClearPendingIRQ(LDMA0_CHNL2_IRQn); + NVIC_ClearPendingIRQ(LDMA0_CHNL3_IRQn); + NVIC_ClearPendingIRQ(LDMA0_CHNL4_IRQn); + NVIC_ClearPendingIRQ(LDMA0_CHNL5_IRQn); + NVIC_ClearPendingIRQ(LDMA0_CHNL6_IRQn); + NVIC_ClearPendingIRQ(LDMA0_CHNL7_IRQn); + + NVIC_SetPriority(LDMA0_CHNL0_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA0_CHNL1_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA0_CHNL2_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA0_CHNL3_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA0_CHNL4_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA0_CHNL5_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA0_CHNL6_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA0_CHNL7_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + + NVIC_EnableIRQ(LDMA0_CHNL0_IRQn); + NVIC_EnableIRQ(LDMA0_CHNL1_IRQn); + NVIC_EnableIRQ(LDMA0_CHNL2_IRQn); + NVIC_EnableIRQ(LDMA0_CHNL3_IRQn); + NVIC_EnableIRQ(LDMA0_CHNL4_IRQn); + NVIC_EnableIRQ(LDMA0_CHNL5_IRQn); + NVIC_EnableIRQ(LDMA0_CHNL6_IRQn); + NVIC_EnableIRQ(LDMA0_CHNL7_IRQn); + + sl_hal_ldma_enable(LDMA0); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +#if defined(EMDRV_DMADRV_LDMA) || defined(DOXYGEN) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + * + * @details + * This function is similar to the emlib LDMA function. + * + * @param[in] channelId + * The channel ID to use. + * + * @param[in] transfer + * A DMA transfer configuration data structure. + * + * @param[in] descriptor + * A DMA transfer descriptor, can be an array of descriptors linked together. + * + * @param[in] callback + * An optional callback function for signalling completion. May be NULL if not + * needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. May be NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + LDMA_TransferCfg_t *transfer, + LDMA_Descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= (int)EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + LDMA_StartTransfer(channelId, transfer, descriptor); + + return ECODE_EMDRV_DMADRV_OK; +} +#elif defined(EMDRV_DMADRV_LDMA_S3) +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + sl_hal_ldma_transfer_config_t *transfer, + sl_hal_ldma_descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= (int)EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + sl_hal_ldma_init_transfer(LDMA0, channelId, transfer, descriptor); + sl_hal_ldma_enable_interrupts(LDMA0, (1 << channelId)); + sl_hal_ldma_start_transfer(LDMA0, channelId); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif + +/***************************************************************************//** + * @brief + * Start a memory to a peripheral DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination (peripheral register) memory address. + * + * @param[in] src + * A source memory address. + * + * @param[in] srcInc + * Set to true to enable source address increment (increments according to + * @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModeBasic, + dmaDirectionMemToPeripheral, + channelId, + peripheralSignal, + dst, + src, + NULL, + srcInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a memory to a peripheral ping-pong DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination (peripheral register) memory address. + * + * @param[in] src0 + * A source memory address of the first (ping) buffer. + * + * @param[in] src1 + * A source memory address of the second (pong) buffer. + * + * @param[in] srcInc + * Set to true to enable source address increment (increments according to + * @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_MemoryPeripheralPingPong( + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src0, + void *src1, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModePingPong, + dmaDirectionMemToPeripheral, + channelId, + peripheralSignal, + dst, + src0, + src1, + srcInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a peripheral to memory DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination memory address. + * + * @param[in] src + * A source memory (peripheral register) address. + * + * @param[in] dstInc + * Set to true to enable destination address increment (increments according + * to @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModeBasic, + dmaDirectionPeripheralToMem, + channelId, + peripheralSignal, + dst, + src, + NULL, + dstInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a peripheral to memory ping-pong DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst0 + * A destination memory address of the first (ping) buffer. + * + * @param[in] dst1 + * A destination memory address of the second (pong) buffer. + * + * @param[in] src + * A source memory (peripheral register) address. + * + * @param[in] dstInc + * Set to true to enable destination address increment (increments according + * to @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PeripheralMemoryPingPong( + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst0, + void *dst1, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModePingPong, + dmaDirectionPeripheralToMem, + channelId, + peripheralSignal, + dst0, + dst1, + src, + dstInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Pause an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to pause. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PauseTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelRequestEnable(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_EnableChannelRequest(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_disable_channel_request(LDMA0, channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Resume an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to resume. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_ResumeTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelRequestEnable(channelId, true); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_EnableChannelRequest(channelId, true); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_enable_channel_request(LDMA0, channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Stop an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to stop. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_StopTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelEnable(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_StopTransfer(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_stop_transfer(LDMA0, channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer is running. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] active + * True if transfer is running, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (active == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + if ( DMA_ChannelEnabled(channelId) ) +#elif defined(EMDRV_DMADRV_LDMA) + if ( LDMA_ChannelEnabled(channelId) ) +#elif defined(EMDRV_DMADRV_LDMA_S3) + if ( sl_hal_ldma_channel_is_enabled(LDMA0, channelId) ) +#endif + { + *active = true; + } else { + *active = false; + } + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer complete is pending. + * + * @details + * Will check the channel interrupt flag. This assumes that the DMA is configured + * to give a completion interrupt. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] pending + * True if a transfer complete is pending, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (pending == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + if ( DMA->IF & (1 << channelId) ) +#elif defined(EMDRV_DMADRV_LDMA) + if ( LDMA->IF & (1 << channelId) ) +#elif defined(EMDRV_DMADRV_LDMA_S3) + if ( sl_hal_ldma_get_pending_interrupts(LDMA0) & (1 << channelId) ) +#endif + { + *pending = true; + } else { + *pending = false; + } + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer has completed. + * + * @note + * This function should be used in a polled environment. + * Will only work reliably for transfers NOT using the completion interrupt. + * On UDMA, it will only work on basic transfers on the primary channel. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] done + * True if a transfer has completed, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done) +{ +#if defined(EMDRV_DMADRV_UDMA) + uint32_t remaining, iflag; +#endif + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (done == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + CORE_ATOMIC_SECTION( + /* This works for primary channel only ! */ + remaining = (dmaControlBlock[channelId].CTRL + & _DMA_CTRL_N_MINUS_1_MASK) + >> _DMA_CTRL_N_MINUS_1_SHIFT; + iflag = DMA->IF; + ) + + if ( (remaining == 0) && (iflag & (1 << channelId)) ) { + *done = true; + } else { + *done = false; + } +#elif defined(EMDRV_DMADRV_LDMA) + *done = LDMA_TransferDone(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + *done = sl_hal_ldma_transfer_is_done(LDMA0, channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Get number of items remaining in a transfer. + * + * @note + * This function does not take into account that a DMA transfer with + * a chain of linked transfers might be ongoing. It will only check the + * count for the current transfer. + * On UDMA, it will only work on the primary channel. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] remaining + * A number of items remaining in the transfer. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, + int *remaining) +{ +#if defined(EMDRV_DMADRV_UDMA) + uint32_t remain, iflag; +#endif + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (remaining == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + CORE_ATOMIC_SECTION( + /* This works for the primary channel only ! */ + remain = (dmaControlBlock[channelId].CTRL + & _DMA_CTRL_N_MINUS_1_MASK) + >> _DMA_CTRL_N_MINUS_1_SHIFT; + iflag = DMA->IF; + ) + + if ( (remain == 0) && (iflag & (1 << channelId)) ) { + *remaining = 0; + } else { + *remaining = 1 + remain; + } +#elif defined(EMDRV_DMADRV_LDMA) + *remaining = LDMA_TransferRemainingCount(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + *remaining = sl_hal_ldma_transfer_remaining_count(LDMA0, channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(EMDRV_DMADRV_LDMA) +/***************************************************************************//** + * @brief + * An interrupt handler for LDMA. + ******************************************************************************/ +void LDMA_IRQHandler(void) +{ + bool stop; + ChTable_t *ch; + uint32_t pending, chnum, chmask; + + /* Get all pending and enabled interrupts. */ + pending = LDMA->IF; + pending &= LDMA->IEN; + + /* Check for LDMA error. */ + if ( pending & LDMA_IF_ERROR ) { + /* Loop to enable debugger to see what has happened. */ + while (true) { + /* Wait forever. */ + } + } + + /* Iterate over all LDMA channels. */ + for ( chnum = 0, chmask = 1; + chnum < EMDRV_DMADRV_DMA_CH_COUNT; + chnum++, chmask <<= 1 ) { + if ( pending & chmask ) { + /* Clear the interrupt flag. */ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chmask; +#else + LDMA->IFC = chmask; +#endif + + ch = &chTable[chnum]; + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); + + if ( (ch->mode == dmaModePingPong) && stop ) { + dmaXfer[chnum].desc[0].xfer.link = 0; + dmaXfer[chnum].desc[1].xfer.link = 0; + } + } + } + } +} +#endif /* defined( EMDRV_DMADRV_LDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA_S3) +/***************************************************************************//** + * @brief + * Default interrupt handler for LDMA common to all interrupt channel lines. + * + * @param[in] chnum + * The channel ID responsible for the interrupt signal trigger. + ******************************************************************************/ +static void LDMA_IRQHandlerDefault(uint8_t chnum) +{ + bool stop; + ChTable_t *ch; + uint32_t pending; + uint32_t chmask; + + /* Get all pending and enabled interrupts. */ + pending = sl_hal_ldma_get_enabled_pending_interrupts(LDMA0); + + /* Check for LDMA error. */ + if ( pending & (LDMA_IF_ERROR0 << chnum) ) { + /* Loop to enable debugger to see what has happened. */ + while (true) { + /* Wait forever. */ + } + } + + chmask = 1 << chnum; + if ( pending & chmask ) { + /* Clear the interrupt flag. */ + sl_hal_ldma_clear_interrupts(LDMA0, chmask); + + /* Callback called if it was provided for the given channel. */ + ch = &chTable[chnum]; + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); + + /* Continue or not a ping-pong transfer. */ + if ( (ch->mode == dmaModePingPong) && stop ) { + dmaXfer[chnum].desc[0].xfer.link = 0; + dmaXfer[chnum].desc[1].xfer.link = 0; + } + } + } +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 0. + ******************************************************************************/ +void LDMA0_CHNL0_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(0); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 1. + ******************************************************************************/ +void LDMA0_CHNL1_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(1); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 2. + ******************************************************************************/ +void LDMA0_CHNL2_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(2); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 3. + ******************************************************************************/ +void LDMA0_CHNL3_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(3); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 4. + ******************************************************************************/ +void LDMA0_CHNL4_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(4); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 5. + ******************************************************************************/ +void LDMA0_CHNL5_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(5); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 6. + ******************************************************************************/ +void LDMA0_CHNL6_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(6); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 7. + ******************************************************************************/ +void LDMA0_CHNL7_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(7); +} + +#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * A callback function for UDMA basic transfers. + ******************************************************************************/ +static void DmaBasicCallback(unsigned int channel, bool primary, void *user) +{ + ChTable_t *ch = &chTable[channel]; + (void)user; + (void)primary; + + if ( ch->callback != NULL ) { + ch->callbackCount++; + ch->callback(channel, ch->callbackCount, ch->userParam); + } +} +#endif + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * A callback function for UDMA ping-pong transfers. + ******************************************************************************/ +static void DmaPingPongCallback(unsigned int channel, bool primary, void *user) +{ + bool stop = true; + ChTable_t *ch = &chTable[channel]; + + (void)user; + + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(channel, ch->callbackCount, ch->userParam); + } + + DMA_RefreshPingPong(channel, + primary, + false, + NULL, + NULL, + ch->length - 1, + stop); +} +#endif + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * Start a UDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + DMA_CfgChannel_TypeDef chCfg; + DMA_CfgDescr_TypeDef descrCfg; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + /* Se tup the interrupt callback routine. */ + if ( mode == dmaModeBasic ) { + dmaCallBack[channelId].cbFunc = DmaBasicCallback; + } else { + dmaCallBack[channelId].cbFunc = DmaPingPongCallback; + } + dmaCallBack[channelId].userPtr = NULL; + + /* Set up the channel */ + chCfg.highPri = false; /* Can't use hi pri with peripherals. */ + + /* Whether the interrupt is needed. */ + if ( (callback != NULL) || (mode == dmaModePingPong) ) { + chCfg.enableInt = true; + } else { + chCfg.enableInt = false; + } + chCfg.select = peripheralSignal; + chCfg.cb = &dmaCallBack[channelId]; + DMA_CfgChannel(channelId, &chCfg); + + /* Set up the channel descriptor. */ + if ( direction == dmaDirectionMemToPeripheral ) { + if ( bufInc ) { + if ( size == dmadrvDataSize1 ) { + descrCfg.srcInc = dmaDataInc1; + } else if ( size == dmadrvDataSize2 ) { + descrCfg.srcInc = dmaDataInc2; + } else { /* dmadrvDataSize4 */ + descrCfg.srcInc = dmaDataInc4; + } + } else { + descrCfg.srcInc = dmaDataIncNone; + } + descrCfg.dstInc = dmaDataIncNone; + } else { + if ( bufInc ) { + if ( size == dmadrvDataSize1 ) { + descrCfg.dstInc = dmaDataInc1; + } else if ( size == dmadrvDataSize2 ) { + descrCfg.dstInc = dmaDataInc2; + } else { /* dmadrvDataSize4 */ + descrCfg.dstInc = dmaDataInc4; + } + } else { + descrCfg.dstInc = dmaDataIncNone; + } + descrCfg.srcInc = dmaDataIncNone; + } + descrCfg.size = (DMA_DataSize_TypeDef)size; + descrCfg.arbRate = dmaArbitrate1; + descrCfg.hprot = 0; + DMA_CfgDescr(channelId, true, &descrCfg); + if ( mode == dmaModePingPong ) { + DMA_CfgDescr(channelId, false, &descrCfg); + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->length = len; + + DMA->IFC = 1 << channelId; + + /* Start the DMA cycle. */ + if ( mode == dmaModeBasic ) { + DMA_ActivateBasic(channelId, true, false, buf0, buf1, len - 1); + } else { + if ( direction == dmaDirectionMemToPeripheral ) { + DMA_ActivatePingPong(channelId, + false, + buf0, /* dest */ + buf1, /* src */ + len - 1, + buf0, /* dest */ + buf2, /* src */ + len - 1); + } else { + DMA_ActivatePingPong(channelId, + false, + buf0, /* dest */ + buf2, /* src */ + len - 1, + buf1, /* dest */ + buf2, /* src */ + len - 1); + } + } + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_UDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + LDMA_TransferCfg_t xfer; + LDMA_Descriptor_t *desc; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + xfer = xferCfgPeripheral; + desc = &dmaXfer[channelId].desc[0]; + + if ( direction == dmaDirectionMemToPeripheral ) { + *desc = m2p; + if ( !bufInc ) { + desc->xfer.srcInc = ldmaCtrlSrcIncNone; + } + } else { + *desc = p2m; + if ( !bufInc ) { + desc->xfer.dstInc = ldmaCtrlDstIncNone; + } + } + + xfer.ldmaReqSel = peripheralSignal; + desc->xfer.xferCnt = len - 1; + desc->xfer.dstAddr = (uint32_t)(uint8_t *)buf0; + desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf1; + desc->xfer.size = size; + + if ( mode == dmaModePingPong ) { + desc->xfer.linkMode = ldmaLinkModeRel; + desc->xfer.link = 1; + desc->xfer.linkAddr = 4; /* Refer to the "pong" descriptor. */ + + /* Set the "pong" descriptor equal to the "ping" descriptor. */ + dmaXfer[channelId].desc[1] = *desc; + /* Refer to the "ping" descriptor. */ + dmaXfer[channelId].desc[1].xfer.linkAddr = -4; + dmaXfer[channelId].desc[1].xfer.srcAddr = (uint32_t)(uint8_t *)buf2; + + if ( direction == dmaDirectionPeripheralToMem ) { + dmaXfer[channelId].desc[1].xfer.dstAddr = (uint32_t)(uint8_t *)buf1; + desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf2; + } + } + + /* Whether an interrupt is needed. */ + if ( (callback == NULL) && (mode == dmaModeBasic) ) { + desc->xfer.doneIfs = 0; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->mode = mode; + + LDMA_StartTransfer(channelId, &xfer, desc); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_LDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA_S3) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + sl_hal_ldma_transfer_config_t xfer; + sl_hal_ldma_descriptor_t *desc; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + xfer = xferCfgPeripheral; + desc = &dmaXfer[channelId].desc[0]; + + if ( direction == dmaDirectionMemToPeripheral ) { + *desc = m2p; + if ( !bufInc ) { + desc->xfer.src_inc = SL_HAL_LDMA_CTRL_SRC_INC_NONE; + } + } else { + *desc = p2m; + if ( !bufInc ) { + desc->xfer.dst_inc = SL_HAL_LDMA_CTRL_DST_INC_NONE; + } + } + + xfer.request_sel = peripheralSignal; + desc->xfer.xfer_count = len - 1; + desc->xfer.dst_addr = (uint32_t)(uint8_t *)buf0; + desc->xfer.src_addr = (uint32_t)(uint8_t *)buf1; + desc->xfer.size = size; + + if ( mode == dmaModePingPong ) { + desc->xfer.link_mode = SL_HAL_LDMA_LINK_MODE_REL; + desc->xfer.link = 1; + desc->xfer.link_addr = 4; /* Refer to the "pong" descriptor. */ + + /* Set the "pong" descriptor equal to the "ping" descriptor. */ + dmaXfer[channelId].desc[1] = *desc; + /* Refer to the "ping" descriptor. */ + dmaXfer[channelId].desc[1].xfer.link_addr = -4; + dmaXfer[channelId].desc[1].xfer.src_addr = (uint32_t)(uint8_t *)buf2; + + if ( direction == dmaDirectionPeripheralToMem ) { + dmaXfer[channelId].desc[1].xfer.dst_addr = (uint32_t)(uint8_t *)buf1; + desc->xfer.src_addr = (uint32_t)(uint8_t *)buf2; + } + } + + /* Whether an interrupt is needed. */ + if ( (callback == NULL) && (mode == dmaModeBasic) ) { + desc->xfer.done_ifs = 0; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->mode = mode; + + sl_hal_ldma_init_transfer(LDMA0, channelId, &xfer, desc); + sl_hal_ldma_start_transfer(LDMA0, channelId); + sl_hal_ldma_enable_interrupts(LDMA0, (0x1UL << channelId)); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ + +/// @endcond + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup dmadrv DMADRV - DMA Driver +/// @brief Direct Memory Access Driver +/// @{ +/// +/// @details +/// +/// +/// @n @section dmadrv_intro Introduction +/// +/// The DMADRV driver supports writing code using DMA which will work +/// regardless of the type of the DMA controller on the underlying microcontroller. +/// Additionally, DMA can be used in several modules that are +/// completely unaware of each other. +/// The driver does not preclude use of the native emlib or peripheral API of the +/// underlying DMA controller. On the contrary, it will often result in more efficient +/// code and is necessary for complex DMA operations. The housekeeping +/// functions of this driver are valuable even in this use-case. +/// +/// The dmadrv.c and dmadrv.h source files are in the +/// emdrv/dmadrv folder. +/// +/// @note DMA transfer completion callback functions are called from within the +/// DMA interrupt handler. On versions of the DMA controller with one interrupt per +/// channel, the callback function is called from its respective channel interrupt +/// handler. +/// +/// @n @section dmadrv_conf Configuration Options +/// +/// Some properties of the DMADRV driver are compile-time configurable. These +/// properties are stored in a file named dmadrv_config.h. A template for this +/// file, containing default values, is in the emdrv/config folder. IC specific +/// versions of dmadrv_config.h files are available in config/sx_xch directories. +/// Currently the configuration options are as follows: +/// @li The interrupt priority of the DMA peripheral. +/// @li A number of DMA channels to support. +/// @li Use the native emlib/peripheral API belonging to the underlying DMA hardware in +/// combination with the DMADRV API. +/// +/// Both configuration options will help reduce the driver's RAM footprint. +/// +/// To configure DMADRV, provide a custom configuration file. This is an +/// example dmadrv_config.h file: +/// @code{.c} +/// #ifndef __SILICON_LABS_DMADRV_CONFIG_H__ +/// #define __SILICON_LABS_DMADRV_CONFIG_H__ +/// +/// // DMADRV DMA interrupt priority configuration option. +/// // Set DMA interrupt priority. Range is 0..7, 0 is the highest priority. +/// #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 +/// +/// // DMADRV channel count configuration option. +/// // A number of DMA channels to support. A lower DMA channel count will reduce +/// // RAM footprint. +/// #define EMDRV_DMADRV_DMA_CH_COUNT 4 +/// +/// #endif +/// @endcode +/// +/// @n @section dmadrv_api The API +/// +/// This section contains brief descriptions of the API functions. +/// For more information about input and output parameters and return values, +/// click on the hyperlinked function names. Most functions return an error +/// code, @ref ECODE_EMDRV_DMADRV_OK is returned on success, +/// see @ref ecode and @ref dmadrv_error_codes for other error codes. +/// +/// The application code must include @em dmadrv.h header file. +/// +/// @ref DMADRV_Init(), @ref DMADRV_DeInit() @n +/// These functions initialize or deinitialize the DMADRV driver. Typically, +/// DMADRV_Init() is called once in the startup code. +/// +/// @ref DMADRV_AllocateChannel(), @ref DMADRV_FreeChannel() @n +/// DMA channel reserve and release functions. It is recommended that +/// application code check that DMADRV_AllocateChannel() +/// returns ECODE_EMDRV_DMADRV_OK before starting a DMA +/// transfer. +/// +/// @ref DMADRV_MemoryPeripheral() @n +/// Start a DMA transfer from memory to a peripheral. +/// +/// @ref DMADRV_PeripheralMemory() @n +/// Start a DMA transfer from a peripheral to memory. +/// +/// @ref DMADRV_MemoryPeripheralPingPong() @n +/// Start a DMA ping-pong transfer from memory to a peripheral. +/// +/// @ref DMADRV_PeripheralMemoryPingPong() @n +/// Start a DMA ping-pong transfer from a peripheral to memory. +/// +/// @ref DMADRV_LdmaStartTransfer() @n +/// Start a DMA transfer on an LDMA controller. +/// +/// @ref DMADRV_PauseTransfer() @n +/// Pause an ongoing DMA transfer. +/// +/// @ref DMADRV_ResumeTransfer() @n +/// Resume paused DMA transfer. +/// +/// @ref DMADRV_StopTransfer() @n +/// Stop an ongoing DMA transfer. +/// +/// @ref DMADRV_TransferActive() @n +/// Check if a transfer is ongoing. +/// +/// @ref DMADRV_TransferCompletePending() @n +/// Check if a transfer completion is pending. +/// +/// @ref DMADRV_TransferDone() @n +/// Check if a transfer has completed. +/// +/// @ref DMADRV_TransferRemainingCount() @n +/// Get number of items remaining in a transfer. +/// +/// @n @section dmadrv_example Example +/// Transfer a text string to USART1. +/// @code{.c} +/// #include "dmadrv.h" +/// +/// char str[] = "Hello DMA !"; +/// unsigned int channel; +/// +/// int main( void ) +/// { +/// // Initialize DMA. +/// DMADRV_Init(); +/// +/// // Request a DMA channel. +/// DMADRV_AllocateChannel( &channel, NULL ); +/// +/// // Start the DMA transfer. +/// DMADRV_MemoryPeripheral( channel, +/// dmadrvPeripheralSignal_USART1_TXBL, +/// (void*)&(USART1->TXDATA), +/// str, +/// true, +/// sizeof( str ), +/// dmadrvDataSize1, +/// NULL, +/// NULL ); +/// +/// return 0; +/// } +/// @endcode +/// +/// @} end group dmadrv ******************************************************** diff --git a/simplicity_sdk/platform/emlib/inc/em_acmp.h b/simplicity_sdk/platform/emlib/inc/em_acmp.h index 3079df84f..33e5cc418 100644 --- a/simplicity_sdk/platform/emlib/inc/em_acmp.h +++ b/simplicity_sdk/platform/emlib/inc/em_acmp.h @@ -1136,6 +1136,28 @@ __STATIC_INLINE ACMP_Channel_TypeDef ACMP_PortPinToInput(GPIO_Port_TypeDef port, } #endif +/***************************************************************************//** + * @brief + * Get state of ACMP output value + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @return + * State of ACMP output value + ******************************************************************************/ +__STATIC_INLINE bool ACMP_OutputGet(ACMP_TypeDef *acmp) +{ + /* Waiting for ACMP is ready*/ +#if defined(ACMP_STATUS_ACMPRDY) + while (!(acmp->STATUS & ACMP_STATUS_ACMPRDY)) ; +#elif defined(ACMP_STATUS_ACMPACT) + while (!(acmp->STATUS & ACMP_STATUS_ACMPACT)) ; +#endif + + return (acmp->STATUS & ACMP_STATUS_ACMPOUT); +} + /** @} (end addtogroup acmp) */ #ifdef __cplusplus diff --git a/simplicity_sdk/platform/emlib/inc/em_chip.h b/simplicity_sdk/platform/emlib/inc/em_chip.h index 1de476ae6..b19b7448b 100644 --- a/simplicity_sdk/platform/emlib/inc/em_chip.h +++ b/simplicity_sdk/platform/emlib/inc/em_chip.h @@ -42,6 +42,10 @@ #include "em_gpio.h" #endif +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_240) +#include "em_cmu.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -411,6 +415,23 @@ __STATIC_INLINE void CHIP_Init(void) } } #endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_240) + + // Enable ICache out of reset. + CMU->CLKEN1_SET = _CMU_CLKEN1_ICACHE0_MASK; + ICACHE0->CTRL_CLR = _ICACHE_CTRL_CACHEDIS_MASK; + CMU->CLKEN1_CLR = _CMU_CLKEN1_ICACHE0_MASK; + + CMU->CLKEN0_SET = _CMU_CLKEN0_HFRCO0_MASK; + + if (((HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT) == _HFRCO_CAL_TUNING_MASK) { + CMU_HFRCODPLLBandSet(cmuHFRCODPLLFreq_19M0Hz); + } + + CMU->CLKEN0_CLR = _CMU_CLKEN0_HFRCO0_MASK; + +#endif } /**************************************************************************//** diff --git a/simplicity_sdk/platform/emlib/inc/em_dbg.h b/simplicity_sdk/platform/emlib/inc/em_dbg.h index f69acefa3..ae8c55c2d 100644 --- a/simplicity_sdk/platform/emlib/inc/em_dbg.h +++ b/simplicity_sdk/platform/emlib/inc/em_dbg.h @@ -88,10 +88,6 @@ __STATIC_INLINE bool DBG_Connected(void) void DBG_SWOEnable(unsigned int location); #endif -#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) -void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode); -#endif - #if defined (EMU_CTRL_EM2DBGEN) /***************************************************************************//** * @brief diff --git a/simplicity_sdk/platform/emlib/inc/em_emu.h b/simplicity_sdk/platform/emlib/inc/em_emu.h index 6ff497e23..b205c0c10 100644 --- a/simplicity_sdk/platform/emlib/inc/em_emu.h +++ b/simplicity_sdk/platform/emlib/inc/em_emu.h @@ -226,6 +226,28 @@ typedef enum { } EMU_EM4PinRetention_TypeDef; #endif +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +/** HDREG Stop Gear Max Current Type. */ +typedef enum { + /** HDREG current limit is 4mA. */ + emuHdregStopGearILmt4mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA, + /** HDREG current limit is 8mA. */ + emuHdregStopGearILmt8mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA, + /** HDREG current limit is 12mA. */ + emuHdregStopGearILmt12mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA, + /** HDREG current limit is 16mA. */ + emuHdregStopGearILmt16mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA, + /** HDREG current limit is 24mA. */ + emuHdregStopGearILmt24mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA, + /** HDREG current limit is 48mA. */ + emuHdregStopGearILmt48mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA, + /** HDREG current limit is 64mA. */ + emuHdregStopGearILmt64mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA, + /** HDREG current limit is 64mA. */ + emuHdregStopGearILmtMax = _EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX, +} EMU_HdregStopGearILmt_TypeDef; +#endif + /** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ typedef enum { /** DCDC is connected to DVDD. */ @@ -504,6 +526,20 @@ typedef enum { typedef enum { emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */ } EMU_DcdcBoostEM23PeakCurrent_TypeDef; + +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +/** DCDC Boost output voltage */ +typedef enum { + emuDcdcBoostOutputVoltage_1v8 = _DCDC_CTRL_DVDDBSTPRG_BOOST_1V8, /**< Output voltage is 1.8V. */ + emuDcdcBoostOutputVoltage_1v9 = _DCDC_CTRL_DVDDBSTPRG_BOOST_1V9, /**< Output voltage is 1.9V. */ + emuDcdcBoostOutputVoltage_2v0 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V, /**< Output voltage is 2.0V. */ + emuDcdcBoostOutputVoltage_2v1 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V1, /**< Output voltage is 2.1V. */ + emuDcdcBoostOutputVoltage_2v2 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V2, /**< Output voltage is 2.2V. */ + emuDcdcBoostOutputVoltage_2v3 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V3, /**< Output voltage is 2.3V. */ + emuDcdcBoostOutputVoltage_2v4 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V4, /**< Output voltage is 2.4V. */ +} EMU_DcdcBoostOutputVoltage_TypeDef; +#endif + #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */ #if defined(EMU_STATUS_VMONRDY) @@ -713,15 +749,25 @@ typedef enum { is always enabled. */ typedef struct { bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */ +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) + EMU_HdregStopGearILmt_TypeDef current; /**< limit HDREG max current capability. */ +#endif } EMU_EM01Init_TypeDef; /** Default initialization of EM0 and 1 configuration. */ -#define EMU_EM01INIT_DEFAULT \ - { \ - false /* Do not scale down in EM0/1.*/ \ +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +#define EMU_EM01INIT_DEFAULT \ + { \ + false, /* Do not scale down in EM0/1.*/ \ + emuHdregStopGearILmt64mA /* HDREG current limit is 64mA. */ \ + } +#else +#define EMU_EM01INIT_DEFAULT \ + { \ + false /* Do not scale down in EM0/1.*/ \ } #endif - +#endif /** EM2 and 3 initialization structure. */ typedef struct { bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */ @@ -743,7 +789,6 @@ typedef struct { false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ } #endif - #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) /** EM4 initialization structure. */ typedef struct { @@ -886,18 +931,34 @@ typedef struct { EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) + EMU_DcdcBoostOutputVoltage_TypeDef outputVoltage; /**< DCDC Boost output voltage. */ +#endif } EMU_DCDCBoostInit_TypeDef; /** Default DCDC Boost initialization. */ +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +#define EMU_DCDCBOOSTINIT_DEFAULT \ + { \ + emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcBoostEM01PeakCurrent_Load23mA, /**< Default peak current in EM0/1. */ \ + emuDcdcBoostEM23PeakCurrent_Load10mA, /**< Default peak current in EM2/3. */ \ + emuDcdcBoostOutputVoltage_1v8 /**< DCDC Boost output voltage. */ \ + } +#else #define EMU_DCDCBOOSTINIT_DEFAULT \ { \ emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \ + emuDcdcBoostEM01PeakCurrent_Load23mA, /**< Default peak current in EM0/1. */ \ emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \ } +#endif #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) @@ -1192,6 +1253,9 @@ void EMU_DCDCUpdatedHook(void); bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit); void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01); void EMU_BoostExternalShutdownEnable(bool enable); +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +void EMU_DCDCBoostOutputVoltageSet(const EMU_DcdcBoostOutputVoltage_TypeDef boostOutputVoltage); +#endif #endif #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ @@ -1241,7 +1305,12 @@ void EMU_EFPDriveDecoupleSet(bool enable); #if defined(EMU_CTRL_EFPDRVDVDD) void EMU_EFPDriveDvddSet(bool enable); #endif - +#if defined(_EMU_CTRL_HDREGEM2EXITCLIM_MASK) +void EMU_HDRegEM2ExitCurrentLimitEnable(bool enable); +#endif +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +void EMU_HDRegStopGearSet(EMU_HdregStopGearILmt_TypeDef current); +#endif #if defined(_DCDC_CTRL_MASK) /***************************************************************************//** * @brief diff --git a/simplicity_sdk/platform/emlib/inc/em_gpio.h b/simplicity_sdk/platform/emlib/inc/em_gpio.h index db31760a2..9bca763b7 100644 --- a/simplicity_sdk/platform/emlib/inc/em_gpio.h +++ b/simplicity_sdk/platform/emlib/inc/em_gpio.h @@ -40,6 +40,10 @@ #include "sl_common.h" #include "sl_enum.h" +#if defined(SL_CATALOG_GPIO_PRESENT) +#include "sl_device_gpio.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -48,6 +52,50 @@ extern "C" { ******************************* DEFINES *********************************** ******************************************************************************/ +#ifdef gpioPortA +#undef gpioPortA +#endif + +#ifdef gpioPortB +#undef gpioPortB +#endif + +#ifdef gpioPortC +#undef gpioPortC +#endif + +#ifdef gpioPortD +#undef gpioPortD +#endif + +#ifdef gpioPortE +#undef gpioPortE +#endif + +#ifdef gpioPortF +#undef gpioPortF +#endif + +#ifdef gpioPortG +#undef gpioPortG +#endif + +#ifdef gpioPortH +#undef gpioPortH +#endif + +#ifdef gpioPortI +#undef gpioPortI +#endif + +#ifdef gpioPortJ +#undef gpioPortJ +#endif + +#ifdef gpioPortK +#undef gpioPortK +#endif + #if defined(_SILICON_LABS_32B_SERIES_0) \ && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) @@ -514,6 +562,43 @@ SL_ENUM(GPIO_Port_TypeDef) { #endif }; +/** Mapping between SL_GPIO_PORT_ enums and gpioPort values. */ +#if !defined(SL_CATALOG_GPIO_PRESENT) +#if (_GPIO_PORT_A_PIN_COUNT > 0) +#define SL_GPIO_PORT_A gpioPortA +#endif +#if (_GPIO_PORT_B_PIN_COUNT > 0) +#define SL_GPIO_PORT_B gpioPortB +#endif +#if (_GPIO_PORT_C_PIN_COUNT > 0) +#define SL_GPIO_PORT_C gpioPortC +#endif +#if (_GPIO_PORT_D_PIN_COUNT > 0) +#define SL_GPIO_PORT_D gpioPortD +#endif +#if (_GPIO_PORT_E_PIN_COUNT > 0) +#define SL_GPIO_PORT_E gpioPortE +#endif +#if (_GPIO_PORT_F_PIN_COUNT > 0) +#define SL_GPIO_PORT_F gpioPortF +#endif +#if (_GPIO_PORT_G_PIN_COUNT > 0) +#define SL_GPIO_PORT_G gpioPortG +#endif +#if (_GPIO_PORT_H_PIN_COUNT > 0) +#define SL_GPIO_PORT_H gpioPortH +#endif +#if (_GPIO_PORT_I_PIN_COUNT > 0) +#define SL_GPIO_PORT_I gpioPortI +#endif +#if (_GPIO_PORT_J_PIN_COUNT > 0) +#define SL_GPIO_PORT_J gpioPortJ +#endif +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define SL_GPIO_PORT_K gpioPortK +#endif +#endif // !defined(SL_CATALOG_GPIO_PRESENT) + #if defined(_GPIO_P_CTRL_DRIVEMODE_MASK) /** GPIO drive mode. */ SL_ENUM_GENERIC(GPIO_DriveMode_TypeDef, uint32_t) { diff --git a/simplicity_sdk/platform/emlib/inc/em_msc.h b/simplicity_sdk/platform/emlib/inc/em_msc.h index d7fe03089..9b097bdff 100644 --- a/simplicity_sdk/platform/emlib/inc/em_msc.h +++ b/simplicity_sdk/platform/emlib/inc/em_msc.h @@ -171,8 +171,15 @@ typedef enum { mscDmemMasterLDMA = _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT, mscDmemMasterSRWAES = _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT, mscDmemMasterAHBSRW = _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT, +#if defined(_SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_MASK) + mscDmemMasterIFADCDEBUG = _SYSCFG_DMEM0PORTMAPSEL_IFADCDEBUGPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK) mscDmemMasterSRWECA0 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK) mscDmemMasterSRWECA1 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT, +#endif #if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK) mscDmemMasterMVPAHBDATA0 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT, #endif diff --git a/simplicity_sdk/platform/emlib/inc/em_se.h b/simplicity_sdk/platform/emlib/inc/em_se.h index 81e02da45..d7bff9c73 100644 --- a/simplicity_sdk/platform/emlib/inc/em_se.h +++ b/simplicity_sdk/platform/emlib/inc/em_se.h @@ -30,6 +30,10 @@ #ifndef EM_SE_H #define EM_SE_H +#ifndef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2024_6 +#warning "This file is deprecated as of SiSDK 2024.6. The content was moved to sli_se_manager_mailbox.h." +#endif + #if defined(__linux__) #define SLI_EM_SE_HOST diff --git a/simplicity_sdk/platform/emlib/inc/em_smu.h b/simplicity_sdk/platform/emlib/inc/em_smu.h index 7fa121ae2..c36cf9826 100755 --- a/simplicity_sdk/platform/emlib/inc/em_smu.h +++ b/simplicity_sdk/platform/emlib/inc/em_smu.h @@ -1383,7 +1383,7 @@ typedef struct { bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) - bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ @@ -1414,26 +1414,24 @@ typedef struct { bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ - - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ - bool privilegedSEPUF : 1; /**< Privileged access enabler for SEPUF */ bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ #else #error "No peripherals defined for SMU for this device configuration" diff --git a/simplicity_sdk/platform/emlib/inc/sli_em_cmu.h b/simplicity_sdk/platform/emlib/inc/sli_em_cmu.h index f683662ba..09053842e 100644 --- a/simplicity_sdk/platform/emlib/inc/sli_em_cmu.h +++ b/simplicity_sdk/platform/emlib/inc/sli_em_cmu.h @@ -342,10 +342,10 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void); #define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK #define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK -#define CMU_SYSTICK_SELECT_HCLK \ - do { \ - sli_em_cmu_SYSTICEXTCLKENClear(); \ - SysTick->CTRL = (SysTick->CTRL | ~SysTick_CTRL_CLKSOURCE_Msk); \ +#define CMU_SYSTICK_SELECT_HCLK \ + do { \ + sli_em_cmu_SYSTICEXTCLKENClear(); \ + SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); \ } while (0) #define CMU_EM23GRPACLK_SELECT_LFRCO \ @@ -854,12 +854,12 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void); #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ #endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23) #define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ do { \ CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ } while (0) - #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 #define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ @@ -872,6 +872,7 @@ void sli_em_cmu_SYSTICEXTCLKENClear(void); #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 #define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif #define CMU_EM01GRPCCLK_SELECT_FSRCO \ do { \ diff --git a/simplicity_sdk/platform/emlib/src/em_cmu.c b/simplicity_sdk/platform/emlib/src/em_cmu.c index 19039d951..dd704b7f8 100644 --- a/simplicity_sdk/platform/emlib/src/em_cmu.c +++ b/simplicity_sdk/platform/emlib/src/em_cmu.c @@ -193,6 +193,8 @@ static int8_t ctuneDelta = 0; #endif #endif +static uint8_t pclkDiv = 0; + /******************************************************************************* ************************** LOCAL PROTOTYPES ******************************* ******************************************************************************/ @@ -809,7 +811,7 @@ void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) * @li true - enable specified clock. * @li false - disable specified clock. ******************************************************************************/ -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +SL_WEAK void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) { volatile uint32_t *reg = NULL; uint32_t bit; @@ -1001,6 +1003,12 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) #endif #endif case cmuClock_I2C1: +#if I2C_COUNT > 2 + case cmuClock_I2C2: +#endif +#if I2C_COUNT > 3 + case cmuClock_I2C3: +#endif case cmuClock_PRS: case cmuClock_GPIO: case cmuClock_GPCRC: @@ -1172,6 +1180,10 @@ uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) break; #endif + case cmuClock_DPLLREFCLK: + dpllRefClkGet(&ret, NULL); + break; + default: EFM_ASSERT(false); break; @@ -1423,6 +1435,9 @@ void sli_em_cmu_SYSCLKInitPreClockSelect(void) EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); #endif + // Save the previous PCLK divisor + pclkDiv = CMU_ClockDivGet(cmuClock_PCLK); + // Set max wait-states and PCLK divisor while changing core clock. waitStateMax(); pclkDivMax(); @@ -1454,6 +1469,9 @@ void sli_em_cmu_SYSCLKInitPostClockSelect(bool optimize_divider) if (optimize_divider) { // Set optimal PCLK divisor pclkDivOptimize(); + } else { + // Restore previous PCLK divisor + CMU_ClockDivSet(cmuClock_PCLK, pclkDiv); } #if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) @@ -2147,10 +2165,11 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; break; #endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23) case cmuSelect_HFRCOEM23: tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; break; - +#endif case cmuSelect_FSRCO: tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; break; @@ -3307,7 +3326,7 @@ void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prs * registers. Sufficient wait time for settling, on the order of * TIMEOUTSTEADY, should pass before new frequency measurement is taken. *****************************************************************************/ -sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) +SL_WEAK sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) { uint32_t hfxoCtrlBkup = HFXO0->CTRL; @@ -3372,7 +3391,7 @@ sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) different and can be found using the delta (difference between XI and XO). See @ref CMU_HFXOCTuneCurrentDeltaGet to retrieve the delta value. *****************************************************************************/ -uint32_t CMU_HFXOCTuneGet(void) +SL_WEAK uint32_t CMU_HFXOCTuneGet(void) { uint32_t ctune = 0; uint32_t hfxoCtrlBkup = HFXO0->CTRL; @@ -3474,7 +3493,7 @@ int32_t CMU_HFXOCTuneCurrentDeltaGet(void) * to only use this function when HFXO isn't being used. It's also a blocking * function that can be time consuming. *****************************************************************************/ -void CMU_HFXOCoreBiasCurrentCalibrate(void) +SL_WEAK void CMU_HFXOCoreBiasCurrentCalibrate(void) { uint32_t hfxoCtrlBkup = HFXO0->CTRL; @@ -4201,10 +4220,12 @@ static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) break; #endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23) case _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23: f = SystemHFRCOEM23ClockGet(); s = cmuSelect_HFRCOEM23; break; +#endif case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO: f = SystemHFXOClockGet(); diff --git a/simplicity_sdk/platform/emlib/src/em_dbg.c b/simplicity_sdk/platform/emlib/src/em_dbg.c index 7cd73a05e..99ab543b3 100644 --- a/simplicity_sdk/platform/emlib/src/em_dbg.c +++ b/simplicity_sdk/platform/emlib/src/em_dbg.c @@ -128,72 +128,5 @@ void DBG_SWOEnable(unsigned int location) } #endif -#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) - -/***************************************************************************//** - * @brief - * Disable debug access. - * - * @cond DOXYDOC_S2_DEVICE - * @details - * SE interface is used to disable debug access. By choosing - * @ref dbgLockModePermanent, debug access is blocked permanently. SE disables - * the device erase command and thereafter disables debug access. - * @endcond - * @cond DOXYDOC_P2_DEVICE - * @ - * @details - * Debug access is blocked using debug lock word. On series 1 devices, - * if @ref dbgLockModePermanent is chosen, debug access is blocked - * permanently using AAP lock word. - * @endcond - * @param[in] lockMode - * Debug lock mode to be used. - * - * @cond !DOXYDOC_P1_DEVICE - * @warning - * If @ref dbgLockModePermanent is chosen as the lock mode, the debug port - * will be closed permanently and is irreversible. - * @endcond - ******************************************************************************/ -void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) - if (lockMode != dbgLockModeAllowErase) { - EFM_ASSERT(0); - } -#else - if ((lockMode != dbgLockModeAllowErase) && (lockMode != dbgLockModePermanent)) { - EFM_ASSERT(0); - } -#endif - - bool wasLocked; - uint32_t lockWord = 0x0; - wasLocked = ((MSC->LOCK & _MSC_LOCK_MASK) != 0U); - MSC_Init(); - - uint32_t *dlw = (uint32_t*)(LOCKBITS_BASE + (127 * 4)); - - if (*dlw == 0xFFFFFFFF) { - MSC_WriteWord(dlw, &lockWord, sizeof(lockWord)); - } -#if !defined(_SILICON_LABS_32B_SERIES_0) - uint32_t *alw = (uint32_t*)(LOCKBITS_BASE + (124 * 4)); - - if (lockMode == dbgLockModePermanent) { - if (*alw == 0xFFFFFFFF) { - MSC_WriteWord(alw, &lockWord, sizeof(lockWord)); - } - } -#endif - - if (wasLocked) { - MSC_Deinit(); - } -} - -#endif /* defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) */ - /** @} (end addtogroup dbg) */ #endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ diff --git a/simplicity_sdk/platform/emlib/src/em_emu.c b/simplicity_sdk/platform/emlib/src/em_emu.c index 515109ed5..b453df8dc 100644 --- a/simplicity_sdk/platform/emlib/src/em_emu.c +++ b/simplicity_sdk/platform/emlib/src/em_emu.c @@ -224,7 +224,8 @@ static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) #define RAM0_BLOCKS 32U #define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) #define RAM0_BLOCKS 16U #define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks #endif @@ -696,9 +697,8 @@ static void vScaleAfterWakeup(void) } #endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) typedef enum { dpllState_Save, /* Save DPLL state. */ dpllState_Restore, /* Restore DPLL. */ @@ -974,9 +974,8 @@ void EMU_EnterEM2(bool restore) bool errataFixEmuE110En; #endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) if (restore) { dpllState(dpllState_Save); } @@ -1087,9 +1086,8 @@ void EMU_EnterEM2(bool restore) #endif #endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) if (restore) { dpllState(dpllState_Restore); } @@ -1177,9 +1175,8 @@ void EMU_EnterEM3(bool restore) bool errataFixEmuE110En; #endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) if (restore) { dpllState(dpllState_Save); } @@ -1301,9 +1298,8 @@ void EMU_EnterEM3(bool restore) #endif #endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) if (restore) { dpllState(dpllState_Restore); } @@ -1332,9 +1328,8 @@ void EMU_Save(void) #if (_SILICON_LABS_32B_SERIES < 2) emState(emState_Save); #endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) dpllState(dpllState_Save); #endif } @@ -1353,9 +1348,8 @@ void EMU_Restore(void) #if (_SILICON_LABS_32B_SERIES < 2) emState(emState_Restore); #endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) dpllState(dpllState_Restore); #endif } @@ -1460,9 +1454,17 @@ SL_WEAK void EMU_EFPEM4PresleepHook(void) * * @note * Only a power on reset or external reset pin can wake the device from EM4. + * Device which is configured in Boost DC-DC mode can not enter EM4. ******************************************************************************/ void EMU_EnterEM4(void) { + /* Device with Boost DC-DC cannot enter EM4 because Boost DC-DC module does not + * have BYPASS switch so DC-DC converter can not be set to bypass mode. */ +#if (defined(_SILICON_LABS_DCDC_FEATURE) \ + && (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST)) + EFM_ASSERT(false); +#endif + #if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) sli_metric_em4_wake_init(); #endif @@ -1586,6 +1588,7 @@ void EMU_EnterEM4(void) #endif #if defined(_DCDC_IF_EM4ERR_MASK) + /* If EM4ERR flag in DCDC->IF is set, mean that device cannot enter EM4, device will be suspended in this assertion */ EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0); CORE_EXIT_CRITICAL(); #endif @@ -1685,8 +1688,9 @@ void EMU_MemPwrDown(uint32_t blocks) * function can be used in a generic way to power down a RAM memory region * which is known to be unused. * - * This function will only power down blocks which are completely enclosed - * by the memory range given by [start, end). + * This function will power down blocks from start to the end of RAM. For xg27, + * it will shut off blocks which are completely enclosed by the memory range + * given by [start, end]. * * This is an example to power down all RAM blocks except the first * one. The first RAM block is special in that it cannot be powered down @@ -1698,17 +1702,18 @@ void EMU_MemPwrDown(uint32_t blocks) * @endcode * * @note - * Only a reset can power up the specified memory block(s) after power down - * on a series 0 device. The specified memory block(s) will stay off - * until a call to EMU_RamPowerUp() is done on series 1/2. + * The specified memory block(s) will stay off until a call + * to EMU_RamPowerUp() is done. * * @param[in] start * The start address of the RAM region to power down. This address is * inclusive. * * @param[in] end - * The end address of the RAM region to power down. This address is - * exclusive. If this parameter is 0, all RAM blocks contained in the + * The end address of the RAM region to power down. Except for xg27, It can only + * have two values: 0 or more than RAM0_END. Any other valid RAM address + * will just do nothing without any error or indication that nothing happened. + * This address is exclusive. If this parameter is 0, all RAM blocks contained in the * region from start to the upper RAM address will be powered down. ******************************************************************************/ void EMU_RamPowerDown(uint32_t start, uint32_t end) @@ -1721,29 +1726,18 @@ void EMU_RamPowerDown(uint32_t start, uint32_t end) } // Check to see if something in RAM0 can be powered down. - if (end > RAM0_END) { -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 - // Block 0 is 16 kB and cannot be powered off. - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 0; // Block 1, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 1; // Block 2, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000UL) << 2; // Block 3, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000UL) << 3; // Block 4, 64 kB -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 - // Block 0 is 4 kB and cannot be powered off. - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000UL) << 0; // Block 1, 4 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000UL) << 1; // Block 2, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 2; // Block 3, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 3; // Block 4, 7 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#if defined(_SILICON_LABS_32B_SERIES_2) + if (end >= RAM0_END) { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) // Lynx has 2 blocks. We do no shut off block 0 because we dont want to disable all RAM0 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 2; // Block 2, 32 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) // These platforms have equally-sized RAM blocks and block 0 can be powered down but should not. // This condition happens when the block 0 disable bit flag is available in the retention control register. for (unsigned i = 1; i < RAM0_BLOCKS; i++) { @@ -1756,6 +1750,13 @@ void EMU_RamPowerDown(uint32_t start, uint32_t end) } #endif } +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + else if (end > 0x20006000UL) { + // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB + } +#endif +#endif // Power down the selected blocks. #if defined(_EMU_MEMCTRL_MASK) @@ -3352,6 +3353,12 @@ bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit) EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); #endif +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) + BUS_RegMaskedWrite(&DCDC->CTRL, + _DCDC_CTRL_DVDDBSTPRG_MASK, + ((uint32_t)dcdcBoostInit->outputVoltage << _DCDC_CTRL_DVDDBSTPRG_SHIFT)); +#endif + DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) | ((uint32_t)dcdcBoostInit->tonMax << _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT); DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) @@ -3426,6 +3433,40 @@ void EMU_BoostExternalShutdownEnable(bool enable) EMU->BOOSTCTRL_SET = EMU_BOOSTCTRL_BOOSTENCTRL; } } + +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) +/***************************************************************************//** + * @brief + * Set DCDC Boost output voltage. + * + * @param[in] boostOutputVoltage + * Boost output voltage. + ******************************************************************************/ +void EMU_DCDCBoostOutputVoltageSet(const EMU_DcdcBoostOutputVoltage_TypeDef boostOutputVoltage) +{ + bool dcdcLocked = false; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + + BUS_RegMaskedWrite(&DCDC->CTRL, + _DCDC_CTRL_DVDDBSTPRG_MASK, + ((uint32_t)boostOutputVoltage << _DCDC_CTRL_DVDDBSTPRG_SHIFT)); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); +} +#endif #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ @@ -3702,7 +3743,7 @@ void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value) * @param[in] value * Maximum time for peak current detection. ******************************************************************************/ -void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value) +SL_WEAK void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value) { bool dcdcLocked = false; bool dcdcClkWasEnabled = false; @@ -4238,5 +4279,41 @@ void EMU_EFPDriveDvddSet(bool enable) } #endif +#if defined(_EMU_CTRL_HDREGEM2EXITCLIM_MASK) +/***************************************************************************//** + * @brief + * Set to enable HDREG EM2 Exit current limit. + * + * @details + * Limit HDREG max current drawn on EM2 exit by temporarily adjusting its + * output trim so current is pulled from DECOUPLE cap. + * + * @param[in] enable + * True to enable HDREG EM2 Exit current limit. + ******************************************************************************/ +void EMU_HDRegEM2ExitCurrentLimitEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_HDREGEM2EXITCLIM; + } else { + EMU->CTRL_CLR = EMU_CTRL_HDREGEM2EXITCLIM; + } +} +#endif + +#if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK) +/***************************************************************************//** + * @brief + * Set the HDREG max current capability limit. + * + * @param[in] current + * HDREG max current capability limit. + ******************************************************************************/ +void EMU_HDRegStopGearSet(EMU_HdregStopGearILmt_TypeDef current) +{ + EMU->CTRL = ((current << _EMU_CTRL_HDREGSTOPGEAR_SHIFT) \ + & _EMU_CTRL_HDREGSTOPGEAR_MASK) | (EMU->CTRL & ~_EMU_CTRL_HDREGSTOPGEAR_MASK); +} +#endif /** @} (end addtogroup emu) */ #endif /* __EM_EMU_H */ diff --git a/simplicity_sdk/platform/emlib/src/em_ldma.c b/simplicity_sdk/platform/emlib/src/em_ldma.c index b9096bfa2..92a2f312f 100644 --- a/simplicity_sdk/platform/emlib/src/em_ldma.c +++ b/simplicity_sdk/platform/emlib/src/em_ldma.c @@ -146,20 +146,6 @@ void LDMA_Init(const LDMA_Init_t *init) EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT) & ~_LDMA_CTRL_NUMFIXED_MASK)); -#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); -#endif - -#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); -#endif - EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); CMU_ClockEnable(cmuClock_LDMA, true); @@ -242,34 +228,12 @@ void LDMA_StartTransfer(int ch, EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK)); #endif -#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); -#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); -#endif - EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) & ~_LDMA_CH_CFG_ARBSLOTS_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) & ~_LDMA_CH_CFG_SRCINCSIGN_MASK)); EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) & ~_LDMA_CH_CFG_DSTINCSIGN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT) - & ~_LDMA_CH_LOOP_LOOPCNT_MASK)); /* Clear the pending channel interrupt. */ #if defined (LDMA_HAS_SET_CLEAR) @@ -470,26 +434,25 @@ bool LDMA_TransferDone(int ch) ******************************************************************************/ uint32_t LDMA_TransferRemainingCount(int ch) { - uint32_t remaining, done, iflag; + uint32_t remaining, done; uint32_t chMask = 1UL << (uint8_t)ch; EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); CORE_ATOMIC_SECTION( - iflag = LDMA->IF; done = LDMA->CHDONE; remaining = LDMA->CH[ch].CTRL; ) - iflag &= chMask; done &= chMask; - remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) - >> _LDMA_CH_CTRL_XFERCNT_SHIFT; - if (done || ((remaining == 0) && iflag)) { + if (done) { return 0; } + remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) + >> _LDMA_CH_CTRL_XFERCNT_SHIFT; + /* +1 because XFERCNT is 0-based. */ return remaining + 1; } diff --git a/simplicity_sdk/platform/emlib/src/em_msc.c b/simplicity_sdk/platform/emlib/src/em_msc.c index 96e0937af..ede8ad904 100644 --- a/simplicity_sdk/platform/emlib/src/em_msc.c +++ b/simplicity_sdk/platform/emlib/src/em_msc.c @@ -133,7 +133,7 @@ #elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) + || (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) && !defined(_MPAHBRAM_CTRL_MASK))) /* On Series 2 Config 2, aka EFR32XG22, ECC is supported for the main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ @@ -201,7 +201,7 @@ #if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) + || (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) && !defined(_MPAHBRAM_CTRL_MASK))) #define ECC_CTRL_REG (SYSCFG->DMEM0ECCCTRL) #define ECC_IFC_REG (SYSCFG->IF_CLR) #define ECC_IFC_MASK (SYSCFG_IF_RAMERR1B | SYSCFG_IF_RAMERR2B) @@ -1591,7 +1591,7 @@ static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank) #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) + || (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) && !defined(_MPAHBRAM_CTRL_MASK)) enableEcc = eccBank->initSyndromeEnable; #elif defined(_MPAHBRAM_CTRL_MASK) /* MPAHBRAM ECC requires both ECCEN and ECCWEN to be set for the syndromes diff --git a/simplicity_sdk/platform/emlib/src/em_prs.c b/simplicity_sdk/platform/emlib/src/em_prs.c index 3dbfc4d6e..3b906f8fa 100644 --- a/simplicity_sdk/platform/emlib/src/em_prs.c +++ b/simplicity_sdk/platform/emlib/src/em_prs.c @@ -367,9 +367,9 @@ void PRS_SourceSignalSet(unsigned int ch, * An asynchronous signal (for selected @p source) to use. Use one of the * PRS_CH_CTRL_SIGSEL_x defines that support asynchronous operation. ******************************************************************************/ -void PRS_SourceAsyncSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal) +SL_WEAK void PRS_SourceAsyncSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal) { PRS_ConnectSignal(ch, prsTypeAsync, (PRS_Signal_t) (source | signal)); } @@ -425,7 +425,7 @@ void PRS_GpioOutputLocation(unsigned int ch, * Channel number >= 0 if an unused PRS channel was found. If no free PRS * channel was found then -1 is returned. ******************************************************************************/ -int PRS_GetFreeChannel(PRS_ChType_t type) +SL_WEAK int PRS_GetFreeChannel(PRS_ChType_t type) { int ch = -1; PRS_Signal_t signal; @@ -551,7 +551,7 @@ void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal) * @param[in] consumer * This is the PRS consumer. ******************************************************************************/ -void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) +SL_WEAK void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) { EFM_ASSERT((uint32_t)consumer <= 0xFFF); volatile uint32_t * addr = (volatile uint32_t *) PRS; @@ -592,7 +592,7 @@ void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t cons * @param[in] pin * GPIO pin ******************************************************************************/ -void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) +SL_WEAK void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) { volatile uint32_t * addr; if (type == prsTypeAsync) { @@ -637,7 +637,7 @@ void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, u * output of the logic function is the output of Channel A. Function like * AND, OR, XOR, NOT and more are available. ******************************************************************************/ -void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) +SL_WEAK void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) { EFM_ASSERT(chA < PRS_ASYNC_CHAN_COUNT); EFM_ASSERT(chB < PRS_ASYNC_CHAN_COUNT); diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter.h b/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter.h index 2fa6c35e7..403b36da5 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter.h @@ -28,4 +28,6 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_dcdc_coulomb_counter.h has been renamed to +// sl_hal_dcdc_coulomb_counter.h #include "sl_hal_dcdc_coulomb_counter.h" diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter_compat.h b/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter_compat.h index 0148e96fa..8462ec563 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter_compat.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_dcdc_coulomb_counter_compat.h @@ -28,4 +28,6 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_dcdc_coulomb_counter_compat.h has been renamed to +// sl_hal_dcdc_coulomb_counter_compat.h #include "sl_hal_dcdc_coulomb_counter_compat.h" diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet.h b/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet.h index e3f79873d..98f37c37d 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet.h @@ -28,4 +28,5 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_etampdet.h has been renamed to sl_hal_etampdet.h #include "sl_hal_etampdet.h" diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet_compat.h b/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet_compat.h index 8e84ad302..b539f4a98 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet_compat.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_etampdet_compat.h @@ -28,4 +28,6 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_etampdet_compat.h has been renamed to +// sl_hal_etampdet_compat.h #include "sl_hal_etampdet_compat.h" diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan.h b/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan.h index bb0e837e8..9df9c20b6 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan.h @@ -28,4 +28,5 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_keyscan.h has been renamed to sl_hal_keyscan.h #include "sl_hal_keyscan.h" diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan_compat.h b/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan_compat.h index 2bef4c1be..e768c4db8 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan_compat.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_keyscan_compat.h @@ -28,4 +28,6 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_keyscan_compat.h has been renamed to +// sl_hal_keyscan_compat.h #include "sl_hal_keyscan_compat.h" diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc.h b/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc.h index ba70253b1..500c11551 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc.h @@ -28,4 +28,5 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_sysrtc.h has been renamed to sl_hal_sysrtc.h #include "sl_hal_sysrtc.h" diff --git a/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc_compat.h b/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc_compat.h index 04bf8ab81..2321e8b2f 100644 --- a/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc_compat.h +++ b/simplicity_sdk/platform/peripheral/inc/peripheral_sysrtc_compat.h @@ -28,4 +28,6 @@ * ******************************************************************************/ +// Compatibility layer. peripheral_sysrtc_compat.h has been renamed to +// sl_hal_sysrtc_compat.h #include "sl_hal_sysrtc_compat.h" diff --git a/simplicity_sdk/platform/peripheral/inc/sl_hal_bus.h b/simplicity_sdk/platform/peripheral/inc/sl_hal_bus.h index f026445e3..4283af07a 100644 --- a/simplicity_sdk/platform/peripheral/inc/sl_hal_bus.h +++ b/simplicity_sdk/platform/peripheral/inc/sl_hal_bus.h @@ -34,6 +34,7 @@ #include "sl_assert.h" #include "sl_core.h" #include "em_device.h" +#include "sl_code_classification.h" #ifdef __cplusplus extern "C" { @@ -99,6 +100,7 @@ __STATIC_INLINE unsigned int sl_hal_bus_ram_read_bit(volatile const uint32_t *ad * * @param[in] val A value to set bit to, 0 or 1. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_COMMON, SL_CODE_CLASS_TIME_CRITICAL) __STATIC_INLINE void sl_hal_bus_reg_write_bit(volatile uint32_t *addr, uint32_t bit, uint32_t val) diff --git a/simplicity_sdk/platform/peripheral/inc/sl_hal_gpio.h b/simplicity_sdk/platform/peripheral/inc/sl_hal_gpio.h index 67da655d1..87df88941 100644 --- a/simplicity_sdk/platform/peripheral/inc/sl_hal_gpio.h +++ b/simplicity_sdk/platform/peripheral/inc/sl_hal_gpio.h @@ -42,9 +42,8 @@ extern "C" { #include #include #include "sl_assert.h" -#include "sl_core.h" -#include "sl_status.h" #include "sl_device_gpio.h" +#include "sl_code_classification.h" /* *INDENT-OFF* */ // ***************************************************************************** @@ -66,6 +65,189 @@ extern "C" { ******************************** DEFINES ********************************** ******************************************************************************/ +/// Define for port specific pin mask +#if defined(GPIO_PA_MASK) +#define SL_HAL_GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) +#else +#define SL_HAL_GPIO_PORT_A_PIN_MASK 0 +#endif +#if defined(GPIO_PB_MASK) +#define SL_HAL_GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) +#else +#define SL_HAL_GPIO_PORT_B_PIN_MASK 0 +#endif +#if defined(GPIO_PC_MASK) +#define SL_HAL_GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) +#else +#define SL_HAL_GPIO_PORT_C_PIN_MASK 0 +#endif +#if defined(GPIO_PD_MASK) +#define SL_HAL_GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) +#else +#define SL_HAL_GPIO_PORT_D_PIN_MASK 0 +#endif +#if defined(GPIO_PE_MASK) +#define SL_HAL_GPIO_PORT_E_PIN_MASK (GPIO_PE_MASK) +#else +#define SL_HAL_GPIO_PORT_E_PIN_MASK 0 +#endif +#if defined(GPIO_PF_MASK) +#define SL_HAL_GPIO_PORT_F_PIN_MASK (GPIO_PF_MASK) +#else +#define SL_HAL_GPIO_PORT_F_PIN_MASK 0 +#endif +#if defined(GPIO_PG_MASK) +#define SL_HAL_GPIO_PORT_G_PIN_MASK (GPIO_PG_MASK) +#else +#define SL_HAL_GPIO_PORT_G_PIN_MASK 0 +#endif +#if defined(GPIO_PH_MASK) +#define SL_HAL_GPIO_PORT_H_PIN_MASK (GPIO_PH_MASK) +#else +#define SL_HAL_GPIO_PORT_H_PIN_MASK 0 +#endif +#if defined(GPIO_PI_MASK) +#define SL_HAL_GPIO_PORT_I_PIN_MASK (GPIO_PI_MASK) +#else +#define SL_HAL_GPIO_PORT_I_PIN_MASK 0 +#endif +#if defined(GPIO_PJ_MASK) +#define SL_HAL_GPIO_PORT_J_PIN_MASK (GPIO_PJ_MASK) +#else +#define SL_HAL_GPIO_PORT_J_PIN_MASK 0 +#endif +#if defined(GPIO_PK_MASK) +#define SL_HAL_GPIO_PORT_K_PIN_MASK (GPIO_PK_MASK) +#else +#define SL_HAL_GPIO_PORT_K_PIN_MASK 0 +#endif + +/// Define for port specific pin count +#if defined(GPIO_PA_COUNT) +#define SL_HAL_GPIO_PORT_A_PIN_COUNT (GPIO_PA_COUNT) +#else +#define SL_HAL_GPIO_PORT_A_PIN_COUNT 0 +#endif +#if defined(GPIO_PB_COUNT) +#define SL_HAL_GPIO_PORT_B_PIN_COUNT (GPIO_PB_COUNT) +#else +#define SL_HAL_GPIO_PORT_B_PIN_COUNT 0 +#endif +#if defined(GPIO_PC_COUNT) +#define SL_HAL_GPIO_PORT_C_PIN_COUNT (GPIO_PC_COUNT) +#else +#define SL_HAL_GPIO_PORT_C_PIN_COUNT 0 +#endif +#if defined(GPIO_PD_COUNT) +#define SL_HAL_GPIO_PORT_D_PIN_COUNT (GPIO_PD_COUNT) +#else +#define SL_HAL_GPIO_PORT_D_PIN_COUNT 0 +#endif +#if defined(GPIO_PE_COUNT) +#define SL_HAL_GPIO_PORT_E_PIN_COUNT (GPIO_PE_COUNT) +#else +#define SL_HAL_GPIO_PORT_E_PIN_COUNT 0 +#endif +#if defined(GPIO_PF_COUNT) +#define SL_HAL_GPIO_PORT_F_PIN_COUNT (GPIO_PF_COUNT) +#else +#define SL_HAL_GPIO_PORT_F_PIN_COUNT 0 +#endif +#if defined(GPIO_PG_COUNT) +#define SL_HAL_GPIO_PORT_G_PIN_COUNT (GPIO_PG_COUNT) +#else +#define SL_HAL_GPIO_PORT_G_PIN_COUNT 0 +#endif +#if defined(GPIO_PH_COUNT) +#define SL_HAL_GPIO_PORT_H_PIN_COUNT (GPIO_PH_COUNT) +#else +#define SL_HAL_GPIO_PORT_H_PIN_COUNT 0 +#endif +#if defined(GPIO_PI_COUNT) +#define SL_HAL_GPIO_PORT_I_PIN_COUNT (GPIO_PI_COUNT) +#else +#define SL_HAL_GPIO_PORT_I_PIN_COUNT 0 +#endif +#if defined(GPIO_PJ_COUNT) +#define SL_HAL_GPIO_PORT_J_PIN_COUNT (GPIO_PJ_COUNT) +#else +#define SL_HAL_GPIO_PORT_J_PIN_COUNT 0 +#endif +#if defined(GPIO_PK_COUNT) +#define SL_HAL_GPIO_PORT_K_PIN_COUNT (GPIO_PK_COUNT) +#else +#define SL_HAL_GPIO_PORT_K_PIN_COUNT 0 +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/// Highest GPIO port number. + +#if (SL_HAL_GPIO_PORT_K_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 10 +#elif (SL_HAL_GPIO_PORT_J_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 9 +#elif (SL_HAL_GPIO_PORT_I_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 8 +#elif (SL_HAL_GPIO_PORT_H_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 7 +#elif (SL_HAL_GPIO_PORT_G_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 6 +#elif (SL_HAL_GPIO_PORT_F_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 5 +#elif (SL_HAL_GPIO_PORT_E_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 4 +#elif (SL_HAL_GPIO_PORT_D_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 3 +#elif (SL_HAL_GPIO_PORT_C_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 2 +#elif (SL_HAL_GPIO_PORT_B_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 1 +#elif (SL_HAL_GPIO_PORT_A_PIN_COUNT > 0) +#define SL_HAL_GPIO_PORT_MAX 0 +#else +#error "Max GPIO port number is undefined for this part." +#endif + +/// Highest GPIO pin number. +#define SL_HAL_GPIO_PIN_MAX 15 + +/// @endcond + +#define SL_HAL_GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? SL_HAL_GPIO_PORT_A_PIN_COUNT \ + : (port) == 1 ? SL_HAL_GPIO_PORT_B_PIN_COUNT \ + : (port) == 2 ? SL_HAL_GPIO_PORT_C_PIN_COUNT \ + : (port) == 3 ? SL_HAL_GPIO_PORT_D_PIN_COUNT \ + : (port) == 4 ? SL_HAL_GPIO_PORT_E_PIN_COUNT \ + : (port) == 5 ? SL_HAL_GPIO_PORT_F_PIN_COUNT \ + : (port) == 6 ? SL_HAL_GPIO_PORT_G_PIN_COUNT \ + : (port) == 7 ? SL_HAL_GPIO_PORT_H_PIN_COUNT \ + : (port) == 8 ? SL_HAL_GPIO_PORT_I_PIN_COUNT \ + : (port) == 9 ? SL_HAL_GPIO_PORT_J_PIN_COUNT \ + : (port) == 10 ? SL_HAL_GPIO_PORT_K_PIN_COUNT \ + : 0) + +#define SL_HAL_GPIO_PORT_MASK(port) ( \ + ((int)port) == 0 ? SL_HAL_GPIO_PORT_A_PIN_MASK \ + : ((int)port) == 1 ? SL_HAL_GPIO_PORT_B_PIN_MASK \ + : ((int)port) == 2 ? SL_HAL_GPIO_PORT_C_PIN_MASK \ + : ((int)port) == 3 ? SL_HAL_GPIO_PORT_D_PIN_MASK \ + : ((int)port) == 4 ? SL_HAL_GPIO_PORT_E_PIN_MASK \ + : ((int)port) == 5 ? SL_HAL_GPIO_PORT_F_PIN_MASK \ + : ((int)port) == 6 ? SL_HAL_GPIO_PORT_G_PIN_MASK \ + : ((int)port) == 7 ? SL_HAL_GPIO_PORT_H_PIN_MASK \ + : ((int)port) == 8 ? SL_HAL_GPIO_PORT_I_PIN_MASK \ + : ((int)port) == 9 ? SL_HAL_GPIO_PORT_J_PIN_MASK \ + : ((int)port) == 10 ? SL_HAL_GPIO_PORT_K_PIN_MASK \ + : 0UL) + +/// Validation of port. +#define SL_HAL_GPIO_PORT_IS_VALID(port) (SL_HAL_GPIO_PORT_MASK(port) != 0x0UL) + +/// Validation of port and pin. +#define SL_HAL_GPIO_PORT_PIN_IS_VALID(port, pin) ((((SL_HAL_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) + /// Max interrupt lines for external and EM4 interrupts. #define SL_HAL_GPIO_INTERRUPT_MAX 15 @@ -77,7 +259,7 @@ extern "C" { #define SL_HAL_GPIO_INT_IF_ODD_MASK ((_GPIO_IF_MASK) & 0xAAAAAAAAUL) /// Validation of mode. -#define SL_HAL_GPIO_MODE_VALID(mode) ((mode & _GPIO_P_MODEL_MODE0_MASK) == mode) +#define SL_HAL_GPIO_MODE_IS_VALID(mode) ((mode & _GPIO_P_MODEL_MODE0_MASK) == mode) /// Validation of interrupt number and pin. #define SL_HAL_GPIO_INTNO_PIN_VALID(int_no, pin) (((int_no) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) @@ -86,57 +268,6 @@ extern "C" { ******************************** ENUMS ************************************ ******************************************************************************/ -/// GPIO Pin Modes. -SL_ENUM(sl_hal_gpio_mode_t) { - /// Input disabled. Pull-up if DOUT is set. - SL_HAL_GPIO_MODE_DISABLED = _GPIO_P_MODEL_MODE0_DISABLED, - - /// Input enabled. Filter if DOUT is set. - SL_HAL_GPIO_MODE_INPUT = _GPIO_P_MODEL_MODE0_INPUT, - - /// Input enabled. DOUT determines pull direction. - SL_HAL_GPIO_MODE_INPUT_PULL = _GPIO_P_MODEL_MODE0_INPUTPULL, - - /// Input enabled with filter. DOUT determines pull direction. - SL_HAL_GPIO_MODE_INPUT_PULL_FILTER = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, - - /// Push-pull output. - SL_HAL_GPIO_MODE_PUSH_PULL = _GPIO_P_MODEL_MODE0_PUSHPULL, - - /// Push-pull using alternate control. - SL_HAL_GPIO_MODE_PUSH_PULL_ALTERNATE = _GPIO_P_MODEL_MODE0_PUSHPULLALT, - - /// Wired-or output. - SL_HAL_GPIO_MODE_WIRED_OR = _GPIO_P_MODEL_MODE0_WIREDOR, - - /// Wired-or output with pull-down. - SL_HAL_GPIO_MODE_WIRED_OR_PULL_DOWN = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, - - /// Open-drain output. - SL_HAL_GPIO_MODE_WIRED_AND = _GPIO_P_MODEL_MODE0_WIREDAND, - - /// Open-drain output with filter. - SL_HAL_GPIO_MODE_WIRED_AND_FILTER = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, - - /// Open-drain output with pull-up. - SL_HAL_GPIO_MODE_WIRED_AND_PULLUP = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, - - /// Open-drain output with filter and pull-up. - SL_HAL_GPIO_MODE_WIRED_AND_PULLUP_FILTER = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, - - /// Open-drain output using alternate control. - SL_HAL_GPIO_MODE_WIRED_AND_ALTERNATE = _GPIO_P_MODEL_MODE0_WIREDANDALT, - - /// Open-drain output using alternate control with filter. - SL_HAL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, - - /// Open-drain output using alternate control with pull-up. - SL_HAL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, - - /// Open-drain output using alternate control with filter and pull-up. - SL_HAL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER -}; - /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ @@ -150,7 +281,7 @@ SL_ENUM(sl_hal_gpio_mode_t) { * some input mode configurations to determine the pull-up/down direction. ******************************************************************************/ void sl_hal_gpio_set_pin_mode(const sl_gpio_t *gpio, - sl_hal_gpio_mode_t mode, + sl_gpio_mode_t mode, bool output_value); /***************************************************************************//** @@ -160,7 +291,7 @@ void sl_hal_gpio_set_pin_mode(const sl_gpio_t *gpio, * * @return Return the pin mode. ******************************************************************************/ -sl_hal_gpio_mode_t sl_hal_gpio_get_pin_mode(const sl_gpio_t *gpio); +sl_gpio_mode_t sl_hal_gpio_get_pin_mode(const sl_gpio_t *gpio); /***************************************************************************//** * Configure the GPIO external pin interrupt by connecting external interrupt id with gpio pin. @@ -199,7 +330,7 @@ int32_t sl_hal_gpio_configure_external_interrupt(const sl_gpio_t *gpio, * EM4 mode can be safely entered. * * @note It is assumed that the GPIO pin modes are set correctly. - * Valid modes are SL_HAL_GPIO_MODE_INPUT and SL_HAL_GPIO_MODE_INPUT_PULL. + * Valid modes are SL_GPIO_MODE_INPUT and SL_GPIO_MODE_INPUT_PULL. * * @param[in] pinmask A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. * @param[in] polaritymask A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. @@ -282,10 +413,11 @@ __INLINE uint32_t sl_hal_gpio_get_lock_status(void) * * @param[in] gpio Pointer to GPIO structure with port and pin ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_GPIO, SL_CODE_CLASS_TIME_CRITICAL) __INLINE void sl_hal_gpio_set_pin(const sl_gpio_t *gpio) { EFM_ASSERT(gpio != NULL); - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); GPIO->P_SET[gpio->port].DOUT = 1UL << gpio->pin; } @@ -299,7 +431,7 @@ __INLINE void sl_hal_gpio_set_pin(const sl_gpio_t *gpio) __INLINE void sl_hal_gpio_set_port(sl_gpio_port_t port, uint32_t pins) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); GPIO->P_SET[port].DOUT = pins; } @@ -314,7 +446,7 @@ __INLINE void sl_hal_gpio_set_port_value(sl_gpio_port_t port, uint32_t val, uint32_t mask) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); } @@ -327,7 +459,7 @@ __INLINE void sl_hal_gpio_set_port_value(sl_gpio_port_t port, __INLINE void sl_hal_gpio_set_slew_rate(sl_gpio_port_t port, uint8_t slewrate) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); @@ -345,7 +477,7 @@ __INLINE void sl_hal_gpio_set_slew_rate(sl_gpio_port_t port, __INLINE void sl_hal_gpio_set_slew_rate_alternate(sl_gpio_port_t port, uint8_t slewrate_alt) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); EFM_ASSERT(slewrate_alt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); @@ -363,7 +495,7 @@ __INLINE void sl_hal_gpio_set_slew_rate_alternate(sl_gpio_port_t port, ******************************************************************************/ __INLINE uint8_t sl_hal_gpio_get_slew_rate(sl_gpio_port_t port) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); return (GPIO->P[port].CTRL & _GPIO_P_CTRL_SLEWRATE_MASK) >> _GPIO_P_CTRL_SLEWRATE_SHIFT; } @@ -377,7 +509,7 @@ __INLINE uint8_t sl_hal_gpio_get_slew_rate(sl_gpio_port_t port) ******************************************************************************/ __INLINE uint8_t sl_hal_gpio_get_slew_rate_alternate(sl_gpio_port_t port) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); return (GPIO->P[port].CTRL & _GPIO_P_CTRL_SLEWRATEALT_MASK) >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT; } @@ -390,7 +522,7 @@ __INLINE uint8_t sl_hal_gpio_get_slew_rate_alternate(sl_gpio_port_t port) __INLINE void sl_hal_gpio_clear_pin(const sl_gpio_t *gpio) { EFM_ASSERT(gpio != NULL); - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); GPIO->P_CLR[gpio->port].DOUT = 1UL << gpio->pin; } @@ -404,7 +536,7 @@ __INLINE void sl_hal_gpio_clear_pin(const sl_gpio_t *gpio) __INLINE void sl_hal_gpio_clear_port(sl_gpio_port_t port, uint32_t pins) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); GPIO->P_CLR[port].DOUT = pins; } @@ -419,7 +551,7 @@ __INLINE void sl_hal_gpio_clear_port(sl_gpio_port_t port, __INLINE bool sl_hal_gpio_get_pin_input(const sl_gpio_t *gpio) { EFM_ASSERT(gpio != NULL); - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); bool pin_input = ((GPIO->P[gpio->port].DIN) >> gpio->pin) & 1UL; @@ -436,7 +568,7 @@ __INLINE bool sl_hal_gpio_get_pin_input(const sl_gpio_t *gpio) __INLINE bool sl_hal_gpio_get_pin_output(const sl_gpio_t *gpio) { EFM_ASSERT(gpio != NULL); - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); bool pin_output = ((GPIO->P[gpio->port].DOUT) >> gpio->pin) & 1UL; @@ -452,7 +584,7 @@ __INLINE bool sl_hal_gpio_get_pin_output(const sl_gpio_t *gpio) ******************************************************************************/ __INLINE uint32_t sl_hal_gpio_get_port_input(sl_gpio_port_t port) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); return GPIO->P[port].DIN; } @@ -466,7 +598,7 @@ __INLINE uint32_t sl_hal_gpio_get_port_input(sl_gpio_port_t port) ******************************************************************************/ __INLINE uint32_t sl_hal_gpio_get_port_output(sl_gpio_port_t port) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); return GPIO->P[port].DOUT; } @@ -479,7 +611,7 @@ __INLINE uint32_t sl_hal_gpio_get_port_output(sl_gpio_port_t port) __INLINE void sl_hal_gpio_toggle_pin(const sl_gpio_t *gpio) { EFM_ASSERT(gpio != NULL); - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); GPIO->P_TGL[gpio->port].DOUT = 1UL << gpio->pin; } @@ -493,7 +625,7 @@ __INLINE void sl_hal_gpio_toggle_pin(const sl_gpio_t *gpio) __INLINE void sl_hal_gpio_toggle_port(sl_gpio_port_t port, uint32_t pins) { - EFM_ASSERT(SL_GPIO_PORT_IS_VALID(port)); + EFM_ASSERT(SL_HAL_GPIO_PORT_IS_VALID(port)); GPIO->P_TGL[port].DOUT = pins; } diff --git a/simplicity_sdk/platform/peripheral/inc/sl_hal_keyscan.h b/simplicity_sdk/platform/peripheral/inc/sl_hal_keyscan.h index ba64c8d01..8ee3373ae 100644 --- a/simplicity_sdk/platform/peripheral/inc/sl_hal_keyscan.h +++ b/simplicity_sdk/platform/peripheral/inc/sl_hal_keyscan.h @@ -143,7 +143,7 @@ __STATIC_INLINE void sl_hal_keyscan_wait_ready(void) ******************************************************************************/ __STATIC_INLINE void sl_hal_keyscan_wait_sync(void) { - while ((KEYSCAN->EN != 0U) && ((KEYSCAN->STATUS & KEYSCAN_STATUS_SYNCBUSY))) { + while ((KEYSCAN->EN != 0U) && (KEYSCAN->STATUS & KEYSCAN_STATUS_SYNCBUSY)) { // Wait for all synchronizations to finish } } diff --git a/simplicity_sdk/platform/peripheral/inc/sl_hal_syscfg.h b/simplicity_sdk/platform/peripheral/inc/sl_hal_syscfg.h new file mode 100644 index 000000000..4f417e74d --- /dev/null +++ b/simplicity_sdk/platform/peripheral/inc/sl_hal_syscfg.h @@ -0,0 +1,89 @@ +/***************************************************************************//** + * @file + * @brief API defining access to SYSCFG registers + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_HAL_SYSCFG_H +#define SL_HAL_SYSCFG_H + +#include + +#if defined(SL_TRUSTZONE_NONSECURE) +#include "sli_tz_service_syscfg.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup syscfg SYSTEM CONFIGURATION - System Configurations + * @brief Syscfg API + * @details + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/******************************************************************************* + ******************************** TZ SERVICES ********************************** + ******************************************************************************/ + +/******************************************************************************* + * @brief + * Reads CHIPREV register. + ******************************************************************************/ +uint32_t sl_hal_syscfg_read_chip_rev(void); + +/******************************************************************************* + * @brief + * Set SYSTICEXTCLKEN bit in CFGSYSTIC to one. + ******************************************************************************/ +void sl_hal_syscfg_set_systicextclken_cfgsystic(void); + +/******************************************************************************* + * @brief + * Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero. + ******************************************************************************/ +void sl_hal_syscfg_clear_systicextclken_cfgsystic(void); + +#ifdef __cplusplus +} +#endif +#endif // SL_HAL_SYSCFG_H diff --git a/simplicity_sdk/platform/peripheral/inc/sl_hal_sysrtc.h b/simplicity_sdk/platform/peripheral/inc/sl_hal_sysrtc.h index c15ff49c7..e3a9b8a40 100644 --- a/simplicity_sdk/platform/peripheral/inc/sl_hal_sysrtc.h +++ b/simplicity_sdk/platform/peripheral/inc/sl_hal_sysrtc.h @@ -187,8 +187,7 @@ void sl_hal_sysrtc_disable(void); * Waits for the SYSRTC to complete all synchronization of register changes * and commands. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) __INLINE void sl_hal_sysrtc_wait_sync(void) { while ((SYSRTC0->EN & SYSRTC_EN_EN) && (SYSRTC0->SYNCBUSY != 0U)) { @@ -282,8 +281,7 @@ __INLINE void sl_hal_sysrtc_unlock(void) * * @return Current SYSRTC counter value. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) __INLINE uint32_t sl_hal_sysrtc_get_counter(void) { // Wait for Counter to synchronize before getting value @@ -329,8 +327,7 @@ void sl_hal_sysrtc_init_group(uint8_t group_number, * Use a set of interrupt flags OR-ed together to set * multiple interrupt sources for the given SYSRTC group. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, uint32_t flags); @@ -343,8 +340,7 @@ void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, * Use a set of interrupt flags OR-ed together to disable * multiple interrupt sources for the given SYSRTC group. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, uint32_t flags); @@ -357,8 +353,7 @@ void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, * Use a set of interrupt flags OR-ed together to clear * multiple interrupt sources for the given SYSRTC group. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, uint32_t flags); @@ -373,8 +368,7 @@ void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, * Returns a set of interrupt flags OR-ed together for multiple * interrupt sources in the SYSRTC group. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) uint32_t sl_hal_sysrtc_get_group_interrupts(uint8_t group_number); /***************************************************************************//** @@ -413,8 +407,7 @@ void sl_hal_sysrtc_set_group_interrupts(uint8_t group_number, * * @return Compare register value. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, uint8_t channel); @@ -427,8 +420,7 @@ uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, * * @param[in] value Compare register value. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, uint8_t channel, uint32_t value); @@ -440,8 +432,7 @@ void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, * * @return Capture register value. ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PERIPHERAL_SYSRTC, - SL_CODE_CLASS_TIME_CRITICAL) +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_HAL_SYSRTC, SL_CODE_CLASS_TIME_CRITICAL) uint32_t sl_hal_sysrtc_get_group_capture_channel_value(uint8_t group_number); /** @} (end addtogroup sysrtc) */ diff --git a/simplicity_sdk/platform/peripheral/inc/sl_hal_system.h b/simplicity_sdk/platform/peripheral/inc/sl_hal_system.h new file mode 100644 index 000000000..08e26b9b5 --- /dev/null +++ b/simplicity_sdk/platform/peripheral/inc/sl_hal_system.h @@ -0,0 +1,146 @@ +/***************************************************************************//** + * @file + * @brief System API + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_HAL_SYSTEM_H +#define _SL_HAL_SYSTEM_H + +#include "em_device.h" +#include "sl_hal_system_generic.h" +#include "sl_enum.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system SYSTEM - System Utils + * @brief System API + * @details + * This module contains functions to read information such as RAM and Flash size, + * device unique ID, chip revision, family, and part number from DEVINFO and + * SCB blocks. Functions to configure and read status from FPU are available for + * compatible devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// Family identifiers. +SL_ENUM_GENERIC(sl_hal_system_part_family_t, uint32_t) { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_FLEX_21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 1 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 1 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_RCP_21 = DEVINFO_PART_FAMILY_MR | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty RCP Series 2 Config 1 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_22 = DEVINFO_PART_FAMILY_MG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 2 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_FLEX_22 = DEVINFO_PART_FAMILY_FG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 2 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_22 = DEVINFO_PART_FAMILY_BG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 2 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_22 = DEVINFO_PART_FAMILY_PG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 2 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + SL_HAL_SYSTEM_PART_FAMILY_FLEX_23 = DEVINFO_PART_FAMILY_FG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 3 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_ZEN_23 = DEVINFO_PART_FAMILY_ZG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Zen Gecko Series 2 Config 3 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_23 = DEVINFO_PART_FAMILY_PG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 3 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_SIDEWALK_23 = DEVINFO_PART_FAMILY_SG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Side Walk Gecko Series 2 Config 3 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_24 = DEVINFO_PART_FAMILY_MG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 4 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_FLEX_24 = DEVINFO_PART_FAMILY_FG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 4 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_24 = DEVINFO_PART_FAMILY_BG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 4 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + SL_HAL_SYSTEM_PART_FAMILY_FLEX_25 = DEVINFO_PART_FAMILY_FG | (25 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 5 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_26 = DEVINFO_PART_FAMILY_MG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 6 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_26 = DEVINFO_PART_FAMILY_BG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 6 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_26 = DEVINFO_PART_FAMILY_PG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 6 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + SL_HAL_SYSTEM_PART_FAMILY_MIGHTY_27 = DEVINFO_PART_FAMILY_MG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Mighty Gecko Series 2 Config 7 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_BLUE_27 = DEVINFO_PART_FAMILY_BG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Blue Gecko Series 2 Config 7 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + SL_HAL_SYSTEM_PART_FAMILY_FLEX_28 = DEVINFO_PART_FAMILY_FG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Flex Gecko Series 2 Config 8 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_ZEN_28 = DEVINFO_PART_FAMILY_ZG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Zen Gecko Series 2 Config 8 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_SIDEWALK_28 = DEVINFO_PART_FAMILY_SG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFR32 Side Walk Gecko Series 2 Config 8 Value Device Family + SL_HAL_SYSTEM_PART_FAMILY_EFM32_PEARL_28 = DEVINFO_PART_FAMILY_PG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), ///< EFM32 Pearl Gecko Series 2 Config 8 Value Device Family +#endif +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + SL_HAL_SYSTEM_PART_FAMILY_BLUETOOTH_301 = DEVINFO_PART0_PROTOCOL_BLUETOOTH \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Bluetooth Config 1 Value Device Family (BG) + SL_HAL_SYSTEM_PART_FAMILY_PROPRIETARY_301 = DEVINFO_PART0_PROTOCOL_PROPRIETARY \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Proprietary Config 1 Value Device Family (FG) + SL_HAL_SYSTEM_PART_FAMILY_FIFTEENPFOUR_301 = DEVINFO_PART0_PROTOCOL_FIFTEENPFOUR \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 15.4 Config 1 Value Device Family (MG) + SL_HAL_SYSTEM_PART_FAMILY_PEARL_301 = DEVINFO_PART0_PROTOCOL_PEARL \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Pearl Config 1 Value Device Family (PG) + SL_HAL_SYSTEM_PART_FAMILY_WIFI_301 = DEVINFO_PART0_PROTOCOL_WIFI \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Wifi Config 1 Value Device Family (WG) + SL_HAL_SYSTEM_PART_FAMILY_ZWAVE_301 = DEVINFO_PART0_PROTOCOL_ZWAVE \ + | (0x33 << _DEVINFO_PART0_SERIES_SHIFT) \ + | (0x30 << _DEVINFO_PART0_DIECODE0_SHIFT), ///< SI Series 3 Zwave Config 1 Value Device Family (ZG) +#endif + SL_HAL_SYSTEM_PART_FAMILY_UNKNOWN = 0xFF ///< Unknown Device Family. Family ID is missing on unprogrammed parts. +}; + +/***************************************************************************//** + * @brief + * Get the MCU family identifier. + * + * @return + * Family identifier of MCU. + * + * @note + * This function retrieves family ID by reading the chip's device info + * structure in flash memory. Users can retrieve family ID directly + * by reading DEVINFO->PART item and decode with mask and shift + * \#defines defined in \_devinfo.h (refer to code + * below for details). + ******************************************************************************/ +sl_hal_system_part_family_t sl_hal_system_get_family(void); + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SL_HAL_SYSTEM_H */ diff --git a/simplicity_sdk/platform/peripheral/inc/sl_hal_system_generic.h b/simplicity_sdk/platform/peripheral/inc/sl_hal_system_generic.h new file mode 100644 index 000000000..27c6f62c7 --- /dev/null +++ b/simplicity_sdk/platform/peripheral/inc/sl_hal_system_generic.h @@ -0,0 +1,341 @@ +/***************************************************************************//** + * @file + * @brief System API (Generic) + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_HAL_SYSTEM_GENERIC_H +#define _SL_HAL_SYSTEM_GENERIC_H + +#include "sl_enum.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system SYSTEM - System Utils + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// Family security capability. +SL_ENUM(sl_hal_system_security_capability_t) { + /// Unknown security capability. + SL_SYSTEM_SECURITY_CAPABILITY_UNKNOWN, + /// Security capability not applicable. + SL_SYSTEM_SECURITY_CAPABILITY_NA, + /// Basic security capability. + SL_SYSTEM_SECURITY_CAPABILITY_BASIC, + /// Root of Trust security capability. + SL_SYSTEM_SECURITY_CAPABILITY_ROT, + /// Secure Element security capability. + SL_SYSTEM_SECURITY_CAPABILITY_SE, + /// Secure Vault security capability. + SL_SYSTEM_SECURITY_CAPABILITY_VAULT +}; + +/// Floating point co-processor access modes. +SL_ENUM_GENERIC(sl_hal_system_fpu_access_t, uint32_t) { + /// Access denied, any attempted access generates a NOCP UsageFault. + SL_SYSTEM_FPU_ACCESS_DENIED = (0x0 << 20), + /// Privileged access only, an unprivileged access generates a NOCP UsageFault. + SL_SYSTEM_FPU_ACCESS_PRIVILEGED_ONLY = (0x5 << 20), + /// Reserved. + SL_SYSTEM_FPU_ACCESS_RESERVED = (0xA << 20), + /// Full access. + SL_SYSTEM_FPU_ACCESS_FULL = (0xF << 20) +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/// Chip revision details. +typedef struct { + uint8_t minor; ///< Minor revision number. + uint8_t major; ///< Major revision number. + uint16_t part_number; ///< Device part number. (0xFFFF if unavailable) + uint16_t family; ///< Device family number. (0xFFFF if unavailable) +} sl_hal_system_chip_revision_t; + +/// ADC Calibration DEVINFO Structures. +typedef struct sl_hal_system_devinfo_adc_cal_data_t { + uint8_t trim_vros0; + uint8_t trim_vros1; + uint8_t trim_gain_4x; + uint8_t trim_gain_0x3_int; +} sl_hal_system_devinfo_adc_cal_data_t; + +typedef struct sl_hal_system_devinfo_adc_offset_t { + uint8_t trim_off_1x; + uint8_t trim_off_2x; + uint8_t trim_off_4x; + uint8_t dummy_byte; +} sl_hal_system_devinfo_adc_offset_t; + +typedef struct sl_hal_system_devinfo_adc_t { + sl_hal_system_devinfo_adc_cal_data_t cal_data; + sl_hal_system_devinfo_adc_offset_t offset; +} sl_hal_system_devinfo_adc_t; + +/// Temperature DEVINFO Structure. +typedef struct sl_hal_system_devinfo_temperature_t { + uint16_t emu_temp_room; + uint16_t cal_temp; +} sl_hal_system_devinfo_temperature_t; + +/// Chip features Structure. +typedef struct sl_hal_system_features { + char feature1; + char feature2; + char feature3; +} sl_hal_system_features_t; + +/******************************************************************************* + ************************** GLOBAL CONSTANTS ******************************* + ******************************************************************************/ + +extern const sl_hal_system_devinfo_adc_t SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; + +extern const sl_hal_system_devinfo_temperature_t SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/******************************************************************************* + * @brief + * Get the chip revision. + * + * @param [out] + * rev Pointer to return the chip revision to. + * + * @warning + * The chip revision structure may be returned with either the partnumber or + * family unpopulated (0xFFFF) depending on the device. + ******************************************************************************/ +void sl_hal_system_get_chip_revision(sl_hal_system_chip_revision_t *rev); + +/***************************************************************************//** + * @brief + * Get DEVINFO revision. + * + * @return + * Revision of the DEVINFO contents. + ******************************************************************************/ +uint8_t sl_hal_system_get_devinfo_rev(void); + +/***************************************************************************//** + * @brief + * Get the default factory calibration value for HFRCO oscillator. + * + * @return + * HFRCOCAL default value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_default_calibration(void); + +/***************************************************************************//** + * @brief + * Get the speed factory calibration value for HFRCO oscillator. + * + * @return + * HFRCOCAL speed value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_speed_calibration(void); + +/***************************************************************************//** + * @brief Get the HFRCO calibration based on the frequency band. + * + * @param[in] frequency + * Frequency for which to retrieve calibration. + * + * @return + * HFRCOCAL value for the given band. + * + * @note + * Those calibrations are only valid for the HFRCO oscillator when used with + * the DPLL module. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcodpll_band_calibration(uint32_t frequency); + +/***************************************************************************//** + * @brief + * Get a factory calibration value for HFRCOCEM23 oscillator. + * + * @return + * HFRCOEM23 calibration value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcoem23_calibration(void); + +/***************************************************************************//** + * @brief + * Get a factory calibration value for HFXOCAL. + * + * @return + * HFXOCAL value. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfxocal(void); + +/***************************************************************************//** + * @brief + * Get family security capability. + * + * @note + * This function retrieves the family security capability based on the + * device number. + * + * @return + * Security capability of MCU. + ******************************************************************************/ +sl_hal_system_security_capability_t sl_hal_system_get_security_capability(void); + +/***************************************************************************//** + * @brief + * Get the unique number for this device. + * + * @return + * Unique number for this device. + ******************************************************************************/ +uint64_t sl_hal_system_get_unique(void); + +/***************************************************************************//** + * @brief + * Get the production revision for this part. + * + * @return + * Production revision for this part. + ******************************************************************************/ +uint8_t sl_hal_system_get_prod_rev(void); + +/***************************************************************************//** + * @brief + * Get the SRAM Base Address. + * + * @return + * Base address SRAM (32-bit unsigned integer). + ******************************************************************************/ +uint32_t sl_hal_system_get_sram_base_address(void); + +/***************************************************************************//** + * @brief + * Get the SRAM size (in KB). + * + * @note + * This function retrieves SRAM size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use SRAM_SIZE instead. + * + * @return + * Size of internal SRAM (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_sram_size(void); + +/***************************************************************************//** + * @brief + * Get the flash size (in KB). + * + * @note + * This function retrieves flash size by reading the chip device info structure or + * DEVINFO->EMBMSIZE (embedded flash. not the case for S3 for now) or + * user config (external flash). + * + * @return + * Size of flash (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_flash_size(void); + +/***************************************************************************//** + * @brief + * Get the flash page size in bytes. + * + * @note + * This function retrieves flash page size by reading the SE or + * user config (external flash) + * + * @return + * Page size of flash in bytes. + ******************************************************************************/ +uint32_t sl_hal_system_get_flash_page_size(void); + +/***************************************************************************//** + * @brief + * Get the MCU part number. + * + * @return + * The part number of MCU. + ******************************************************************************/ +uint16_t sl_hal_system_get_part_number(void); + +/***************************************************************************//** + * @brief + * Get the SoC or MCU features. + * + * @return + * The features of the current SoC or MCU. + * + * @note The features can be decoded by referring to the SoC or MCU datasheet. + ******************************************************************************/ +sl_hal_system_features_t sl_hal_system_get_part_features(void); + +/***************************************************************************//** + * @brief + * Get the temperature information. + * + * @param[out] info + * Pointer to variable where to store the temperature info. + ******************************************************************************/ +void sl_hal_system_get_temperature_info(sl_hal_system_devinfo_temperature_t *info); + +/***************************************************************************//** + * @brief + * Set floating point co-processor (FPU) access mode. + * + * @param[in] accessMode + * Floating point co-processor access mode. + ******************************************************************************/ +void sl_hal_system_fpu_set_access_mode(sl_hal_system_fpu_access_t access_mode); + +/***************************************************************************//** + * @brief Get the ADC calibration info. + * + * @param[out] info + * Pointer to variable where to store the adc calibration info. + ******************************************************************************/ +void sl_hal_system_get_adc_calibration_info(sl_hal_system_devinfo_adc_t *info); + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SL_HAL_SYSTEM_GENERIC_H */ diff --git a/simplicity_sdk/platform/peripheral/src/sl_hal_gpio.c b/simplicity_sdk/platform/peripheral/src/sl_hal_gpio.c index a35e4cd76..c941bc683 100644 --- a/simplicity_sdk/platform/peripheral/src/sl_hal_gpio.c +++ b/simplicity_sdk/platform/peripheral/src/sl_hal_gpio.c @@ -81,18 +81,107 @@ extern __INLINE void sl_hal_gpio_enable_debug_swd_io(bool enable); * Sets the mode for GPIO pin. ******************************************************************************/ void sl_hal_gpio_set_pin_mode(const sl_gpio_t *gpio, - sl_hal_gpio_mode_t mode, + sl_gpio_mode_t mode, bool output_value) { - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); - EFM_ASSERT(SL_HAL_GPIO_MODE_VALID(mode)); + sl_gpio_mode_t gpio_mode = SL_GPIO_MODE_DISABLED; + + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); EFM_ASSERT(sl_hal_gpio_get_lock_status() == 0); + switch (mode) { +#if defined(_GPIO_P_MODEL_MODE0_DISABLED) + case SL_GPIO_MODE_DISABLED: + gpio_mode = _GPIO_P_MODEL_MODE0_DISABLED; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUT) + case SL_GPIO_MODE_INPUT: + gpio_mode = _GPIO_P_MODEL_MODE0_INPUT; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULL) + case SL_GPIO_MODE_INPUT_PULL: + gpio_mode = _GPIO_P_MODEL_MODE0_INPUTPULL; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULLFILTER) + case SL_GPIO_MODE_INPUT_PULL_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULL) + case SL_GPIO_MODE_PUSH_PULL: + gpio_mode = _GPIO_P_MODEL_MODE0_PUSHPULL; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) + case SL_GPIO_MODE_PUSH_PULL_ALTERNATE: + gpio_mode = _GPIO_P_MODEL_MODE0_PUSHPULLALT; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDOR) + case SL_GPIO_MODE_WIRED_OR: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDOR; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN) + case SL_GPIO_MODE_WIRED_OR_PULL_DOWN: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDAND) + case SL_GPIO_MODE_WIRED_AND: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDAND; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDFILTER) + case SL_GPIO_MODE_WIRED_AND_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUP) + case SL_GPIO_MODE_WIRED_AND_PULLUP: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER) + case SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALT; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP; + break; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER) + case SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER: + gpio_mode = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + EFM_ASSERT(SL_HAL_GPIO_MODE_IS_VALID(gpio_mode)); + // If disabling a pin, do not modify DOUT to reduce the chance of // a glitch/spike (may not be sufficient precaution in all use cases). // As mode settings are dependent on DOUT values, setting output value - // prior to mode. @ref enum - sl_hal_gpio_mode_t - if (mode != SL_HAL_GPIO_MODE_DISABLED) { + // prior to mode. @ref enum - sl_gpio_mode_t + if (mode != SL_GPIO_MODE_DISABLED) { if (output_value) { sl_hal_gpio_set_pin(gpio); } else { @@ -103,15 +192,15 @@ void sl_hal_gpio_set_pin_mode(const sl_gpio_t *gpio, // There are two registers controlling the pins for each port. // The MODEL register controls pins 0-7 and MODEH controls pins 8-15. if (gpio->pin < 8) { - sl_hal_bus_reg_write_mask(&(GPIO->P[gpio->port].MODEL), 0xFu << (gpio->pin * 4), mode << (gpio->pin * 4)); + sl_hal_bus_reg_write_mask(&(GPIO->P[gpio->port].MODEL), 0xFu << (gpio->pin * 4), gpio_mode << (gpio->pin * 4)); } else { - sl_hal_bus_reg_write_mask(&(GPIO->P[gpio->port].MODEH), 0xFu << ((gpio->pin - 8) * 4), mode << ((gpio->pin - 8) * 4)); + sl_hal_bus_reg_write_mask(&(GPIO->P[gpio->port].MODEH), 0xFu << ((gpio->pin - 8) * 4), gpio_mode << ((gpio->pin - 8) * 4)); } - // SL_HAL_GPIO_MODE_DISABLED based on DOUT Value (low/high) act as two different configurations. + // SL_GPIO_MODE_DISABLED based on DOUT Value (low/high) act as two different configurations. // By setting mode to disabled first and then modifying the DOUT value, so that // previous mode configuration on given pin not effected. - if (mode == SL_HAL_GPIO_MODE_DISABLED) { + if (mode == SL_GPIO_MODE_DISABLED) { if (output_value) { sl_hal_gpio_set_pin(gpio); } else { @@ -123,17 +212,88 @@ void sl_hal_gpio_set_pin_mode(const sl_gpio_t *gpio, /***************************************************************************//** * Get the mode for a GPIO pin. ******************************************************************************/ -sl_hal_gpio_mode_t sl_hal_gpio_get_pin_mode(const sl_gpio_t *gpio) +sl_gpio_mode_t sl_hal_gpio_get_pin_mode(const sl_gpio_t *gpio) { - sl_hal_gpio_mode_t mode; - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + sl_gpio_mode_t mode = SL_GPIO_MODE_DISABLED; + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + // Determine the current mode of the GPIO pin based on the pin number. if (gpio->pin < 8) { - mode = (sl_hal_gpio_mode_t) ((GPIO->P[gpio->port].MODEL >> (gpio->pin * 4)) & 0xF); + mode = (sl_gpio_mode_t) ((GPIO->P[gpio->port].MODEL >> (gpio->pin * 4)) & 0xF); } else { - mode = (sl_hal_gpio_mode_t) ((GPIO->P[gpio->port].MODEH >> ((gpio->pin - 8) * 4)) & 0xF); + mode = (sl_gpio_mode_t) ((GPIO->P[gpio->port].MODEH >> ((gpio->pin - 8) * 4)) & 0xF); + } + + // Map the hardware-specific mode to the corresponding sl_gpio_mode_t value + switch (mode) { +#if defined(_GPIO_P_MODEL_MODE0_DISABLED) + case _GPIO_P_MODEL_MODE0_DISABLED: + return SL_GPIO_MODE_DISABLED; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUT) + case _GPIO_P_MODEL_MODE0_INPUT: + return SL_GPIO_MODE_INPUT; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULL) + case _GPIO_P_MODEL_MODE0_INPUTPULL: + return SL_GPIO_MODE_INPUT_PULL; +#endif +#if defined(_GPIO_P_MODEL_MODE0_INPUTPULLFILTER) + case _GPIO_P_MODEL_MODE0_INPUTPULLFILTER: + return SL_GPIO_MODE_INPUT_PULL_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULL) + case _GPIO_P_MODEL_MODE0_PUSHPULL: + return SL_GPIO_MODE_PUSH_PULL; +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) + case _GPIO_P_MODEL_MODE0_PUSHPULLALT: + return SL_GPIO_MODE_PUSH_PULL_ALTERNATE; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDOR) + case _GPIO_P_MODEL_MODE0_WIREDOR: + return SL_GPIO_MODE_WIRED_OR; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN) + case _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN: + return SL_GPIO_MODE_WIRED_OR_PULL_DOWN; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDAND) + case _GPIO_P_MODEL_MODE0_WIREDAND: + return SL_GPIO_MODE_WIRED_AND; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDFILTER: + return SL_GPIO_MODE_WIRED_AND_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUP) + case _GPIO_P_MODEL_MODE0_WIREDANDPULLUP: + return SL_GPIO_MODE_WIRED_AND_PULLUP; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER: + return SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) + case _GPIO_P_MODEL_MODE0_WIREDANDALT: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP) + case _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP; +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER) + case _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER: + return SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER; +#endif + default: + EFM_ASSERT(false); + return mode; // returning the default state } - return mode; } /***************************************************************************//** @@ -143,11 +303,11 @@ int32_t sl_hal_gpio_configure_external_interrupt(const sl_gpio_t *gpio, int32_t int_no, sl_gpio_interrupt_flag_t flags) { - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); EFM_ASSERT(SL_GPIO_FLAG_IS_VALID(flags)); EFM_ASSERT(sl_hal_gpio_get_lock_status() == 0); - if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { + if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE && int_no >= 0) { #if defined(_GPIO_EXTIPINSELL_MASK) EFM_ASSERT(SL_HAL_GPIO_INTNO_PIN_VALID(int_no, gpio->pin)); #endif @@ -162,7 +322,7 @@ int32_t sl_hal_gpio_configure_external_interrupt(const sl_gpio_t *gpio, int_no = sl_hal_gpio_get_external_interrupt_number(gpio->pin, interrupts_enabled); } - if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { + if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE && int_no >= 0) { if (int_no < 8) { // The EXTIPSELL register controls pins 0-7 of the interrupt configuration. #if defined(_GPIO_EXTIPSELL_EXTIPSEL0_MASK) @@ -242,7 +402,7 @@ int32_t sl_hal_gpio_configure_wakeup_em4_external_interrupt(const sl_gpio_t *gpi int32_t int_no, bool polarity) { - EFM_ASSERT(SL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); + EFM_ASSERT(SL_HAL_GPIO_PORT_PIN_IS_VALID(gpio->port, gpio->pin)); EFM_ASSERT(sl_hal_gpio_get_lock_status() == 0); int32_t em4_int_no = sl_hal_gpio_get_em4_interrupt_number(gpio); @@ -257,7 +417,7 @@ int32_t sl_hal_gpio_configure_wakeup_em4_external_interrupt(const sl_gpio_t *gpi if (int_no != SL_GPIO_INTERRUPT_UNAVAILABLE) { // GPIO pin mode set. - sl_hal_gpio_set_pin_mode(gpio, SL_HAL_GPIO_MODE_INPUT_PULL_FILTER, (unsigned int)!polarity); + sl_hal_gpio_set_pin_mode(gpio, SL_GPIO_MODE_INPUT_PULL_FILTER, (unsigned int)!polarity); // Enable EM4WU function and set polarity. uint32_t polarityMask = (uint32_t)polarity << (int_no + _GPIO_EM4WUEN_EM4WUEN_SHIFT); diff --git a/simplicity_sdk/platform/peripheral/src/sl_hal_system.c b/simplicity_sdk/platform/peripheral/src/sl_hal_system.c new file mode 100644 index 000000000..baa23e80d --- /dev/null +++ b/simplicity_sdk/platform/peripheral/src/sl_hal_system.c @@ -0,0 +1,649 @@ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_hal_system.h" +#include "sl_hal_syscfg.h" +#include "em_device.h" +#include +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) +#include "sl_se_manager.h" +#include "sli_se_manager_device_data.h" +#endif +#include "sl_status.h" +#include "sl_assert.h" +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** DEFINES ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Bit mask used to extract the part number value without the new naming + * bitfield. */ +#define SYSCFG_CHIPREV_PARTNUMBER1 0xFE0 +#define SYSCFG_CHIPREV_PARTNUMBER0 0xF + +/** @endcond */ + +#define HFRCO_DPLL_FREQUENCY_TABLE_SIZE 11 + +#define DEVINFO_TEMPERATURE_CALTEMP_INTEGER_SHIFT 4 + +/******************************************************************************* + ******************************* TYPEDEF *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) +typedef struct hfrco_dpll_cal_element { + uint32_t min_freq; + uint32_t max_freq; +} hfrco_dpll_cal_element_t; +#endif + +/******************************************************************************* + ****************************** CONSTANTS ********************************** + ******************************************************************************/ +const sl_hal_system_devinfo_adc_t SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES = { + .cal_data = { + .trim_vros0 = 0, + .trim_vros1 = 0, + .trim_gain_4x = 0, + .trim_gain_0x3_int = 0 + }, + .offset = { + .trim_off_1x = 0, + .trim_off_2x = 0, + .trim_off_4x = 0 + } +}; + +const sl_hal_system_devinfo_temperature_t SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES = { + .emu_temp_room = 0, + .cal_temp = 0 +}; + +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) +static const hfrco_dpll_cal_element_t HFRCO_DPLL_FREQUENCY_TABLE[HFRCO_DPLL_FREQUENCY_TABLE_SIZE] = { + { .min_freq = 16000000, .max_freq = 20000000 }, // 18MHz calibration central frequency + { .min_freq = 20000000, .max_freq = 24500000 }, // 22MHz calibration central frequency + { .min_freq = 24500000, .max_freq = 30000000 }, // 27MHz calibration central frequency + { .min_freq = 30000000, .max_freq = 36000000 }, // 33MHz calibration central frequency + { .min_freq = 36000000, .max_freq = 42500000 }, // 39MHz calibration central frequency + { .min_freq = 42500000, .max_freq = 50500000 }, // 46MHz calibration central frequency + { .min_freq = 50500000, .max_freq = 60000000 }, // 55MHz calibration central frequency + { .min_freq = 60000000, .max_freq = 70000000 }, // 65MHz calibration central frequency + { .min_freq = 70000000, .max_freq = 80000000 }, // 75MHz calibration central frequency + { .min_freq = 80000000, .max_freq = 90000000 }, // 85MHz calibration central frequency + { .min_freq = 90000000, .max_freq = 100000000 } // 95MHz calibration central frequency +}; +#endif + +/******************************************************************************* + ****************************** UTILITY ************************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief Get the nth ASCII character of a specified number. + * + * @param[in] input_number + * The number where the digit will be taken. + * + * @param[in] position + * The digit position. + * + * @return + * The ASCII value of the specified digit. + ******************************************************************************/ +char sli_get_n_digit(uint16_t input_number, uint8_t position) +{ + uint32_t exp[] = { 10, 100, 1000, 10000, 100000 }; + uint32_t number = input_number; + + if (position > 4) { + EFM_ASSERT(false); + return '0'; + } + + number = (number % exp[position]); + + if (position != 0) { + number = number / (exp[position - 1]); + } + + return (char)number + '0'; +} +#endif + +#if defined(_DEVINFO_PART0_DIECODE0_MASK) && defined(_SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * @brief Convert hexadecimal ASCII character to integer value. + * + * @param[in] character + * The character to be coverted to a number. + * + * @return + * The uint8_t value of the character given in parameter. + ******************************************************************************/ +uint8_t sli_hex_ascii_to_value(char character) +{ + if (character >= '0' && character <= '9') { + return character - '0'; + } else if (character >= 'A' && character <= 'F') { + return character - 'A'; + } + + return 0U; +} +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/******************************************************************************* + * @brief Get CHIPREV register. + ******************************************************************************/ +void sl_hal_system_get_chip_revision(sl_hal_system_chip_revision_t *rev) +{ +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + uint32_t chip_rev = sl_hal_syscfg_read_chip_rev(); + + rev->minor = (chip_rev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; + rev->major = (chip_rev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + rev->part_number = ((chip_rev & SYSCFG_CHIPREV_PARTNUMBER1) >> 5) | (chip_rev & SYSCFG_CHIPREV_PARTNUMBER0); + rev->family = (uint16_t)0xFFFF; +#elif defined(_SYSCFG_CHIPREV_FAMILY_MASK) + rev->part_number = (uint16_t)0xFFFF; + rev->family = (chip_rev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; +#else + #error No Chip Revision Part Number or Family +#endif +} + +/***************************************************************************//** + * @brief Get the MCU family identifier. + ******************************************************************************/ +sl_hal_system_part_family_t sl_hal_system_get_family(void) +{ +#if defined(_DEVINFO_PART_FAMILY_MASK) + return (DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK + | _DEVINFO_PART_FAMILYNUM_MASK)); +#else + return (DEVINFO->PART0 & (_DEVINFO_PART0_PROTOCOL_MASK + | _DEVINFO_PART0_SERIES_MASK + | _DEVINFO_PART0_DIECODE0_MASK)); +#endif +} + +/***************************************************************************//** + * @brief Get DEVINFO revision. + ******************************************************************************/ +uint8_t sl_hal_system_get_devinfo_rev(void) +{ +#if defined(_DEVINFO_INFO_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) + >> _DEVINFO_INFO_DEVINFOREV_SHIFT); +#elif defined(_DEVINFO_REVISION_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->REVISION & _DEVINFO_REVISION_DEVINFOREV_MASK) + >> _DEVINFO_REVISION_DEVINFOREV_SHIFT); +#else +#error (sl_hal_system.c): Location of devinfo revision is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the default factory calibration value for HFRCO oscillator. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_default_calibration(void) +{ +#if defined(_DEVINFO_HFRCOCALDEFAULT_MASK) + return DEVINFO->HFRCOCALDEFAULT; +#else + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get the speed factory calibration value for HFRCO oscillator. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrco_speed_calibration(void) +{ +#if defined(_DEVINFO_HFRCOCALSPEED_MASK) + return DEVINFO->HFRCOCALSPEED; +#else + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get the HFRCO calibration based on the frequency band. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcodpll_band_calibration(uint32_t frequency) +{ +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + uint8_t band_index = 0xFF; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset; + uint32_t calibration_value = 0; + + for (uint8_t i = 0; i < HFRCO_DPLL_FREQUENCY_TABLE_SIZE; i++) { + if ((frequency >= HFRCO_DPLL_FREQUENCY_TABLE[i].min_freq) + && (frequency <= HFRCO_DPLL_FREQUENCY_TABLE[i].max_freq)) { + band_index = i; + break; + } + } + + if (band_index >= HFRCO_DPLL_FREQUENCY_TABLE_SIZE) { + return 0; + } + + // Calculate memory offset based on the band index we want. + offset = (band_index * 4) + DEVINFO_GP_HFRCODPLLBAND0_OFFSET; + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + return 0; + } + + // Send the SE command to retrieve the HFRCODPLL calibration for a given band from the DEVINFO OTP section + status = sli_se_device_data_read_word(&se_command_ctx, otp_section_id, offset, &calibration_value); + if (status != SL_STATUS_OK) { + return 0; + } + + return calibration_value; +#else + (void)frequency; + return 0; +#endif +} + +/***************************************************************************//** + * Get a factory calibration value for HFRCOCEM23 oscillator. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfrcoem23_calibration(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset = DEVINFO_GP_HFRCOEM23DEFAULT_OFFSET; + uint32_t calibration_value = 0; + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + return 0; + } + + // Send the SE command to retrieve the HFRCOEM23 calibration from the DEVINFO OTP section + status = sli_se_device_data_read_word(&se_command_ctx, otp_section_id, offset, &calibration_value); + if (status != SL_STATUS_OK) { + return 0; + } + + return calibration_value; +#else + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get a factory calibration value for HFXOCAL. + ******************************************************************************/ +uint32_t sl_hal_system_get_hfxocal(void) +{ +#if defined(_DEVINFO_HFXOCAL_MASK) + return DEVINFO->HFXOCAL; +#else + return 0; +#endif +} + +/***************************************************************************//** + * @brief Get family security capability. + ******************************************************************************/ +sl_hal_system_security_capability_t sl_hal_system_get_security_capability(void) +{ + sl_hal_system_security_capability_t sc = SL_SYSTEM_SECURITY_CAPABILITY_UNKNOWN; + + uint16_t mcu_feature_set_major; + uint16_t device_number; + device_number = sl_hal_system_get_part_number(); + mcu_feature_set_major = 'A' + (device_number / 1000); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // override feature set since BRD4182A Rev A00 -> rev B02 are marked "A" + mcu_feature_set_major = 'C'; +#endif + + switch (mcu_feature_set_major) { + case 'A': + sc = SL_SYSTEM_SECURITY_CAPABILITY_SE; + break; + + case 'B': + sc = SL_SYSTEM_SECURITY_CAPABILITY_VAULT; + break; + + case 'C': + sc = SL_SYSTEM_SECURITY_CAPABILITY_ROT; + break; + + default: + sc = SL_SYSTEM_SECURITY_CAPABILITY_UNKNOWN; + break; + } + + return sc; +} + +/***************************************************************************//** + * @brief Get the unique number for this device. + ******************************************************************************/ +uint64_t sl_hal_system_get_unique(void) +{ + uint32_t tmp = DEVINFO->EUI64L; + return ((uint64_t)DEVINFO->EUI64H << 32) | tmp; +} + +/***************************************************************************//** + * @brief Get the production revision for this part. + ******************************************************************************/ +uint8_t sl_hal_system_get_prod_rev(void) +{ +#if defined(_DEVINFO_INFO_PRODREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) + >> _DEVINFO_INFO_PRODREV_SHIFT); +#elif defined(_DEVINFO_REVISION_PRODREV_MASK) + return (uint8_t)((DEVINFO->REVISION & _DEVINFO_REVISION_PRODREV_MASK) + >> _DEVINFO_REVISION_PRODREV_SHIFT); +#else +#error (sl_hal_system.c): Location of production revision is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the SRAM Base Address. + ******************************************************************************/ +uint32_t sl_hal_system_get_sram_base_address(void) +{ + return SRAM_BASE; +} + +/***************************************************************************//** + * @brief Get the SRAM size (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_sram_size(void) +{ +#if defined(_DEVINFO_MSIZE_SRAM_MASK) + return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT); +#elif defined(_DEVINFO_EMBSIZE_RAM_MASK) + return (uint16_t)((DEVINFO->EMBSIZE & _DEVINFO_EMBSIZE_RAM_MASK) + >> _DEVINFO_EMBSIZE_RAM_SHIFT); +#else + #error (sl_hal_system.c): Location of SRAM Size is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the flash size (in KB). + ******************************************************************************/ +uint16_t sl_hal_system_get_flash_size(void) +{ +#if defined(_DEVINFO_MSIZE_FLASH_MASK) + return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT); +#elif defined(_DEVINFO_STACKMSIZE_FLASH_MASK) + uint16_t stacked_flach_size = (uint16_t)((DEVINFO->STACKMSIZE & _DEVINFO_STACKMSIZE_FLASH_MASK) + >> _DEVINFO_STACKMSIZE_FLASH_SHIFT); + + if (stacked_flach_size == 0) { + // Defined in linker script for external flash provided by customers. + extern uint32_t __flash_size__; + // Get flash size in kB. + stacked_flach_size = (uint16_t)(uintptr_t)&__flash_size__ / 1024; + } + + return stacked_flach_size; +#endif +} + +/***************************************************************************//** + * @brief Get the flash page size in bytes. + ******************************************************************************/ +uint32_t sl_hal_system_get_flash_page_size(void) +{ +#if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + uint32_t tmp; + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; + return 1UL << ((tmp + 10UL) & 0x1FUL); +#else + // Defined in linker script for external flash provided by customers. + extern uint32_t __flash_page_size__; + return (uintptr_t)&__flash_page_size__; +#endif +} + +/***************************************************************************//** + * @brief Get the MCU part number. + ******************************************************************************/ +uint16_t sl_hal_system_get_part_number(void) +{ +#if defined(_DEVINFO_PART_DEVICENUM_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) + >> _DEVINFO_PART_DEVICENUM_SHIFT); +#elif defined(_DEVINFO_PART0_DIECODE0_MASK) && defined(_SILICON_LABS_SECURITY_FEATURE_VAULT) + // Encode features to the series 2 format. + // Add security level vault high for SIxG301. + uint16_t device_number = 1000; + uint32_t register_value = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE1_MASK) >> _DEVINFO_PART1_FEATURE1_SHIFT; + + device_number = sli_hex_ascii_to_value((char)register_value) * 100; + + register_value = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE2_MASK) >> _DEVINFO_PART1_FEATURE2_SHIFT; + device_number += sli_hex_ascii_to_value((char)register_value) * 10; + + register_value = (DEVINFO->PART2 & _DEVINFO_PART2_FEATURE3_MASK) >> _DEVINFO_PART2_FEATURE3_SHIFT; + device_number += sli_hex_ascii_to_value((char)register_value); + + return device_number; +#else +#error (em_system.c): Location of device part number is not defined. +#endif +} + +/***************************************************************************//** + * @brief Get the SoC or MCU features. + ******************************************************************************/ +sl_hal_system_features_t sl_hal_system_get_part_features(void) +{ + sl_hal_system_features_t part_features = { .feature1 = '0', .feature2 = '0', .feature3 = '0' }; + +#if defined(_SILICON_LABS_32B_SERIES_2) + uint16_t device_number = ((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) >> _DEVINFO_PART_DEVICENUM_SHIFT); + + part_features.feature1 = sli_get_n_digit(device_number, 2); + part_features.feature2 = sli_get_n_digit(device_number, 1); + part_features.feature3 = sli_get_n_digit(device_number, 0); + +#elif defined(_SILICON_LABS_32B_SERIES_3) + + part_features.feature1 = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE1_MASK) >> _DEVINFO_PART1_FEATURE1_SHIFT; + part_features.feature2 = (DEVINFO->PART1 & _DEVINFO_PART1_FEATURE2_MASK) >> _DEVINFO_PART1_FEATURE2_SHIFT; + part_features.feature3 = (DEVINFO->PART2 & _DEVINFO_PART2_FEATURE3_MASK) >> _DEVINFO_PART2_FEATURE3_SHIFT; + +#else +#error Not defined for this die. +#endif + + return part_features; +} + +/***************************************************************************//** + * @brief Get the temperature information. + ******************************************************************************/ +void sl_hal_system_get_temperature_info(sl_hal_system_devinfo_temperature_t *info) +{ +#if defined(_DEVINFO_CALTEMP_MASK) || defined(_DEVINFO_EMUTEMP_MASK) +#if defined(_DEVINFO_CALTEMP_TEMP_MASK) + info->cal_temp = ((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) + >> _DEVINFO_CALTEMP_TEMP_SHIFT); +#else + info->cal_temp = 0; +#endif +#if defined(_DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) + info->emu_temp_room = ((DEVINFO->EMUTEMP & _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) + >> _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT); +#else + info->emu_temp_room = 0; +#endif +#elif defined (_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset = DEVINFO_GP_TEMPERATURE_OFFSET; + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES; + return; + } + + // Send the SE command to retrieve the temperature information from the DEVINFO OTP section + status = sli_se_device_data_read_word(&se_command_ctx, otp_section_id, offset, (uint32_t*)info); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_TEMPERATURE_RESET_VALUES; + return; + } + + // Divide the temperature by 16 to retrieve only the integer part of the temperature value. + info->cal_temp = info->cal_temp >> DEVINFO_TEMPERATURE_CALTEMP_INTEGER_SHIFT; +#else + (void)info; +#endif +} + +/******************************************************************************* + * @brief Reads CHIPREV register. + ******************************************************************************/ +uint32_t sl_hal_syscfg_read_chip_rev(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_chiprev_register(); +#else + return SYSCFG->CHIPREV; +#endif +} + +/******************************************************************************* + * @brief Set SYSTICEXTCLKEN bit in CFGSYSTIC to one. + ******************************************************************************/ +void sl_hal_syscfg_set_systicextclken_cfgsystic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} + +/******************************************************************************* + * @brief Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero. + ******************************************************************************/ +void sl_hal_syscfg_clear_systicextclken_cfgsystic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/***************************************************************************//** + * @brief Set floating point co-processor (FPU) access mode. + ******************************************************************************/ +void sl_hal_system_fpu_set_access_mode(sl_hal_system_fpu_access_t access_mode) +{ + SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | access_mode; +} +#endif + +/***************************************************************************//** + * @brief Get the ADC calibration info. + ******************************************************************************/ +void sl_hal_system_get_adc_calibration_info(sl_hal_system_devinfo_adc_t *info) +{ +#if defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + sl_status_t status; + sl_se_command_context_t se_command_ctx; + sli_se_device_data_t otp_section_id = (sli_se_device_data_t)(SLI_SE_DEVICE_DATA_DI0 + DEVINFO_GP_FRAGMENT_INDEX); + uint32_t offset = DEVINFO_GP_ADC0CALDATA_OFFSET; + EFM_ASSERT(info != NULL); + + // Initialize command context + status = sl_se_init_command_context(&se_command_ctx); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; + return; + } + + // Send the SE command to retrieve the ADC calibration from the DEVINFO OTP section + status = sli_se_device_data_read_chunk(&se_command_ctx, + otp_section_id, + offset, + sizeof(sl_hal_system_devinfo_adc_offset_t), + info); + if (status != SL_STATUS_OK) { + *info = SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; + return; + } +#else + *info = SL_HAL_SYSTEM_DEVINFO_ADC_RESET_VALUES; +#endif +} + +/** @} (end addtogroup system) */ diff --git a/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h b/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h index 983c4edf6..f5737d6cd 100644 --- a/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h +++ b/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg1x/rail_chip_specific.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief This file contains the type definitions for efr32xg1x chip-specific + * @brief This file contains the type definitions for EFR32xG1x chip-specific * aspects of RAIL. ******************************************************************************* * # License @@ -45,60 +45,49 @@ #include "rail_features.h" -#if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) -// Copied from rail_types.h to satisfy doxygen build. -/// The RAIL library does not use enumerations because the ARM EABI leaves their -/// size ambiguous, which causes problems if the application is built -/// with different flags than the library. Instead, uint8_t typedefs -/// are used in compiled code for all enumerations. For documentation purposes, this is -/// converted to an actual enumeration since it's much easier to read in Doxygen. -#define RAIL_ENUM(name) enum name -/// This macro is a more generic version of the \ref RAIL_ENUM() macro that -/// allows the size of the type to be overridden instead of forcing the use of -/// a uint8_t. See \ref RAIL_ENUM() for more information. -#define RAIL_ENUM_GENERIC(name, type) enum name -#endif//(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) - #ifdef __cplusplus extern "C" { #endif +/****************************************************************************** + * General Structures + *****************************************************************************/ /** - * @addtogroup General_EFR32XG1 EFR32xG1 - * @{ - * @brief EFR32xG1-specific initialization data types + * @addtogroup General_EFR32XG1X EFR32xG1x * @ingroup General + * @{ + * @brief Types specific to the EFR32xG1x for general configuration. */ #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * @def RAIL_EFR32XG1_STATE_BUFFER_BYTES - * @brief The EFR32XG1 series size needed for + * @brief The EFR32xG1 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG1_STATE_BUFFER_BYTES 480 +#define RAIL_EFR32XG1_STATE_BUFFER_BYTES 440 /** * @def RAIL_EFR32XG12_STATE_BUFFER_BYTES - * @brief The EFR32XG12 series size needed for + * @brief The EFR32xG12 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG12_STATE_BUFFER_BYTES 488 +#define RAIL_EFR32XG12_STATE_BUFFER_BYTES 456 /** * @def RAIL_EFR32XG13_STATE_BUFFER_BYTES - * @brief The EFR32XG13 series size needed for + * @brief The EFR32xG13 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG13_STATE_BUFFER_BYTES 496 +#define RAIL_EFR32XG13_STATE_BUFFER_BYTES 464 /** * @def RAIL_EFR32XG14_STATE_BUFFER_BYTES - * @brief The EFR32XG14 series size needed for + * @brief The EFR32xG14 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG14_STATE_BUFFER_BYTES 496 +#define RAIL_EFR32XG14_STATE_BUFFER_BYTES 464 /** * @def RAIL_STATE_BUFFER_BYTES @@ -119,6 +108,10 @@ extern "C" { #error "Unsupported platform!" #endif +#endif//DOXYGEN_SHOULD_SKIP_THIS + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + /** * @def RAIL_SEQ_IMAGE_1 * @brief A macro for the first sequencer image. @@ -134,14 +127,14 @@ extern "C" { #if (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) /** * @def RAIL_SEQ_IMAGE_ZWAVE - * @brief A chip-specific macro for the sequencer image used on EFR32XG13 OPNs + * @brief A chip-specific macro for the sequencer image used on EFR32xG13 OPNs * with ZWave. */ #define RAIL_SEQ_IMAGE_ZWAVE RAIL_SEQ_IMAGE_1 /** * @def RAIL_SEQ_IMAGE_HIGH_BW_PHY - * @brief A chip-specific macro for the sequencer image used on EFR32XG13 OPNs + * @brief A chip-specific macro for the sequencer image used on EFR32xG13 OPNs * with High BW PHYs supported. */ #define RAIL_SEQ_IMAGE_HIGH_BW_PHY RAIL_SEQ_IMAGE_2 @@ -170,16 +163,11 @@ extern "C" { #define RAIL_SEQ_IMAGE_COUNT 1 #endif //(_SILICON_LABS_32B_SERIES_1_CONFIG == 3) -/** - * Redefined here for use in common source code \ref RAIL_RadioStateEfr32_t - */ -typedef RAIL_RadioStateEfr32_t RAIL_RacRadioState_t; - /** * @typedef RAIL_TimerTick_t - * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. This - * wraps at the same time as the RAIL timebase, but at a value before the full - * 32 bit range. + * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. + * This wraps at the same time as the RAIL timebase, but at a value before + * the full 32 bit range. * * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between * two \ref RAIL_TimerTick_t values to microseconds. @@ -199,7 +187,7 @@ typedef uint32_t RAIL_TimerTick_t; * that drives the RAIL timebase. * * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. On EFR32XG1 family of + * clock period, and will simply be a register read. On EFR32xG1x family of * chips, ticks wrap in about 72 minutes and for all other series 1 they * wrap in about 17 minutes, since it does not use the full 32-bit range. * For more details, check the documentation for \ref RAIL_TimerTick_t. @@ -208,16 +196,13 @@ extern const volatile uint32_t *RAIL_TimerTick; /** * A global pointer to the memory address of the internal RAIL hardware timer - * that captures the latest RX packet reception time. This would not include - * the RX chain delay, so may not be equal to the packet timestamp, passed to - * the application, representing the actual on-air time the packet finished. + * that captures the latest RX packet reception time. + * See \ref RAIL_TimerTick_t for its granularity and range. * - * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. On EFR32XG1 family of - * chips, ticks wrap in about 72 minutes and for all other series 1 and - * they wrap in about 17 minutes, since it does not use the full - * 32-bit range. - * For more details, check the documentation for \ref RAIL_TimerTick_t. + * @note This would not include the RX chain delay, so may not exactly + * correspond to the \ref RAIL_Time_t packet timestamp available within + * \ref RAIL_RxPacketDetails_t::timeReceived which reflects the actual + * on-air time that the packet finished. */ extern const volatile uint32_t *RAIL_RxPacketTimestamp; @@ -239,18 +224,19 @@ RAIL_Time_t RAIL_TimerTicksToUs(RAIL_TimerTick_t startTick, * \ref RAIL_Time_t time. */ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); + #endif//DOXYGEN_SHOULD_SKIP_THIS -/** @} */ // end of group General_EFR32XG1 +/** @} */ // end of group General_EFR32XG1X -// ----------------------------------------------------------------------------- -// Multiprotocol -// ----------------------------------------------------------------------------- +/****************************************************************************** + * Multiprotocol + *****************************************************************************/ /** - * @addtogroup Multiprotocol_EFR32 EFR32 - * @{ - * @brief EFR32-specific multiprotocol support defines + * @addtogroup Multiprotocol_EFR32XG1X EFR32xG1x * @ingroup Multiprotocol + * @{ + * @brief EFR32xG1x-specific multiprotocol support defines. */ /** @@ -259,21 +245,21 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); */ #define TRANSITION_TIME_US 430 -/** @} */ // end of group Multiprotocol_EFR32 +/** @} */ // end of group Multiprotocol_EFR32XG1X -// ----------------------------------------------------------------------------- -// Calibration -// ----------------------------------------------------------------------------- +/****************************************************************************** + * Calibration + *****************************************************************************/ /** - * @addtogroup Calibration_EFR32 EFR32 - * @{ - * @brief EFR32-specific Calibrations + * @addtogroup Calibration_EFR32XG1X EFR32xG1x * @ingroup Calibration + * @{ + * @brief EFR32xG1x-specific Calibrations. */ /** * @def RAIL_RF_PATHS - * @brief Indicates the number of RF Paths supported + * @brief Indicates the number of RF Paths supported. */ #define RAIL_RF_PATHS 1 @@ -291,16 +277,16 @@ struct RAIL_ChannelConfigEntryAttr { RAIL_RxIrCalValues_t calValues; }; -/** @} */ // end of group Calibration_EFR32 +/** @} */ // end of group Calibration_EFR32XG1X -// ----------------------------------------------------------------------------- -// Transmit -// ----------------------------------------------------------------------------- +/****************************************************************************** + * Transmit + *****************************************************************************/ /** - * @addtogroup PA_EFR32 EFR32 - * @{ + * @addtogroup PA_EFR32XG1X EFR32xG1x * @ingroup PA - * @brief Types specific to the EFR32 for dealing with the on-chip PAs. + * @{ + * @brief Types specific to the EFR32xG1x for dealing with the on-chip PAs. */ /** @@ -348,7 +334,7 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN /** - * The number of PA's on this chip. (Including Virtual PAs) + * The number of PA's on this chip (including Virtual PAs). */ #define RAIL_NUM_PA (3U) @@ -364,14 +350,16 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG) #endif//DOXYGEN_SHOULD_SKIP_THIS -/** @} */ // end of group PA_EFR32 +/** @} */ // end of group PA_EFR32XG1X /****************************************************************************** * RX Channel Hopping *****************************************************************************/ /** - * @addtogroup Rx_Channel_Hopping RX Channel Hopping + * @addtogroup Rx_Channel_Hopping_EFR32XG1X EFR32xG1x + * @ingroup Rx_Channel_Hopping * @{ + * @brief EFR32xG1x-specific RX channel hopping. */ /// The static amount of memory needed per channel for channel hopping, measured @@ -383,11 +371,16 @@ struct RAIL_ChannelConfigEntryAttr { #error "Update rail_types.h RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE" #endif -/** @} */ // end of group Rx_Channel_Hopping +/** @} */ // end of group Rx_Channel_Hopping_EFR32XG1X +/****************************************************************************** + * Sleep Structures + *****************************************************************************/ /** - * @addtogroup Sleep + * @addtogroup Sleep_EFR32XG1X EFR32xG1x + * @ingroup Sleep * @{ + * @brief EFR32xG1x-specific Sleeping. */ /// Default PRS channel to use when configuring sleep @@ -401,25 +394,29 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U) #endif -/** @} */ // end of group Sleep +/** @} */ // end of group Sleep_EFR32XG1X +/****************************************************************************** + * State Transitions + *****************************************************************************/ /** - * @addtogroup State_Transitions_EFR32 EFR32 - * @{ + * @addtogroup State_Transitions_EFR32XG1X EFR32xG1x * @ingroup State_Transitions + * @{ + * @brief EFR32xG1x-specific State Transitions. */ /** * @def RAIL_MINIMUM_TRANSITION_US - * @brief The minimum value for a consistent RAIL transition + * @brief The minimum value for a consistent RAIL transition. * @note Transitions may need to be slower than this when using longer - * \ref RAIL_TxPowerConfig_t::rampTime values + * \ref RAIL_TxPowerConfig_t::rampTime values. */ #define RAIL_MINIMUM_TRANSITION_US (100U) /** * @def RAIL_MAXIMUM_TRANSITION_US - * @brief The maximum value for a consistent RAIL transition + * @brief The maximum value for a consistent RAIL transition. */ #if (_SILICON_LABS_32B_SERIES_1_CONFIG == 1) #define RAIL_MAXIMUM_TRANSITION_US (13000U) @@ -427,7 +424,12 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_MAXIMUM_TRANSITION_US (1000000U) #endif//(_SILICON_LABS_32B_SERIES_1_CONFIG == 1) -/** @} */ // end of group State_Transitions_EFR32 +/** + * Internal Radio State type mapping for EFR32 chips. + */ +typedef RAIL_RadioStateEfr32_t RAIL_RacRadioState_t; + +/** @} */ // end of group State_Transitions_EFR32XG1X #ifdef __cplusplus } diff --git a/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h b/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h index 828212486..b8c3d0d3b 100644 --- a/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h +++ b/simplicity_sdk/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h @@ -1,6 +1,6 @@ /***************************************************************************//** * @file - * @brief This file contains the type definitions for efr32xg2x chip-specific + * @brief This file contains the type definitions for EFR32xG2x chip-specific * aspects of RAIL. ******************************************************************************* * # License @@ -48,240 +48,84 @@ #include "rail_chip_specific_internal.h" #endif -#if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) -// Copied from rail_types.h to satisfy doxygen build. -/// The RAIL library does not use enumerations because the ARM EABI leaves their -/// size ambiguous, which causes problems if the application is built -/// with different flags than the library. Instead, uint8_t typedefs -/// are used in compiled code for all enumerations. For documentation purposes, this is -/// converted to an actual enumeration since it's much easier to read in Doxygen. -#define RAIL_ENUM(name) enum name -/// This macro is a more generic version of the \ref RAIL_ENUM() macro that -/// allows the size of the type to be overridden instead of forcing the use of -/// a uint8_t. See \ref RAIL_ENUM() for more information. -#define RAIL_ENUM_GENERIC(name, type) enum name -#endif //(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) - #ifdef __cplusplus extern "C" { #endif -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -// This section serves as a compatibility layer until sl_gpio is fully supported on Series 2 devices. -#include "em_gpio.h" -/** @defgroup GPIO_Modes GPIO_Modes - * @{ - * @brief GPIO Modes - */ -#define SL_GPIO_MODE_PUSH_PULL gpioModePushPull ///< Push-Pull mode for GPIO. -#define SL_GPIO_MODE_DISABLED gpioModeDisabled ///< Disabled mode for GPIO. -#define SL_GPIO_MODE_INPUT_PULL gpioModeInputPull ///< Input-Pull mode for GPIO. -#define SL_GPIO_MODE_INPUT gpioModeInput ///< Input mode for GPIO. -/** @} */ - -/** @defgroup GPIO_Port_Definitions GPIO_Port_Definitions - * @{ - * @brief GPIO Port Definitions - */ -#define sl_gpio_port_t GPIO_Port_TypeDef ///< Typedef for GPIO port. -#define SL_GPIO_PORT_A gpioPortA ///< Definition for GPIO port A. -#define SL_GPIO_PORT_IS_VALID GPIO_PORT_VALID ///< Macro to check if GPIO port is valid. -#define SL_GPIO_PORT_PIN_IS_VALID GPIO_PORT_PIN_VALID ///< Macro to check if GPIO port pin is valid. -/** @} */ - -/** @defgroup GPIO_Interrupts GPIO_Interrupts - * @{ - * @brief GPIO Interrupts - */ -#define sl_gpio_disable_interrupts GPIO_IntDisable ///< Macro to disable GPIO interrupts. -#define sl_hal_gpio_clear_interrupts GPIO_IntClear ///< Macro to clear GPIO interrupts. -/** @} */ - -/** @defgroup GPIO_Initialization GPIO_Initialization - * @{ - * @brief GPIO Initialization - */ -#define sl_gpio_init GPIOINT_Init ///< Macro to initialize GPIO. -/** @} */ - -/** @defgroup PRS_Channel_Count PRS_Channel_Count - * @{ - * @brief PRS Channel Count - */ -#define SL_HAL_PRS_ASYNC_CHAN_COUNT PRS_ASYNC_CHAN_COUNT ///< PRS asynchronous channel count. -/** @} */ - -#ifndef RAIL_UNIT_TEST -/** - * @struct sl_gpio_t - * @brief Structure to define GPIO pin configuration. - * - * @var sl_gpio_t::port - * The GPIO port number. - * - * @var sl_gpio_t::pin - * The GPIO pin number. - */ -typedef struct { - uint8_t port; - uint8_t pin; -} sl_gpio_t; - -/** - * @brief Sets the mode and output value of a GPIO pin. - * - * @param[in] gpio Pointer to the GPIO structure. - * @param[in] mode The mode to set for the GPIO pin. - * @param[in] output_value The output value to set for the GPIO pin if it is an output. - * - * @return Returns SL_STATUS_OK on successful operation. - */ -__STATIC_INLINE sl_status_t sl_gpio_set_pin_mode(const sl_gpio_t *gpio, - uint32_t mode, - bool output_value) -{ - GPIO_PinModeSet(gpio->port, gpio->pin, mode, output_value); - return SL_STATUS_OK; -} - -/** - * @brief Clears the output of a GPIO pin. - * - * @param[in] gpio Pointer to the GPIO structure. - * - * @return Returns SL_STATUS_OK on successful operation. - */ -__STATIC_INLINE sl_status_t sl_gpio_clear_pin(const sl_gpio_t *gpio) -{ - GPIO_PinOutClear(gpio->port, gpio->pin); - return SL_STATUS_OK; -} - -/** - * @brief Sets the output of a GPIO pin. - * - * @param[in] gpio Pointer to the GPIO structure. - * - * @return Returns SL_STATUS_OK on successful operation. - */ -__STATIC_INLINE sl_status_t sl_gpio_set_pin(const sl_gpio_t *gpio) -{ - GPIO_PinOutSet(gpio->port, gpio->pin); - return SL_STATUS_OK; -} - -/** - * @brief Gets the output value of a GPIO pin. - * - * @param[in] gpio Pointer to the GPIO structure. - * @param[out] pin_value Pointer to store the output value of the GPIO pin. - * - * @return Returns SL_STATUS_OK on successful operation. - */ -__STATIC_INLINE sl_status_t sl_gpio_get_pin_output(const sl_gpio_t *gpio, bool *pin_value) -{ - *pin_value = GPIO_PinOutGet(gpio->port, gpio->pin); - return SL_STATUS_OK; -} - -/** - * @brief Gets the input value of a GPIO pin. - * - * @param[in] gpio Pointer to the GPIO structure. - * @param[out] pin_value Pointer to store the input value of the GPIO pin. - * - * @return Returns SL_STATUS_OK on successful operation. - */ -__STATIC_INLINE sl_status_t sl_gpio_get_pin_input(const sl_gpio_t *gpio, bool *pin_value) -{ - *pin_value = GPIO_PinInGet(gpio->port, gpio->pin); - return SL_STATUS_OK; -} - -/** - * @brief Toggles the state of a GPIO pin. - * - * @param[in] gpio Pointer to the GPIO structure. - * - * @return Returns SL_STATUS_OK on successful operation. - */ -__STATIC_INLINE sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio) -{ - GPIO_PinOutToggle(gpio->port, gpio->pin); - return SL_STATUS_OK; -} -#endif //RAIL_UNIT_TEST - -#endif // !DOXYGEN_SHOULD_SKIP_THIS - /****************************************************************************** * General Structures *****************************************************************************/ /** - * @addtogroup General_EFR32XG2X EFR32XG2X + * @addtogroup General_EFR32XG2X EFR32xG2x * @ingroup General * @{ - * @brief Types specific to the EFR32XG2X for general configuration. + * @brief Types specific to the EFR32xG2x for general configuration. */ #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * @def RAIL_EFR32XG21_STATE_BUFFER_BYTES - * @brief The EFR32XG21 series size needed for + * @brief The EFR32xG21 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG21_STATE_BUFFER_BYTES 560 +#define RAIL_EFR32XG21_STATE_BUFFER_BYTES 592 /** * @def RAIL_EFR32XG22_STATE_BUFFER_BYTES - * @brief The EFR32XG22 series size needed for + * @brief The EFR32xG22 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG22_STATE_BUFFER_BYTES 568 +#define RAIL_EFR32XG22_STATE_BUFFER_BYTES 608 /** * @def RAIL_EFR32XG23_STATE_BUFFER_BYTES - * @brief The EFR32XG23 series size needed for + * @brief The EFR32xG23 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG23_STATE_BUFFER_BYTES 584 +#define RAIL_EFR32XG23_STATE_BUFFER_BYTES 616 /** * @def RAIL_EFR32XG24_STATE_BUFFER_BYTES - * @brief The EFR32XG24 series size needed for + * @brief The EFR32xG24 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG24_STATE_BUFFER_BYTES 592 +#define RAIL_EFR32XG24_STATE_BUFFER_BYTES 632 /** * @def RAIL_EFR32XG25_STATE_BUFFER_BYTES - * @brief The EFR32XG25 series size needed for + * @brief The EFR32xG25 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 592 +#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 624 /** * @def RAIL_EFR32XG26_STATE_BUFFER_BYTES - * @brief The EFR32XG26 series size needed for + * @brief The EFR32xG26 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG26_STATE_BUFFER_BYTES 592 +#define RAIL_EFR32XG26_STATE_BUFFER_BYTES 632 /** * @def RAIL_EFR32XG27_STATE_BUFFER_BYTES - * @brief The EFR32XG27 series size needed for + * @brief The EFR32xG27 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG27_STATE_BUFFER_BYTES 568 +#define RAIL_EFR32XG27_STATE_BUFFER_BYTES 608 /** * @def RAIL_EFR32XG28_STATE_BUFFER_BYTES - * @brief The EFR32XG28 series size needed for + * @brief The EFR32xG28 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG28_STATE_BUFFER_BYTES 624 + +/** + * @def RAIL_EFR32XG29_STATE_BUFFER_BYTES + * @brief The EFR32XG29 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_EFR32XG28_STATE_BUFFER_BYTES 584 +#define RAIL_EFR32XG29_STATE_BUFFER_BYTES 608 #ifndef RAIL_STATE_BUFFER_BYTES /** @@ -306,6 +150,8 @@ __STATIC_INLINE sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio) #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG27_STATE_BUFFER_BYTES #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) #define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG28_STATE_BUFFER_BYTES +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG29_STATE_BUFFER_BYTES #else #define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen #error "Unsupported platform!" @@ -320,36 +166,36 @@ __STATIC_INLINE sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio) * @def RAIL_SEQ_IMAGE_1 * @brief A macro for the first sequencer image. */ -#define RAIL_SEQ_IMAGE_1 1 +#define RAIL_SEQ_IMAGE_1 1 /** * @def RAIL_SEQ_IMAGE_2 * @brief A macro for the second sequencer image. */ -#define RAIL_SEQ_IMAGE_2 2 +#define RAIL_SEQ_IMAGE_2 2 #ifndef RAIL_INTERNAL_BUILD #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) /** * @def RAIL_SEQ_IMAGE_PA_10_DBM - * @brief A chip-specific macro for the sequencer image used on EFR32XG24 and EFR32XG26 OPNs + * @brief A chip-specific macro for the sequencer image used on EFR32xG24 and EFR32xG26 OPNs * with a 10 dBm PA. */ -#define RAIL_SEQ_IMAGE_PA_10_DBM RAIL_SEQ_IMAGE_1 +#define RAIL_SEQ_IMAGE_PA_10_DBM RAIL_SEQ_IMAGE_1 /** * @def RAIL_SEQ_IMAGE_PA_20_DBM - * @brief A chip-specific macro for the sequencer image used on EFR32XG24 and EFR32XG26 OPNs + * @brief A chip-specific macro for the sequencer image used on EFR32xG24 and EFR32xG26 OPNs * with a 20 dBm PA. */ -#define RAIL_SEQ_IMAGE_PA_20_DBM RAIL_SEQ_IMAGE_2 +#define RAIL_SEQ_IMAGE_PA_20_DBM RAIL_SEQ_IMAGE_2 /** * @def RAIL_SEQ_IMAGE_COUNT * @brief A macro for the total number of sequencer images supported on the * platform. */ -#define RAIL_SEQ_IMAGE_COUNT 2 +#define RAIL_SEQ_IMAGE_COUNT 2 #else //((_SILICON_LABS_32B_SERIES_2_CONFIG != 4) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 6)) @@ -358,22 +204,17 @@ __STATIC_INLINE sl_status_t sl_gpio_toggle_pin(const sl_gpio_t *gpio) * @brief A chip-specific macro for the default sequencer image on platforms * that support only one sequencer image. */ -#define RAIL_SEQ_IMAGE_DEFAULT RAIL_SEQ_IMAGE_1 +#define RAIL_SEQ_IMAGE_DEFAULT RAIL_SEQ_IMAGE_1 /** * @def RAIL_SEQ_IMAGE_COUNT * @brief A macro for the total number of sequencer images supported on the * platform. */ -#define RAIL_SEQ_IMAGE_COUNT 1 +#define RAIL_SEQ_IMAGE_COUNT 1 #endif //((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) #endif //RAIL_INTERNAL_BUILD -/** - * Redefined here for use in common source code \ref RAIL_RadioStateEfr32_t - */ -typedef RAIL_RadioStateEfr32_t RAIL_RacRadioState_t; - /** * @struct RAIL_RffpllConfig_t * @brief Stores information relevant to the Radio-Friendly Frequency @@ -381,11 +222,11 @@ typedef RAIL_RadioStateEfr32_t RAIL_RacRadioState_t; * memory. */ typedef struct { - /** Divider X (Modem Clock), Divider Y (M33 System Clock), and Divider N (Feedback) values */ + /** Divider X (Modem Clock), Divider Y (M33 System Clock), and Divider N (Feedback) values. */ uint32_t dividers; - /** Radio clock frequency in Hz */ + /** Radio clock frequency in Hz. */ uint32_t radioFreqHz; - /** System clock frequency in Hz */ + /** System clock frequency in Hz. */ uint32_t sysclkFreqHz; } RAIL_RffpllConfig_t; @@ -427,9 +268,9 @@ typedef struct { /** * @typedef RAIL_TimerTick_t - * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. This - * wraps at the same time as the RAIL timebase, but at a value before the full - * 32 bit range. + * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. + * A tick is roughly 0.5 microseconds but it wraps somewhat before + * 0xFFFFFFFF giving a time range of about 17 minutes. * * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between * two \ref RAIL_TimerTick_t values to microseconds. @@ -437,36 +278,31 @@ typedef struct { typedef uint32_t RAIL_TimerTick_t; /** - * @def RAIL_GetTimerTick(channel) + * @def RAIL_GetTimerTick(timerTickType) * @brief The RAIL hardware timer ticks value. * - * @note channel is added for compatibility reasons and is ignored here. + * @note timerTickType is added for compatibility reasons and is ignored here; + * this gets the equivalent of \ref RAIL_TIMER_TICK_DEFAULT. */ -#define RAIL_GetTimerTick(channel) (*RAIL_TimerTick) +#define RAIL_GetTimerTick(timerTickType) (*RAIL_TimerTick) /** - * A global pointer to the memory address of the internal RAIL hardware timer - * that drives the RAIL timebase. - * - * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. On EFR32XG2X family of - * chips, ticks wrap in about 17 minutes, since it does not use the full - * 32-bit range. - * For more details, check the documentation for \ref RAIL_TimerTick_t. + * A global pointer to the memory address of the 32-bit + * \ref RAIL_TimerTick_t internal RAIL hardware timer that drives + * the RAIL timebase. + * Equivalent to \ref RAIL_TimerTick_t for its granularity and range. */ extern const volatile uint32_t *RAIL_TimerTick; /** * A global pointer to the memory address of the internal RAIL hardware timer - * that captures the latest RX packet reception time. This would not include - * the RX chain delay, so may not be equal to the packet timestamp, passed to - * the application, representing the actual on-air time the packet finished. + * that captures the latest RX packet reception time. + * See \ref RAIL_TimerTick_t for its granularity and range. * - * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. On EFR32XG2X family of - * chips, ticks wrap in about 17 minutes, since it does not use the full - * 32-bit range. - * For more details, check the documentation for \ref RAIL_TimerTick_t. + * @note This would not include the RX chain delay, so may not exactly + * correspond to the \ref RAIL_Time_t packet timestamp available within + * \ref RAIL_RxPacketDetails_t::timeReceived which reflects the actual + * on-air time that the packet finished. */ extern const volatile uint32_t *RAIL_RxPacketTimestamp; @@ -481,13 +317,14 @@ RAIL_Time_t RAIL_TimerTicksToUs(RAIL_TimerTick_t startTick, RAIL_TimerTick_t endTick); /** - * Get \ref RAIL_TimerTick_t tick corresponding to the \ref RAIL_Time_t time. + * Get \ref RAIL_TimerTick_t tick corresponding to a \ref RAIL_Time_t time. * * @param[in] microseconds Time in microseconds. * @return The \ref RAIL_TimerTick_t tick corresponding to the * \ref RAIL_Time_t time. */ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); + #endif//DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group General_EFR32XG2X @@ -496,10 +333,10 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); * Multiprotocol *****************************************************************************/ /** - * @addtogroup Multiprotocol_EFR32XG2X EFR32XG2X + * @addtogroup Multiprotocol_EFR32XG2X EFR32xG2x * @ingroup Multiprotocol * @{ - * @brief EFR32XG2X-specific multiprotocol support defines + * @brief EFR32xG2x-specific multiprotocol support defines. */ /** @@ -520,21 +357,22 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); * Calibration *****************************************************************************/ /** - * @addtogroup Calibration_EFR32XG2X EFR32XG2X + * @addtogroup Calibration_EFR32XG2X EFR32xG2x * @ingroup Calibration * @{ - * @brief EFR32XG2X-specific Calibrations + * @brief EFR32xG2x-specific Calibrations. */ /** * @def RAIL_RF_PATHS_2P4GIG - * @brief Indicates the number of 2.4 GHz RF Paths suppported + * @brief Indicates the number of 2.4 GHz RF Paths suppported. */ #ifndef RAIL_RF_PATHS_2P4GIG #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) #define RAIL_RF_PATHS_2P4GIG 2 #elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_RF_PATHS_2P4GIG 1 #else @@ -544,7 +382,7 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); /** * @def RAIL_RF_PATHS_SUBGIG - * @brief Indicates the number of sub-GHz RF Paths supported + * @brief Indicates the number of Sub-GHz RF Paths supported. */ #ifndef RAIL_RF_PATHS_SUBGHZ #if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 @@ -560,7 +398,7 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); /** * @def RAIL_RF_PATHS - * @brief Indicates the number of RF Paths supported + * @brief Indicates the number of RF Paths supported. */ #define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG) @@ -579,7 +417,7 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); #ifdef DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen #define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0 #endif //DOXYGEN_SHOULD_SKIP_THIS -#endif +#endif //RAIL_RF_PATHS /** * @struct RAIL_ChannelConfigEntryAttr @@ -601,10 +439,10 @@ struct RAIL_ChannelConfigEntryAttr { * Transmit *****************************************************************************/ /** - * @addtogroup PA_EFR32XG2X EFR32XG2X + * @addtogroup PA_EFR32XG2X EFR32xG2x * @ingroup PA * @{ - * @brief Types specific to the EFR32 for dealing with the on-chip PAs. + * @brief Types specific to the EFR32xG2x for dealing with the on-chip PAs. */ #ifndef RAIL_TX_POWER_LEVEL_2P4_HP_MAX @@ -643,10 +481,10 @@ struct RAIL_ChannelConfigEntryAttr { /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4GIG_HP mode. - * EFR32XG24: capable of 20dBm max output power has max powerlevel:180 - * EFR32XG24: capable of 10dBm max output power has max powerlevel:90 - * EFR32XG26: capable of 20dBm max output power has max powerlevel:180 - * EFR32XG26: capable of 10dBm max output power has max powerlevel:90 + * EFR32xG24: capable of 20dBm max output power has max powerlevel:180 + * EFR32xG24: capable of 10dBm max output power has max powerlevel:90 + * EFR32xG26: capable of 20dBm max output power has max powerlevel:180 + * EFR32xG26: capable of 10dBm max output power has max powerlevel:90 */ #if defined (_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10) @@ -669,7 +507,9 @@ struct RAIL_ChannelConfigEntryAttr { * RAIL_TX_POWER_MODE_2P4GIG_LP mode. */ #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) -#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4GIG_HP mode. @@ -701,7 +541,7 @@ struct RAIL_ChannelConfigEntryAttr { * RAIL_TX_POWER_MODE_2P4GIG_HP mode. */ #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) -#else //efr32xg23 +#else //EFR32xG23 /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_2P4GIG_HP mode. @@ -748,7 +588,7 @@ struct RAIL_ChannelConfigEntryAttr { #if RAIL_SUPPORTS_SUBGHZ_BAND /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when using - * a SUBGHZ PA mode. + * a Sub-GHz PA mode. */ #ifndef RAIL_SUBGIG_MAX #if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8 @@ -762,7 +602,7 @@ struct RAIL_ChannelConfigEntryAttr { /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when using - * a SUBGHZ PA mode. + * a Sub-GHz PA mode. */ #define RAIL_SUBGIG_MIN 1U @@ -771,36 +611,43 @@ struct RAIL_ChannelConfigEntryAttr { * RAIL_TX_POWER_MODE_SUBGIG_HP mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX (RAIL_SUBGIG_MAX) + /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG_HP mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN (RAIL_SUBGIG_MIN) + /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG_MP mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX (RAIL_SUBGIG_MAX) + /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG_MP mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN (RAIL_SUBGIG_MIN) + /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG_LP mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX (RAIL_SUBGIG_MAX) + /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG_LP mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN (RAIL_SUBGIG_MIN) + /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. */ #define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX (RAIL_SUBGIG_MAX) + /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. @@ -814,11 +661,13 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_OFDM_PA_MULT 5U #define RAIL_OFDM_PA_MIN 0U #endif + /** * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE mode. */ #define RAIL_TX_POWER_LEVEL_OFDM_PA_MAX (RAIL_OFDM_PA_MAX) + /** * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref * RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE mode. @@ -844,13 +693,14 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN /** - * The number of PA's on this chip. (Including Virtual PAs) + * The number of PA's on this chip (including Virtual PAs). */ #ifndef RAIL_NUM_PA #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) #define RAIL_NUM_PA (2U) #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) #define RAIL_NUM_PA (4U) @@ -882,11 +732,6 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_TX_POWER_MODE_2P4_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HIGHEST) #endif//RAIL_SUPPORTS_2P4GHZ_BAND -/** Convenience macro for any mapping table mode. */ -#define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) \ - (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ - || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) - #if RAIL_SUPPORTS_SUBGHZ_BAND #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE #define RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) @@ -907,16 +752,25 @@ struct RAIL_ChannelConfigEntryAttr { #endif//RAIL_SUPPORTS_OFDM_PA #endif//DOXYGEN_SHOULD_SKIP_THIS +/** Convenience macro for any mapping table mode. */ +#define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) \ + (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ + || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) + +/** Convenience macro to check if the power mode supports raw setting. */ +#define RAIL_POWER_MODE_SUPPORTS_RAW_SETTING(x) \ + (((x) != RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ + && ((x) != RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) /** @} */ // end of group PA_EFR32XG2X /****************************************************************************** * RX Channel Hopping *****************************************************************************/ /** - * @addtogroup Rx_Channel_Hopping_EFR32XG2X EFR32XG2X + * @addtogroup Rx_Channel_Hopping_EFR32XG2X EFR32xG2x * @ingroup Rx_Channel_Hopping * @{ - * @brief EFR32XG2X-specific RX channel hopping. + * @brief EFR32xG2x-specific RX channel hopping. */ #if _SILICON_LABS_32B_SERIES_2_CONFIG == 8 @@ -940,16 +794,18 @@ struct RAIL_ChannelConfigEntryAttr { * Sleep Structures *****************************************************************************/ /** - * @addtogroup Sleep_EFR32XG2X EFR32XG2X + * @addtogroup Sleep_EFR32XG2X EFR32xG2x * @ingroup Sleep * @{ - * @brief EFR32XG2X-specific Sleeping. + * @brief EFR32xG2x-specific Sleeping. */ /// Default PRS channel to use when configuring sleep #define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U) -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) /// Default RTCC channel to use when configuring sleep #define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (1U) #else @@ -963,9 +819,10 @@ struct RAIL_ChannelConfigEntryAttr { * State Transitions *****************************************************************************/ /** - * @addtogroup State_Transitions_EFR32XG2X EFR32XG2X + * @addtogroup State_Transitions_EFR32XG2X EFR32xG2x * @ingroup State_Transitions * @{ + * @brief EFR32xG2x-specific State Transitions. */ /** @@ -982,6 +839,11 @@ struct RAIL_ChannelConfigEntryAttr { */ #define RAIL_MAXIMUM_TRANSITION_US (1000000U) +/** + * Internal Radio State type mapping for EFR32 chips. + */ +typedef RAIL_RadioStateEfr32_t RAIL_RacRadioState_t; + /** @} */ // end of group State_Transitions_EFR32XG2X #ifdef __cplusplus @@ -992,4 +854,4 @@ struct RAIL_ChannelConfigEntryAttr { #endif //__RAIL_CHIP_SPECIFIC_H_ -#endif // SLI_LIBRARY_BUILD +#endif //SLI_LIBRARY_BUILD diff --git a/simplicity_sdk/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h b/simplicity_sdk/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h index 5a50c1b31..7ad70b028 100644 --- a/simplicity_sdk/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h +++ b/simplicity_sdk/platform/radio/rail_lib/chip/efr32/sixg3xx/rail_chip_specific.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file - * @brief This file contains the type definitions for efr32xg2x chip specific + * @brief This file contains the type definitions for SIxx3xx chip-specific * aspects of RAIL. ******************************************************************************* * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -29,6 +29,12 @@ * ******************************************************************************/ +#ifdef SLI_LIBRARY_BUILD + +// This file should not be included when doing SLI_LIBRARY_BUILDs + +#else//!SLI_LIBRARY_BUILD + #ifndef __RAIL_CHIP_SPECIFIC_H_ #if !defined(__RAIL_TYPES_H__) && !defined(DOXYGEN_SHOULD_SKIP_THIS) #warning rail_chip_specific.h should only be included by rail_types.h @@ -46,30 +52,41 @@ extern "C" { #endif +#if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) +// Copied from rail_types.h to satisfy doxygen build. +/// The RAIL library does not use enumerations because the ARM EABI leaves their +/// size ambiguous, which causes problems if the application is built +/// with different flags than the library. Instead, uint8_t typedefs +/// are used in compiled code for all enumerations. For documentation purposes, this is +/// converted to an actual enumeration since it's much easier to read in Doxygen. +#define RAIL_ENUM(name) enum name +/// This macro is a more generic version of the \ref RAIL_ENUM() macro that +/// allows the size of the type to be overridden instead of forcing the use of +/// a uint8_t. See \ref RAIL_ENUM() for more information. +#define RAIL_ENUM_GENERIC(name, type) enum name +#endif //(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) + +/****************************************************************************** + * General Structures + *****************************************************************************/ /** - * @addtogroup General_EFR32XG3 EFR32xG3 - * @{ - * @brief EFR32xG3-specific initialization data types + * @addtogroup General_SIXX3XX SIxx3xx * @ingroup General + * @{ + * @brief Types specific to the SIxx3xx for general configuration. */ -/** - * A placeholder for a chip-specific RAIL handle. Using NULL as a RAIL handle is - * not recommended. As a result, another value that can't be de-referenced is used. - * - * This generic handle can and should be used for RAIL APIs that are called - * prior to RAIL initialization. - */ -#define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL) +/** Synonym of \ref RAIL_EFR32_HANDLE for Series 3 */ +#define RAIL_S3LPW_HANDLE RAIL_EFR32_HANDLE #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * @def RAIL_SIXG301_STATE_BUFFER_BYTES - * @brief The SIXG301 series size needed for + * @brief The SIxG301 series size needed for * \ref RAIL_StateBufferEntry_t::bufferBytes. */ -#define RAIL_SIXG301_STATE_BUFFER_BYTES 576 +#define RAIL_SIXG301_STATE_BUFFER_BYTES 624 #ifndef RAIL_STATE_BUFFER_BYTES /** @@ -78,25 +95,23 @@ extern "C" { * on this platform for this radio. This compile-time size may be slightly * larger than what \ref RAIL_GetStateBufferSize() determines at run-time. */ -#if (_SILICON_LABS_32B_SERIES_3_CONFIG == 1) +#if (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300) #define RAIL_STATE_BUFFER_BYTES RAIL_SIXG301_STATE_BUFFER_BYTES #else #define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen #error "Unsupported platform!" -#endif //_SILICON_LABS_32B_SERIES_3_CONFIG +#endif #endif //#ifndef RAIL_STATE_BUFFER_BYTES -/** - * Redefined to use \ref RAIL_RadioStateSix3x_t instead of \ref RAIL_RadioStateEfr32_t - */ -#ifdef RAIL_RAC_STATE_NONE -#undef RAIL_RAC_STATE_NONE -#define RAIL_RAC_STATE_NONE RAIL_RAC_STATE_SIX3X_NONE -#endif +#endif//DOXYGEN_SHOULD_SKIP_THIS + +#ifndef DOXYGEN_SHOULD_SKIP_THIS /** * @typedef RAIL_TimerTick_t * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. + * A tick is roughly 0.125 microseconds and it has a full 64-bit range + * (i.e, spanning 2^61 microseconds or ~73 millenia). * * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between * two \ref RAIL_TimerTick_t values to microseconds. @@ -105,45 +120,37 @@ typedef uint64_t RAIL_TimerTick_t; /** * @typedef RAIL_GetTimerTick_t - * @brief A pointer to a function to RAIL internal timer tick. + * @brief A function pointer type for reading RAIL internal timer ticks. * - * @param[in] timerChannel \ref RAIL_TimerTickType_t timer tick - * channel to read. - * @return RAIL timer tick, type \ref RAIL_TimerTick_t, corresponding to the - * timer channel. + * @param[in] timerTickType A timer tick type to read. + * @return RAIL timer tick corresponding to the timerTickType. */ -typedef RAIL_TimerTick_t (*RAIL_GetTimerTick_t) (RAIL_TimerTickType_t timerChannel); +typedef RAIL_TimerTick_t (*RAIL_GetTimerTick_t)(RAIL_TimerTickType_t timerTickType); /** - * Function pointer of type \ref RAIL_GetTimerTick_t to get RAIL timer - * tick. - * - * @note This function pointer is only supported for series-3 chips and will be - * NULL otherwise. + * Function pointer of type \ref RAIL_GetTimerTick_t to read RAIL internal + * timer ticks. */ extern RAIL_GetTimerTick_t RAIL_GetTimerTick; /** - * A global pointer to the memory address of the internal RAIL hardware timer - * that drives the RAIL timebase. - * - * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. The ticks wrap after about - * 9 minutes on series 3 chips. - * For more details, check the documentation for \ref RAIL_TimerTick_t. + * A global pointer to the memory address of the least significant 32 bits + * of the \ref RAIL_TimerTick_t internal RAIL hardware timer that drives + * the RAIL timebase. + * It's 0.125 microsecond tick range is 2^29 microseconds or ~9 minutes. */ extern const volatile uint32_t *RAIL_TimerTick; /** - * A global pointer to the memory address of the internal RAIL hardware timer - * that captures the latest RX packet reception time. This would not include - * the RX chain delay, so may not be equal to the packet timestamp, passed to - * the application, representing the actual on-air time the packet finished. + * A global pointer to the memory address of the least significant 32 bits + * of the \ref RAIL_TimerTick_t internal RAIL hardware timer that captures + * the latest RX packet reception time. + * It's 0.125 microsecond tick range is 2^29 microseconds or ~9 minutes. * - * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. The ticks wrap after about - * 9 minutes on series 3 chips. - * For more details, check the documentation for \ref RAIL_TimerTick_t. + * @note This would not include the RX chain delay, so may not exactly + * correspond to the \ref RAIL_Time_t packet timestamp available within + * \ref RAIL_RxPacketDetails_t::timeReceived which reflects the actual + * on-air time that the packet finished. */ extern const volatile uint32_t *RAIL_RxPacketTimestamp; @@ -158,25 +165,26 @@ RAIL_Time_t RAIL_TimerTicksToUs(RAIL_TimerTick_t startTick, RAIL_TimerTick_t endTick); /** - * Get \ref RAIL_TimerTick_t tick corresponding to the \ref RAIL_Time_t time. + * Get \ref RAIL_TimerTick_t tick corresponding to a \ref RAIL_Time_t time. * * @param[in] microseconds Time in microseconds. * @return The \ref RAIL_TimerTick_t tick corresponding to the * \ref RAIL_Time_t time. */ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); + #endif//DOXYGEN_SHOULD_SKIP_THIS -/** @} */ // end of group General_EFR32XG2 +/** @} */ // end of group General_SIXX3XX -// ----------------------------------------------------------------------------- -// Multiprotocol -// ----------------------------------------------------------------------------- +/****************************************************************************** + * Multiprotocol + *****************************************************************************/ /** - * @addtogroup Multiprotocol_EFR32 EFR32 - * @{ - * @brief EFR32-specific multiprotocol support defines + * @addtogroup Multiprotocol_SIXX3XX SIxx3xx * @ingroup Multiprotocol + * @{ + * @brief SIxx3xx-specific multiprotocol support defines. */ /** @@ -185,23 +193,23 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); */ #define TRANSITION_TIME_US 510 -/** @} */ // end of group Multiprotocol_EFR32 +/** @} */ // end of group Multiprotocol_SIXX3XX -// ----------------------------------------------------------------------------- -// Calibration -// ----------------------------------------------------------------------------- +/****************************************************************************** + * Calibration + *****************************************************************************/ /** - * @addtogroup Calibration_EFR32XG3X EFR32XG3X - * @{ - * @brief EFR32XG3X-specific Calibrations + * @addtogroup Calibration_SIXX3XX SIxx3xx * @ingroup Calibration + * @{ + * @brief SIxx3xx-specific Calibrations. */ /** * @def RAIL_RF_PATHS_2P4GIG - * @brief Indicates the number of 2.4 GHz RF Paths suppported + * @brief Indicates the number of 2.4 GHz RF Paths suppported. */ -#if _SILICON_LABS_32B_SERIES_3_CONFIG == 1 +#if (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300) #define RAIL_RF_PATHS_2P4GIG 1 #else #define RAIL_RF_PATHS_2P4GIG 0 @@ -209,16 +217,20 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); /** * @def RAIL_RF_PATHS_SUBGIG - * @brief Indicates the number of sub-GHz RF Paths supported + * @brief Indicates the number of Sub-GHz RF Paths supported. */ #define RAIL_RF_PATHS_SUBGIG 0 /** * @def RAIL_RF_PATHS - * @brief Indicates the number of RF Paths supported + * @brief Indicates the number of RF Paths supported. */ #define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG) +#if (RAIL_RF_PATHS > RAIL_MAX_RF_PATHS) +#error "Update rail_types.h RAIL_MAX_RF_PATHS" +#endif + /** * @def RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS * @brief Indicates this version of RAIL supports IR calibration on multiple RF paths @@ -229,8 +241,8 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); #else #ifdef DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen #define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0 -#endif//DOXYGEN_SHOULD_SKIP_THIS -#endif // RAIL_RF_PATHS +#endif //DOXYGEN_SHOULD_SKIP_THIS +#endif //RAIL_RF_PATHS /** * @struct RAIL_ChannelConfigEntryAttr @@ -239,52 +251,52 @@ RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); */ struct RAIL_ChannelConfigEntryAttr { /** IR calibration attributes specific to each channel configuration entry. */ -#if RAIL_SUPPORTS_OFDM_PA + #if RAIL_SUPPORTS_OFDM_PA RAIL_IrCalValues_t calValues; #else//!RAIL_SUPPORTS_OFDM_PA RAIL_RxIrCalValues_t calValues; #endif//RAIL_SUPPORTS_OFDM_PA }; -/** @} */ // end of group Calibration_EFR32 +/** @} */ // end of group Calibration_SIXX3XX -// ----------------------------------------------------------------------------- -// Transmit -// ----------------------------------------------------------------------------- +/****************************************************************************** + * Transmit + *****************************************************************************/ /** - * @addtogroup PA_EFR32XG3X EFR32XG3X - * @{ + * @addtogroup PA_SIXX3XX SIxx3xx * @ingroup PA - * @brief Types specific to the EFR32 for dealing with the on-chip PAs. + * @{ + * @brief Types specific to the SIxx3xx for dealing with the on-chip PAs. */ -#if _SILICON_LABS_32B_SERIES_3_CONFIG == 1 +#if (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300) /** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t for both \ref - * RAIL_TX_POWER_MODE_2P4GIG_HP and \ref RAIL_TX_POWER_MODE_2P4GIG_LP modes. + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4GIG_HP or \ref RAIL_TX_POWER_MODE_2P4GIG_LP modes. */ #define RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MAX (95U) /** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t for both \ref - * RAIL_TX_POWER_MODE_2P4GIG_HP and \ref RAIL_TX_POWER_MODE_2P4GIG_LP modes. + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4GIG_HP or \ref RAIL_TX_POWER_MODE_2P4GIG_LP modes. */ #define RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MIN (0U) -/** - * Legacy defines for High Power (HP) and Low Power (LP) modes. - * These defines are used for setting the minimum and maximum transmit power levels. - */ +/** Legacy define for High Power (HP) and Low Power (LP) modes. */ #define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MIN) +/** Legacy define for High Power (HP) and Low Power (LP) modes. */ #define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MAX) +/** Legacy define for High Power (HP) and Low Power (LP) modes. */ #define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MIN) +/** Legacy define for High Power (HP) and Low Power (LP) modes. */ #define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (RAIL_TX_POWER_LEVEL_2P4GIG_HP_LP_MAX) #else #error "RAIL_TX_POWER_LEVEL not defined for this device" -#endif //_SILICON_LABS_32B_SERIES_3_CONFIG +#endif /** - * The number of PA's on this chip. + * The number of PA's on this chip (including Virtual PAs). */ -#if (_SILICON_LABS_32B_SERIES_3_CONFIG == 1) +#if (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300) #define RAIL_NUM_PA (2U) #else #error "RAIL_NUM_PA undefined for platform" @@ -302,256 +314,406 @@ struct RAIL_ChannelConfigEntryAttr { #define RAIL_TX_POWER_MODE_2P4GIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HIGHEST) #define RAIL_TX_POWER_MODE_2P4_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HIGHEST) #endif//RAIL_SUPPORTS_2P4GHZ_BAND +#endif//DOXYGEN_SHOULD_SKIP_THIS /** Convenience macro for any mapping table mode. */ #define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) \ (((x) == RAIL_TX_POWER_MODE_2P4GIG_HP) \ || ((x) == RAIL_TX_POWER_MODE_2P4GIG_LP)) -#endif//DOXYGEN_SHOULD_SKIP_THIS -/** @} */ // end of group PA_EFR32 +/** Convenience macro to check if the power mode supports raw setting. */ +#define RAIL_POWER_MODE_SUPPORTS_RAW_SETTING(x) \ + (((x) == RAIL_TX_POWER_MODE_2P4GIG_HP) || ((x) == RAIL_TX_POWER_MODE_2P4GIG_LP)) + +/** @} */ // end of group PA_SIXX3XX /****************************************************************************** - * User Sequencer Structures + * RX Channel Hopping *****************************************************************************/ /** - * @addtogroup User Sequencer + * @addtogroup Rx_Channel_Hopping_SIXX3XX SIxx3xx + * @ingroup Rx_Channel_Hopping * @{ + * @brief SIxx3xx-specific RX channel hopping. */ -/** - * TODO: Document and cleanup. - */ -typedef struct RAIL_UserCommonGlobal { - void *pLocSeqVirtualReg; - void *pLocSeqTiming; - void *pLocUserSeqConfig; - void *pLocRtccsyncConfig; - void *pLocStateVarConfig; - void *pLocGenericPhyConfig; - void *pLocpSeqTimestamp; -} RAIL_UserCommonGlobal_t; +/// The static amount of memory needed per channel for channel hopping, measured +/// in 32 bit words, regardless of the size of radio configuration structures. +#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (54U) -/** - * TODO: Document and cleanup. - */ -typedef struct UserSeqShMem { - /** - * pointer to the start of M33 and sequencer shared memory. - * TBD: This part of memory should be moved to user memory intead of in generic_seq_common.h - */ - void *pStart; - /** - * size of shared memory in bytes. - * TBD: This part of memory should be moved to user memory intead of in generic_seq_common.h - */ - uint32_t szBytes; -} UserSeqShMem_t; +#if (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ + > RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE) +#error "Update rail_types.h RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE" +#endif +/** @} */ // end of group Rx_Channel_Hopping_SIXX3XX + +/****************************************************************************** + * Sleep Structures + *****************************************************************************/ /** - * @struct RAIL_SeqUserAppInfo_t - * @brief RAIL sequencer user application structure - * - * This structure describe the user application that is loaded on the sequencer. + * @addtogroup Sleep_SIXX3XX SIxx3xx + * @ingroup Sleep + * @{ + * @brief SIxx3xx-specific Sleeping. */ -// TBD: Is this the right place for this strucutre? This should probably stays internal????? -typedef void (*RAIL_SEQ_UserStartMain_t)(void); -typedef struct { - uint32_t version; // Version of the structure? do we need this? how would this work? - uint8_t *pProgramStartMem;// pointer to the start of user executable in memory - uint8_t *pProgramStartLoc;// pointer to the start of user executable storage - uint32_t programSzB; // size of user executable in bytes - RAIL_SEQ_UserStartMain_t programInitStart;// main user function entry - uint8_t *pDataStartMem; // pointer to the start of user initialized data in memory - uint8_t *pDataStartLoc; // pointer to the start of user initialized data storage - uint32_t dataSzB; // size of user initialized data in bytes - uint8_t *pScratchStartMem;// pointer to the start of user un-initialized data in memory - uint32_t scratchSzB; // size of user un-initialized data in bytes -} RAIL_SeqUserAppInfo_t; -/** @} */ // end of group User Sequencer +/// Default PRS channel to use when configuring sleep +#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U) + +/// Default RTCC channel to use when configuring sleep +#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U) + +/** @} */ // end of group Sleep_SIXX3XX /****************************************************************************** * State Transitions *****************************************************************************/ /** - * @addtogroup State_Transitions + * @addtogroup State_Transitions_SIXX3XX SIxx3xx + * @ingroup State_Transitions * @{ + * @brief SIxx3xx-specific State Transitions. + */ + +/** + * @def RAIL_MINIMUM_TRANSITION_US + * @brief The minimum value for a consistent RAIL transition + * @note Transitions may need to be slower than this when using longer + * \ref RAIL_TxPowerConfig_t::rampTime values */ +#define RAIL_MINIMUM_TRANSITION_US (100U) + +/** + * @def RAIL_MAXIMUM_TRANSITION_US + * @brief The maximum value for a consistent RAIL transition + */ +#define RAIL_MAXIMUM_TRANSITION_US (1000000U) /** * @enum RAIL_RadioStateSix3x_t - * @brief Detailed Series-3 Radio state machine statuses. + * @brief Detailed Series 3 Radio state machine states. */ RAIL_ENUM(RAIL_RadioStateSix3x_t) { - RAIL_RAC_STATE_SIX3X_OFF, /**< Radio is off. */ - RAIL_RAC_STATE_SIX3X_RXWARM, /**< Radio is enabling the receiver. */ - RAIL_RAC_STATE_SIX3X_RXSEARCH, /**< Radio is listening for incoming frames. */ - RAIL_RAC_STATE_SIX3X_RXFRAME, /**< Radio is receiving a frame. */ - RAIL_RAC_STATE_SIX3X_RXWRAPUP, /**< Radio is going to RX Wrapup mode after - receiving a frame. */ - RAIL_RAC_STATE_SIX3X_TXWARM, /**< Radio is enabling transmitter. */ - RAIL_RAC_STATE_SIX3X_TX, /**< Radio is transmitting data. */ - RAIL_RAC_STATE_SIX3X_TXWRAPUP, /**< Radio is going to TX Wrapup mode after - transmitting a frame. */ - RAIL_RAC_STATE_SIX3X_SHUTDOWN, /**< Radio is powering down receiver and going to - OFF state. */ - RAIL_RAC_STATE_SIX3X_POR, /**< Radio power-on-reset state (EFR32xG22 and later) */ - RAIL_RAC_STATE_SIX3X_NONE /**< Invalid Radio state, must be the last entry. */ + /** Radio is off. */ + RAIL_RAC_STATE_SIX3X_OFF = 0, + /** Radio is enabling the receiver. */ + RAIL_RAC_STATE_SIX3X_RXWARM = 1, + /** Radio is listening for incoming frames. */ + RAIL_RAC_STATE_SIX3X_RXSEARCH = 2, + /** Radio is receiving a frame. */ + RAIL_RAC_STATE_SIX3X_RXFRAME = 3, + /** Radio is wrapping up after receiving a frame. */ + RAIL_RAC_STATE_SIX3X_RXWRAPUP = 4, + /** Radio is enabling transmitter. */ + RAIL_RAC_STATE_SIX3X_TXWARM = 5, + /** Radio is transmitting data. */ + RAIL_RAC_STATE_SIX3X_TX = 6, + /** Radio is wrapping up after transmitting a frame. */ + RAIL_RAC_STATE_SIX3X_TXWRAPUP = 7, + /** Radio is powering down and going to OFF state. */ + RAIL_RAC_STATE_SIX3X_SHUTDOWN = 8, + /** Radio power-on-reset state. */ + RAIL_RAC_STATE_SIX3X_POR = 9, + /** Invalid Radio state, must be the last entry. */ + RAIL_RAC_STATE_SIX3X_NONE }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RAC_STATE_SIX3X_OFF ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_OFF) -#define RAIL_RAC_STATE_SIX3X_RXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_RXWARM) -#define RAIL_RAC_STATE_SIX3X_RXSEARCH ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_RXSEARCH) -#define RAIL_RAC_STATE_SIX3X_RXFRAME ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_RXFRAME) -#define RAIL_RAC_STATE_SIX3X_RXWRAPUP ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_RXWRAPUP) -#define RAIL_RAC_STATE_SIX3X_TXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_TXWARM) -#define RAIL_RAC_STATE_SIX3X_TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_TX) -#define RAIL_RAC_STATE_SIX3X_TXWRAPUP ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_TXWRAPUP) -#define RAIL_RAC_STATE_SIX3X_SHUTDOWN ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_SHUTDOWN) -#define RAIL_RAC_STATE_SIX3X_POR ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_POR) -#define RAIL_RAC_STATE_SIX3X_NONE ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SIX3X_NONE) +#define RAIL_RAC_STATE_SIX3X_OFF ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_OFF) +#define RAIL_RAC_STATE_SIX3X_RXWARM ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_RXWARM) +#define RAIL_RAC_STATE_SIX3X_RXSEARCH ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_RXSEARCH) +#define RAIL_RAC_STATE_SIX3X_RXFRAME ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_RXFRAME) +#define RAIL_RAC_STATE_SIX3X_RXWRAPUP ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_RXWRAPUP) +#define RAIL_RAC_STATE_SIX3X_TXWARM ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_TXWARM) +#define RAIL_RAC_STATE_SIX3X_TX ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_TX) +#define RAIL_RAC_STATE_SIX3X_TXWRAPUP ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_TXWRAPUP) +#define RAIL_RAC_STATE_SIX3X_SHUTDOWN ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_SHUTDOWN) +#define RAIL_RAC_STATE_SIX3X_POR ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_POR) +#define RAIL_RAC_STATE_SIX3X_NONE ((RAIL_RadioStateSix3x_t) RAIL_RAC_STATE_SIX3X_NONE) +/** + * Redefined to use \ref RAIL_RadioStateSix3x_t instead of \ref RAIL_RadioStateEfr32_t. + */ +#ifdef RAIL_RAC_STATE_NONE +#undef RAIL_RAC_STATE_NONE +#define RAIL_RAC_STATE_NONE RAIL_RAC_STATE_SIX3X_NONE +#endif #endif//DOXYGEN_SHOULD_SKIP_THIS /** - * Redefined here for use in common source code \ref RAIL_RadioStateSix3x_t + * Internal Radio State type mapping for SIxx3xx chips. */ typedef RAIL_RadioStateSix3x_t RAIL_RacRadioState_t; -/** @} */ // end of group State_Transitions +/** @} */ // end of group State_Transitions_SIXX3XX + +#ifndef DOXYGEN_SHOULD_SKIP_THIS /****************************************************************************** - * RX Channel Hopping + * Sequencer User Structures *****************************************************************************/ /** - * @addtogroup Rx_Channel_Hopping RX Channel Hopping + * @addtogroup Sequencer_User_SIXX3XX Sequencer User + * @ingroup RAIL_API * @{ + * @brief Types specific to the SIxx3xx for dealing with the Sequencer User. */ -/// The static amount of memory needed per channel for channel hopping, measured -/// in 32 bit words, regardless of the size of radio configuration structures. -#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (54U) - -/** @} */ // end of group Rx_Channel_Hopping - /** - * @addtogroup Sleep - * @{ + * TODO: Document and cleanup. */ - -/// Default PRS channel to use when configuring sleep -#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U) - -/// Default RTCC channel to use when configuring sleep -#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U) - -/** @} */ // end of group Sleep +typedef struct RAIL_UserCommonGlobal { + void *pLocSeqVirtualReg; + void *pLocSeqTiming; + void *pLocUserSeqConfig; + void *pLocRtccsyncConfig; + void *pLocStateVarConfig; + void *pLocGenericPhyConfig; + void *pLocpSeqTimestamp; + void *pLocpSeqMisc; + void *pLocpNewFeatureConfig; +} RAIL_UserCommonGlobal_t; /** - * @addtogroup Data_Management_EFR32XG3X EFR32XG3X - * @{ - * @ingroup Data_Management + * TODO: Document and cleanup. */ - -/// Fixed-width type indicating the needed alignment for RX and TX FIFOs. Note -/// that docs.silabs.com will incorrectly indicate that this is always a -/// uint8_t, but it does vary across RAIL platforms. -#if _SILICON_LABS_32B_SERIES_3_CONFIG == 1 -#define RAIL_FIFO_ALIGNMENT_TYPE uint32_t -#endif - -/// Alignment that is needed for the RX and TX FIFOs. -#define RAIL_FIFO_ALIGNMENT (sizeof(RAIL_FIFO_ALIGNMENT_TYPE)) - -/** @} */ // end of group Data_Management_EFR32 +typedef struct UserSeqShMem { + /** + * pointer to the start of M33 and sequencer shared memory. + * TBD: This part of memory should be moved to user memory instead of in generic_seq_common.h + */ + void *pStart; + /** + * size of shared memory in bytes. + * TBD: This part of memory should be moved to user memory instead of in generic_seq_common.h + */ + uint32_t szBytes; +} UserSeqShMem_t; /** - * @addtogroup State_Transitions_EFR32XG2X - * @{ - * @ingroup State_Transitions + * TODO: Document and cleanup. */ +typedef void (*RAIL_SEQ_UserStartMain_t)(void); /** - * @def RAIL_MINIMUM_TRANSITION_US - * @brief The minimum value for a consistent RAIL transition - * @note Transitions may need to be slower than this when using longer - * \ref RAIL_TxPowerConfig_t::rampTime values + * @struct RAIL_SeqUserAppInfo_t + * @brief RAIL sequencer user application structure. + * + * This structure describes the user application that is loaded on the sequencer. */ -#define RAIL_MINIMUM_TRANSITION_US (100U) +// TBD: Is this the right place for this structure? This should probably stays internal????? +typedef struct { + /// Version of the structure? do we need this? how would this work? + uint32_t version; + /// Pointer to the start of user executable in memory. + uint8_t *pProgramStartMem; + /// Pointer to the start of user executable storage. + uint8_t *pProgramStartLoc; + /// Size of user executable in bytes. + uint32_t programSzB; + /// Main user function entry. + RAIL_SEQ_UserStartMain_t programInitStart; + /// Pointer to the start of user initialized data in memory. + uint8_t *pDataStartMem; + /// Pointer to the start of user initialized data storage. + uint8_t *pDataStartLoc; + /// Size of user initialized data in bytes. + uint32_t dataSzB; + /// Pointer to the start of user un-initialized data in memory. + uint8_t *pScratchStartMem; + /// Size of user un-initialized data in bytes. + uint32_t scratchSzB; +} RAIL_SeqUserAppInfo_t; /** - * @def RAIL_MAXIMUM_TRANSITION_US - * @brief The maximum value for a consistent RAIL transition + * @typedef RAIL_UserCpReqCb_t + * @brief Callback function type used to indicate status of user copy request. + * + * @param[in] pCpReq A non-NULL pointer to the user copy request. + * @param[in] reqStatus The status of the request. */ -#define RAIL_MAXIMUM_TRANSITION_US (1000000U) +typedef void(*RAIL_UserCpReqCb_t)(const void *pCpReq, + RAIL_Status_t reqStatus); -/** @} */ // end of group State_Transitions_EFR32 +//FIXME: these are not RAIL_Status_t values, and need doxygen +#define RAIL_USER_CP_REQ_STATUS_FLAG_STARTED 1U +#define RAIL_USER_CP_REQ_STATUS_FLAG_COMPLETED 2U +#define RAIL_USER_CP_REQ_STATUS_FLAG_REQ_HOST 4U +#define RAIL_USER_CP_REQ_STATUS_FLAG_INVALID_PARAMETER 8U + +/** + * @struct RAIL_UserCpReq_t + * @brief Memory copy request configuration structure. + * + * This structure describes the user request to copy contents from one memory area to another. + */ +typedef struct RAIL_UserCpReq { + // Pointer to the next request; NULL if none. + struct RAIL_UserCpReq *pNext; + // Non-NULL pointer to the location to copy from. + const uint8_t *pSrc; + // Non-NULL pointer to the location to copy to. + uint8_t *pDst; + // The number of bytes to copy. + uint16_t xferSzBytes; + // Status of the request. + volatile uint8_t statusFlag; + // Reserved. + volatile uint8_t reserved; + // A pointer to the callback called on completion or error. May be NULL. + RAIL_UserCpReqCb_t pCpReqCB; +} RAIL_UserCpReq_t; /** * Load sequencer user application to memory. * * @param[in] railHandle A RAIL instance handle. - * @param[in] pSeqUserApp pointer to the structure describing the sequencer - * user application metadata. + * @param[in] pSeqUserApp A pointer to the structure describing the user + * sequencer application metadata. * @return Status code indicating success of the function call. * * Attempts to load sequencer user application to the sequencer memory and * execute its initialization function. */ RAIL_Status_t RAIL_LoadUserSeqApp(RAIL_Handle_t railHandle, - RAIL_SeqUserAppInfo_t *pSeqUserApp); + const RAIL_SeqUserAppInfo_t *pSeqUserApp); /** * Send a shutdown message to the sequencer user application. * * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. - * */ RAIL_Status_t RAIL_ShutdownUserSeqApp(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports User Sequencer. + * Indicate whether this chip supports Sequencer User. * * @param[in] railHandle A RAIL instance handle. - * @return true if User Sequencer is supported; false otherwise. + * @return true if Sequencer User is supported; false otherwise. */ bool RAIL_SupportsUserSequencer(RAIL_Handle_t railHandle); /** - * Prints the common global variables. - * - * This function sets the pointers of the common global variables to their corresponding values. + * Get the sequencer user common global variables. * - * @param[in] railHandle A handle of the RAIL instance. - * @param[in] pCommonGlobal A pointer to the common global variables. - * @return RAIL_Status_t Returns RAIL_STATUS_NO_ERROR on success or an error code on failure. + * @param[in] railHandle A RAIL instance handle. + * @param[out] pCommonGlobal A non-NULL pointer to store the common global variables. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_USER_printCommonGlobal(RAIL_Handle_t railHandle, RAIL_UserCommonGlobal_t *pCommonGlobal); /** - * TODO: Document and cleanup. + * Get sequencer user mailbox message. * * @param[in] railHandle A RAIL instance handle. - * @param[in] pMsg - * @return RAIL_Status_t Returns RAIL_STATUS_NO_ERROR on success or an error code on failure. + * @param[out] pMsg A non-NULL pointer to the message filled in by the call. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_USER_GetMboxMsg(RAIL_Handle_t railHandle, uint32_t *pMsg); /** - * TODO: Document and cleanup. + * Send user mailbox message to the sequencer. * * @param[in] railHandle A RAIL instance handle. - * @param[in] msg - * @return RAIL_Status_t Returns RAIL_STATUS_NO_ERROR on success or an error code on failure. + * @param[in] msg A message to send. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_USER_SendMbox(RAIL_Handle_t railHandle, uint32_t msg); +/** + * Initialize internal RAIL state used to run a user application on + * the sequencer. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_USER_startSeqCtrl(RAIL_Handle_t railHandle); + +/** + * Initialize a semaphore. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] pSemaphore A non-NULL pointer to a 32-bit aligned + * semaphore location updated to become an unacquired semaphore. + * @return Status code indicating success of the function call. + * + * @note This must be called from the hsot for each semaphore's memory location. + */ +RAIL_Status_t RAIL_USER_InitSemaphore(RAIL_Handle_t railHandle, + uint32_t *pSemaphore); + +/** + * Acquire a semaphore lock. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] pSemaphore A non-NULL pointer to the semaphore location + * which will be updated if the lock was acquired. + * @return Status code indicating success of the function call: + * \ref RAIL_STATUS_NO_ERROR if lock was acquired; + * \ref RAIL_STATUS_INVALID_PARAMETER if the lock is corrupted (the lock need to be initialized with \ref RAIL_USER_InitSemaphore()); + * \ref RAIL_STATUS_INVALID_CALL if the lock has been acquired by another processor; + * \ref RAIL_STATUS_INVALID_STATE if the lock has been acquired before by the current processor; + * \ref RAIL_STATUS_SUSPENDED if the lock has been changed recently, user can try to acuire it again + * + * This function attempts to acquire (lock) a semaphore that was previously + * initialized by \ref RAIL_USER_InitSemaphore(). + */ +RAIL_Status_t RAIL_USER_TryLockSemaphore(RAIL_Handle_t railHandle, + uint32_t *pSemaphore); + +/** + * Release a semaphore. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] pSemaphore A non-NULL pointer to the semaphore location + * which will be updated if the semaphore was released. + * @return Status code indicating success of the function call. + * + * This function releases a semaphore that was previously initialized by + * \ref RAIL_USER_InitSemaphore() and acquired by \ref RAIL_USER_TryLockSemaphore(). + */ +RAIL_Status_t RAIL_USER_ReleaseSemaphore(RAIL_Handle_t railHandle, + uint32_t *pSemaphore); + +/** + * Initilize which DMA to use to copy user data. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] dmaChannel The DMA channel to use. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_USER_InitCp(RAIL_Handle_t railHandle, + uint32_t dmaChannel); + +/** + * Start a request to copy user data. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] pCpReqHead A non-NULL pointer to the start of a chain of user copy request configurations. + * @param[in,out] pCpReqTail A non-NULL pointer to the last configuration in the chain. + * @return Status code indicating success of the function call. + * + * This function will initiate copy operations for each element in the linked + * list chain between pCpReqHead and pCpReqTail, inclusive. The \ref + * RAIL_UserCpReq_t::statusFlag of each element in the chain will be + * updated as the operation progresses to completion or failure. + * + * @note Before using this function, \ref RAIL_USER_InitCp() must be + * called once from the host. + */ +RAIL_Status_t RAIL_USER_StartCpReq(RAIL_Handle_t railHandle, + RAIL_UserCpReq_t *pCpReqHead, + RAIL_UserCpReq_t *pCpReqTail); + +/** @} */ // end of group Sequencer_User_SIXX3XX + +#endif//DOXYGEN_SHOULD_SKIP_THIS + #ifdef __cplusplus } #endif @@ -559,3 +721,5 @@ RAIL_Status_t RAIL_USER_SendMbox(RAIL_Handle_t railHandle, #endif //__RAIL_TYPES_H__ #endif //__RAIL_CHIP_SPECIFIC_H_ + +#endif //SLI_LIBRARY_BUILD diff --git a/simplicity_sdk/platform/radio/rail_lib/common/rail.h b/simplicity_sdk/platform/radio/rail_lib/common/rail.h index c08b12061..4cb415c43 100644 --- a/simplicity_sdk/platform/radio/rail_lib/common/rail.h +++ b/simplicity_sdk/platform/radio/rail_lib/common/rail.h @@ -45,7 +45,7 @@ extern "C" { /** * @addtogroup RAIL_API RAIL API * @brief This is the primary API layer for the Radio Abstraction Interface - * Layer (RAIL) + * Layer (RAIL). * @{ */ @@ -165,15 +165,27 @@ RAIL_Status_t RAIL_AddStateBuffer4(RAIL_Handle_t genericRailHandle); * Allocate a DMA channel for RAIL to work with. * * @param[in] channel The DMA channel to use when copying memory. If a value of - * RAIL_DMA_INVALID is passed, RAIL will stop using any DMA channel. + * \ref RAIL_DMA_INVALID is passed, RAIL will stop using any DMA channel. * @return Status code indicating success of the function call. * * To use this API, the application must initialize the DMA engine * on the chip and allocate a DMA channel. This channel will be used * periodically to copy memory more efficiently. Call this function - * before RAIL_Init to have the most benefit. If the application needs + * before \ref RAIL_Init() to have the most benefit. If the application needs * to take back control of the DMA channel that RAIL is using, this API may be - * called with a channel of RAIL_DMA_INVALID to tell RAIL to stop using DMA. + * called with a channel of \ref RAIL_DMA_INVALID to tell RAIL to stop using DMA. + * + * @warning To allocate and use a DMA channel for RAIL to work with when + * TrustZone is enabled and LDMA is configured as secure peripheral, the + * secure application must initialize the DMA engine and call this API. The + * non-secure application must provide a non-NULL + * \ref RAIL_TZ_Config_t::radioPerformM2mLdmaCallback to + * \ref RAIL_TZ_InitNonSecure(). + * To take back control of the DMA channel when TrustZone is enabled and LDMA + * is configured as secure peripheral, the secure application must call this + * API with a channel of \ref RAIL_DMA_INVALID. The non-secure application + * must provide a NULL \ref RAIL_TZ_Config_t::radioPerformM2mLdmaCallback to + * \ref RAIL_TZ_InitNonSecure(). */ RAIL_Status_t RAIL_UseDma(uint8_t channel); @@ -187,7 +199,7 @@ RAIL_Status_t RAIL_UseDma(uint8_t channel); * @return Status code indicating success of the function call. * * This function must only be called from within the RAIL callback context of - * \ref RAILCb_RadioSequencerImageLoad. Otherwise, the function returns \ref + * \ref RAILCb_RadioSequencerImageLoad(). Otherwise, the function returns \ref * RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_LoadSequencerImage1(RAIL_Handle_t genericRailHandle); @@ -200,7 +212,7 @@ RAIL_Status_t RAIL_LoadSequencerImage1(RAIL_Handle_t genericRailHandle); * @return Status code indicating success of the function call. * * This function must only be called from within the RAIL callback context of - * \ref RAILCb_RadioSequencerImageLoad. Otherwise, the function returns \ref + * \ref RAILCb_RadioSequencerImageLoad(). Otherwise, the function returns \ref * RAIL_STATUS_INVALID_STATE. On platforms where \ref RAIL_SEQ_IMAGE_COUNT < 2, * the function returns with \ref RAIL_STATUS_INVALID_CALL. */ @@ -213,32 +225,19 @@ RAIL_Status_t RAIL_LoadSequencerImage2(RAIL_Handle_t genericRailHandle); * @return Status code indicating success of the function call. * * This callback is used by RAIL to load a radio sequencer image during \ref - * RAIL_Init via an API such as \ref RAIL_LoadSequencerImage1. If this + * RAIL_Init() via an API such as \ref RAIL_LoadSequencerImage1(). If this * function is not implemented, a default image will be loaded. On some - * platforms, (in particular EFR32XG24), not implementing this function may + * platforms, (in particular EFR32xG24), not implementing this function may * result in a larger overall code size due to unused sequencer images not * being dead stripped. * * @note If this function is implemented without a call to an image loading API - * such as \ref RAIL_LoadSequencerImage1, an assert will occur during + * such as \ref RAIL_LoadSequencerImage1(), an assert will occur during * RAIL initialization. Similarly, if an image is loaded that is * unsupported by the platform, an assert will occur. */ RAIL_Status_t RAILCb_RadioSequencerImageLoad(void); -/** - * Load the FSK, OFDM and OQPSK image into the software modem (SFM) sequencer - * during RAIL initialization. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * - * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref - * RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_LoadSfmSunFskOfdmOqpsk(RAIL_Handle_t genericRailHandle); - /** * Load the OFDM and OQPSK image into the software modem (SFM) sequencer during * RAIL initialization. @@ -247,7 +246,7 @@ RAIL_Status_t RAIL_LoadSfmSunFskOfdmOqpsk(RAIL_Handle_t genericRailHandle); * @return Status code indicating success of the function call. * * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref + * \ref RAILCb_LoadSfmSequencer(). Otherwise, the function returns \ref * RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_LoadSfmSunOfdmOqpsk(RAIL_Handle_t genericRailHandle); @@ -260,7 +259,7 @@ RAIL_Status_t RAIL_LoadSfmSunOfdmOqpsk(RAIL_Handle_t genericRailHandle); * @return Status code indicating success of the function call. * * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref + * \ref RAILCb_LoadSfmSequencer(). Otherwise, the function returns \ref * RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_LoadSfmSunOfdm(RAIL_Handle_t genericRailHandle); @@ -273,7 +272,7 @@ RAIL_Status_t RAIL_LoadSfmSunOfdm(RAIL_Handle_t genericRailHandle); * @return Status code indicating success of the function call. * * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref + * \ref RAILCb_LoadSfmSequencer(). Otherwise, the function returns \ref * RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_LoadSfmEmpty(RAIL_Handle_t genericRailHandle); @@ -284,28 +283,38 @@ RAIL_Status_t RAIL_LoadSfmEmpty(RAIL_Handle_t genericRailHandle); * * @return Status code indicating success of the function call. * - * This callback is used by RAIL to load a software modem sequencer image during \ref - * RAIL_Init via an API such as \ref RAIL_LoadSfmSunFskOfdmOqpsk. If this - * function is not implemented, a default image including FSK, OFDM andd OQPSK - * modulations will be loaded. + * This callback is used by RAIL to load a software modem sequencer image + * during \ref RAIL_Init() via an API such as \ref RFHAL_LoadSfmSunOfdmOqpsk(). + * If this function is not implemented, a default image including OFDM and + * OQPSK modulations will be loaded. * * @note If this function is implemented without a call to an image loading API - * such as \ref RAIL_LoadSfmSunFskOfdmOqpsk, an assert will occur during - * RAIL initialization. Similiarly, if an image is loaded that is - * unsupported by the platform, an assert will occur. + * such as \ref RFHAL_LoadSfmSunOfdmOqpsk(), an assert will occur during RAIL + * initialization. Similarly, if an image is loaded that is unsupported by + * the platform, an assert will occur. */ RAIL_Status_t RAILCb_LoadSfmSequencer(void); #endif //DOXYGEN_SHOULD_SKIP_THIS +/** + * Reads out device specific data that may be needed by RAIL + * and populates appropriate data structures in the library. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * + * @note This function must be called before calling \ref RAIL_Init() + * on any platforms that require this data + * and should not be called inside a critical section. + * This function does nothing on EFR32 Series 2 devices. + */ +RAIL_Status_t RAIL_CopyDeviceInfo(RAIL_Handle_t genericRailHandle); + /** * Initialize RAIL. * - * @param[in,out] railCfg The configuration and state structure for setting up - * the library, which contains memory and other options that RAIL needs. - * This structure must be allocated in application global read-write - * memory. RAIL may modify fields within or referenced by this structure - * during its operation. + * @param[in] railCfg The configuration for setting up the protocol. * @param[in] cb A callback that notifies the application when the radio is * finished initializing and is ready for further configuration. This * callback is useful for potential transceiver products that require a @@ -316,9 +325,11 @@ RAIL_Status_t RAILCb_LoadSfmSequencer(void); * invalid value was passed in the railCfg. * * @note Call this function only once per protocol. If called - * again, it will do nothing and return NULL. + * again, it will do nothing and return NULL. \ref RAIL_CopyDeviceInfo() + * should be called once before calling this function for + * Silicon Labs Series 3 devices. */ -RAIL_Handle_t RAIL_Init(RAIL_Config_t *railCfg, +RAIL_Handle_t RAIL_Init(const RAIL_Config_t *railCfg, RAIL_InitCompleteCallbackPtr_t cb); /** @@ -327,8 +338,8 @@ RAIL_Handle_t RAIL_Init(RAIL_Config_t *railCfg, * @return true if the radio has finished initializing and * false otherwise. * - * RAIL APIs, e.g., RAIL_GetTime(), which work only if RAIL_Init() has been called, - * can use RAIL_IsInitialized() to determine whether RAIL has been initialized or not. + * RAIL APIs, e.g., \ref RAIL_GetTime(), which work only if \ref RAIL_Init() has been called, + * can use \ref RAIL_IsInitialized() to determine whether RAIL has been initialized or not. */ bool RAIL_IsInitialized(void); @@ -368,12 +379,12 @@ uint16_t RAIL_GetRadioEntropy(RAIL_Handle_t railHandle, /** * Configure PTI pin locations, serial protocols, and baud rates. * - * @param[in] railHandle A RAIL instance handle, e.g., \ref RAIL_EFR32_HANDLE. + * @param[in] railHandle A radio-generic or real RAIL instance handle. * @param[in] ptiConfig A non-NULL pointer to the PTI configuration structure * to use. * @return Status code indicating success of the function call. * - * This method must be called before RAIL_EnablePti() is called. + * This method must be called before \ref RAIL_EnablePti() is called. * There is only one PTI configuration that can be active on a * radio, regardless of the number of protocols (unless the application * updates the configuration upon a protocol switch -- RAIL does not @@ -383,6 +394,10 @@ uint16_t RAIL_GetRadioEntropy(RAIL_Handle_t railHandle, * * @note On EFR32 platforms GPIO configuration must be unlocked * (see GPIO->LOCK register) to configure or use PTI. + * + * @warning As this function relies on GPIO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if GPIO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_ConfigPti(RAIL_Handle_t railHandle, const RAIL_PtiConfig_t *ptiConfig); @@ -390,7 +405,7 @@ RAIL_Status_t RAIL_ConfigPti(RAIL_Handle_t railHandle, /** * Get the currently-active PTI configuration. * - * @param[in] railHandle A RAIL instance handle, e.g., \ref RAIL_EFR32_HANDLE. + * @param[in] railHandle A radio-generic or real RAIL instance handle. * @param[out] ptiConfig A non-NULL pointer to the configuration structure * to be filled in with the active PTI configuration. * @return RAIL status indicating success of the function call. @@ -406,7 +421,7 @@ RAIL_Status_t RAIL_GetPtiConfig(RAIL_Handle_t railHandle, /** * Enable Packet Trace Interface (PTI) output of packet data. * - * @param[in] railHandle A RAIL instance handle, e.g., \ref RAIL_EFR32_HANDLE. + * @param[in] railHandle A radio-generic or real RAIL instance handle. * @param[in] enable PTI is enabled if true; disabled if false. * @return Status code indicating success of the function call. * @@ -424,6 +439,10 @@ RAIL_Status_t RAIL_GetPtiConfig(RAIL_Handle_t railHandle, * If GPIO configuration locking is desired, PTI must be disabled * beforehand either with this function or with \ref RAIL_ConfigPti() * using \ref RAIL_PTI_MODE_DISABLED. + * + * @warning As this function relies on GPIO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if GPIO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_EnablePti(RAIL_Handle_t railHandle, bool enable); @@ -472,7 +491,7 @@ RAIL_PtiProtocol_t RAIL_GetPtiProtocol(RAIL_Handle_t railHandle); * @warning This API must be called before any TX or RX occurs. Otherwise, * the antenna configurations for those functions will not take effect. * - * @param[in] railHandle A RAIL instance handle, e.g., \ref RAIL_EFR32_HANDLE. + * @param[in] railHandle A radio-generic or real RAIL instance handle. * @param[in] config A pointer to a configuration structure applied to the relevant Antenna * Configuration registers. A NULL configuration will produce undefined behavior. * @return Status code indicating success of the function call. @@ -553,7 +572,7 @@ RAIL_Status_t RAIL_ConfigRadio(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in] length The expected fixed frame length. A value of 0 is infinite. - * A value of RAIL_SETFIXEDLENGTH_INVALID restores the frame's length back to + * A value of \ref RAIL_SETFIXEDLENGTH_INVALID restores the frame's length back to * the length specified by the default frame type configuration. * @return The new frame length configured into the hardware * for use: 0 if in infinite mode, or \ref RAIL_SETFIXEDLENGTH_INVALID if the frame @@ -562,7 +581,7 @@ RAIL_Status_t RAIL_ConfigRadio(RAIL_Handle_t railHandle, * Sets the fixed-length configuration for transmit and receive. * Be careful when using this function in receive and transmit as this * function changes the default frame configuration and remains in force until - * it is called again with an input value of RAIL_SETFIXEDLENGTH_INVALID. This + * it is called again with an input value of \ref RAIL_SETFIXEDLENGTH_INVALID. This * function will override any fixed or variable length settings from a radio * configuration. */ @@ -592,6 +611,37 @@ uint16_t RAIL_ConfigChannels(RAIL_Handle_t railHandle, const RAIL_ChannelConfig_t *config, RAIL_RadioConfigChangedCallback_t cb); +/** + * Configure the channels supported by this device. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] config A pointer to the channel configuration for your device. + * This pointer will be cached in the library so it must + * exist for the runtime of the application. Typically, this should be + * what is stored in Flash by the configuration tool. + * @param[in] cb A pointer to a function called whenever a radio + * configuration change occurs. May be NULL if do not need a callback. + * @return Status code indicating success of the function call. + * + * @note Unlike \ref RAIL_ConfigChannels(), this function only caches the + * configuration and does not prepare any channel in the configuration. That + * action is deferred to the next call to a RAIL API where channel is passed + * as a parameter, namely + * \ref RAIL_PrepareChannel(), \ref RAIL_StartTx(), + * \ref RAIL_StartScheduledTx(), \ref RAIL_StartCcaCsmaTx(), + * \ref RAIL_StartCcaLbtTx(), \ref RAIL_StartScheduledCcaCsmaTx(), + * \ref RAIL_StartScheduledCcaLbtTx(), \ref RAIL_StartRx(), + * \ref RAIL_ScheduleRx(), \ref RAIL_StartAverageRssi(), + * \ref RAIL_StartTxStream(). + * + * @note config can be NULL to simply register or unregister the cb callback + * function when using RAIL internal protocol-specific radio configuration + * APIs for BLE, IEEE 802.15.4, or Z-Wave, which lack callback specification. + */ +RAIL_Status_t RAIL_ConfigChannelsAlt(RAIL_Handle_t railHandle, + const RAIL_ChannelConfig_t *config, + RAIL_RadioConfigChangedCallback_t cb); + /** * Get verbose listing of channel metadata for the current channel configuration. * @@ -662,11 +712,11 @@ RAIL_Status_t RAIL_PrepareChannel(RAIL_Handle_t railHandle, uint16_t channel); * or \ref RAIL_STATUS_INVALID_PARAMETER if channel parameter is NULL. * * This function returns the channel most recently specified in API calls that - * pass in a channel to tune to, namely \ref RAIL_PrepareChannel, - * \ref RAIL_StartTx, \ref RAIL_StartScheduledTx, \ref RAIL_StartCcaCsmaTx, - * \ref RAIL_StartCcaLbtTx, \ref RAIL_StartScheduledCcaCsmaTx, - * \ref RAIL_StartScheduledCcaLbtTx, \ref RAIL_StartRx, \ref RAIL_ScheduleRx, - * \ref RAIL_StartAverageRssi, \ref RAIL_StartTxStream, \ref RAIL_StartTxStreamAlt. + * pass in a channel to tune to, namely \ref RAIL_PrepareChannel(), + * \ref RAIL_StartTx(), \ref RAIL_StartScheduledTx(), \ref RAIL_StartCcaCsmaTx(), + * \ref RAIL_StartCcaLbtTx(), \ref RAIL_StartScheduledCcaCsmaTx(), + * \ref RAIL_StartScheduledCcaLbtTx(), \ref RAIL_StartRx(), \ref RAIL_ScheduleRx(), + * \ref RAIL_StartAverageRssi(), \ref RAIL_StartTxStream(), \ref RAIL_StartTxStreamAlt(). * It doesn't follow changes RAIL performs implicitly during channel hopping * and mode switch. */ @@ -793,12 +843,12 @@ RAIL_Status_t RAIL_GetSyncWords(RAIL_Handle_t railHandle, * @return Status code indicating success of the function call. * * When the custom sync word(s) applied by this API are no longer needed, or to - * revert to default sync word, calling RAIL_ConfigChannels() will re-establish + * revert to default sync word, calling \ref RAIL_ConfigChannels() will re-establish * the sync words specified in the radio configuration. * * This function will return \ref RAIL_STATUS_INVALID_STATE if called when BLE * has been enabled for this railHandle. When changing sync words in BLE mode, - * use \ref RAIL_BLE_ConfigChannelRadioParams instead. + * use \ref RAIL_BLE_ConfigChannelRadioParams() instead. **/ RAIL_Status_t RAIL_ConfigSyncWords(RAIL_Handle_t railHandle, const RAIL_SyncWordConfig_t *syncWordConfig); @@ -897,7 +947,7 @@ RAIL_Status_t RAIL_ResetCrcInitVal(RAIL_Handle_t railHandle); /// These functions can be used to get information about the current system time /// or to manipulate the RAIL timer. /// -/// The system time returned by RAIL_GetTime() is in the same timebase that is +/// The system time returned by \ref RAIL_GetTime() is in the same timebase that is /// used throughout RAIL. Any callbacks or structures that provide a timestamp, /// such as \ref RAIL_RxPacketDetails_t::timeReceived, will use the same timebase /// as will any APIs that accept an absolute time for scheduling their action. @@ -910,8 +960,8 @@ RAIL_Status_t RAIL_ResetCrcInitVal(RAIL_Handle_t railHandle); /// for timing any event in the system, but is especially helpful for /// timing protocol-based state machines and other systems that interact with /// the radio. To avoid processing the expiration in interrupt -/// context, leave the cb parameter passed to RAIL_SetTimer() as NULL and poll -/// for expiration with the RAIL_IsTimerExpired() function. See below for an +/// context, leave the cb parameter passed to \ref RAIL_SetTimer() as NULL and poll +/// for expiration with the \ref RAIL_IsTimerExpired() function. See below for an /// example of the interrupt driven method of interacting with the timer. /// @code{.c} /// void timerCb(RAIL_Handle_t cbArg) @@ -1022,7 +1072,7 @@ RAIL_Status_t RAIL_DelayUs(RAIL_Time_t microseconds); * @param[in] time The timer's expiration time in the RAIL timebase. * @param[in] mode Indicates whether the time argument is an absolute * RAIL time or relative to the current RAIL time. Specifying mode - * \ref RAIL_TIME_DISABLED is the same as calling RAIL_CancelTimer(). + * \ref RAIL_TIME_DISABLED is the same as calling \ref RAIL_CancelTimer(). * @param[in] cb A pointer to a callback function that RAIL will call * when the timer expires. May be NULL if no callback is desired. * @return \ref RAIL_STATUS_NO_ERROR on success and @@ -1051,7 +1101,7 @@ RAIL_Status_t RAIL_SetTimer(RAIL_Handle_t railHandle, * @return The absolute time that this timer was set to expire. * * Provides the absolute time regardless of the \ref RAIL_TimeMode_t that - * was passed into \ref RAIL_SetTimer. Note that the time might be in the + * was passed into \ref RAIL_SetTimer(). Note that the time might be in the * past if the timer has already expired. The return value is undefined if the * timer was never set. */ @@ -1101,11 +1151,11 @@ bool RAIL_IsTimerRunning(RAIL_Handle_t railHandle); * so that the user can have as many timers as desired. It is not necessary to * call this function if the MultiTimer APIs are not used. * - * @note This function must be called before calling \ref RAIL_SetMultiTimer. + * @note This function must be called before calling \ref RAIL_SetMultiTimer(). * This function is a no-op on multiprotocol as this layer is already used * under the hood. * Do not call this function while the RAIL timer is running. - * Call \ref RAIL_IsTimerRunning before enabling/disabling the multitimer. + * Call \ref RAIL_IsTimerRunning() before enabling/disabling the multitimer. * If the multitimer is not needed, do not call this function to * allow the multitimer code to be dead stripped. If the multitimer is * enabled for use, the multitimer and timer APIs can both be used. @@ -1121,7 +1171,7 @@ bool RAIL_ConfigMultiTimer(bool enable); * @param[in] expirationMode Select mode of expirationTime. See \ref * RAIL_TimeMode_t. * @param[in] callback A function to call on timer expiry. See \ref - * RAIL_MultiTimerCallback_t. NULL is a legal value. + * RAIL_MultiTimerCallback_t. May be NULL if no callback is desired. * @param[in] cbArg An extra callback function parameter for the user application. * @return * \ref RAIL_STATUS_NO_ERROR on success.@n @@ -1141,12 +1191,12 @@ RAIL_Status_t RAIL_SetMultiTimer(RAIL_MultiTimer_t *tmr, /** * Stop the currently scheduled RAIL multitimer. * - * @param[in,out] tmr A RAIL timer instance handle. + * @param[in,out] tmr A pointer to a RAIL timer instance. * @return true if the timer was successfully canceled; * false if the timer was not running. * * Cancels the timer. If this function is called before the timer expires, - * the cb callback specified in the earlier RAIL_SetTimer() call will never + * the cb callback specified in the earlier \ref RAIL_SetTimer() call will never * be called. */ bool RAIL_CancelMultiTimer(RAIL_MultiTimer_t *tmr); @@ -1154,8 +1204,9 @@ bool RAIL_CancelMultiTimer(RAIL_MultiTimer_t *tmr); /** * Check if a given timer is running. * - * @param[in] tmr A pointer to the timer structure to query. - * @return true if the timer is running; false if the timer is not running. + * @param[in] tmr A pointer to the timer instance. + * @return true if the timer is running; false if the timer is not running + * or tmr is not a timer instance. */ bool RAIL_IsMultiTimerRunning(RAIL_MultiTimer_t *tmr); @@ -1163,14 +1214,15 @@ bool RAIL_IsMultiTimerRunning(RAIL_MultiTimer_t *tmr); * Check if a given timer has expired. * * @param[in] tmr A pointer to the timer instance. - * @return true if the timer is expired; false if the timer is running. + * @return true if the timer has expired or tmr is not a timer instance; + * false if the timer is running. */ bool RAIL_IsMultiTimerExpired(RAIL_MultiTimer_t *tmr); /** * Get time left before a given timer instance expires. * - * @param[in] tmr A pointer to the timer structure to query. + * @param[in] tmr A pointer to the timer instance to query. * @param[in] timeMode Indicates how the function provides the time * remaining. By choosing \ref * RAIL_TimeMode_t::RAIL_TIME_ABSOLUTE, the function returns the @@ -1179,7 +1231,7 @@ bool RAIL_IsMultiTimerExpired(RAIL_MultiTimer_t *tmr); * amount of time remaining before the timer's expiration. * @return * Time left expressed in RAIL's time units. - * 0 if the soft timer is not running or has already expired. + * 0 if the timer is not running or has already expired. */ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, RAIL_TimeMode_t timeMode); @@ -1200,12 +1252,12 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// synchronized to a running LFCLK and the chip is set to wake up before the /// next scheduled event. /// If RAIL has not been configured to use the power manager, -/// \ref RAIL_Sleep and \ref RAIL_Wake must be called for performing this +/// \ref RAIL_Sleep() and \ref RAIL_Wake() must be called for performing this /// synchronization. /// If RAIL has been configured to use the power manager, -/// \ref RAIL_InitPowerManager, it will automatically perform timer +/// \ref RAIL_InitPowerManager(), it will automatically perform timer /// synchronization based on the selected \ref RAIL_TimerSyncConfig_t. Calls to -/// \ref RAIL_Sleep and \ref RAIL_Wake are unsupported in such a scenario. +/// \ref RAIL_Sleep() and \ref RAIL_Wake() are unsupported in such a scenario. /// /// Following example code snippets demonstrate synchronizing the timebase /// with and without timer synchronization: @@ -1216,7 +1268,7 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// LFCLK up and running and leave it running across sleep so that the high /// frequency clock that drives the RAIL time base can be synchronized to it. /// The \ref RAIL_Sleep() API will also set up a wake event on the timer to wake -/// up wakeupTime before the next timer event so that it can run successfully. +/// up wakeupProcessTime before the next timer event so that it can run successfully. /// See the \ref efr32_main sections on Low-Frequency Clocks and RAIL Timer /// Synchronization for more setup details. /// @@ -1231,7 +1283,7 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// /// extern RAIL_Handle_t railHandle; /// // Wakeup time for your crystal/board/chip combination -/// extern uint32_t wakeupTime; +/// extern uint32_t wakeupProcessTime; /// /// void main(void) /// { @@ -1244,7 +1296,8 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// BoardSetupLFCLK() /// /// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); +/// RAIL_TimerSyncConfig_t timerSyncConfig = RAIL_TIMER_SYNC_DEFAULT; +/// status = RAIL_ConfigSleepAlt(railHandle, &timerSyncConfig); /// assert(status == RAIL_STATUS_NO_ERROR); /// /// // Application main loop @@ -1256,7 +1309,7 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// /// // Go critical to assess sleep decisions /// CORE_ENTER_CRITICAL(); -/// if (RAIL_Sleep(wakeupTime, &sleepAllowed) != RAIL_STATUS_NO_ERROR) { +/// if (RAIL_Sleep(wakeupProcessTime, &sleepAllowed) != RAIL_STATUS_NO_ERROR) { /// printf("Error trying to go to sleep!"); /// CORE_EXIT_CRITICAL(); /// continue; @@ -1289,7 +1342,8 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// // will attempt to auto detect the clock. /// BoardSetupLFCLK(); /// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); +/// RAIL_TimerSyncConfig_t timerSyncConfig = RAIL_TIMER_SYNC_DEFAULT; +/// status = RAIL_ConfigSleepAlt(railHandle, &timerSyncConfig); /// assert(status == RAIL_STATUS_NO_ERROR); /// // Initialize application-level power manager service /// sl_power_manager_init(); @@ -1308,8 +1362,8 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// } /// @endcode /// -/// RAIL APIs such as, \ref RAIL_StartScheduledTx, \ref RAIL_ScheduleRx, -/// \ref RAIL_SetTimer, \ref RAIL_SetMultiTimer can be used to schedule periodic +/// RAIL APIs such as, \ref RAIL_StartScheduledTx(), \ref RAIL_ScheduleRx(), +/// \ref RAIL_SetTimer(), \ref RAIL_SetMultiTimer() can be used to schedule periodic /// wakeups to perform a scheduled operation. The call to /// sl_power_manager_sleep() in the main loop ensures that the device sleeps /// until the scheduled operation is due. @@ -1317,11 +1371,11 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// indicate radio busy to the power manager to allow the application to /// service the RAIL event and perform subsequent operations before going to /// sleep. Therefore, it is important that the application idle the radio by either -/// calling \ref RAIL_Idle or \ref RAIL_YieldRadio. +/// calling \ref RAIL_Idle() or \ref RAIL_YieldRadio(). /// If the radio transitions to RX after an RX or TX operation, -/// always call \ref RAIL_Idle in order transition to a lower sleep state. +/// always call \ref RAIL_Idle() in order transition to a lower sleep state. /// If the radio transitions to idle after an RX or TX operation, -/// \ref RAIL_YieldRadio should suffice in indicating to the power manager +/// \ref RAIL_YieldRadio() should suffice in indicating to the power manager /// that the radio is no longer busy and the device can sleep. /// /// The following example shows scheduling periodic TX on getting a TX completion @@ -1342,16 +1396,16 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// @endcode /// /// @note The above code assumes that RAIL automatic state transitions after TX -/// are idle. Set \ref RAIL_SetTxTransitions to ensure the right state -/// transitions. Radio must be idle for the device to enter EM2 or lower +/// are idle. Use \ref RAIL_SetTxTransitions() to ensure the right state +/// transitions are used. Radio must be idle for the device to enter EM2 or lower /// energy mode. /// -/// @note When using the power manager, usage of \ref RAIL_YieldRadio in +/// @note When using the power manager, usage of \ref RAIL_YieldRadio() in /// single protocol RAIL is similar to its usage in multiprotocol RAIL. /// See \ref rail_radio_scheduler_yield for more details. /// /// @note Back to back scheduled operations do not require an explicit call to -/// \ref RAIL_YieldRadio if the radio transitions to idle. +/// \ref RAIL_YieldRadio() if the radio transitions to idle. /// /// Sleep without timer synchronization: /// @@ -1373,8 +1427,11 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// RAIL_Status_t status; /// bool shouldSleep = false; /// -/// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED); +/// // Configure sleep for no timer synchronization +/// RAIL_TimerSyncConfig_t timerSyncConfig = { +/// .sleep = RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED, +/// }; +/// status = RAIL_ConfigSleepAlt(railHandle, &timerSyncConfig); /// assert(status == RAIL_STATUS_NO_ERROR); /// /// // Application main loop @@ -1420,8 +1477,11 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, /// // you intend to use for RTCC sync before we configure sleep as that function /// // will attempt to auto detect the clock. /// BoardSetupLFCLK(); -/// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED); +/// // Configure sleep for no timer synchronization +/// RAIL_TimerSyncConfig_t timerSyncConfig = { +/// .sleep = RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED, +/// }; +/// status = RAIL_ConfigSleepAlt(railHandle, &timerSyncConfig); /// assert(status == RAIL_STATUS_NO_ERROR); /// // Initialize application-level power manager service /// sl_power_manager_init(); @@ -1446,7 +1506,7 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, * structure containing the configuration parameters for timer sync. The * \ref RAIL_TimerSyncConfig_t::sleep field is ignored in this call. * - * This function is called during \ref RAIL_ConfigSleep to allow an application + * This function is called during \ref RAIL_ConfigSleep() to allow an application * to configure the PRS and RTCC channels used for timer sync to values other * than their defaults. The default channels are populated in timerSyncConfig and * can be overwritten by the application. If this function is not implemented by the @@ -1461,7 +1521,7 @@ RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, * } * @endcode * - * If an unsupported channel is selected by the application, \ref RAIL_ConfigSleep + * If an unsupported channel is selected by the application, \ref RAIL_ConfigSleep() * will return \ref RAIL_STATUS_INVALID_PARAMETER. */ void RAILCb_ConfigSleepTimerSync(RAIL_TimerSyncConfig_t *timerSyncConfig); @@ -1472,6 +1532,12 @@ void RAILCb_ConfigSleepTimerSync(RAIL_TimerSyncConfig_t *timerSyncConfig); * @param[in] railHandle A RAIL instance handle. * @param[in] sleepConfig A sleep configuration. * @return Status code indicating success of the function call. + * + * @warning As this function relies on PRS and SYSRTC access and RAIL is meant + * to run in TrustZone non-secure world, it is not supported if PRS or SYSRTC + * are configured as secure peripheral and sleepConfig is set to + * \ref RAIL_SleepConfig_t::RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED. It will + * return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_ConfigSleep(RAIL_Handle_t railHandle, RAIL_SleepConfig_t sleepConfig); @@ -1480,14 +1546,20 @@ RAIL_Status_t RAIL_ConfigSleep(RAIL_Handle_t railHandle, * Initialize RAIL timer synchronization. * * @param[in] railHandle A RAIL instance handle. - * @param[in] syncConfig A pointer to the timer synchronization configuration. + * @param[in] syncConfig A non-NULL pointer to the timer synchronization configuration. * @return Status code indicating success of the function call. * * The default structure used to enable timer synchronization across sleep is * \ref RAIL_TIMER_SYNC_DEFAULT. + * + * @warning As this function relies on PRS and SYSRTC access and RAIL is meant + * to run in TrustZone non-secure world, it is not supported if PRS or SYSRTC + * are configured as secure peripheral and syncConfig->sleep is set to + * \ref RAIL_SleepConfig_t::RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED. It will + * return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_ConfigSleepAlt(RAIL_Handle_t railHandle, - RAIL_TimerSyncConfig_t *syncConfig); + const RAIL_TimerSyncConfig_t *syncConfig); /** * Stop the RAIL timer(s) and prepare RAIL for sleep. @@ -1512,7 +1584,7 @@ RAIL_Status_t RAIL_Sleep(uint16_t wakeupProcessTime, bool *deepSleepAllowed); * to the RAIL timer(s) before restarting it(them). * @return Status code indicating success of the function call. * - * If the timer sync was enabled by \ref RAIL_ConfigSleep, synchronize the RAIL + * If the timer sync was enabled by \ref RAIL_ConfigSleep(), synchronize the RAIL * timer(s) using an alternate timer. Otherwise, add elapsedTime to the RAIL * timer(s). * @@ -1534,6 +1606,10 @@ RAIL_Status_t RAIL_Wake(RAIL_Time_t elapsedTime); * @warning Since EM transition callbacks are not called in a deterministic * order, it is suggested to not call any RAIL time dependent APIs * in an EM transition callback. + * + * @warning As this function relies on EMU access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if EMU is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_InitPowerManager(void); @@ -1564,13 +1640,11 @@ RAIL_Status_t RAIL_DeinitPowerManager(void); * * @param[in] railHandle A RAIL instance handle. * @param[in] mask A bitmask of events to configure. - * @param[in] events A bitmask of events to trigger \ref RAIL_Config_t::eventsCallback - * For a full list of available callbacks, see - * RAIL_EVENT_* set of defines. + * @param[in] events A bitmask of events to trigger \ref RAIL_Config_t::eventsCallback. * @return Status code indicating success of the function call. * * Sets up which radio interrupts generate a RAIL event. The full list of - * options is in \ref RAIL_Events_t. + * events is in \ref RAIL_Events_t. */ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, RAIL_Events_t mask, @@ -1598,7 +1672,7 @@ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, /// RAIL_DataMethod_t::FIFO_MODE operation but can be used in \ref /// RAIL_DataMethod_t::PACKET_MODE too. /// -/// The application can configure RAIL data management through +/// The application can configure RAIL data management through \ref /// RAIL_ConfigData(). This function allows the application to specify the type /// of radio data (\ref RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and /// the method of interacting with data (\ref RAIL_DataMethod_t). By default, @@ -1608,23 +1682,23 @@ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, /// For transmit, \ref RAIL_DataMethod_t::PACKET_MODE and \ref /// RAIL_DataMethod_t::FIFO_MODE are functionally the same: /// - When not actively transmitting, load a packet's initial transmit -/// data using RAIL_WriteTxFifo() with reset set to true. Alternatively +/// data using \ref RAIL_WriteTxFifo() with reset set to true. Alternatively /// this data copying can be avoided by changing the transmit FIFO to an /// already-loaded section of memory with \ref RAIL_SetTxFifo(). /// - When actively transmitting, load remaining transmit data with -/// RAIL_WriteTxFifo() with reset set to false. +/// \ref RAIL_WriteTxFifo() with reset set to false. /// - If transmit packets exceed the FIFO size, set the transmit FIFO -/// threshold through RAIL_SetTxFifoThreshold(). The \ref +/// threshold through \ref RAIL_SetTxFifoThreshold(). The \ref /// RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY /// will occur telling the application to load more TX packet data, if /// needed, to prevent a \ref RAIL_EVENT_TX_UNDERFLOW event from occurring. /// One can get how much space is available in the transmit FIFO for more -/// transmit data through RAIL_GetTxFifoSpaceAvailable(). +/// transmit data through \ref RAIL_GetTxFifoSpaceAvailable(). /// - After transmit completes, the transmit FIFO can be manually reset -/// with RAIL_ResetFifo(), but this should rarely be necessary. +/// with \ref RAIL_ResetFifo(), but this should rarely be necessary. /// /// The transmit FIFO is specified by the application and its size is -/// the value returned from the most recent call to RAIL_SetTxFifo(). +/// the value returned from the most recent call to \ref RAIL_SetTxFifo(). /// The transmit FIFO is edge-based in that it only provides the \ref /// RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event once when the threshold is crossed /// in the emptying direction. @@ -1642,10 +1716,10 @@ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, /// and can be read out at the end using \ref RAIL_GetRxPacketInfo(). /// - Received packet data is made available on successful packet completion /// via \ref RAIL_Config_t::eventsCallback with \ref -/// RAIL_EVENT_RX_PACKET_RECEIVED which can then use RAIL_GetRxPacketInfo() -/// and RAIL_GetRxPacketDetailsAlt() to access packet information and -/// RAIL_PeekRxPacket() to access packet data. -/// - Filtered, Aborted, or FrameError received packet data is automatically +/// RAIL_EVENT_RX_PACKET_RECEIVED which can then use \ref RAIL_GetRxPacketInfo() +/// and \ref RAIL_GetRxPacketDetailsAlt() to access packet information and +/// \ref RAIL_PeekRxPacket() to access packet data. +/// - FILTERED, ABORTED, or FRAMEERROR received packet data is automatically /// rolled back (dropped) without the application needing to worry about /// consuming it. /// The application can choose to not even be bothered with the events @@ -1656,52 +1730,54 @@ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, /// - Packet Lengths are determined from the Radio Configurator configuration /// or by application knowledge of packet payload structure. /// - Received data can be retrieved prior to packet completion through -/// RAIL_ReadRxFifo() and is never rolled back on Filtered, Aborted, or -/// FrameError packets. The application should enable and handle these +/// \ref RAIL_ReadRxFifo() and is never rolled back on FILTERED, ABORTED, or +/// FRAMEERROR packets. The application should enable and handle these /// events so it can flush any packet data it's already retrieved. -/// - After packet completion, remaining packet data for Filtered, Aborted, -/// or FrameError packets remains in the FIFO and the appropriate event is +/// - After packet completion, remaining packet data for FILTERED, ABORTED, +/// or FRAMEERROR packets remains in the FIFO and the appropriate event is /// triggered to the user. This data may be consumed in the callback unlike /// in packet mode where it is automatically rolled back. At the end of the /// callback all remaining data in the FIFO will be cleaned up as usual. -/// Keep in mind that RAIL_GetRxPacketDetailsAlt() provides full packet +/// Keep in mind that \ref RAIL_GetRxPacketDetailsAlt() provides full packet /// detailed information only for successfully received packets. /// /// Common receive data management features: -/// - Set the receive FIFO threshold through RAIL_SetRxFifoThreshold(). The +/// - Set the receive FIFO threshold through \ref RAIL_SetRxFifoThreshold(). The /// \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL /// will occur telling the application to consume some RX packet data to /// prevent a \ref RAIL_EVENT_RX_FIFO_OVERFLOW event from occurring. /// - Get receive FIFO count information through -/// RAIL_GetRxPacketInfo(\ref RAIL_RX_PACKET_HANDLE_NEWEST) -/// (or RAIL_GetRxFifoBytesAvailable()). +/// \ref RAIL_GetRxPacketInfo(\ref RAIL_RX_PACKET_HANDLE_NEWEST) +/// (or \ref RAIL_GetRxFifoBytesAvailable()). /// - After receive completes and all its data has been consumed, the receive -/// FIFO can be manually reset with RAIL_ResetFifo(), though this should +/// FIFO can be manually reset with \ref RAIL_ResetFifo(), though this should /// rarely be necessary and should only be done with the radio idle. /// /// When trying to determine an appropriate threshold, the application needs /// to know the size of each FIFO. The default receive FIFO is internal to RAIL /// with a size of 512 bytes. This can be changed, however, using /// \ref RAIL_SetRxFifo() and the default may be removed entirely by calling -/// this from the RAILCb_SetupRxFifo() callback. The receive FIFO event is +/// this from the \ref RAILCb_SetupRxFifo() callback. The receive FIFO event is /// level-based in that the \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event will /// constantly pend if the threshold is exceeded. This normally means that /// inside this event's callback, the application should empty enough of the FIFO /// to go under the threshold. To defer reading the FIFO to main context, the /// application can disable or re-enable the receive FIFO threshold event using -/// RAIL_ConfigEvents() with the mask \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL. +/// \ref RAIL_ConfigEvents() with the mask \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL. /// /// The receive FIFO can store multiple packets and processing of a packet can /// be deferred from the RAIL event callback to main-loop processing -/// by using RAIL_HoldRxPacket() in the event callback and -/// RAIL_ReleaseRxPacket() in the main-loop. +/// by using \ref RAIL_HoldRxPacket() in the event callback and +/// \ref RAIL_ReleaseRxPacket() in the main-loop. /// On some platforms, the receive FIFO is supplemented by an internal /// fixed-size packet metadata FIFO that limits the number of packets /// RAIL and applications can hold onto for deferred processing. /// See chip-specific documentation, such as \ref efr32_main, for more -/// information. Note that when using multiprotocol the receive FIFO is reset -/// prior to a protocol switch so held packets will be lost if not processed -/// before then. +/// information. +/// +/// @note When using multiprotocol the receive FIFO is reset +/// prior to a protocol switch so held packets will be lost if not processed +/// before then. /// /// While \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL occurs solely based on the /// state of the receive FIFO used for packet data, both @@ -1713,7 +1789,7 @@ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, /// for new packets/data, reducing the possibility of packet/data loss /// and \ref RAIL_EVENT_RX_FIFO_OVERFLOW. /// -/// Before a packet is fully received you can always use +/// Before a packet is fully received you can always use \ref /// RAIL_PeekRxPacket() to look at the contents. In FIFO mode, you may also /// consume its data with \ref RAIL_ReadRxFifo(). Remember that none of these /// APIs will read across a packet boundary (even in FIFO mode) so you will @@ -1840,12 +1916,12 @@ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, * sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. * * Generally with \ref RAIL_DataMethod_t::FIFO_MODE, the application sets - * appropriate FIFO thresholds via RAIL_SetTxFifoThreshold() and - * RAIL_SetRxFifoThreshold() and then enables and handles the + * appropriate FIFO thresholds via \ref RAIL_SetTxFifoThreshold() and + * \ref RAIL_SetRxFifoThreshold() and then enables and handles the * \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event callback (to feed more packet - * data via RAIL_WriteTxFifo() before the FIFO underflows) and the \ref + * data via \ref RAIL_WriteTxFifo() before the FIFO underflows) and the \ref * RAIL_EVENT_RX_FIFO_ALMOST_FULL event callback (to consume packet data - * via RAIL_ReadRxFifo() before the receive FIFO overflows). + * via \ref RAIL_ReadRxFifo() before the receive FIFO overflows). * * When configuring TX for \ref RAIL_DataMethod_t::FIFO_MODE, this * function resets the transmit FIFO. When configuring TX or RX for @@ -1860,13 +1936,13 @@ RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, * to deal with accordingly. On completion of erroneous packets, the * \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_PACKET_ABORTED, * \ref RAIL_EVENT_RX_FRAME_ERROR, or \ref RAIL_EVENT_RX_ADDRESS_FILTERED will - * tell the application it can drop any data it read via RAIL_ReadRxFifo() during reception. + * tell the application it can drop any data it read via \ref RAIL_ReadRxFifo() during reception. * For CRC error packets when the \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS * RX option is in effect, the application should check for that from the - * \ref RAIL_RxPacketStatus_t obtained by calling RAIL_GetRxPacketInfo(). + * \ref RAIL_RxPacketStatus_t obtained by calling \ref RAIL_GetRxPacketInfo(). * RAIL will automatically flush any remaining packet data after reporting * one of these packet completion events or the application can explicitly - * flush it by calling RAIL_ReleaseRxPacket(). + * flush it by calling \ref RAIL_ReleaseRxPacket(). * * When \ref RAIL_DataConfig_t::rxMethod is set to \ref * RAIL_DataMethod_t::PACKET_MODE, the radio will roll back (drop) all packet @@ -1898,14 +1974,14 @@ RAIL_Status_t RAIL_ConfigData(RAIL_Handle_t railHandle, * @return The number of bytes written to the transmit FIFO. * * This function copies writeLength bytes of data from the provided dataPtr into the - * transmit FIFO previously established by RAIL_SetTxFifo() or RAIL_Init(). + * transmit FIFO previously established by \ref RAIL_SetTxFifo() or \ref RAIL_Init(). * If the requested writeLength exceeds the current number of bytes open * in the transmit FIFO, the function only writes until the transmit FIFO * is full. The function returns the number of bytes written to the transmit - * FIFO or returns zero if raiHhandle is NULL or if the transmit FIFO is full. + * FIFO or returns zero if railHandle is NULL or if the transmit FIFO is full. * * @note The protocol's packet configuration, as set up by the radio - * configurator or via RAIL_SetFixedLength(), determines how many + * configurator or via \ref RAIL_SetFixedLength(), determines how many * bytes of data are consumed from the transmit FIFO for a successful transmit * operation, not the writeLength value passed in. If not enough data has * been put into the transmit FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will @@ -1926,7 +2002,8 @@ uint16_t RAIL_WriteTxFifo(RAIL_Handle_t railHandle, bool reset); /** - * Set the address of the transmit FIFO, a circular buffer used for TX data. + * Set the address of the transmit FIFO, a circular buffer used for TX data, + * possibly pre-populated with transmit data. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] addr An appropriately-aligned (see below) pointer to a read-write memory @@ -1951,7 +2028,7 @@ uint16_t RAIL_WriteTxFifo(RAIL_Handle_t railHandle, * size, the FIFO will be filled up to its size. * * A user may write to the custom memory location directly before calling this - * function, or use \ref RAIL_WriteTxFifo to write to the memory location after + * function, or use \ref RAIL_WriteTxFifo() to write to the memory location after * calling this function. Users must specify the initLength for * previously-written memory to be set in the transmit FIFO. * @@ -1959,7 +2036,7 @@ uint16_t RAIL_WriteTxFifo(RAIL_Handle_t railHandle, * returned FIFO size, which is used internally as a circular buffer for the * transmit FIFO. It must be able to hold the entire FIFO size. The caller must * guarantee that the custom FIFO remains intact and unchanged (except via calls - * to \ref RAIL_WriteTxFifo) until the next call to this function. + * to \ref RAIL_WriteTxFifo()) until the next call to this function. * * @note The protocol's packet configuration, as set up by the radio * configurator or via RAIL_SetFixedLength(), determines how many @@ -2020,8 +2097,9 @@ uint16_t RAIL_SetTxFifoAlt(RAIL_Handle_t railHandle, * @param[in,out] addr A pointer to a read-write memory location in RAM used as * the receive FIFO. This memory must persist until the next call to this * function. - * @param[in,out] size A desired size of the receive FIFO in bytes. This will - * be populated with the actual size during the function call. + * @param[in,out] size A pointer to the desired size of the receive + * FIFO in bytes. This will be updated with the actual size during the + * function call. * @return Status code indicating success of the function call. * * This function sets the memory location for the receive FIFO. It @@ -2060,16 +2138,16 @@ RAIL_Status_t RAIL_SetRxFifo(RAIL_Handle_t railHandle, /// @param[in] railHandle A RAIL instance handle. /// @return Status code indicating success of the function call. /// -/// This function is called during the \ref RAIL_Init process to set up the FIFO +/// This callback is called during the \ref RAIL_Init() process to set up the FIFO /// to use for received packets. If not implemented by the application, /// a default implementation from within the RAIL library will be used to /// initialize an internal default 512-byte receive FIFO. /// -/// If this function returns an error, the RAIL_Init process will fail. +/// If this function returns an error, the RAIL_Init() process will fail. /// /// During this function, the application should generally call -/// \ref RAIL_SetRxFifo. If that does not happen, the application needs to -/// set up the receive FIFO via a call to \ref RAIL_SetRxFifo before attempting +/// \ref RAIL_SetRxFifo(). If that does not happen, the application needs to +/// set up the receive FIFO via a call to \ref RAIL_SetRxFifo() before attempting /// to receive any packets. An example implementation may look like the following: /// @code{.c} /// #define RX_FIFO_BYTES 1024 @@ -2216,7 +2294,7 @@ RAIL_Status_t RAIL_ResetFifo(RAIL_Handle_t railHandle, bool txFifo, bool rxFifo) /** * Get the number of bytes used in the receive FIFO. * Only use this function in RX \ref RAIL_DataMethod_t::FIFO_MODE. - * Apps should use RAIL_GetRxPacketInfo() instead. + * Apps should use \ref RAIL_GetRxPacketInfo() instead. * * @param[in] railHandle A RAIL instance handle. * @return Number of bytes used in the receive FIFO. @@ -2229,7 +2307,7 @@ RAIL_Status_t RAIL_ResetFifo(RAIL_Handle_t railHandle, bool txFifo, bool rxFifo) * after successful packet reception and bytes from subsequently received * packets. It is up to the app to never try to consume more than the * packet's actual data when using the value returned here in a subsequent - * call to RAIL_ReadRxFifo(), otherwise the receive FIFO will be corrupted. + * call to \ref RAIL_ReadRxFifo(), otherwise the receive FIFO will be corrupted. */ uint16_t RAIL_GetRxFifoBytesAvailable(RAIL_Handle_t railHandle); @@ -2292,8 +2370,9 @@ RAIL_Status_t RAIL_GetRxTransitions(RAIL_Handle_t railHandle, * * This function fails if unsupported transitions are passed in or if the * radio is currently in the TX state. Success and error can each transition - * to RX or IDLE. For the ability to run repeated transmits, see - * \ref RAIL_SetNextTxRepeat. + * to RX or IDLE only, not TX. For the ability to run repeated transmits, see + * \ref RAIL_SetNextTxRepeat(). Calling this function will clear any repeated + * transmissions set up by \ref RAIL_SetNextTxRepeat(). */ RAIL_Status_t RAIL_SetTxTransitions(RAIL_Handle_t railHandle, const RAIL_StateTransitions_t *transitions); @@ -2328,15 +2407,16 @@ RAIL_Status_t RAIL_GetTxTransitions(RAIL_Handle_t railHandle, * will receive events such as \ref RAIL_EVENT_TX_PACKET_SENT as normal. * * If a TX error occurs during the repetition, the process will abort and the - * TX error transition from \ref RAIL_SetTxTransitions will be used. If the + * TX error transition from \ref RAIL_SetTxTransitions() will be used. If the * repetition completes successfully, then the TX success transition from - * \ref RAIL_SetTxTransitions will be used. + * \ref RAIL_SetTxTransitions() will be used. * * Use \ref RAIL_GetTxPacketsRemaining() if need to know how many transmit * completion events are expected before the repeating sequence is done, or * how many were not performed due to a transmit error. * - * Any call to \ref RAIL_Idle or \ref RAIL_StopTx will clear the pending + * Any call to \ref RAIL_Idle(), \ref RAIL_StopTx(), or \ref + * RAIL_SetTxTransitions() will clear the pending * repeated transmits. The state will also be cleared by another call to this * function. A DMP switch will clear this * state only if the initial transmit triggering the repeated transmits has @@ -2349,7 +2429,7 @@ RAIL_Status_t RAIL_GetTxTransitions(RAIL_Handle_t railHandle, * transmit from repeating. * * The application is responsible for populating the transmit data to be used - * by the repeated transmits via \ref RAIL_SetTxFifo or \ref RAIL_WriteTxFifo. + * by the repeated transmits via \ref RAIL_SetTxFifo() or \ref RAIL_WriteTxFifo(). * Data will be transmitted from the transmit FIFO. If the transmit FIFO does * not have sufficient data to transmit, a TX error will be caused and a \ref * RAIL_EVENT_TX_UNDERFLOW will occur. In order to avoid an underflow, the @@ -2455,7 +2535,7 @@ RAIL_Status_t RAIL_Idle(RAIL_Handle_t railHandle, * When transitioning directly from RX to TX or vice-versa, this function * returns the earlier state. * - * @note For a more detailed radio state, see \ref RAIL_GetRadioStateDetail + * @note For a more detailed radio state, see \ref RAIL_GetRadioStateDetail(). */ RAIL_RadioState_t RAIL_GetRadioState(RAIL_Handle_t railHandle); @@ -2480,7 +2560,7 @@ RAIL_RadioState_t RAIL_GetRadioState(RAIL_Handle_t railHandle); * returned state bitmask will be set; otherwise, this bit will be clear. * * For the most part, the more detailed radio states returned by this API - * correspond to radio states returned by \ref RAIL_GetRadioState as follows: + * correspond to radio states returned by \ref RAIL_GetRadioState() as follows: * * \ref RAIL_RadioStateDetail_t \ref RAIL_RadioState_t * RAIL_RF_STATE_DETAIL_INACTIVE RAIL_RF_STATE_INACTIVE @@ -2598,14 +2678,14 @@ RAIL_Status_t RAIL_EnableCacheSynthCal(RAIL_Handle_t railHandle, bool enable); /// that fit their criteria for the trade-off between radio range and /// power savings, regardless of what dBm power that maps to. /// -/// \ref RAIL_ConvertRawToDbm and \ref RAIL_ConvertDbmToRaw, +/// \ref RAIL_ConvertRawToDbm() and \ref RAIL_ConvertDbmToRaw(), /// which convert between the dBm power and the raw power levels, /// provide a solution that fits all these applications. /// The levels of customization are outlined below: /// 1) No customization needed: for a given dBm value, the result -/// of RAIL_ConvertDbmToRaw provides an appropriate +/// of \ref RAIL_ConvertDbmToRaw() provides an appropriate /// raw power level that, when written to the registers via -/// RAIL_SetPowerLevel, causes the radio to output at that +/// \ref RAIL_SetTxPower(), causes the radio to output at that /// dBm power. In this case, no action is needed by the user, /// the WEAK versions of the conversion functions can be used /// and the default include paths in pa_conversions_efr32.h can @@ -2625,22 +2705,22 @@ RAIL_Status_t RAIL_EnableCacheSynthCal(RAIL_Handle_t railHandle, bool enable); /// 3) A different level of precision is needed and the fit is bad: /// If the piecewise-linear line segment fit is not appropriate for /// your solution, the functions in pa_conversions_efr32.c can be -/// totally rewritten, as long as RAIL_ConvertDbmToRaw and -/// RAIL_ConvertRawToDbm have the same signatures. It is completely +/// totally rewritten, as long as \ref RAIL_ConvertDbmToRaw() and +/// \ref RAIL_ConvertRawToDbm() have the same signatures. It is completely /// acceptable to re-write these in a way that makes the /// pa_curves_efr32.h and pa_curve_types_efr32.h files referenced in /// pa_conversions_efr32.h unnecessary. Those files are needed solely /// for the provided conversion methods. /// 4) dBm values are not necessary: If the application does not require -/// dBm values at all, overwrite -/// RAIL_ConvertDbmToRaw and RAIL_ConvertRawToDbm with smaller functions +/// dBm values at all, overwrite \ref +/// RAIL_ConvertDbmToRaw() and \ref RAIL_ConvertRawToDbm() with smaller functions /// (i.e., return 0 or whatever was input). These functions are called /// from within the RAIL library, so they can never be deadstripped, /// but making them as small as possible is the best way to reduce code -/// size. From there, call RAIL_SetTxPower, without +/// size. From there, call \ref RAIL_SetTxPower(), without /// converting from a dBm value. To stop the library from coercing the -/// power based on channels, overwrite RAIL_ConvertRawToDbm -/// to always return 0 and overwrite RAIL_ConvertDbmToRaw to +/// power based on channels, overwrite \ref RAIL_ConvertRawToDbm() +/// to always return 0 and overwrite \ref RAIL_ConvertDbmToRaw() to /// always return 255. /// /// The following is example code that shows how to initialize your PA @@ -2668,14 +2748,13 @@ RAIL_Status_t RAIL_EnableCacheSynthCal(RAIL_Handle_t railHandle, bool enable); /// // Picks a dBm power to use: 100 deci-dBm = 10 dBm. See docs on RAIL_TxPower_t. /// RAIL_TxPower_t power = 100; /// -/// // Gets the config written by RAIL_ConfigTxPower to confirm what was actually set. +/// // Gets the config written by RAIL_ConfigTxPower() to confirm what was actually set. /// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); /// -/// // RAIL_ConvertDbmToRaw is the default weak version, +/// // RAIL_ConvertDbmToRaw() is the default weak version, /// // or the customer version, if overwritten. -/// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, -/// txPowerConfig.mode, -/// power); +/// RAIL_TxPowerLevel_t powerLevel +/// = RAIL_ConvertDbmToRaw(railHandle, txPowerConfig.mode, power); /// /// // Writes the result of the conversion to the PA power registers in terms /// // of raw power levels. @@ -2683,9 +2762,9 @@ RAIL_Status_t RAIL_EnableCacheSynthCal(RAIL_Handle_t railHandle, bool enable); /// @endcode /// /// @note All lines following "RAIL_TxPower_t power = 100;" can be -/// replaced with the provided utility function, \ref RAIL_SetTxPowerDbm. +/// replaced with the provided utility function, \ref RAIL_SetTxPowerDbm(). /// However, the full example here was provided for clarity. See the -/// documentation on \ref RAIL_SetTxPowerDbm for more details. +/// documentation on \ref RAIL_SetTxPowerDbm() for more details. /// /// @{ @@ -2693,22 +2772,22 @@ RAIL_Status_t RAIL_EnableCacheSynthCal(RAIL_Handle_t railHandle, bool enable); * Initialize TX power settings. * * @param[in] railHandle A RAIL instance handle. - * @param[in] config A pointer to apower config with the desired initial settings + * @param[in] config A pointer to a power config with the desired initial settings * for the TX amplifier. * @return Status code indicating success of the function call. * * These settings include the selection between the multiple TX amplifiers, * voltage supplied to the TX power amplifier, and ramp times. This must - * be called before any transmit occurs or \ref RAIL_SetTxPower is called. + * be called before any transmit occurs or \ref RAIL_SetTxPower() is called. * While this function should always be called during initialization, * it can also be called any time if these settings need to change to adapt * to a different application/protocol. This API also resets TX power to - * \ref RAIL_TX_POWER_LEVEL_INVALID, so \ref RAIL_SetTxPower must be called + * \ref RAIL_TX_POWER_LEVEL_INVALID, so \ref RAIL_SetTxPower() must be called * afterwards. * * At times, certain combinations of configurations cannot be achieved. * This API attempts to get as close as possible to the requested settings. The - * following "RAIL_Get..." API can be used to determine what values were set. A + * following "RAIL_GetTxPower..." API can be used to determine what values were set. A * change in \ref RAIL_TxPowerConfig_t::rampTime may affect the minimum timings * that can be achieved in \ref RAIL_StateTiming_t::idleToTx and * \ref RAIL_StateTiming_t::rxToTx. Call \ref RAIL_SetStateTiming() again to @@ -2721,15 +2800,14 @@ RAIL_Status_t RAIL_ConfigTxPower(RAIL_Handle_t railHandle, * Get the TX power settings currently used in the amplifier. * * @param[in] railHandle A RAIL instance handle. - * @param[out] config A pointer to memory allocated to hold the current TxPower - * configuration structure. A NULL configuration will produce undefined - * behavior. + * @param[out] config A non-NULL pointer to a \ref + * RAIL_TxPowerConfig_t structure filled in by the function. * @return Status code indicating success of the function call. * * Note that this API does not return the current TX power, which is separately - * managed by the \ref RAIL_GetTxPower / \ref RAIL_SetTxPower APIs. Use this API + * managed by the \ref RAIL_GetTxPower() / \ref RAIL_SetTxPower() APIs. Use this API * to determine which values were set as a result of - * \ref RAIL_ConfigTxPower. + * \ref RAIL_ConfigTxPower(). */ RAIL_Status_t RAIL_GetTxPowerConfig(RAIL_Handle_t railHandle, RAIL_TxPowerConfig_t *config); @@ -2743,19 +2821,19 @@ RAIL_Status_t RAIL_GetTxPowerConfig(RAIL_Handle_t railHandle, * @return Status code indicating success of the function call. * * To convert between decibels and the integer values that the - * registers take, call \ref RAIL_ConvertDbmToRaw. + * registers take, call \ref RAIL_ConvertDbmToRaw(). * A weak version of this function, which works well with our boards is provided. However, * customers using a custom board need to characterize * radio operation on that board and override the function to convert * appropriately from the desired dB values to raw integer values. * - * Depending on the configuration used in \ref RAIL_ConfigTxPower, not all + * Depending on the configuration used in \ref RAIL_ConfigTxPower(), not all * power levels are achievable. This API will get as close as possible to - * the desired power without exceeding it, and calling \ref RAIL_GetTxPower is + * the desired power without exceeding it, and calling \ref RAIL_GetTxPower() is * the only way to know the exact value written. * * Calling this function before configuring the PA (i.e., before a successful - * call to \ref RAIL_ConfigTxPower) will return an error. + * call to \ref RAIL_ConfigTxPower()) will return an error. */ RAIL_Status_t RAIL_SetTxPower(RAIL_Handle_t railHandle, RAIL_TxPowerLevel_t powerLevel); @@ -2767,16 +2845,16 @@ RAIL_Status_t RAIL_SetTxPower(RAIL_Handle_t railHandle, * @return The radio-specific \ref RAIL_TxPowerLevel_t value of the current * transmit power. * - * This API returns the raw value that was set by \ref RAIL_SetTxPower. - * A weak version of \ref RAIL_ConvertRawToDbm that works + * This API returns the raw value that was set by \ref RAIL_SetTxPower(). + * A weak version of \ref RAIL_ConvertRawToDbm() that works * with Silicon Labs boards to convert the raw values into actual output dBm values is provided. * However, customers using a custom board need to * re-characterize the relationship between raw and decibel values and rewrite * the provided function. * * Calling this function before configuring the PA (i.e., before a successful - * call to \ref RAIL_ConfigTxPower) will return an error - * (RAIL_TX_POWER_LEVEL_INVALID). + * call to \ref RAIL_ConfigTxPower()) will return error \ref + * RAIL_TX_POWER_LEVEL_INVALID. */ RAIL_TxPowerLevel_t RAIL_GetTxPower(RAIL_Handle_t railHandle); @@ -2794,8 +2872,8 @@ RAIL_TxPowerLevel_t RAIL_GetTxPower(RAIL_Handle_t railHandle); * to provide accurate values for our boards. For a * custom board, the relationship between what is written to the TX amplifier * and the actual output power should be re-characterized and implemented in an - * overriding version of \ref RAIL_ConvertRawToDbm. For minimum code size and - * best speed, use only raw values with the TxPower API and override this + * overriding version of \ref RAIL_ConvertRawToDbm(). For minimum code size and + * best speed, use only raw values with the \ref RAIL_SetTxPower() API and override this * function with a smaller function. In the weak version provided with the RAIL * library, railHandle is only used to indicate to the user from where the * function was called, so it is okay to use either a real protocol handle, or one @@ -2814,16 +2892,16 @@ RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in] mode PA mode for which to do the conversion. - * @param[in] power Desired dBm values in units of deci-dBm. + * @param[in] power Desired dBm value in units of deci-dBm. * @return deci-dBm value converted to a raw - * integer value that can be used directly with \ref RAIL_SetTxPower. + * integer value that can be used directly with \ref RAIL_SetTxPower(). * * A weak version of this function is provided that is tuned * to provide accurate values for our boards. For a * custom board, the relationship between what is written to the TX amplifier * and the actual output power should be characterized and implemented in an - * overriding version of \ref RAIL_ConvertDbmToRaw. For minimum code size and - * best speed use only raw values with the TxPower API and override this + * overriding version of \ref RAIL_ConvertDbmToRaw(). For minimum code size and + * best speed use only raw values with the \ref RAIL_SetTxPower() API and override this * function with a smaller function. In the weak version provided with the RAIL * library, railHandle is only used to indicate to the user from where the * function was called, so it is okay to use either a real protocol handle, or one @@ -2858,11 +2936,10 @@ RAIL_Status_t RAIL_VerifyTxPowerCurves(const struct RAIL_TxPowerCurvesConfigAlt /// RAIL_TxPower_t power = 100; // 100 deci-dBm, 10 dBm /// RAIL_TxPowerConfig_t txPowerConfig; /// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); -/// // RAIL_ConvertDbmToRaw will be the weak version provided by Silicon Labs +/// // RAIL_ConvertDbmToRaw() will be the weak version provided by Silicon Labs /// // by default, or the customer version, if overwritten. -/// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, -/// txPowerConfig.mode, -/// power); +/// RAIL_TxPowerLevel_t powerLevel +/// = RAIL_ConvertDbmToRaw(railHandle, txPowerConfig.mode, power); /// RAIL_SetTxPower(railHandle, powerLevel); /// @endcode /// @@ -2883,11 +2960,10 @@ RAIL_Status_t RAIL_SetTxPowerDbm(RAIL_Handle_t railHandle, /// RAIL_TxPowerLevel_t powerLevel = RAIL_GetTxPower(railHandle); /// RAIL_TxPowerConfig_t txPowerConfig; /// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); -/// // RAIL_ConvertRawToDbm will be the weak version provided by Silicon Labs +/// // RAIL_ConvertRawToDbm() will be the weak version provided by Silicon Labs /// // by default, or the customer version, if overwritten. -/// RAIL_TxPower_t power = RAIL_ConvertRawToDbm(railHandle, -/// txPowerConfig.mode, -/// powerLevel); +/// RAIL_TxPower_t power +/// = RAIL_ConvertRawToDbm(railHandle, txPowerConfig.mode, powerLevel); /// return power; /// @endcode /// @@ -2950,17 +3026,17 @@ RAIL_PaPowerSetting_t RAIL_GetPaPowerSetting(RAIL_Handle_t railHandle); * @return Status code indicating success of the function call. * * While PA Automode is enabled, the PA will be chosen and set automatically whenever - * \ref RAIL_SetTxPowerDbm is called or whenever powers are coerced automatically, + * \ref RAIL_SetTxPowerDbm() is called or whenever powers are coerced automatically, * internally to the RAIL library during a channel change. While PA Auto Mode - * is enabled, users cannot call \ref RAIL_ConfigTxPower or - * \ref RAIL_SetTxPower. When entering auto mode, \ref RAIL_SetTxPowerDbm must + * is enabled, users cannot call \ref RAIL_ConfigTxPower() or + * \ref RAIL_SetTxPower(). When entering auto mode, \ref RAIL_SetTxPowerDbm() must * be called to specify the desired power. When leaving auto mode, - * \ref RAIL_ConfigTxPower as well as one of \ref RAIL_SetTxPower or - * \ref RAIL_SetTxPowerDbm must be called to re-specify the desired PA and power + * \ref RAIL_ConfigTxPower() as well as one of \ref RAIL_SetTxPower() or + * \ref RAIL_SetTxPowerDbm() must be called to re-specify the desired PA and power * level combination. * * @note: Power conversion curves must be initialized before calling this function. - * That is, \ref RAIL_ConvertDbmToRaw and \ref RAIL_ConvertRawToDbm most both be + * That is, \ref RAIL_ConvertDbmToRaw() and \ref RAIL_ConvertRawToDbm() most both be * able to operate properly to ensure that PA Auto Mode functions correctly. * See the PA Conversions plugin or AN1127 for more details. */ @@ -2987,7 +3063,7 @@ bool RAIL_IsPaAutoModeEnabled(RAIL_Handle_t railHandle); * returns will be applied to the radio. * @param[in] chCfgEntry A pointer to a \ref RAIL_ChannelConfigEntry_t. * While switching channels, it will be the entry RAIL is switch *to*, - * during a call to \ref RAIL_SetTxPowerDbm, it will be the entry + * during a call to \ref RAIL_SetTxPowerDbm(), it will be the entry * RAIL is *already on*. Can be NULL if a channel configuration * was not set or no valid channels are present. * @return Status code indicating success of the function call. If this @@ -2998,9 +3074,9 @@ bool RAIL_IsPaAutoModeEnabled(RAIL_Handle_t railHandle); * will be applied to the PA hardware and used for transmits. * * @note The mode and power level provided by this function depends on the - * RAIL_PaAutoModeConfig provided for the radio. The RAIL_PaAutoModeConfig - * definition for a radio should tend to all the bands supported by the radio - * and cover the full range of power to find a valid entry for requested power + * \ref RAIL_PaAutoModeConfig provided for the radio. The \ref RAIL_PaAutoModeConfig + * definition for a radio should tend to cover all the bands supported by the radio + * and cover the full range of power in each to find a valid entry for requested power * for a specific band. */ RAIL_Status_t RAILCb_PaAutoModeDecision(RAIL_Handle_t railHandle, @@ -3210,6 +3286,8 @@ RAIL_Status_t RAIL_StartCcaLbtTx(RAIL_Handle_t railHandle, * If changing channels, the channel is changed immediately and any ongoing * packet reception is aborted. * + * Returns an error if a scheduled RX is still in progress. + * * In multiprotocol, ensure that the radio is properly yielded after this * operation completes. See \ref rail_radio_scheduler_yield for more details. */ @@ -3251,6 +3329,8 @@ RAIL_Status_t RAIL_StartScheduledCcaCsmaTx(RAIL_Handle_t railHandle, * If changing channels, the channel is changed immediately and any ongoing * packet reception is aborted. * + * Returns an error if a scheduled RX is still in progress. + * * In multiprotocol, ensure that the radio is properly yielded after this * operation completes. See \ref rail_radio_scheduler_yield for more details. */ @@ -3273,7 +3353,7 @@ RAIL_Status_t RAIL_StartScheduledCcaLbtTx(RAIL_Handle_t railHandle, * operation to stop. * * @note When mode includes \ref RAIL_STOP_MODE_ACTIVE, this can also stop - * an active auto-ACK transmit. When an active transmit is stopped, \ref + * an active Auto-Ack transmit. When an active transmit is stopped, \ref * RAIL_EVENT_TX_ABORTED or \ref RAIL_EVENT_TXACK_ABORTED should occur. * When mode includes \ref RAIL_STOP_MODE_PENDING this can also stop * a \ref RAIL_TX_OPTION_CCA_ONLY transmit operation. When a pending @@ -3288,7 +3368,7 @@ RAIL_Status_t RAIL_StopTx(RAIL_Handle_t railHandle, RAIL_StopMode_t mode); * @param[in] ccaThresholdDbm The CCA threshold in dBm. * @return Status code indicating success of the function call. * - * Unlike RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(), which can cause a + * Unlike \ref RAIL_StartCcaCsmaTx() or \ref RAIL_StartCcaLbtTx(), which can cause a * transmit, this function only modifies the CCA threshold. A possible * use case for this function involves setting the CCA threshold to invalid RSSI * of -128 which blocks transmission by preventing clear channel assessments @@ -3305,7 +3385,7 @@ RAIL_Status_t RAIL_SetCcaThreshold(RAIL_Handle_t railHandle, * RAIL_TxPacketDetails_t corresponding to the transmit event. * The isAck and timeSent fields totalPacketBytes and timePosition * must be initialized prior to each call: - * - isAck true to obtain details about the most recent ACK transmit, + * - isAck true to obtain details about the most recent Ack transmit, * false to obtain details about the most recent app-initiated transmit. * - totalPacketBytes with the total number of bytes of the transmitted * packet for RAIL to use when calculating the specified timestamp. @@ -3331,7 +3411,7 @@ RAIL_Status_t RAIL_GetTxPacketDetails(RAIL_Handle_t railHandle, * Get detailed information about the last packet transmitted. * * @param[in] railHandle A RAIL instance handle. - * @param[in] isAck true to obtain details about the most recent ACK transmit. + * @param[in] isAck true to obtain details about the most recent Ack transmit. * false to obtain details about the most recent app-initiated transmit. * @param[out] pPacketTime An application-provided non-NULL pointer to store a * RAIL_Time_t corresponding to the transmit event. This will be populated @@ -3360,16 +3440,16 @@ RAIL_Status_t RAIL_GetTxPacketDetailsAlt(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails An application-provided pointer to store - * RAIL_TxPacketDetails_t corresponding to the transmit event. + * \ref RAIL_TxPacketDetails_t corresponding to the transmit event. * The isAck field must be initialized prior to each call: - * - isAck true to obtain details about the most recent ACK transmit, + * - isAck true to obtain details about the most recent Ack transmit, * false to obtain details about the most recent app-initiated transmit. * The timeSent field packetTime will be populated with a timestamp * corresponding to a default location in the packet. The timeSent field * timePosition will be populated with a \ref RAIL_PacketTimePosition_t value * specifying that default packet location. - * Call \ref RAIL_GetTxTimePreambleStartAlt, - * \ref RAIL_GetTxTimeSyncWordEndAlt, or \ref RAIL_GetTxTimeFrameEndAlt to + * Call \ref RAIL_GetTxTimePreambleStartAlt(), + * \ref RAIL_GetTxTimeSyncWordEndAlt(), or \ref RAIL_GetTxTimeFrameEndAlt() to * adjust the timestamp for different locations in the packet. * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, * or an appropriate error code otherwise. @@ -3393,7 +3473,7 @@ RAIL_Status_t RAIL_GetTxPacketDetailsAlt2(RAIL_Handle_t railHandle, * and Sync word(s), including CRC bytes. Pass \ref RAIL_TX_STARTED_BYTES * to retrieve the start-of-normal-TX timestamp (see below). * @param[in,out] pPacketTime This points to the \ref RAIL_Time_t returned - * from a previous call to \ref RAIL_GetTxPacketDetailsAlt for this same + * from a previous call to \ref RAIL_GetTxPacketDetailsAlt() for this same * packet. That time will be updated with the time that the preamble for * this packet started on air. * Must be non-NULL. @@ -3405,7 +3485,7 @@ RAIL_Status_t RAIL_GetTxPacketDetailsAlt2(RAIL_Handle_t railHandle, * \ref RAIL_GetTxPacketDetailsAlt() is called. * * This function may be called when handling the \ref RAIL_EVENT_TX_STARTED - * event to retrieve that event's start-of-normal-TX timestamp. (ACK + * event to retrieve that event's start-of-normal-TX timestamp. (Ack * transmits currently have no equivalent event or associated timestamp.) * In this case, totalPacketBytes must be \ref RAIL_TX_STARTED_BYTES, and * pPacketTime is an output-only parameter filled in with that time (so no @@ -3424,7 +3504,7 @@ RAIL_Status_t RAIL_GetTxTimePreambleStart(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails A non-NULL pointer to the details that were returned from - * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. + * a previous call to \ref RAIL_GetTxPacketDetailsAlt2() for this same packet. * The application must update the timeSent field totalPacketBytes to be * the total number of bytes of the sent packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes @@ -3440,7 +3520,7 @@ RAIL_Status_t RAIL_GetTxTimePreambleStart(RAIL_Handle_t railHandle, * \ref RAIL_GetTxPacketDetailsAlt2() is called. * * This function may be called when handling the \ref RAIL_EVENT_TX_STARTED - * event to retrieve that event's start-of-normal-TX timestamp. (ACK + * event to retrieve that event's start-of-normal-TX timestamp. (Ack * transmits currently have no equivalent event or associated timestamp.) * In this case, the timeSent field totalPacketBytes must be * \ref RAIL_TX_STARTED_BYTES, and the timeSent field packetTime is an @@ -3460,7 +3540,7 @@ RAIL_Status_t RAIL_GetTxTimePreambleStartAlt(RAIL_Handle_t railHandle, * should account for all bytes transmitted over the air after the Preamble * and Sync word(s), including CRC bytes. * @param[in,out] pPacketTime The time that was returned in a - * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt + * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt() * for this same packet. After this function, the time at that location will * be updated with the time that the sync word for this packet finished on * air. Must be non-NULL. @@ -3480,7 +3560,7 @@ RAIL_Status_t RAIL_GetTxTimeSyncWordEnd(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails A non-NULL pointer to the details that were returned from - * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. + * a previous call to \ref RAIL_GetTxPacketDetailsAlt2() for this same packet. * The application must update the timeSent field totalPacketBytes to be * the total number of bytes of the sent packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes @@ -3507,7 +3587,7 @@ RAIL_Status_t RAIL_GetTxTimeSyncWordEndAlt(RAIL_Handle_t railHandle, * should account for all bytes transmitted over the air after the Preamble * and Sync word(s), including CRC bytes. * @param[in,out] pPacketTime The time that was returned in a - * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt + * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt() * for this same packet. After this function, the time at that location will * be updated with the time that this packet finished on air. Must be * non-NULL. @@ -3527,7 +3607,7 @@ RAIL_Status_t RAIL_GetTxTimeFrameEnd(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails A non-NULL pointer to the details that were returned from - * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. + * a previous call to \ref RAIL_GetTxPacketDetailsAlt2() for this same packet. * The application must update the timeSent field totalPacketBytes to be * the total number of bytes of the sent packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes @@ -3558,7 +3638,7 @@ RAIL_Status_t RAIL_GetTxTimeFrameEndAlt(RAIL_Handle_t railHandle, * events. * * @note This function does not affect a transmit that has already started. - * To stop an already-started transmission, use RAIL_Idle() with + * To stop an already-started transmission, use \ref RAIL_Idle() with * \ref RAIL_IDLE_ABORT. */ RAIL_Status_t RAIL_EnableTxHoldOff(RAIL_Handle_t railHandle, bool enable); @@ -3569,7 +3649,7 @@ RAIL_Status_t RAIL_EnableTxHoldOff(RAIL_Handle_t railHandle, bool enable); * @param[in] railHandle A RAIL instance handle. * @return true if TX hold off is enabled, false otherwise. * - * TX hold off can be enabled/disabled using \ref RAIL_EnableTxHoldOff. + * TX hold off can be enabled/disabled using \ref RAIL_EnableTxHoldOff(). * Attempting to transmit with the TX hold off enabled will block the * transmission and result in \ref RAIL_EVENT_TX_BLOCKED * and/or \ref RAIL_EVENT_TXACK_BLOCKED events. @@ -3628,11 +3708,10 @@ RAIL_Status_t RAIL_ConfigRxOptions(RAIL_Handle_t railHandle, * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. * - * This function must be called before \ref RAIL_ConfigChannels to allow configurations - * using a frame type based length setup. In RAIL 2.x, it is called by default - * in the \ref RAILCb_ConfigFrameTypeLength API which can be overridden to save - * code space. In future versions, the user may be required to call this API - * explicitly. + * This function must be called before \ref RAIL_ConfigChannels() to allow configurations + * using a frame type based length setup. It is called by default + * in the \ref RAILCb_ConfigFrameTypeLength() API which can be overridden to save + * code space. */ RAIL_Status_t RAIL_IncludeFrameTypeLength(RAIL_Handle_t railHandle); @@ -3686,7 +3765,7 @@ RAIL_Status_t RAIL_StartRx(RAIL_Handle_t railHandle, * at the specified time and end at the given end time. If you do not specify * an end time, you may call this API later with an end time as long as you set * the start time to disabled. You can also terminate the receive - * operation immediately using the RAIL_Idle() function. Note that relative + * operation immediately using the \ref RAIL_Idle() function. Note that relative * end times are always relative to the start unless no start time is * specified. If changing channels, the channel is changed immediately and * will abort any ongoing packet transmission or reception. @@ -3702,27 +3781,26 @@ RAIL_Status_t RAIL_ScheduleRx(RAIL_Handle_t railHandle, const RAIL_SchedulerInfo_t *schedulerInfo); /** - * Enable automatic LNA bypass for external FEM. + * Enable automatic PRS LNA bypass for external FEM. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @param[in] enable Enable/Disable automatic LNA bypass. - * @param[in] pAutoLnaBypassConfig A pointer to an automatic LNA bypass + * @param[in] enable Enable/Disable automatic PRS LNA bypass. + * @param[in] pPrsLnaBypassConfig A pointer to an automatic PRS LNA bypass * configuration structure. It must be non-NULL to enable the feature. * @return Status code indicating success of the function call. * - * If automatic LNA bypass is enabled on chip that supports the feature - * (\ref RAIL_SUPPORTS_AUTO_LNA_BYPASS), GPIO is used to bypass external - * FEM LNA when the received power exceed a threshold. The bypass is turned off - * after frame reception or after timeout if no frame has been detected. - * - * @note As this automatic LNA bypass relies on GPIO and RAIL is meant to run - * in TrustZone non-secure world, the feature is not supported if GPIO is - * configured as secure peripheral. + * If automatic PRS LNA bypass is enabled on chip that supports the feature + * (\ref RAIL_SUPPORTS_PRS_LNA_BYPASS), a level is generated on a PRS channel + * when the received power exceed a threshold. It is turned off after frame + * reception or after timeout if no frame has been detected. * + * @warning As this function relies on PRS access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if PRS is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ -RAIL_Status_t RAIL_EnableAutoLnaBypass(RAIL_Handle_t railHandle, - bool enable, - const RAIL_AutoLnaBypassConfig_t *pAutoLnaBypassConfig); +RAIL_Status_t RAIL_EnablePrsLnaBypass(RAIL_Handle_t railHandle, + bool enable, + const RAIL_PrsLnaBypassConfig_t *pPrsLnaBypassConfig); /****************************************************************************** * Packet Information (RX) @@ -3788,7 +3866,7 @@ RAIL_Status_t RAIL_EnableAutoLnaBypass(RAIL_Handle_t railHandle, * integrity checking. Also note that the packet could be aborted, canceled, or * fail momentarily, invalidating its data in Packet mode. Furthermore, there * is a small chance towards the end of packet reception that the filled-in - * RAIL_RxPacketInfo_t could include not only packet data received so far, + * \ref RAIL_RxPacketInfo_t could include not only packet data received so far, * but also some raw radio-appended info detail bytes that RAIL's * packet-completion processing will subsequently deal with. It's up to the * application to know its packet format well enough to avoid confusing such @@ -3821,7 +3899,7 @@ RAIL_RxPacketHandle_t RAIL_GetRxPacketInfo(RAIL_Handle_t railHandle, * it has not yet passed any CRC integrity checking. Also note that the * packet could be aborted, canceled, or fail momentarily, invalidating * its data in Packet mode. Furthermore, there is a small chance towards - * the end of packet reception that the filled-in RAIL_RxPacketInfo_t + * the end of packet reception that the filled-in \ref RAIL_RxPacketInfo_t * could include not only packet data received so far, but also some raw * radio-appended info detail bytes that RAIL's packet-completion * processing will subsequently deal with. It's up to the application to @@ -3846,7 +3924,7 @@ RAIL_Status_t RAIL_GetRxIncomingPacketInfo(RAIL_Handle_t railHandle, * check the validity of its arguments, * so don't pass either as NULL, and don't * pass a pDest pointer to a buffer that's too small for the packet's data. - * @note If only a portion of the packet is needed, use RAIL_PeekRxPacket() + * @note If only a portion of the packet is needed, use \ref RAIL_PeekRxPacket() * instead. */ static inline @@ -3907,8 +3985,8 @@ RAIL_Status_t RAIL_GetRxPacketDetails(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle for the unreleased packet as - * returned from a previous call to RAIL_GetRxPacketInfo() or - * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST + * returned from a previous call to \ref RAIL_GetRxPacketInfo() or + * \ref RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE or * \ref RAIL_RX_PACKET_HANDLE_NEWEST. * @param[out] pPacketDetails A non-NULL application-provided pointer to @@ -3918,8 +3996,8 @@ RAIL_Status_t RAIL_GetRxPacketDetails(RAIL_Handle_t railHandle, * corresponding to a default location in the packet. The timeReceived field * timePosition will be populated with a \ref RAIL_PacketTimePosition_t value * specifying that default packet location. Call - * \ref RAIL_GetRxTimePreambleStart, \ref RAIL_GetRxTimeSyncWordEnd, or - * \ref RAIL_GetRxTimeFrameEnd to adjust that timestamp for different + * \ref RAIL_GetRxTimePreambleStart(), \ref RAIL_GetRxTimeSyncWordEnd(), or + * \ref RAIL_GetRxTimeFrameEnd() to adjust that timestamp for different * locations in the packet. * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, * or an appropriate error code otherwise. @@ -3972,7 +4050,7 @@ RAIL_Status_t RAIL_GetRxTimePreambleStart(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails A non-NULL pointer to the details that were returned from - * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. + * a previous call to \ref RAIL_GetRxPacketDetailsAlt() for this same packet. * The application must update the timeReceived field totalPacketBytes to be * the total number of bytes of the received packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes @@ -3981,9 +4059,6 @@ RAIL_Status_t RAIL_GetRxTimePreambleStart(RAIL_Handle_t railHandle, * updated with the time that the preamble for this packet started on air. * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully * calculated, or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_GetRxTimePreambleStartAlt(RAIL_Handle_t railHandle, RAIL_RxPacketDetails_t *pPacketDetails); @@ -4020,7 +4095,7 @@ RAIL_Status_t RAIL_GetRxTimeSyncWordEnd(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails A non-NULL pointer to the details that were returned from - * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. + * a previous call to \ref RAIL_GetRxPacketDetailsAlt() for this same packet. * The application must update the timeReceived field totalPacketBytes to be * the total number of bytes of the received packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes @@ -4029,9 +4104,6 @@ RAIL_Status_t RAIL_GetRxTimeSyncWordEnd(RAIL_Handle_t railHandle, * updated with the time that the sync word for this packet finished on air. * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully * calculated, or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_GetRxTimeSyncWordEndAlt(RAIL_Handle_t railHandle, RAIL_RxPacketDetails_t *pPacketDetails); @@ -4068,7 +4140,7 @@ RAIL_Status_t RAIL_GetRxTimeFrameEnd(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in,out] pPacketDetails A non-NULL pointer to the details that were returned from - * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. + * a previous call to \ref RAIL_GetRxPacketDetailsAlt() for this same packet. * The application must update the timeReceived field totalPacketBytes to be * the total number of bytes of the received packet for RAIL to use when * calculating the specified timestamp. This should account for all bytes @@ -4077,9 +4149,6 @@ RAIL_Status_t RAIL_GetRxTimeFrameEnd(RAIL_Handle_t railHandle, * updated with the time that the packet finished on air. * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully * calculated, or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. */ RAIL_Status_t RAIL_GetRxTimeFrameEndAlt(RAIL_Handle_t railHandle, RAIL_RxPacketDetails_t *pPacketDetails); @@ -4121,7 +4190,7 @@ RAIL_RxPacketHandle_t RAIL_HoldRxPacket(RAIL_Handle_t railHandle); * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle as returned from a previous - * RAIL_GetRxPacketInfo() or RAIL_HoldRxPacket() call, or + * \ref RAIL_GetRxPacketInfo() or \ref RAIL_HoldRxPacket() call, or * sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST, * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. @@ -4136,8 +4205,8 @@ RAIL_RxPacketHandle_t RAIL_HoldRxPacket(RAIL_Handle_t railHandle); * available packet data (though there is a small chance it might * for a \ref RAIL_RX_PACKET_HANDLE_NEWEST packet at the very end of * still being received). Nor can one peek into already-consumed data read - * by RAIL_ReadRxFifo(). len and offset are relative to the remaining data - * available in the packet, if any was already consumed by RAIL_ReadRxFifo(). + * by \ref RAIL_ReadRxFifo(). len and offset are relative to the remaining data + * available in the packet, if any was already consumed by \ref RAIL_ReadRxFifo(). */ uint16_t RAIL_PeekRxPacket(RAIL_Handle_t railHandle, RAIL_RxPacketHandle_t packetHandle, @@ -4146,18 +4215,18 @@ uint16_t RAIL_PeekRxPacket(RAIL_Handle_t railHandle, uint16_t offset); /** - * Release RAIL's resources for the packet previously held in the receive FIFO + * Release RAIL's resources for a packet previously held in the receive FIFO * and internal receive metadata FIFO. * * This function must be called for any packet previously held via - * RAIL_HoldRxPacket(). It may optionally be called within a + * \ref RAIL_HoldRxPacket(). It may optionally be called within a * callback context to release RAIL resources sooner than at * callback completion time when not holding the packet. * This function can be used in any RX mode. * * @param[in] railHandle A RAIL instance handle. * @param[in] packetHandle A packet handle as returned from a previous - * RAIL_HoldRxPacket() call, or sentinel values + * \ref RAIL_HoldRxPacket() call, or sentinel values * \ref RAIL_RX_PACKET_HANDLE_OLDEST, * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. @@ -4195,7 +4264,7 @@ RAIL_Status_t RAIL_ReleaseRxPacket(RAIL_Handle_t railHandle, * wait is true. * * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID - * immediately if railHandle is not the current active \ref RAIL_Handle_t. + * immediately if railHandle is not the currently active \ref RAIL_Handle_t. * Additionally, 'wait' should never be set 'true' in multiprotocol * as the wait time is not consistent, so scheduling a scheduler * slot cannot be done accurately. Rather if waiting for a valid RSSI is @@ -4225,7 +4294,7 @@ int16_t RAIL_GetRssi(RAIL_Handle_t railHandle, bool wait); * If equal to \ref RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT waits for a valid RSSI * with no maximum timeout. * @return \ref RAIL_RSSI_INVALID if the receiver is disabled and an RSSI - * value can't be obtained. Otherwise, return the RSSI in quarter dBm, dbm*4. + * value can't be obtained. Otherwise, return the RSSI in quarter dBm (dBm*4). * * Gets the current RSSI value. This value represents the current energy of the * channel. It can change rapidly, and will be low if no RF energy is @@ -4245,7 +4314,7 @@ int16_t RAIL_GetRssi(RAIL_Handle_t railHandle, bool wait); * this function can take a significantly longer time when waitTimeout is non-zero. * * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID - * immediately if railHandle is not the current active \ref RAIL_Handle_t. + * immediately if railHandle is not the currently active \ref RAIL_Handle_t. * Additionally, waitTimeout should never be set to a value other than * \ref RAIL_GET_RSSI_NO_WAIT in multiprotocol as the integration between this * feature and the radio scheduler has not been implemented. @@ -4258,7 +4327,7 @@ int16_t RAIL_GetRssi(RAIL_Handle_t railHandle, bool wait); * the RSSI value returned could come from either antenna and vary between antennas. * * @note If RX channel hopping is turned on, do not use this API. - * Instead, see RAIL_GetChannelHoppingRssi(). + * Instead, see \ref RAIL_GetChannelHoppingRssi(). */ int16_t RAIL_GetRssiAlt(RAIL_Handle_t railHandle, RAIL_Time_t waitTimeout); @@ -4280,15 +4349,15 @@ int16_t RAIL_GetRssiAlt(RAIL_Handle_t railHandle, RAIL_Time_t waitTimeout); * In multiprotocol, this is a scheduled event. It will start when railHandle * becomes active. railHandle needs to stay active until the averaging * completes. If the averaging is interrupted, calls to - * \ref RAIL_GetAverageRssi will return \ref RAIL_RSSI_INVALID. + * \ref RAIL_GetAverageRssi() will return \ref RAIL_RSSI_INVALID. * - * Also in multiprotocol, the user is required to call \ref RAIL_YieldRadio + * Also in multiprotocol, the user is required to call \ref RAIL_YieldRadio() * after this event completes (i.e., when \ref RAIL_EVENT_RSSI_AVERAGE_DONE * occurs). * * @note If the radio is idled while RSSI averaging is still in effect, a * \ref RAIL_EVENT_RSSI_AVERAGE_DONE event may not occur and - * \ref RAIL_IsAverageRssiReady may never return true. + * \ref RAIL_IsAverageRssiReady() may never return true. * * @note Completion of RSSI averaging, marked by RAIL event * \ref RAIL_EVENT_RSSI_AVERAGE_DONE, will return the radio to idle state. @@ -4319,8 +4388,8 @@ bool RAIL_IsAverageRssiReady(RAIL_Handle_t railHandle); * @return The RSSI in quarter-dBm (dBm * 4), or \ref RAIL_RSSI_INVALID * if the receiver is disabled or an an RSSI value couldn't be obtained. * - * Gets the hardware RSSI average after issuing RAIL_StartAverageRssi. - * Use after \ref RAIL_StartAverageRssi. + * Gets the hardware RSSI average after issuing \ref RAIL_StartAverageRssi(). + * Use after \ref RAIL_StartAverageRssi(). */ int16_t RAIL_GetAverageRssi(RAIL_Handle_t railHandle); @@ -4347,13 +4416,13 @@ int16_t RAIL_GetAverageRssi(RAIL_Handle_t railHandle); * * @note: Setting a large rssiOffset may still cause the RSSI readings to * underflow. If that happens, the RSSI value returned by - * \ref RAIL_GetRssi, \ref RAIL_GetAverageRssi, - * \ref RAIL_GetChannelHoppingRssi etc. will be \ref RAIL_RSSI_LOWEST + * \ref RAIL_GetRssi(), \ref RAIL_GetAverageRssi(), + * \ref RAIL_GetChannelHoppingRssi() etc. will be \ref RAIL_RSSI_LOWEST. * * @note: During \ref Rx_Channel_Hopping this API will not update the * RSSI offset immediately if channel hopping has already been configured. - * A subsequent call to \ref RAIL_ZWAVE_ConfigRxChannelHopping or - * \ref RAIL_ConfigRxChannelHopping is required for the new RSSI offset to + * A subsequent call to \ref RAIL_ZWAVE_ConfigRxChannelHopping() or + * \ref RAIL_ConfigRxChannelHopping() is required for the new RSSI offset to * take effect. */ RAIL_Status_t RAIL_SetRssiOffset(RAIL_Handle_t railHandle, int8_t rssiOffset); @@ -4380,7 +4449,7 @@ int8_t RAIL_GetRssiOffset(RAIL_Handle_t railHandle); * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD is triggered. * @return Status code indicating success of the function call. * Returns \ref RAIL_STATUS_INVALID_STATE in multiprotocol, - * if the requested \ref RAIL_Handle_t is not active. + * if the requested railHandle is not active. * Returns \ref RAIL_STATUS_INVALID_CALL if called on parts on which this function * is not supported. * @@ -4396,7 +4465,7 @@ int8_t RAIL_GetRssiOffset(RAIL_Handle_t railHandle); * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD occurs, this function needs to be * called again to reactivate the RSSI threshold detection. * - * This function is only available on EFR32 Series 2 Sub-GHz parts EFR32XG23 and EFR32XG25. + * This function is only available on EFR32 Series 2 Sub-GHz parts EFR32xG23 and EFR32xG25. */ RAIL_Status_t RAIL_SetRssiDetectThreshold(RAIL_Handle_t railHandle, int8_t rssiThresholdDbm); @@ -4408,14 +4477,27 @@ RAIL_Status_t RAIL_SetRssiDetectThreshold(RAIL_Handle_t railHandle, * @return The RSSI threshold in dBm corresponding to the railHandle. * * @note: The function returns \ref RAIL_RSSI_INVALID_DBM when - * \ref RAIL_SetRssiDetectThreshold is not supported or disabled. + * \ref RAIL_SetRssiDetectThreshold() is not supported or disabled. * In multiprotocol, the function returns \ref RAIL_RSSI_INVALID_DBM if railHandle * is not active. * - * This function is only available on EFR32 Series 2 Sub-GHz parts EFR32XG23 and EFR32XG25. + * This function is only available on EFR32 Series 2 Sub-GHz parts EFR32xG23 and EFR32xG25. */ int8_t RAIL_GetRssiDetectThreshold(RAIL_Handle_t railHandle); +/** + * Return the RSSI associated with the incoming packet. + * + * @param[in] railHandle A RAIL instance handle. + * @return The RSSI on the incoming packet in dBm, + * or \ref RAIL_RSSI_INVALID_DBM if not available. + * + * This function can only be called from callback context, e.g., + * when handling \ref RAIL_EVENT_RX_FILTER_PASSED or + * \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND. + */ +int8_t RAIL_GetRxIncomingPacketRssi(RAIL_Handle_t railHandle); + /** * Set up a callback function capable of converting a RX packet's LQI value * before being consumed by application code. @@ -4438,22 +4520,22 @@ RAIL_Status_t RAIL_ConvertLqi(RAIL_Handle_t railHandle, * * The address filtering code examines the packet as follows. * - * | `Bytes: 0 - 255` | `0 - 8` | `0 - 255` | `0 - 8` | `Variable` | - * |:----------------:|---------:|----------:|---------:|:----------:| - * | `Data0` | `Field0` | `Data1` | `Field1` | `Data2` | + * | `Bytes: 0 - 255` | `0 - 8` | `0 - 255` | `0 - 8` | `Variable` | + * |:----------------:|----------:|----------:|----------:|:----------:| + * | `Data_0` | `Field_0` | `Data_1` | `Field_1` | `Data_2` | * - * In the above structure, anything listed as DataN is an optional section of - * bytes that RAIL will not process for address filtering. The FieldN segments + * In the above structure, anything listed as Data_# is an optional section of + * bytes that RAIL will not process for address filtering. The Field_# segments * reference specific sections in the packet that will each be interpreted * as an address during address filtering. The application may submit up to * four addresses to attempt to match each field segment and each address may * have a size of up to 8 bytes. To set up address filtering, first configure * the locations and length of the addresses in the packet. Next, configure - * which combinations of matches in Field0 and Field1 should constitute an + * which combinations of matches in Field_0 and Field_1 should constitute an * address match. Last, enter addresses into tables for each field and * enable them. The first two of these are part of the \ref RAIL_AddrConfig_t * structure while the second part is configured at runtime using the - * RAIL_SetAddressFilterAddress() API. A brief description of each + * \ref RAIL_SetAddressFilterAddress() API. A brief description of each * configuration is listed below. * * The offsets and sizes of the fields @@ -4461,27 +4543,27 @@ RAIL_Status_t RAIL_ConvertLqi(RAIL_Handle_t railHandle, * arrays for these values in the sizes and offsets entries in the * \ref RAIL_AddrConfig_t structure. A size of zero indicates that a field is * disabled. The start offset for a field is relative to the previous start - * offset and, if you're using FrameType decoding, the first start offset is + * offset and, if you're using frame type decoding, the first start offset is * relative to the end of the byte containing the frame type. * - * Configuring which combinations of Field0 and Field1 constitute a match is + * Configuring which combinations of Field_0 and Field_1 constitute a match is * the most complex portion of the address filter. The easiest way to think * about this is with a truth table. If you consider each of the four possible * address entries in a field, you can have a match on any one of those or a * match for none of them. This is shown in the 5x5 truth table below where - * Field0 matches are the rows and Field1 matches are the columns. + * Field_0 matches are the rows and Field_1 matches are the columns. * * | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | * |----------------|----------|-----------|-----------|-----------|-----------| - * | __No Match__ | bit0 | bit1 | bit2 | bit3 | bit4 | - * | __Address 0__ | bit5 | bit6 | bit7 | bit8 | bit9 | - * | __Address 1__ | bit10 | bit11 | bit12 | bit13 | bit14 | - * | __Address 2__ | bit15 | bit16 | bit17 | bit18 | bit19 | - * | __Address 3__ | bit20 | bit21 | bit22 | bit23 | bit24 | + * | __No Match__ | bit 0 | bit 1 | bit 2 | bit 3 | bit 4 | + * | __Address 0__ | bit 5 | bit 6 | bit 7 | bit 8 | bit 9 | + * | __Address 1__ | bit 10 | bit 11 | bit 12 | bit 13 | bit 14 | + * | __Address 2__ | bit 15 | bit 16 | bit 17 | bit 18 | bit 19 | + * | __Address 3__ | bit 20 | bit 21 | bit 22 | bit 23 | bit 24 | * * Because this is only 25 bits, it can be represented in one 32-bit integer * where 1 indicates a filter pass and 0 indicates a filter fail. This is the - * matchTable parameter in the configuration structure and is used during + * \ref RAIL_AddrConfig_t::matchTable field and is used during * filtering. For common simple configurations, two defines are provided with * the truth tables as shown below. The first is \ref * ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD, which can be used if only using @@ -4555,7 +4637,7 @@ RAIL_Status_t RAIL_ResetAddressFilter(RAIL_Handle_t railHandle); * @param[in] index Indicates a match entry for this address for a * given field. * @param[in] value A pointer to the address data. This must be at least as - * long as the size specified in RAIL_ConfigAddressFilter(). The first byte, + * long as the size specified in \ref RAIL_ConfigAddressFilter(). The first byte, * value[0], will be compared to the first byte received over the air for this * address field. * @param[in] enable A boolean to indicate whether this address should be @@ -4564,7 +4646,7 @@ RAIL_Status_t RAIL_ResetAddressFilter(RAIL_Handle_t railHandle); * * This function loads the given address into hardware for filtering and * starts filtering if you set the enable parameter to true. Otherwise, - * call RAIL_EnableAddressFilterAddress() to turn it on later. + * call \ref RAIL_EnableAddressFilterAddress() to turn it on later. */ RAIL_Status_t RAIL_SetAddressFilterAddress(RAIL_Handle_t railHandle, uint8_t field, @@ -4578,7 +4660,7 @@ RAIL_Status_t RAIL_SetAddressFilterAddress(RAIL_Handle_t railHandle, * @param[in] railHandle A RAIL instance handle. * @param[in] field Indicates an address field for this address bit mask. * @param[in] bitMask A pointer to the address bitmask. This must be at least - * as long as the size specified in RAIL_ConfigAddressFilter(). The first + * as long as the size specified in \ref RAIL_ConfigAddressFilter(). The first * byte, bitMask[0], will be applied to the first byte received over the air * for this address field. Bits set to 1 in the bit mask indicate which bit * positions in the incoming packet to compare against the stored addresses @@ -4592,7 +4674,7 @@ RAIL_Status_t RAIL_SetAddressFilterAddress(RAIL_Handle_t railHandle, * set to 1 during hardware initialization and when either \ref * RAIL_ConfigAddressFilter() or \ref RAIL_ResetAddressFilter() are called. * - * @note This feature/API is not supported on the EFR32XG21. + * @note This feature/API is not supported on the EFR32xG21. * Use the compile time symbol \ref * RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK or the runtime call \ref * RAIL_SupportsAddrFilterAddressBitMask() to check whether the platform @@ -4622,17 +4704,17 @@ RAIL_Status_t RAIL_EnableAddressFilterAddress(RAIL_Handle_t railHandle, /** @} */ // end of group Receive /****************************************************************************** - * Auto-ACKing + * Auto-Acking *****************************************************************************/ -/// @addtogroup Auto_Ack Auto-ACK -/// @brief APIs for configuring auto-ACK functionality +/// @addtogroup Auto_Ack Auto-Ack +/// @brief APIs for configuring Auto-Ack functionality /// /// These APIs configure the radio for automatic acknowledgment -/// features. Auto-ACK inherently changes how the underlying state machine -/// behaves so users should not modify RAIL_SetRxTransitions() and -/// RAIL_SetTxTransitions() while using auto-ACK features. +/// features. Auto-Ack inherently changes how the underlying state machine +/// behaves so users should not modify \ref RAIL_SetRxTransitions() and +/// \ref RAIL_SetTxTransitions() while using Auto-Ack features. /// @code{.c} -/// // Go to RX after ACK operation. +/// // Go to RX after Ack operation. /// RAIL_AutoAckConfig_t autoAckConfig = { /// .enable = true, /// .ackTimeout = 1000, @@ -4657,99 +4739,101 @@ RAIL_Status_t RAIL_EnableAddressFilterAddress(RAIL_Handle_t railHandle, /// /// The acknowledgment transmits based on the frame format configured via /// the Radio Configurator. For example, if the frame format is using a variable -/// length scheme, the ACK will be sent according to that scheme. If a 10-byte -/// packet is loaded into the ACK, but the variable length field of the ACK -/// payload specifies a length of 5, only 5 bytes will transmit for the ACK. +/// length scheme, the Ack will be sent according to that scheme. If a 10-byte +/// packet is loaded into the Ack, but the variable length field of the Ack +/// payload specifies a length of 5, only 5 bytes will transmit for the Ack. /// The converse is also true, if the frame length is configured to be a fixed -/// 10-byte packet but only 5 bytes are loaded into the ACK buffer, a TX -/// underflow occurs during the ACK transmit. +/// 10-byte packet but only 5 bytes are loaded into the Ack buffer, a TX +/// underflow occurs during the Ack transmit. /// -/// Unlike in non-auto-ACK mode, auto-ACK mode will always return to a single -/// state after all ACK sequences complete, regardless of whether -/// the ACK was successfully received/sent or not. See the documentation +/// Unlike in non-Auto-Ack mode, Auto-Ack mode will always return to a single +/// state after all Ack sequences complete, regardless of whether +/// the Ack was successfully received/sent or not. See the documentation /// of \ref RAIL_ConfigAutoAck() for configuration information. To /// suspend automatic acknowledgment of a series of packets after transmit -/// or receive call RAIL_PauseTxAutoAck() or RAIL_PauseRxAutoAck() respectively -/// with the pause parameter set to true. When auto-ACKing is paused, after +/// or receive call \ref RAIL_PauseTxAutoAck() or \ref RAIL_PauseRxAutoAck() respectively +/// with the pause parameter set to true. When Auto-Acking is paused, after /// receiving or transmitting a packet (regardless of success), the radio -/// transitions to the same state it would use while ACKing. To return to -/// normal state transition logic outside of ACKing, call \ref +/// transitions to the same state it would use while Acking. To return to +/// normal state transition logic outside of Acking, call \ref /// RAIL_ConfigAutoAck() with the \ref RAIL_AutoAckConfig_t::enable field false /// and specify the desired transitions in the \ref /// RAIL_AutoAckConfig_t::rxTransitions and RAIL_AutoAckConfig_t::txTransitions -/// fields. To get out of a paused state and resume auto-ACKing, call -/// RAIL_PauseTxAutoAck() and/or RAIL_PauseRxAutoAck() with the pause parameter +/// fields. To get out of a paused state and resume Auto-Acking, call \ref +/// RAIL_PauseTxAutoAck() and/or \ref RAIL_PauseRxAutoAck() with the pause parameter /// set to false. /// -/// Applications can cancel the transmission of an ACK with +/// Applications can cancel the transmission of an Ack with \ref /// RAIL_CancelAutoAck(). Conversely, applications can control if a transmit -/// operation should wait for an ACK after transmitting by using +/// operation should wait for an Ack after transmitting by using /// the \ref RAIL_TX_OPTION_WAIT_FOR_ACK option. /// -/// When \ref Antenna_Control is used for multiple antennas, ACKs are +/// When \ref Antenna_Control is used for multiple antennas, Acks are /// transmitted on the antenna that was selected to receive the packet -/// being acknowledged. When receiving an ACK, the +/// being acknowledged. When receiving an Ack, the /// \ref RAIL_RxOptions_t antenna options are used just like for any other /// receive. /// -/// If the ACK payload is dynamic, the application must call -/// RAIL_WriteAutoAckFifo() with the appropriate ACK payload after the -/// application processes the receive. RAIL can auto-ACK from the normal -/// transmit buffer if RAIL_UseTxFifoForAutoAck() is called before the radio -/// transmits the ACK. Ensure the transmit buffer contains data loaded by +/// If the Ack payload is dynamic, the application must call \ref +/// RAIL_WriteAutoAckFifo() with the appropriate Ack payload after the +/// application processes the receive. RAIL can Auto-Ack from the normal +/// transmit buffer if \ref RAIL_UseTxFifoForAutoAck() is called before the radio +/// transmits the Ack. Ensure the transmit buffer contains data loaded by \ref /// RAIL_WriteTxFifo(). /// -/// Standard-based protocols that contain auto-ACK functionality are normally +/// Standard-based protocols that contain Auto-Ack functionality are normally /// configured in the protocol-specific configuration function. For example, -/// RAIL_IEEE802154_Init() provides auto-ACK configuration parameters in \ref +/// \ref RAIL_IEEE802154_Init() provides Auto-Ack configuration parameters in \ref /// RAIL_IEEE802154_Config_t and should only be configured through that -/// function. It is not advisable to call both RAIL_IEEE802154_Init() and \ref -/// RAIL_ConfigAutoAck(). However, ACK modification functions are still valid to -/// use with protocol-specific ACKs. To cancel an IEEE 802.15.4 ACK transmit, -/// use RAIL_CancelAutoAck(). +/// function. It is not advisable to call both \ref RAIL_IEEE802154_Init() and \ref +/// RAIL_ConfigAutoAck(). However, Ack modification functions are still valid to +/// use with protocol-specific Acks. To cancel an IEEE 802.15.4 Ack transmit, +/// use \ref RAIL_CancelAutoAck(). /// /// @{ /// Configure and enable automatic acknowledgment. /// /// @param[in] railHandle A RAIL instance handle. -/// @param[in] config A pointer to an Auto-ACK configuration structure. +/// @param[in] config A pointer to an Auto-Ack configuration structure. /// @return Status code indicating success of the function call. /// /// Configures the RAIL state machine for hardware-accelerated automatic -/// acknowledgment. ACK timing parameters are defined in the configuration +/// acknowledgment. Ack timing parameters are defined in the configuration /// structure. /// -/// While auto-ACKing is enabled, do not call the following RAIL functions: -/// - RAIL_SetRxTransitions() -/// - RAIL_SetTxTransitions() -/// Indeed, when auto-ACKing is enabled, only one state transition can be defined +/// While Auto-Acking is enabled, do not call the following RAIL functions: +/// - \ref RAIL_SetRxTransitions() +/// - \ref RAIL_SetTxTransitions() +/// +/// When Auto-Acking is enabled, only one state transition can be defined /// (without notion of success or error). -/// Thus if you are enabling auto-ACK (i.e., "config.enable" field is true) -/// the "error" fields of config.rxTransitions and config.txTransitions are ignored. -/// After all ACK sequences, (success or fail) the state machine will return +/// Thus if you are enabling Auto-Ack (i.e., config->enable field is true) +/// the "error" states of config->rxTransitions and config->txTransitions are ignored. +/// After all Ack sequences, (success or fail) the state machine will return /// the radio to the "success" state, which can be either /// \ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE (returning to /// \ref RAIL_RF_STATE_TX is not supported). -/// On the oppsite, if you are disabling auto-ACK (i.e., "config.enable" field is -/// false), transitions are reconfigured using all fields of config.rxTransitions -/// and config.txTransitions. +/// Alternatively when Auto-Acking is disabled (i.e., config->enable field is +/// false), transitions are reconfigured using all fields of config->rxTransitions +/// and config->txTransitions. When disabling, the "ackTimeout" field isn't used. +/// /// If you need information about the -/// actual success of the ACK sequence, use RAIL events such as -/// \ref RAIL_EVENT_TXACK_PACKET_SENT to make sure an ACK was sent, or -/// \ref RAIL_EVENT_RX_ACK_TIMEOUT to make sure that an ACK was received +/// actual success of the Ack sequence, use RAIL events such as +/// \ref RAIL_EVENT_TXACK_PACKET_SENT to make sure an Ack was sent, or +/// \ref RAIL_EVENT_RX_ACK_TIMEOUT to make sure that an Ack was received /// within the specified timeout. /// /// To set a certain turnaround time (i.e., txToRx and rxToTx /// in \ref RAIL_StateTiming_t), make txToRx lower than -/// desired to ensure you get to RX in time to receive the ACK. +/// desired to ensure you get to RX in time to receive the Ack. /// Silicon Labs recommends setting 10 us lower than desired: /// @code{.c} /// void setAutoAckStateTimings(void) /// { /// RAIL_StateTiming_t timings; /// -/// // User is already in auto-ACK and wants a turnaround of 192 us. +/// // User is already in Auto-Ack and wants a turnaround of 192 us. /// timings.rxToTx = 192; /// timings.txToRx = 192 - 10; /// @@ -4763,43 +4847,37 @@ RAIL_Status_t RAIL_EnableAddressFilterAddress(RAIL_Handle_t railHandle, /// } /// @endcode /// -/// As opposed to an explicit "Disable" API, set the "enable" -/// field of the RAIL_AutoAckConfig_t to false. Then, auto-ACK will be -/// disabled and state transitions will be returned to the values set -/// in \ref RAIL_AutoAckConfig_t. When disabling, the "ackTimeout" field -/// isn't used. -/// -/// @note Auto-ACKing may not be enabled while RX Channel Hopping is enabled, +/// @note Auto-Acking may not be enabled while RX Channel Hopping is enabled, /// or when BLE is enabled. /// RAIL_Status_t RAIL_ConfigAutoAck(RAIL_Handle_t railHandle, const RAIL_AutoAckConfig_t *config); /** - * Return the enable status of the auto-ACK feature. + * Return the enable status of the Auto-Ack feature. * * @param[in] railHandle A RAIL instance handle. - * @return true if auto-ACK is enabled, false if disabled. + * @return true if Auto-Ack is enabled, false if disabled. */ bool RAIL_IsAutoAckEnabled(RAIL_Handle_t railHandle); /** - * Load the auto-ACK buffer with ACK data. + * Load the Auto-Ack buffer with Ack data. * * @param[in] railHandle A RAIL instance handle. - * @param[in] ackData A pointer to ACK data to transmit. + * @param[in] ackData A pointer to Ack data to transmit. * This may be NULL, in which case it's assumed the data has already - * been emplaced into the ACK buffer and RAIL just needs to be told + * been emplaced into the Ack buffer and RAIL just needs to be told * how many bytes are there. Use \ref RAIL_GetAutoAckFifo() to get - * the address of RAIL's auto-ACK buffer in RAM and its size. - * @param[in] ackDataLen The number of bytes in ACK data. + * the address of RAIL's Auto-Ack buffer in RAM and its size. + * @param[in] ackDataLen The number of bytes in Ack data. * @return Status code indicating success of the function call. * - * If the ACK buffer is available for updates, load the ACK buffer with data. + * If the Ack buffer is available for updates, load the Ack buffer with data. * If it is not available, \ref RAIL_STATUS_INVALID_STATE is returned. * If ackDataLen exceeds \ref RAIL_AUTOACK_MAX_LENGTH then * \ref RAIL_STATUS_INVALID_PARAMETER will be returned and nothing is - * written to the ACK buffer (unless ackData is NULL in which case this + * written to the Ack buffer (unless ackData is NULL in which case this * indicates the application has already likely corrupted RAM). */ RAIL_Status_t RAIL_WriteAutoAckFifo(RAIL_Handle_t railHandle, @@ -4807,17 +4885,17 @@ RAIL_Status_t RAIL_WriteAutoAckFifo(RAIL_Handle_t railHandle, uint16_t ackDataLen); /** - * Get the address and size of the auto-ACK transmit buffer for direct access. + * Get the address and size of the Auto-Ack transmit buffer for direct access. * * @param[in] railHandle A RAIL instance handle. * @param[in,out] ackBuffer A pointer to a uint8_t pointer that will be - * updated to the RAM base address of the auto-ACK FIFO buffer. + * updated to the RAM base address of the Auto-Ack FIFO buffer. * @param[in,out] ackBufferBytes A pointer to a uint16_t that will be - * updated to the size of the auto-ACK FIFO buffer, in bytes, + * updated to the size of the Auto-Ack FIFO buffer, in bytes, * currently \ref RAIL_AUTOACK_MAX_LENGTH. * @return Status code indicating success of the function call. * - * Applications can use this to more flexibly write auto-ACK data into + * Applications can use this to more flexibly write Auto-Ack data into * the buffer directly and in pieces, passing NULL ackData parameter to * \ref RAIL_WriteAutoAckFifo() or \ref RAIL_IEEE802154_WriteEnhAck() * to inform RAIL of its final length. @@ -4827,99 +4905,99 @@ RAIL_Status_t RAIL_GetAutoAckFifo(RAIL_Handle_t railHandle, uint16_t *ackBufferBytes); /** - * Pause/resume RX auto-ACK functionality. + * Pause/resume RX Auto-Ack functionality. * * @param[in] railHandle A RAIL instance handle. - * @param[in] pause Pause or resume RX auto-ACKing. + * @param[in] pause Pause or resume RX Auto-Acking. * @return Status code indicating success of the function call. * - * When RX auto-ACKing is paused, the radio transitions to + * When RX Auto-Acking is paused, the radio transitions to * \ref RAIL_AutoAckConfig_t::rxTransitions's * \ref RAIL_StateTransitions_t::success state after receiving a packet and - * does not transmit an ACK. When RX auto-ACK is resumed, the radio resumes - * automatically ACKing every successfully received packet. + * does not transmit an Ack. When RX Auto-Ack is resumed, the radio resumes + * automatically Acking every successfully received packet. */ RAIL_Status_t RAIL_PauseRxAutoAck(RAIL_Handle_t railHandle, bool pause); /** - * Return whether the RX auto-ACK is paused. + * Return whether the RX Auto-Ack is paused. * * @param[in] railHandle A RAIL instance handle. - * @return true if RX auto-ACK is paused, false if not paused. + * @return true if RX Auto-Ack is paused, false if not paused. */ bool RAIL_IsRxAutoAckPaused(RAIL_Handle_t railHandle); /** - * Pause/resume TX auto-ACK functionality. + * Pause/resume TX Auto-Ack functionality. * * @param[in] railHandle A RAIL instance handle. - * @param[in] pause Pause or resume TX auto-ACKing. + * @param[in] pause Pause or resume TX Auto-Acking. * @return Status code indicating success of the function call. * - * When TX auto-ACKing is paused, the radio transitions to + * When TX Auto-Acking is paused, the radio transitions to * \ref RAIL_AutoAckConfig_t::txTransitions's * \ref RAIL_StateTransitions_t::success state after transmitting a packet and - * does not wait for an ACK. When TX auto-ACK is resumed, the radio resumes - * automatically waiting for an ACK after a successful transmit. + * does not wait for an Ack. When TX Auto-Ack is resumed, the radio resumes + * automatically waiting for an Ack after a successful transmit. */ RAIL_Status_t RAIL_PauseTxAutoAck(RAIL_Handle_t railHandle, bool pause); /** - * Return whether the TX auto-ACK is paused. + * Return whether the TX Auto-Ack is paused. * * @param[in] railHandle A RAIL instance handle. - * @return true if TX auto-ACK is paused, false if not paused. + * @return true if TX Auto-Ack is paused, false if not paused. */ bool RAIL_IsTxAutoAckPaused(RAIL_Handle_t railHandle); /** - * Modify the upcoming ACK to use the transmit FIFO. + * Modify the upcoming Ack to use the transmit FIFO. * * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. The call will - * fail if it is too late to modify the outgoing ACK. + * fail if it is too late to modify the outgoing Ack. * * This function allows the application to use the normal transmit FIFO as - * the data source for the upcoming ACK. The ACK modification to use the - * transmit FIFO only applies to one ACK transmission. + * the data source for the upcoming Ack. The Ack modification to use the + * transmit FIFO only applies to one Ack transmission. * * This function only returns true if the following conditions are met: - * - Radio has not already decided to use the ACK buffer AND + * - Radio has not already decided to use the Ack buffer AND * - Radio is either looking for sync, receiving the packet after sync, or in - * the Rx2Tx turnaround before the ACK is sent. + * the \ref RAIL_StateTiming_t::rxToTx turnaround before the Ack is sent. * - * @note The transmit FIFO must not be used for auto-ACK when IEEE 802.15.4, + * @note The transmit FIFO must not be used for Auto-Ack when IEEE 802.15.4, * Z-Wave, or BLE protocols are active. */ RAIL_Status_t RAIL_UseTxFifoForAutoAck(RAIL_Handle_t railHandle); /** - * Cancel the upcoming ACK. + * Cancel the upcoming Ack. * * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. This call will - * fail if it is too late to modify the outgoing ACK. + * fail if it is too late to modify the outgoing Ack. * * This function allows the application to cancel the upcoming automatic * acknowledgment. * * This function only returns true if the following conditions are met: - * - Radio has not already decided to transmit the ACK AND + * - Radio has not already decided to transmit the Ack, and * - Radio is either looking for sync, receiving the packet after sync or in - * the Rx2Tx turnaround before the ACK is sent. + * the \ref RAIL_StateTiming_t::rxToTx turnaround before the Ack is sent. */ RAIL_Status_t RAIL_CancelAutoAck(RAIL_Handle_t railHandle); /** - * Return whether the radio is currently waiting for an ACK. + * Return whether the radio is currently waiting for an Ack. * * @param[in] railHandle A RAIL instance handle. - * @return true if radio is waiting for ACK, false if radio is not waiting for - * an ACK. + * @return true if radio is waiting for Ack, false if radio is not waiting for + * an Ack. * * This function allows the application to query whether the radio is currently - * waiting for an ACK after a transmit operation. + * waiting for an Ack after a transmit operation. */ bool RAIL_IsAutoAckWaitingForAck(RAIL_Handle_t railHandle); @@ -4934,23 +5012,39 @@ bool RAIL_IsAutoAckWaitingForAck(RAIL_Handle_t railHandle); /// /// These APIs calibrate the radio. The RAIL library /// determines which calibrations are necessary. Calibrations can -/// be enabled/disabled with the RAIL_CalMask_t parameter. +/// be enabled/disabled with the \ref RAIL_CalMask_t parameter. /// /// Some calibrations produce values that can be saved and reapplied to /// avoid repeating the calibration process. /// -/// Calibrations can either be run with \ref RAIL_Calibrate, or with the +/// Calibrations can either be run with \ref RAIL_Calibrate(), or with the /// individual chip-specific calibration routines. An example for running code -/// with \ref RAIL_Calibrate looks like the following: +/// with \ref RAIL_Calibrate() looks like the following: /// @code{.c} /// static RAIL_CalValues_t calValues = RAIL_CALVALUES_UNINIT; +/// static volatile bool calibrateRadio = false; /// /// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) /// { /// // Omitting other event handlers /// if (events & RAIL_EVENT_CAL_NEEDED) { -/// // Run all pending calibrations, and save the results -/// RAIL_Calibrate(railHandle, &calValues, RAIL_CAL_ALL_PENDING); +/// calibrateRadio = true; +/// } +/// } +/// +/// void main(void) +/// { +/// // Initialize RAIL ... +/// +/// // Application main loop +/// while (1) { +/// ... +/// if (calibrateRadio) { +/// // Run all pending calibrations, and save the results +/// RAIL_Calibrate(railHandle, &calValues, RAIL_CAL_ALL_PENDING); +/// calibrateRadio = false; +/// } +/// ... /// } /// } /// @endcode @@ -4971,7 +5065,8 @@ bool RAIL_IsAutoAckWaitingForAck(RAIL_Handle_t railHandle); /// }, /// }; /// -/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { +/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) +/// { /// // Omitting other event handlers /// if (events & RAIL_EVENT_CAL_NEEDED) { /// RAIL_CalMask_t pendingCals = RAIL_GetPendingCal(railHandle); @@ -5031,12 +5126,13 @@ RAIL_Status_t RAIL_ConfigCal(RAIL_Handle_t railHandle, * call this function with a calibration values structure containing valid * calibration values after a reset). * + * Silicon Labs recommends calling this function from the application main loop. + * * If multiple protocols are used, this function will make the given railHandle * active, if not already, and perform calibration. If called during a protocol * switch, to perform an IR calibration for the first time, it will * return \ref RAIL_STATUS_INVALID_STATE, in which case the application must - * defer calibration until after the protocol switch is complete. Silicon Labs - * recommends calling this function from the application main loop. + * defer calibration until after the protocol switch is complete. * * @note Instead of this function, consider using the individual calibration-specific * functions. Using the individual functions will allow for better @@ -5083,7 +5179,7 @@ RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle, uint32_t imageRejection); /** - * Apply a given image rejection calibration value. + * Apply given image rejection calibration values. * * @param[in] railHandle A RAIL instance handle. * @param[in] imageRejection A pointer to the image rejection values to apply. @@ -5091,12 +5187,12 @@ RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle, * @return Status code indicating success of the function call. * * Take image rejection calibration values and apply them. These values should be - * determined from a previous run of \ref RAIL_CalibrateIrAlt on the same + * determined from a previous run of \ref RAIL_CalibrateIrAlt() on the same * physical device with the same radio configuration. The imageRejection values * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible. * * @note: To make sure the imageRejection values are stored/configured correctly, - * \ref RAIL_ConfigAntenna should be called before calling this API. + * \ref RAIL_ConfigAntenna() should be called before calling this API. * * If multiple protocols are used, this function will return * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is @@ -5119,15 +5215,15 @@ RAIL_Status_t RAIL_ApplyIrCalibrationAlt(RAIL_Handle_t railHandle, * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running * calibration that adds significant code space when run and can be run with a * separate firmware image on each device to save code space in the - * final image. + * final image. Silicon Labs recommends calling this function from the + * application main loop. * * If multiple protocols are used, this function will make the given railHandle * active, if not already, and perform calibration. If called during a protocol * switch, it will return \ref RAIL_STATUS_INVALID_STATE. In this case, * \ref RAIL_ApplyIrCalibration may be called to apply a previously determined * IR calibration value, or the app must defer calibration until the - * protocol switch is complete. Silicon Labs recommends calling this function - * from the application main loop. + * protocol switch is complete. * * @deprecated Please use \ref RAIL_CalibrateIrAlt instead. */ @@ -5148,9 +5244,11 @@ RAIL_Status_t RAIL_CalibrateIr(RAIL_Handle_t railHandle, * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running * calibration that adds significant code space when run and can be run with a * separate firmware image on each device to save code space in the - * final image. + * final image. Silicon Labs recommends calling this function from the + * application main loop. + * * @note: To make sure the imageRejection values are stored/configured correctly, - * \ref RAIL_ConfigAntenna should be called before calling this API. + * \ref RAIL_ConfigAntenna() should be called before calling this API. * * If multiple protocols are used, this function will return * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is @@ -5222,7 +5320,7 @@ RAIL_Status_t RAIL_CalibrateHFXO(RAIL_Handle_t railHandle, int8_t *crystalPPMErr * on initialization, which can override the default state of the feature. * * @note Call this function before \ref RAIL_ConfigTxPower() if this - * feature is desired. + * feature is not desired. */ void RAIL_EnablePaCal(bool enable); @@ -5256,7 +5354,7 @@ void RAIL_EnablePaCal(bool enable); * within either or both the 2.4 GHz and Sub-GHz bands and trigger an event * if that energy is continuously present for certain durations of time. An * application can check when RF energy is sensed either by enabling the event - * \ref RAIL_EVENT_RF_SENSED, by polling on the \ref RAIL_IsRfSensed API, or + * \ref RAIL_EVENT_RF_SENSED, by polling on the \ref RAIL_IsRfSensed() API, or * by using the cb callback. * * @note After RF energy has been sensed, the RF Sense is automatically @@ -5292,7 +5390,7 @@ RAIL_Time_t RAIL_StartRfSense(RAIL_Handle_t railHandle, /// /// Some radios support Selective RF energy detection (OOK mode) where the /// user can program the radio to look for a particular sync word pattern -/// (1byte - 4bytes) sent using OOK and wake only when that is detected. +/// (1-4 bytes) sent using OOK and wake only when that is detected. /// See chip-specific documentation for more details. /// /// The following code gives an example of how to use RF Sense functionality @@ -5302,6 +5400,8 @@ RAIL_Time_t RAIL_StartRfSense(RAIL_Handle_t railHandle, /// #define NUM_SYNC_WORD_BYTES (2U) /// // Sync word value. /// #define SYNC_WORD (0xB16FU) +/// // Desired RF band +/// RAIL_RfSenseBand_t rfBand = RAIL_RFSENSE_2_4GHZ; /// /// // Configure the transmitting node for sending the wakeup packet. /// RAIL_Idle(railHandle, RAIL_IDLE_ABORT, true); @@ -5309,12 +5409,12 @@ RAIL_Time_t RAIL_StartRfSense(RAIL_Handle_t railHandle, /// RAIL_SetRfSenseSelectiveOokWakeupPayload(railHandle, NUM_SYNC_WORD_BYTES, SYNC_WORD); /// RAIL_StartTx(railHandle, channel, RAIL_TX_OPTIONS_DEFAULT, NULL); /// -/// // Configure the receiving node (EFR32XG22) for RF Sense. +/// // Configure the receiving node (EFR32xG22) for RF Sense. /// RAIL_RfSenseSelectiveOokConfig_t config = { /// .band = rfBand, /// .syncWordNumBytes = NUM_SYNC_WORD_BYTES, /// .syncWord = SYNC_WORD, -/// .cb = &RAILCb_SensedRf +/// .cb = NULL // Use RAIL_EVENT_RF_SENSED event or poll RAIL_IsRfSensed() /// }; /// RAIL_StartSelectiveOokRfSense(railHandle, &config); /// @endcode @@ -5350,7 +5450,7 @@ RAIL_Status_t RAIL_StartSelectiveOokRfSense(RAIL_Handle_t railHandle, * * @note The user must also set up the transmit FIFO, via * \ref RAIL_SetRfSenseSelectiveOokWakeupPayload, post this function call to - * include the first byte as the Preamble Byte, followed by the + * include the first byte as the Preamble byte, followed by the * Sync word (1-4 bytes). * See chip-specific documentation for more details. */ @@ -5367,7 +5467,6 @@ RAIL_Status_t RAIL_ConfigRfSenseSelectiveOokWakeupPhy(RAIL_Handle_t railHandle); * * @note You must call this function after the chip has been set up with the * RF Sense Selective(OOK) PHY, using \ref RAIL_ConfigRfSenseSelectiveOokWakeupPhy. - * */ RAIL_Status_t RAIL_SetRfSenseSelectiveOokWakeupPayload(RAIL_Handle_t railHandle, uint8_t numSyncwordBytes, @@ -5377,10 +5476,10 @@ RAIL_Status_t RAIL_SetRfSenseSelectiveOokWakeupPayload(RAIL_Handle_t railHandle, * Check whether the RF was sensed. * * @param[in] railHandle A RAIL instance handle. - * @return true if RF was sensed since the last call to \ref RAIL_StartRfSense. + * @return true if RF was sensed since the last call to \ref RAIL_StartRfSense(). * false otherwise. * - * This function is useful if \ref RAIL_StartRfSense is called with a NULL + * This function is useful if \ref RAIL_StartRfSense() is called with a NULL * callback. It is generally used after EM4 reboot but can be used any time. */ bool RAIL_IsRfSensed(RAIL_Handle_t railHandle); @@ -5398,23 +5497,24 @@ bool RAIL_IsRfSensed(RAIL_Handle_t railHandle); * * Channel hopping provides a hardware accelerated method for * scanning across multiple channels quickly, as part of a receive protocol. - * While it is possible to call \ref RAIL_StartRx on different channels, + * While it is possible to call \ref RAIL_StartRx() on different channels, * back to back, and listen on many channels sequentially in that way, the * time it takes to switch channels with that method may be too long for some * protocols. This API pre-computes necessary channel change operations * for a given list of channels, so that the radio can move from channel * to channel much faster. Additionally, it leads to more succinct code * as channel changes will be done implicitly, without requiring numerous calls - * to \ref RAIL_StartRx. Currently, while this feature is enabled, the radio + * to \ref RAIL_StartRx(). Currently, while this feature is enabled, the radio * will hop channels in the given sequence each time it enters RX. * Note that RX Channel hopping and EFR32xG25's concurrent mode / collision * detection are mutually exclusive. * - * The channel hopping buffer requires RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL + * The channel hopping buffer requires \ref RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL * number of 32-bit words of overhead per channel, plus 3 words overall plus the - * twice the size of the radioConfigDeltaSubtract of the whole radio configuration, - * plus the twice the sum of the sizes of all the radioConfigDeltaAdd's of - * all the channel hopping channels. + * twice the size of the \ref RAIL_ChannelConfig_t::phyConfigDeltaSubtract + * of the whole radio configuration, plus the twice the sum of the sizes of all + * the \ref RAIL_ChannelConfigEntry_t::phyConfigDeltaAdd in all the channel + * hopping channels. * * The following code gives an example of how to use * the RX Channel Hopping API. @@ -5467,7 +5567,7 @@ bool RAIL_IsRfSensed(RAIL_Handle_t railHandle); * the platform supports this feature. * * @note Calling this function will overwrite any settings configured with - * \ref RAIL_ConfigRxDutyCycle. + * \ref RAIL_ConfigRxDutyCycle(). */ RAIL_Status_t RAIL_ConfigRxChannelHopping(RAIL_Handle_t railHandle, RAIL_RxChannelHoppingConfig_t *config); @@ -5485,28 +5585,29 @@ RAIL_Status_t RAIL_ConfigRxChannelHopping(RAIL_Handle_t railHandle, * Enable or disable Channel Hopping. Additionally, specify whether hopping * should be reset to start from the first channel index, or continue * from the channel last hopped to. The radio should not be on when - * this API is called. \ref RAIL_ConfigRxChannelHopping must be called + * this API is called. \ref RAIL_ConfigRxChannelHopping() must be called * successfully before this API is called. * * @note Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or * the runtime call \ref RAIL_SupportsChannelHopping() to check whether * the platform supports this feature. * - * @note RX Channel Hopping may not be enabled while auto-ACKing is enabled. + * @note RX Channel Hopping may not be enabled while Auto-Acking is enabled. * * @note Calling this function will overwrite any settings configured with - * \ref RAIL_EnableRxDutyCycle. + * \ref RAIL_EnableRxDutyCycle(). */ RAIL_Status_t RAIL_EnableRxChannelHopping(RAIL_Handle_t railHandle, bool enable, bool reset); + /** * Get RSSI in deci-dBm of one channel in the channel hopping sequence, during * channel hopping. * * @param[in] railHandle A RAIL instance handle. * @param[in] channelIndex Index in the channel hopping sequence of the - * channel of interest + * channel of interest. * @return Latest RSSI in deci-dBm for the channel at the specified index. * * @note Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or @@ -5514,15 +5615,15 @@ RAIL_Status_t RAIL_EnableRxChannelHopping(RAIL_Handle_t railHandle, * the platform supports this feature. * * @note In multiprotocol, this function returns \ref RAIL_RSSI_INVALID - * immediately if railHandle is not the current active \ref RAIL_Handle_t. + * immediately if railHandle is not the currently active \ref RAIL_Handle_t. * - * @note \ref RAIL_ConfigRxChannelHopping must be called successfully + * @note \ref RAIL_ConfigRxChannelHopping() must be called successfully * before this API is called. * * @note When the Z-Wave protocol is active, running - * \ref RAIL_GetChannelHoppingRssi() on the 9.6kbps PHY returns the RSSI - * measurement of the 40kpbs PHY. This is because the 9.6kbps PHY has - * trouble with RSSI measurements on EFR32XG2 family of chips. + * \ref RAIL_GetChannelHoppingRssi() on the 9.6 kbps PHY returns the RSSI + * measurement of the 40kpbs PHY. This is because the 9.6 kbps PHY has + * trouble with RSSI measurements on EFR32xG2x family of chips. */ int16_t RAIL_GetChannelHoppingRssi(RAIL_Handle_t railHandle, uint8_t channelIndex); @@ -5626,7 +5727,7 @@ int16_t RAIL_GetChannelHoppingRssi(RAIL_Handle_t railHandle, /// the platform supports this feature. /// /// @note Calling this function will overwrite any settings configured with -/// \ref RAIL_ConfigRxChannelHopping. +/// \ref RAIL_ConfigRxChannelHopping(). /// RAIL_Status_t RAIL_ConfigRxDutyCycle(RAIL_Handle_t railHandle, const RAIL_RxDutyCycleConfig_t *config); @@ -5640,7 +5741,7 @@ RAIL_Status_t RAIL_ConfigRxDutyCycle(RAIL_Handle_t railHandle, * * Enable or disable RX duty cycle mode. After this is called, the radio * will begin duty cycling each time it enters RX, based on the - * configuration passed to \ref RAIL_ConfigRxDutyCycle. This API must not + * configuration passed to \ref RAIL_ConfigRxDutyCycle(). This API must not * be called while the radio is on. * * @note Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or @@ -5648,7 +5749,7 @@ RAIL_Status_t RAIL_ConfigRxDutyCycle(RAIL_Handle_t railHandle, * the platform supports this feature. * * @note Calling this function will overwrite any settings configured with - * \ref RAIL_EnableRxChannelHopping. + * \ref RAIL_EnableRxChannelHopping(). */ RAIL_Status_t RAIL_EnableRxDutyCycle(RAIL_Handle_t railHandle, bool enable); @@ -5701,7 +5802,7 @@ RAIL_Status_t RAIL_GetDefaultRxDutyCycleConfig(RAIL_Handle_t railHandle, * delayed. It is also possible to call the \ref RAIL_Idle() API to * both terminate the operation and idle the radio. In single protocol RAIL * this API does nothing, however, if RAIL Power Manager is initialized, - * calling \ref RAIL_YieldRadio after scheduled TX/RX and instantaneous TX + * calling \ref RAIL_YieldRadio() after scheduled TX/RX and instantaneous TX * completion, is required, to indicate to the Power Manager that the the radio * is no longer busy and can be idled for sleeping. * @@ -5751,7 +5852,7 @@ RAIL_Status_t RAIL_GetSchedulerStatusAlt(RAIL_Handle_t railHandle, * * While the application can use this function however it likes, a major use * case is being able to increase an infinite receive priority while receiving - * a packet. In other words, a given RAIL_Handle_t can maintain a very low + * a packet. In other words, a given \ref RAIL_Handle_t can maintain a very low * priority background receive, but upon getting a * \ref RAIL_EVENT_RX_SYNC1_DETECT_SHIFT or * \ref RAIL_EVENT_RX_SYNC2_DETECT_SHIFT event, the app can call this function @@ -5805,11 +5906,11 @@ void RAIL_SetTransitionTime(RAIL_Time_t transitionTime); * RAIL_DirectModeConfig_t defaultConfig = { * .syncRx = false, * .syncTx = false, - * .doutPort = gpioPortA, + * .doutPort = SL_GPIO_PORT_A, * .doutPin = 5, - * .dinPort = gpioPortA, + * .dinPort = SL_GPIO_PORT_A, * .dinPin = 7, - * .dclkPort = gpioPortA, + * .dclkPort = SL_GPIO_PORT_A, * .dclkPin = 6, * }; * @endcode @@ -5829,14 +5930,16 @@ RAIL_Status_t RAIL_ConfigDirectMode(RAIL_Handle_t railHandle, * See \ref RAIL_EnableDirectModeAlt() for more detailed function * description. * - * @warning New applications should consider using RAIL_EnableDirectModeAlt() for + * @warning New applications should consider using \ref RAIL_EnableDirectModeAlt() for * this functionality. * * @note This feature is only available on certain devices. * \ref RAIL_SupportsDirectMode() can be used to check if a particular * device supports this feature or not. * - * @warning This API is not safe to use in a multiprotocol app. + * @warning As this function relies on GPIO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if GPIO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_EnableDirectMode(RAIL_Handle_t railHandle, bool enable); @@ -5849,10 +5952,10 @@ RAIL_Status_t RAIL_EnableDirectMode(RAIL_Handle_t railHandle, * of the radio. * @param[in] enableDirectRx Enable direct mode for data being received from * the radio. - * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. + * @return \ref RAIL_STATUS_NO_ERROR on success or an error code on failure. * * This API enables or disables the modem and GPIOs for direct mode operation. - * see \ref RAIL_ConfigDirectMode for information on selecting the + * see \ref RAIL_ConfigDirectMode() for information on selecting the * correct hardware configuration. If direct mode is enabled, * packets are output and input directly to the radio via GPIO * and RAIL packet handling is ignored. @@ -5862,6 +5965,10 @@ RAIL_Status_t RAIL_EnableDirectMode(RAIL_Handle_t railHandle, * chip supports this feature or not. * * @warning This API is not safe to use in a multiprotocol app. + * + * @warning As this function relies on GPIO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if GPIO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_EnableDirectModeAlt(RAIL_Handle_t railHandle, bool enableDirectTx, @@ -5895,7 +6002,7 @@ uint32_t RAIL_GetRadioClockFreqHz(RAIL_Handle_t railHandle); * peripheral timing. * @note This API sets CTUNEXIANA and internally * CTUNEXOANA = CTUNEXIANA + delta where delta is set or changed by - * \ref RAIL_SetTuneDelta. The default delta may not be 0 on some devices. + * \ref RAIL_SetTuneDelta(). The default delta may not be 0 on some devices. */ RAIL_Status_t RAIL_SetTune(RAIL_Handle_t railHandle, uint32_t tune); @@ -5918,10 +6025,10 @@ uint32_t RAIL_GetTune(RAIL_Handle_t railHandle); * @param[in] delta A chip-dependent crystal capacitor bank tuning delta. * @return Status code indicating success of the function call. * - * Set the CTUNEXOANA delta for \ref RAIL_SetTune to use: - * CTUNEXOANA = CTUNEXIANA + delta. This function does not change CTUNE values; - * call \ref RAIL_SetTune to put a new delta into effect. - * + * Set the CTUNEXOANA delta for \ref RAIL_SetTune() to use: + * CTUNEXOANA = CTUNEXIANA + delta (subject to field-size limitations). + * This function does not change CTUNE values; + * call \ref RAIL_SetTune() to put a new delta into effect. */ RAIL_Status_t RAIL_SetTuneDelta(RAIL_Handle_t railHandle, int32_t delta); @@ -5931,8 +6038,8 @@ RAIL_Status_t RAIL_SetTuneDelta(RAIL_Handle_t railHandle, int32_t delta); * @param[in] railHandle A RAIL instance handle. * @return A chip-dependent crystal capacitor bank tuning delta. * - * Retrieves the current tuning delta used by \ref RAIL_SetTune. - * @note The default delta if \ref RAIL_SetTuneDelta has never been called + * Retrieves the current tuning delta used by \ref RAIL_SetTune(). + * @note The default delta if \ref RAIL_SetTuneDelta() has never been called * is device-dependent and may not be 0. */ int32_t RAIL_GetTuneDelta(RAIL_Handle_t railHandle); @@ -6023,7 +6130,7 @@ RAIL_Status_t RAIL_StartTxStreamAlt(RAIL_Handle_t railHandle, * @param[in] railHandle A RAIL instance handle. * @return Status code indicating success of the function call. * - * Halts the transmission started by RAIL_StartTxStream(). + * Halts the transmission started by \ref RAIL_StartTxStream(). */ RAIL_Status_t RAIL_StopTxStream(RAIL_Handle_t railHandle); @@ -6052,7 +6159,7 @@ RAIL_Status_t RAIL_StopInfinitePreambleTx(RAIL_Handle_t railHandle); * RAIL to perform radio state verification. This structure must be * allocated in application global read-write memory. RAIL may modify * fields within or referenced by this structure during its operation. - * @param[in] radioConfig A radioConfig (pointer) that is to be used as a + * @param[in] radioConfig A radio configuration (pointer) that is to be used as a * white list for verifying memory contents. * @param[in] cb A callback that notifies the application of a mismatch in * expected vs actual memory contents. A NULL parameter may be passed in @@ -6074,7 +6181,7 @@ RAIL_Status_t RAIL_ConfigVerification(RAIL_Handle_t railHandle, * previously established by \ref RAIL_ConfigVerification(). * @param[in] durationUs The duration (in microseconds) for how long memory * verification should occur before returning to the application. A value of - * RAIL_VERIFY_DURATION_MAX indicates that all memory contents should be + * \ref RAIL_VERIFY_DURATION_MAX indicates that all memory contents should be * verified before returning to the application. * @param[in] restart This flag only has meaning if a previous call of this * function returned \ref RAIL_STATUS_SUSPENDED. By restarting (true), the @@ -6085,7 +6192,7 @@ RAIL_Status_t RAIL_ConfigVerification(RAIL_Handle_t railHandle, * memory locations have been verified. * \ref RAIL_STATUS_SUSPENDED is returned if the provided test duration * expired but the time was not sufficient to verify all memory contents. - * By calling \ref RAIL_Verify again, further verification will commence. + * By calling \ref RAIL_Verify() again, further verification will commence. * \ref RAIL_STATUS_INVALID_PARAMETER is returned if the provided * verifyConfig structure pointer is not configured for use by the active * RAIL handle. @@ -6097,6 +6204,7 @@ RAIL_Status_t RAIL_Verify(RAIL_VerifyConfig_t *configVerify, bool restart); #ifndef DOXYGEN_SHOULD_SKIP_THIS + /** * Enable radio state change interrupt. * @@ -6106,11 +6214,18 @@ RAIL_Status_t RAIL_Verify(RAIL_VerifyConfig_t *configVerify, * \ref RAIL_STATUS_NO_ERROR once the interrupt has been enabled or disabled. * * @note If enabled, state change events are reported through the separate - * RAILCb_RadioStateChanged() callback. + * \ref RAILCb_RadioStateChanged() callback. */ RAIL_Status_t RAIL_EnableRadioStateChanged(RAIL_Handle_t railHandle, bool enable); +/** + * Callback on radio state changes. + * + * @param[in] state The current radio state. + */ +void RAILCb_RadioStateChanged(uint8_t state); + /** * Get the current radio state. * @@ -6136,7 +6251,7 @@ RAIL_RadioStateEfr32_t RAIL_GetRadioStateAlt(RAIL_Handle_t railHandle); * Front End Module at a specific time in a Tx packet. This information allows * optimizations to power configuration, and monitoring FEM performance. * - * @note VDET is only supported with EFR32XG25 devices. + * @note VDET is only supported with EFR32xG25 devices. * @{ */ @@ -6148,8 +6263,12 @@ RAIL_RadioStateEfr32_t RAIL_GetRadioStateAlt(RAIL_Handle_t railHandle); * configuration data for the VDET. * @return \ref RAIL_Status_t * \retval RAIL_STATUS_NO_ERROR - All went well - * \retval RAIL_STATUS_INVALID_STATE - VDET is enabled. Must be disabled first. + * \retval RAIL_STATUS_INVALID_STATE - VDET is enabled. Must be disabled first. * \retval RAIL_STATUS_INVALID_PARAMETER - mode/resolution/delayUs out-of-bounds. + * + * @warning As this function relies on GPIO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if GPIO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_ConfigVdet(RAIL_Handle_t genericRailHandle, const RAIL_VdetConfig_t *config); @@ -6160,11 +6279,12 @@ RAIL_Status_t RAIL_ConfigVdet(RAIL_Handle_t genericRailHandle, * @param[in] genericRailHandle A radio-generic RAIL handle. * @param[out] config A pointer to a \ref RAIL_VdetConfig_t struct that will * return configuration data for the VDET. - * @return RAIL_Status_t + * @return \ref RAIL_Status_t * \retval RAIL_STATUS_NO_ERROR - All went well. */ RAIL_Status_t RAIL_GetVdetConfig(RAIL_Handle_t genericRailHandle, RAIL_VdetConfig_t *config); + /** * Enable the VDET plugin. * @@ -6175,6 +6295,10 @@ RAIL_Status_t RAIL_GetVdetConfig(RAIL_Handle_t genericRailHandle, * \retval RAIL_STATUS_NO_ERROR - All went well, VDET is enabled or disabled. * \retval RAIL_STATUS_INVALID_STATE - VDET has not been configured or VDET was not idle. * VDET is disabled. + * + * @warning As this function relies on HFXO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if HFXO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_EnableVdet(RAIL_Handle_t genericRailHandle, bool enable); @@ -6203,6 +6327,10 @@ bool RAIL_IsVdetEnabled(RAIL_Handle_t genericRailHandle); * \retval RAIL_STATUS_INVALID_PARAMETER - In \ref RAIL_VDET_MODE_IMMEDIATE, resend \ref RAIL_EnableVdet().\n * \retval RAIL_STATUS_SUSPENDED - Blocked by AuxADC contention. Wait until next packet and try reading again. + * + * @warning As this function relies on HFXO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if HFXO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_GetVdet(RAIL_Handle_t genericRailHandle, uint32_t *pVdetMv); @@ -6226,7 +6354,7 @@ RAIL_Status_t RAIL_GetVdet(RAIL_Handle_t genericRailHandle, * @param[in] chipTempConfig A pointer to a \ref RAIL_ChipTempConfig_t that contains * the configuration to be applied. * @return Status code indicating the result of the function call. - * Returns RAIL_STATUS_INVALID_PARAMETER if enable field from \ref RAIL_ChipTempConfig_t + * Returns \ref RAIL_STATUS_INVALID_PARAMETER if enable field from \ref RAIL_ChipTempConfig_t * is set to false when an EFF is present on the board. * * When the temperature threshold minus a precise number of degrees @@ -6248,7 +6376,7 @@ RAIL_Status_t RAIL_ConfigThermalProtection(RAIL_Handle_t genericRailHandle, * * @param[in] genericRailHandle A radio-generic RAIL handle. * @param[out] chipTempConfig A non-NULL pointer to a \ref RAIL_ChipTempConfig_t that will - * by updated with the current configuration. + * be updated with the current configuration. * @return Status code indicating the result of the function call. */ RAIL_Status_t RAIL_GetThermalProtection(RAIL_Handle_t genericRailHandle, @@ -6263,21 +6391,22 @@ RAIL_Status_t RAIL_GetThermalProtection(RAIL_Handle_t genericRailHandle, /** * Get the different temperature measurements in Kelvin done by sequencer or host. - * Values that are not populated yet or incorrect are set to 0. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] tempBuffer The address of the array that will contain temperatures. + * This array must have at least \ref RAIL_TEMP_MEASURE_COUNT entries. + * @param[in] reset true to reset the temperature statistics, false otherwise. + * @return Status code indicating success of the function call. * * Temperatures, in Kelvin, are stored in tempBuffer such as: - * tempBuffer[0] is the chip temperature - * tempBuffer[1] is the minimal chip temperature - * tempBuffer[2] is the maximal chip temperature + * - tempBuffer[0] is the chip temperature + * - tempBuffer[1] is the minimal chip temperature + * - tempBuffer[2] is the maximal chip temperature + * + * Values that are not populated yet or incorrect are set to 0. * * If \ref RAIL_SUPPORTS_HFXO_COMPENSATION * tempBuffer[3] is the HFXO temperature - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] reset Reset the temperature statistics. - * @param[out] tempBuffer The address of the array that will contain temperatures. - * tempBuffer array must be at least \ref RAIL_TEMP_MEASURE_COUNT int16_t. - * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_GetTemperature(RAIL_Handle_t railHandle, int16_t tempBuffer[RAIL_TEMP_MEASURE_COUNT], @@ -6408,7 +6537,7 @@ uint32_t RAIL_GetSchedBufferSize(RAIL_Handle_t genericRailHandle); * However, with the callback, each assert is given a unique error code so that * they can be handled on a more case-by-case basis. For documentation on each * of the errors, see the rail_assert_error_codes.h file. - * RAIL_ASSERT_ERROR_MESSAGES[errorCode] gives the explanation of the error. + * \ref RAIL_ASSERT_ERROR_MESSAGES[errorCode] gives the explanation of the error. * With asserts built into the library, users can choose how to handle each * error inside the callback. * @@ -6446,21 +6575,26 @@ void RAILCb_AssertFailed(RAIL_Handle_t railHandle, * * @param[in] railHandle A radio-generic or real RAIL instance handle. * @return Status code indicating success of the function call. - * Returns RAIL_STATUS_INVALID_STATE if the thermistor is started while the + * Returns \ref RAIL_STATUS_INVALID_STATE if the thermistor is started while the * radio is transmitting. * * To get the thermistor impedance, call the - * function \ref RAIL_GetThermistorImpedance. On platforms having + * function \ref RAIL_GetThermistorImpedance(). On platforms having * \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR, this function reconfigures * GPIO_THMSW_EN_PIN located in GPIO_THMSW_EN_PORT. * To locate this pin, refer to the data sheet or appropriate header files - * of the device. For proper operation, \ref RAIL_Init must be called before + * of the device. For proper operation, \ref RAIL_Init() must be called before * using this function. * * @note When an EFF is attached, this function must not be called during * transmit. * * @warning This API is not safe to use in a multiprotocol app. + * + * @warning As this function relies on EMU, GPIO and HFXO access and RAIL is + * meant to run in TrustZone non-secure world, it is not supported if EMU, + * GPIO or HFXO are configured as secure peripheral and it will return + * \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_StartThermistorMeasurement(RAIL_Handle_t railHandle); @@ -6487,7 +6621,7 @@ RAIL_Status_t RAIL_GetThermistorImpedance(RAIL_Handle_t railHandle, * @param[in] thermistorImpedance Current thermistor impedance measurement in * Ohms. * @param[out] thermistorTemperatureC A non-NULL pointer to an int16_t updated - * with the current thermistor temperature in eighth of Celsius degrees. + * with the current thermistor temperature in eighth of Celsius degrees. * @return Status code indicating success of the function call. * * A version of this function is provided in the \ref rail_util_thermistor @@ -6505,7 +6639,7 @@ RAIL_Status_t RAIL_ConvertThermistorImpedance(RAIL_Handle_t railHandle, * * @param[in] railHandle A radio-generic or real RAIL instance handle. * @param[in] crystalTemperatureC Current crystal temperature, in Celsius. - * @param[out] crystalPPMError A non-NULL pointer to an int16_t updated + * @param[out] crystalPPMError A non-NULL pointer to an int8_t updated * with the current ppm error in ppm units. * @return Status code indicating success of the function call. * @@ -6523,12 +6657,16 @@ RAIL_Status_t RAIL_ComputeHFXOPPMError(RAIL_Handle_t railHandle, * Configure the GPIO for thermistor usage. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @param[in] pHfxoThermistorConfig A pointer to the thermistor configuration + * @param[in] pHfxoThermistorConfig A non-NULL pointer to the thermistor configuration * indicating the GPIO port and pin to use. * @return Status code indicating the result of the function call. * * @note The port and pin that must be passed in \ref RAIL_HFXOThermistorConfig_t * are GPIO_THMSW_EN_PORT and GPIO_THMSW_EN_PIN respectively. + * + * @warning As this function relies on GPIO access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if GPIO is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_ConfigHFXOThermistor(RAIL_Handle_t railHandle, const RAIL_HFXOThermistorConfig_t *pHfxoThermistorConfig); @@ -6537,11 +6675,11 @@ RAIL_Status_t RAIL_ConfigHFXOThermistor(RAIL_Handle_t railHandle, * Configure the temperature parameters for HFXO compensation. * * @param[in] railHandle A RAIL instance handle. - * @param[in] pHfxoCompensationConfig A pointer to HFXO compensation parameters + * @param[in] pHfxoCompensationConfig A non-NULL pointer to HFXO compensation parameters * indicating the temperature variations used to trigger a compensation. * @return Status code indicating the result of the function call. * - * @note This function must be called after \ref RAIL_ConfigHFXOThermistor to succeed. + * @note This function must be called after \ref RAIL_ConfigHFXOThermistor() to succeed. * * In \ref RAIL_HFXOCompensationConfig_t, deltaNominal and * deltaCritical define the temperature variation triggering @@ -6553,8 +6691,8 @@ RAIL_Status_t RAIL_ConfigHFXOThermistor(RAIL_Handle_t railHandle, * are exceeded, RAIL raises * event \ref RAIL_EVENT_CAL_NEEDED with \ref RAIL_CAL_TEMP_HFXO bit set. * The API \ref RAIL_StartThermistorMeasurement() must be called afterwards. - * The latter will raise RAIL_EVENT_THERMISTOR_DONE with calibration bit - * \ref RAIL_CAL_COMPENSATE_HFXO set and RAIL_CalibrateHFXO() must follow. + * The latter will raise \ref RAIL_EVENT_THERMISTOR_DONE with calibration bit + * \ref RAIL_CAL_COMPENSATE_HFXO set and a call to \ref RAIL_CalibrateHFXO() must follow. * * @note Set deltaNominal and deltaCritical to 0 to perform * compensation after each transmit. @@ -6585,8 +6723,244 @@ RAIL_Status_t RAIL_GetHFXOCompensationConfig(RAIL_Handle_t railHandle, * \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR alongside \ref RAIL_SUPPORTS_HFXO_COMPENSATION. */ RAIL_Status_t RAIL_CompensateHFXO(RAIL_Handle_t railHandle, int8_t crystalPPMError); + /** @} */ // end of group External_Thermistor +/****************************************************************************** + * TrustZone + *****************************************************************************/ +/** + * @addtogroup TrustZone + * @brief APIs to use RAIL with TrustZone enabled and peripherals configured + * as secure. + * + * RAIL internally accesses CMU, EMU, GPIO, LDMA, HFXO, PRS and SYSRTC. + * If some of them are configured as secure peripherals, some RAIL code must be + * executed as secure code. To do so, callbacks gathered in + * \ref RAIL_TZ_Config_t must be implemented and passed to RAIL through + * \ref RAIL_TZ_InitNonSecure(). Each callback must do the non-secure/secure + * transition, call \ref RAIL_TZ_CheckPeripheralsSecureStates() and then call + * the corresponding RAIL API from secure world: + * + * | Secure peripheral | Callbacks to implement | + * |-------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| + * | CMU | \ref RAIL_TZ_Config_t::changedDcdcCallback, \ref RAIL_TZ_Config_t::configAntennaGpioCallback, \ref RAIL_TZ_Config_t::radioClockEnableCallback, \ref RAIL_TZ_Config_t::getRadioClockFreqHzCallback, \ref RAIL_TZ_Config_t::rfecaClockEnableCallback, \ref RAIL_TZ_Config_t::rfecaIsClockEnabledCallback | + * | EMU | \ref RAIL_TZ_Config_t::readInternalTemperatureCallback, \ref RAIL_TZ_Config_t::enableSecureRadioIrqsCallback, \ref RAIL_TZ_Config_t::disableSecureRadioIrqsCallback | + * | GPIO | \ref RAIL_TZ_Config_t::configAntennaGpioCallback | + * | LDMA | \ref RAIL_TZ_Config_t::radioPerformM2mLdmaCallback | + * | HFXO | \ref RAIL_TZ_Config_t::configureHfxoCallback | + * + * RAIL internally calls platform functions that access CMU, EMU, GPIO, LDMA + * HFXO and PRS. + * If some of them are configured as secure peripherals, some functions must be + * executed as secure code. To do so, those functions are prepended with weak + * symbols and must be overwritten to do the non-secure/secure transition and + * call the corresponding platform function from secure world: + * + * | Secure peripheral | Platform functions to overwrite | + * |-------------------|-----------------------------------------------------------------------------------------------| + * | CMU | CMU_ClockEnable, EMU_DCDCSetPFMXTimeoutMaxCtrl (DCDC access: SL_TRUSTZONE_PERIPHERAL_DCDC_S) | + * | HFXO | CMU_HFXOCTuneSet, CMU_HFXOCTuneGet, CMU_HFXOCoreBiasCurrentCalibrate | + * | PRS | PRS_SourceAsyncSignalSet, PRS_GetFreeChannel, PRS_ConnectConsumer, PRS_PinOutput, PRS_Combine | + * + * When there is a combination of secure and non-secure peripherals, defines + * must be added in secure application slcp file so non-secure peripherals can + * properly accessed by secure code. Example with only CMU non-secure: + * + * @code{.slcp} + * define: + * - name: SL_TRUSTZONE_PERIPHERAL_CMU_S + * value: 0 + * condition: [trustzone_secure] + * - name: SL_TRUSTZONE_PERIPHERAL_EMU_S + * value: 1 + * condition: [trustzone_secure] + * - name: SL_TRUSTZONE_PERIPHERAL_GPIO_S + * value: 1 + * condition: [trustzone_secure] + * - name: SL_TRUSTZONE_PERIPHERAL_LDMA_S + * value: 1 + * condition: [trustzone_secure] + * - name: SL_TRUSTZONE_PERIPHERAL_HFXO0_S + * value: 1 + * condition: [trustzone_secure] + * - name: SL_TRUSTZONE_PERIPHERAL_PRS_S + * value: 1 + * condition: [trustzone_secure] + * - name: SL_TRUSTZONE_PERIPHERAL_SYSRTC_S + * value: 1 + * condition: [trustzone_secure] + * @endcode + * + * Some RAIL API are not suppoted with EMU, GPIO, LDMA, HFXO, PRS or SYSRTC + * configured secure: + * + * | Secure peripheral | Unsupported RAIL API/features | + * |-------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| + * | EMU | \ref RAIL_StartThermistorMeasurement(), \ref RAIL_InitPowerManager() | + * | GPIO | \ref RAIL_EnableDirectMode(), \ref RAIL_EnableDirectModeAlt(), \ref RAIL_EnablePti(), \ref RAIL_ConfigPti(), \ref RAIL_ConfigHFXOThermistor(), \ref RAIL_StartThermistorMeasurement(), \ref RAIL_ConfigVdet() | + * | LDMA | \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING (\ref RAIL_IEEE802154_ConfigRxChannelSwitching() and \ref RAIL_RX_OPTION_CHANNEL_SWITCHING) | + * | HFXO | \ref RAIL_StartThermistorMeasurement(), \ref RAIL_EnableVdet(), \ref RAIL_GetVdet() | + * | PRS | \ref RAIL_EnablePrsLnaBypass() | + * | SYSRTC | \ref RAIL_ConfigSleep() with \ref RAIL_SleepConfig_t::RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, \ref RAIL_ConfigSleepAlt() with \ref RAIL_SleepConfig_t::RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED | + * + * @{ + */ + +/** + * Init RAIL TrustZone feature for non-secure world + * + * @param[in] pTzConfig A non-NULL pointer to a \ref RAIL_TZ_Config_t + * structure. + * @return Status code indicating success of the function call. + * + * @note This function must only be called from non-secure world (only if + * TrustZone is activated) on platforms having + * \ref RAIL_SUPPORTS_TRUSTZONE_SECURE_PERIPHERALS. It must be called + * before \ref RAIL_Init() and it must be called again with updated + * \ref RAIL_TZ_Config_t if peripherals secure configuration has changed. + */ +RAIL_Status_t RAIL_TZ_InitNonSecure(const RAIL_TZ_Config_t *pTzConfig); + +/** + * Init RAIL TrustZone feature for secure world + * + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world (only if TrustZone + * is activated) on platforms having + * \ref RAIL_SUPPORTS_TRUSTZONE_SECURE_PERIPHERALS. It must be called + * before starting the non-secure application. + */ +RAIL_Status_t RAIL_TZ_InitSecure(void); + +/** + * Check the secure state of peripherals used by RAIL. + * + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world and it must be + * called at the beginning of each RAIL TrustZone callbacks + * (\ref RAIL_TZ_Config_t) secure code to avoid secure fault. + */ +RAIL_Status_t RAIL_TZ_CheckPeripheralsSecureStates(void); + +/** + * Enable radio clocks. + * + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when CMU is + * configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_RadioClockEnable(void); + +/** + * Enable RFECA clocks. + * + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when CMU is + * configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_RfecaClockEnable(void); + +/** + * Indicate whether RFECA clocks are enabled. + * + * @return true if RFECA clocks are enabled; false otherwise + * + * @note This function must only be called from secure world when CMU is + * configured as secure TrustZone peripheral. + * + */ +bool RAIL_TZ_RfecaIsClockEnabled(void); + +/** + * Read the internal temperature. + * + * @param[out] internalTemperatureKelvin A pointer to the internal temperature + * in Kelvin. + * @param[in] enableTemperatureInterrupts Indicate whether temperature + * interrupts are enabled. + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when EMU is + * configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_ReadInternalTemperature(uint16_t *internalTemperatureKelvin, + bool enableTemperatureInterrupts); + +/** + * Enable secure peripheral interrupts needed by the radio. + * + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when EMU is + * configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_EnableSecureRadioIrqs(void); + +/** + * Disable secure peripheral interrupts needed by the radio. + * + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when EMU is + * configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_DisableSecureRadioIrqs(void); + +/** + * Perform ldma transfer for the radio. + * + * @param[in] pDest A pointer to the destination data. + * @param[in] pSrc A pointer to the source data. + * @param[in] numWords Number of words to transfer. + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when LDMA is + * configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_RadioPerformM2mLdma(uint32_t *pDest, + const uint32_t *pSrc, + uint32_t numWords); + +/** + * Configure HFXO. + * + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when HFXO is + * configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_ConfigureHfxo(void); + +/** + * Set GPIO for antenna config. + * + * @param[in] config A pointer to a configuration structure applied to the relevant Antenna + * Configuration registers. A NULL configuration will produce undefined behavior. + * @return Status code indicating success of the function call. + * + * @note This function must only be called from secure world when CMU or GPIO + * are configured as secure TrustZone peripheral. + * + */ +RAIL_Status_t RAIL_TZ_ConfigAntennaGpio(const RAIL_AntennaConfig_t *config); + +/** @} */ // end of group TrustZone + +/****************************************************************************** + * Features + *****************************************************************************/ /** * @addtogroup Features * @{ @@ -6899,8 +7273,8 @@ bool RAIL_SupportsTxPowerMode(RAIL_Handle_t railHandle, * * @param[in] railHandle A radio-generic or real RAIL instance handle. * @param[in,out] powerMode A pointer to PA power mode to check if supported. - * For platforms that support \ref RAIL_TX_POWER_MODE_2P4GIG_HIGHEST or - * \ref RAIL_TX_POWER_MODE_SUBGIG_HIGHEST the powerMode is updated + * If \ref RAIL_TX_POWER_MODE_2P4GIG_HIGHEST or \ref + * RAIL_TX_POWER_MODE_SUBGIG_HIGHEST is passed in, it will be updated * to the highest corresponding PA available on the chip. * @param[out] maxPowerLevel A pointer to a \ref RAIL_TxPowerLevel_t that * if non-NULL will be filled in with the power mode's highest power level @@ -6909,6 +7283,8 @@ bool RAIL_SupportsTxPowerMode(RAIL_Handle_t railHandle, * if non-NULL will be filled in with the power mode's lowest power level * allowed if this function returns true. * @return true if powerMode is supported; false otherwise. + * + * This function has no compile-time equivalent. */ bool RAIL_SupportsTxPowerModeAlt(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t *powerMode, @@ -6936,30 +7312,30 @@ bool RAIL_SupportsTxToTx(RAIL_Handle_t railHandle); bool RAIL_SupportsProtocolBLE(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports BLE 1Mbps Non-Viterbi PHY. + * Indicate whether this chip supports BLE 1 Mbps Non-Viterbi PHY. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if BLE 1Mbps Non-Viterbi is supported; false otherwise. + * @return true if BLE 1 Mbps Non-Viterbi is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI. */ bool RAIL_BLE_Supports1MbpsNonViterbi(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports BLE 1Mbps Viterbi PHY. + * Indicate whether this chip supports BLE 1 Mbps Viterbi PHY. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if BLE 1Mbps Viterbi is supported; false otherwise. + * @return true if BLE 1 Mbps Viterbi is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI. */ bool RAIL_BLE_Supports1MbpsViterbi(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports BLE 1Mbps operation. + * Indicate whether this chip supports BLE 1 Mbps operation. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if BLE 1Mbps operation is supported; false otherwise. + * @return true if BLE 1 Mbps operation is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS. */ @@ -6972,30 +7348,30 @@ bool RAIL_BLE_Supports1Mbps(RAIL_Handle_t railHandle) } /** - * Indicate whether this chip supports BLE 2Mbps Non-Viterbi PHY. + * Indicate whether this chip supports BLE 2 Mbps Non-Viterbi PHY. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if BLE 2Mbps Non-Viterbi is supported; false otherwise. + * @return true if BLE 2 Mbps Non-Viterbi is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI. */ bool RAIL_BLE_Supports2MbpsNonViterbi(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports BLE 2Mbps Viterbi PHY. + * Indicate whether this chip supports BLE 2 Mbps Viterbi PHY. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if BLE 2Mbps Viterbi is supported; false otherwise. + * @return true if BLE 2 Mbps Viterbi is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI. */ bool RAIL_BLE_Supports2MbpsViterbi(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports BLE 2Mbps operation. + * Indicate whether this chip supports BLE 2 Mbps operation. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if BLE 2Mbps operation is supported; false otherwise. + * @return true if BLE 2 Mbps operation is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS. */ @@ -7049,7 +7425,7 @@ bool RAIL_BLE_SupportsCte(RAIL_Handle_t railHandle); * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CS. */ bool RAIL_BLE_SupportsCs(RAIL_Handle_t railHandle); -#endif +#endif//DOXYGEN_SHOULD_SKIP_THIS /** * Indicate whether this chip supports BLE IQ Sampling needed for @@ -7094,7 +7470,7 @@ bool RAIL_BLE_SupportsSignalIdentifier(RAIL_Handle_t railHandle); /** * Indicate whether this chip supports BLE Simulscan PHY used for simultaneous - * BLE 1Mbps and Coded PHY reception. + * BLE 1 Mbps and Coded PHY reception. * * @param[in] railHandle A radio-generic or real RAIL instance handle. * @return true if BLE Simulscan PHY is supported; false otherwise. @@ -7115,10 +7491,10 @@ bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle); #ifndef DOXYGEN_SHOULD_SKIP_THIS /** - * Indicate whether this chip supports the IEEE 802.15.4 2Mbps PHY. + * Indicate whether this chip supports the IEEE 802.15.4 2 Mbps PHY. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if the 802.15.4 2Mbps PHY is supported; false otherwise. + * @return true if the 802.15.4 2 Mbps PHY is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY. */ @@ -7193,7 +7569,7 @@ bool RAIL_IEEE802154_SupportsFemPhy(RAIL_Handle_t railHandle); * Indicate whether this chip supports canceling the frame-pending lookup * event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND when the radio * transitions to a state that renders the the reporting of this event moot - * (i.e., too late for the stack to influence the outgoing ACK). + * (i.e., too late for the stack to influence the outgoing Ack). * * @param[in] railHandle A radio-generic or real RAIL instance handle. * @return true if canceling the lookup event is supported; false otherwise. @@ -7227,10 +7603,10 @@ bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle); bool RAIL_IEEE802154_SupportsDualPaConfig(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports IEEE 802.15.4E-2012 Enhanced ACKing. + * Indicate whether this chip supports IEEE 802.15.4E-2012 Enhanced Acking. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if 802.15.4E Enhanced ACKing is supported; false otherwise. + * @return true if 802.15.4E Enhanced Acking is supported; false otherwise. * * Runtime refinement of compile-time \ref * RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. @@ -7403,10 +7779,10 @@ bool RAIL_ZWAVE_SupportsRegionPti(RAIL_Handle_t railHandle); bool RAIL_IEEE802154_SupportsSignalIdentifier(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports fast RX2RX. + * Indicate whether this chip supports fast RX-to-RX. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if fast RX2RX is supported; false otherwise. + * @return true if fast RX-to-RX is supported; false otherwise. * * Runtime refinement of compile-time \ref RAIL_SUPPORTS_FAST_RX2RX. */ @@ -7433,14 +7809,26 @@ bool RAIL_SupportsCollisionDetection(RAIL_Handle_t railHandle); bool RAIL_SupportsProtocolSidewalk(RAIL_Handle_t railHandle); /** - * Indicate whether this chip supports automatic LNA bypass for external FEM. + * Indicate whether this chip supports TrustZone secure configuration of + * peripherals used by RAIL. + * + * @param[in] railHandle A radio-generic or real RAIL instance handle. + * @return true if secure mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_TRUSTZONE_SECURE_PERIPHERALS. + */ +bool RAIL_SupportsTrustZoneSecurePeripherals(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports automatic PRS LNA bypass for external + * FEM. * * @param[in] railHandle A radio-generic or real RAIL instance handle. - * @return true if automatic LNA bypass is supported; false otherwise. + * @return true if automatic PRS LNA bypass is supported; false otherwise. * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_AUTO_LNA_BYPASS. + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PRS_LNA_BYPASS. */ -bool RAIL_SupportsAutoLnaBypass(RAIL_Handle_t railHandle); +bool RAIL_SupportsPrsLnaBypass(RAIL_Handle_t railHandle); /** @} */ // end of group Features diff --git a/simplicity_sdk/platform/radio/rail_lib/common/rail_assert_error_codes.h b/simplicity_sdk/platform/radio/rail_lib/common/rail_assert_error_codes.h index 760f3be44..6ed194884 100644 --- a/simplicity_sdk/platform/radio/rail_lib/common/rail_assert_error_codes.h +++ b/simplicity_sdk/platform/radio/rail_lib/common/rail_assert_error_codes.h @@ -1,7 +1,7 @@ /***************************************************************************//** * @file - * @brief Definition of error codes that occur in rail for use in - * RAILCb_AssertFailed. This file is purely informational and optional - + * @brief Definition of error codes that occur in RAIL. + * This file is purely informational and optional - * it need not be included even if rail_assert libraries are included. ******************************************************************************* * # License @@ -45,7 +45,7 @@ extern "C" { */ /** - * Enumeration of all possible error codes from RAIL_ASSERT + * Enumeration of all possible error codes from RAIL_ASSERT. */ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) { @@ -69,8 +69,8 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO = 8, /** Reached unexpected state while handling TX ACK FIFO events. */ RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO = 9, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_10 = 10, + /** Invalid memory region accessed. */ + RAIL_ASSERT_INVALID_MEMORY_ACCESS = 10, /** Invalid assert, no longer used. */ RAIL_ASSERT_UNUSED_11 = 11, /** Invalid assert, no longer used. */ @@ -125,8 +125,8 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) RAIL_ASSERT_UNUSED_36 = 36, /** Invalid assert, no longer used. */ RAIL_ASSERT_UNUSED_37 = 37, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_38 = 38, + /** Failed to enable synth for transmit. */ + RAIL_ASSERT_FAILED_TX_SYNTH_ENABLE = 38, /** This function is deprecated and must not be called. */ RAIL_ASSERT_DEPRECATED_FUNCTION = 39, /** Multiprotocol task started with no event to run. */ @@ -141,8 +141,8 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) RAIL_ASSERT_CANT_USE_HARDWARE = 44, /** Pointer parameter was passed as NULL. */ RAIL_ASSERT_NULL_PARAMETER = 45, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_46 = 46, + /** Secure Element fault */ + RAIL_ASSERT_SECURE_ELEMENT_FAULT = 46, /** Synth radio config buffer for channel hopping too small. */ RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER = 47, /** Buffer provided for RX Channel Hopping is too small. */ @@ -155,8 +155,8 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) RAIL_ASSERT_CHANNEL_CHANGE_FAILED = 51, /** Attempted to read invalid register. */ RAIL_ASSERT_INVALID_REGISTER = 52, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_53 = 53, + /** CP/DMA Invalid error. */ + RAIL_ASSERT_CP_DMA_INTERNAL_GENERIC_ERROR = 53, /** DMP radio config caching failed. */ RAIL_ASSERT_CACHE_CONFIG_FAILED = 54, /** NULL was supplied as a RAIL_StateTransitions_t argument. */ @@ -183,8 +183,8 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG = 65, /** Radio Calculator configuration HFXO frequency mismatch with chip */ RAIL_ASSERT_INVALID_XTAL_FREQUENCY = 66, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_67 = 67, + /** Internal error. */ + RAIL_ASSERT_INTERNAL_GENERIC_ERROR = 67, /** Software modem image does not support requested modulation */ RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION = 68, /** Failed to disable RTCC synchronization. */ @@ -237,7 +237,7 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) #define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO) #define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO) #define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO) -#define RAIL_ASSERT_UNUSED_10 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_10) +#define RAIL_ASSERT_INVALID_MEMORY_ACCESS ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_MEMORY_ACCESS) #define RAIL_ASSERT_UNUSED_11 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_11) #define RAIL_ASSERT_UNUSED_12 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_12) #define RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP) @@ -265,7 +265,7 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) #define RAIL_ASSERT_UNUSED_35 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_35) #define RAIL_ASSERT_UNUSED_36 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_36) #define RAIL_ASSERT_UNUSED_37 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_37) -#define RAIL_ASSERT_UNUSED_38 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_38) +#define RAIL_ASSERT_FAILED_TX_SYNTH_ENABLE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TX_SYNTH_ENABLE) #define RAIL_ASSERT_DEPRECATED_FUNCTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DEPRECATED_FUNCTION) #define RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT) #define RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED) @@ -273,14 +273,14 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) #define RAIL_ASSERT_DIVISION_BY_ZERO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DIVISION_BY_ZERO) #define RAIL_ASSERT_CANT_USE_HARDWARE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CANT_USE_HARDWARE) #define RAIL_ASSERT_NULL_PARAMETER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_PARAMETER) -#define RAIL_ASSERT_UNUSED_46 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_46) +#define RAIL_ASSERT_SECURE_ELEMENT_FAULT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SECURE_ELEMENT_FAULT) #define RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER) #define RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT) #define RAIL_ASSERT_INVALID_MODULE_ACTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_MODULE_ACTION) #define RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG) #define RAIL_ASSERT_CHANNEL_CHANGE_FAILED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_CHANGE_FAILED) #define RAIL_ASSERT_INVALID_REGISTER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_REGISTER) -#define RAIL_ASSERT_UNUSED_53 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_53) +#define RAIL_ASSERT_CP_DMA_INTERNAL_GENERIC_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CP_DMA_INTERNAL_GENERIC_ERROR) #define RAIL_ASSERT_CACHE_CONFIG_FAILED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CACHE_CONFIG_FAILED) #define RAIL_ASSERT_NULL_TRANSITIONS ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_TRANSITIONS) #define RAIL_ASSERT_BAD_LDMA_TRANSFER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_BAD_LDMA_TRANSFER) @@ -294,7 +294,7 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) #define RAIL_ASSERT_SEQ_INVALID_PA_SELECTED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQ_INVALID_PA_SELECTED) #define RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG) #define RAIL_ASSERT_INVALID_XTAL_FREQUENCY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_XTAL_FREQUENCY) -#define RAIL_ASSERT_UNUSED_67 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_67) +#define RAIL_ASSERT_INTERNAL_GENERIC_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INTERNAL_GENERIC_ERROR) #define RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION) #define RAIL_ASSERT_FAILED_RTCC_SYNC_STOP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_STOP) #define RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT) @@ -321,9 +321,8 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) /// detailed error strings related to a particular assert error code if desired. /// For example, you could implement your assert failed callback as follows to /// make use of this. -/// /// @code{.c} -/// void RAILCb_AssertFailed(RAIL_Handle_t railHandle, uint32_t errorCode) +/// void RAILCb_AssertFailed(RAIL_Handle_t railHandle, RAIL_AssertErrorCodes_t errorCode) /// { /// static const char* railErrorMessages[] = RAIL_ASSERT_ERROR_MESSAGES; /// const char *errorMessage = "Unknown"; @@ -333,7 +332,7 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) /// if (errorCode < (sizeof(railErrorMessages) / sizeof(char*))) { /// errorMessage = railErrorMessages[errorCode]; /// } -/// printf(errorMessage); +/// printf("RAIL ASSERT %u: %s\n", errorCode, errorMessage); /// /// // Reset the chip since an assert is a fatal error /// NVIC_SystemReset(); @@ -379,7 +378,7 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) /*35*/ "Invalid assert, no longer used", \ /*36*/ "Invalid assert, no longer used", \ /*37*/ "Invalid assert, no longer used", \ - /*38*/ "Invalid assert, no longer used", \ + /*38*/ "Failed to enable synth for transmit.", \ /*39*/ "This function is deprecated and must not be called", \ /*40*/ "Multiprotocol task started with no event to run", \ /*41*/ "Invalid interrupt enabled", \ @@ -387,14 +386,14 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) /*43*/ "Division by zero", \ /*44*/ "Function cannot be called without access to the hardware", \ /*45*/ "Pointer parameter was passed as NULL", \ - /*46*/ "Invalid assert, no longer used", \ + /*46*/ "Secure Element fault", \ /*47*/ "Synth radio config buffer for channel hopping too small", \ /*48*/ "Buffer provided for RX Channel Hopping is too small", \ /*49*/ "Invalid action was attempted on a module", \ /*50*/ "The radio config for this channel is not compatible with channel hopping", \ /*51*/ "Channel change failed", \ /*52*/ "Attempted to read invalid register", \ - /*53*/ "Invalid assert, no longer used", \ + /*53*/ "CP/DMA Generic internal error", \ /*54*/ "DMP radio config caching failed", \ /*55*/ "NULL was supplied as a RAIL_StateTransitions_t argument", \ /*56*/ "LDMA transfer failed", \ @@ -408,7 +407,7 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) /*64*/ "The sequencer selected an invalid PA", \ /*65*/ "Invalid/unsupported channel config", \ /*66*/ "Radio Calculator configuration HFXO frequency mismatch with chip", \ - /*67*/ "Invalid assert, no longer used", \ + /*67*/ "Generic internal error", \ /*68*/ "Software modem image does not support requested modulation", \ /*69*/ "Failed to disable RTCC synchronization", \ /*70*/ "Multitimer linked list corrupted", \ @@ -430,9 +429,14 @@ RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) /*86*/ "The sequencer user generated error", \ } -/** - * @} - */ +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Undocumented RAIL 2.x internal symbol renaming +#define RAIL_AssertErrorCode sli_rail_assert_error_code +#define RAIL_AssertLineNumber sli_rail_assert_line_number +#define RAIL_AssertRailHandle sli_rail_assert_rail_handle +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of Assertions #ifdef __cplusplus } diff --git a/simplicity_sdk/platform/radio/rail_lib/common/rail_features.h b/simplicity_sdk/platform/radio/rail_lib/common/rail_features.h index a78bfdb0a..53790ce26 100644 --- a/simplicity_sdk/platform/radio/rail_lib/common/rail_features.h +++ b/simplicity_sdk/platform/radio/rail_lib/common/rail_features.h @@ -39,7 +39,7 @@ extern "C" { #endif /** - * @addtogroup RAIL_API RAIL API + * @addtogroup RAIL_API * @{ */ @@ -54,7 +54,7 @@ extern "C" { * these defines hold true for chip families. Your specific part * may have further restrictions (band limitations, power amplifier * restrictions, and so on) on top of those listed below, for which - * runtime RAIL_Supports*() APIs can be used to check availability + * runtime RAIL_*Supports*() APIs can be used to check availability * on a particular chip (after \ref RAIL_Init() has been called). * In general, an attempt to call an API that is not supported on your * chip family as listed below will result in a @@ -62,7 +62,7 @@ extern "C" { * @{ */ -/// Boolean to indicate whether the selected chip supports both SubGHz and 2.4 GHz bands. +/// Boolean to indicate whether the selected chip supports both Sub-GHz and 2.4 GHz bands. /// See also runtime refinement \ref RAIL_SupportsDualBand(). #if ((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ || ((FEAT_RF_2G4 == 1) && (FEAT_RF_SUBG == 1))) @@ -85,7 +85,7 @@ extern "C" { /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_2P4GHZ_BAND. #define RAIL_FEAT_2G4_RADIO RAIL_SUPPORTS_2P4GHZ_BAND -/// Boolean to indicate whether the selected chip supports SubGHz bands. +/// Boolean to indicate whether the selected chip supports Sub-GHz bands. /// See also runtime refinement \ref RAIL_SupportsSubGHzBand(). #if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ || (_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_SUBGHZ)) \ @@ -108,7 +108,9 @@ extern "C" { /// Boolean to indicate whether the selected chip supports /// bit masked address filtering. /// See also runtime refinement \ref RAIL_SupportsAddrFilterAddressBitMask(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) || (_SILICON_LABS_32B_SERIES_3_CONFIG == 1) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300)) #define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 1 #else #define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 0 @@ -128,9 +130,9 @@ extern "C" { /// Boolean to indicate whether the selected chip supports /// alternate power settings for the Power Amplifier. /// See also runtime refinement \ref RAIL_SupportsAlternateTxPower(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1) \ +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG > 1) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_SUPPORTS_ALTERNATE_TX_POWER 1 #else #define RAIL_SUPPORTS_ALTERNATE_TX_POWER 0 @@ -146,12 +148,14 @@ extern "C" { #else #define RAIL_SUPPORTS_ANTENNA_DIVERSITY 0 #endif + /// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY. #define RAIL_FEAT_ANTENNA_DIVERSITY RAIL_SUPPORTS_ANTENNA_DIVERSITY -/// Boolean to indicate whether the selected chip supports RF path diversity. +/// Boolean to indicate whether the selected chip supports internal RF path diversity. /// See also runtime refinement \ref RAIL_SupportsPathDiversity(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_SUPPORTS_PATH_DIVERSITY 1 #else #define RAIL_SUPPORTS_PATH_DIVERSITY 0 @@ -159,7 +163,9 @@ extern "C" { /// Boolean to indicate whether the selected chip supports channel hopping. /// See also runtime refinement \ref RAIL_SupportsChannelHopping(). -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG >= 1) || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1)) +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG >= 1) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_SUPPORTS_CHANNEL_HOPPING 1 #else #define RAIL_SUPPORTS_CHANNEL_HOPPING 0 @@ -198,7 +204,8 @@ extern "C" { || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) #define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 1 #else #define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 0 @@ -216,9 +223,12 @@ extern "C" { /// Boolean to indicate whether the selected chip supports AUXADC measurements. /// See also runtime refinement \ref RAIL_SupportsAuxAdc(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) #define RAIL_SUPPORTS_AUXADC 1 #else #define RAIL_SUPPORTS_AUXADC 0 @@ -228,7 +238,10 @@ extern "C" { /// LFRCO. /// Best to use the runtime refinement \ref RAIL_SupportsPrecisionLFRCO() /// because some chip revisions do not support it. -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) #define RAIL_SUPPORTS_PRECISION_LFRCO 1 #else #define RAIL_SUPPORTS_PRECISION_LFRCO 0 @@ -245,7 +258,10 @@ extern "C" { /// Boolean to indicate whether the selected chip supports /// RFSENSE Energy Detection Mode. /// See also runtime refinement \ref RAIL_SupportsRfSenseEnergyDetection(). -#if ((_SILICON_LABS_32B_SERIES == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#if ((_SILICON_LABS_32B_SERIES == 1) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) #define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 1 #else #define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 0 @@ -254,7 +270,9 @@ extern "C" { /// Boolean to indicate whether the selected chip supports /// RFSENSE Selective(OOK) Mode. /// See also runtime refinement \ref RAIL_SupportsRfSenseSelectiveOok(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) #define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 1 #else #define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 0 @@ -274,8 +292,8 @@ extern "C" { #ifndef DOXYGEN_SHOULD_SKIP_THIS /// Boolean to indicate whether the selected chip supports the User Sequencer -/// See also runtime refinement RAIL_SupportsUserSequencer(). -#if (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1) +/// See also runtime refinement \ref RAIL_SupportsUserSequencer(). +#if (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300) #define RAIL_SUPPORTS_USER_SEQUENCER 1 #else #define RAIL_SUPPORTS_USER_SEQUENCER 0 @@ -294,7 +312,7 @@ extern "C" { #define RAIL_SUPPORTS_PROTOCOL_BLE 0 #endif -/// Boolean to indicate whether the selected chip supports BLE 1Mbps +/// Boolean to indicate whether the selected chip supports BLE 1 Mbps /// Non-Viterbi PHY. /// See also runtime refinement \ref RAIL_BLE_Supports1MbpsNonViterbi(). #if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 1) @@ -303,7 +321,7 @@ extern "C" { #define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI 0 #endif -/// Boolean to indicate whether the selected chip supports BLE 1Mbps Viterbi +/// Boolean to indicate whether the selected chip supports BLE 1 Mbps Viterbi /// PHY. /// See also runtime refinement \ref RAIL_BLE_Supports1MbpsViterbi(). #if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) @@ -312,12 +330,12 @@ extern "C" { #define RAIL_BLE_SUPPORTS_1MBPS_VITERBI 0 #endif -/// Boolean to indicate whether the selected chip supports BLE 1Mbps operation. +/// Boolean to indicate whether the selected chip supports BLE 1 Mbps operation. /// See also runtime refinement \ref RAIL_BLE_Supports1Mbps(). #define RAIL_BLE_SUPPORTS_1MBPS \ (RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_1MBPS_VITERBI) -/// Boolean to indicate whether the selected chip supports BLE 2Mbps +/// Boolean to indicate whether the selected chip supports BLE 2 Mbps /// Non-Viterbi PHY. /// See also runtime refinement \ref RAIL_BLE_Supports2MbpsNonViterbi(). #if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) @@ -326,7 +344,7 @@ extern "C" { #define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI 0 #endif -/// Boolean to indicate whether the selected chip supports BLE 2Mbps Viterbi +/// Boolean to indicate whether the selected chip supports BLE 2 Mbps Viterbi /// PHY. /// See also runtime refinement \ref RAIL_BLE_Supports2MbpsViterbi(). #if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) @@ -335,7 +353,7 @@ extern "C" { #define RAIL_BLE_SUPPORTS_2MBPS_VITERBI 0 #endif -/// Boolean to indicate whether the selected chip supports BLE 2Mbps operation. +/// Boolean to indicate whether the selected chip supports BLE 2 Mbps operation. /// See also runtime refinement \ref RAIL_BLE_Supports2Mbps(). #define RAIL_BLE_SUPPORTS_2MBPS \ (RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_2MBPS_VITERBI) @@ -347,7 +365,7 @@ extern "C" { #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ - || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1)) + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING RAIL_SUPPORTS_PROTOCOL_BLE #else #define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING 0 @@ -362,7 +380,8 @@ extern "C" { || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ - || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1)) + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_BLE_SUPPORTS_CODED_PHY RAIL_SUPPORTS_PROTOCOL_BLE #else #define RAIL_BLE_SUPPORTS_CODED_PHY 0 @@ -371,14 +390,14 @@ extern "C" { #define RAIL_FEAT_BLE_CODED RAIL_BLE_SUPPORTS_CODED_PHY /// Boolean to indicate whether the selected chip supports the BLE Simulscan PHY -/// used for simultaneous BLE 1Mbps and Coded PHY reception. +/// used for simultaneous BLE 1 Mbps and Coded PHY reception. /// See also runtime refinement \ref RAIL_BLE_SupportsSimulscanPhy(). #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ - || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1)) - + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY RAIL_SUPPORTS_PROTOCOL_BLE #else #define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY 0 @@ -390,9 +409,10 @@ extern "C" { /// See also runtime refinement \ref RAIL_BLE_SupportsCte(). #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ - || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1)) + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_BLE_SUPPORTS_CTE RAIL_SUPPORTS_PROTOCOL_BLE #else #define RAIL_BLE_SUPPORTS_CTE 0 @@ -401,7 +421,9 @@ extern "C" { /// Boolean to indicate whether the selected chip supports the /// Quuppa PHY. /// See also runtime refinement \ref RAIL_BLE_SupportsQuuppa(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) #define RAIL_BLE_SUPPORTS_QUUPPA RAIL_SUPPORTS_PROTOCOL_BLE #else #define RAIL_BLE_SUPPORTS_QUUPPA 0 @@ -413,7 +435,7 @@ extern "C" { #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ - || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1)) + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_BLE_SUPPORTS_IQ_SAMPLING RAIL_SUPPORTS_PROTOCOL_BLE #else #define RAIL_BLE_SUPPORTS_IQ_SAMPLING 0 @@ -437,7 +459,7 @@ extern "C" { #else #define RAIL_BLE_SUPPORTS_CS 0 #endif -#endif +#endif//DOXYGEN_SHOULD_SKIP_THIS /// Boolean to indicate whether the selected chip supports BLE PHY switch to RX /// functionality, which is used to switch BLE PHYs at a specific time @@ -563,9 +585,10 @@ extern "C" { /// dynamic FEC /// See also runtime refinement \ref /// RAIL_IEEE802154_SupportsGDynFec(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1 || _SILICON_LABS_32B_SERIES_3_CONFIG >= 1) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG > 1) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_IEEE802154_SUPPORTS_G_DYNFEC \ - RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to SUBGHZ for now + RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to Sub-GHz for now #else #define RAIL_IEEE802154_SUPPORTS_G_DYNFEC 0 #endif @@ -577,7 +600,7 @@ extern "C" { #if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH \ - RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to SUBGHZ for now + RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to Sub-GHz for now #else #define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH 0 #endif @@ -667,7 +690,8 @@ extern "C" { #endif /// Boolean to indicate whether the selected chip supports the pa power setting table. -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300)) #define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 1 #else #define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 0 @@ -678,7 +702,7 @@ extern "C" { /// This feature is available when the configuration for Silicon Labs Series 3 /// devices is set to 1, enabling the use of a unified Power Amplifier (PA) interface /// across different configurations. -#if (_SILICON_LABS_32B_SERIES_3_CONFIG >= 1) +#if (_SILICON_LABS_32B_SERIES_3_CONFIG >= 300) #define RAIL_SUPPORTS_COMMON_PA_INTERFACE 1 #else #define RAIL_SUPPORTS_COMMON_PA_INTERFACE 0 @@ -690,7 +714,11 @@ extern "C" { /// IEEE802.15.4 2.4 GHz at 2 Mbps /// See also runtime refinement \ref /// RAIL_IEEE802154_Supports2MbpsPhy(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) +#if (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300) #define RAIL_IEEE802154_SUPPORTS_2MBPS_PHY \ (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) #else @@ -700,7 +728,8 @@ extern "C" { /// Boolean to indicate whether the selected chip supports IEEE 802.15.4 PHY /// with custom settings -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_1_CONFIG == 3)) +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_1_CONFIG == 3)) #define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) #else #define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY 0 @@ -757,7 +786,8 @@ extern "C" { /// Boolean to indicate whether the selected chip supports concurrent PHY. /// See also runtime refinement \ref RAIL_ZWAVE_SupportsConcPhy(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_ZWAVE_SUPPORTS_CONC_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE #else #define RAIL_ZWAVE_SUPPORTS_CONC_PHY 0 @@ -765,9 +795,11 @@ extern "C" { /// Boolean to indicate whether the selected chip supports SQ-based PHY. /// See also runtime refinement \ref RAIL_SupportsSQPhy(). -#if (((_SILICON_LABS_32B_SERIES_2_CONFIG >= 3) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG != 7)) \ - || (_SILICON_LABS_32B_SERIES_3_CONFIG == 1)) +#if (((_SILICON_LABS_32B_SERIES_2_CONFIG >= 3) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG != 7) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG != 9)) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300)) #define RAIL_SUPPORTS_SQ_PHY 1 #else #define RAIL_SUPPORTS_SQ_PHY 0 @@ -775,7 +807,7 @@ extern "C" { /// Boolean to indicate whether the code supports Z-Wave /// region information in PTI and -/// newer RAIL_ZWAVE_RegionConfig_t structure +/// newer \ref RAIL_ZWAVE_RegionConfig_t structure /// See also runtime refinement \ref RAIL_ZWAVE_SupportsRegionPti(). #if 1 #define RAIL_ZWAVE_SUPPORTS_REGION_PTI RAIL_SUPPORTS_PROTOCOL_ZWAVE @@ -808,7 +840,8 @@ extern "C" { /// Boolean to indicate whether the selected chip supports /// RX direct mode data to FIFO. /// See also runtime refinement \ref RAIL_SupportsRxDirectModeDataToFifo(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 1 #else #define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 0 @@ -817,33 +850,37 @@ extern "C" { /// Boolean to indicate whether the selected chip supports /// MFM protocol. /// See also runtime refinement \ref RAIL_SupportsMfm(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_SUPPORTS_MFM 1 #else #define RAIL_SUPPORTS_MFM 0 #endif -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6)) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 6) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) \ + || (_SILICON_LABS_32B_SERIES_3_CONFIG == 300)) /// Boolean to indicate whether the selected chip supports /// 802.15.4 signal detection - #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_IEEE802154) +#define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_IEEE802154) /// Boolean to indicate whether the selected chip supports /// BLE signal detection - #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_BLE) +#define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_BLE) #else /// Boolean to indicate whether the selected chip supports /// 802.15.4 signal detection - #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER 0 +#define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER 0 /// Boolean to indicate whether the selected chip supports /// BLE signal detection - #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER 0 +#define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER 0 #endif /// Boolean to indicate whether the selected chip supports /// configurable RSSI threshold set by \ref RAIL_SetRssiDetectThreshold(). /// See also runtime refinement \ref RAIL_SupportsRssiDetectThreshold(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5)) #define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (1U) #else #define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (0U) @@ -858,7 +895,7 @@ extern "C" { #define RAIL_SUPPORTS_THERMAL_PROTECTION (0U) #endif -/// Boolean to indicate whether the selected chip supports fast RX2RX enabled by +/// Boolean to indicate whether the selected chip supports fast RX-to-RX enabled by /// \ref RAIL_RX_OPTION_FAST_RX2RX. /// See also runtime refinement \ref RAIL_SupportsFastRx2Rx(). #if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) @@ -868,7 +905,7 @@ extern "C" { #endif /// Boolean to indicate whether the selected chip supports collision detection -/// enabled by RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION +/// enabled by \ref RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION /// See also runtime refinement \ref RAIL_SupportsCollisionDetection(). #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) #define RAIL_SUPPORTS_COLLISION_DETECTION (1U) @@ -878,20 +915,30 @@ extern "C" { /// Boolean to indicate whether the selected chip supports Sidewalk protocol. /// See also runtime refinement \ref RAIL_SupportsProtocolSidewalk(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (1U) #else #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (0U) #endif -/// Boolean to indicate whether the selected chip supports automatic LNA bypass -/// for external FEM. -/// See also runtime refinement \ref RAIL_SupportsAutoLnaBypass(). +/// Boolean to indicate whether the selected chip supports TrustZone secure +/// configuration of peripherals used by RAIL. +/// See also runtime refinement \ref RAIL_SupportsTrustZoneSecurePeripherals(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) + #define RAIL_SUPPORTS_TRUSTZONE_SECURE_PERIPHERALS (1U) +#else + #define RAIL_SUPPORTS_TRUSTZONE_SECURE_PERIPHERALS (0U) +#endif + +/// Boolean to indicate whether the selected chip supports automatic PRS LNA +/// bypass for external FEM. +/// See also runtime refinement \ref RAIL_SupportsPrsLnaBypass(). #if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) - #define RAIL_SUPPORTS_AUTO_LNA_BYPASS (1U) + #define RAIL_SUPPORTS_PRS_LNA_BYPASS (1U) #else - #define RAIL_SUPPORTS_AUTO_LNA_BYPASS (0U) + #define RAIL_SUPPORTS_PRS_LNA_BYPASS (0U) #endif /** @} */ // end of group Features @@ -902,8 +949,4 @@ extern "C" { } #endif -#ifdef RAIL_INTERNAL_BUILD -#include "rail_features_internal.h" -#endif - #endif // __RAIL_FEATURES_H__ diff --git a/simplicity_sdk/platform/radio/rail_lib/common/rail_mfm.h b/simplicity_sdk/platform/radio/rail_lib/common/rail_mfm.h index eee8c7b7b..7a78a2f85 100644 --- a/simplicity_sdk/platform/radio/rail_lib/common/rail_mfm.h +++ b/simplicity_sdk/platform/radio/rail_lib/common/rail_mfm.h @@ -63,37 +63,29 @@ extern "C" { /// \ref RAIL_ConfigData() and is activated when transmit is started by /// \ref RAIL_StartTx(). Once transmitting the data in the ping-pong buffers, /// RAIL will manage them so it looks like a continuous transmission to the -/// receiver. Every time one of the ping-ping buffers has been transmitted, +/// receiver. Every time one of the ping-pong buffers has been transmitted, /// \ref RAIL_EVENT_MFM_TX_BUFFER_DONE is triggered so the application can /// update the data in that buffer without the need to start/stop the /// transmission. \ref RAIL_EVENT_MFM_TX_BUFFER_DONE can be enable with \ref /// RAIL_ConfigEvents(). /// Use \ref RAIL_StopTx() to finish transmitting. -/// /// @code{.c} +/// #define MFM_RAW_BUF_WORDS 128 +/// extern RAIL_Handle_t railHandle; /// uint8_t txCount = 0; +/// uint32_t mfmPingPongBuffers[2][MFM_RAW_BUF_WORDS]; /// -/// typedef struct RAIL_MFM_Config_App { +/// typedef struct mfmConfigApp { /// RAIL_MFM_PingPongBufferConfig_t buffer; /// RAIL_StateTiming_t timings; -/// } RAIL_MFM_Config_App_t; +/// RAIL_DataConfig_t dataConfig; +/// } mfmConfigApp_t; /// -/// // Main RAIL_EVENT callback -/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) -/// { -/// // Increment TX counter -/// if (events & RAIL_EVENT_MFM_BUF_DONE) { -/// txCount++; -/// return; -/// } -/// } -/// } -/// -/// static const RAIL_MFM_Config_App_t mfmConfig = { +/// static mfmConfigApp_t mfmConfig = { /// .buffer = { -/// .pBuffer0 = (&channelHoppingBufferSpace[0]), -/// .pBuffer1 = (&channelHoppingBufferSpace[MFM_RAW_BUF_SZ_BYTES / 4]), -/// .bufferSizeWords = (MFM_RAW_BUF_SZ_BYTES / 4) +/// .pBuffer0 = (&mfmPingPongBuffers[0]), +/// .pBuffer1 = (&mfmPingPongBuffers[1]), +/// .bufferSizeWords = MFM_RAW_BUF_WORDS, /// }, /// .timings = { /// .idleToTx = 100, @@ -102,16 +94,33 @@ extern "C" { /// .txToRx = 0, /// .rxSearchTimeout = 0, /// .txToRxSearchTimeout = 0 +/// }, +/// .dataConfig = { +/// .txSource = TX_MFM_DATA, +/// .rxSource = RX_PACKET_DATA, +/// .txMethod = PACKET_MODE, +/// .rxMethod = PACKET_MODE, +/// }, /// }; /// -/// RAIL_Status_t mfmInit(void) +/// // Main RAIL events handler callback +/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) +/// { +/// // Increment TX counter +/// if (events & RAIL_EVENT_MFM_BUF_DONE) { +/// txCount++; +/// return; +/// } +/// } +/// } +/// +/// void mfmInit(void) /// { /// // initialize MFM /// uint32_t idx; -/// uint32_t *pDst0 = mfmConfig.pBuffer0; -/// uint32_t *pDst1 = mfmConfig.pBuffer1; -/// RAIL_Status_t status; -/// for (idx = 0; idx < (MFM_RAW_BUF_SZ_BYTES / 16); idx++) { +/// uint32_t *pDst0 = mfmConfig.buffer.pBuffer0; +/// uint32_t *pDst1 = mfmConfig.buffer.pBuffer1; +/// for (idx = 0; idx < (mfmConfig.buffer.bufferSizeWords / 4); idx++) { /// pDst0[4 * idx + 0] = 0x755A3100; /// pDst1[4 * idx + 0] = 0x755A3100; /// pDst0[4 * idx + 1] = 0x315A757F; @@ -123,38 +132,30 @@ extern "C" { /// } /// /// RAIL_Status_t status; -/// railDataConfig.txSource = TX_MFM_DATA; -/// status = RAIL_SetMfmPingPongFifo(railHandle, -/// &(config->buffer)); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } +/// status = RAIL_SetMfmPingPongFifo(railHandle, &mfmConfig.buffer); +/// assert(status == RAIL_STATUS_NO_ERROR); /// +/// status = RAIL_SetStateTiming(railHandle, &mfmConfig.timings); +/// assert(status == RAIL_STATUS_NO_ERROR); /// -/// status = RAIL_ConfigData(railHandle, &railDataConfig); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } -/// -/// status = RAIL_SetStateTiming(railHandle, &(config->timings)); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } +/// mfmConfig.dataConfig.txSource = TX_MFM_DATA; +/// status = RAIL_ConfigData(railHandle, &mfmConfig.dataConfig); +/// assert(status == RAIL_STATUS_NO_ERROR); /// /// // start transmitting -/// return (RAIL_StartTx(railHandle, 0, 0, &schedulerInfo)); +/// status = RAIL_StartTx(railHandle, 0, 0, NULL); +/// assert(status == RAIL_STATUS_NO_ERROR); /// } /// -/// RAIL_Status_t mfmDeInit(void) +/// void mfmDeInit(void) /// { /// RAIL_Status_t status; /// status = RAIL_StopTx(railHandle, RAIL_STOP_MODES_ALL); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } +/// assert(status == RAIL_STATUS_NO_ERROR); /// -/// railDataConfig.txSource = TX_PACKET_DATA; -/// return (RAIL_ConfigData(railHandle, &railDataConfig)); +/// mfmConfig.dataConfig.txSource = TX_PACKET_DATA; +/// status = RAIL_ConfigData(railHandle, &mfmConfig.dataConfig); +/// assert(status == RAIL_STATUS_NO_ERROR); /// } /// @endcode /// @@ -165,11 +166,11 @@ extern "C" { * @brief A configuration structure for MFM Ping-pong buffer in RAIL. */ typedef struct RAIL_MFM_PingPongBufferConfig { - /** pointer to buffer0. Must be 32-bit aligned. */ + /** Pointer to buffer 0. Must be 32-bit aligned. */ uint32_t *pBuffer0; - /** pointer to buffer1. Must be 32-bit aligned. */ + /** Pointer to buffer 1. Must be 32-bit aligned. */ uint32_t *pBuffer1; - /** size of each buffer A and B in 32-bit words. */ + /** Size of each buffer in 32-bit words. */ uint32_t bufferSizeWords; } RAIL_MFM_PingPongBufferConfig_t; @@ -177,9 +178,8 @@ typedef struct RAIL_MFM_PingPongBufferConfig { * Set MFM ping-pong buffer. * * @param[in] railHandle A handle of RAIL instance. - * @param[in] config A MFM ping-pong buffer configuration structure. - * @return A status code indicating success of the function call. - * + * @param[in] config A non-NULL pointer to the MFM ping-pong buffer configuration structure. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_SetMfmPingPongFifo(RAIL_Handle_t railHandle, const RAIL_MFM_PingPongBufferConfig_t *config); diff --git a/simplicity_sdk/platform/radio/rail_lib/common/rail_types.h b/simplicity_sdk/platform/radio/rail_lib/common/rail_types.h index 6149bd7b3..d11fba6cf 100644 --- a/simplicity_sdk/platform/radio/rail_lib/common/rail_types.h +++ b/simplicity_sdk/platform/radio/rail_lib/common/rail_types.h @@ -36,6 +36,7 @@ #include #include #include +#include "sl_status.h" #ifdef __cplusplus extern "C" { @@ -77,33 +78,33 @@ extern "C" { /** * @struct RAIL_Version_t * @brief Contains RAIL Library Version Information. - * It is filled in by RAIL_GetVersion(). + * It is filled in by \ref RAIL_GetVersion(). */ typedef struct RAIL_Version { /** Git hash */ uint32_t hash; /** Major number */ - uint8_t major; + uint8_t major; /** Minor number */ - uint8_t minor; + uint8_t minor; /** Revision number */ - uint8_t rev; + uint8_t rev; /** Build number */ - uint8_t build; + uint8_t build; /** Build flags */ - uint8_t flags; + uint8_t flags; /** Boolean to indicate whether this is a multiprotocol library or not. */ - bool multiprotocol; + bool multiprotocol; } RAIL_Version_t; /** * @typedef RAIL_Handle_t - * @brief A generic handle to a particular radio (e.g. RAIL_EFR32_HANDLE), - * or a real handle of a RAIL instance, as returned from RAIL_Init(). + * @brief A radio-generic handle (e.g., \ref RAIL_EFR32_HANDLE), + * or a real RAIL instance handle as returned from \ref RAIL_Init(). * * Generic handles should be used for certain RAIL APIs that are called * prior to RAIL initialization. However, once RAIL has been initialized, - * the real handle returned by RAIL_Init() should be used instead. + * the real handle returned by \ref RAIL_Init() should be used instead. */ typedef void *RAIL_Handle_t; @@ -118,46 +119,40 @@ typedef void *RAIL_Handle_t; #define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL) /** - * @enum RAIL_Status_t + * @typedef RAIL_Status_t * @brief A status returned by many RAIL API calls indicating their success or - * failure. + * failure. It is a subset of sl_status_t. */ -RAIL_ENUM(RAIL_Status_t) { - /** RAIL function reports no error. */ - RAIL_STATUS_NO_ERROR, - /** Call to RAIL function threw an error because of an invalid parameter. */ - RAIL_STATUS_INVALID_PARAMETER, - /** - * Call to RAIL function threw an error because it was called during - * an invalid radio state. - */ - RAIL_STATUS_INVALID_STATE, - /** RAIL function is called in an invalid order. */ - RAIL_STATUS_INVALID_CALL, - /** RAIL function did not finish in the allotted time. */ - RAIL_STATUS_SUSPENDED, - /** - * RAIL function could not be scheduled by the Radio scheduler. - * Only issued when using a Multiprotocol application. - */ - RAIL_STATUS_SCHED_ERROR, -}; +typedef sl_status_t RAIL_Status_t; -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_STATUS_NO_ERROR ((RAIL_Status_t) RAIL_STATUS_NO_ERROR) -#define RAIL_STATUS_INVALID_PARAMETER ((RAIL_Status_t) RAIL_STATUS_INVALID_PARAMETER) -#define RAIL_STATUS_INVALID_STATE ((RAIL_Status_t) RAIL_STATUS_INVALID_STATE) -#define RAIL_STATUS_INVALID_CALL ((RAIL_Status_t) RAIL_STATUS_INVALID_CALL) -#define RAIL_STATUS_SUSPENDED ((RAIL_Status_t) RAIL_STATUS_SUSPENDED) -#define RAIL_STATUS_SCHED_ERROR ((RAIL_Status_t) RAIL_STATUS_SCHED_ERROR) -#endif//DOXYGEN_SHOULD_SKIP_THIS +/** RAIL function reports no error. */ +#define RAIL_STATUS_NO_ERROR SL_STATUS_OK // 0x0000 + +/** Call to RAIL function threw an error because of an invalid parameter. */ +#define RAIL_STATUS_INVALID_PARAMETER SL_STATUS_INVALID_PARAMETER // 0x0021 + +/** + * Call to RAIL function threw an error because it was called during + * an invalid radio state. + */ +#define RAIL_STATUS_INVALID_STATE SL_STATUS_INVALID_STATE // 0x0002 + +/** RAIL function is called in an invalid order. */ +#define RAIL_STATUS_INVALID_CALL SL_STATUS_NOT_AVAILABLE // 0x000E + +/** RAIL function did not finish in the allotted time. */ +#define RAIL_STATUS_SUSPENDED SL_STATUS_IN_PROGRESS // 0x0005 + +/** + * RAIL function could not be scheduled by the Radio scheduler. + * Only issued when using a Multiprotocol application. + */ +#define RAIL_STATUS_SCHED_ERROR SL_STATUS_ABORT // 0x0006 /** - * A pointer to init complete callback function + * A pointer to an initialization complete callback function. * * @param[in] railHandle The initialized RAIL instance handle. - * */ typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle); @@ -281,7 +276,7 @@ typedef void (*RAIL_MultiTimerCallback_t)(struct RAIL_MultiTimer *tmr, /** * @struct RAIL_MultiTimer_t - * @brief RAIL timer state structure + * @brief RAIL timer state structure. * * This structure is filled out and maintained internally only. * The user/application should not alter any elements of this structure. @@ -307,7 +302,7 @@ typedef struct RAIL_MultiTimer { /** * @enum RAIL_PacketTimePosition_t - * @brief The available packet timestamp position choices + * @brief The available packet timestamp position choices. */ RAIL_ENUM(RAIL_PacketTimePosition_t) { /** @@ -319,8 +314,10 @@ RAIL_ENUM(RAIL_PacketTimePosition_t) { /** * Request the choice most expedient for RAIL to calculate, * which may depend on the radio and/or its configuration. - * The actual choice would always be reflected in the timePosition - * field of \ref RAIL_RxPacketDetails_t or \ref RAIL_TxPacketDetails_t + * The actual choice would always be reflected in the \ref + * RAIL_PacketTimeStamp_t::timePosition field of the \ref + * RAIL_RxPacketDetails_t::timeReceived or \ref + * RAIL_TxPacketDetails_t::timeSent * returned and would never be one of the _USED_TOTAL values. */ RAIL_PACKET_TIME_DEFAULT = 1, @@ -360,8 +357,8 @@ RAIL_ENUM(RAIL_PacketTimePosition_t) { * Indicate that timestamp did require using totalPacketBytes. */ RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL = 7, - /** A count of the choices in this enumeration. */ - RAIL_PACKET_TIME_COUNT = 8, + /** A count of the choices in this enumeration. Must be last. */ + RAIL_PACKET_TIME_COUNT }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -394,7 +391,7 @@ typedef struct RAIL_PacketTimeStamp { */ uint16_t totalPacketBytes; /** - * A RAIL_PacketTimePosition_t value specifying the packet position + * A \ref RAIL_PacketTimePosition_t value specifying the packet position * to return in the packetTime field. * If this is \ref RAIL_PACKET_TIME_DEFAULT, this field will be * updated with the actual position corresponding to the packetTime @@ -402,18 +399,17 @@ typedef struct RAIL_PacketTimeStamp { */ RAIL_PacketTimePosition_t timePosition; /** - * In RX for EFR32xG25 only : + * In RX for EFR32xG25 only: * A value specifying the on-air duration of the data packet, - * starting with the first bit of the PHR (i.e. end of sync word). - * Preamble and sync word duration are hence excluded. + * starting with the first bit of the PHR (i.e., end of sync word); + * preamble and sync word duration are hence excluded. * - * In Tx for all EFR32 except EFR32xG21 : + * In Tx for all platforms: * A value specifying the on-air duration of the data packet, - * starting at the preamble (i.e. includes preamble, sync word, PHR, payload and FCS). - * This value can be use to compute duty cycles. - * - * At the present time, this field is set to zero for EFR32xG21, - * and also for transmission of auto-ack. + * starting at the preamble (i.e. includes preamble, sync word, PHR, + * payload and FCS). This value can be used to compute duty cycles. + * @note This field is currently valid only for normal transmits but + * not Auto-Ack transmits which set the field to zero. */ RAIL_Time_t packetDurationUs; } RAIL_PacketTimeStamp_t; @@ -470,7 +466,7 @@ typedef struct RAIL_TimerSyncConfig { RAIL_SleepConfig_t sleep; } RAIL_TimerSyncConfig_t; -/// Default timer synchronization configuration +/// Default timer synchronization configuration. #define RAIL_TIMER_SYNC_DEFAULT { \ .prsChannel = RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT, \ .rtccChannel = RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT, \ @@ -503,14 +499,14 @@ typedef struct RAIL_SchedulerInfo { */ uint8_t priority; /** - * The amount of time in us that this operation can slip by into the future + * The amount of time in microseconds that this operation can slip by into the future * and still be run. This time is relative to the start time which may be * the current time for relative transmits. If the scheduler can't start the * operation by this time, it will be considered a failure. */ RAIL_Time_t slipTime; /** - * The transaction time in us for this operation. Since transaction times may + * The transaction time in microseconds for this operation. Since transaction times may * not be known exactly, use a minimum or an expected * guess for this time. The scheduler will use the value entered here to look * for overlaps between low-priority and high-priority tasks and attempt to @@ -519,19 +515,19 @@ typedef struct RAIL_SchedulerInfo { RAIL_Time_t transactionTime; } RAIL_SchedulerInfo_t; -/** Radio Scheduler Status mask*/ +/** Radio Scheduler Status mask within \ref RAIL_SchedulerStatus_t values. */ #define RAIL_SCHEDULER_STATUS_MASK 0x0FU -/** Radio Scheduler Status shift*/ +/** Radio Scheduler Status shift within \ref RAIL_SchedulerStatus_t values. */ #define RAIL_SCHEDULER_STATUS_SHIFT 0 -/** Radio Scheduler Task mask*/ +/** Radio Scheduler Task mask within \ref RAIL_SchedulerStatus_t values. */ #define RAIL_SCHEDULER_TASK_MASK 0xF0U -/** Radio Scheduler Task shift*/ +/** Radio Scheduler Task shift within \ref RAIL_SchedulerStatus_t values. */ #define RAIL_SCHEDULER_TASK_SHIFT 4 /** * @enum RAIL_SchedulerStatus_t - * @brief Multiprotocol scheduler status returned by RAIL_GetSchedulerStatus(). + * @brief Multiprotocol scheduler status returned by \ref RAIL_GetSchedulerStatus(). * * \ref Multiprotocol scheduler status is a combination of the upper 4 bits which * constitute the type of scheduler task and the lower 4 bits which constitute @@ -557,7 +553,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL = (3U << RAIL_SCHEDULER_STATUS_SHIFT), /** * Calling the RAIL API associated with the Radio scheduler task returned - * an error code. See \ref RAIL_GetSchedulerStatus or \ref RAIL_GetSchedulerStatusAlt + * an error code. See \ref RAIL_GetSchedulerStatus() or \ref RAIL_GetSchedulerStatusAlt() * for more information about \ref RAIL_Status_t status. */ RAIL_SCHEDULER_STATUS_TASK_FAIL = (4U << RAIL_SCHEDULER_STATUS_SHIFT), @@ -626,7 +622,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol scheduled TX scheduling error. */ RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_TX | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartScheduledTx() operation interrupted */ + /** \ref RAIL_StartScheduledTx() operation interrupted. */ RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_TX | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), @@ -636,7 +632,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol instantaneous TX scheduling error. */ RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_TX | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartTx() operation interrupted */ + /** \ref RAIL_StartTx() operation interrupted. */ RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_TX | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), @@ -646,7 +642,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol single CSMA transmit scheduling error. */ RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartCcaCsmaTx() operation interrupted */ + /** \ref RAIL_StartCcaCsmaTx() operation interrupted. */ RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), @@ -656,7 +652,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol single LBT transmit scheduling error. */ RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartCcaLbtTx() operation interrupted */ + /** \ref RAIL_StartCcaLbtTx() operation interrupted. */ RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), @@ -669,7 +665,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol scheduled CSMA transmit scheduling error. */ RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartScheduledCcaCsmaTx() operation interrupted */ + /** \ref RAIL_StartScheduledCcaCsmaTx() operation interrupted. */ RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), @@ -682,7 +678,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol scheduled LBT transmit scheduling error. */ RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartScheduledCcaLbtTx() operation interrupted */ + /** \ref RAIL_StartScheduledCcaLbtTx() operation interrupted. */ RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), @@ -692,7 +688,7 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol stream transmit scheduling error. */ RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_TX_STREAM | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartTxStream() operation interrupted */ + /** \ref RAIL_StartTxStream() operation interrupted. */ RAIL_SCHEDULER_TX_STREAM_INTERRUPTED = (RAIL_SCHEDULER_TASK_TX_STREAM | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), @@ -702,77 +698,77 @@ RAIL_ENUM(RAIL_SchedulerStatus_t) { /** Multiprotocol RSSI average scheduling error. */ RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartAverageRssi() operation interrupted */ + /** \ref RAIL_StartAverageRssi() operation interrupted. */ RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_SCHEDULER_STATUS_NO_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_NO_ERROR) -#define RAIL_SCHEDULER_STATUS_UNSUPPORTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_UNSUPPORTED) -#define RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED) -#define RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL) -#define RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL) -#define RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL) -#define RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL) -#define RAIL_SCHEDULER_STATUS_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_INTERNAL_ERROR) - -#define RAIL_SCHEDULER_TASK_EMPTY ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_EMPTY) -#define RAIL_SCHEDULER_TASK_SCHEDULED_RX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_RX) -#define RAIL_SCHEDULER_TASK_SCHEDULED_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX) -#define RAIL_SCHEDULER_TASK_SINGLE_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_TX) -#define RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX) -#define RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX) -#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX) -#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX) -#define RAIL_SCHEDULER_TASK_TX_STREAM ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_TX_STREAM) -#define RAIL_SCHEDULER_TASK_AVERAGE_RSSI ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_AVERAGE_RSSI) - -#define RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED) -#define RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED) -#define RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED) -#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED) -#define RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED) -#define RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR) -#define RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_TX_STREAM_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERRUPTED) -#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR) -#define RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED) +#define RAIL_SCHEDULER_STATUS_NO_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_NO_ERROR) +#define RAIL_SCHEDULER_STATUS_UNSUPPORTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_UNSUPPORTED) +#define RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED) +#define RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL) +#define RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL) +#define RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL) +#define RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL) +#define RAIL_SCHEDULER_STATUS_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_INTERNAL_ERROR) + +#define RAIL_SCHEDULER_TASK_EMPTY ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_EMPTY) +#define RAIL_SCHEDULER_TASK_SCHEDULED_RX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_RX) +#define RAIL_SCHEDULER_TASK_SCHEDULED_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX) +#define RAIL_SCHEDULER_TASK_SINGLE_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_TX) +#define RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX) +#define RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX) +#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX) +#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX) +#define RAIL_SCHEDULER_TASK_TX_STREAM ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_TX_STREAM) +#define RAIL_SCHEDULER_TASK_AVERAGE_RSSI ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_AVERAGE_RSSI) + +#define RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED) +#define RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED) +#define RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED) +#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED) +#define RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED) +#define RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR) +#define RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_TX_STREAM_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERRUPTED) +#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR) +#define RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_TaskType_t * @brief Multiprotocol radio operation task types, used with - * RAIL_SetTaskPriority. + * \ref RAIL_SetTaskPriority(). */ RAIL_ENUM(RAIL_TaskType_t) { - /** Indicate a task started using RAIL_StartRx */ + /** Indicate a task started using \ref RAIL_StartRx(). */ RAIL_TASK_TYPE_START_RX = 0, - /** Indicate a task started functions other than RAIL_StartRx */ + /** Indicate a task started functions other than \ref RAIL_StartRx(). */ RAIL_TASK_TYPE_OTHER = 1, }; @@ -800,155 +796,154 @@ RAIL_ENUM(RAIL_TaskType_t) { RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { // RX Event Bit Shifts - /** Shift position of \ref RAIL_EVENT_RSSI_AVERAGE_DONE bit */ + /** Shift position of \ref RAIL_EVENT_RSSI_AVERAGE_DONE bit. */ RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT = 0, - /** Shift position of \ref RAIL_EVENT_RX_ACK_TIMEOUT bit */ + /** Shift position of \ref RAIL_EVENT_RX_ACK_TIMEOUT bit. */ RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT = 1, - /** Shift position of \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL bit */ + /** Shift position of \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL bit. */ RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT = 2, - /** Shift position of \ref RAIL_EVENT_RX_PACKET_RECEIVED bit */ + /** Shift position of \ref RAIL_EVENT_RX_PACKET_RECEIVED bit. */ RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT = 3, - /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_LOST bit */ + /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_LOST bit. */ RAIL_EVENT_RX_PREAMBLE_LOST_SHIFT = 4, - /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_DETECT bit */ + /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_DETECT bit. */ RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT = 5, - /** Shift position of \ref RAIL_EVENT_RX_SYNC1_DETECT bit */ + /** Shift position of \ref RAIL_EVENT_RX_SYNC1_DETECT bit. */ RAIL_EVENT_RX_SYNC1_DETECT_SHIFT = 6, - /** Shift position of \ref RAIL_EVENT_RX_SYNC2_DETECT bit */ + /** Shift position of \ref RAIL_EVENT_RX_SYNC2_DETECT bit. */ RAIL_EVENT_RX_SYNC2_DETECT_SHIFT = 7, - /** Shift position of \ref RAIL_EVENT_RX_FRAME_ERROR bit */ + /** Shift position of \ref RAIL_EVENT_RX_FRAME_ERROR bit. */ RAIL_EVENT_RX_FRAME_ERROR_SHIFT = 8, - /** Shift position of \ref RAIL_EVENT_RX_FIFO_FULL bit */ + /** Shift position of \ref RAIL_EVENT_RX_FIFO_FULL bit. */ RAIL_EVENT_RX_FIFO_FULL_SHIFT = 9, - /** Shift position of \ref RAIL_EVENT_RX_FIFO_OVERFLOW bit */ + /** Shift position of \ref RAIL_EVENT_RX_FIFO_OVERFLOW bit. */ RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT = 10, - /** Shift position of \ref RAIL_EVENT_RX_ADDRESS_FILTERED bit */ + /** Shift position of \ref RAIL_EVENT_RX_ADDRESS_FILTERED bit. */ RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT = 11, - /** Shift position of \ref RAIL_EVENT_RX_TIMEOUT bit */ + /** Shift position of \ref RAIL_EVENT_RX_TIMEOUT bit. */ RAIL_EVENT_RX_TIMEOUT_SHIFT = 12, - /** Shift position of \ref RAIL_EVENT_SCHEDULED_RX_STARTED bit */ + /** Shift position of \ref RAIL_EVENT_SCHEDULED_RX_STARTED bit. */ RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT = 13, - /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_END bit */ + /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_END bit. */ RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT = 14, - /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_MISSED bit */ + /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_MISSED bit. */ RAIL_EVENT_RX_SCHEDULED_RX_MISSED_SHIFT = 15, - /** Shift position of \ref RAIL_EVENT_RX_PACKET_ABORTED bit */ + /** Shift position of \ref RAIL_EVENT_RX_PACKET_ABORTED bit. */ RAIL_EVENT_RX_PACKET_ABORTED_SHIFT = 16, - /** Shift position of \ref RAIL_EVENT_RX_FILTER_PASSED bit */ + /** Shift position of \ref RAIL_EVENT_RX_FILTER_PASSED bit. */ RAIL_EVENT_RX_FILTER_PASSED_SHIFT = 17, - /** Shift position of \ref RAIL_EVENT_RX_TIMING_LOST bit */ + /** Shift position of \ref RAIL_EVENT_RX_TIMING_LOST bit. */ RAIL_EVENT_RX_TIMING_LOST_SHIFT = 18, - /** Shift position of \ref RAIL_EVENT_RX_TIMING_DETECT bit */ + /** Shift position of \ref RAIL_EVENT_RX_TIMING_DETECT bit. */ RAIL_EVENT_RX_TIMING_DETECT_SHIFT = 19, - /** Shift position of \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE bit */ + /** Shift position of \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE bit. */ RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT = 20, - /** Shift position of \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND bit */ + /** Shift position of \ref RAIL_EVENT_RX_DUTY_CYCLE_RX_END bit. */ + RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT = RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT, + /** Shift position of \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND bit. */ RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT = 21, + /** Shift position of \ref RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT bit. */ + RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT = RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT, + /** Shift position of \ref RAIL_EVENT_MFM_TX_BUFFER_DONE bit. */ + RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT = RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT, // TX Event Bit Shifts - /** Shift position of \ref RAIL_EVENT_ZWAVE_BEAM bit */ + /** Shift position of \ref RAIL_EVENT_ZWAVE_BEAM bit. */ RAIL_EVENT_ZWAVE_BEAM_SHIFT = 22, - /** Shift position of \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY bit */ + /** Shift position of \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY bit. */ RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT = 23, - /** Shift position of \ref RAIL_EVENT_TX_PACKET_SENT bit */ + /** Shift position of \ref RAIL_EVENT_TX_PACKET_SENT bit. */ RAIL_EVENT_TX_PACKET_SENT_SHIFT = 24, - /** Shift position of \ref RAIL_EVENT_TXACK_PACKET_SENT bit */ + /** Shift position of \ref RAIL_EVENT_TXACK_PACKET_SENT bit. */ RAIL_EVENT_TXACK_PACKET_SENT_SHIFT = 25, - /** Shift position of \ref RAIL_EVENT_TX_ABORTED bit */ + /** Shift position of \ref RAIL_EVENT_TX_ABORTED bit. */ RAIL_EVENT_TX_ABORTED_SHIFT = 26, - /** Shift position of \ref RAIL_EVENT_TXACK_ABORTED bit */ + /** Shift position of \ref RAIL_EVENT_TXACK_ABORTED bit. */ RAIL_EVENT_TXACK_ABORTED_SHIFT = 27, - /** Shift position of \ref RAIL_EVENT_TX_BLOCKED bit */ + /** Shift position of \ref RAIL_EVENT_TX_BLOCKED bit. */ RAIL_EVENT_TX_BLOCKED_SHIFT = 28, - /** Shift position of \ref RAIL_EVENT_TXACK_BLOCKED bit */ + /** Shift position of \ref RAIL_EVENT_TXACK_BLOCKED bit. */ RAIL_EVENT_TXACK_BLOCKED_SHIFT = 29, - /** Shift position of \ref RAIL_EVENT_TX_UNDERFLOW bit */ + /** Shift position of \ref RAIL_EVENT_TX_UNDERFLOW bit. */ RAIL_EVENT_TX_UNDERFLOW_SHIFT = 30, - /** Shift position of \ref RAIL_EVENT_TXACK_UNDERFLOW bit */ + /** Shift position of \ref RAIL_EVENT_TXACK_UNDERFLOW bit. */ RAIL_EVENT_TXACK_UNDERFLOW_SHIFT = 31, - /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_CLEAR bit */ + /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_CLEAR bit. */ RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT = 32, - /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_BUSY bit */ + /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_BUSY bit. */ RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT = 33, - /** Shift position of \ref RAIL_EVENT_TX_CCA_RETRY bit */ + /** Shift position of \ref RAIL_EVENT_TX_CCA_RETRY bit. */ RAIL_EVENT_TX_CCA_RETRY_SHIFT = 34, - /** Shift position of \ref RAIL_EVENT_TX_START_CCA bit */ + /** Shift position of \ref RAIL_EVENT_TX_START_CCA bit. */ RAIL_EVENT_TX_START_CCA_SHIFT = 35, - /** Shift position of \ref RAIL_EVENT_TX_STARTED bit */ + /** Shift position of \ref RAIL_EVENT_TX_STARTED bit. */ RAIL_EVENT_TX_STARTED_SHIFT = 36, - /** Shift position of \ref RAIL_EVENT_TX_SCHEDULED_TX_MISSED bit */ + /** Shift position of \ref RAIL_EVENT_SCHEDULED_TX_STARTED bit. */ + RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT = RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_SCHEDULED_TX_MISSED bit. */ RAIL_EVENT_TX_SCHEDULED_TX_MISSED_SHIFT = 37, // Scheduler Event Bit Shifts - /** Shift position of \ref RAIL_EVENT_CONFIG_UNSCHEDULED bit */ + /** Shift position of \ref RAIL_EVENT_CONFIG_UNSCHEDULED bit. */ RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT = 38, - /** Shift position of \ref RAIL_EVENT_CONFIG_SCHEDULED bit */ + /** Shift position of \ref RAIL_EVENT_CONFIG_SCHEDULED bit. */ RAIL_EVENT_CONFIG_SCHEDULED_SHIFT = 39, - /** Shift position of \ref RAIL_EVENT_SCHEDULER_STATUS bit */ + /** Shift position of \ref RAIL_EVENT_SCHEDULER_STATUS bit. */ RAIL_EVENT_SCHEDULER_STATUS_SHIFT = 40, // Other Event Bit Shifts - /** Shift position of \ref RAIL_EVENT_CAL_NEEDED bit */ + /** Shift position of \ref RAIL_EVENT_CAL_NEEDED bit. */ RAIL_EVENT_CAL_NEEDED_SHIFT = 41, - /** Shift position of \ref RAIL_EVENT_RF_SENSED bit */ + /** Shift position of \ref RAIL_EVENT_RF_SENSED bit. */ RAIL_EVENT_RF_SENSED_SHIFT = 42, - /** Shift position of \ref RAIL_EVENT_PA_PROTECTION bit */ + /** Shift position of \ref RAIL_EVENT_PA_PROTECTION bit. */ RAIL_EVENT_PA_PROTECTION_SHIFT = 43, - /** Shift position of \ref RAIL_EVENT_SIGNAL_DETECTED bit */ + /** Shift position of \ref RAIL_EVENT_SIGNAL_DETECTED bit. */ RAIL_EVENT_SIGNAL_DETECTED_SHIFT = 44, - /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_START bit */ + /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_START bit. */ RAIL_EVENT_IEEE802154_MODESWITCH_START_SHIFT = 45, - /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_END bit */ + /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_END bit. */ RAIL_EVENT_IEEE802154_MODESWITCH_END_SHIFT = 46, - /** Shift position of \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD bit */ + /** Shift position of \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD bit. */ RAIL_EVENT_DETECT_RSSI_THRESHOLD_SHIFT = 47, - /** Shift position of \ref RAIL_EVENT_THERMISTOR_DONE bit */ + /** Shift position of \ref RAIL_EVENT_THERMISTOR_DONE bit. */ RAIL_EVENT_THERMISTOR_DONE_SHIFT = 48, - /** Shift position of \ref RAIL_EVENT_TX_BLOCKED_TOO_HOT bit */ + /** Shift position of \ref RAIL_EVENT_TX_BLOCKED_TOO_HOT bit. */ RAIL_EVENT_TX_BLOCKED_TOO_HOT_SHIFT = 49, - /** Shift position of \ref RAIL_EVENT_TEMPERATURE_TOO_HOT bit */ + /** Shift position of \ref RAIL_EVENT_TEMPERATURE_TOO_HOT bit. */ RAIL_EVENT_TEMPERATURE_TOO_HOT_SHIFT = 50, - /** Shift position of \ref RAIL_EVENT_TEMPERATURE_COOL_DOWN bit */ + /** Shift position of \ref RAIL_EVENT_TEMPERATURE_COOL_DOWN bit. */ RAIL_EVENT_TEMPERATURE_COOL_DOWN_SHIFT = 51, - /** Shift position of \ref RAIL_EVENT_USER_MBOX bit */ + /** Shift position of \ref RAIL_EVENT_USER_MBOX bit. */ RAIL_EVENT_USER_MBOX_SHIFT = 52, }; -/** Shift position of \ref RAIL_EVENT_SCHEDULED_TX_STARTED bit */ -#define RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT -/** Shift position of \ref RAIL_EVENT_RX_DUTY_CYCLE_RX_END bit */ -#define RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT -/** Shift position of \ref RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT bit */ -#define RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT -/** Shift position of \ref RAIL_EVENT_MFM_TX_BUFFER_DONE bit */ -#define RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT - // RAIL_Event_t bitmasks -/** A value representing no events */ +/** A value representing no events. */ #define RAIL_EVENTS_NONE 0ULL /** * Occurs when the hardware-averaged RSSI is done in response to - * RAIL_StartAverageRssi() to indicate that the hardware has completed + * \ref RAIL_StartAverageRssi() to indicate that the hardware has completed * averaging. * - * Call RAIL_GetAverageRssi() to get the result. + * Call \ref RAIL_GetAverageRssi() to get the result. */ #define RAIL_EVENT_RSSI_AVERAGE_DONE (1ULL << RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT) /** - * Occurs when the ACK timeout expires while waiting to receive the - * sync word of an expected ACK. If the timeout occurs within packet + * Occurs when the Ack timeout expires while waiting to receive the + * sync word of an expected Ack. If the timeout occurs within packet * reception, this event won't be signaled until after packet - * completion has determined the packet wasn't the expected ACK. + * completion has determined the packet wasn't the expected Ack. * See \ref RAIL_RxPacketDetails_t::isAck for the definition of an - * expected ACK. + * expected Ack. * - * This event only occurs after calling RAIL_ConfigAutoAck() and after + * This event only occurs after calling \ref RAIL_ConfigAutoAck() and after * transmitting a packet with \ref RAIL_TX_OPTION_WAIT_FOR_ACK set. */ #define RAIL_EVENT_RX_ACK_TIMEOUT (1ULL << RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT) @@ -957,9 +952,9 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Keeps occurring as long as the number of bytes in the receive FIFO * exceeds the configured threshold value. * - * Call RAIL_GetRxFifoBytesAvailable() to get the number of + * Call \ref RAIL_GetRxFifoBytesAvailable() to get the number of * bytes available. When using this event, the threshold should be set via - * RAIL_SetRxFifoThreshold(). + * \ref RAIL_SetRxFifoThreshold(). * * How to avoid sticking in the event handler (even in idle state): * 1. Disable the event (via the config events API or the @@ -974,10 +969,10 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Occurs whenever a packet is received with \ref RAIL_RX_PACKET_READY_SUCCESS * or \ref RAIL_RX_PACKET_READY_CRC_ERROR. * - * Call RAIL_GetRxPacketInfo() to get + * Call \ref RAIL_GetRxPacketInfo() to get * basic information about the packet along with a handle to this packet for - * subsequent use with RAIL_PeekRxPacket(), RAIL_GetRxPacketDetails(), - * RAIL_HoldRxPacket(), and RAIL_ReleaseRxPacket() as needed. + * subsequent use with \ref RAIL_PeekRxPacket(), \ref RAIL_GetRxPacketDetails(), + * \ref RAIL_HoldRxPacket(), and \ref RAIL_ReleaseRxPacket() as needed. */ #define RAIL_EVENT_RX_PACKET_RECEIVED (1ULL << RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT) @@ -1083,7 +1078,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_FILTERED * because its address does not match the filtering settings. * - * This event can only occur after calling RAIL_EnableAddressFilter(). + * This event can only occur after calling \ref RAIL_EnableAddressFilter(). */ #define RAIL_EVENT_RX_ADDRESS_FILTERED (1ULL << RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT) @@ -1091,33 +1086,26 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Occurs when an RX event times out. * * This event can only occur if the - * RAIL_StateTiming_t::rxSearchTimeout passed to RAIL_SetStateTiming() is + * RAIL_StateTiming_t::rxSearchTimeout passed to \ref RAIL_SetStateTiming() is * not zero. */ #define RAIL_EVENT_RX_TIMEOUT (1ULL << RAIL_EVENT_RX_TIMEOUT_SHIFT) /** * Occurs when a scheduled RX begins turning on the receiver. - * This event has the same numerical value as RAIL_EVENT_SCHEDULED_TX_STARTED + * This event has the same numerical value as \ref RAIL_EVENT_SCHEDULED_TX_STARTED * because one cannot schedule both RX and TX simultaneously. */ #define RAIL_EVENT_SCHEDULED_RX_STARTED (1ULL << RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT) -/** - * Occurs when a scheduled TX begins turning on the transmitter. - * This event has the same numerical value as RAIL_EVENT_SCHEDULED_RX_STARTED - * because one cannot schedule both RX and TX simultaneously. - */ -#define RAIL_EVENT_SCHEDULED_TX_STARTED (1ULL << RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT) - /** * Occurs when the scheduled RX window ends. * * This event only occurs in response - * to a scheduled receive timeout after calling RAIL_ScheduleRx(). If + * to a scheduled receive timeout after calling \ref RAIL_ScheduleRx(). If * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as false, * this event will occur unless the receive is aborted (due to a call to - * RAIL_Idle() or a scheduler preemption, for instance). If + * \ref RAIL_Idle() or a scheduler preemption, for instance). If * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as true, * any of the \ref RAIL_EVENTS_RX_COMPLETION events occurring will also cause * this event not to occur, since the scheduled receive will end with the @@ -1128,7 +1116,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { #define RAIL_EVENT_RX_SCHEDULED_RX_END (1ULL << RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT) /** - * Occurs when start of a scheduled receive is missed + * Occurs when start of a scheduled receive is missed. * * This can occur if the radio is put to sleep and not woken up with enough time * to configure the scheduled receive event. @@ -1224,15 +1212,15 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Indicate a Data Request is received when using IEEE 802.15.4 * functionality. * - * It occurs when the command byte of an incoming ACK-requesting MAC Control + * It occurs when the command byte of an incoming Ack-requesting MAC Control * frame is for a data request. This callback is called before * the packet is fully received to allow the node to have more time to decide - * whether to indicate a frame is pending in the outgoing ACK. This event only + * whether to indicate a frame is pending in the outgoing Ack. This event only * occurs if the RAIL IEEE 802.15.4 functionality is enabled, but will never - * occur if promiscuous mode is enabled via + * occur if promiscuous mode is enabled via \ref * RAIL_IEEE802154_SetPromiscuousMode(). * - * Call RAIL_IEEE802154_GetAddress() to get the source address of the packet. + * Call \ref RAIL_IEEE802154_GetAddress() to get the source address of the packet. */ #define RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND (1ULL << RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT) @@ -1244,7 +1232,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * This event is used in lieu of \ref RAIL_EVENT_RX_PACKET_RECEIVED, * which is reserved for Z-Wave packets other than Beams. * - * Call RAIL_ZWAVE_GetBeamNodeId() to get the NodeId to which the Beam was + * Call \ref RAIL_ZWAVE_GetBeamNodeId() to get the Node Id to which the Beam was * targeted, which would be either the broadcast id 0xFF or the node's own * single-cast id. * @@ -1265,12 +1253,12 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { #define RAIL_EVENT_MFM_TX_BUFFER_DONE (1ULL << RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT) /** - * Indicate a request for populating Z-Wave LR ACK packet. + * Indicate a request for populating Z-Wave LR Ack packet. * This event only occurs if the RAIL Z-Wave functionality is enabled. * * Following this event, the application must call \ref RAIL_ZWAVE_SetLrAckData() * to populate noise floor, TX power and receive RSSI fields of the Z-Wave - * Long Range ACK packet. + * Long Range Ack packet. */ #define RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND (1ULL << RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT) @@ -1282,9 +1270,9 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * \ref RAIL_EVENT_RX_SYNC2_DETECT, * exactly one of the following events will occur. When one of these events * occurs, a state transition will take place based on the parameter passed to - * RAIL_SetRxTransitions(). The RAIL_StateTransitions_t::success transition + * \ref RAIL_SetRxTransitions(). The \ref RAIL_StateTransitions_t::success transition * will be followed only if the \ref RAIL_EVENT_RX_PACKET_RECEIVED event occurs. - * Any of the other events will trigger the RAIL_StateTransitions_t::error + * Any of the other events will trigger the \ref RAIL_StateTransitions_t::error * transition. */ #define RAIL_EVENTS_RX_COMPLETION (RAIL_EVENT_RX_PACKET_RECEIVED \ @@ -1301,11 +1289,11 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * configured threshold value. * * This event does not occur on initialization or after resetting the transmit - * FIFO with RAIL_ResetFifo(). + * FIFO with \ref RAIL_ResetFifo(). * - * Call RAIL_GetTxFifoSpaceAvailable() to get the + * Call \ref RAIL_GetTxFifoSpaceAvailable() to get the * number of bytes available in the transmit FIFO at the time of the callback - * dispatch. When using this event, the threshold should be set via + * dispatch. When using this event, the threshold should be set via \ref * RAIL_SetTxFifoThreshold(). */ #define RAIL_EVENT_TX_FIFO_ALMOST_EMPTY (1ULL << RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT) @@ -1313,30 +1301,30 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { /** * Occurs after a packet has been transmitted. * - * Call RAIL_GetTxPacketDetails() + * Call \ref RAIL_GetTxPacketDetails() * to get information about the packet that was transmitted. * - * @note RAIL_GetTxPacketDetails() is only valid to call during the time frame - * of the RAIL_Config_t::eventsCallback. + * @note \ref RAIL_GetTxPacketDetails() is only valid to call during the time frame + * of the \ref RAIL_Config_t::eventsCallback. */ #define RAIL_EVENT_TX_PACKET_SENT (1ULL << RAIL_EVENT_TX_PACKET_SENT_SHIFT) /** - * Occurs after an ACK packet has been transmitted. + * Occurs after an Ack packet has been transmitted. * - * Call RAIL_GetTxPacketDetails() + * Call \ref RAIL_GetTxPacketDetails() * to get information about the packet that was transmitted. This event can only occur - * after calling RAIL_ConfigAutoAck(). + * after calling \ref RAIL_ConfigAutoAck(). * - * @note RAIL_GetTxPacketDetails() is only valid to call during the time frame - * of the RAIL_Config_t::eventsCallback. + * @note \ref RAIL_GetTxPacketDetails() is only valid to call during the time frame + * of the \ref RAIL_Config_t::eventsCallback. */ #define RAIL_EVENT_TXACK_PACKET_SENT (1ULL << RAIL_EVENT_TXACK_PACKET_SENT_SHIFT) /** * Occurs when a transmit is aborted by the user. * - * This can happen due to calling RAIL_Idle() or due to a scheduler + * This can happen due to calling \ref RAIL_Idle() or due to a scheduler * preemption. * * @note The Transmit FIFO is left in an indeterminate state and should be @@ -1346,17 +1334,17 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { #define RAIL_EVENT_TX_ABORTED (1ULL << RAIL_EVENT_TX_ABORTED_SHIFT) /** - * Occurs when an ACK transmit is aborted by the user. + * Occurs when an Ack transmit is aborted by the user. * * This event can only - * occur after calling RAIL_ConfigAutoAck(), which can happen due to calling - * RAIL_Idle() or due to a scheduler preemption. + * occur after calling \ref RAIL_ConfigAutoAck(), which can happen due to calling + * \ref RAIL_Idle() or due to a scheduler preemption. */ #define RAIL_EVENT_TXACK_ABORTED (1ULL << RAIL_EVENT_TXACK_ABORTED_SHIFT) /** * Occurs when a transmit is blocked from occurring because - * RAIL_EnableTxHoldOff() was called. + * \ref RAIL_EnableTxHoldOff() was called. * * @note Since the transmit never started, the Transmit FIFO remains intact * after this event -- no packet data was consumed from it. Contrast this @@ -1365,10 +1353,10 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { #define RAIL_EVENT_TX_BLOCKED (1ULL << RAIL_EVENT_TX_BLOCKED_SHIFT) /** - * Occurs when an ACK transmit is blocked from occurring because - * RAIL_EnableTxHoldOff() was called. + * Occurs when an Ack transmit is blocked from occurring because + * \ref RAIL_EnableTxHoldOff() was called. * - * This event can only occur after calling RAIL_ConfigAutoAck(). + * This event can only occur after calling \ref RAIL_ConfigAutoAck(). */ #define RAIL_EVENT_TXACK_BLOCKED (1ULL << RAIL_EVENT_TXACK_BLOCKED_SHIFT) @@ -1377,7 +1365,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * * This can happen due to the * transmitted packet specifying an unintended length based on the current - * radio configuration or due to RAIL_WriteTxFifo() calls not keeping up with + * radio configuration or due to \ref RAIL_WriteTxFifo() calls not keeping up with * the transmit rate if the entire packet isn't loaded at once. * * @note The Transmit FIFO is left in an indeterminate state and should be @@ -1387,14 +1375,14 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { #define RAIL_EVENT_TX_UNDERFLOW (1ULL << RAIL_EVENT_TX_UNDERFLOW_SHIFT) /** - * Occurs when the ACK transmit buffer underflows. + * Occurs when the Ack transmit buffer underflows. * * This can happen due to the * transmitted packet specifying an unintended length based on the current - * radio configuration or due to RAIL_WriteAutoAckFifo() not being called at - * all before an ACK transmit. + * radio configuration or due to \ref RAIL_WriteAutoAckFifo() not being called at + * all before an Ack transmit. * - * This event can only occur after calling RAIL_ConfigAutoAck(). + * This event can only occur after calling \ref RAIL_ConfigAutoAck(). */ #define RAIL_EVENT_TXACK_UNDERFLOW (1ULL << RAIL_EVENT_TXACK_UNDERFLOW_SHIFT) @@ -1402,8 +1390,8 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) * succeeds. * - * This event can only happen after calling RAIL_StartCcaCsmaTx() or - * RAIL_StartCcaLbtTx(). + * This event can only happen after calling \ref RAIL_StartCcaCsmaTx() or + * \ref RAIL_StartCcaLbtTx() or their scheduled equivalent. */ #define RAIL_EVENT_TX_CHANNEL_CLEAR (1ULL << RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT) @@ -1411,8 +1399,8 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) * fails. * - * This event can only happen after calling RAIL_StartCcaCsmaTx() or - * RAIL_StartCcaLbtTx(). + * This event can only happen after calling \ref RAIL_StartCcaCsmaTx() or + * \ref RAIL_StartCcaLbtTx() or their scheduled equivalent. * * @note Since the transmit never started, the Transmit FIFO remains intact * after this event -- no packet data was consumed from it. @@ -1426,7 +1414,8 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * * This event can occur multiple times based on the configuration * of the ongoing CSMA or LBT transmission. It can only happen after - * calling RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(). + * calling \ref RAIL_StartCcaCsmaTx() or \ref RAIL_StartCcaLbtTx() + * or their scheduled equivalent. */ #define RAIL_EVENT_TX_CCA_RETRY (1ULL << RAIL_EVENT_TX_CCA_RETRY_SHIFT) @@ -1438,8 +1427,8 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * the \ref RAIL_StateTiming_t::idleToRx time (subject to * \ref RAIL_MINIMUM_TRANSITION_US). It can * occur multiple times based on the configuration of the ongoing CSMA or LBT - * transmission. It can only happen after calling RAIL_StartCcaCsmaTx() - * or RAIL_StartCcaLbtTx(). + * transmission. It can only happen after calling \ref RAIL_StartCcaCsmaTx() + * or \ref RAIL_StartCcaLbtTx() or their scheduled equivalent. */ #define RAIL_EVENT_TX_START_CCA (1ULL << RAIL_EVENT_TX_START_CCA_SHIFT) @@ -1450,9 +1439,9 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * retrieved by calling \ref RAIL_GetTxTimePreambleStart() passing \ref * RAIL_TX_STARTED_BYTES for its totalPacketBytes parameter. * - * @note This event does not apply to ACK transmits. Currently there + * @note This event does not apply to Ack transmits. Currently there * is no equivalent event or timestamp captured for the start of an - * ACK transmit. + * Ack transmit. */ #define RAIL_EVENT_TX_STARTED (1ULL << RAIL_EVENT_TX_STARTED_SHIFT) @@ -1462,6 +1451,13 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { */ #define RAIL_TX_STARTED_BYTES 0U +/** + * Occurs when a scheduled TX begins turning on the transmitter. + * This event has the same numerical value as \ref RAIL_EVENT_SCHEDULED_RX_STARTED + * because one cannot schedule both RX and TX simultaneously. + */ +#define RAIL_EVENT_SCHEDULED_TX_STARTED (1ULL << RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT) + /** * Occurs when the start of a scheduled transmit is missed * @@ -1478,10 +1474,10 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * packet. After a \ref RAIL_STATUS_NO_ERROR return value * from one of the transmit functions, exactly one of the following * events will occur. When one of these events occurs, a state transition - * takes place based on the parameter passed to RAIL_SetTxTransitions(). + * takes place based on the parameter passed to \ref RAIL_SetTxTransitions(). * The RAIL_StateTransitions_t::success transition will be followed only * if the \ref RAIL_EVENT_TX_PACKET_SENT event occurs. Any of the other - * events will trigger the RAIL_StateTransitions_t::error transition. + * events will trigger the \ref RAIL_StateTransitions_t::error transition. */ #define RAIL_EVENTS_TX_COMPLETION (RAIL_EVENT_TX_PACKET_SENT \ | RAIL_EVENT_TX_ABORTED \ @@ -1492,11 +1488,11 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { /** * A mask representing all events that determine the end of a transmitted - * ACK packet. After an ACK-requesting receive, exactly one of the + * Ack packet. After an Ack-requesting receive, exactly one of the * following events will occur. When one of these events occurs, a state * transition takes place based on the RAIL_AutoAckConfig_t::rxTransitions - * passed to RAIL_ConfigAutoAck(). The receive transitions are used because the - * transmitted ACK packet is considered a part of the ACK-requesting received + * passed to \ref RAIL_ConfigAutoAck(). The receive transitions are used because the + * transmitted Ack packet is considered a part of the Ack-requesting received * packet. The RAIL_StateTransitions_t::success transition will be followed * only if the \ref RAIL_EVENT_TXACK_PACKET_SENT event occurs. Any of the other * events will trigger the RAIL_StateTransitions_t::error transition. @@ -1513,7 +1509,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * * This event will occur in dynamic multiprotocol scenarios each * time a protocol is shutting down. When it does occur, it will be - * the only event passed to RAIL_Config_t::eventsCallback. Therefore, + * the only event passed to \ref RAIL_Config_t::eventsCallback. Therefore, * to optimize protocol switch time, this event should be handled * among the first in that callback, and then the application can return * immediately. @@ -1528,7 +1524,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * * This event will occur in dynamic multiprotocol scenarios each time * a protocol is starting up. When it does occur, it will - * be the only event passed to RAIL_Config_t::eventsCallback. Therefore, in + * be the only event passed to \ref RAIL_Config_t::eventsCallback. Therefore, in * order to optimize protocol switch time, this event should be handled among * the first in that callback, and then the application can return immediately. * @@ -1540,15 +1536,15 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { /** * Occurs when the scheduler has a status to report. * - * The exact status can be found with RAIL_GetSchedulerStatus(). + * The exact status can be found with \ref RAIL_GetSchedulerStatus(). * See \ref RAIL_SchedulerStatus_t for more details. When this event - * does occur, it will be the only event passed to RAIL_Config_t::eventsCallback. + * does occur, it will be the only event passed to \ref RAIL_Config_t::eventsCallback. * Therefore, to optimize protocol switch time, this event should * be handled among the first in that callback, and then the application * can return immediately. * - * @note RAIL_GetSchedulerStatus() is only valid to call during the time frame - * of the RAIL_Config_t::eventsCallback. + * @note \ref RAIL_GetSchedulerStatus() is only valid to call during the time frame + * of the \ref RAIL_Config_t::eventsCallback. * * @note: To minimize protocol switch time, Silicon Labs recommends this event * event being turned off unless it is used. @@ -1561,15 +1557,14 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { * Occurs when the application needs to run a calibration, as * determined by the RAIL library. * - * The application determines the opportune time to call RAIL_Calibrate(). + * The application determines the opportune time to call \ref RAIL_Calibrate(). */ #define RAIL_EVENT_CAL_NEEDED (1ULL << RAIL_EVENT_CAL_NEEDED_SHIFT) /** * Occurs when RF energy is sensed from the radio. This event can be used as - * an alternative to the callback passed as \ref RAIL_RfSense_CallbackPtr_t. - * - * Alternatively, the application can poll using \ref RAIL_IsRfSensed(). + * an alternative to the callback passed as \ref RAIL_RfSense_CallbackPtr_t + * or the application polling with \ref RAIL_IsRfSensed(). * * @note This event will not occur when waking up from EM4. Prefer * \ref RAIL_IsRfSensed() when waking from EM4. @@ -1582,8 +1577,8 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { #define RAIL_EVENT_PA_PROTECTION (1ULL << RAIL_EVENT_PA_PROTECTION_SHIFT) /** - * Occurs after enabling the signal detection using \ref RAIL_BLE_EnableSignalDetection - * or \ref RAIL_IEEE802154_EnableSignalDetection when a signal is detected. + * Occurs after enabling the signal detection using \ref RAIL_BLE_EnableSignalDetection() + * or \ref RAIL_IEEE802154_EnableSignalDetection() when a signal is detected. * This is only used on platforms that support signal identifier, where * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER or * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER is true. @@ -1628,7 +1623,7 @@ RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { /** * Occurs when a Tx has been blocked because of temperature exceeding * the safety threshold. - * @deprecated + * @deprecated but reserved for possible future use. */ #define RAIL_EVENT_TX_BLOCKED_TOO_HOT (1ULL << RAIL_EVENT_TX_BLOCKED_TOO_HOT_SHIFT) @@ -1736,7 +1731,7 @@ typedef int16_t RAIL_TxPower_t; #define RAIL_TX_POWER_DBM_SCALING_FACTOR 10 /** - * Raw power levels used directly by the RAIL_Get/SetTxPower API where a higher + * Raw power levels used directly by \ref RAIL_GetTxPower() and \ref RAIL_SetTxPower() where a higher * numerical value corresponds to a higher output power. These are referred to * as 'raw (values/units)'. On EFR32, they can range from one of \ref * RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MIN, or @@ -1748,27 +1743,27 @@ typedef int16_t RAIL_TxPower_t; typedef uint8_t RAIL_TxPowerLevel_t; /** - * Invalid RAIL_TxPowerLevel_t value returned when an error occurs - * with RAIL_GetTxPower. + * Invalid \ref RAIL_TxPowerLevel_t value returned when an error occurs + * with \ref RAIL_GetTxPower(). */ #define RAIL_TX_POWER_LEVEL_INVALID (255U) /** - * Sentinel value that can be passed to RAIL_SetTxPower to set + * Sentinel value that can be passed to \ref RAIL_SetTxPower() to set * the highest power level available on the current PA, regardless * of which one is selected. */ #define RAIL_TX_POWER_LEVEL_MAX (254U) /** - * PA power setting used directly by the \ref RAIL_GetPaPowerSetting() and - * \ref RAIL_SetPaPowerSetting() APIs which is decoded to the actual + * PA power setting used directly by \ref RAIL_GetPaPowerSetting() and + * \ref RAIL_SetPaPowerSetting() which is decoded to the actual * hardware register value(s). */ typedef uint32_t RAIL_PaPowerSetting_t; /** - * Returned by \ref RAIL_GetPaPowerSetting when the device does + * Returned by \ref RAIL_GetPaPowerSetting() when the device does * not support the dBm to power setting mapping table. */ #define RAIL_TX_PA_POWER_SETTING_UNSUPPORTED (0U) @@ -1831,12 +1826,12 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { * PA for all Sub-GHz dBm values in range, using \ref * RAIL_PaPowerSetting_t table. * Only supported on platforms with \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE (e.g. EFR32xG25). + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE (e.g., EFR32xG25). */ RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE = 5U, /** * High-power Sub-GHz amplifier (Class D mode) - * Supported on FR32xG23 and EFR32xG28. + * Supported on EFR32xG23 and EFR32xG28. * Not supported other Sub-GHz-incapable platforms or those with \ref * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. */ @@ -1873,13 +1868,13 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { * RAIL_PaPowerSetting_t table. * Supported only on platforms with both \ref * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE and \ref - * RAIL_SUPPORTS_OFDM_PA (e.g. EFR32xG25). + * RAIL_SUPPORTS_OFDM_PA (e.g., EFR32xG25). */ RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE = 11U, /** @deprecated Please use \ref RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE instead. */ RAIL_TX_POWER_MODE_OFDM_PA = RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE, - /** Invalid amplifier Selection */ - RAIL_TX_POWER_MODE_NONE // Must be last + /** Invalid amplifier Selection. Must be last. */ + RAIL_TX_POWER_MODE_NONE }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -1890,7 +1885,7 @@ RAIL_ENUM(RAIL_TxPowerMode_t) { /** * @def RAIL_TX_POWER_MODE_NAMES - * @brief The names of the TX power modes + * @brief The names of the TX power modes. * * A list of the names for the TX power modes on EFR32 parts. This * macro is useful for test applications and debugging output. @@ -1925,16 +1920,16 @@ typedef struct RAIL_TxPowerConfig { * Battery supply ~ 3300 mV (3.3 V) */ uint16_t voltage; - /** The amount of time to spend ramping for TX in uS. */ + /** The amount of time to spend ramping for TX in microseconds. */ uint16_t rampTime; } RAIL_TxPowerConfig_t; /** Convenience macro for any OFDM mapping table mode. */ #define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_OFDM(x) \ - (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE)) + ((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) /** Convenience macro for any Sub-GHz mapping table mode. */ #define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_SUBGIG(x) \ - (((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) + ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) /** Convenience macro for any OFDM mode. */ #define RAIL_POWER_MODE_IS_ANY_OFDM(x) \ RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_OFDM(x) @@ -1966,13 +1961,14 @@ typedef const uint32_t *RAIL_RadioConfig_t; */ typedef struct RAIL_FrameType { /** - * A pointer to an array of frame lengths for each frame type. The length of this - * array should be equal to the number of frame types. The array that - * frameLen points to should not change location or be modified. + * A pointer to an array of frame byte lengths for each frame type. + * The number of elements in this array should be equal to the number of + * frame types. The memory to which frameLen points should not + * change location or be modified. */ uint16_t *frameLen; /** - * Zero-indexed location of the byte containing the frame type field. + * Zero-indexed byte offset location of the byte containing the frame type field. */ uint8_t offset; /** @@ -1986,7 +1982,7 @@ typedef struct RAIL_FrameType { /** * A bitmask that marks if each frame is valid or should be filtered. Frame type * 0 corresponds to the lowest bit in isValid. If the frame is filtered, a - * RAIL_EVENT_RX_PACKET_ABORTED will be raised. + * \ref RAIL_EVENT_RX_PACKET_ABORTED will be raised. */ uint8_t isValid; /** @@ -1998,9 +1994,9 @@ typedef struct RAIL_FrameType { /** * @def RAIL_SETFIXEDLENGTH_INVALID - * @brief An invalid return value when calling RAIL_SetFixedLength(). + * @brief An invalid return value when calling \ref RAIL_SetFixedLength(). * - * An invalid return value when calling RAIL_SetFixedLength() while the radio is + * An invalid return value when calling \ref RAIL_SetFixedLength() while the radio is * not in fixed-length mode. */ #define RAIL_SETFIXEDLENGTH_INVALID (0xFFFFU) @@ -2015,7 +2011,7 @@ typedef struct RAIL_ChannelConfigEntryAttr RAIL_ChannelConfigEntryAttr_t; /** * @enum RAIL_ChannelConfigEntryType_t * @brief Define if the channel support using concurrent PHY during channel - * hopping. RAIL_RX_CHANNEL_HOPPING_MODE_CONC and RAIL_RX_CHANNEL_HOPPING_MODE_VT + * hopping. \ref RAIL_RX_CHANNEL_HOPPING_MODE_CONC and \ref RAIL_RX_CHANNEL_HOPPING_MODE_VT * can only be used if the channel supports it. */ RAIL_ENUM(RAIL_ChannelConfigEntryType_t) { @@ -2066,18 +2062,9 @@ typedef struct RAIL_AlternatePhy { uint16_t minBaseIf_kHz; /** Indicates that OFDM modem is used by this alternate PHY. */ bool isOfdmModem; - /** rate Info of the alternate PHY. */ + /** Rate info of the alternate PHY. */ uint32_t rateInfo; - /** - * AGC_CTRL1 configuration for CCA with hw modem. - * Concurrent phy's AGC CCA-related registers are configured for CCA with - * OFDM modem. To perform a CCA with hw modem, AGC CTRL1 and CTRL7 need to - * be reconfigured. - * CTRL7_SUBPERIOD bit is set to 0 before the CCA and retored to 1 after. - * CTRL1 is reconfigured using hwModemAgcCtrl1 before the CCA and restore - * after using pSeqFrcConfig->agcCtrl1 where ofdm MODEM CCA configurations - * have been stored. - */ + /** Used to adjust the AGC for CCA between hard and soft modems. */ uint32_t hwModemAgcCtrl1; } RAIL_AlternatePhy_t; @@ -2122,8 +2109,8 @@ typedef struct RAIL_ChannelConfigEntry { /** to align to 32-bit boundary. */ uint8_t reserved[3]; /** - * Array containing information according to the protocolId value, - * first byte of this array. The first 2 fields are common to all + * Array containing information according to the \ref RAIL_PtiProtocol_t in + * the first byte of this array. The first 2 fields are common to all * protocols and accessible by RAIL, others are ignored by RAIL * and only used by the application. Common fields are listed in * \ref RAIL_StackInfoCommon_t. @@ -2135,11 +2122,11 @@ typedef struct RAIL_ChannelConfigEntry { /// @struct RAIL_ChannelConfig_t /// @brief A channel configuration structure, which defines the channel meaning -/// when a channel number is passed into a RAIL function, e.g., RAIL_StartTx() -/// and RAIL_StartRx(). +/// when a channel number is passed into a RAIL function, e.g., \ref RAIL_StartTx() +/// and \ref RAIL_StartRx(). /// -/// A RAIL_ChannelConfig_t structure defines the channel scheme that an -/// application uses when registered in RAIL_ConfigChannels(). +/// A \ref RAIL_ChannelConfig_t structure defines the channel scheme that an +/// application uses when registered in \ref RAIL_ConfigChannels(). /// /// These are a few examples of different channel configurations: /// @code{.c} @@ -2350,9 +2337,9 @@ typedef struct RAIL_ChannelConfig { * channel entries back to base configuration. */ RAIL_RadioConfig_t phyConfigDeltaSubtract; - /** Pointer to an array of RAIL_ChannelConfigEntry_t entries. */ + /** Pointer to an array of \ref RAIL_ChannelConfigEntry_t entries. */ const RAIL_ChannelConfigEntry_t *configs; - /** Number of RAIL_ChannelConfigEntry_t entries. */ + /** Number of \ref RAIL_ChannelConfigEntry_t entries. */ uint32_t length; /** Signature for this structure. Only used on modules. */ uint32_t signature; @@ -2375,12 +2362,12 @@ typedef struct RAIL_ChannelMetadata { /** * @struct RAIL_StackInfoCommon_t - * @brief StackInfo fields common to all protocols. + * @brief Stack info fields common to all protocols. */ typedef struct RAIL_StackInfoCommon { - /** Same as \ref RAIL_PtiProtocol_t */ + /** Same as \ref RAIL_PtiProtocol_t. */ uint8_t protocolId; - /** PHY Id depending on the protocol_id value */ + /** PHY Id depending on the protocolId value. */ uint8_t phyId; } RAIL_StackInfoCommon_t; @@ -2484,14 +2471,14 @@ RAIL_ENUM(RAIL_PtiProtocol_t) { #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_PTI_PROTOCOL_CUSTOM ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CUSTOM) -#define RAIL_PTI_PROTOCOL_THREAD ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_THREAD) -#define RAIL_PTI_PROTOCOL_BLE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_BLE) -#define RAIL_PTI_PROTOCOL_CONNECT ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CONNECT) -#define RAIL_PTI_PROTOCOL_ZIGBEE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZIGBEE) -#define RAIL_PTI_PROTOCOL_ZWAVE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZWAVE) -#define RAIL_PTI_PROTOCOL_802154 ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_802154) -#define RAIL_PTI_PROTOCOL_SIDEWALK ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_SIDEWALK) +#define RAIL_PTI_PROTOCOL_CUSTOM ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CUSTOM) +#define RAIL_PTI_PROTOCOL_THREAD ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_THREAD) +#define RAIL_PTI_PROTOCOL_BLE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_BLE) +#define RAIL_PTI_PROTOCOL_CONNECT ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CONNECT) +#define RAIL_PTI_PROTOCOL_ZIGBEE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZIGBEE) +#define RAIL_PTI_PROTOCOL_ZWAVE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZWAVE) +#define RAIL_PTI_PROTOCOL_802154 ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_802154) +#define RAIL_PTI_PROTOCOL_SIDEWALK ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_SIDEWALK) #endif//DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group PTI @@ -2525,8 +2512,8 @@ RAIL_ENUM(RAIL_TxDataSource_t) { * Z-Wave). */ TX_MFM_DATA = 1, - /** A count of the choices in this enumeration. */ - RAIL_TX_DATA_SOURCE_COUNT // Must be last + /** A count of the choices in this enumeration. Must be last. */ + RAIL_TX_DATA_SOURCE_COUNT }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -2568,8 +2555,8 @@ RAIL_ENUM(RAIL_RxDataSource_t) { * Only efr32xg23, efr32xg25, or efr32xg28 have this mode. */ RX_DIRECT_SYNCHRONOUS_MODE_DATA = 5, - /** A count of the choices in this enumeration. */ - RAIL_RX_DATA_SOURCE_COUNT // Must be last + /** A count of the choices in this enumeration. Must be last. */ + RAIL_RX_DATA_SOURCE_COUNT }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -2589,7 +2576,7 @@ RAIL_ENUM(RAIL_RxDataSource_t) { * * For Transmit the distinction between \ref RAIL_DataMethod_t::PACKET_MODE * and \ref RAIL_DataMethod_t::FIFO_MODE has become more cosmetic than - * functional, as the RAIL_WriteTxFifo() and RAIL_SetTxFifoThreshold() APIs + * functional, as the \ref RAIL_WriteTxFifo() and \ref RAIL_SetTxFifoThreshold() APIs * and related \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event can be used in * either mode. For Receive the distinction is functionally important because * in \ref RAIL_DataMethod_t::PACKET_MODE rollback occurs automatically for @@ -2605,8 +2592,8 @@ RAIL_ENUM(RAIL_DataMethod_t) { PACKET_MODE = 0, /** FIFO-based data method. */ FIFO_MODE = 1, - /** A count of the choices in this enumeration. */ - RAIL_DATA_METHOD_COUNT // Must be last + /** A count of the choices in this enumeration. Must be last. */ + RAIL_DATA_METHOD_COUNT }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -2744,7 +2731,7 @@ RAIL_ENUM(RAIL_RadioState_t) { #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_RadioStateEfr32_t - * @brief Detailed EFR32 Radio state machine statuses. + * @brief Detailed EFR32 Radio state machine states. */ RAIL_ENUM(RAIL_RadioStateEfr32_t) { /** Radio is off. */ @@ -2773,33 +2760,33 @@ RAIL_ENUM(RAIL_RadioStateEfr32_t) { RAIL_RAC_STATE_TX2RX = 11, /** Radio is preparing a transmission after the previous transmission was ended. */ RAIL_RAC_STATE_TX2TX = 12, - /** Radio is powering down receiver and going to OFF state. */ + /** Radio is powering down and going to OFF state. */ RAIL_RAC_STATE_SHUTDOWN = 13, - /** Radio power-on-reset state (EFR32xG22 and later) */ + /** Radio power-on-reset state (EFR32xG22 and later). */ RAIL_RAC_STATE_POR = 14, /** Invalid Radio state, must be the last entry. */ RAIL_RAC_STATE_NONE }; -#endif//DOXYGEN_SHOULD_SKIP_THIS #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RAC_STATE_OFF ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_OFF) -#define RAIL_RAC_STATE_RXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXWARM) -#define RAIL_RAC_STATE_RXSEARCH ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXSEARCH) -#define RAIL_RAC_STATE_RXFRAME ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXFRAME) -#define RAIL_RAC_STATE_RXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXPD) -#define RAIL_RAC_STATE_RX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2RX) -#define RAIL_RAC_STATE_RXOVERFLOW ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXOVERFLOW) -#define RAIL_RAC_STATE_RX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2TX) -#define RAIL_RAC_STATE_TXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXWARM) -#define RAIL_RAC_STATE_TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX) -#define RAIL_RAC_STATE_TXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXPD) -#define RAIL_RAC_STATE_TX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2RX) -#define RAIL_RAC_STATE_TX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2TX) -#define RAIL_RAC_STATE_SHUTDOWN ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SHUTDOWN) -#define RAIL_RAC_STATE_POR ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_POR) -#define RAIL_RAC_STATE_NONE ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_NONE) +#define RAIL_RAC_STATE_OFF ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_OFF) +#define RAIL_RAC_STATE_RXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXWARM) +#define RAIL_RAC_STATE_RXSEARCH ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXSEARCH) +#define RAIL_RAC_STATE_RXFRAME ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXFRAME) +#define RAIL_RAC_STATE_RXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXPD) +#define RAIL_RAC_STATE_RX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2RX) +#define RAIL_RAC_STATE_RXOVERFLOW ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXOVERFLOW) +#define RAIL_RAC_STATE_RX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2TX) +#define RAIL_RAC_STATE_TXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXWARM) +#define RAIL_RAC_STATE_TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX) +#define RAIL_RAC_STATE_TXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXPD) +#define RAIL_RAC_STATE_TX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2RX) +#define RAIL_RAC_STATE_TX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2TX) +#define RAIL_RAC_STATE_SHUTDOWN ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SHUTDOWN) +#define RAIL_RAC_STATE_POR ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_POR) +#define RAIL_RAC_STATE_NONE ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_NONE) +#endif//DOXYGEN_SHOULD_SKIP_THIS #endif//DOXYGEN_SHOULD_SKIP_THIS /** @@ -2844,20 +2831,20 @@ typedef struct RAIL_StateTransitions { * (e.g., performing CCA) is currently ongoing, and clear otherwise. */ RAIL_ENUM(RAIL_RadioStateDetail_t) { - /** Shift position of \ref RAIL_RF_STATE_DETAIL_IDLE_STATE bit */ - RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT = 0u, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_RX_STATE bit */ - RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT = 1u, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_TX_STATE bit */ - RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT = 2u, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_TRANSITION bit */ - RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT = 3u, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_ACTIVE bit */ - RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT = 4u, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_NO_FRAMES bit */ - RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT = 5u, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_LBT bit */ - RAIL_RF_STATE_DETAIL_LBT_SHIFT = 6u, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_IDLE_STATE bit. */ + RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT = 0, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_RX_STATE bit. */ + RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT = 1, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_TX_STATE bit. */ + RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT = 2, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_TRANSITION bit. */ + RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT = 3, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_ACTIVE bit. */ + RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT = 4, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_NO_FRAMES bit. */ + RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT = 5, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_LBT bit. */ + RAIL_RF_STATE_DETAIL_LBT_SHIFT = 6, }; /** Radio is inactive. */ @@ -3027,9 +3014,9 @@ typedef struct RAIL_TxChannelHoppingConfig { * @brief Stop radio operation options bit mask */ RAIL_ENUM(RAIL_StopMode_t) { - /** Shift position of \ref RAIL_STOP_MODE_ACTIVE bit */ + /** Shift position of \ref RAIL_STOP_MODE_ACTIVE bit. */ RAIL_STOP_MODE_ACTIVE_SHIFT = 0, - /** Shift position of \ref RAIL_STOP_MODE_PENDING bit */ + /** Shift position of \ref RAIL_STOP_MODE_PENDING bit. */ RAIL_STOP_MODE_PENDING_SHIFT = 1, }; @@ -3047,28 +3034,28 @@ RAIL_ENUM(RAIL_StopMode_t) { * @brief Transmit options, in reality a bitmask. */ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { - /** Shift position of \ref RAIL_TX_OPTION_WAIT_FOR_ACK bit */ + /** Shift position of \ref RAIL_TX_OPTION_WAIT_FOR_ACK bit. */ RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT = 0, - /** Shift position of \ref RAIL_TX_OPTION_REMOVE_CRC bit */ + /** Shift position of \ref RAIL_TX_OPTION_REMOVE_CRC bit. */ RAIL_TX_OPTION_REMOVE_CRC_SHIFT = 1, - /** Shift position of \ref RAIL_TX_OPTION_SYNC_WORD_ID bit */ + /** Shift position of \ref RAIL_TX_OPTION_SYNC_WORD_ID bit. */ RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT = 2, - /** Shift position of \ref RAIL_TX_OPTION_ANTENNA0 bit */ + /** Shift position of \ref RAIL_TX_OPTION_ANTENNA0 bit. */ RAIL_TX_OPTION_ANTENNA0_SHIFT = 3, - /** Shift position of \ref RAIL_TX_OPTION_ANTENNA1 bit */ + /** Shift position of \ref RAIL_TX_OPTION_ANTENNA1 bit. */ RAIL_TX_OPTION_ANTENNA1_SHIFT = 4, - /** Shift position of \ref RAIL_TX_OPTION_ALT_PREAMBLE_LEN bit */ + /** Shift position of \ref RAIL_TX_OPTION_ALT_PREAMBLE_LEN bit. */ RAIL_TX_OPTION_ALT_PREAMBLE_LEN_SHIFT = 5, - /** Shift position of \ref RAIL_TX_OPTION_CCA_PEAK_RSSI bit */ + /** Shift position of \ref RAIL_TX_OPTION_CCA_PEAK_RSSI bit. */ RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT = 6, - /** Shift position of \ref RAIL_TX_OPTION_CCA_ONLY bit */ + /** Shift position of \ref RAIL_TX_OPTION_CCA_ONLY bit. */ RAIL_TX_OPTION_CCA_ONLY_SHIFT = 7, - /** Shift position of \ref RAIL_TX_OPTION_RESEND bit */ + /** Shift position of \ref RAIL_TX_OPTION_RESEND bit. */ RAIL_TX_OPTION_RESEND_SHIFT = 8, - /** Shift position of \ref RAIL_TX_OPTION_CONCURRENT_PHY_ID bit */ + /** Shift position of \ref RAIL_TX_OPTION_CONCURRENT_PHY_ID bit. */ RAIL_TX_OPTION_CONCURRENT_PHY_ID_SHIFT = 9, - /** A count of the choices in this enumeration. */ - RAIL_TX_OPTIONS_COUNT // Must be last + /** A count of the choices in this enumeration. Must be last. */ + RAIL_TX_OPTIONS_COUNT }; /** A value representing no options enabled. */ @@ -3078,16 +3065,16 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { #define RAIL_TX_OPTIONS_DEFAULT RAIL_TX_OPTIONS_NONE /** - * An option when auto-ACK has been configured, enabled, and not TX paused, to - * configure whether or not the transmitting node will listen for an ACK + * An option when Auto-Ack has been configured, enabled, and not TX paused, to + * configure whether or not the transmitting node will listen for an Ack * response. - * If this is false, the isAck flag in RAIL_RxPacketDetails_t of a received + * If this is false, the \ref RAIL_RxPacketDetails_t::isAck flag of a received * packet will always be false. - * If auto-ACK is enabled, for instance using \ref RAIL_ConfigAutoAck() or + * If Auto-Ack is enabled, for instance using \ref RAIL_ConfigAutoAck() or * \ref RAIL_IEEE802154_Init(), and if this option is false, the radio * transitions to \ref RAIL_AutoAckConfig_t::txTransitions's * \ref RAIL_StateTransitions_t::success state directly after transmitting a - * packet and does not wait for an ACK. + * packet and does not wait for an Ack. */ #define RAIL_TX_OPTION_WAIT_FOR_ACK (1UL << RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT) @@ -3105,7 +3092,7 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { * * This option should not be used when only one sync word has been configured. * - * @note There are a few special radio configurations (e.g. BLE Viterbi) that do + * @note There are a few special radio configurations (e.g., BLE Viterbi) that do * not support transmitting different sync words. */ #define RAIL_TX_OPTION_SYNC_WORD_ID (1UL << RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT) @@ -3115,7 +3102,7 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { * option is not set or if both antenna options are set, then the transmit * will occur on either antenna depending on the last receive or transmit * selection. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + * \ref Antenna_Control and have been configured via \ref RAIL_ConfigAntenna(). * * @note These TX antenna options do not control the antenna used for * \ref Auto_Ack transmissions, which always occur on the same antenna @@ -3128,7 +3115,7 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { * option is not set or if both antenna options are set, then the transmit * will occur on either antenna depending on the last receive or transmit * selection. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + * \ref Antenna_Control and have been configured via \ref RAIL_ConfigAntenna(). * * @note These TX antenna options do not control the antenna used for * \ref Auto_Ack transmissions, which always occur on the same antenna @@ -3145,20 +3132,20 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { /** * An option to use peak rather than average RSSI energy detected during - * CSMA's RAIL_CsmaConfig_t::ccaDuration or LBT's + * CSMA's \ref RAIL_CsmaConfig_t::ccaDuration or LBT's \ref * RAIL_LbtConfig_t::lbtDuration to determine whether the channel is clear * or busy. This option is only valid when calling one of the CCA transmit - * routines: \ref RAIL_StartCcaCsmaTx, \ref RAIL_StartCcaLbtTx, \ref - * RAIL_StartScheduledCcaCsmaTx, or \ref RAIL_StartScheduledCcaLbtTx. + * routines: \ref RAIL_StartCcaCsmaTx(), \ref RAIL_StartCcaLbtTx(), \ref + * RAIL_StartScheduledCcaCsmaTx(), or \ref RAIL_StartScheduledCcaLbtTx(). */ #define RAIL_TX_OPTION_CCA_PEAK_RSSI (1UL << RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT) /** * An option to only perform the CCA (CSMA/LBT) operation but *not* * automatically transmit if the channel is clear. This option is only valid - * when calling one of the CCA transmit routines: \ref RAIL_StartCcaCsmaTx, - * \ref RAIL_StartCcaLbtTx, \ref RAIL_StartScheduledCcaCsmaTx, or \ref - * RAIL_StartScheduledCcaLbtTx. + * when calling one of the CCA transmit routines: \ref RAIL_StartCcaCsmaTx(), + * \ref RAIL_StartCcaLbtTx(), \ref RAIL_StartScheduledCcaCsmaTx(), or \ref + * RAIL_StartScheduledCcaLbtTx(). * * Application can then use the \ref RAIL_EVENT_TX_CHANNEL_CLEAR to * initiate transmit manually, e.g., giving it the opportunity to adjust @@ -3167,7 +3154,7 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { * @note Configured state transitions to Rx or Idle are suspended during * this CSMA/LBT operation. If packet reception occurs, the radio will * return to the state it was in just prior to the CSMA/LBT operation - * when that reception (including any auto-ACK response) is complete. + * when that reception (including any Auto-Ack response) is complete. */ #define RAIL_TX_OPTION_CCA_ONLY (1UL << RAIL_TX_OPTION_CCA_ONLY_SHIFT) @@ -3206,13 +3193,13 @@ RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { typedef struct RAIL_TxPacketDetails { /** * The timestamp of the transmitted packet in the RAIL timebase, - * filled in by RAIL_GetTxPacketDetails(). + * filled in by \ref RAIL_GetTxPacketDetails(). */ RAIL_PacketTimeStamp_t timeSent; /** - * Indicate whether the transmitted packet was an automatic ACK. In a generic - * sense, an automatic ACK is defined as a packet sent in response to a - * received ACK-requesting frame when auto-ACK is enabled. In a protocol + * Indicate whether the transmitted packet was an automatic Ack. In a generic + * sense, an automatic Ack is defined as a packet sent in response to a + * received Ack-requesting frame when Auto-Ack is enabled. In a protocol * specific sense this definition may be more or less restrictive to match the * specification and you should refer to that protocol's documentation. */ @@ -3224,7 +3211,7 @@ typedef struct RAIL_TxPacketDetails { * @brief Enumerates the possible outcomes of what will occur if a * scheduled TX ends up firing during RX. Because RX and TX can't * happen at the same time, it is up to the user how the TX should be - * handled. This enumeration is passed into RAIL_StartScheduledTx() + * handled. This enumeration is passed into \ref RAIL_StartScheduledTx() * as part of \ref RAIL_ScheduleTxConfig_t. */ RAIL_ENUM(RAIL_ScheduledTxDuringRx_t) { @@ -3367,7 +3354,7 @@ typedef struct RAIL_CsmaConfig { * follow up with a random backoff operation starting at \ref csmaMinBoExp * = 1 for the remaining iterations. */ - uint8_t csmaMinBoExp; + uint8_t csmaMinBoExp; /** * The maximum exponent for CSMA random backoff (2^exp - 1). * It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT and must be greater @@ -3375,26 +3362,28 @@ typedef struct RAIL_CsmaConfig { * \n If both exponents are 0, a non-random fixed backoff of \ref ccaBackoff * duration results. */ - uint8_t csmaMaxBoExp; + uint8_t csmaMaxBoExp; /** * The number of backoff-then-CCA iterations that can fail before reporting * \ref RAIL_EVENT_TX_CHANNEL_BUSY. Typically ranges from 1 to \ref * RAIL_MAX_LBT_TRIES; higher values are disallowed. A value 0 always * transmits immediately without performing CSMA, similar to calling - * RAIL_StartTx(). + * \ref RAIL_StartTx(). */ - uint8_t csmaTries; + uint8_t csmaTries; /** * The CCA RSSI threshold, in dBm, above which the channel is * considered 'busy'. */ - int8_t ccaThreshold; + int8_t ccaThreshold; /** * The backoff unit period in RAIL's microsecond time base. It is * multiplied by the random backoff exponential controlled by \ref * csmaMinBoExp and \ref csmaMaxBoExp to determine the overall backoff - * period. For random backoffs, any value above 511 microseconds will - * be truncated. For fixed backoffs it can go up to 65535 microseconds. + * period. For random backoffs, any value above 32768 microseconds for + * the 'EFR Series 2' and 8192 microseconds for the 'Series 3' will be truncated + * for a single backoff period. Up to 255 backoff periods are supported. + * For fixed backoffs it can go up to 65535 microseconds. */ uint16_t ccaBackoff; /** @@ -3404,7 +3393,7 @@ typedef struct RAIL_CsmaConfig { * * @note Depending on the radio configuration, due to hardware constraints, * the actual duration may be longer. Also, if the requested duration - * is too large for the radio to accommodate, RAIL_StartCcaCsmaTx() + * is too large for the radio to accommodate, \ref RAIL_StartCcaCsmaTx() * will fail returning \ref RAIL_STATUS_INVALID_PARAMETER. */ uint16_t ccaDuration; @@ -3419,11 +3408,11 @@ typedef struct RAIL_CsmaConfig { /** * @def RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA - * @brief RAIL_CsmaConfig_t initializer configuring CSMA per IEEE 802.15.4-2003 - * on 2.4 GHz OSPSK, commonly used by ZigBee. + * @brief \ref RAIL_CsmaConfig_t initializer configuring CSMA per IEEE 802.15.4-2003 + * on 2.4 GHz OSPSK, commonly used by Zigbee. */ #define RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA { \ - /* CSMA per 802.15.4-2003 on 2.4 GHz OSPSK, commonly used by ZigBee */ \ + /* CSMA per 802.15.4-2003 on 2.4 GHz OSPSK, commonly used by Zigbee */ \ .csmaMinBoExp = 3, /* 2^3-1 for 0..7 backoffs on 1st try */ \ .csmaMaxBoExp = 5, /* 2^5-1 for 0..31 backoffs on 3rd+ tries */ \ .csmaTries = 5, /* 5 tries overall (4 re-tries) */ \ @@ -3435,7 +3424,7 @@ typedef struct RAIL_CsmaConfig { /** * @def RAIL_CSMA_CONFIG_SINGLE_CCA - * @brief RAIL_CsmaConfig_t initializer configuring a single CCA prior to TX. + * @brief \ref RAIL_CsmaConfig_t initializer configuring a single CCA prior to TX. * It can be used to as a basis for implementing other channel access schemes * with custom backoff delays. Users can override ccaBackoff with a fixed * delay on each use. @@ -3486,33 +3475,35 @@ typedef struct RAIL_LbtConfig { /** * The minimum backoff random multiplier. */ - uint8_t lbtMinBoRand; + uint8_t lbtMinBoRand; /** * The maximum backoff random multiplier. * It must be greater than or equal to \ref lbtMinBoRand. * \n If both backoff multipliers are identical, a non-random fixed backoff * of \ref lbtBackoff times the multiplier (minimum 1) duration results. */ - uint8_t lbtMaxBoRand; + uint8_t lbtMaxBoRand; /** * The number of LBT iterations that can fail before reporting * \ref RAIL_EVENT_TX_CHANNEL_BUSY. Typically ranges from 1 to \ref * RAIL_MAX_LBT_TRIES; higher values are disallowed. A value 0 always * transmits immediately without performing LBT, similar to calling - * RAIL_StartTx(). + * \ref RAIL_StartTx(). */ - uint8_t lbtTries; + uint8_t lbtTries; /** * The LBT RSSI threshold, in dBm, above which the channel is * considered 'busy'. */ - int8_t lbtThreshold; + int8_t lbtThreshold; /** * The backoff unit period, in RAIL's microsecond time base. It is * multiplied by the random backoff multiplier controlled by \ref * lbtMinBoRand and \ref lbtMaxBoRand to determine the overall backoff - * period. For random backoffs, any value above 511 microseconds will - * be truncated. For fixed backoffs, it can go up to 65535 microseconds. + * period. For random backoffs, any value above 32768 microseconds for + * the 'EFR Series 2' and 8192 microseconds for the 'Series 3' will be truncated + * for a single backoff period. Up to 255 backoff periods are supported. + * For fixed backoffs, it can go up to 65535 microseconds. */ uint16_t lbtBackoff; /** @@ -3520,7 +3511,7 @@ typedef struct RAIL_LbtConfig { * * @note Depending on the radio configuration, due to hardware constraints, * the actual duration may be longer. Also, if the requested duration - * is too large for the radio to accommodate, RAIL_StartCcaLbtTx() + * is too large for the radio to accommodate, \ref RAIL_StartCcaLbtTx() * will fail returning \ref RAIL_STATUS_INVALID_PARAMETER. */ uint16_t lbtDuration; @@ -3537,7 +3528,7 @@ typedef struct RAIL_LbtConfig { /** * @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 - * @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 + * @brief \ref RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 * V2.4.1 for a typical Sub-GHz band. To be practical, users should override * lbtTries and/or lbtTimeout so channel access failure will be reported in a * reasonable time frame rather than the unbounded time frame ETSI defined. @@ -3556,7 +3547,7 @@ typedef struct RAIL_LbtConfig { /** * @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V3_1_0 - * @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 + * @brief \ref RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 * V3.1.0 for a typical Sub-GHz band. To be practical, users should override * lbtTries and/or lbtTimeout so channel access failure will be reported in a * reasonable time frame rather than the unbounded time frame ETSI defined. @@ -3599,9 +3590,9 @@ typedef struct RAIL_SyncWordConfig { * @brief Transmit repeat options, in reality a bitmask. */ RAIL_ENUM_GENERIC(RAIL_TxRepeatOptions_t, uint16_t) { - /** Shift position of \ref RAIL_TX_REPEAT_OPTION_HOP bit */ + /** Shift position of \ref RAIL_TX_REPEAT_OPTION_HOP bit. */ RAIL_TX_REPEAT_OPTION_HOP_SHIFT = 0, - /** Shift position of the \ref RAIL_TX_REPEAT_OPTION_START_TO_START bit */ + /** Shift position of the \ref RAIL_TX_REPEAT_OPTION_START_TO_START bit. */ RAIL_TX_REPEAT_OPTION_START_TO_START_SHIFT = 1, }; @@ -3663,7 +3654,7 @@ typedef struct RAIL_TxRepeatConfig { } delayOrHop; } RAIL_TxRepeatConfig_t; -/// RAIL_TxRepeatConfig_t::iterations initializer configuring infinite +/// \ref RAIL_TxRepeatConfig_t::iterations initializer configuring infinite /// repeated transmissions. #define RAIL_TX_REPEAT_INFINITE_ITERATIONS (0xFFFFU) @@ -3745,8 +3736,8 @@ typedef struct RAIL_AddrConfig { * - For filtering that only uses a single address field. * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you * - For filtering that uses two address fields in a configurations where - * you want the following logic `((Field0, Index0) && (Field1, Index0)) - * || ((Field0, Index1) && (Field1, Index1)) || ...` + * you want the following logic `((Field_0, Index_0) && (Field_1, Index_0)) + * || ((Field_0, Index_1) && (Field_1, Index_1)) || ...` */ uint32_t matchTable; } RAIL_AddrConfig_t; @@ -3824,9 +3815,9 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { * If this is set, RX will still be successful, even if * the CRC does not pass the check. Defaults to false. * - * @note An expected ACK that fails CRC with this option set - * will still be considered the expected ACK, terminating - * the RAIL_AutoAckConfig_t::ackTimeout period. + * @note An expected Ack that fails CRC with this option set + * will still be considered the expected Ack, terminating + * the \ref RAIL_AutoAckConfig_t::ackTimeout period. */ #define RAIL_RX_OPTION_IGNORE_CRC_ERRORS (1UL << RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT) @@ -3837,8 +3828,8 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { * will contain which sync word was detected. Note, this only affects which * sync word(s) are received, but not what each of the sync words actually are. * This feature may not be available on some combinations of chips, PHYs, and - * protocols. Use the compile time symbol RAIL_SUPPORTS_DUAL_SYNC_WORDS or - * the runtime call RAIL_SupportsDualSyncWords() to check whether the + * protocols. Use the compile time symbol \ref RAIL_SUPPORTS_DUAL_SYNC_WORDS or + * the runtime call \ref RAIL_SupportsDualSyncWords() to check whether the * platform supports this feature. Also, DUALSYNC may be incompatible * with certain radio configurations. In these cases, setting this bit will * be ignored. See the data sheet or support team for more details. @@ -3877,7 +3868,7 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { * \ref Auto_Ack receive). If no antenna option is selected, the packet * will be received on the last antenna used for receive or transmit. * Defaults to false. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + * \ref Antenna_Control and have been configured via \ref RAIL_ConfigAntenna(). */ #define RAIL_RX_OPTION_ANTENNA0 (1UL << RAIL_RX_OPTION_ANTENNA0_SHIFT) @@ -3886,7 +3877,7 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { * \ref Auto_Ack receive). If no antenna option is selected, the packet * will be received on the last antenna used for receive or transmit. * Defaults to false. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + * \ref Antenna_Control and have been configured via \ref RAIL_ConfigAntenna(). */ #define RAIL_RX_OPTION_ANTENNA1 (1UL << RAIL_RX_OPTION_ANTENNA1_SHIFT) @@ -3898,7 +3889,7 @@ RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { * reception. This option is only valid when the antenna diversity * field is properly configured via Simplicity Studio. * This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + * \ref Antenna_Control and have been configured via \ref RAIL_ConfigAntenna(). */ #define RAIL_RX_OPTION_ANTENNA_AUTO (RAIL_RX_OPTION_ANTENNA0 | RAIL_RX_OPTION_ANTENNA1) @@ -4185,7 +4176,7 @@ typedef const void *RAIL_RxPacketHandle_t; * completed and awaiting processing, including memory pointers to * its data in the circular receive FIFO buffer. This packet information * refers to remaining packet data that has not already been consumed - * by RAIL_ReadRxFifo(). + * by \ref RAIL_ReadRxFifo(). * * @note Because the receive FIFO buffer is circular, a packet might start * near the end of the buffer and wrap around to the beginning of @@ -4223,7 +4214,7 @@ typedef struct RAIL_RxPacketInfo { /** * @struct RAIL_RxPacketDetails_t - * @brief Received packet details obtained via RAIL_GetRxPacketDetails() + * @brief Received packet details obtained via \ref RAIL_GetRxPacketDetails() * or RAIL_GetRxPacketDetailsAlt(). * * @note Certain details are always available, while others are only available @@ -4249,27 +4240,28 @@ typedef struct RAIL_RxPacketDetails { */ bool crcPassed; /** - * Indicate whether the received packet was the expected ACK. - * It is true for the expected ACK and false otherwise. + * Indicate whether the received packet was the expected Ack. + * It is true for the expected Ack and false otherwise. * * It is always available. * - * An expected ACK is defined as a protocol-correct ACK packet + * An expected Ack is defined as a protocol-correct Ack packet * successfully-received (\ref RAIL_RX_PACKET_READY_SUCCESS or * \ref RAIL_RX_PACKET_READY_CRC_ERROR) and whose sync word was * detected within the * RAIL_AutoAckConfig_t::ackTimeout period following a transmit * which specified \ref RAIL_TX_OPTION_WAIT_FOR_ACK, requested - * an ACK, and auto-ACK is enabled. When true, the ackTimeout + * an Ack, and Auto-Ack is enabled. When true, the ackTimeout * period was terminated so no \ref RAIL_EVENT_RX_ACK_TIMEOUT * will be subsequently posted for the transmit. * - * A "protocol-correct ACK" applies to the 802.15.4 or Z-Wave + * A "protocol-correct Ack" applies to the 802.15.4 or Z-Wave * protocols for which RAIL can discern the frame type and match - * the ACK's sequence number with that of the transmitted frame. + * the Ack's sequence number with that of the transmitted frame. * For other protocols, the first packet successfully-received - * whose sync word was detected within the ackTimeout period is - * considered the expected ACK; upper layers are responsible for + * whose sync word was detected within the \ref + * RAIL_AutoAckConfig_t::ackTimeout period is + * considered the expected Ack; upper layers are responsible for * confirming this. */ bool isAck; @@ -4306,7 +4298,7 @@ typedef struct RAIL_RxPacketDetails { * and the SUN OFDM PHYs. * In BLE cases, a value of 0 marks a 500 kbps packet, a value of 1 marks a 125 * kbps packet, and a value of 2 marks a 1 Mbps packet. - * Also, see \ref RAIL_BLE_ConfigPhyCoded and \ref RAIL_BLE_ConfigPhySimulscan. + * Also, see \ref RAIL_BLE_ConfigPhyCoded() and \ref RAIL_BLE_ConfigPhySimulscan(). * * In SUN OFDM cases, the value corresponds to the numerical value of the * Modulation and Coding Scheme (MCS) level of the last received packet. @@ -4370,14 +4362,14 @@ typedef uint8_t (*RAIL_ConvertLqiCallback_t)(uint8_t lqi, int8_t rssi); /** - * @struct RAIL_AutoLnaBypassConfig_t - * @brief Configures the automatic LNA bypass. + * @struct RAIL_PrsLnaBypassConfig_t + * @brief Configures the automatic PRS LNA bypass. */ -typedef struct RAIL_AutoLnaBypassConfig { +typedef struct RAIL_PrsLnaBypassConfig { /** * Maximum time in microseconds to wait for frame detection after the LNA has - * been bypassed. It must be greater than 0 to enable automatic LNA bypass - * with \ref RAIL_EnableAutoLnaBypass(). + * been bypassed. It must be greater than 0 to enable automatic PRS LNA + * bypass with \ref RAIL_EnablePrsLnaBypass(). */ uint32_t timeoutUs; /** @@ -4406,26 +4398,28 @@ typedef struct RAIL_AutoLnaBypassConfig { */ uint8_t deltaRssiDbm; /** - * GPIO port used for the bypass. - */ - uint8_t port; - /** - * GPIO pin used for the bypass. + * PRS Channel used for the bypass. + * PRS_GetFreeChannel() can be use to find a free channel. Then the signal + * can be routed to GPIO pin and port using PRS_PinOutput(). This allows + * logical operations with other PRS channels and so to adapt to the FEM + * control logic table. Any call to PRS_Combine() with + * \ref RAIL_PrsLnaBypassConfig_t::prsChannel as chA must be done after + * the \ref RAIL_EnablePrsLnaBypass() call. */ - uint8_t pin; + uint8_t prsChannel; /** - * GPIO DOUT configuration for bypass. + * PRS signal polarity for bypass. * - * With a polarity of 1, GPIO DOUT is set to 1 for bypass and 0 for un-bypass. - * with a polarity of 0, GPIO DOUT is set to 0 for bypass and 1 for un-bypass. + * With a polarity of 1, PRS signal is set to 1 for bypass and 0 for un-bypass. + * with a polarity of 0, PRS signal is set to 0 for bypass and 1 for un-bypass. */ bool polarity; -} RAIL_AutoLnaBypassConfig_t; +} RAIL_PrsLnaBypassConfig_t; /** @} */ // end of group Receive /****************************************************************************** - * Auto-ACK Structures + * Auto-Ack Structures *****************************************************************************/ /** * @addtogroup Auto_Ack @@ -4433,50 +4427,50 @@ typedef struct RAIL_AutoLnaBypassConfig { */ /** * @struct RAIL_AutoAckConfig_t - * @brief Enable/disable the auto-ACK algorithm, based on "enable". + * @brief Enable/disable the Auto-Ack algorithm, based on "enable". * - * The structure provides a default state (the "success" of tx/rxTransitions - * when ACKing is enabled) for the radio to return to after an ACK - * operation occurs (transmitting or attempting to receive an ACK), or normal - * state transitions to return to in the case ACKing is - * disabled. Regardless whether the ACK operation was successful, the + * The structure provides a default state (the "success" of TX/RX transitions + * when Acking is enabled) for the radio to return to after an Ack + * operation occurs (transmitting or attempting to receive an Ack), or normal + * state transitions to return to in the case Acking is + * disabled. Regardless whether the Ack operation was successful, the * radio returns to the specified success state. * - * ackTimeout specifies how long to stay in receive and wait for an ACK - * to start (sync detected) before issuing a RAIL_EVENT_RX_ACK_TIMEOUT + * ackTimeout specifies how long to stay in receive and wait for an Ack + * to start (sync detected) before issuing a \ref RAIL_EVENT_RX_ACK_TIMEOUT * event and return to the default state. */ typedef struct RAIL_AutoAckConfig { /** - * Indicate whether auto-ACKing should be enabled or disabled. + * Indicate whether Auto-Acking should be enabled or disabled. */ bool enable; // Unnamed 'uint8_t reserved1[1]' pad byte field here. /** - * Define the RX ACK timeout duration in microseconds up to 65535 - * microseconds maximum. Only applied when auto-ACKing is enabled. - * The ACK timeout timer starts at the completion of a \ref + * Define the RX Ack timeout duration in microseconds up to 65535 + * microseconds maximum. Only applied when Auto-Acking is enabled. + * The Ack timeout timer starts at the completion of a \ref * RAIL_TX_OPTION_WAIT_FOR_ACK transmit and expires only while waiting * for a packet (prior to SYNC detect), triggering \ref * RAIL_EVENT_RX_ACK_TIMEOUT. During packet reception that event is * held off until packet completion and suppressed entirely if the - * received packet is the expected ACK. + * received packet is the expected Ack. */ uint16_t ackTimeout; /** - * State transitions to do after receiving a packet. When auto-ACKing is + * State transitions to do after receiving a packet. When Auto-Acking is * enabled, the "error" transition is always ignored and the radio will - * return to the "success" state after any ACKing sequence + * return to the "success" state after any Acking sequence * (\ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE). - * See \ref RAIL_ConfigAutoAck for more details on this. + * See \ref RAIL_ConfigAutoAck() for more details on this. */ RAIL_StateTransitions_t rxTransitions; /** - * State transitions to do after transmitting a packet. When auto-ACKing is + * State transitions to do after transmitting a packet. When Auto-Acking is * enabled, the "error" transition is always ignored and the radio will - * return to the "success" state after any ACKing sequence + * return to the "success" state after any Acking sequence * (\ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE). - * See \ref RAIL_ConfigAutoAck for more details on this. + * See \ref RAIL_ConfigAutoAck() for more details on this. */ RAIL_StateTransitions_t txTransitions; } RAIL_AutoAckConfig_t; @@ -4531,8 +4525,8 @@ typedef struct RAIL_AntennaConfig { * value specifying the internal default RF path. It is ignored * on EFR32 parts that have only one RF path bonded * out and on EFR32xG28 dual-band OPNs where the appropriate - * RF path is automatically set by RAIL to 0 for 2.4GHZ band - * and 1 for SubGHz band PHYs. On EFR32xG23 and EFR32xG28 + * RF path is automatically set by RAIL to 0 for 2.4 GHz band + * and 1 for Sub-GHz band PHYs. On EFR32xG23 and EFR32xG28 * single-band OPNs where both RF paths are bonded out this can * be set to \ref RAIL_ANTENNA_AUTO to effect internal RF path * diversity on PHYs supporting diversity. This avoids the need @@ -4577,7 +4571,7 @@ typedef struct RAIL_AntennaConfig { * @struct RAIL_HFXOThermistorConfig_t * @brief Configure the port and pin of the thermistor. * - * @note This configuration is OPN dependent. + * @note This configuration is chip OPN dependent. */ typedef struct RAIL_HFXOThermistorConfig { /** @@ -4659,7 +4653,7 @@ typedef uint32_t RAIL_CalMask_t; /** EFR32-specific HFXO compensation bit. * (Ignored if platform lacks \ref RAIL_SUPPORTS_HFXO_COMPENSATION.) */ #define RAIL_CAL_COMPENSATE_HFXO (0x00000004U) -/** EFR32-specific IR calibration bit */ +/** EFR32-specific IR calibration bit. */ #define RAIL_CAL_RX_IRCAL (0x00010000U) /** EFR32-specific Tx IR calibration bit. * (Ignored if platform lacks \ref RAIL_SUPPORTS_OFDM_PA.) */ @@ -4700,7 +4694,7 @@ typedef uint32_t RAIL_CalMask_t; typedef uint32_t RAIL_RxIrCalValues_t[RAIL_MAX_RF_PATHS]; /** - * A define to set all RAIL_RxIrCalValues_t values to uninitialized. + * A define to set all \ref RAIL_RxIrCalValues_t values to uninitialized. * * This define can be used when you have no data to pass to the calibration * routines but wish to compute and save all possible calibrations. @@ -4716,7 +4710,7 @@ typedef uint32_t RAIL_RxIrCalValues_t[RAIL_MAX_RF_PATHS]; * This definition contains the set of persistent calibration values for * OFDM on EFR32. You can set these beforehand and apply them at startup * to save the time required to compute them. Any of these values may be - * set to RAIL_IRCAL_INVALID_VALUE to force the code to compute that + * set to \ref RAIL_CAL_INVALID_VALUE to force the code to compute that * calibration value. * * Only supported on platforms with \ref RAIL_SUPPORTS_OFDM_PA enabled. @@ -4729,7 +4723,7 @@ typedef struct RAIL_TxIrCalValues { } RAIL_TxIrCalValues_t; /** - * A define to set all RAIL_TxIrCalValues_t values to uninitialized. + * A define to set all \ref RAIL_TxIrCalValues_t values to uninitialized. * * This define can be used when you have no data to pass to the calibration * routines but wish to compute and save all possible calibrations. @@ -4746,7 +4740,7 @@ typedef struct RAIL_TxIrCalValues { * This definition contains the set of persistent calibration values for * EFR32. You can set these beforehand and apply them at startup to save the * time required to compute them. Any of these values may be set to - * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value. + * \ref RAIL_CAL_INVALID_VALUE to force the code to compute that calibration value. */ typedef struct RAIL_IrCalValues { /** RX Image Rejection (IR) calibration value(s) */ @@ -4756,7 +4750,7 @@ typedef struct RAIL_IrCalValues { } RAIL_IrCalValues_t; /** - * A define to set all RAIL_IrCalValues_t values to uninitialized. + * A define to set all \ref RAIL_IrCalValues_t values to uninitialized. * * This define can be used when you have no data to pass to the calibration * routines but wish to compute and save all possible calibrations. @@ -4779,24 +4773,24 @@ typedef struct RAIL_IrCalValues { * * This structure contains the set of persistent calibration values for * EFR32. You can set these beforehand and apply them at startup to save the - * time required to compute them. Any of these values may be set to + * time required to compute them. Any of these values may be set to \ref * RAIL_CAL_INVALID_VALUE to force the code to compute that calibration value. */ typedef RAIL_IrCalValues_t RAIL_CalValues_t; /** - * A define to set all RAIL_CalValues_t values to uninitialized. + * A define to set all \ref RAIL_CalValues_t values to uninitialized. * * This define can be used when you have no data to pass to the calibration * routines but wish to compute and save all possible calibrations. */ #define RAIL_CALVALUES_UNINIT RAIL_IRCALVALUES_UNINIT -/// Use this value with either TX or RX values in RAIL_SetPaCTune +/// Use this value with either TX or RX values in \ref RAIL_SetPaCTune() /// to use whatever value is already set and do no update. This /// value is provided to provide consistency across EFR32 chips, /// but technically speaking, all PA capacitance tuning values are -/// invalid on EFR32XG21 parts, as RAIL_SetPaCTune is not supported +/// invalid on EFR32xG21 parts, as \ref RAIL_SetPaCTune() is not supported /// on those parts. #define RAIL_PACTUNE_IGNORE (255U) @@ -4831,16 +4825,19 @@ RAIL_ENUM(RAIL_RfSenseBand_t) { RAIL_RFSENSE_OFF, /** RF Sense is in 2.4 GHz band. */ RAIL_RFSENSE_2_4GHZ, - /** RF Sense is in sub-GHz band. */ + /** RF Sense is in Sub-GHz band. */ RAIL_RFSENSE_SUBGHZ, /** RF Sense is in both bands. */ RAIL_RFSENSE_ANY, - /** Must be last before sensitivity options. */ + /** + * A count of the basic choices in this enumeration. + * Must be last before sensitivity options. + */ RAIL_RFSENSE_MAX, /** RF Sense is in low sensitivity 2.4 GHz band */ RAIL_RFSENSE_2_4GHZ_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_2_4GHZ, - /** RF Sense is in low sensitivity sub-GHz band */ + /** RF Sense is in low sensitivity Sub-GHz band */ RAIL_RFSENSE_SUBGHZ_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_SUBGHZ, /** RF Sense is in low sensitivity for both bands. */ RAIL_RFENSE_ANY_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_ANY, @@ -4997,15 +4994,16 @@ RAIL_ENUM(RAIL_RxChannelHoppingMode_t) { */ RAIL_RX_CHANNEL_HOPPING_MODE_VT = 8, /** - * This is the transmit channel used for auto-ACK if the regular channel, + * This is the transmit channel used for Auto-Ack if the regular channel, * specified in RAIL_RxChannelHoppingConfigEntry::parameter, is * optimized for RX which may degrade some TX performance */ RAIL_RX_CHANNEL_HOPPING_MODE_TX = 9, /** * A count of the basic choices in this enumeration. + * Must be last before _WITH_OPTIONS twins. */ - RAIL_RX_CHANNEL_HOPPING_MODES_COUNT = 10, // Must be last before _WITH_OPTIONS twins + RAIL_RX_CHANNEL_HOPPING_MODES_COUNT, /** * The start of equivalent modes requiring non-default \ref @@ -5117,16 +5115,16 @@ typedef uint32_t RAIL_RxChannelHoppingParameter_t; * on a per-hop basis. */ RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) { - /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL bit */ + /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL bit. */ RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL_SHIFT = 0, - /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL bit */ + /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL bit. */ RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL_SHIFT = 1, - /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD bit */ + /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD bit. */ RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT = 2, /** Stop hopping on this hop. */ RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT = 3, - /** A count of the choices in this enumeration. */ - RAIL_RX_CHANNEL_HOPPING_OPTIONS_COUNT // Must be last + /** A count of the choices in this enumeration. Must be last. */ + RAIL_RX_CHANNEL_HOPPING_OPTIONS_COUNT }; /** A value representing no options enabled. */ @@ -5326,7 +5324,7 @@ typedef struct RAIL_RxChannelHoppingConfigEntry { * channel indicated by this entry. */ uint32_t delay; - /** @deprecated Set delayMode to RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC. */ + /** @deprecated Set delayMode to \ref RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC. */ RAIL_RxChannelHoppingDelayMode_t delayMode; /** * Bitmask of various options that can be applied to the current @@ -5386,8 +5384,8 @@ typedef struct RAIL_RxChannelHoppingConfig { /** * A pointer to the first element of an array of \ref * RAIL_RxChannelHoppingConfigEntry_t that represents the channels - * used during channel hopping. The length of this array must be - * numberOfChannels. + * used during channel hopping. This array must have numberOfChannels + * entries. */ RAIL_RxChannelHoppingConfigEntry_t *entries; } RAIL_RxChannelHoppingConfig_t; @@ -5399,20 +5397,18 @@ typedef struct RAIL_RxChannelHoppingConfig { typedef struct RAIL_RxDutyCycleConfig { /** The mode by which RAIL determines when to exit RX. */ RAIL_RxChannelHoppingMode_t mode; + // Unnamed 'uint8_t reserved[3]' pad byte field here. /** * Depending on the 'mode' parameter that was specified, this member * is used to parameterize that mode. See the comments on each value of * \ref RAIL_RxChannelHoppingMode_t to learn what to specify here. */ - // Unnamed 'uint8_t reserved[3]' pad byte field here. RAIL_RxChannelHoppingParameter_t parameter; /** * Idle time in microseconds to wait before re-entering RX. */ uint32_t delay; - /** - * Indicate how the timing specified in 'delay' should be applied. - */ + /** @deprecated Set delayMode to \ref RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC. */ RAIL_RxChannelHoppingDelayMode_t delayMode; /** * Bitmask of various options that can be applied to the current @@ -5452,7 +5448,7 @@ typedef struct RAIL_RxDutyCycleConfig { * \ref RAIL_SetFreqOffset(). * * The units are chip-specific. For EFR32 they are radio synthesizer - * resolution steps (synthTicks) and is limited to 15 bits. + * resolution steps (synth ticks) and is limited to 15 bits. * A value of \ref RAIL_FREQUENCY_OFFSET_INVALID * means that this value is invalid. */ @@ -5519,12 +5515,14 @@ RAIL_ENUM(RAIL_StreamMode_t) { RAIL_STREAM_PN9_STREAM = 1, /** 101010 sequence. */ RAIL_STREAM_10_STREAM = 2, - /** An unmodulated carrier wave with no change to PLL BW. Same as RAIL_STREAM_CARRIER_WAVE. */ + /** An unmodulated carrier wave with no change to PLL BW. Same as \ref RAIL_STREAM_CARRIER_WAVE. */ RAIL_STREAM_CARRIER_WAVE_PHASENOISE = 3, - /** ramp sequence starting at a different offset for consecutive packets. Only available for some modulations. Fall back to RAIL_STREAM_PN9_STREAM if not available. */ + /** ramp sequence starting at a different offset for consecutive packets. Only available for some modulations. Fall back to \ref RAIL_STREAM_PN9_STREAM if not available. */ RAIL_STREAM_RAMP_STREAM = 4, - /** An unmodulated carrier wave not centered on DC but shifted roughly by channel_bandwidth/6 allowing an easy check of the residual DC. Only available for OFDM PA. Fall back to RAIL_STREAM_CARRIER_WAVE_PHASENOISE if not available. */ + /** An unmodulated carrier wave not centered on DC but shifted roughly by channel_bandwidth/6 allowing an easy check of the residual DC. Only available for OFDM PA. Fall back to \ref RAIL_STREAM_CARRIER_WAVE_PHASENOISE if not available. */ RAIL_STREAM_CARRIER_WAVE_SHIFTED = 5, + /** 10001000 sequence. */ + RAIL_STREAM_1000_STREAM = 6, /** A count of the choices in this enumeration. Must be last. */ RAIL_STREAM_MODES_COUNT }; @@ -5537,6 +5535,7 @@ RAIL_ENUM(RAIL_StreamMode_t) { #define RAIL_STREAM_CARRIER_WAVE_PHASENOISE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_PHASENOISE) #define RAIL_STREAM_RAMP_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_RAMP_STREAM) #define RAIL_STREAM_CARRIER_WAVE_SHIFTED ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_SHIFTED) +#define RAIL_STREAM_1000_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_1000_STREAM) #define RAIL_STREAM_MODES_COUNT ((RAIL_StreamMode_t) RAIL_STREAM_MODES_COUNT) #endif//DOXYGEN_SHOULD_SKIP_THIS @@ -5608,7 +5607,7 @@ typedef struct RAIL_VerifyConfig { * @brief VDET Modes. * * The VDET Mode is passed to \ref RAIL_ConfigVdet() via \ref RAIL_VdetConfig_t. - * The \ref rail_util_vdet allows customers to measure their Front End Module performance + * The \ref rail_util_vdet component allows customers to measure their Front End Module performance * at specified points in the Transmit packet. */ RAIL_ENUM(RAIL_Vdet_Mode_t) { @@ -5624,10 +5623,10 @@ RAIL_ENUM(RAIL_Vdet_Mode_t) { #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_VDET_MODE_DISABLED ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_DISABLED) -#define RAIL_VDET_MODE_AUTOMATIC ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_AUTOMATIC) -#define RAIL_VDET_MODE_IMMEDIATE ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_IMMEDIATE) -#define RAIL_VDET_MODE_COUNT ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_COUNT) +#define RAIL_VDET_MODE_DISABLED ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_DISABLED) +#define RAIL_VDET_MODE_AUTOMATIC ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_AUTOMATIC) +#define RAIL_VDET_MODE_IMMEDIATE ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_IMMEDIATE) +#define RAIL_VDET_MODE_COUNT ((RAIL_Vdet_Mode_t) RAIL_VDET_MODE_COUNT) #endif//DOXYGEN_SHOULD_SKIP_THIS /** @@ -5642,7 +5641,7 @@ RAIL_ENUM(RAIL_Vdet_Mode_t) { /** * @enum RAIL_Vdet_Resolution_t - * @brief VDET Resolution for the AuxADC. + * @brief VDET Resolution for the Aux ADC. * * The VDET Resolution is passed to \ref RAIL_ConfigVdet() via \ref RAIL_VdetConfig_t. * Shows available resolution options. @@ -5660,10 +5659,10 @@ RAIL_ENUM(RAIL_Vdet_Resolution_t) { #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_VDET_RESOLUTION_10_BIT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_10_BIT) -#define RAIL_VDET_RESOLUTION_11_BIT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_11_BIT) -#define RAIL_VDET_RESOLUTION_12_BIT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_12_BIT) -#define RAIL_VDET_RESOLUTION_COUNT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_COUNT) +#define RAIL_VDET_RESOLUTION_10_BIT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_10_BIT) +#define RAIL_VDET_RESOLUTION_11_BIT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_11_BIT) +#define RAIL_VDET_RESOLUTION_12_BIT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_12_BIT) +#define RAIL_VDET_RESOLUTION_COUNT ((RAIL_Vdet_Resolution_t) RAIL_VDET_RESOLUTION_COUNT) #endif//DOXYGEN_SHOULD_SKIP_THIS /** @@ -5736,11 +5735,11 @@ RAIL_ENUM(RAIL_Vdet_Status_t) { * A structure of type \ref RAIL_VdetConfig_t is passed to \ref RAIL_ConfigVdet(). */ typedef struct RAIL_VdetConfig { - /** Mode for the VDET */ + /** Mode for the VDET. */ RAIL_Vdet_Mode_t mode; - /** Resolution to use for the capture */ + /** Resolution to use for the capture. */ RAIL_Vdet_Resolution_t resolution; - /** Delay in us for the capture from Tx Start in \ref RAIL_VDET_MODE_AUTOMATIC. Minimum 5us, maximum 100ms*/ + /** Delay in microseconds for the capture from Tx Start in \ref RAIL_VDET_MODE_AUTOMATIC. Minimum 5 us, maximum 100000 us. */ uint32_t delayUs; } RAIL_VdetConfig_t; @@ -5783,7 +5782,6 @@ typedef struct RAIL_ChipTempConfig { /** * @struct RAIL_ChipTempMetrics_t * @brief Data used for thermal protection. - * */ typedef struct RAIL_ChipTempMetrics { /** Store chip temperature for metrics */ @@ -5823,7 +5821,6 @@ RAIL_ENUM(RAIL_RetimeOptions_t) { RAIL_RETIME_OPTION_LCD_SHIFT = 3, }; -// RAIL_RetimeOptions_t bitmasks /** * An option to configure HFXO retiming. */ @@ -5888,7 +5885,7 @@ RAIL_ENUM(RAIL_RetimeOptions_t) { * Detailed Timing Structures *****************************************************************************/ /** - * @addtogroup Detailed Timing + * @addtogroup Detailed_Timing Detailed Timing * @{ */ @@ -5916,16 +5913,230 @@ RAIL_ENUM(RAIL_TimerTickType_t) { RAIL_TIMER_TICK_RXSTAMP = 2, }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_TIMER_TICK_DEFAULT ((RAIL_TimerTickType_t) RAIL_TIMER_TICK_DEFAULT) +#define RAIL_TIMER_TICK_DEFAULT ((RAIL_TimerTickType_t) RAIL_TIMER_TICK_DEFAULT) #define RAIL_TIMER_TICK_RADIO_STATE ((RAIL_TimerTickType_t) RAIL_TIMER_TICK_RADIO_STATE) -#define RAIL_TIMER_TICK_RXSTAMP ((RAIL_TimerTickType_t) RAIL_TIMER_TICK_RXSTAMP) +#define RAIL_TIMER_TICK_RXSTAMP ((RAIL_TimerTickType_t) RAIL_TIMER_TICK_RXSTAMP) +#endif //DOXYGEN_SHOULD_SKIP_THIS /** @} */ // end of group Detailed Timing #endif //DOXYGEN_SHOULD_SKIP_THIS -/** @} */ // end of RAIL_API +/****************************************************************************** + * TrustZone + *****************************************************************************/ +/** + * @addtogroup TrustZone + * @{ + */ + +/** + * @typedef RAIL_TZ_ChangedDcdcCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_ChangedDcdc(). + * + * @return Status code indicating success of the function call. + */ +typedef RAIL_Status_t (*RAIL_TZ_ChangedDcdcCallbackPtr_t)(void); + +/** + * @typedef RAIL_TZ_ConfigAntennaGpioCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_ConfigAntennaGpio(). + * + * @param[in] config A pointer to a configuration structure applied to the relevant Antenna + * Configuration registers. A NULL configuration will produce undefined behavior. + * @return Status code indicating success of the function call. + * + */ +typedef RAIL_Status_t (*RAIL_TZ_ConfigAntennaGpioCallbackPtr_t)(const RAIL_AntennaConfig_t *config); + +/** + * @typedef RAIL_TZ_RadioClockEnableCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_RadioClockEnable(). + * + */ +typedef void (*RAIL_TZ_RadioClockEnableCallbackPtr_t)(void); + +/** + * @typedef RAIL_TZ_GetRadioClockFreqHzCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_GetRadioClockFreqHz(). + * + * @return Radio subsystem clock frequency in Hz. + * + */ +typedef uint32_t (*RAIL_TZ_GetRadioClockFreqHzCallbackPtr_t)(void); + +/** + * @typedef RAIL_TZ_RfecaClockEnableCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_RfecaClockEnable(). + * + */ +typedef void (*RAIL_TZ_RfecaClockEnableCallbackPtr_t)(void); + +/** + * @typedef RAIL_TZ_RfecaIsClockEnabledCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_RfecaIsClockEnabled(). + * + * @return true if RFECA clocks are enabled; false otherwise + * + */ +typedef bool (*RAIL_TZ_RfecaIsClockEnabledCallbackPtr_t)(void); + +/** + * @typedef RAIL_TZ_ReadInternalTemperatureCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_ReadInternalTemperature(). + * + * @param[out] internalTemperatureKelvin A pointer to the internal temperature + * in Kelvin. + * @param[in] enableTemperatureInterrupts Indicate whether temperature + * interrupts are enabled. + * @return Status code indicating success of the function call. + * + */ +typedef RAIL_Status_t (*RAIL_TZ_ReadInternalTemperatureCallbackPtr_t)(uint16_t *internalTemperatureKelvin, + bool enableTemperatureInterrupts); + +/** + * @typedef RAIL_TZ_EnableSecureRadioIrqsCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_EnableSecureRadioIrqs(). + * + */ +typedef void (*RAIL_TZ_EnableSecureRadioIrqsCallbackPtr_t)(void); + +/** + * @typedef RAIL_TZ_DisableSecureRadioIrqsCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_DisableSecureRadioIrqs(). + * + */ +typedef void (*RAIL_TZ_DisableSecureRadioIrqsCallbackPtr_t)(void); + +/** + * @typedef RAIL_TZ_RadioPerformM2mLdmaCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_RadioPerformM2mLdma(). + * + * @param[in] pDest A pointer to the destination data. + * @param[in] pSrc A pointer to the source data. + * @param[in] numWords Number of words to transfer. + * @return Status code indicating success of the function call. + * + */ +typedef RAIL_Status_t (*RAIL_TZ_RadioPerformM2mLdmaCallbackPtr_t)(uint32_t *pDest, + const uint32_t *pSrc, + uint32_t numWords); + +/** + * @typedef RAIL_TZ_ConfigureHfxoCallbackPtr_t + * @brief A pointer to the callback used to switch to secure world and run + * \ref RAIL_TZ_ConfigureHfxo(). + * + */ +typedef RAIL_Status_t (*RAIL_TZ_ConfigureHfxoCallbackPtr_t)(void); + +/** + * @struct RAIL_TZ_Config_t + * @brief Gather RAIL TrustZone callbacks pointers and booleans indicating + * peripheral secure configuration. + */ +typedef struct RAIL_TZ_Config { + /** + * See \ref RAIL_TZ_ChangedDcdcCallbackPtr_t. + * In non-secure world, it must be NULL if CMU is a non-secure peripheral. + */ + RAIL_TZ_ChangedDcdcCallbackPtr_t changedDcdcCallback; + /** + * See \ref RAIL_TZ_ConfigAntennaGpioCallbackPtr_t. + * In non-secure world, it must be NULL if CMU and GPIO are non-secure + * peripherals. + */ + RAIL_TZ_ConfigAntennaGpioCallbackPtr_t configAntennaGpioCallback; + /** + * See \ref RAIL_TZ_RadioClockEnableCallbackPtr_t. + * In non-secure world, it must be NULL if CMU is a non-secure peripheral. + */ + RAIL_TZ_RadioClockEnableCallbackPtr_t radioClockEnableCallback; + /** + * See \ref RAIL_TZ_GetRadioClockFreqHzCallbackPtr_t. + * In non-secure world, it must be NULL if CMU is a non-secure peripheral. + */ + RAIL_TZ_GetRadioClockFreqHzCallbackPtr_t getRadioClockFreqHzCallback; + /** + * See \ref RAIL_TZ_RfecaClockEnableCallbackPtr_t. + * In non-secure world, it must be NULL if CMU is a non-secure peripheral. + */ + RAIL_TZ_RfecaClockEnableCallbackPtr_t rfecaClockEnableCallback; + /** + * See \ref RAIL_TZ_RfecaIsClockEnabledCallbackPtr_t. + * In non-secure world, it must be NULL if CMU is a non-secure peripheral. + */ + RAIL_TZ_RfecaIsClockEnabledCallbackPtr_t rfecaIsClockEnabledCallback; + /** + * See \ref RAIL_TZ_ReadInternalTemperatureCallbackPtr_t. + * In non-secure world, it must be NULL if EMU is a non-secure peripheral. + */ + RAIL_TZ_ReadInternalTemperatureCallbackPtr_t readInternalTemperatureCallback; + /** + * See \ref RAIL_TZ_EnableSecureRadioIrqsCallbackPtr_t. + * In non-secure world, it must be NULL if EMU is a non-secure peripheral. + */ + RAIL_TZ_EnableSecureRadioIrqsCallbackPtr_t enableSecureRadioIrqsCallback; + /** + * See \ref RAIL_TZ_DisableSecureRadioIrqsCallbackPtr_t. + * In non-secure world, it must be NULL if EMU is a non-secure peripheral. + */ + RAIL_TZ_DisableSecureRadioIrqsCallbackPtr_t disableSecureRadioIrqsCallback; + /** + * See \ref RAIL_TZ_RadioPerformM2mLdmaCallbackPtr_t. + * In non-secure world, it must be NULL if LDMA is a non-secure peripheral or + * if RAIL must not use LDMA. + */ + RAIL_TZ_RadioPerformM2mLdmaCallbackPtr_t radioPerformM2mLdmaCallback; + /** + * See \ref RAIL_TZ_ConfigureHfxoCallbackPtr_t. + * In non-secure world, it must be NULL if HFXO is a non-secure peripheral. + */ + RAIL_TZ_ConfigureHfxoCallbackPtr_t configureHfxoCallback; + /** + * Indicate whether CMU is configured as secure peripheral. + */ + bool isCmuSecure; + /** + * Indicate whether EMU is configured as secure peripheral. + */ + bool isEmuSecure; + /** + * Indicate whether GPIO is configured as secure peripheral. + */ + bool isGpioSecure; + /** + * Indicate whether LDMA is configured as secure peripheral. + */ + bool isLdmaSecure; + /** + * Indicate whether HFXO is configured as secure peripheral. + */ + bool isHfxoSecure; + /** + * Indicate whether PRS is configured as secure peripheral. + */ + bool isPrsSecure; + /** + * Indicate whether SYSRTC is configured as secure peripheral. + */ + bool isSysrtcSecure; +} RAIL_TZ_Config_t; + +/** @} */ // end of group TrustZone #ifdef SLI_LIBRARY_BUILD #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -5946,6 +6157,8 @@ struct RAIL_ChannelConfigEntryAttr { #endif//DOXYGEN_SHOULD_SKIP_THIS #endif//SLI_LIBRARY_BUILD +/** @} */ // end of RAIL_API + #ifdef __cplusplus } #endif diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/pa_curves_brd4276a.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/sl_rail_util_pa_curves_brd4276a.h similarity index 96% rename from simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/pa_curves_brd4276a.h rename to simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/sl_rail_util_pa_curves_brd4276a.h index 16e2cf100..71bcef3aa 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/pa_curves_brd4276a.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/sl_rail_util_pa_curves_brd4276a.h @@ -6,7 +6,7 @@ * dBm powers. ******************************************************************************* * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table_brd4276a.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table_brd4276a.h index c74d063b8..f71463578 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table_brd4276a.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table_brd4276a.h @@ -6,7 +6,7 @@ * dBm powers. ******************************************************************************* * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg26/config/module/sl_rail_util_pa_config.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg26/config/module/sl_rail_util_pa_config.h new file mode 100644 index 000000000..26c6fb28c --- /dev/null +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg26/config/module/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// PA configuration + +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <10-10:1> +// Default: 10 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 10 + +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 + +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE + +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" + +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" + +// Enable PA Calibration +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 + +// +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg29/config/sl_rail_util_pa_config.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg29/config/sl_rail_util_pa_config.h new file mode 100644 index 000000000..7c14e2f34 --- /dev/null +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg29/config/sl_rail_util_pa_config.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 2 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 3300 +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg29/sl_rail_util_pa_curves.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg29/sl_rail_util_pa_curves.h new file mode 100644 index 000000000..bd1ad5bee --- /dev/null +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/efr32xg29/sl_rail_util_pa_curves.h @@ -0,0 +1,116 @@ +/***************************************************************************//** + * @file + * @brief PA power conversion curves used by Silicon Labs PA power conversion + * functions. + * @details This file contains the curves needed convert PA power levels to + * dBm powers. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __PA_CURVES_H_ +#define __PA_CURVES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RAIL_PA_CURVES_PIECEWISE_SEGMENTS (9U) +#define RAIL_PA_CURVES_LP_VALUES (16U) + +#define RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER 80 +#define RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER -300 +#define RAIL_PA_CURVES_2P4_HP_VBAT_CURVES \ + { { 255, 80, 20 }, \ + { 127, 2727, -97308 }, \ + { 60, 1028, 956 }, \ + { 39, 573, 18042 }, \ + { 27, 338, 21614 }, \ + { 20, 220, 21109 }, \ + { 16, 177, 20065 }, \ + { 12, 130, 17905 }, \ + { 7, 39, 10592 } } + +#define RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER 0 +#define RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER -291 +#define RAIL_PA_CURVES_2P4_LP_VBAT_CURVES \ + { \ + -291, /*! Power Level 0 */ \ + -178, /*! Power Level 1 */ \ + -125, /*! Power Level 2 */ \ + -94, /*! Power Level 3 */ \ + -74, /*! Power Level 4 */ \ + -60, /*! Power Level 5 */ \ + -49, /*! Power Level 6 */ \ + -40, /*! Power Level 7 */ \ + -33, /*! Power Level 8 */ \ + -28, /*! Power Level 9 */ \ + -23, /*! Power Level 10 */ \ + -19, /*! Power Level 11 */ \ + -16, /*! Power Level 12 */ \ + -12, /*! Power Level 13 */ \ + -10, /*! Power Level 14 */ \ + -8, /*! Power Level 15 */ \ + } +// *INDENT-OFF* +// Macro to declare the variables needed to initialize RAIL_TxPowerCurvesConfig_t for use in +// RAIL_InitTxPowerCurves, assuming battery powered operation +#define RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT \ + static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHp = { \ + RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, \ + RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, \ + RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, \ + }; \ + static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = \ + RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; +// *INDENT-OFF* + +#define RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT \ + { \ + .curves = { \ + { \ + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, \ + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, \ + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, \ + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, \ + .conversion = { .powerCurve = &RAIL_piecewiseDataHp }, \ + }, \ + { \ + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, \ + .segments = 0U, \ + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, \ + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, \ + }, \ + } \ + } +// *INDENT-OFF* + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c index 812c70307..08de25406 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c @@ -43,7 +43,7 @@ #include "pa_conversions_efr32.h" #include "rail.h" -#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define _SL_MAX(a, b) ((a) > (b) ? (a) : (b)) static RAIL_TxPowerCurvesConfigAlt_t powerCurvesState; @@ -133,6 +133,13 @@ static RAIL_TxPowerCurvesConfigAlt_t powerCurvesState; 4U, /* SUBGIG_LLP */ \ /* The rest are unsupported */ \ } +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) +#define SUPPORTED_PA_INDICES { \ + 0U, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + 1U, /* 2P4GIG_LP */ \ + /* The rest are unsupported */ \ +} #else #error "unknown platform" #endif @@ -256,11 +263,11 @@ __WEAK #endif RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config) { - (void) RAIL_VerifyTxPowerCurves(config); - - powerCurvesState = *config; - - return RAIL_STATUS_NO_ERROR; + RAIL_Status_t status = RAIL_VerifyTxPowerCurves(config); + if (status == RAIL_STATUS_NO_ERROR) { + powerCurvesState = *config; + } + return status; } #ifdef RAIL_PA_CONVERSIONS_WEAK @@ -300,14 +307,7 @@ RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, RAIL_TxPower_t power) { (void)railHandle; - // This function is called internally from the RAIL library, - // so if the user never calls RAIL_InitTxPowerCurves - even - // if they never intend to use dBm values in their code - - // they'll always hit the assert below. Give the user a way - // to not have to call RAIL_InitTxPowerCurves if they don't - // care about dBm values by picking a dBm value that returns the - // highest RAIL_TxPowerLevel_t possible. In other words, when - // a channel dBm limitation greater than or equal to \ref RAIL_TX_POWER_MAX + // When a channel dBm limitation greater than or equal to \ref RAIL_TX_POWER_MAX // is converted to raw units, the max RAIL_TxPowerLevel_t will be // returned. When compared to the current power level of the PA, // it will always be greater, indicating that no power coercion @@ -319,7 +319,7 @@ RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, if ((mode < sizeof(supportedPaIndices)) && (supportedPaIndices[mode] < RAIL_NUM_PA)) { RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; - uint32_t minPowerLevel = MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); + uint32_t minPowerLevel = _SL_MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { RAIL_TxPower_t minPower = modeInfo->minPowerDbm; @@ -337,7 +337,15 @@ RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, uint32_t powerIndex = (power - minPower) / step; RAIL_SetPaPowerSetting(railHandle, modeInfo->conversion.mappingTable[powerIndex], minPower, maxPower, power); +#ifdef _SILICON_LABS_32B_SERIES_3 + // Hack until librail is switched over to enforcing power limits in dBm + // This should work on rainier as rainier power table is only based on RAC_TX_PAPOWERSCALOR register, + // so the table value is guaranteed to be monotonic. + // As sol using a combination of more than a register field, the resulting power table is not guaranteed to be monotonic + return (RAIL_TxPowerLevel_t)(modeInfo->conversion.mappingTable[powerIndex]); +#else return 0U; +#endif } #endif @@ -464,7 +472,7 @@ RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, } // We 1-index low power PA power levels, but of course arrays are 0 indexed - powerLevel -= MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); + powerLevel -= _SL_MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); //If the index calculation above underflowed, then provide the lowest array index. if (powerLevel > (modeInfo->max - modeInfo->min)) { @@ -678,9 +686,9 @@ void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle, #if RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG if (currentTxPowerConfig.mode == RAIL_TX_POWER_MODE_NONE) { #if RAIL_SUPPORTS_OFDM_PA - if (RAIL_SupportsTxPowerMode(rail_handle, - txPowerConfigOFDM.mode, - NULL)) { + if (RAIL_SupportsTxPowerModeAlt(rail_handle, + &txPowerConfigOFDM.mode, + NULL, NULL)) { // Apply OFDM Power Config. status = RAIL_ConfigTxPower(rail_handle, &txPowerConfigOFDM); if (status != RAIL_STATUS_NO_ERROR) { diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h index aecbe0fe9..927905df9 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h @@ -39,8 +39,8 @@ // This macro is defined when Silicon Labs builds curves into the library as WEAK // to ensure it can be overriden by customer versions of these functions. It // should *not* be defined in a customer build. -#if !defined(RAIL_PA_CONVERSIONS_WEAK) -#ifdef SL_RAIL_UTIL_PA_CONFIG_HEADER +#ifndef RAIL_PA_CONVERSIONS_WEAK +#ifdef SL_RAIL_UTIL_PA_CONFIG_HEADER #include SL_RAIL_UTIL_PA_CONFIG_HEADER #else #include "sl_rail_util_pa_conversions_efr32_config.h" @@ -57,16 +57,16 @@ #endif #endif -#ifdef SL_RAIL_UTIL_PA_CURVE_HEADER -#include SL_RAIL_UTIL_PA_CURVE_HEADER +#ifdef SL_RAIL_UTIL_PA_CURVE_TYPES +#include SL_RAIL_UTIL_PA_CURVE_TYPES #else -#include "pa_curves_efr32.h" +#include "pa_curve_types_efr32.h" #endif -#ifdef SL_RAIL_UTIL_PA_CURVE_TYPES -#include SL_RAIL_UTIL_PA_CURVE_TYPES +#ifdef SL_RAIL_UTIL_PA_CURVE_HEADER +#include SL_RAIL_UTIL_PA_CURVE_HEADER #else -#include "pa_curve_types_efr32.h" +#include "pa_curves_efr32.h" #endif #ifdef __cplusplus @@ -86,7 +86,7 @@ extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat; extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc; /** - * Initialize TxPower curves. + * Initialize Transmit power curves. * * @param[in] config A pointer to the custom TX power curves. * @return Status code indicating success of the function call. @@ -99,8 +99,8 @@ RAIL_Status_t RAIL_InitTxPowerCurves(const RAIL_TxPowerCurvesConfig_t *config); /** * Initialize TxPower curves. * - * @param[in] config A pointer to the custom TX power curves. - * @return RAIL_Status_t indicating success or an error. + * @param[in] config A pointer to the custom TX power curves to use. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config); @@ -109,24 +109,17 @@ RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *con * current PA configuration. * * @param[in] mode PA mode whose curves are needed. - * @return RAIL_TxPowerCurves_t that should be used for conversion functions. + * @return A pointer to the \ref RAIL_TxPowerCurves_t that are used for conversion functions. * * @note: If the mode is not supported by the the chip, * then NULL will be returned. */ -RAIL_TxPowerCurves_t const * RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode); +RAIL_TxPowerCurves_t const *RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode); /** * Gets the maximum power in deci-dBm that should be used for calculating * the segments and to find right curve segment to convert Dbm to raw power * level for a specific PA. - * For the PAs with \ref RAIL_PaConversionAlgorithm_t - * \ref RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, if the curves are generated with - * maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and - * \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first - * \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to - * \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the - * maxPower and increment in deci-dBm respectively. * * @param[in] railHandle A RAIL instance handle. * @param[in] mode PA mode whose curves are needed. @@ -135,6 +128,14 @@ RAIL_TxPowerCurves_t const * RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode); * @param[out] increment A non-NULL pointer to memory allocated to hold * the increment in deci-dBm used in calculation of curve segments. * @return Status code indicating success of the function call. + * + * For the PAs with \ref RAIL_PaConversionAlgorithm_t + * \ref RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, if the curves are generated with + * maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and + * \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first + * \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to + * \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the + * maxPower and increment in deci-dBm respectively. */ RAIL_Status_t RAIL_GetTxPowerCurveLimits(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, @@ -178,12 +179,10 @@ RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_ofdm(void); void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle, const RAIL_ChannelConfigEntry_t *entry); +/** @} */ // PA_Curve_Conversions + #ifdef __cplusplus } #endif -/** - * @} - */ - #endif // PA_CONVERSIONS_EFR32_H diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h index f080d1e75..48128c115 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h @@ -50,13 +50,13 @@ extern "C" { * @struct RAIL_TxPowerCurveSegment_t * * @brief Structure containing data defining each segment of the - * power (deci-dBm) to powerLevel (raw) mapping curve fits. + * deci-dBm to raw power level mapping curve fits. * * Note, these used in an equation of the form: * * powerLevel * 1000 = slope * power + intercept * - * powerLevel is the 0-252/0-248/1-7 values used in the RAIL_Get/SetTxPower + * powerLevel is the 0-252/0-248/1-7 values used in the RAIL_Get/SetTxPower() * functions, and power is the actual output power of the PA, specified * in deci-dBm. * @@ -88,9 +88,9 @@ typedef struct RAIL_TxPowerCurves { /** min deci-dBm value */ int16_t minPower; /** - * Pointer to "piecewiseSegments"-length array of - * RAIL_TxPowerCurveSegment_t of power (deci-dBm) to - * powerLevel conversion fits. + * Pointer to an array of \ref RAIL_TxPowerCurvesConfig_t::piecewiseSegments + * elements of \ref RAIL_TxPowerCurveSegment_t for deci-dBm to raw + * power level conversion fits. */ const RAIL_TxPowerCurveSegment_t *powerParams; } RAIL_TxPowerCurves_t; @@ -173,14 +173,32 @@ typedef struct RAIL_TxPowerCurveAlt { /** min deci-dBm value */ int16_t minPower; /** - * Array of piecewise_segments RAIL_TxPowerCurveSegment_t - * structures for the power (deci-dBm) to powerLevel conversion fits. + * Array of \ref RAIL_PaDescriptor_t::segments \ref RAIL_TxPowerCurveSegment_t + * structures for the deci-dBm to raw power level conversion fits. */ //Array does not have a size since it can be various sizes. //No further fields allowed after this one. RAIL_TxPowerCurveSegment_t powerParams[]; } RAIL_TxPowerCurveAlt_t; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +#if defined(SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION) +#if RAIL_SUPPORTS_COMMON_PA_INTERFACE +#if SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION == 1 +/// The entry in the powersetting table have the below bitfields +/// |15-14 =sub-mode|13-8:unused|7-0:scalor(stripe+slice)| +/// Mask for submode +#define SLI_RAIL_UTIL_PA_TABLE_SUBMODE_MASK 0xC000UL +/// Shift for submode +#define SLI_RAIL_UTIL_PA_TABLE_SUBMODE_SHIFT 14U +/// Mask for scalor +#define SLI_RAIL_UTIL_PATABLE_SCALOR_MASK 0xFFU +/// Shift for scalor +#define SLI_RAIL_UTIL_PA_TABLE_SCALOR_SHIFT 0U +#endif //SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION == 1 +#endif //RAIL_SUPPORTS_COMMON_PA_INTERFACE +#endif //defined(SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION) +#endif //DOXYGEN_SHOULD_SKIP_THIS /** * @struct RAIL_PowerConversion_t * @@ -204,7 +222,7 @@ typedef union RAIL_PowerConversion { */ #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE #if RAIL_SUPPORTS_COMMON_PA_INTERFACE - const int8_t *mappingTable; + const int16_t *mappingTable; #else const int32_t *mappingTable; #endif @@ -220,7 +238,7 @@ typedef union RAIL_PowerConversion { * PA descriptor as used in the PA conversion functions. */ typedef struct RAIL_PaDescriptor { - /** Algorithm used to map dBm to power levels for this PA */ + /** Algorithm used to map dBm to power levels for this PA. */ RAIL_PaConversionAlgorithm_t algorithm; /** * The number of piecewise segments provided to the PA in a piecewise linear @@ -228,20 +246,20 @@ typedef struct RAIL_PaDescriptor { * piecewise linear algorithm. */ uint8_t segments; - /** Min power level for this PA */ + /** Min power level for this PA. */ RAIL_TxPowerLevel_t min; - /** Max power level for this PA */ + /** Max power level for this PA. */ RAIL_TxPowerLevel_t max; #if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE - /** step size in deci-dBm between entries in table */ + /** step size in deci-dBm between entries in table. */ RAIL_TxPowerLevel_t step; - /** structure padding */ + /** structure padding. */ uint8_t padding; - /** structure padding */ + /** structure padding. */ uint16_t padding2; - /** Min power in deci-dBm for this PA */ + /** Min power in deci-dBm for this PA. */ RAIL_TxPower_t minPowerDbm; - /** Max power in deci-dBm for this PA */ + /** Max power in deci-dBm for this PA. */ RAIL_TxPower_t maxPowerDbm; #endif /** Union containing a pointer to algorithm-specific conversion data. */ @@ -263,12 +281,10 @@ typedef struct RAIL_TxPowerCurvesConfigAlt { uint16_t paVoltage; } RAIL_TxPowerCurvesConfigAlt_t; +/** @} */ // PA_Curve_Conversions + #ifdef __cplusplus } #endif -/** - * @} - */ - #endif // PA_CURVE_TYPES_EFR32_H diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c index bf8c3225a..2e7d7ef8a 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c @@ -126,7 +126,9 @@ const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { }, }; -#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 9)) static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, @@ -357,10 +359,10 @@ const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { #elif !defined(_SILICON_LABS_32B_SERIES_2) -static const int8_t RAIL_curves10dbm[RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_NUM_VALUES] = +static const int16_t RAIL_curves10dbm[RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_NUM_VALUES] = RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_CURVES; -static const int8_t RAIL_curves0dbm[RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_NUM_VALUES] = +static const int16_t RAIL_curves0dbm[RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_NUM_VALUES] = RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_CURVES; // This chip has the same curve for Vbat and DCDC diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h index 9ff6ec4de..8322cfa75 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h @@ -109,7 +109,9 @@ extern "C" { #else #include "efr32xg27/sl_rail_util_pa_curves_QFN.h" #endif -#elif (_SILICON_LABS_32B_SERIES_3_CONFIG == 1) +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) +#include "efr32xg29/sl_rail_util_pa_curves.h" +#elif defined(_SILICON_LABS_32B_SERIES_3) #include "sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h" #include "sixg301/sl_rail_util_pa_curves.h" #else diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/config/sl_rail_util_pa_config.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/config/sl_rail_util_pa_config.h index 7c14e2f34..2b0fda391 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/config/sl_rail_util_pa_config.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/config/sl_rail_util_pa_config.h @@ -76,6 +76,14 @@ #define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 // +// PA PowerSetting Table version +// PA powersetting table version +// <0=> Disable +// <1=> 1st version +// Default: 1 +#define SL_RAIL_UTIL_PA_POWERSETTING_TABLE_VERSION 1 +// + // <<< end of configuration section >>> #endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h index efcd58fbe..f87333ca7 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sixg301/sl_rail_util_pa_dbm_powersetting_mapping_table.h @@ -44,27 +44,27 @@ extern "C" { #define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_MIN_POWER_DDBM (-100) #define RAIL_PA_CURVES_COMMON_INTERFACE_10DBM_CURVES \ { \ - 0x1 /* -10.0 dBm */, \ - 0x4 /* -9.0 dBm */, \ - 0xa /* -8.0 dBm */, \ - 0xe /* -7.0 dBm */, \ - 0x13 /* -6.0 dBm */, \ - 0x17 /* -5.0 dBm */, \ - 0x1c /* -4.0 dBm */, \ - 0x21 /* -3.0 dBm */, \ - 0x27 /* -2.0 dBm */, \ - 0x2a /* -1.0 dBm */, \ - 0x2f /* 0.0 dBm */, \ - 0x35 /* 1.0 dBm */, \ - 0x39 /* 2.0 dBm */, \ - 0x3d /* 3.0 dBm */, \ - 0x42 /* 4.0 dBm */, \ - 0x47 /* 5.0 dBm */, \ - 0x4c /* 6.0 dBm */, \ - 0x50 /* 7.0 dBm */, \ - 0x55 /* 8.0 dBm */, \ - 0x5a /* 9.0 dBm */, \ - 0x5f /* 10.0 dBm */ \ + 0x4001 /* -10.0 dBm */, \ + 0x4004 /* -9.0 dBm */, \ + 0x400a /* -8.0 dBm */, \ + 0x400e /* -7.0 dBm */, \ + 0x4013 /* -6.0 dBm */, \ + 0x4017 /* -5.0 dBm */, \ + 0x401c /* -4.0 dBm */, \ + 0x4021 /* -3.0 dBm */, \ + 0x4027 /* -2.0 dBm */, \ + 0x402a /* -1.0 dBm */, \ + 0x402f /* 0.0 dBm */, \ + 0x4035 /* 1.0 dBm */, \ + 0x4039 /* 2.0 dBm */, \ + 0x403d /* 3.0 dBm */, \ + 0x4042 /* 4.0 dBm */, \ + 0x4047 /* 5.0 dBm */, \ + 0x404c /* 6.0 dBm */, \ + 0x4050 /* 7.0 dBm */, \ + 0x4055 /* 8.0 dBm */, \ + 0x405a /* 9.0 dBm */, \ + 0x405f /* 10.0 dBm */ \ } #define RAIL_PA_CURVES_COMMON_INTERFACE_0DBM_NUM_VALUES (20U) diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sl_rail_util_pa_conversions_efr32_config.h b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sl_rail_util_pa_conversions_efr32_config.h index 99111904d..ba97f08ce 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sl_rail_util_pa_conversions_efr32_config.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/pa-conversions/sl_rail_util_pa_conversions_efr32_config.h @@ -54,8 +54,12 @@ extern "C" { #include "efr32xg27/config/sl_rail_util_pa_config.h" #elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) #include "efr32xg28/config/sl_rail_util_pa_config.h" +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 9) +#include "efr32xg29/config/sl_rail_util_pa_config.h" #elif defined (_SILICON_LABS_32B_SERIES_2) #include "efr32xg21/config/sl_rail_util_pa_config.h" +#elif (_SILICON_LABS_32B_SERIES_3_CONFIG == 301) +#include "sixg301/config/sl_rail_util_pa_config.h" #else #error "Unsupported platform!" #endif diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/rail_util_protocol/config/efr32xg28/sl_rail_util_protocol_config.h b/simplicity_sdk/platform/radio/rail_lib/plugin/rail_util_protocol/config/efr32xg28/sl_rail_util_protocol_config.h index 5f2d9315a..ee71670b6 100644 --- a/simplicity_sdk/platform/radio/rail_lib/plugin/rail_util_protocol/config/efr32xg28/sl_rail_util_protocol_config.h +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/rail_util_protocol/config/efr32xg28/sl_rail_util_protocol_config.h @@ -255,6 +255,97 @@ // // +// IEEE 802.15.4, 2.4 GHz Settings +// 2.4 GHz: Node Configuration +// Enable/Disable IEEE 802.15.4 2.4 GHz Protocol +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ENABLE 1 +// PAN Coordinator +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_PAN_COORDINATOR_ENABLE 0 +// Promiscuous Mode +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_PROMISCUOUS_MODE_ENABLE 1 +// Default Frame Pending bit value for outgoing ACKs in response to Data Request Command +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_DEFAULT_FRAME_PENDING_STATE 0 +// + +// 2.4 GHz: Receivable Frame Types +// Beacon Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_BEACON_FRAME_ENABLE 1 +// Data Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_DATA_FRAME_ENABLE 1 +// ACK Frames +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_ACK_FRAME_ENABLE 0 +// Command Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_COMMAND_FRAME_ENABLE 1 +// + +// 2.4 GHz: Transition Times +// Transition time (microseconds) from idle to RX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_IDLE_TO_RX_US 100 +// Transition time (microseconds) from TX to RX +// <0-65535:1> +// Default: 182 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_TX_TO_RX_US 182 +// Transition time (microseconds) from idle to TX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_IDLE_TO_TX_US 100 +// Transition time (microseconds) from RX to TX +// <0-65535:1> +// Default: 192 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_TO_TX_US 192 +// + +// 2.4 GHz: RX Search Timeouts +// Enable RX Search timeout after Idle +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from idle +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_US 65535 +// +// Enable RX Search timeout after TX +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from TX +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_US 65535 +// +// + +// 2.4 GHz: Auto ACK Configuration +// Enable Auto ACKs +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_ENABLE 1 +// RX ACK timeout duration (microseconds) +// <1-65535:1> +// Default: 672 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_TIMEOUT_US 672 +// Radio state transition after attempting to receive ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_RX_TRANSITION_STATE RAIL_RF_STATE_RX +// Radio state transition after transmitting ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_TX_TRANSITION_STATE RAIL_RF_STATE_RX +// +// +// + // <<< end of configuration section >>> #endif // SL_RAIL_UTIL_PROTOCOL_CONFIG_H diff --git a/simplicity_sdk/platform/radio/rail_lib/plugin/rail_util_protocol/config/efr32xg29/sl_rail_util_protocol_config.h b/simplicity_sdk/platform/radio/rail_lib/plugin/rail_util_protocol/config/efr32xg29/sl_rail_util_protocol_config.h new file mode 100644 index 000000000..7f45e9d6a --- /dev/null +++ b/simplicity_sdk/platform/radio/rail_lib/plugin/rail_util_protocol/config/efr32xg29/sl_rail_util_protocol_config.h @@ -0,0 +1,174 @@ +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PROTOCOL_CONFIG_H +#define SL_RAIL_UTIL_PROTOCOL_CONFIG_H + +#include "sl_rail_util_protocol_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Bluetooth LE Settings +// BLE: Transition Times +// Enable/Disable BLE +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_BLE_ENABLE 1 +// Transition time (microseconds) from idle to RX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_IDLE_TO_RX_US 100 +// Transition time (microseconds) from TX to RX +// <0-65535:1> +// Default: 150 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_TX_TO_RX_US 150 +// Transition time (microseconds) from idle to TX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_IDLE_TO_TX_US 100 +// Transition time (microseconds) from RX to TX +// <0-65535:1> +// Default: 150 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_RX_TO_TX_US 150 +// + +// BLE: RX Search Timeouts +// Enable RX Search timeout after Idle +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from idle +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_US 65535 +// +// Enable RX Search timeout after TX +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from TX +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_BLE_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_US 65535 +// +// +// + +// IEEE 802.15.4, 2.4 GHz Settings +// 2.4 GHz: Node Configuration +// Enable/Disable IEEE 802.15.4 2.4 GHz Protocol +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ENABLE 1 +// PAN Coordinator +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_PAN_COORDINATOR_ENABLE 0 +// Promiscuous Mode +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_PROMISCUOUS_MODE_ENABLE 1 +// Default Frame Pending bit value for outgoing ACKs in response to Data Request Command +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_DEFAULT_FRAME_PENDING_STATE 0 +// + +// 2.4 GHz: Receivable Frame Types +// Beacon Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_BEACON_FRAME_ENABLE 1 +// Data Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_DATA_FRAME_ENABLE 1 +// ACK Frames +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_ACK_FRAME_ENABLE 0 +// Command Frames +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_ACCEPT_COMMAND_FRAME_ENABLE 1 +// + +// 2.4 GHz: Transition Times +// Transition time (microseconds) from idle to RX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_IDLE_TO_RX_US 100 +// Transition time (microseconds) from TX to RX +// <0-65535:1> +// Default: 182 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_TX_TO_RX_US 182 +// Transition time (microseconds) from idle to TX +// <0-65535:1> +// Default: 100 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_IDLE_TO_TX_US 100 +// Transition time (microseconds) from RX to TX +// <0-65535:1> +// Default: 192 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_TO_TX_US 192 +// + +// 2.4 GHz: RX Search Timeouts +// Enable RX Search timeout after Idle +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from idle +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_IDLE_US 65535 +// +// Enable RX Search timeout after TX +// Default: 0 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_ENABLE 0 +// Max time (microseconds) radio will search for packet when coming from TX +// <1-65535:1> +// Default: 65535 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_TIMING_RX_SEARCH_TIMEOUT_AFTER_TX_US 65535 +// +// + +// 2.4 GHz: Auto ACK Configuration +// Enable Auto ACKs +// Default: 1 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_ENABLE 1 +// RX ACK timeout duration (microseconds) +// <1-65535:1> +// Default: 672 +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_TIMEOUT_US 672 +// Radio state transition after attempting to receive ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_RX_TRANSITION_STATE RAIL_RF_STATE_RX +// Radio state transition after transmitting ACK +// Idle +// RX +// Default: RAIL_RF_STATE_RX +#define SL_RAIL_UTIL_PROTOCOL_IEEE802154_2P4GHZ_AUTO_ACK_TX_TRANSITION_STATE RAIL_RF_STATE_RX +// +// +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PROTOCOL_CONFIG_H diff --git a/simplicity_sdk/platform/radio/rail_lib/protocol/ble/rail_ble.h b/simplicity_sdk/platform/radio/rail_lib/protocol/ble/rail_ble.h index 0fb89e3f8..45ba8d859 100644 --- a/simplicity_sdk/platform/radio/rail_lib/protocol/ble/rail_ble.h +++ b/simplicity_sdk/platform/radio/rail_lib/protocol/ble/rail_ble.h @@ -50,7 +50,7 @@ extern "C" { /// operation and provide additional helper routines necessary for /// normal BLE send/receive that aren't available directly in RAIL. /// RAIL APIs should be used to set up the application. However, -/// RAIL_ConfigChannels() and RAIL_ConfigRadio() should not be called to set up +/// \ref RAIL_ConfigChannels() and \ref RAIL_ConfigRadio() should not be called to set up /// the PHY. Instead, RAIL_BLE_Config* APIs should be used to set up the /// 1 Mbps, 2 Mbps, or Coded PHY configurations needed by the application. These /// APIs will configure the hardware and also configure the set of valid BLE @@ -58,18 +58,17 @@ extern "C" { /// /// To implement a standard BLE link layer, you will also need to handle tight /// turnaround times and send packets at specific instants. This can all be -/// managed through general RAIL functions, such as RAIL_ScheduleTx(), -/// RAIL_ScheduleRx(), and RAIL_SetStateTiming(). See RAIL APIs for more +/// managed through general RAIL functions, such as \ref RAIL_StartScheduledTx(), +/// \ref RAIL_ScheduleRx(), and \ref RAIL_SetStateTiming(). See RAIL APIs for more /// useful functions. /// /// A simple example to set up the application to be in BLE mode is shown /// below. Note that this will put the radio on the first advertising channel /// with the advertising Access Address. In any full-featured BLE application you -/// will need to use the RAIL_BLE_ConfigChannelRadioParams() function to change +/// will need to use the \ref RAIL_BLE_ConfigChannelRadioParams() function to change /// the sync word and other parameters as needed based on your connection. -/// /// @code{.c} -/// // RAIL Handle set at initialization time. +/// // RAIL handle set at initialization time. /// static RAIL_Handle_t gRailHandle = NULL; /// /// static void radioEventHandler(RAIL_Handle_t railHandle, @@ -78,26 +77,13 @@ extern "C" { /// // ... handle RAIL events, e.g., receive and transmit completion /// } /// -/// #if MULTIPROTOCOL -/// // Allocate memory for RAIL to hold BLE-specific state information -/// static RAIL_BLE_State_t bleState; // Must never be const -/// static RAILSched_Config_t schedCfg; // Must never be const -/// static RAIL_Config_t railCfg = { // Must never be const -/// .eventsCallback = &radioEventHandler, -/// .protocol = &bleState, // For BLE, RAIL needs additional state memory -/// .scheduler = &schedCfg, // For MultiProtocol, additional scheduler memory -/// }; -/// #else -/// static RAIL_Config_t railCfg = { // Must never be const -/// .eventsCallback = &radioEventHandler, -/// .protocol = NULL, -/// .scheduler = NULL, -/// }; -/// #endif -/// /// // Set the radio to receive on the first BLE advertising channel. -/// int bleAdvertiseEnable(void) +/// void bleAdvertiseEnable(void) /// { +/// RAIL_Config_t railCfg = { +/// .eventsCallback = &radioEventHandler, +/// }; +/// /// // Initializes the RAIL library and any internal state it requires. /// gRailHandle = RAIL_Init(&railCfg, NULL); /// @@ -128,13 +114,13 @@ extern "C" { * @brief The variant of the BLE Coded PHY. */ RAIL_ENUM(RAIL_BLE_Coding_t) { - /** Enables the 125 kbps variant of the BLE Coded PHY */ + /** Enables the 125 kbps variant of the BLE Coded PHY. */ RAIL_BLE_Coding_125kbps = 0, - /** @deprecated Will be removed in a future version of RAIL */ + /** @deprecated Will be removed in a future version of RAIL. */ RAIL_BLE_Coding_125kbps_DSA = 1, - /** Enables the 500 kbps variant of the BLE Coded PHY */ + /** Enables the 500 kbps variant of the BLE Coded PHY. */ RAIL_BLE_Coding_500kbps = 2, - /** @deprecated Will be removed in a future version of RAIL */ + /** @deprecated Will be removed in a future version of RAIL. */ RAIL_BLE_Coding_500kbps_DSA = 3, }; @@ -151,14 +137,24 @@ RAIL_ENUM(RAIL_BLE_Coding_t) { * @brief The variant of the BLE PHY. */ RAIL_ENUM(RAIL_BLE_Phy_t) { - /** Use the standard BLE 1Mbps PHY */ - RAIL_BLE_1Mbps, - /** Use the high data rate BLE 2Mbps PHY */ - RAIL_BLE_2Mbps, - /** Enables the 125 kbps variant of the BLE Coded PHY */ - RAIL_BLE_Coded125kbps, - /** Enables the 500 kbps variant of the BLE Coded PHY */ - RAIL_BLE_Coded500kbps, + /** Use the standard BLE 1 Mbps PHY. */ + RAIL_BLE_1Mbps = 0U, + /** Use the high data rate BLE 2 Mbps PHY. */ + RAIL_BLE_2Mbps = 1U, + /** Enables the 125 kbps variant of the BLE Coded PHY. */ + RAIL_BLE_Coded125kbps = 2U, + /** Enables the 500 kbps variant of the BLE Coded PHY. */ + RAIL_BLE_Coded500kbps = 3U, + /** Use the BLE Simulscan PHY. */ + RAIL_BLE_Simulscan = 4U, + /** Use the 1 Mbps variant of the BLE CS PHY. */ + RAIL_BLE_CS1Mbps = 5U, + /** Use the 2 Mbps variant of the BLE CS PHY. */ + RAIL_BLE_CS2Mbps = 6U, + /** Use the BLE 2 Mbps AOX PHY. */ + RAIL_BLE_AOX2Mbps = 7U, + /** Use the BLE 1 Mbps Quuppa PHY. */ + RAIL_BLE_Quuppa1Mbps = 8U, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -167,6 +163,11 @@ RAIL_ENUM(RAIL_BLE_Phy_t) { #define RAIL_BLE_2Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_2Mbps) #define RAIL_BLE_Coded125kbps ((RAIL_BLE_Phy_t) RAIL_BLE_Coded125kbps) #define RAIL_BLE_Coded500kbps ((RAIL_BLE_Phy_t) RAIL_BLE_Coded500kbps) +#define RAIL_BLE_Simulscan ((RAIL_BLE_Phy_t) RAIL_BLE_Simulscan) +#define RAIL_BLE_CS1Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_CS1Mbps) +#define RAIL_BLE_CS2Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_CS2Mbps) +#define RAIL_BLE_AOX2Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_AOX2Mbps) +#define RAIL_BLE_Quuppa1Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_Quuppa1Mbps) #endif //DOXYGEN_SHOULD_SKIP_THIS /// @addtogroup BLE_PHY BLE Radio Configurations @@ -182,25 +183,25 @@ RAIL_ENUM(RAIL_BLE_Phy_t) { /// @{ /** - * Default PHY to use for BLE 1M non-Viterbi. Will be NULL if + * Default PHY to use for BLE 1 Mbps non-Viterbi. Will be NULL if * \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1Mbps; /** - * Default PHY to use for BLE 2M non-Viterbi. Will be NULL if + * Default PHY to use for BLE 2 Mbps non-Viterbi. Will be NULL if * \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2Mbps; /** - * Default PHY to use for BLE 1M Viterbi. Will be NULL if + * Default PHY to use for BLE 1 Mbps Viterbi. Will be NULL if * \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbi; /** - * Default PHY to use for BLE 2M Viterbi. Will be NULL if + * Default PHY to use for BLE 2 Mbps Viterbi. Will be NULL if * \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbi; @@ -208,64 +209,63 @@ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbi; #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * Default PHY to use for BLE 1M Viterbi CS. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_CS is 0. On EFR32XG24, this will also + * \ref RAIL_BLE_SUPPORTS_CS is 0. On EFR32xG24, this will also * be NULL for non 40MHz HFXO frequencies. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbiCs; /** * Default PHY to use for BLE 2M Viterbi CS. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_CS is 0. On EFR32XG24, this will also + * \ref RAIL_BLE_SUPPORTS_CS is 0. On EFR32xG24, this will also * be NULL for non 40MHz HFXO frequencies. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbiCs; #endif /** - * PHY to use for BLE 2M with AoX functionality. Will be NULL if either + * PHY to use for BLE 2 Mbps with AoX functionality. Will be NULL if either * \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI or \ref RAIL_BLE_SUPPORTS_AOX is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsAox; /** - * Default PHY to use for BLE Coded 125kbps. Will be NULL if + * Default PHY to use for BLE Coded 125 kbps. Will be NULL if * \ref RAIL_BLE_SUPPORTS_CODED_PHY is 0. This PHY can receive on both - * 125kbps and 500kbps BLE Coded, but will only transmit at 125kbps. + * 125 kbps and 500 kbps BLE Coded, but will only transmit at 125 kbps. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy125kbps; /** - * Default PHY to use for BLE Coded 500kbps. Will be NULL if + * Default PHY to use for BLE Coded 500 kbps. Will be NULL if * \ref RAIL_BLE_SUPPORTS_CODED_PHY is 0. This PHY can receive on both - * 125kbps and 500kbps BLE Coded, but will only transmit at 125kbps. + * 125 kbps and 500 kbps BLE Coded, but will only transmit at 125 kbps. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy500kbps; /** * Default PHY to use for BLE Simulscan. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY is 0. This PHY can receive on 1Mbps - * as well as 125kbps and 500kbps BLE Coded, but will only transmit at 1Mbps. + * \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY is 0. This PHY can receive on 1 Mbps + * as well as 125 kbps and 500 kbps BLE Coded, but will only transmit at 1 Mbps. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_PhySimulscan; /** - * Default 1Mbps Quuppa PHY. Will be NULL if + * Default 1 Mbps Quuppa PHY. Will be NULL if * \ref RAIL_BLE_SUPPORTS_QUUPPA is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_BLE_PhyQuuppa; /// @} // End of group BLE_PHY -// Defines for subPhyID field in RAIL_RxPacketDetails_t -/** subPhyId indicating a 500kbps packet */ +/** \ref RAIL_RxPacketDetails_t::subPhyId indicating a 500 kbps packet. */ #define RAIL_BLE_RX_SUBPHY_ID_500K (0U) -/** subPhyId indicating a 125kbps packet */ +/** \ref RAIL_RxPacketDetails_t::subPhyId indicating a 125 kbps packet. */ #define RAIL_BLE_RX_SUBPHY_ID_125K (1U) -/** subPhyId value indicating a 1Mbps packet */ +/** \ref RAIL_RxPacketDetails_t::subPhyId value indicating a 1 Mbps packet. */ #define RAIL_BLE_RX_SUBPHY_ID_1M (2U) -/** Invalid subPhyId value */ +/** \ref RAIL_RxPacketDetails_t::subPhyId invalid value. */ #define RAIL_BLE_RX_SUBPHY_ID_INVALID (3U) -/** subPhyId indicating the total count */ +/** The total count of BLE subPhyId's. Must be last. */ #define RAIL_BLE_RX_SUBPHY_COUNT (4U) /** @@ -273,35 +273,39 @@ extern const RAIL_ChannelConfig_t *const RAIL_BLE_PhyQuuppa; * @brief Available Signal Identifier modes. */ RAIL_ENUM(RAIL_BLE_SignalIdentifierMode_t) { - /* Disable signal detection mode. */ + /** Disable signal detection mode. */ RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE = 0, - /* BLE 1Mbps (GFSK) detection mode. */ - RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS, - /* BLE 2Mbps (GFSK) detection mode. */ - RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS + /** BLE 1 Mbps (GFSK) detection mode. */ + RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS = 1, + /** BLE 2 Mbps (GFSK) detection mode. */ + RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS = 2, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE) -#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS) -#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS) +#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_BLE_SignalIdentifierMode_t) RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE) +#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS ((RAIL_BLE_SignalIdentifierMode_t) RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS) +#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS ((RAIL_BLE_SignalIdentifierMode_t) RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS) #endif /** * @struct RAIL_BLE_State_t - * @brief A state structure for BLE. - * - * This structure must be allocated in application global read-write memory - * that persists for the duration of BLE usage. It cannot be allocated - * in read-only memory or on the call stack. + * @brief A structure for BLE radio state parameters. */ typedef struct RAIL_BLE_State { - uint32_t crcInit; /**< The value used to initialize the CRC algorithm. */ - uint32_t accessAddress; /**< The access address used for the connection. */ - uint16_t channel; /**< The logical channel used. */ - bool disableWhitening; /**< Indicates whether the whitening engine should be off. */ - uint16_t whiteInit; /**< The value used to initialize the whitening algorithm */ + /** The value used to initialize the CRC algorithm. */ + uint32_t crcInit; + /** + * The access address used for the connection. + * It is transmitted or received least-significant bit first. + */ + uint32_t accessAddress; + /** The logical channel used. */ + uint16_t channel; + /** Indicates whether the whitening engine should be off (generally used for testing only). */ + bool disableWhitening; + /** Reserved for future use; specify 0. */ + uint16_t whiteInit; } RAIL_BLE_State_t; /** @@ -312,8 +316,8 @@ typedef struct RAIL_BLE_State { * * This function changes your radio, channel configuration, and other * parameters to match what is needed for BLE, initially establishing - * the BLE 1mbps PHY. To switch back to a - * default RAIL mode, call RAIL_BLE_Deinit() first. This function + * the BLE 1 Mbps PHY. To switch back to a + * default RAIL mode, call \ref RAIL_BLE_Deinit() first. This function * will configure the protocol output on PTI to \ref RAIL_PTI_PROTOCOL_BLE. * * @note BLE may not be enabled while Auto-ACKing is enabled. @@ -327,7 +331,7 @@ RAIL_Status_t RAIL_BLE_Init(RAIL_Handle_t railHandle); * @return Status code indicating success of the function call. * * This function will undo some of the configuration that happens when you call - * RAIL_BLE_Init(). After this you can safely run your normal radio + * \ref RAIL_BLE_Init(). After this you can safely run your normal radio * initialization code to use a non-BLE configuration. This function does \b * not change back your radio or channel configurations so you must do this by * manually reinitializing. This also resets the protocol output on PTI to \ref @@ -342,7 +346,7 @@ RAIL_Status_t RAIL_BLE_Deinit(RAIL_Handle_t railHandle); * @return true if BLE mode is enabled and false otherwise. * * This function returns the current status of RAIL's BLE mode. It is enabled by - * a call to RAIL_BLE_Init() and disabled by a call to RAIL_BLE_Deinit(). + * a call to \ref RAIL_BLE_Init() and disabled by a call to \ref RAIL_BLE_Deinit(). */ bool RAIL_BLE_IsEnabled(RAIL_Handle_t railHandle); @@ -354,7 +358,7 @@ bool RAIL_BLE_IsEnabled(RAIL_Handle_t railHandle); * * You can use this function to switch to the Quuppa PHY. * - * @note Not all chips support the 1Mbps Quuppa PHY. This API should return RAIL_STATUS_INVALID_CALL if + * @note Not all chips support the 1 Mbps Quuppa PHY. This API should return \ref RAIL_STATUS_INVALID_CALL if * unsupported by the hardware we're building for. */ RAIL_Status_t RAIL_BLE_ConfigPhyQuuppa(RAIL_Handle_t railHandle); @@ -363,7 +367,7 @@ RAIL_Status_t RAIL_BLE_ConfigPhyQuuppa(RAIL_Handle_t railHandle); * Switch to the Viterbi 1 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Use this function to switch back to the default BLE 1 Mbps PHY if you * have switched to the 2 Mbps or another configuration. You may only call this @@ -375,13 +379,13 @@ RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsViterbi(RAIL_Handle_t railHandle); * Switch to the legacy non-Viterbi 1 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Use this function to switch back to the legacy BLE 1 Mbps PHY if you * have switched to the 2 Mbps or another configuration. You may only call this * function after initializing BLE and while the radio is idle. * - * @note The EFR32XG2x family does not support BLE non-Viterbi PHYs. + * @deprecated BLE non-Viterbi PHYs are no longer supported. */ RAIL_Status_t RAIL_BLE_ConfigPhy1Mbps(RAIL_Handle_t railHandle); @@ -389,7 +393,7 @@ RAIL_Status_t RAIL_BLE_ConfigPhy1Mbps(RAIL_Handle_t railHandle); * Switch to the Viterbi 2 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Use this function to switch back to the BLE 2 Mbps PHY from the * default 1 Mbps option. You may only call this function after initializing BLE @@ -401,14 +405,13 @@ RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsViterbi(RAIL_Handle_t railHandle); * Switch to the legacy non-Viterbi 2 Mbps BLE PHY. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * - * Use this function to switch back to legacy BLE 2Mbps PHY from the + * Use this function to switch back to legacy BLE 2 Mbps PHY from the * default 1 Mbps option. You may only call this function after initializing BLE * and while the radio is idle. * - * @deprecated No EFR32 Series 2 parts support BLE non-Viterbi - * 2 Mbps PHY. + * @deprecated BLE non-Viterbi PHYs are no longer supported. */ RAIL_Status_t RAIL_BLE_ConfigPhy2Mbps(RAIL_Handle_t railHandle); @@ -416,8 +419,8 @@ RAIL_Status_t RAIL_BLE_ConfigPhy2Mbps(RAIL_Handle_t railHandle); * Switch to the BLE Coded PHY. * * @param[in] railHandle A handle for RAIL instance. - * @param[in] bleCoding The RAIL_BLE_Coding_t to use - * @return A status code indicating success of the function call. + * @param[in] bleCoding The \ref RAIL_BLE_Coding_t to use + * @return Status code indicating success of the function call. * * Use this function to switch back to BLE Coded PHY from the default * 1 Mbps option. You may only call this function after initializing BLE and @@ -433,7 +436,7 @@ RAIL_Status_t RAIL_BLE_ConfigPhyCoded(RAIL_Handle_t railHandle, * Switch to the Simulscan PHY. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Use this function to switch to the BLE Simulscan PHY. You may only * call this function after initializing BLE and while the radio is idle. @@ -454,7 +457,7 @@ RAIL_Status_t RAIL_BLE_ConfigPhySimulscan(RAIL_Handle_t railHandle); * Switch to the 1 Mbps BLE PHY for CS. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Use this function to switch back to the BLE 1 Mbps CS PHY from * another configuration. You may only call this @@ -468,7 +471,7 @@ RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsCs(RAIL_Handle_t railHandle); * Switch to the 2 Mbps BLE PHY for CS. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Use this function to switch back to the BLE 2 Mbps CS PHY from * another configuration. You may only call this @@ -477,7 +480,7 @@ RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsCs(RAIL_Handle_t railHandle); * @note This PHY is only supported when \ref RAIL_BLE_SUPPORTS_CS is not 0. */ RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsCs(RAIL_Handle_t railHandle); -#endif +#endif //DOXYGEN_SHOULD_SKIP_THIS /** * Change BLE radio parameters. @@ -490,13 +493,14 @@ RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsCs(RAIL_Handle_t railHandle); * initializes the whitener if used. * @param[in] disableWhitening This can turn off the whitening engine and is useful * for sending BLE test mode packets that don't have this turned on. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function can be used to switch radio parameters on every connection * and/or channel change. It is BLE-aware and will set the access address, * preamble, CRC initialization value, and whitening configuration without - * requiring you to load a new radio configuration. This function should not be - * called while the radio is active. + * requiring you to load a new radio configuration. This function should be + * called after switching to a particular BLE phy (1 Mbps, 2 Mbps, etc.) and + * not while the radio is active. */ RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle, uint32_t crcInit, @@ -508,9 +512,9 @@ RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle, * Change the current BLE PHY and go into receive. * * @param[in] railHandle A handle for RAIL instance. - * @param[in] phy Indicates which PHY to receive on - * @param[in] railChannel Which channel of the given PHY to receive on - * @param[in] startRxTime When to enter RX + * @param[in] phy Indicates which PHY to receive on. + * @param[in] railChannel Which channel of the given PHY to receive on. + * @param[in] startRxTime Absolute near-future RAIL time to enter RX. * @param[in] crcInit The value to use for CRC initialization. * @param[in] accessAddress The access address to use for the connection. The * bits of this parameter are transmitted or received LSB first. @@ -518,7 +522,7 @@ RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle, * initializes the whitener if used. * @param[in] disableWhitening This can turn off the whitening engine and is useful * for sending BLE test mode packets that don't have this turned on. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function is used to implement auxiliary packet reception, as defined in * the BLE specification. The radio will be put into IDLE, the PHY and channel @@ -532,7 +536,7 @@ RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle, RAIL_Status_t RAIL_BLE_PhySwitchToRx(RAIL_Handle_t railHandle, RAIL_BLE_Phy_t phy, uint16_t railChannel, - uint32_t startRxTime, + RAIL_Time_t startRxTime, uint32_t crcInit, uint32_t accessAddress, uint16_t logicalChannel, @@ -543,6 +547,7 @@ RAIL_Status_t RAIL_BLE_PhySwitchToRx(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in] signalIdentifierMode Mode of signal identifier operation. + * @return Status code indicating success of the function call. * * This features allows detection of BLE signal on air based on the mode. * This function must be called once before \ref RAIL_BLE_EnableSignalDetection @@ -554,8 +559,6 @@ RAIL_Status_t RAIL_BLE_PhySwitchToRx(RAIL_Handle_t railHandle, * This function is only supported by chips where * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER and * \ref RAIL_BLE_SupportsSignalIdentifier() are true. - * - * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_BLE_ConfigSignalIdentifier(RAIL_Handle_t railHandle, RAIL_BLE_SignalIdentifierMode_t signalIdentifierMode); @@ -565,19 +568,18 @@ RAIL_Status_t RAIL_BLE_ConfigSignalIdentifier(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in] enable Signal detection is enabled if true, disabled if false. + * @return Status code indicating success of the function call. * - * \ref RAIL_BLE_ConfigSignalIdentifier must be called once before calling this + * \ref RAIL_BLE_ConfigSignalIdentifier() must be called once before calling this * function to configure and enable signal identifier. * Once a signal is detected signal detection will be turned off and this * function should be called to re-enable the signal detection without needing - * to call \ref RAIL_BLE_ConfigSignalIdentifier if the signal identifier + * to call \ref RAIL_BLE_ConfigSignalIdentifier() if the signal identifier * is already configured and enabled. * * This function is only supported by chips where * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER and * \ref RAIL_BLE_SupportsSignalIdentifier() are true. - * - * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_BLE_EnableSignalDetection(RAIL_Handle_t railHandle, bool enable); @@ -602,25 +604,23 @@ RAIL_Status_t RAIL_BLE_EnableSignalDetection(RAIL_Handle_t railHandle, */ /** - * * The maximum number of GPIO pins used for AoX Antenna switching. * * If the user configures more pins using - * \ref RAIL_BLE_ConfigAoxAntenna than allowed + * \ref RAIL_BLE_ConfigAoxAntenna() than allowed * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then * \ref RAIL_STATUS_INVALID_PARAMETER status will be returned. * * \ref RAIL_STATUS_INVALID_CALL is returned if : * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT is set to 0 or - * The user configures no pins. + * the user configures no pins. * * The maximum value \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT can take depends on * number of Antenna route pins , a chip provides. - * For EFR32XG22, the maximum value of \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT is 6. + * For EFR32xG22, the maximum value of \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT is 6. * If the user configures fewer pins than \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, * then only number of pins asked by user will be configured with * \ref RAIL_STATUS_NO_ERROR. - * */ #define RAIL_BLE_AOX_ANTENNA_PIN_COUNT (6U) @@ -629,13 +629,13 @@ RAIL_Status_t RAIL_BLE_EnableSignalDetection(RAIL_Handle_t railHandle, * @brief Angle of Arrival/Departure options bit fields */ RAIL_ENUM_GENERIC(RAIL_BLE_AoxOptions_t, uint16_t) { - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE bit */ + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE bit. */ RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE_SHIFT = 0, - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONNLESS bit */ + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONNLESS bit. */ RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT = 1, - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONN bit */ + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONN bit. */ RAIL_BLE_AOX_OPTIONS_CONN_SHIFT = 2, - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK bit */ + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK bit. */ RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT = 3, }; @@ -683,12 +683,10 @@ RAIL_ENUM_GENERIC(RAIL_BLE_AoxOptions_t, uint16_t) { /** * @struct RAIL_BLE_AoxConfig_t - * @brief Contains arguments for \ref RAIL_BLE_ConfigAox function. + * @brief Contains arguments for \ref RAIL_BLE_ConfigAox() function. */ typedef struct RAIL_BLE_AoxConfig { - /** - * See RAIL_BLE_AOX_OPTIONS_* for bitfield defines for different AoX features. - */ + /** AoX options. */ RAIL_BLE_AoxOptions_t aoxOptions; /** * Size of the raw AoX CTE (continuous tone extension) data capture buffer in @@ -708,7 +706,7 @@ typedef struct RAIL_BLE_AoxConfig { */ uint8_t * antArrayAddr; /** - * Size of the antenna pattern array. + * Number of entries in the antenna pattern array. */ uint8_t antArraySize; } RAIL_BLE_AoxConfig_t; @@ -718,25 +716,20 @@ typedef struct RAIL_BLE_AoxConfig { * @brief Contains elements of \ref RAIL_BLE_AoxAntennaConfig_t struct. */ typedef struct RAIL_BLE_AoxAntennaPortPins { - /** - * The port which is used for AoX antenna switching - */ + /** The port which is used for AoX antenna switching. */ uint8_t antPort; - /** - * The pin which is used for AoX antenna switching - */ + /** The pin which is used for AoX antenna switching. */ uint8_t antPin; } RAIL_BLE_AoxAntennaPortPins_t; /** * @struct RAIL_BLE_AoxAntennaConfig_t - * @brief Contains arguments for \ref RAIL_BLE_ConfigAoxAntenna function for - * EFR32XG22. + * @brief Contains arguments for \ref RAIL_BLE_ConfigAoxAntenna() function. */ typedef struct RAIL_BLE_AoxAntennaConfig { /** * A pointer to an array containing struct of port and pin used for - * AoX antenna switching + * AoX antenna switching. */ RAIL_BLE_AoxAntennaPortPins_t *antPortPin; /** @@ -772,7 +765,7 @@ bool RAIL_BLE_CteBufferIsLocked(RAIL_Handle_t railHandle); * * @param[in] railHandle A handle for RAIL instance. * @return The offset of CTE data in a CTE sample in bytes. - * On unsupported platforms this returns 0. + * On unsupported platforms this returns 0. */ uint8_t RAIL_BLE_GetCteSampleOffset(RAIL_Handle_t railHandle); @@ -786,7 +779,13 @@ uint8_t RAIL_BLE_GetCteSampleOffset(RAIL_Handle_t railHandle); uint32_t RAIL_BLE_GetCteSampleRate(RAIL_Handle_t railHandle); /** - * Configure Angle of Arrival/Departure (AoX) functionality. AoX is a method + * Configure Angle of Arrival/Departure (AoX) functionality. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] aoxConfig Configuration options for AoX + * @return Status code indicating success of the function call. + * + * AoX is a method * of radio localization which infers angle of arrival/departure of the signal * based on different phases of the raw I/Q signal from different antennas by * controlling external RF switch during the continuous tone extension (CTE). @@ -794,34 +793,31 @@ uint32_t RAIL_BLE_GetCteSampleRate(RAIL_Handle_t railHandle); * they have 3 header bytes instead of 2 and they have CTE appended after the * payload's CRC. 3rd byte or CTE info contains CTE length. Connectionless AoX * packets have 2 header bytes and CTE info is part of the payload. - * Note that calling \ref RAIL_GetRadioEntropy during AoX reception may break - * receiving packets. * - * @param[in] railHandle A RAIL instance handle. - * @param[in] aoxConfig Configuration options for AoX - * @return RAIL_Status_t indicating success or failure of the call. + * @note Calling \ref RAIL_GetRadioEntropy() during AoX reception may break + * packet reception. */ RAIL_Status_t RAIL_BLE_ConfigAox(RAIL_Handle_t railHandle, const RAIL_BLE_AoxConfig_t *aoxConfig); + /** * Perform one time initialization of AoX registers. - * This function must be called before \ref RAIL_BLE_ConfigAox + * This function must be called before \ref RAIL_BLE_ConfigAox() * and before configuring the BLE PHY. * * @param[in] railHandle A RAIL instance handle. - * @return RAIL_Status_t indicating success or failure of the call. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_BLE_InitCte(RAIL_Handle_t railHandle); /** * Perform initialization of AoX antenna GPIO pins. - * This function must be called before calls to \ref RAIL_BLE_InitCte - * and \ref RAIL_BLE_ConfigAox, and before configuring the BLE PHY, + * This function must be called before calls to \ref RAIL_BLE_InitCte() + * and \ref RAIL_BLE_ConfigAox(), and before configuring the BLE PHY, * else a \ref RAIL_STATUS_INVALID_CALL is returned. * - * If user configures more pins, i.e., antCount in - * \ref RAIL_BLE_AoxAntennaConfig_t, than allowed - * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then the API returns + * If user configures more pins in \ref RAIL_BLE_AoxAntennaConfig_t::antCount + * than allowed by \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then the API returns * \ref RAIL_STATUS_INVALID_PARAMETER. * * If user configures lesser than or equal to number of pins allowed by @@ -833,16 +829,17 @@ RAIL_Status_t RAIL_BLE_InitCte(RAIL_Handle_t railHandle); * on the default antenna if no antenna pattern is provided. * * @param[in] railHandle A RAIL instance handle. - * @param[in] antennaConfig structure to hold the set of ports and pins to - * configure Antenna pins for AoX Antenna switching. - * @return RAIL_Status_t indicating success or failure of the call. + * @param[in] antennaConfig A pointer to the antenna configuration + * structure to hold the set of GPIO ports and pins for AoX antenna + * switching. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_BLE_ConfigAoxAntenna(RAIL_Handle_t railHandle, RAIL_BLE_AoxAntennaConfig_t *antennaConfig); /** @} */ // end of group AoX - #ifndef DOXYGEN_SHOULD_SKIP_THIS +#ifndef DOXYGEN_SHOULD_SKIP_THIS /****************************************************************************** * Channel Sounding (CS) *****************************************************************************/ @@ -869,9 +866,9 @@ RAIL_Status_t RAIL_BLE_ConfigAoxAntenna(RAIL_Handle_t railHandle, RAIL_ENUM(RAIL_BLE_CsRole_t) { /** Device cannot perform CS events. */ RAIL_BLE_CS_ROLE_UNASSIGNED = 0, - /** Device is an initiator during CS events */ + /** Device is an initiator during CS events. */ RAIL_BLE_CS_ROLE_INITIATOR = 1, - /** Device is a reflector during CS events */ + /** Device is a reflector during CS events. */ RAIL_BLE_CS_ROLE_REFLECTOR = 2, }; @@ -884,10 +881,11 @@ RAIL_ENUM(RAIL_BLE_CsRole_t) { /** * @struct RAIL_BLE_CsResults_t - * @brief Contains measurement results from CS step + * @brief Contains measurement results from CS step. */ typedef struct { - uint32_t result[7]; /**< CS measurement data for a particular step. */ + /** CS measurement data for a particular step. */ + uint32_t result[7]; } RAIL_BLE_CsResults_t; /** @@ -903,25 +901,49 @@ RAIL_ENUM(RAIL_BLE_CsRttType_t) { RAIL_BLE_CS_RTT_96B_SS = 2U, }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_CS_RTT_AA_ONLY ((RAIL_BLE_CsRttType_t) RAIL_BLE_CS_RTT_AA_ONLY) +#define RAIL_BLE_CS_RTT_32B_SS ((RAIL_BLE_CsRttType_t) RAIL_BLE_CS_RTT_32B_SS) +#define RAIL_BLE_CS_RTT_96B_SS ((RAIL_BLE_CsRttType_t) RAIL_BLE_CS_RTT_96B_SS) +#endif//DOXYGEN_SHOULD_SKIP_THIS + /** * The minimum size in 32 bit words for the IQ buffer. This value guarantees - * all IQ samples for a single 1mbps CS step can be stored. + * all IQ samples for a single 1 Mbps CS step can be stored. */ -#define RAIL_BLE_CS_1MBPS_MINIMUM_IQ_BUFFER_SIZE 600U +#define RAIL_BLE_CS_1MBPS_MINIMUM_IQ_BUFFER_SIZE 1500U /** * @struct RAIL_BLE_CsConfig_t * @brief Contains arguments for \ref RAIL_BLE_ConfigCs function. */ typedef struct RAIL_BLE_CsConfig { - RAIL_BLE_CsRole_t role; /**< The device role during CS event. */ - uint16_t csSqteSteps; /**< Number of steps in CS event. */ + /** The device role during CS event. */ + RAIL_BLE_CsRole_t role; + /** + * Number of mode 2 phase measurement slots, including the + * tone extension slot. This value should be between + * \ref RAIL_BLE_CS_MIN_ANTENNA_SLOTS and + * \ref RAIL_BLE_CS_MAX_ANTENNA_SLOTS, inclusive. + * A provided value below or above this range will be pegged + * to the appropriate minimum or maximum value. + */ + uint8_t slotCount; + /** Number of steps in CS event. */ + uint16_t csSqteSteps; /** Pointer to CS measurements. Set to NULL if unused. */ RAIL_BLE_CsResults_t *pCsDataOutput; - uint16_t t_fcs; /**< Frequency change spacing (in us). */ - uint16_t t_ip1; /**< Interlude period for mode 0 & 1 steps (in us). */ - uint16_t t_ip2; /**< Interlude period for mode 2 steps (in us). */ - uint16_t t_pm; /**< Phase measurement time (in us). */ + /** Frequency change spacing (in us). */ + uint16_t t_fcs; + /** Interlude period for mode 0 & 1 steps (in us). */ + uint16_t t_ip1; + /** Interlude period for mode 2 steps (in us). */ + uint16_t t_ip2; + /** Phase measurement time (in us). */ + uint16_t t_pm; + /**< Antenna switching time (in us). */ + uint16_t t_sw; /** * Pointer to buffer where IQ data will be written. Buffer must be 32-bit * aligned. @@ -930,7 +952,7 @@ typedef struct RAIL_BLE_CsConfig { /** * Size of IQ buffer in 32 bit words. Must be at least \ref * RAIL_BLE_CS_1MBPS_MINIMUM_IQ_BUFFER_SIZE or else an error will be - * returned by \ref RAIL_BLE_ConfigCs. + * returned by \ref RAIL_BLE_ConfigCs(). */ uint16_t iqBufferSize; /** @@ -938,7 +960,8 @@ typedef struct RAIL_BLE_CsConfig { * to a mode 0 step or else the event calibration won't occur. */ uint8_t eventCalStepIndex; - RAIL_BLE_CsRttType_t rttType; /**< RTT type returned during mode 1 step. */ + /** RTT type returned during mode 1 step. */ + RAIL_BLE_CsRttType_t rttType; /** * A pointer to the selected CS event gain index. This field will be * populated after \ref eventCalStepIndex has been reached. @@ -946,14 +969,18 @@ typedef struct RAIL_BLE_CsConfig { uint8_t *pEventGainIndex; /** * A pointer to the selected CS event Fractional Frequency Offset - * (FFO) * 100. This field will be populated after \ref eventCalStepIndex - * has been reached. + * (FFO) * pp100m (parts-per-100-million). This field will be populated + * after \ref eventCalStepIndex has been reached. */ int16_t *pEventFfoPp100m; - bool disableRttGdComp; /**< Debug flag to disable RTT GD compensation. */ - bool disablePbrDcComp; /**< Debug flag to disable PBR DC compensation. */ - bool disablePbrGdComp; /**< Debug flag to disable PBR GD compensation. */ - bool forceAgcGain; /**< Debug flag to force event gain for calibration. */ + /** Debug flag to disable RTT GD compensation. */ + bool disableRttGdComp; + /** Debug flag to disable PBR DC compensation. */ + bool disablePbrDcComp; + /** Debug flag to disable PBR GD compensation. */ + bool disablePbrGdComp; + /** Debug flag to force event gain for calibration. */ + bool forceAgcGain; /** * Pointer to an FAE table of size \ref RAIL_BLE_CS_NUM_ALLOWED_CHANNELS * that holds the FAE value for each allowed CS channel in units of @@ -962,10 +989,11 @@ typedef struct RAIL_BLE_CsConfig { * Set to NULL if unused. */ int8_t(*pFaeTable)[RAIL_BLE_CS_NUM_ALLOWED_CHANNELS]; - uint32_t forcedAgcStatus0; /**< Equivalent AGC status0 register to force. */ + /** Equivalent AGC STATUS0 register to force. */ + uint32_t forcedAgcStatus0; } RAIL_BLE_CsConfig_t; -/** The maximum number of CS steps allowed during a CS event */ +/** The maximum number of CS steps allowed during a CS event. */ #define RAIL_BLE_CS_MAX_SQTE_STEPS 512U /** @@ -973,22 +1001,33 @@ typedef struct RAIL_BLE_CsConfig { * @brief The current CS step state. */ RAIL_ENUM(RAIL_BLE_CsStepState_t) { - /** CS step state idle */ + /** CS step state idle. */ RAIL_BLE_CS_STATE_IDLE = 0, - /** CS step state initiator initiator transmit mode 0 */ + /** CS step state initiator initiator transmit mode 0. */ RAIL_BLE_CS_STATE_I_TX_MODE0 = 1, - /** CS step state initiator reflector transmit mode 0 */ + /** CS step state initiator reflector transmit mode 0. */ RAIL_BLE_CS_STATE_R_TX_MODE0 = 2, - /** CS step state initiator initiator transmit mode 1 */ + /** CS step state initiator initiator transmit mode 1. */ RAIL_BLE_CS_STATE_I_TX_MODE1 = 3, - /** CS step state initiator reflector transmit mode 1 */ + /** CS step state initiator reflector transmit mode 1. */ RAIL_BLE_CS_STATE_R_TX_MODE1 = 4, - /** CS step state initiator initiator transmit mode 2 */ + /** CS step state initiator initiator transmit mode 2. */ RAIL_BLE_CS_STATE_R_TX_MODE2 = 6, - /** CS step state initiator reflector transmit mode 2 */ + /** CS step state initiator reflector transmit mode 2. */ RAIL_BLE_CS_STATE_I_TX_MODE2 = 7, }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_CS_STATE_IDLE ((RAIL_BLE_CsStepState_t) RAIL_BLE_CS_STATE_IDLE) +#define RAIL_BLE_CS_STATE_I_TX_MODE0 ((RAIL_BLE_CsStepState_t) RAIL_BLE_CS_STATE_I_TX_MODE0) +#define RAIL_BLE_CS_STATE_R_TX_MODE0 ((RAIL_BLE_CsStepState_t) RAIL_BLE_CS_STATE_R_TX_MODE0) +#define RAIL_BLE_CS_STATE_I_TX_MODE1 ((RAIL_BLE_CsStepState_t) RAIL_BLE_CS_STATE_I_TX_MODE1) +#define RAIL_BLE_CS_STATE_R_TX_MODE1 ((RAIL_BLE_CsStepState_t) RAIL_BLE_CS_STATE_R_TX_MODE1) +#define RAIL_BLE_CS_STATE_R_TX_MODE2 ((RAIL_BLE_CsStepState_t) RAIL_BLE_CS_STATE_R_TX_MODE2) +#define RAIL_BLE_CS_STATE_I_TX_MODE2 ((RAIL_BLE_CsStepState_t) RAIL_BLE_CS_STATE_I_TX_MODE2) +#endif//DOXYGEN_SHOULD_SKIP_THIS + /** * First step state for CS mode 0. */ @@ -1009,23 +1048,54 @@ RAIL_ENUM(RAIL_BLE_CsStepState_t) { * @brief The CS step mode. */ RAIL_ENUM(RAIL_BLE_CsStepMode_t) { - RAIL_BLE_CS_MODE_0, /**< CS step mode 0. */ - RAIL_BLE_CS_MODE_1, /**< CS step mode 1. */ - RAIL_BLE_CS_MODE_2, /**< CS step mode 2. */ - RAIL_BLE_CS_MODE_3, /**< CS step mode 3. */ + /** CS step mode 0. */ + RAIL_BLE_CS_MODE_0 = 0, + /** CS step mode 1. */ + RAIL_BLE_CS_MODE_1 = 1, + /** CS step mode 2. */ + RAIL_BLE_CS_MODE_2 = 2, + /** CS step mode 3. */ + RAIL_BLE_CS_MODE_3 = 3, }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_CS_MODE_0 ((RAIL_BLE_CsStepMode_t) RAIL_BLE_CS_MODE_0) +#define RAIL_BLE_CS_MODE_1 ((RAIL_BLE_CsStepMode_t) RAIL_BLE_CS_MODE_1) +#define RAIL_BLE_CS_MODE_2 ((RAIL_BLE_CsStepMode_t) RAIL_BLE_CS_MODE_2) +#define RAIL_BLE_CS_MODE_3 ((RAIL_BLE_CsStepMode_t) RAIL_BLE_CS_MODE_3) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** The maximum number of antennas supported. */ +#define RAIL_BLE_CS_MAX_ANTENNAS 4U + /** * @enum RAIL_BLE_CsAntennaId_t - * @brief The CS antenna ID. + * @brief The CS antenna ID. Valid values according to the CS spec are within + * the range 1 and 4 inclusive. */ RAIL_ENUM(RAIL_BLE_CsAntennaId_t) { - RAIL_BLE_CS_ANTENNA_1 = 0, /**< CS antenna ID 1. */ - RAIL_BLE_CS_ANTENNA_2, /**< CS antenna ID 2. */ - RAIL_BLE_CS_ANTENNA_3, /**< CS antenna ID 3. */ - RAIL_BLE_CS_ANTENNA_4, /**< CS antenna ID 4. */ + /** Antenna ID of the first supported antenna. */ + RAIL_BLE_CS_ANTENNA_ID_1 = 1U, + /** Antenna ID of the second supported antenna. */ + RAIL_BLE_CS_ANTENNA_ID_2 = 2U, + /** Antenna ID of the third supported antenna. */ + RAIL_BLE_CS_ANTENNA_ID_3 = 3U, + /** Antenna ID of the fourth supported antenna. */ + RAIL_BLE_CS_ANTENNA_ID_4 = 4U, }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_CS_ANTENNA_ID_1 ((RAIL_BLE_CsAntennaId_t) RAIL_BLE_CS_ANTENNA_ID_1) +#define RAIL_BLE_CS_ANTENNA_ID_2 ((RAIL_BLE_CsAntennaId_t) RAIL_BLE_CS_ANTENNA_ID_2) +#define RAIL_BLE_CS_ANTENNA_ID_3 ((RAIL_BLE_CsAntennaId_t) RAIL_BLE_CS_ANTENNA_ID_3) +#define RAIL_BLE_CS_ANTENNA_ID_4 ((RAIL_BLE_CsAntennaId_t) RAIL_BLE_CS_ANTENNA_ID_4) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** The value returned by RAIL for an invalid CS antenna count. */ +#define RAIL_BLE_CS_INVALID_ANTENNA_COUNT 0U + /** * @enum RAIL_BLE_CsRttPacketQuality_t * @brief CS RTT packet quality. @@ -1039,6 +1109,13 @@ RAIL_ENUM(RAIL_BLE_CsRttPacketQuality_t) { RAIL_BLE_CS_RTT_AA_NOT_FOUND = 2U, }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_CS_RTT_AA_SUCCESS ((RAIL_BLE_CsRttPacketQuality_t) RAIL_BLE_CS_RTT_AA_SUCCESS) +#define RAIL_BLE_CS_RTT_AA_BIT_ERRORS ((RAIL_BLE_CsRttPacketQuality_t) RAIL_BLE_CS_RTT_AA_BIT_ERRORS) +#define RAIL_BLE_CS_RTT_AA_NOT_FOUND ((RAIL_BLE_CsRttPacketQuality_t) RAIL_BLE_CS_RTT_AA_NOT_FOUND) +#endif//DOXYGEN_SHOULD_SKIP_THIS + /** * @struct RAIL_BLE_CsMode0Results_t * @brief Contains CS mode 0 step measurement results. @@ -1050,16 +1127,16 @@ typedef struct RAIL_BLE_CsMode0Results { RAIL_BLE_CsAntennaId_t antenna; /** RSSI during step in integer dBm. */ int8_t rssi; - /** Packet quality */ + /** Packet quality. */ uint8_t packetQuality; - /** Reserved */ + /** Reserved. */ uint16_t reserved; - /** Fractional Frequency Offset (FFO) * 100 */ + /** Fractional Frequency Offset (FFO) in units of parts per 100 million. */ int16_t csFfoPp100m; /** The gain setting. */ uint32_t stepGainSetting; - /** Reserved */ - uint32_t reserved1; + /** Reserved. */ + uint32_t reserved1[4]; } RAIL_BLE_CsMode0Results_t; /** @@ -1079,7 +1156,7 @@ typedef struct RAIL_BLE_CsMode1Results { RAIL_BLE_CsAntennaId_t antenna; /** RSSI during step in integer dBm. */ int8_t rssi; - /** Packet quality */ + /** Packet quality. */ uint8_t packetQuality; /** * For the initiator, this is the time (in 0.5 ns units) between time of @@ -1090,12 +1167,12 @@ typedef struct RAIL_BLE_CsMode1Results { * period and packet length. */ int16_t rttHalfNs; - /** Flag used to indicate whether we have missed FCAL during calibration */ + /** Flag used to indicate whether we have missed frequency calibration. */ uint8_t missedFcal; - /** Reserved */ - uint8_t reserved1; - /** Reserved */ - uint32_t reserved2[2]; + /** Reserved. */ + uint8_t reserved; + /** Reserved. */ + uint32_t reserved1[5]; } RAIL_BLE_CsMode1Results_t; /** @@ -1113,6 +1190,20 @@ RAIL_ENUM(RAIL_BLE_CsToneQuality_t) { RAIL_BLE_CS_TONE_QUALITY_UNAVAILABLE = 3U, }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_CS_TONE_QUALITY_GOOD ((RAIL_BLE_CsToneQuality_t) RAIL_BLE_CS_TONE_QUALITY_GOOD) +#define RAIL_BLE_CS_TONE_QUALITY_MEDIUM ((RAIL_BLE_CsToneQuality_t) RAIL_BLE_CS_TONE_QUALITY_MEDIUM) +#define RAIL_BLE_CS_TONE_QUALITY_LOW ((RAIL_BLE_CsToneQuality_t) RAIL_BLE_CS_TONE_QUALITY_LOW) +#define RAIL_BLE_CS_TONE_QUALITY_UNAVAILABLE ((RAIL_BLE_CsToneQuality_t) RAIL_BLE_CS_TONE_QUALITY_UNAVAILABLE) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** The minimum number of antenna slots supported during a CS event. */ +#define RAIL_BLE_CS_MIN_ANTENNA_SLOTS 2U + +/** The maximum number of antenna slots supported during a CS event. */ +#define RAIL_BLE_CS_MAX_ANTENNA_SLOTS 5U + /** * @struct RAIL_BLE_CsMode2Results_t * @brief Contains CS mode 2 step measurement results. @@ -1120,26 +1211,16 @@ RAIL_ENUM(RAIL_BLE_CsToneQuality_t) { typedef struct RAIL_BLE_CsMode2Results { /** Mode of CS step. */ uint8_t mode; - /** Antenna ID. */ - RAIL_BLE_CsAntennaId_t antenna; - /** Flag used to indicate whether we have missed FCAL during calibration */ + /** Flag used to indicate whether we have missed frequency calibration. */ uint8_t missedFcal; - /** Reserved */ - uint8_t reserved1; - /** PCT i value */ - int16_t pctI; - /** PCT q value */ - int16_t pctQ; - /** Tone extension PCT i value */ - int16_t pctToneExtI; - /** Tone extension PCT q value */ - int16_t pctToneExtQ; - /** Tone quality indicator */ - RAIL_BLE_CsToneQuality_t tqi; - /** Tone quality indicator for tone extension */ - RAIL_BLE_CsToneQuality_t tqiToneExt; - /** Reserved */ - uint16_t reserved2; + /** PCT i value. */ + int16_t pctI[RAIL_BLE_CS_MAX_ANTENNA_SLOTS]; + /** PCT q value. */ + int16_t pctQ[RAIL_BLE_CS_MAX_ANTENNA_SLOTS]; + /** Tone quality indicator. */ + RAIL_BLE_CsToneQuality_t tqi[RAIL_BLE_CS_MAX_ANTENNA_SLOTS]; + /** Reserved. */ + uint8_t reserved[3]; } RAIL_BLE_CsMode2Results_t; /** @@ -1147,17 +1228,17 @@ typedef struct RAIL_BLE_CsMode2Results { * @brief Generic CS step mode result structure. Based on the value of the * mode field, this structure can be type cast to the appropriate mode * specific structure \ref RAIL_BLE_CsMode0Results_t, - * \ref RAIL_BLE_CsMode1Results_t, or RAIL_BLE_CsMode2Results_t. + * \ref RAIL_BLE_CsMode1Results_t, or \ref RAIL_BLE_CsMode2Results_t. */ typedef struct RAIL_BLE_CsStepResults { /** Mode of CS step. */ uint8_t mode; - /** Reserved */ - uint8_t reserved0; - /** Reserved */ + /** Reserved. */ + uint8_t reserved; + /** Reserved. */ uint16_t reserved1; - /** Reserved */ - uint32_t reserved2[3]; + /** Reserved. */ + uint32_t reserved2[6]; } RAIL_BLE_CsStepResults_t; /** @@ -1176,15 +1257,13 @@ typedef struct RAIL_BLE_CsMode0DebugResults { * configured as a reflector, this value will always be 0. */ int32_t freqOffHz; - /** - * Estimated coarse frequency offset in internal units. - */ + /** Estimated coarse frequency offset in internal units. */ int32_t hwFreqOffEst; /** Starting index IQ sample index of unmodulated carrier. */ uint16_t ucStartIndex; /** End index IQ sample index of unmodulated carrier. */ uint16_t ucEndIndex; - /** Reserved */ + /** Reserved. */ uint32_t reserved[2]; /** * FFO of the Mode 0 step with the highest recorded RSSI @@ -1193,8 +1272,10 @@ typedef struct RAIL_BLE_CsMode0DebugResults { int16_t csFfoPp100m; /** Highest recorded RSSI up to and including the current mode 0 step, in dBm. */ int8_t highestRssiDbm; - /** Reserved */ - uint8_t reserved0; + /** Reserved. */ + uint8_t reserved1; + /** Reserved. */ + uint32_t reserved2[3]; } RAIL_BLE_CsMode0DebugResults_t; /** @@ -1202,14 +1283,24 @@ typedef struct RAIL_BLE_CsMode0DebugResults { * @brief Contains CS mode 1 step measurement debug results. */ typedef struct RAIL_BLE_CsMode1DebugResults { + /** Coarse time of flight in units of HFXO clock cycles. */ uint16_t toxClks; + /** Fractional component of time of flight in units of half nanoseconds. */ int16_t fracRttHalfNs; + /** Coarse component of time of flight in units of half nanoseconds. */ uint32_t coarseRttHalfNs; + /** Group delay compensation in units of half nanoseconds. */ int32_t gdCompRttHalfNs; + /** Time of flight without T_SY_CENTER_DELTA compensation in units of half nanoseconds. */ int32_t toxWithOffsetsRttHalfNs; + /** Internal CS status register. */ uint32_t csstatus3; + /** Internal CS status register. */ uint32_t csstatus4; + /** Internal CS status register. */ uint32_t csstatus5; + /** Reserved. */ + uint32_t reserved[3]; } RAIL_BLE_CsMode1DebugResults_t; /** @@ -1217,30 +1308,36 @@ typedef struct RAIL_BLE_CsMode1DebugResults { * @brief Contains CS mode 2 step measurement debug results. */ typedef struct RAIL_BLE_CsMode2DebugResults { - /** Hardware PCT I value */ + /** Hardware PCT I value. */ int16_t hardwarePctI; - /** Hardware PCT Q value */ + /** Hardware PCT Q value. */ int16_t hardwarePctQ; - /** DCCOMP i value */ + /** DCCOMP i value. */ int16_t dcCompI; - /** DCCOMP q value */ + /** DCCOMP q value. */ int16_t dcCompQ; - /** GDCOMP i value */ - int16_t gdCompI; - /** GDCOMP q value */ - int16_t gdCompQ; - /** Raw tone quality value */ + /** GDCOMP i value. */ + int16_t gdCompI[RAIL_BLE_CS_MAX_ANTENNAS]; + /** GDCOMP q value. */ + int16_t gdCompQ[RAIL_BLE_CS_MAX_ANTENNAS]; + /** Raw tone quality value. */ uint16_t tqiRaw; - /** Raw tone quality tone extension value */ + /** Raw tone quality tone extension value. */ uint16_t tqiToneExtRaw; - /** FCAL value from SYNTH_VCOTUNING */ + /** + * Pointer to the starting index of each antenna slot for + * reading IQ samples. + */ + uint16_t *ucStartIndex; + /** + * Pointer to the end index of each antenna slot for + * reading IQ samples. + */ + uint16_t *ucEndIndex; + /** Frequency calibration value in internal units. */ uint16_t fcal; - /** Starting index for reading IQ samples */ - uint16_t ucStartIndex; - /** End index for reading IQ samples */ - uint16_t ucEndIndex; - /** Reserved */ - uint16_t reserved[3]; + /** Reserved. */ + uint16_t reserved; } RAIL_BLE_CsMode2DebugResults_t; /** @@ -1248,21 +1345,34 @@ typedef struct RAIL_BLE_CsMode2DebugResults { * @brief Generic CS step mode debug result structure. Based on the value of * the mode field, this structure can be type cast to the appropriate mode * specific structure \ref RAIL_BLE_CsMode0DebugResults_t, - * \ref RAIL_BLE_CsMode1DebugResults_t, or RAIL_BLE_CsMode2DebugResults_t. + * \ref RAIL_BLE_CsMode1DebugResults_t, or \ref RAIL_BLE_CsMode2DebugResults_t. */ typedef struct RAIL_BLE_CsStepDebugResults { + /** Reserved. */ uint32_t reserved; + /** Reserved. */ uint32_t reserved1; + /** Reserved. */ uint32_t reserved2; + /** Reserved. */ uint32_t reserved3; + /** Reserved. */ uint32_t reserved4; + /** Reserved. */ uint32_t reserved5; + /** Reserved. */ uint32_t reserved6; + /** Reserved. */ + uint32_t reserved7; + /** Reserved. */ + uint32_t reserved8; + /** Reserved. */ + uint32_t reserved9; } RAIL_BLE_CsStepDebugResults_t; /** * @struct RAIL_BLE_CsStepConfig_t - * @brief Contains arguments for \ref RAIL_BLE_SetNextCsStep. + * @brief Contains arguments for \ref RAIL_BLE_SetNextCsStep(). */ typedef struct RAIL_BLE_CsStepConfig { /** Sets the CS step state. */ @@ -1281,14 +1391,14 @@ typedef struct RAIL_BLE_CsStepConfig { uint8_t packetLength; /** Sets the CS step logical channel. */ uint16_t channel; + /** RTT marker bit positions. Ignored for mode 0 and 2 steps. */ + uint8_t rttMarkerBitPosition[2]; /** The initiator (first) access address during step. */ uint32_t initAccessAddress; /** The reflector (second) access address during step. */ uint32_t reflAccessAddress; - /** Pointer to TX data to be transmitted. Ignored for mode 0 and 2 steps. */ + /** A pointer to TX data to be transmitted. Ignored for mode 0 and 2 steps. */ uint8_t *pTxData; - /** RTT marker bit position. Ignored for mode 0 and 2 steps. */ - uint8_t rttMarkerBitPosition[2]; /** * A pointer to an array of CS step results. These results will be * populated after the completion of the CS step. This array can be cast to @@ -1330,41 +1440,58 @@ typedef struct RAIL_BLE_CsStepConfig { * IQ data from that step was actually preserved. */ bool *pSaveIqData; + /** + * Array containing antenna settings for this step. This field has two uses + * depending on the mode of the current step. + * + * On mode 0 and mode 1 steps, only the first element will be used to + * indicate the antenna to be utilized during a mode 0 and + * mode 1 step. + * + * On mode 2 steps, as many elements as + * \ref RAIL_BLE_CS_MAX_ANTENNA_SLOTS - 1 that were configured for the + * CS event will be applied. + * + * @note \ref RAIL_BLE_ConfigCsAntenna must be called prior to setting + * this field in order to set the antenna count as well as configure + * each antenna. Each element must be a valid antenna between 1 and + * the set antenna count. + */ + RAIL_BLE_CsAntennaId_t antennaSelectBuffer[RAIL_BLE_CS_MAX_ANTENNAS]; } RAIL_BLE_CsStepConfig_t; /** * @struct RAIL_BLE_CsAntennaConfig_t - * @brief Contains arguments for \ref RAIL_BLE_ConfigCsAntenna function. + * @brief Contains arguments for \ref RAIL_BLE_ConfigCsAntenna() function. */ typedef struct RAIL_BLE_CsAntennaConfig { - uint8_t antennaCount; /**< Total number of antenna elements. */ - const int16_t *pAntennaOffsetCm; /**< Pointer to antenna offsets in cm units. */ + /** Total number of antenna elements. */ + uint8_t antennaCount; + /** A pointer to antenna offsets in cm units. */ + const int16_t *pAntennaOffsetCm; } RAIL_BLE_CsAntennaConfig_t; -/** The maximum number of antennas supported. */ -#define RAIL_BLE_CS_MAX_ANTENNAS 4 - /** * @struct RAIL_BLE_CsGdCompTables_t * @brief Contains pointers to CS group delay compensation tables. */ typedef struct RAIL_BLE_CsGdCompTables { - /** Pointer to PBR phase LSB group delay compensation table. */ + /** A pointer to PBR phase LSB group delay compensation table. */ const int16_t *pPbrPhaseLsb; - /** Pointer to RTT slope group delay compensation table. */ + /** A pointer to RTT slope group delay compensation table. */ const int16_t *pRttSlope; - /** Pointer to RTT offset group delay compensation table. */ + /** A pointer to RTT offset group delay compensation table. */ const int16_t *pRttOffset; /** Common length for each table in units of int16_t. */ uint8_t length; } RAIL_BLE_CsGdCompTables_t; /** - * Configure High Accuracy Distance Measurement (CS) functionality. + * Configure Channel Sounding (CS) functionality. * * @param[in] railHandle A RAIL instance handle. - * @param[in] csConfig Configuration options for CS. - * @return RAIL_Status_t indicating success or failure of the call. + * @param[in] csConfig A non-NULL pointer to configuration options for CS. + * @return Status code indicating success of the function call. * * @warning This API is not safe to use in a multiprotocol app. */ @@ -1372,11 +1499,11 @@ RAIL_Status_t RAIL_BLE_ConfigCs(RAIL_Handle_t railHandle, const RAIL_BLE_CsConfig_t *csConfig); /** - * Enable High Accuracy Distance Measurement (CS) functionality. + * Enable Channel Sounding (CS) functionality. * * @param[in] railHandle A RAIL instance handle. * @param[in] enable Enable or disable CS functionality. - * @return RAIL_Status_t indicating success or failure of the call. + * @return Status code indicating success of the function call. * * @warning This API is not safe to use in a multiprotocol app. */ @@ -1387,11 +1514,11 @@ RAIL_Status_t RAIL_BLE_EnableCs(RAIL_Handle_t railHandle, * Set up the next CS step. * * @param[in] railHandle A RAIL instance handle. - * @param[in,out] csStepConfig Configuration options for next CS step. + * @param[in,out] csStepConfig A pointer to configuration options for next CS step. * @param[in] pend If true, apply configuration at next appropriate radio - * transition (i.e. at Rx2Tx for an initiator, or Tx2Rx for a reflector). + * transition (i.e., at Rx-to-Tx for an initiator, or Tx-to-Rx for a reflector). * Otherwise, apply configuration immediately. - * @return RAIL_Status_t indicating success or failure of the call. + * @return Status code indicating success of the function call. * * @note When the next CS step is to be pended, the specified step in * csStepConfig must be the initial step state for a particular mode (e.g. @@ -1410,17 +1537,30 @@ RAIL_Status_t RAIL_BLE_SetNextCsStep(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[in] pAntennaConfig A pointer to the antenna config - * @return RAIL_Status_t indicating success or failure of the call. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_BLE_ConfigCsAntenna(RAIL_Handle_t railHandle, RAIL_BLE_CsAntennaConfig_t *pAntennaConfig); +/** + * Returns the number of antennas configured for a CS event. + * + * @param[in] railHandle A RAIL instance handle. + * @return The number of antennas configured for a CS event. + * + * @note If \ref RAIL_BLE_ConfigCsAntenna has not been called, this + * API will return \ref RAIL_BLE_CS_INVALID_ANTENNA_COUNT as + * no antennas have been configured for the CS event. The CS event + * will still run with an antenna count of 1 and 0 cm antenna offset. + */ +uint8_t RAIL_BLE_GetCsAntennaCount(RAIL_Handle_t railHandle); + /** * Loads the CS RTT and PBR group delay compensation tables for a * particular PA mode. * * @param[in] railHandle A RAIL instance handle. - * @param[in] pTables Pointer to group delay compensation lookup tables. + * @param[in] pTables A pointer to group delay compensation lookup tables. * @param[in] powerMode The PA mode for which to load compensation tables. * @return Status code indicating success of the function call. */ @@ -1430,14 +1570,14 @@ RAIL_Status_t RAIL_BLE_LoadCsCompTables(RAIL_Handle_t railHandle, /** * Callback used to load CS group delay compensation tables for all PA modes - * supported by device during \ref RAIL_BLE_EnableCs when enable is true. + * supported by device during \ref RAIL_BLE_EnableCs() when enable is true. * This function is optional to implement. * * @return Status code indicating success of the function call. * * @note If this callback function is not implemented, unneeded tables may not * be dead stripped, resulting in larger overall code size. The API \ref - * RAIL_BLE_LoadCsCompTables should be used within this callback to load the + * RAIL_BLE_LoadCsCompTables() should be used within this callback to load the * appropriate tables for each supported PA mode. */ RAIL_Status_t RAILCb_BLE_CsGdCompTableLoad(void); @@ -1463,7 +1603,7 @@ RAIL_Status_t RAILCb_BLE_CsGdCompTableLoad(void); /// }; /// /// // Send a normal packet on the current channel, then a packet on a new channel -/// int bleSendThenAdvertise(uint8_t *firstPacket, uint8_t *secondPacket) +/// void bleSendThenAdvertise(uint8_t *firstPacket, uint8_t *secondPacket) /// { /// // Load both packets into the FIFO /// RAIL_WriteTxFifo(railHandle, firstPacket, FIRST_PACKET_LEN, true); @@ -1561,7 +1701,7 @@ typedef struct RAIL_BLE_TxChannelHoppingConfig { /** * A pointer to the first element of an array of \ref * RAIL_BLE_TxChannelHoppingConfigEntry_t that represents the channels - * used during channel hopping. The length of this array must be + * used during channel hopping. The number of entries in this array must be * numberOfChannels. */ RAIL_BLE_TxChannelHoppingConfigEntry_t *entries; @@ -1606,7 +1746,7 @@ typedef struct RAIL_BLE_TxRepeatConfig { * Set up automatic repeated transmits after the next transmit. * * @param[in] railHandle A RAIL instance handle. - * @param[in] repeatConfig The configuration structure for repeated transmits. + * @param[in] repeatConfig A non-NULL pointer to the configuration structure for repeated transmits. * @return Status code indicating a success of the function call. * * Repeated transmits will occur after an application-initiated transmit caused @@ -1619,11 +1759,12 @@ typedef struct RAIL_BLE_TxRepeatConfig { * will receive events such as \ref RAIL_EVENT_TX_PACKET_SENT as normal. * * If a TX error occurs during the repetition, the process will abort and the - * TX error transition from \ref RAIL_SetTxTransitions will be used. If the + * TX error transition from \ref RAIL_SetTxTransitions() will be used. If the * repetition completes successfully, the TX success transition from - * \ref RAIL_SetTxTransitions will be used. + * \ref RAIL_SetTxTransitions() will be used. * - * Any call to \ref RAIL_Idle or \ref RAIL_StopTx will clear the pending + * Any call to \ref RAIL_Idle(), \ref RAIL_StopTx(), or \ref + * RAIL_SetTxTransitions() will clear the pending * repeated transmits. The state will also be cleared by another call to this * function. To clear the repeated transmits before they've started without * stopping other radio actions, call this function with a \ref @@ -1632,7 +1773,7 @@ typedef struct RAIL_BLE_TxRepeatConfig { * started. * * The application is responsible for populating the transmit data to be used - * by the repeated transmits via \ref RAIL_SetTxFifo or \ref RAIL_WriteTxFifo. + * by the repeated transmits via \ref RAIL_SetTxFifo() or \ref RAIL_WriteTxFifo(). * Data will be transmitted from the TX FIFO. If the TX FIFO does not have * sufficient data to transmit, a TX error and a \ref * RAIL_EVENT_TX_UNDERFLOW will occur. To avoid an underflow, the @@ -1661,8 +1802,9 @@ RAIL_Status_t RAIL_BLE_SetNextTxRepeat(RAIL_Handle_t railHandle, * Calibrate image rejection for Bluetooth Low Energy. * * @param[in] railHandle A RAIL instance handle. - * @param[out] imageRejection The result of the image rejection calibration. - * @return A status code indicating success of the function call. + * @param[out] imageRejection A pointer to where the result of the image + * rejection calibration will be stored. + * @return Status code indicating success of the function call. * * Some chips have protocol-specific image rejection calibrations programmed * into their flash. This function will either get the value from flash and diff --git a/simplicity_sdk/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h b/simplicity_sdk/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h index a89bd47c6..7991faa95 100644 --- a/simplicity_sdk/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h +++ b/simplicity_sdk/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h @@ -43,17 +43,17 @@ extern "C" { /// /// The functions in this group configure RAIL IEEE 802.15.4 hardware /// acceleration which includes IEEE 802.15.4 format filtering, address -/// filtering, ACKing, and filtering based on the frame type. +/// filtering, Acking, and filtering based on the frame type. /// /// To configure IEEE 802.15.4 functionality, the application must first set up -/// a RAIL instance with RAIL_Init() and other setup functions. -/// Instead of RAIL_ConfigChannels(), however, an -/// application may use RAIL_IEEE802154_Config2p4GHzRadio() to set up the +/// a RAIL instance with \ref RAIL_Init() and other setup functions. +/// Instead of \ref RAIL_ConfigChannels(), however, an +/// application may use \ref RAIL_IEEE802154_Config2p4GHzRadio() to set up the /// official IEEE 2.4 GHz 802.15.4 PHY. This configuration is shown below. /// /// 802.15.4 defines its macAckWaitDuration from the end of the transmitted -/// packet to complete reception of the ACK. RAIL's ackTimeout only covers -/// sync word detection of the ACK. Therefore, subtract the ACK's +/// packet to complete reception of the Ack. RAIL's ackTimeout only covers +/// sync word detection of the Ack. Therefore, subtract the Ack's /// PHY header and payload time to get RAIL's ackTimeout setting. /// For 2.4 GHz OQPSK, macAckWaitDuration is specified as 54 symbols; /// subtracting 2-symbol PHY header and 10-symbol payload yields a RAIL @@ -64,14 +64,14 @@ extern "C" { /// static const RAIL_IEEE802154_Config_t rail154Config = { /// .addresses = NULL, /// .ackConfig = { -/// .enable = true, // Turn on auto ACK for IEEE 802.15.4. +/// .enable = true, // Turn on auto Ack for IEEE 802.15.4. /// .ackTimeout = 672, // See note above: 54-12 sym * 16 us/sym = 672 us. /// .rxTransitions = { -/// .success = RAIL_RF_STATE_RX, // Return to RX after ACK processing +/// .success = RAIL_RF_STATE_RX, // Return to RX after Ack processing /// .error = RAIL_RF_STATE_RX, // Ignored /// }, /// .txTransitions = { -/// .success = RAIL_RF_STATE_RX, // Return to RX after ACK processing +/// .success = RAIL_RF_STATE_RX, // Return to RX after Ack processing /// .error = RAIL_RF_STATE_RX, // Ignored /// }, /// }, @@ -98,10 +98,10 @@ extern "C" { /// } /// @endcode /// -/// To configure address filtering, call +/// To configure address filtering, call \ref /// RAIL_IEEE802154_SetAddresses() with a structure containing all addresses or -/// call the individual RAIL_IEEE802154_SetPanId(), -/// RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress() +/// call the individual \ref RAIL_IEEE802154_SetPanId(), \ref +/// RAIL_IEEE802154_SetShortAddress(), and \ref RAIL_IEEE802154_SetLongAddress() /// APIs. RAIL supports \ref RAIL_IEEE802154_MAX_ADDRESSES number of address /// pairs to receive packets from multiple IEEE /// 802.15.4 networks at the same time. Broadcast addresses are supported by @@ -111,9 +111,9 @@ extern "C" { /// be found in the \ref RAIL_IEEE802154_AddrConfig_t documentation. Below is /// an example of setting filtering for one set of addresses. /// @code{.c} -/// // PanID OTA value of 0x34 0x12. -/// // Short Address OTA byte order of 0x78 0x56. -/// // Long address with OTA byte order of 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88. +/// // PAN Id over-the-air value of 0x34 0x12. +/// // Short Address over-the-air byte order of 0x78 0x56. +/// // Long address with over-the-air byte order of 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88. /// /// // Set up all addresses simultaneously. /// RAIL_Status_t setup1(void) @@ -129,52 +129,45 @@ extern "C" { /// } /// /// // Alternatively, the addresses can be set up individually as follows: -/// RAIL_Status_t setup2(void) +/// void setup2(void) /// { /// RAIL_Status_t status; /// const uint8_t longAddress[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 }; /// /// status = RAIL_IEEE802154_SetPanId(railHandle, 0x1234, 0); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return status -/// } +/// assert(status == RAIL_STATUS_NO_ERROR); /// status = RAIL_IEEE802154_SetShortAddress(railHandle, 0x5678, 0); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return status -/// } +/// assert(status == RAIL_STATUS_NO_ERROR); /// status = RAIL_IEEE802154_SetLongAddress(railHandle, longAddress, 0); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return status -/// } -/// -/// return RAIL_STATUS_NO_ERROR; +/// assert(status == RAIL_STATUS_NO_ERROR); /// } /// @endcode /// /// Address filtering will be enabled except when in promiscuous mode, which can -/// be set with RAIL_IEEE802154_SetPromiscuousMode(). The addresses may be +/// be set with \ref RAIL_IEEE802154_SetPromiscuousMode(). The addresses may be /// changed at runtime. However, if you are receiving a packet while /// reconfiguring the address filters, you may get undesired behavior so it's /// safest to do this while not in receive. /// -/// Auto ACK is controlled by the ackConfig and timings fields passed to +/// Auto Ack is controlled by the \ref RAIL_IEEE802154_Config_t::ackConfig +/// and \ref RAIL_IEEE802154_Config_t::timings fields passed to \ref /// RAIL_IEEE802154_Init(). After initialization, they may be controlled /// using the normal \ref Auto_Ack and \ref State_Transitions APIs. When in IEEE -/// 802.15.4 mode, the ACK will generally have a 5 byte length, its Frame Type -/// will be ACK, its Frame Version 0 (2003), and its Frame Pending bit will be +/// 802.15.4 mode, the Ack will generally have a 5 byte length, its Frame Type +/// will be Ack, its Frame Version 0 (2003), and its Frame Pending bit will be /// false unless the \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event is /// triggered in which case it will default to the /// \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks setting. /// If the default Frame Pending setting is incorrect, -/// the app must call \ref RAIL_IEEE802154_ToggleFramePending -/// (formerly \ref RAIL_IEEE802154_SetFramePending) while handling the +/// the app must call \ref RAIL_IEEE802154_ToggleFramePending() +/// (formerly \ref RAIL_IEEE802154_SetFramePending()) while handling the /// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. /// /// This event must be turned on by the user and will fire whenever a data /// request is being received so that the stack can determine if there /// is pending data. Note that if the default Frame Pending bit needs to -/// be changed, it must be done quickly. Otherwise, the ACK may already -/// have been transmitted with the default setting. Check the return code of +/// be changed, it must be done quickly. Otherwise, the Ack may already +/// have been transmitted with the default setting. Check the return code of \ref /// RAIL_IEEE802154_ToggleFramePending() to be sure that the bit was changed /// in time. /// @@ -190,8 +183,10 @@ extern "C" { * @brief Different lengths that an 802.15.4 address can have */ RAIL_ENUM(RAIL_IEEE802154_AddressLength_t) { - RAIL_IEEE802154_ShortAddress = 2, /**< 2 byte short address. */ - RAIL_IEEE802154_LongAddress = 3, /**< 8 byte extended address. */ + /** 2 byte short address. */ + RAIL_IEEE802154_ShortAddress = 2, + /** 8 byte extended address. */ + RAIL_IEEE802154_LongAddress = 3, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -207,11 +202,13 @@ RAIL_ENUM(RAIL_IEEE802154_AddressLength_t) { * This structure is only used for received source address information * needed to perform Frame Pending lookup. */ -typedef struct RAIL_IEEE802154_Address{ +typedef struct RAIL_IEEE802154_Address { /** Convenient storage for different address types. */ union { - uint16_t shortAddress; /**< Present for 2 byte addresses. */ - uint8_t longAddress[8]; /**< Present for 8 byte addresses. */ + /** Present for 2 byte addresses. */ + uint16_t shortAddress; + /** Present for 8 byte addresses. */ + uint8_t longAddress[8]; }; /** * Enumeration of the received address length. @@ -232,18 +229,18 @@ typedef struct RAIL_IEEE802154_Address{ * @brief A configuration structure for IEEE 802.15.4 Address Filtering. * * This structure allows configuration of multi-PAN functionality by specifying - * multiple PAN IDs and short addresses. A packet will be received if it matches - * an address and its corresponding PAN ID. Long address 0 and short address 0 - * match against PAN ID 0, etc. The broadcast PAN ID and address will work with - * any address or PAN ID, respectively. + * multiple PAN Ids and short addresses. A packet will be received if it matches + * an address and its corresponding PAN Id. Long address 0 and short address 0 + * match against PAN Id 0, etc. The broadcast PAN Id and address will work with + * any address or PAN Id, respectively. * * @note The broadcast addresses are handled separately and do not need to be * specified here. Any address to be ignored should be set with all bits high. */ -typedef struct RAIL_IEEE802154_AddrConfig{ +typedef struct RAIL_IEEE802154_AddrConfig { /** - * PAN IDs for destination filtering. All must be specified. - * To disable a PAN ID, set it to the broadcast value, 0xFFFF. + * PAN Ids for destination filtering. All must be specified. + * To disable a PAN Id, set it to the broadcast value, 0xFFFF. */ uint16_t panId[RAIL_IEEE802154_MAX_ADDRESSES]; /** @@ -253,7 +250,7 @@ typedef struct RAIL_IEEE802154_AddrConfig{ uint16_t shortAddr[RAIL_IEEE802154_MAX_ADDRESSES]; /** * A 64-bit address for destination filtering. All must be specified. - * This field is parsed in over-the-air (OTA) byte order. To disable a long + * This field is parsed in over-the-air byte order. To disable a long * address, set it to the reserved value of 0x00 00 00 00 00 00 00 00. */ uint8_t longAddr[RAIL_IEEE802154_MAX_ADDRESSES][8]; @@ -268,13 +265,13 @@ typedef struct RAIL_IEEE802154_Config { * Configure the RAIL Address Filter to allow the given destination * addresses. If this pointer is NULL, defer destination address configuration. * If a member of addresses is NULL, defer configuration of just that member. - * This can be overridden via RAIL_IEEE802154_SetAddresses(), or the - * individual members can be changed via RAIL_IEEE802154_SetPanId(), - * RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress(). + * This can be overridden via \ref RAIL_IEEE802154_SetAddresses(), or the + * individual members can be changed via \ref RAIL_IEEE802154_SetPanId(), \ref + * RAIL_IEEE802154_SetShortAddress(), and \ref RAIL_IEEE802154_SetLongAddress(). */ const RAIL_IEEE802154_AddrConfig_t *addresses; /** - * Define the ACKing configuration for the IEEE 802.15.4 implementation. + * Define the Acking configuration for the IEEE 802.15.4 implementation. */ RAIL_AutoAckConfig_t ackConfig; /** @@ -282,26 +279,26 @@ typedef struct RAIL_IEEE802154_Config { */ RAIL_StateTiming_t timings; /** - * Set which 802.15.4 frame types will be received, of Beacon, Data, ACK, and - * Command. This setting can be overridden via RAIL_IEEE802154_AcceptFrames(). + * Set which 802.15.4 frame types will be received, of Beacon, Data, Ack, and + * Command. This setting can be overridden via \ref RAIL_IEEE802154_AcceptFrames(). */ uint8_t framesMask; /** * Enable promiscuous mode during configuration. This can be overridden via - * RAIL_IEEE802154_SetPromiscuousMode() afterwards. + * \ref RAIL_IEEE802154_SetPromiscuousMode() afterwards. */ bool promiscuousMode; /** * Set whether the device is a PAN Coordinator during configuration. This can - * be overridden via RAIL_IEEE802154_SetPanCoordinator() afterwards. + * be overridden via \ref RAIL_IEEE802154_SetPanCoordinator() afterwards. */ bool isPanCoordinator; /** - * The default value for the Frame Pending bit in outgoing ACKs for packets + * The default value for the Frame Pending bit in outgoing Acks for packets * that triggered the \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. - * Such an ACK's Frame Pending bit can be inverted if necessary during the - * handling of that event by calling \ref RAIL_IEEE802154_ToggleFramePending - * (formerly \ref RAIL_IEEE802154_SetFramePending). + * Such an Ack's Frame Pending bit can be inverted if necessary during the + * handling of that event by calling \ref RAIL_IEEE802154_ToggleFramePending() + * (formerly \ref RAIL_IEEE802154_SetFramePending()). */ bool defaultFramePendingInOutgoingAcks; } RAIL_IEEE802154_Config_t; @@ -380,13 +377,13 @@ extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz; #ifndef DOXYGEN_SHOULD_SKIP_THIS /** - * Default PHY to use for 1Mbps 2.4 GHz 802.15.4 with forward error correction. + * Default PHY to use for 1 Mbps 2.4 GHz 802.15.4 with forward error correction. * Will be NULL if \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz1MbpsFec; /** - * Default PHY to use for 2Mbps 2.4 GHz 802.15.4. Will be NULL if + * Default PHY to use for 2 Mbps 2.4 GHz 802.15.4. Will be NULL if * \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz2Mbps; @@ -452,13 +449,13 @@ extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoexFem; extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCustom1; /** - * Default PHY to use for 863MHz GB868 802.15.4. Will be NULL if + * Default PHY to use for 863 MHz GB868 802.15.4. Will be NULL if * \ref RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_PhyGB863MHz; /** - * Default PHY to use for 915MHz GB868 802.15.4. Will be NULL if + * Default PHY to use for 915 MHz GB868 802.15.4. Will be NULL if * \ref RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 is 0. */ extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_PhyGB915MHz; @@ -474,28 +471,28 @@ extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzRxChSwitching; /** * Initialize RAIL for IEEE802.15.4 features. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] config An IEEE802154 configuration structure. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @param[in] config A non-NULL pointer to an IEEE802154 configuration structure. + * @return Status code indicating success of the function call. * * This function calls the following RAIL functions to configure the radio for * IEEE802.15.4 features. * * Initializes the following: * - Enables IEEE802154 hardware acceleration - * - Configures RAIL Auto ACK functionality + * - Configures RAIL Auto Ack functionality * - Configures RAIL Address Filter for 802.15.4 address filtering * * It saves having to call the following functions individually: - * - RAIL_ConfigAutoAck() - * - RAIL_SetRxTransitions() - * - RAIL_SetTxTransitions() - * - RAIL_WriteAutoAckFifo() - * - RAIL_SetStateTiming() - * - RAIL_ConfigAddressFilter() - * - RAIL_EnableAddressFilter() + * - \ref RAIL_ConfigAutoAck() + * - \ref RAIL_SetRxTransitions() + * - \ref RAIL_SetTxTransitions() + * - \ref RAIL_WriteAutoAckFifo() + * - \ref RAIL_SetStateTiming() + * - \ref RAIL_ConfigAddressFilter() + * - \ref RAIL_EnableAddressFilter() * - * It must be called before most of RAIL_IEEE802154_* function. + * It must be called before most of the RAIL_IEEE802154_* functions. */ RAIL_Status_t RAIL_IEEE802154_Init(RAIL_Handle_t railHandle, const RAIL_IEEE802154_Config_t *config); @@ -503,11 +500,11 @@ RAIL_Status_t RAIL_IEEE802154_Init(RAIL_Handle_t railHandle, /** * Configure the radio for 2.4 GHz 802.15.4 operation. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, + * calling \ref RAIL_ConfigChannels(). After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -518,12 +515,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio(RAIL_Handle_t railHandle); /** * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports antenna diversity. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, + * calling \ref RAIL_ConfigChannels(). After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -535,12 +532,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDiv(RAIL_Handle_t railHandle); * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity * optimized for radio coexistence. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports antenna diversity optimized for radio coexistence. It takes - * the place of calling \ref RAIL_ConfigChannels. After this call, + * the place of calling \ref RAIL_ConfigChannels(). After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -551,12 +548,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoex(RAIL_Handle_t railHand /** * Configure the radio for 2.4 GHz 802.15.4 operation optimized for radio coexistence. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports radio coexistence. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, + * calling \ref RAIL_ConfigChannels(). After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -567,12 +564,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCoex(RAIL_Handle_t railHandle); /** * Configure the radio for 2.4 GHz 802.15.4 operation with a front end module. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports a front end module. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, + * calling \ref RAIL_ConfigChannels(). After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -584,12 +581,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioFem(RAIL_Handle_t railHandle); * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity * optimized for a front end module. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports antenna diversity and a front end module. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, + * calling \ref RAIL_ConfigChannels(). After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -601,12 +598,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivFem(RAIL_Handle_t railHandl * Configure the radio for 2.4 GHz 802.15.4 operation optimized for radio coexistence * and a front end module. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports radio coexistence and a front end module. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, + * calling \ref RAIL_ConfigChannels(). After this call, * channels 11-26 will be available, giving the frequencies of those channels * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -618,12 +615,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCoexFem(RAIL_Handle_t railHandle) * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity * optimized for radio coexistence and a front end module. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation, but with a configuration * that supports antenna diversity, radio coexistence and a front end module. - * It takes the place of calling \ref RAIL_ConfigChannels. + * It takes the place of calling \ref RAIL_ConfigChannels(). * After this call, channels 11-26 will be available, giving the frequencies of * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. * @@ -634,24 +631,24 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoexFem(RAIL_Handle_t railH #ifndef DOXYGEN_SHOULD_SKIP_THIS /** - * Time in microseconds to listen for a packet on the 2Mbps channel. - * This timeout can be configured at runtime using \ref RAIL_IEEE802154_Config2MbpsRxTimeout. + * Time in microseconds to listen for a packet on the 2 Mbps channel. + * This timeout can be configured at runtime using \ref RAIL_IEEE802154_Config2MbpsRxTimeout(). */ #define RAIL_IEEE802154_2MBPS_RECEIVE_TIMEOUT_US 1500UL /** - * Configure the radio for 2.4 GHz 802.15.4 for 250kbps/2Mbps operation. + * Configure the radio for 2.4 GHz 802.15.4 for 250 kbps or 2 Mbps operation. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz high speed operation. - * It takes the place of calling \ref RAIL_ConfigChannels. + * It takes the place of calling \ref RAIL_ConfigChannels(). * After this call, channels 11-26 will be available, giving the frequencies of * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2 - * at 250kbps. + * at 250 kbps. * Channels 11-26 will support transmitting and receiving using dual sync words. - * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 2Mbps. + * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 2 Mbps. * Auto-ack and address filtering are disabled when channels 27-42 are selected. * * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. @@ -660,19 +657,19 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoexFem(RAIL_Handle_t railH RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio2Mbps(RAIL_Handle_t railHandle); /** - * Configure the radio for 2.4 GHz 802.15.4 for 250kbps/1Mbps forward error correction + * Configure the radio for 2.4 GHz 802.15.4 for 250 kbps or 1 Mbps forward error correction * operation. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz high speed operation. * It takes the place of calling \ref RAIL_ConfigChannels. * After this call, channels 11-26 will be available, giving the frequencies of * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2 - * at 250kbps. + * at 250 kbps. * Channels 11-26 will support transmitting and receiving using dual sync words. - * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 1Mbps. + * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 1 Mbps. * Auto-ack and address filtering are disabled when channels 27-42 are selected. * * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. @@ -683,15 +680,28 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio1MbpsFec(RAIL_Handle_t railHandle /** * Configure the 802.15.4 2Mbps receive timeout. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] timeout Time to listen for a packet on the 2Mbps channel - * before switching back to the 250kbps channel. + * @param[in] railHandle A RAIL instance handle. + * @param[in] timeout Time to listen for a packet on the 2 Mbps channel + * before switching back to the 250 kbps channel. * @return Status code indicating success of the function call. * - * @note By default the 2Mbps receive timeout is \ref RAIL_IEEE802154_2MBPS_RECEIVE_TIMEOUT_US. + * @note By default the 2 Mbps receive timeout is \ref RAIL_IEEE802154_2MBPS_RECEIVE_TIMEOUT_US. */ -RAIL_Status_t RAIL_IEEE802154_Config2MbpsRxTimeout(RAIL_Handle_t railHandle, RAIL_Time_t timeout); +RAIL_Status_t RAIL_IEEE802154_Config2MbpsRxTimeout(RAIL_Handle_t railHandle, + RAIL_Time_t timeout); +/** + * Configure the 802.15.4 2Mbps mode switch receive channel. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel 802.15.4 channel(11-26) to listen for a mode switch packet. + * @return Status code indicating success of the function call. + * + * Mode switch to the 2Mbps radio config will only occur on the provided channel. + * Mode switch packets received on other channels will be ignored. + */ +RAIL_Status_t RAIL_IEEE802154_Config2MbpsRxChannel(RAIL_Handle_t railHandle, + uint16_t channel); #endif //DOXYGEN_SHOULD_SKIP_THIS /** @@ -699,12 +709,12 @@ RAIL_Status_t RAIL_IEEE802154_Config2MbpsRxTimeout(RAIL_Handle_t railHandle, RAI * settings. It enables better interoperability with some proprietary * PHYs, but doesn't guarantee data sheet performance. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * This initializes the radio for 2.4 GHz operation with * custom settings. It replaces needing to call - * \ref RAIL_ConfigChannels. + * \ref RAIL_ConfigChannels(). * Do not call this function unless instructed by Silicon Labs. * * @note This feature is only available on platforms where @@ -713,13 +723,13 @@ RAIL_Status_t RAIL_IEEE802154_Config2MbpsRxTimeout(RAIL_Handle_t railHandle, RAI RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCustom1(RAIL_Handle_t railHandle); /** - * Configure the radio for SubGHz GB868 863 MHz 802.15.4 operation. + * Configure the radio for Sub-GHz GB868 863 MHz 802.15.4 operation. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * - * This initializes the radio for SubGHz GB868 863 MHz operation. It takes the - * place of calling \ref RAIL_ConfigChannels. + * This initializes the radio for Sub-GHz GB868 863 MHz operation. It takes the + * place of calling \ref RAIL_ConfigChannels(). * After this call, GB868 channels in the 863 MHz band (channel pages 28, 29, * and 30 -- logical channels 0x80..0x9A, 0xA0..0xA8, 0xC0..0xDA, respectively) * will be available, as defined by Rev 22 of the Zigbee Specification, 2017 @@ -730,13 +740,13 @@ RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCustom1(RAIL_Handle_t railHandle) RAIL_Status_t RAIL_IEEE802154_ConfigGB863MHzRadio(RAIL_Handle_t railHandle); /** - * Configure the radio for SubGHz GB868 915 MHz 802.15.4 operation. + * Configure the radio for Sub-GHz GB868 915 MHz 802.15.4 operation. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * - * This initializes the radio for SubGHz GB868 915 MHz operation. It takes the - * place of calling \ref RAIL_ConfigChannels. + * This initializes the radio for Sub-GHz GB868 915 MHz operation. It takes the + * place of calling \ref RAIL_ConfigChannels(). * After this call, GB868 channels in the 915 MHz band (channel page 31 -- * logical channels 0xE0..0xFA) will be available, as defined by Rev 22 of * the Zigbee Specification, 2017 document 05-3474-22, section D.10.2.1.3.2. @@ -748,22 +758,22 @@ RAIL_Status_t RAIL_IEEE802154_ConfigGB915MHzRadio(RAIL_Handle_t railHandle); /** * De-initialize IEEE802.15.4 hardware acceleration. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * Disables and resets all IEE802.15.4 hardware acceleration features. This * function should only be called when the radio is IDLE. This calls the * following: - * - RAIL_SetStateTiming(), to reset all timings to 100 us - * - RAIL_EnableAddressFilter(false) - * - RAIL_ResetAddressFilter() + * - \ref RAIL_SetStateTiming(), to reset all timings to 100 us + * - \ref RAIL_EnableAddressFilter() passing false for its enable parameter + * - \ref RAIL_ResetAddressFilter() */ RAIL_Status_t RAIL_IEEE802154_Deinit(RAIL_Handle_t railHandle); /** * Return whether IEEE802.15.4 hardware acceleration is currently enabled. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @return true if IEEE802.15.4 hardware acceleration was enabled to start with * and false otherwise. */ @@ -831,20 +841,20 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_PtiRadioConfig_t, uint16_t) { #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT) #endif//DOXYGEN_SHOULD_SKIP_THIS /** * Return IEEE802.15.4 PTI radio config. * - * @param[in] railHandle A handle of RAIL instance. - * @return PTI (Packet Trace Information) radio config ID. + * @param[in] railHandle A RAIL instance handle. + * @return PTI (Packet Trace Information) radio config Id. */ RAIL_IEEE802154_PtiRadioConfig_t RAIL_IEEE802154_GetPtiRadioConfig(RAIL_Handle_t railHandle); @@ -852,20 +862,20 @@ RAIL_IEEE802154_PtiRadioConfig_t RAIL_IEEE802154_GetPtiRadioConfig(RAIL_Handle_t /** * Set IEEE802.15.4 PTI radio config (for Silicon Labs internal use only). * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] ptiRadioConfig PTI (Packet Trace Information) radio config ID. + * @param[in] railHandle A RAIL instance handle. + * @param[in] ptiRadioConfig PTI (Packet Trace Information) radio config Id. * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_IEEE802154_SetPtiRadioConfig(RAIL_Handle_t railHandle, RAIL_IEEE802154_PtiRadioConfig_t ptiRadioConfigId); -#endif +#endif//DOXYGEN_SHOULD_SKIP_THIS /** * Configure the RAIL Address Filter for 802.15.4 filtering. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] addresses The address information that should be used. - * @return A status code indicating success of the function call. If this returns + * @param[in] railHandle A RAIL instance handle. + * @param[in] addresses A pointer to the address information that should be used. + * @return Status code indicating success of the function call. If this returns * an error, the 802.15.4 address filter is in an undefined state. * * Set up the 802.15.4 address filter to accept messages to the given @@ -877,18 +887,18 @@ RAIL_Status_t RAIL_IEEE802154_SetAddresses(RAIL_Handle_t railHandle, const RAIL_IEEE802154_AddrConfig_t *addresses); /** - * Set a PAN ID for 802.15.4 address filtering. + * Set a PAN Id for 802.15.4 address filtering. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] panId The 16-bit PAN ID information. - * This will be matched against the destination PAN ID of incoming messages. - * The PAN ID is sent little endian over the air, meaning panId[7:0] is first in + * @param[in] railHandle A RAIL instance handle. + * @param[in] panId The 16-bit PAN Id information. + * This will be matched against the destination PAN Id of incoming messages. + * The PAN Id is sent little endian over the air, meaning panId[7:0] is first in * the payload followed by panId[15:8]. Set to 0xFFFF to disable for this index. - * @param[in] index Indicates which PAN ID to set. Must be below - * RAIL_IEEE802154_MAX_ADDRESSES. - * @return A status code indicating success of the function call. + * @param[in] index Indicates which PAN Id to set. Must be below + * \ref RAIL_IEEE802154_MAX_ADDRESSES. + * @return Status code indicating success of the function call. * - * Set up the 802.15.4 address filter to accept messages to the given PAN ID. + * Set up the 802.15.4 address filter to accept messages to the given PAN Id. */ RAIL_Status_t RAIL_IEEE802154_SetPanId(RAIL_Handle_t railHandle, uint16_t panId, @@ -903,8 +913,8 @@ RAIL_Status_t RAIL_IEEE802154_SetPanId(RAIL_Handle_t railHandle, * little endian over the air meaning shortAddr[7:0] is first in the payload * followed by shortAddr[15:8]. Set to 0xFFFF to disable for this index. * @param[in] index Which short address to set. Must be below - * RAIL_IEEE802154_MAX_ADDRESSES. - * @return A status code indicating success of the function call. + * \ref RAIL_IEEE802154_MAX_ADDRESSES. + * @return Status code indicating success of the function call. * * Set up the 802.15.4 address filter to accept messages to the given short * address. @@ -916,14 +926,14 @@ RAIL_Status_t RAIL_IEEE802154_SetShortAddress(RAIL_Handle_t railHandle, /** * Set a long address for 802.15.4 address filtering. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] longAddr A pointer to an 8-byte array containing the long address * information. The long address must be in over-the-air byte order. This will * be matched against the destination long address of incoming messages. Set to * 0x00 00 00 00 00 00 00 00 to disable for this index. * @param[in] index Indicates which long address to set. Must be below - * RAIL_IEEE802154_MAX_ADDRESSES. - * @return A status code indicating success of the function call. + * \ref RAIL_IEEE802154_MAX_ADDRESSES. + * @return Status code indicating success of the function call. * * Set up the 802.15.4 address filter to accept messages to the given long * address. @@ -935,9 +945,9 @@ RAIL_Status_t RAIL_IEEE802154_SetLongAddress(RAIL_Handle_t railHandle, /** * Set whether the current node is a PAN coordinator. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] isPanCoordinator true if this device is a PAN coordinator. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * If the device is a PAN Coordinator, it will accept data and command * frames with no destination address. This function will fail if 802.15.4 @@ -951,9 +961,9 @@ RAIL_Status_t RAIL_IEEE802154_SetPanCoordinator(RAIL_Handle_t railHandle, /** * Set whether to enable 802.15.4 promiscuous mode. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] enable true if all frames and addresses should be accepted. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * If promiscuous mode is enabled, no frame or address filtering steps * will be performed other than checking the CRC. This function will fail if @@ -971,7 +981,9 @@ RAIL_Status_t RAIL_IEEE802154_SetPromiscuousMode(RAIL_Handle_t railHandle, RAIL_ENUM_GENERIC(RAIL_IEEE802154_EOptions_t, uint32_t) { /** Shift position of \ref RAIL_IEEE802154_E_OPTION_GB868 bit. */ RAIL_IEEE802154_E_OPTION_GB868_SHIFT = 0, + /** Shift position of \ref RAIL_IEEE802154_E_OPTION_ENH_ACK bit. */ RAIL_IEEE802154_E_OPTION_ENH_ACK_SHIFT, + /** Shift position of \ref RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST bit. */ RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST_SHIFT, }; @@ -994,37 +1006,37 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_EOptions_t, uint32_t) { * that feature. * * @note This feature does not automatically enable receiving Multipurpose - * frames; that can be enabled via RAIL_IEEE802154_AcceptFrames()'s + * frames; that can be enabled via \ref RAIL_IEEE802154_AcceptFrames()'s * \ref RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES. */ #define RAIL_IEEE802154_E_OPTION_GB868 (1UL << RAIL_IEEE802154_E_OPTION_GB868_SHIFT) /** - * An option to enable/disable 802.15.4E-2012 features needed for Enhanced ACKs. + * An option to enable/disable 802.15.4E-2012 features needed for Enhanced Acks. * This option requires that \ref RAIL_IEEE802154_E_OPTION_GB868 also be * enabled, and is enabled automatically on platforms that support this * feature. It exists as a separate flag to allow runtime detection of whether * the platform supports this feature or not. * - * When enabled, only an Enhanced ACK is expected in response to a transmitted - * ACK-requesting 802.15.4E Version 2 frame. RAIL only knows how to construct - * 802.15.4 Immediate ACKs but not Enhanced ACKs. + * When enabled, only an Enhanced Ack is expected in response to a transmitted + * Ack-requesting 802.15.4E Version 2 frame. RAIL only knows how to construct + * 802.15.4 Immediate Acks but not Enhanced Acks. * * This option causes \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND to be - * issued for ACK-requesting Version 2 MAC Command frames, Data frames + * issued for Ack-requesting Version 2 MAC Command frames, Data frames * (if \ref RAIL_IEEE802154_EnableDataFramePending() is enabled), and * Multipurpose Frames (if \ref RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES * is enabled). * * The application is expected to handle this event by calling \ref * RAIL_GetRxIncomingPacketInfo() and parsing the partly-received incoming - * frame to determine the type of ACK needed: - * - If an Immediate ACK, determine Frame Pending needs based on the packet + * frame to determine the type of Ack needed: + * - If an Immediate Ack, determine Frame Pending needs based on the packet * type and addressing information and call \ref * RAIL_IEEE802154_ToggleFramePending() if necessary; - * - If an Enhanced ACK, generate the complete payload of the Enhanced ACK + * - If an Enhanced Ack, generate the complete payload of the Enhanced Ack * including any Frame Pending information and call \ref - * RAIL_IEEE802154_WriteEnhAck() in time for that Enhanced ACK to + * RAIL_IEEE802154_WriteEnhAck() in time for that Enhanced Ack to * be sent. If not called in time, \ref RAIL_EVENT_TXACK_UNDERFLOW will * likely result. * Note that if 802.15.4 MAC-level encryption is used with Version 2 @@ -1037,8 +1049,8 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_EOptions_t, uint32_t) { * need to examine the MAC Command byte of MAC Command frames but can * infer it to be a Data Request. * - * On 802.15.4E GB868 platforms that lack this support, legacy Immediate ACKs - * are sent/expected for received/transmitted ACK-requesting 802.15.4E Frame + * On 802.15.4E GB868 platforms that lack this support, legacy Immediate Acks + * are sent/expected for received/transmitted Ack-requesting 802.15.4E Frame * Version 2 frames; calls to \ref RAIL_IEEE802154_WriteEnhAck() have no * effect. Attempting to use this feature via \ref * RAIL_IEEE802154_ConfigEOptions() returns an error. @@ -1049,8 +1061,8 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_EOptions_t, uint32_t) { * An option to enable/disable 802.15.4E-2012 macImplicitBroadcast feature. * * When enabled, received Frame Version 2 frames without a destination - * PAN ID or destination address are treated as though they are addressed - * to the broadcast PAN ID and broadcast short address. When disabled, such + * PAN Id or destination address are treated as though they are addressed + * to the broadcast PAN Id and broadcast short address. When disabled, such * frames are filtered unless the device is the PAN coordinator and * appropriate source addressing information exists in the packet */ @@ -1062,12 +1074,12 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_EOptions_t, uint32_t) { /** * Configure certain 802.15.4E-2012 / 802.15.4-2015 Frame Version 2 features. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] mask A bitmask containing which options should be modified. * @param[in] options A bitmask containing desired options settings. * Bit positions for each option are found in the \ref * RAIL_IEEE802154_EOptions_t. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function will fail if 802.15.4 hardware acceleration is not * currently enabled by calling \ref RAIL_IEEE802154_Init() or the platform @@ -1110,8 +1122,8 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_GOptions_t, uint32_t) { * - On platforms where \ref RAIL_FEAT_IEEE802154_G_4BYTE_CRC_SUPPORTED * is true: automatic per-packet 2/4-byte Frame Check Sequence (FCS) * reception and transmission based on the FCS Type bit in the - * received/transmitted PHY header. This includes ACK reception - * and automatically-generated ACKs reflect the CRC size of the + * received/transmitted PHY header. This includes Ack reception + * and automatically-generated Acks reflect the CRC size of the * incoming frame being acknowledged (i.e., their MAC payload will be * increased to 7 bytes when sending 4-byte FCS). * On other platforms, only the 2-byte FCS is supported. @@ -1119,7 +1131,7 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_GOptions_t, uint32_t) { * and/or \ref RAIL_FEAT_IEEE802154_G_UNWHITENED_TX_SUPPORTED are true: * automatic per-packet whitened/unwhitened reception and transmission, * respectively, based on the Data Whitening bit in the received/transmitted - * PHY header. This includes ACK reception and automatically-generated ACKs + * PHY header. This includes Ack reception and automatically-generated Acks * which reflect the whitening of the incoming frame being acknowledged. * On other platforms, only whitened frames are supported. * - Support for frames up to 2049 bytes per the radio configuration's @@ -1132,26 +1144,28 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_GOptions_t, uint32_t) { * packet's PHY header Data Whitening flag. */ #define RAIL_IEEE802154_G_OPTION_GB868 (1UL << RAIL_IEEE802154_G_OPTION_GB868_SHIFT) + /** * An option to enable/disable 802.15.4G dynamic FEC feature (SUN FSK only). - * The syncWord, called start-of-frame delimiter (SFD) in the 15.4 spec, indicates whether + * The sync word, called start-of-frame delimiter (SFD) in the 15.4 spec, indicates whether * the rest of the packet is FEC encoded or not. This feature requires per-packet - * dual syncWord detection and specific receiver pausing. + * dual sync word detection and specific receiver pausing. * Note that this feature is only available on platforms where * \ref RAIL_IEEE802154_SUPPORTS_G_DYNFEC is true. * * This option is only valid for SUN PHYs that have the FEC configured and enabled. * - * The syncWord used during transmit is selected with \ref RAIL_TX_OPTION_SYNC_WORD_ID. + * The sync word used during transmit is selected with \ref RAIL_TX_OPTION_SYNC_WORD_ID. * - * The syncWord corresponding to the FEC encoded mode must be SYNC1, with SYNC2 indicating non-FEC. - * SyncWords are set appropriately in all Sun FEC-enabled PHYs so there should + * The sync word corresponding to the FEC encoded mode must be SYNC1, with SYNC2 indicating non-FEC. + * Sync words are set appropriately in all Sun FEC-enabled PHYs so there should * never be a need to call \ref RAIL_ConfigSyncWords() when this option is enabled. * - * Also, dual syncWord detection is set in all SUN FEC enabled PHYs, then there is no need - * to change \ref RAIL_RX_OPTION_ENABLE_DUALSYNC . + * Also, dual sync word detection is set in all SUN FEC enabled PHYs, then there is no need + * to change \ref RAIL_RX_OPTION_ENABLE_DUALSYNC. */ #define RAIL_IEEE802154_G_OPTION_DYNFEC (1UL << RAIL_IEEE802154_G_OPTION_DYNFEC_SHIFT) + /** * An option to enable/disable Wi-SUN Mode Switch feature. * This feature consists in switching to a new PHY mode with a higher rate typically @@ -1169,12 +1183,12 @@ RAIL_ENUM_GENERIC(RAIL_IEEE802154_GOptions_t, uint32_t) { * Configure certain 802.15.4G-2012 / 802.15.4-2015 SUN PHY features * (only for radio configurations designed accordingly). * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] mask A bitmask containing which options should be modified. * @param[in] options A bitmask containing desired options settings. * Bit positions for each option are found in the \ref * RAIL_IEEE802154_GOptions_t. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function will fail if 802.15.4 hardware acceleration is not * currently enabled by calling \ref RAIL_IEEE802154_Init(), the platform does @@ -1187,40 +1201,42 @@ RAIL_Status_t RAIL_IEEE802154_ConfigGOptions(RAIL_Handle_t railHandle, /** * @struct RAIL_IEEE802154_ModeSwitchPhr_t - * @brief A structure containing the PHYModeID value and the corresponding mode + * @brief A structure containing the PHY Mode Id value and the corresponding mode * switch PHR as defined in Wi-SUN spec. * These structures are usually generated by the radio configurator. */ typedef struct RAIL_IEEE802154_ModeSwitchPhr { - uint8_t phyModeId; /**< PHY mode Id */ - uint16_t phr; /**< Corresponding Mode Switch PHY header */ + /** PHY mode Id. */ + uint8_t phyModeId; + /** Corresponding Mode Switch PHY header. */ + uint16_t phr; } RAIL_IEEE802154_ModeSwitchPhr_t; #ifndef DOXYGEN_SHOULD_SKIP_THIS -/** When filtering PhyModeId, this is the minimum OFDM value */ +/** When filtering PHY Mode Id, this is the minimum OFDM value */ #define MIN_OFDM_PHY_MODE_ID (0x20U) -/** When filtering PhyModeId, this is the maximum OFDM value */ +/** When filtering PHY Mode Id, this is the maximum OFDM value */ #define MAX_OFDM_PHY_MODE_ID (0x5FU) #endif //DOXYGEN_SHOULD_SKIP_THIS /** - * Compute channel to switch to given a targeted PhyMode ID + * Compute channel to switch to given a targeted PHY Mode Id * in the context of Wi-SUN mode switching. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] newPhyModeId A targeted PhyMode ID. + * @param[in] railHandle A RAIL instance handle. + * @param[in] newPhyModeId A targeted PHY Mode Id. * @param[out] pChannel A pointer to the channel to switch to. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function will fail if: - * - the targeted PhyModeID is the same as the current PhyMode ID + * - the targeted PHY Mode Id is the same as the current PHY Mode Id * - called on a platform that lacks \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH * - called on a platform that doesn't have 802154G options enabled * by \ref RAIL_IEEE802154_ConfigGOptions(). * For newPhyModeId associated with a FSK FEC_off PHY, if dynamic FEC is * activated (see \ref RAIL_IEEE802154_G_OPTION_DYNFEC), the returned * channel can correspond to the associated FSK FEC_on PHY corresponding - * then to PhyModeID = newPhyModeId + 16 + * then to PHY Mode Id = newPhyModeId + 16 */ RAIL_Status_t RAIL_IEEE802154_ComputeChannelFromPhyModeId(RAIL_Handle_t railHandle, uint8_t newPhyModeId, @@ -1229,8 +1245,8 @@ RAIL_Status_t RAIL_IEEE802154_ComputeChannelFromPhyModeId(RAIL_Handle_t railHand /** * Manage forbidden channels during mode switch. * - * @param[in] currentBaseFreq The current frequency of the base channel. - * @param[in] newPhyModeId A targeted PhyMode ID. + * @param[in] currentBaseFreq The current frequency of the base channel. + * @param[in] newPhyModeId A targeted PHY Mode Id. * @param[in] configEntryNewPhyModeId A pointer to \ref RAIL_ChannelConfigEntry_t * structure corresponding to the new PHY configEntry. * @param[in,out] pChannel A pointer to the channel to switch to. If channel @@ -1238,9 +1254,9 @@ RAIL_Status_t RAIL_IEEE802154_ComputeChannelFromPhyModeId(RAIL_Handle_t railHand * function must update it with the closest valid channel. The highest * channel must be selected in case of two valid channels being equidistant * to a forbidden channel. - * @return A status code indicating success of the function call. It must - * return RAIL_STATUS_INVALID_PARAMETER for failure or RAIL_STATUS_NO_ERROR - * for success. + * @return Status code indicating success of the function call. It must + * return \ref RAIL_STATUS_INVALID_PARAMETER for failure or \ref + * RAIL_STATUS_NO_ERROR for success. * * This function must fail if no valid channel has been found. If so, RAIL will * abort the mode switch. @@ -1259,10 +1275,10 @@ RAIL_Status_t RAILCb_IEEE802154_IsModeSwitchNewChannelValid(uint32_t currentBase #define RAIL_IEEE802154_ACCEPT_BEACON_FRAMES (0x01) /// When receiving packets, accept 802.15.4 DATA frame types. #define RAIL_IEEE802154_ACCEPT_DATA_FRAMES (0x02) -/// When receiving packets, accept 802.15.4 ACK frame types. -/// @note Expected ACK frame types will still be accepted regardless -/// of this setting when waiting for an ACK after a transmit that -/// used \ref RAIL_TX_OPTION_WAIT_FOR_ACK and auto-ACK is enabled. +/// When receiving packets, accept 802.15.4 Ack frame types. +/// @note Expected Ack frame types will still be accepted regardless +/// of this setting when waiting for an Ack after a transmit that +/// used \ref RAIL_TX_OPTION_WAIT_FOR_ACK and auto-Ack is enabled. #define RAIL_IEEE802154_ACCEPT_ACK_FRAMES (0x04) /// When receiving packets, accept 802.15.4 COMMAND frame types. #define RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES (0x08) @@ -1271,8 +1287,8 @@ RAIL_Status_t RAILCb_IEEE802154_IsModeSwitchNewChannelValid(uint32_t currentBase #define RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES (0x20) /// In standard operation, accept BEACON, DATA and COMMAND frames. -/// Don't receive ACK frames unless waiting for ACK (i.e., only -/// receive expected ACKs). +/// Don't receive Ack frames unless waiting for Ack (i.e., only +/// receive expected Acks). #define RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES (RAIL_IEEE802154_ACCEPT_BEACON_FRAMES \ | RAIL_IEEE802154_ACCEPT_DATA_FRAMES \ | RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES) @@ -1280,25 +1296,25 @@ RAIL_Status_t RAILCb_IEEE802154_IsModeSwitchNewChannelValid(uint32_t currentBase /** * Set which 802.15.4 frame types to accept. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] framesMask A mask containing which 802.15.4 frame types to receive. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function will fail if 802.15.4 hardware acceleration is not currently * enabled by calling \ref RAIL_IEEE802154_Init() or framesMask requests an * unsupported frame type. * This setting may be changed at any time when 802.15.4 hardware - * acceleration is enabled. Only Beacon, Data, ACK, Command, and Multipurpose + * acceleration is enabled. Only Beacon, Data, Ack, Command, and Multipurpose * frames may be received. - * The RAIL_IEEE802154_ACCEPT_XXX_FRAMES defines may be combined to create a + * The RAIL_IEEE802154_ACCEPT_*_FRAMES defines may be combined to create a * bitmask to pass into this function. * * \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES behaves slightly different than the * other defines. If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is set, the radio - * will accept an ACK frame during normal packet reception, but only a - * truly expected ACK will have its \ref RAIL_RxPacketDetails_t::isAck true. - * If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is not set, ACK frames will be - * filtered unless they're expected when the radio is waiting for an ACK. + * will accept an Ack frame during normal packet reception, but only a + * truly expected Ack will have its \ref RAIL_RxPacketDetails_t::isAck true. + * If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is not set, Ack frames will be + * filtered unless they're expected when the radio is waiting for an Ack. */ RAIL_Status_t RAIL_IEEE802154_AcceptFrames(RAIL_Handle_t railHandle, uint8_t framesMask); @@ -1307,17 +1323,17 @@ RAIL_Status_t RAIL_IEEE802154_AcceptFrames(RAIL_Handle_t railHandle, * Enable early Frame Pending lookup event notification * (\ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND). * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] enable true to enable, false to disable. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Normally, \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND is triggered after - * receiving the entire MAC header and MAC command byte for an ACK-requesting + * receiving the entire MAC header and MAC command byte for an Ack-requesting * MAC command frame. Version 0/1 frames also require that command to be a * Data Request for this event to occur. * Enabling this feature causes this event to be triggered earlier to allow for - * more time to determine the type of ACK needed (Immediate or Enhanced) and/or - * perform frame pending lookup to influence the outgoing ACK by using \ref + * more time to determine the type of Ack needed (Immediate or Enhanced) and/or + * perform frame pending lookup to influence the outgoing Ack by using \ref * RAIL_IEEE802154_WriteEnhAck() or \ref RAIL_IEEE802154_ToggleFramePending(). * * For Frame Version 0/1 packets and for Frame Version 2 packets when \ref @@ -1328,10 +1344,10 @@ RAIL_Status_t RAIL_IEEE802154_AcceptFrames(RAIL_Handle_t railHandle, * is in use, "early" means right after receiving any Auxiliary Security * header which follows the source address information in the MAC header. * - * This feature is useful when the protocol knows an ACK-requesting MAC + * This feature is useful when the protocol knows an Ack-requesting MAC * Command must be a data poll without needing to receive the MAC Command * byte, giving it a bit more time to adjust Frame Pending or generate an - * Enhanced ACK. + * Enhanced Ack. * * This function will fail if 802.15.4 hardware acceleration is not * currently enabled by calling \ref RAIL_IEEE802154_Init(), @@ -1346,18 +1362,18 @@ RAIL_Status_t RAIL_IEEE802154_EnableEarlyFramePending(RAIL_Handle_t railHandle, * Enable Frame Pending lookup event notification * (\ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND) for MAC Data frames. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] enable true to enable, false to disable. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Normally \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND is triggered only - * for ACK-requesting MAC command frames. + * for Ack-requesting MAC command frames. * Enabling this feature causes this event to also be triggered for MAC data * frames, at the same point in the packet as \ref * RAIL_IEEE802154_EnableEarlyFramePending() would trigger. * This feature is necessary to support the Thread Basil-Hayden Enhanced * Frame Pending feature in Version 0/1 frames, and to support Version 2 - * Data frames which require an Enhanced ACK. + * Data frames which require an Enhanced Ack. * * This function will fail if 802.15.4 hardware acceleration is not * currently enabled by calling \ref RAIL_IEEE802154_Init(). @@ -1371,41 +1387,28 @@ RAIL_Status_t RAIL_IEEE802154_EnableDataFramePending(RAIL_Handle_t railHandle, * Alternate naming for function \ref RAIL_IEEE802154_SetFramePending * to depict it is used for changing the default setting specified by * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks in - * an outgoing ACK. + * an outgoing Ack. */ #define RAIL_IEEE802154_ToggleFramePending RAIL_IEEE802154_SetFramePending /** - * Change the Frame Pending bit on the outgoing legacy Immediate ACK from + * Change the Frame Pending bit on the outgoing legacy Immediate Ack from * the default specified by * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks. + * * @param[in] railHandle A handle of RAIL instance - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function must only be called while processing the \ref - * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND if the ACK + * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND if the Ack * for this packet should go out with its Frame Pending bit set differently * than what was specified by * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks. * - * It's intended only for use with 802.15.4 legacy immediate ACKs and - * not 802.15.4E enhanced ACKs. + * It's intended only for use with 802.15.4 legacy immediate Acks and + * not 802.15.4E enhanced Acks. * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to - * modify the outgoing Immediate ACK. - - * @note This function is used to set the Frame Pending bit but its meaning - * depends on the value of - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * while transmitting ACK. - * If \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is not set, then Frame Pending bit is set in outgoing ACK. - * Whereas, if \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is set, then Frame Pending bit is cleared in outgoing ACK. - * Therefore, this function is to be called if the frame is pending when - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is not set or if there is no frame pending when - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is set. + * modify the outgoing Immediate Ack. */ RAIL_Status_t RAIL_IEEE802154_SetFramePending(RAIL_Handle_t railHandle); @@ -1415,43 +1418,43 @@ RAIL_Status_t RAIL_IEEE802154_SetFramePending(RAIL_Handle_t railHandle); * @param[in] railHandle A RAIL instance handle. * @param[out] pAddress A pointer to \ref RAIL_IEEE802154_Address_t structure * to populate with source address information. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * This function must only be called when handling the \ref * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. This will return * \ref RAIL_STATUS_INVALID_STATE if the address information is stale - * (i.e., it is too late to affect the outgoing ACK). + * (i.e., it is too late to affect the outgoing Ack). */ RAIL_Status_t RAIL_IEEE802154_GetAddress(RAIL_Handle_t railHandle, RAIL_IEEE802154_Address_t *pAddress); /** - * Write the AutoACK FIFO for the next outgoing 802.15.4E Enhanced ACK. + * Write the Auto-Ack FIFO for the next outgoing 802.15.4E Enhanced Ack. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] ackData Pointer to ACK data to transmit + * @param[in] railHandle A RAIL instance handle. + * @param[in] ackData A pointer to Ack data to transmit * This may be NULL, in which case it's assumed the data has already - * been emplaced into the ACK buffer and RAIL just needs to be told + * been emplaced into the Ack buffer and RAIL just needs to be told * how many bytes are there. Use \ref RAIL_GetAutoAckFifo() to get - * the address of RAIL's AutoACK buffer in RAM and its size. - * @param[in] ackDataLen Length of ACK data, in bytes. + * the address of RAIL's Auto-Ack buffer in RAM and its size. + * @param[in] ackDataLen Length of Ack data, in bytes. * If this exceeds \ref RAIL_AUTOACK_MAX_LENGTH the function * will return \ref RAIL_STATUS_INVALID_PARAMETER. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * - * This function sets the AutoACK data to use in acknowledging the frame + * This function sets the Auto-Ack data to use in acknowledging the frame * being received. It must only be called while processing the \ref * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND, and is intended for use * when packet information from \ref RAIL_GetRxIncomingPacketInfo() - * indicates an 802.15.4E Enhanced ACK must be sent instead of a legacy - * Immediate ACK. \ref RAIL_IEEE802154_ToggleFramePending() should not be - * called for an Enhanced ACK; instead the Enhanced ACK's Frame Control + * indicates an 802.15.4E Enhanced Ack must be sent instead of a legacy + * Immediate Ack. \ref RAIL_IEEE802154_ToggleFramePending() should not be + * called for an Enhanced Ack; instead the Enhanced Ack's Frame Control * Field should have the Frame Pending bit set appropriately in its ackData. * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to - * write the outgoing ACK -- a situation that will likely trigger + * write the outgoing Ack -- a situation that will likely trigger * a \ref RAIL_EVENT_TXACK_UNDERFLOW event. When successful, the Enhanced * ackData will only be sent once. Subsequent packets needing an Enhanced - * ACK will each need to call this function to write their ACK information. + * Ack will each need to call this function to write their Ack information. */ RAIL_Status_t RAIL_IEEE802154_WriteEnhAck(RAIL_Handle_t railHandle, const uint8_t *ackData, @@ -1459,23 +1462,23 @@ RAIL_Status_t RAIL_IEEE802154_WriteEnhAck(RAIL_Handle_t railHandle, /** * Set a separate RX packet to TX state transition turnaround time for - * sending an Enhanced ACK. + * sending an Enhanced Ack. * * @param[in] railHandle A RAIL instance handle. - * @param[in,out] pRxToEnhAckTx Pointer to the turnaround transition requested - * for Enhanced ACKs. It will be updated with the actual time set. - * Requesting a time of 0 will sync the Enhanced ACK turnaround time with - * that used for immediate ACKs (and output 0). Requesting a time of \ref - * RAIL_TRANSITION_TIME_KEEP will output the current Enhanced ACK timing - * parameter (0 if it is the same as that used for Immediate ACKs). + * @param[in,out] pRxToEnhAckTx A pointer to the turnaround transition requested + * for Enhanced Acks. It will be updated with the actual time set. + * Requesting a time of 0 will sync the Enhanced Ack turnaround time with + * that used for immediate Acks (and output 0). Requesting a time of \ref + * RAIL_TRANSITION_TIME_KEEP will output the current Enhanced Ack timing + * parameter (0 if it is the same as that used for Immediate Acks). * @return Status code indicating a success of the function call. * An error will not update the pRxToEnhAckTx output parameter. * - * Normally Immediate and Enhanced ACKs are both sent using the + * Normally Immediate and Enhanced Acks are both sent using the * \ref RAIL_IEEE802154_Config_t::timings rxToTx turnaround time. - * If the stack needs more time to prepare an Enhanced ACK, it can + * If the stack needs more time to prepare an Enhanced Ack, it can * call this function after \ref RAIL_IEEE802154_Init() to set a - * longer turnaround time used just for Enhanced ACK transmits. + * longer turnaround time used just for Enhanced Ack transmits. * * This function will fail on platforms that lack * \ref RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. @@ -1519,7 +1522,7 @@ uint8_t RAIL_IEEE802154_ConvertRssiToEd(int8_t rssiDbm); RAIL_ENUM(RAIL_IEEE802154_CcaMode_t) { /** * RSSI-based CCA. CCA reports a busy medium upon detecting any energy - * above \ref RAIL_CsmaConfig_t.ccaThreshold. + * above \ref RAIL_CsmaConfig_t::ccaThreshold. */ RAIL_IEEE802154_CCA_MODE_RSSI = 0, /** @@ -1547,19 +1550,19 @@ RAIL_ENUM(RAIL_IEEE802154_CcaMode_t) { */ RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT, /** - * Number of CCA modes. + * Number of CCA modes. Must be last. */ RAIL_IEEE802154_CCA_MODE_COUNT }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IEEE802154_CCA_MODE_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_RSSI) -#define RAIL_IEEE802154_CCA_MODE_SIGNAL ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL) -#define RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI) -#define RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI) -#define RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT) -#define RAIL_IEEE802154_CCA_MODE_COUNT ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_COUNT) +#define RAIL_IEEE802154_CCA_MODE_RSSI ((RAIL_IEEE802154_CcaMode_t) RAIL_IEEE802154_CCA_MODE_RSSI) +#define RAIL_IEEE802154_CCA_MODE_SIGNAL ((RAIL_IEEE802154_CcaMode_t) RAIL_IEEE802154_CCA_MODE_SIGNAL) +#define RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI ((RAIL_IEEE802154_CcaMode_t) RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI) +#define RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI ((RAIL_IEEE802154_CcaMode_t) RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI) +#define RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT ((RAIL_IEEE802154_CcaMode_t) RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT) +#define RAIL_IEEE802154_CCA_MODE_COUNT ((RAIL_IEEE802154_CcaMode_t) RAIL_IEEE802154_CCA_MODE_COUNT) #endif /** @@ -1567,16 +1570,16 @@ RAIL_ENUM(RAIL_IEEE802154_CcaMode_t) { * @brief Available Signal identifier modes. */ RAIL_ENUM(RAIL_IEEE802154_SignalIdentifierMode_t) { - /* Disable signal detection mode. */ + /** Disable signal detection mode. */ RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE = 0, - /* 2.4Ghz 802.15.4 signal detection mode. */ + /** 2.4 GHz 802.15.4 signal detection mode. */ RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154 }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_IEEE802154_SignalIdentifierMode_t)RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE) -#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154 ((RAIL_IEEE802154_SignalIdentifierMode_t)RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154) +#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_IEEE802154_SignalIdentifierMode_t) RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE) +#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154 ((RAIL_IEEE802154_SignalIdentifierMode_t) RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154) #endif /** @@ -1585,8 +1588,8 @@ RAIL_ENUM(RAIL_IEEE802154_SignalIdentifierMode_t) { * @param[in] railHandle A RAIL instance handle. * @param[in] signalIdentifierMode Mode of signal identifier operation. * - * This features allows detection of 2.4Ghz 802.15.4 signal on air. This - * function must be called once before \ref RAIL_IEEE802154_EnableSignalDetection + * This features allows detection of 2.4 GHz 802.15.4 signal on air. This + * function must be called once before \ref RAIL_IEEE802154_EnableSignalDetection() * to configure and enable signal identifier. * * To enable event for signal detection \ref RAIL_ConfigEvents() must be called @@ -1607,11 +1610,11 @@ RAIL_Status_t RAIL_IEEE802154_ConfigSignalIdentifier(RAIL_Handle_t railHandle, * @param[in] railHandle A RAIL instance handle. * @param[in] enable Signal detection is enabled if true, disabled if false. * - * \ref RAIL_IEEE802154_ConfigSignalIdentifier must be called once before calling + * \ref RAIL_IEEE802154_ConfigSignalIdentifier() must be called once before calling * this function to configure and enable signal identifier. * Once a signal is detected signal detection will be turned off and this * function should be called to re-enable the signal detection without needing - * to call \ref RAIL_IEEE802154_ConfigSignalIdentifier if the signal identifier + * to call \ref RAIL_IEEE802154_ConfigSignalIdentifier() if the signal identifier * is already configured and enabled. * * This function is only supported by chips where @@ -1638,10 +1641,10 @@ RAIL_Status_t RAIL_IEEE802154_EnableSignalDetection(RAIL_Handle_t railHandle, * This function sets the CCA mode \ref RAIL_IEEE802154_CcaMode_t. * If not called, RAIL_IEEE802154_CCA_MODE_RSSI (RSSI-based CCA) is used for CCA. * - * In RAIL_IEEE802154_CCA_MODE_SIGNAL, RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI and - * RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI signal identifier is enabled + * In \ref RAIL_IEEE802154_CCA_MODE_SIGNAL, \ref RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI and + * \ref RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI the signal identifier is enabled * for the duration of LBT. If previously enabled by - * \ref RAIL_IEEE802154_ConfigSignalIdentifier, the signal identifier will remain + * \ref RAIL_IEEE802154_ConfigSignalIdentifier(), the signal identifier will remain * active until triggered. * * This function is only supported by chips where @@ -1658,9 +1661,9 @@ RAIL_Status_t RAIL_IEEE802154_ConfigCcaMode(RAIL_Handle_t railHandle, /** * Allow certain malformed MAC Header frames to be received. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] enable true to enable, false to disable. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * When allowed, certain MAC header formats that 802.15.4 deems * illegal will be received rather than filtered. This is to @@ -1683,19 +1686,19 @@ RAIL_Status_t RAIL_IEEE802154_AllowMalformed(RAIL_Handle_t railHandle, * structure. Use NULL to disable any switching previously set up. * @return Status code indicating success of the function call. * - * This function configures RX channel switching, allowing reception of 2.4Ghz + * This function configures RX channel switching, allowing reception of 2.4 GHz * 802.15.4 signals on two different radio channels within the same PHY. * (If the two channels are same, the function behaves the same as if * pConfig was NULL.) * This function should be - * called once before \ref RAIL_StartRx and/or enabling + * called once before \ref RAIL_StartRx() and/or enabling * \ref RAIL_RX_OPTION_CHANNEL_SWITCHING. * * When \ref RAIL_RX_OPTION_CHANNEL_SWITCHING is enabled, * channel switching will occur during normal listening but is suspended * (and the radio is idled) when starting any kind of transmit, including * scheduled or CSMA transmits. It remains suspended after a \ref - * RAIL_TX_OPTION_WAIT_FOR_ACK transmit until the ACK is received or + * RAIL_TX_OPTION_WAIT_FOR_ACK transmit until the Ack is received or * times out. * * When \ref RAIL_RX_OPTION_CHANNEL_SWITCHING is disabled after switching @@ -1703,10 +1706,11 @@ RAIL_Status_t RAIL_IEEE802154_AllowMalformed(RAIL_Handle_t railHandle, * so the application should call \ref RAIL_StartRx() to put it on the * desired non-switching channel. * - * @note IEEE 802.15.4 must be enabled via \ref RAIL_IEEE802154_Init, and the + * @note IEEE 802.15.4 must be enabled via \ref RAIL_IEEE802154_Init(), and the * radio must be in the idle state when configuring RX channel switching. - * A DMA channel must be allocated with \ref RAIL_UseDma; otherwise this API - * will return \ref RAIL_STATUS_INVALID_CALL. + * A DMA channel must be allocated with \ref RAIL_UseDma() or by incorporating + * the \ref rail_util_dma plugin; otherwise this API will return + * \ref RAIL_STATUS_INVALID_CALL. * This feature also requires a PRS channel, internally allocated by the RAIL * library, to use and hold onto for future use. If no PRS channel is * available, the function returns \ref RAIL_STATUS_INVALID_PARAMETER. @@ -1714,11 +1718,15 @@ RAIL_Status_t RAIL_IEEE802154_AllowMalformed(RAIL_Handle_t railHandle, * @note When RX channel switching is active, receive sensitivity and performance * are slightly impacted. * - * @note This function internally uses \ref RAIL_EnableCacheSynthCal to + * @note This function internally uses \ref RAIL_EnableCacheSynthCal() to * enable/disable the sequencer cache to store the synth calibration value. * * @note Switching is cancelled on any PHY change, so this function would * need to be re-called to reestablish switching after such a change. + * + * @warning As this function relies on LDMA access and RAIL is meant to run in + * TrustZone non-secure world, it is not supported if LDMA is configured as + * secure peripheral and it will return \ref RAIL_STATUS_INVALID_CALL. */ RAIL_Status_t RAIL_IEEE802154_ConfigRxChannelSwitching(RAIL_Handle_t railHandle, const RAIL_IEEE802154_RxChannelSwitchingCfg_t *pConfig); @@ -1733,8 +1741,8 @@ RAIL_Status_t RAIL_IEEE802154_ConfigRxChannelSwitching(RAIL_Handle_t railHandle, * Calibrate image rejection for IEEE 802.15.4 2.4 GHz. * * @param[in] railHandle A RAIL instance handle. - * @param[out] imageRejection The result of the image rejection calibration. - * @return A status code indicating success of the function call. + * @param[out] imageRejection A pointer to the result of the image rejection calibration. + * @return Status code indicating success of the function call. * * Some chips have protocol-specific image rejection calibrations programmed * into their flash. This function will either get the value from flash and @@ -1748,7 +1756,7 @@ RAIL_Status_t RAIL_IEEE802154_CalibrateIr2p4Ghz(RAIL_Handle_t railHandle, * * @param[in] railHandle A RAIL instance handle. * @param[out] imageRejection The result of the image rejection calibration. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * * Some chips have protocol-specific image rejection calibrations programmed * into their flash. This function will either get the value from flash and diff --git a/simplicity_sdk/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h b/simplicity_sdk/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h index 69967c753..125d08e19 100644 --- a/simplicity_sdk/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h +++ b/simplicity_sdk/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h @@ -62,12 +62,12 @@ extern "C" { extern const RAIL_ChannelConfig_t *const RAIL_Sidewalk_Phy2GFSK50kbps; /** - * Switch to the 2GFSK 50kbps Sidewalk PHY. + * Switch to the 2GFSK 50 kbps Sidewalk PHY. * * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. * - * Use this function to switch to the 2GFSK 50kbps Sidewalk PHY. + * Use this function to switch to the 2GFSK 50 kbps Sidewalk PHY. * * @note The Sidewalk PHY is supported only on some parts. * The preprocessor symbol \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK and the diff --git a/simplicity_sdk/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h b/simplicity_sdk/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h index 241a74a56..d89c9fde4 100644 --- a/simplicity_sdk/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h +++ b/simplicity_sdk/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h @@ -47,11 +47,11 @@ extern "C" { * @brief The RX variant of the WMBUS T+C PHY. */ RAIL_ENUM(RAIL_WMBUS_Phy_t) { - /** subPhyId indicating a mode T frame A packet */ + /** \ref RAIL_RxPacketDetails_t::subPhyId indicating a mode T frame A packet */ RAIL_WMBUS_ModeTFrameA = 0U, - /** subPhyId indicating a mode C frame A packet */ + /** \ref RAIL_RxPacketDetails_t::subPhyId indicating a mode C frame A packet */ RAIL_WMBUS_ModeCFrameA = 2U, - /** subPhyId indicating a mode C frame B packet */ + /** \ref RAIL_RxPacketDetails_t::subPhyId indicating a mode C frame B packet */ RAIL_WMBUS_ModeCFrameB = 3U, }; diff --git a/simplicity_sdk/platform/radio/rail_lib/protocol/zwave/rail_zwave.h b/simplicity_sdk/platform/radio/rail_lib/protocol/zwave/rail_zwave.h index c79da9c71..7e26e4fe3 100644 --- a/simplicity_sdk/platform/radio/rail_lib/protocol/zwave/rail_zwave.h +++ b/simplicity_sdk/platform/radio/rail_lib/protocol/zwave/rail_zwave.h @@ -45,7 +45,7 @@ extern "C" { /// acceleration features. /// /// To configure Z-Wave functionality, the application must first set up -/// a RAIL instance with RAIL_Init() and other setup functions. +/// a RAIL instance with \ref RAIL_Init() and other setup functions. /// @code{.c} /// RAIL_ZWAVE_NodeId_t gRecentBeamNodeId; /// uint8_t gRecentBeamChannelIndex; @@ -53,7 +53,7 @@ extern "C" { /// // Main RAIL_EVENT callback /// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) /// { -/// // Get beamNodeId and channel index from beam packet +/// // Get beam Node Id and channel index from beam packet /// if (events & RAIL_EVENT_ZWAVE_BEAM) { /// if (RAIL_ZWAVE_IsEnabled(railHandle)) { /// if ((RAIL_ZWAVE_GetBeamNodeId(railHandle, &gRecentBeamNodeId) @@ -95,20 +95,16 @@ extern "C" { * @brief Z-Wave options. */ RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { - // Z-Wave Option Bit Shifts - - /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE bit */ + /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE bit. */ RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT = 0, - /** Shift position of \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES bit */ - RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT, - /** Shift position of \ref RAIL_ZWAVE_OPTION_NODE_ID_FILTERING bit */ - RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT, - /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE bit */ - RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT, + /** Shift position of \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES bit. */ + RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT = 1, + /** Shift position of \ref RAIL_ZWAVE_OPTION_NODE_ID_FILTERING bit. */ + RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT = 2, + /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE bit. */ + RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT = 3, }; -// RAIL_ZWAVE_Options_t bitmasks - /** A value representing no options */ #define RAIL_ZWAVE_OPTIONS_NONE 0U @@ -117,14 +113,14 @@ RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { /** * An option to configure promiscuous mode, accepting non-beam packets - * regardless of their HomeId. By default packets are filtered by their HomeId. + * regardless of their Home Id. By default packets are filtered by their Home Id. * When true, such filtering is disabled. */ #define RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE \ (1u << RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT) /** - * An option to filter non-beam packets based on their NodeId when + * An option to filter non-beam packets based on their Node Id when * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE is disabled. * * @note This option has no effect when @@ -137,10 +133,10 @@ RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { * An option to configure beam frame recognition. By default beams are not * considered special and will be received as if they were normal Z-Wave * frames, assuredly triggering \ref RAIL_EVENT_RX_FRAME_ERROR. - * When true, beam frames that are broadcast or match the NodeId and - * HomeIdHash values will trigger \ref RAIL_EVENT_ZWAVE_BEAM event. + * When true, beam frames that are broadcast or match the Node Id and + * Home Id hash values will trigger \ref RAIL_EVENT_ZWAVE_BEAM event. * (All beams additionally trigger \ref RAIL_EVENT_RX_PACKET_ABORTED - * regardless of NodeId / HomeIdHash values.) + * regardless of Node Id / Home Id hash values.) * * @note This option takes precedence over \ref * RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE when receiving a beam frame. @@ -153,7 +149,7 @@ RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { /** * An option to receive all beams promiscuously when \ref * RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is enabled. - * When true, beam frames are received regardless of their NodeId or HomeIdHash + * When true, beam frames are received regardless of their Node Id or Home Id hash * resulting in \ref RAIL_EVENT_ZWAVE_BEAM (and also \ref * RAIL_EVENT_RX_PACKET_ABORTED) for each beam frame. * @@ -168,7 +164,7 @@ RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { /** * @enum RAIL_ZWAVE_NodeId_t - * @brief A Z-Wave Node ID. + * @brief A Z-Wave Node Id. * * This data type is 12 bits wide when using the ZWave Long Range PHY, and * 8 bits wide otherwise. @@ -177,29 +173,31 @@ RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { * Otherwise, values 0xE9..0xFE are reserved. */ RAIL_ENUM_GENERIC(RAIL_ZWAVE_NodeId_t, uint16_t) { - /** The unknown NodeId for uninitialized nodes. */ + /** The unknown Node Id for uninitialized nodes. */ RAIL_ZWAVE_NODE_ID_NONE = 0x00U, - /** The broadcast NodeId. */ + /** The broadcast Node Id. */ RAIL_ZWAVE_NODE_ID_BROADCAST = 0xFFU, - /** Default to the broadcast NodeId. */ + /** Default to the broadcast Node Id. */ RAIL_ZWAVE_NODE_ID_DEFAULT = RAIL_ZWAVE_NODE_ID_BROADCAST, - // All other values between 0x00 and 0xFE are valid node IDs normally - /** The Long Range broadcast NodeId. */ + // All other values between 0x00 and 0xFE are valid Node Ids normally + /** The Long Range broadcast Node Id. */ RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE = 0xFFFU, - /** Default to the Long Range broadcast NodeId. */ + /** Default to the Long Range broadcast Node Id. */ RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE = RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE, - // All values from 0x001 to 0xFA1 are valid node IDs with a Long Range PHY. + // All values from 0x001 to 0xFA1 are valid Node Ids with a Long Range PHY. }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ZWAVE_NODE_ID_NONE ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_NONE) -#define RAIL_ZWAVE_NODE_ID_BROADCAST ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_BROADCAST) -#define RAIL_ZWAVE_NODE_ID_DEFAULT ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_DEFAULT) +#define RAIL_ZWAVE_NODE_ID_NONE ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_NONE) +#define RAIL_ZWAVE_NODE_ID_BROADCAST ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_BROADCAST) +#define RAIL_ZWAVE_NODE_ID_DEFAULT ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_DEFAULT) +#define RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE) +#define RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE) #endif //DOXYGEN_SHOULD_SKIP_THIS #ifndef DOXYGEN_SHOULD_SKIP_THIS -/** Defines for subPhyID field in RAIL_RxPacketDetails_t */ +/** Defines for \ref RAIL_RxPacketDetails_t::subPhyId field. */ #define RAIL_ZWAVE_RX_SUBPHY_ID_0 (0U) #define RAIL_ZWAVE_RX_SUBPHY_ID_1 (1U) #define RAIL_ZWAVE_RX_SUBPHY_ID_2 (2U) @@ -208,13 +206,15 @@ RAIL_ENUM_GENERIC(RAIL_ZWAVE_NodeId_t, uint16_t) { /** * @enum RAIL_ZWAVE_HomeId_t - * @brief A Z-Wave Home ID. + * @brief A Z-Wave Home Id. * - * @note Home IDs in the range 0x54000000..0x55FFFFFF are illegal. + * @note Home Ids in the range 0x54000000..0x55FFFFFF are illegal. */ RAIL_ENUM_GENERIC(RAIL_ZWAVE_HomeId_t, uint32_t) { - RAIL_ZWAVE_HOME_ID_UNKNOWN = 0x00000000U, /**< The unknown HomeId. */ - RAIL_ZWAVE_HOME_ID_DEFAULT = 0x54545454U, /**< An impossible and unlikely HomeId. */ + /** The unknown Home Id. */ + RAIL_ZWAVE_HOME_ID_UNKNOWN = 0x00000000U, + /** An impossible and unlikely Home Id. */ + RAIL_ZWAVE_HOME_ID_DEFAULT = 0x54545454U, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -225,20 +225,24 @@ RAIL_ENUM_GENERIC(RAIL_ZWAVE_HomeId_t, uint32_t) { /** * @enum RAIL_ZWAVE_HomeIdHash_t - * @brief A Z-Wave Home ID hash. + * @brief A Z-Wave Home Id hash. * * @note Certain values (as shown) are illegal. */ RAIL_ENUM(RAIL_ZWAVE_HomeIdHash_t) { - RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 = 0x0AU, /**< An illegal HomeIdHash value. */ - RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 = 0x4AU, /**< An illegal HomeIdHash value. */ - RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 = 0x55U, /**< An illegal HomeIdHash value. */ - RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE = 0x55U, /**< Illegal HomeIdHash value that - suppresses checking the - HomeIdHash field of beam - packets. */ - RAIL_ZWAVE_HOME_ID_HASH_DEFAULT - = RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, /**< Default to don't care. */ + /** An illegal Home Id hash value. */ + RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 = 0x0AU, + /** An illegal Home Id hash value. */ + RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 = 0x4AU, + /** An illegal Home Id hash value. */ + RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 = 0x55U, + /** + * Illegal Home Id hash value that suppresses checking the + * Home Id hash field of beam packets. + */ + RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE = 0x55U, + /** Default to don't care. */ + RAIL_ZWAVE_HOME_ID_HASH_DEFAULT = RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, }; #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -260,7 +264,7 @@ typedef struct RAIL_ZWAVE_Config { */ RAIL_ZWAVE_Options_t options; /** - * Defines Z-Wave ACKing configuration. + * Defines Z-Wave Acking configuration. */ RAIL_AutoAckConfig_t ackConfig; /** @@ -271,27 +275,42 @@ typedef struct RAIL_ZWAVE_Config { /** * @enum RAIL_ZWAVE_Baud_t - * @brief Z-Wave supported baudrates or PHYs. + * @brief Z-Wave supported baud rates or PHYs. */ RAIL_ENUM(RAIL_ZWAVE_Baud_t) { - RAIL_ZWAVE_BAUD_9600, /**< 9.6kbps baudrate*/ - RAIL_ZWAVE_BAUD_40K, /**< 40kbps baudrate*/ - RAIL_ZWAVE_BAUD_100K, /**< 100kbps baudrate*/ - RAIL_ZWAVE_LR, /**< Long Range PHY*/ - RAIL_ZWAVE_ENERGY_DETECT = RAIL_ZWAVE_LR, /**< Energy detection PHY*/ - RAIL_ZWAVE_BAUD_INVALID /**< Sentinel value for invalid baud rate*/ + /** 9.6 kbps baud rate. */ + RAIL_ZWAVE_BAUD_9600, + /** 40 kbps baud rate. */ + RAIL_ZWAVE_BAUD_40K, + /** 100 kbps baud rate. */ + RAIL_ZWAVE_BAUD_100K, + /** Long Range PHY. */ + RAIL_ZWAVE_LR, + /** Energy detection PHY. */ + RAIL_ZWAVE_ENERGY_DETECT = RAIL_ZWAVE_LR, + /** Sentinel value for invalid baud rate. Must be last. */ + RAIL_ZWAVE_BAUD_INVALID }; +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ZWAVE_BAUD_9600 ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_9600) +#define RAIL_ZWAVE_BAUD_40K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_40K) +#define RAIL_ZWAVE_BAUD_100K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_100K) +#define RAIL_ZWAVE_LR ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_LR) +#define RAIL_ZWAVE_ENERGY_DETECT ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_ENERGY_DETECT) +#define RAIL_ZWAVE_INVALID ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_INVALID) +#endif //DOXYGEN_SHOULD_SKIP_THIS + #ifndef DOXYGEN_SHOULD_SKIP_THIS /** * @enum RAIL_ZWAVE_RegionOptions_t * @brief Region Specific Physical */ -RAIL_ENUM(RAIL_ZWAVE_RegionOptions_t) -{ - /** Bit shift for US Long Range End Devices */ - RAIL_ZWAVE_REGION_LONG_RANGE_END_SHIFT = 0, +RAIL_ENUM(RAIL_ZWAVE_RegionOptions_t) { + /** Bit shift for US Long Range 3 */ + RAIL_ZWAVE_REGION_LONG_RANGE_3_SHIFT = 0, /** Bit shift for special low side config, mostly for Japan and Korea */ RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT = 1, /** Bit shift for US long range range configurations */ @@ -305,8 +324,10 @@ RAIL_ENUM(RAIL_ZWAVE_RegionOptions_t) #define RAIL_ZWAVE_REGION_LONG_RANGE_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_SHIFT) /** A value representing lowside configurations: JP and KR */ #define RAIL_ZWAVE_REGION_LOW_SIDE_MASK (1u << RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT) -/** A value representing Long Range End Device region */ -#define RAIL_ZWAVE_REGION_LONG_RANGE_END_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_END_SHIFT) +/** A value representing Long Range 3 (end device) region */ +#define RAIL_ZWAVE_REGION_LONG_RANGE_3_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_3_SHIFT) +/** @deprecated Backwards compatible name. */ +#define RAIL_ZWAVE_REGION_LONG_RANGE_END_MASK RAIL_ZWAVE_REGION_LONG_RANGE_3_MASK /** A value representing No bit to be enabled */ #define RAIL_ZWAVE_REGION_SPECIFIC_NONE 0u #endif // DOXYGEN SHOULD SKIP THIS @@ -317,67 +338,82 @@ RAIL_ENUM(RAIL_ZWAVE_RegionOptions_t) */ #define RAIL_ZWAVE_FREQ_INVALID 0xFFFFFFFFUL -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ZWAVE_BAUD_9600 ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_9600) -#define RAIL_ZWAVE_BAUD_40K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_40K) -#define RAIL_ZWAVE_BAUD_100K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_100K) -#define RAIL_ZWAVE_LR ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_LR) -#define RAIL_ZWAVE_ENERGY_DETECT ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_ENERGY_DETECT) -#define RAIL_ZWAVE_INVALID ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_INVALID) -#endif //DOXYGEN_SHOULD_SKIP_THIS - /** * @enum RAIL_ZWAVE_RegionId_t * @brief Z-Wave region identifications. */ RAIL_ENUM(RAIL_ZWAVE_RegionId_t) { - RAIL_ZWAVE_REGIONID_UNKNOWN, /**< Unknown/Invalid*/ - RAIL_ZWAVE_REGIONID_EU, /**< European Union*/ - RAIL_ZWAVE_REGIONID_US, /**< United States*/ - RAIL_ZWAVE_REGIONID_ANZ, /**< Australia/New Zealand*/ - RAIL_ZWAVE_REGIONID_HK, /**< Hong Kong*/ - RAIL_ZWAVE_REGIONID_MY, /**< Malaysia*/ - RAIL_ZWAVE_REGIONID_IN, /**< India*/ - RAIL_ZWAVE_REGIONID_JP, /**< Japan*/ - RAIL_ZWAVE_REGIONID_RU, /**< Russian Federation*/ - RAIL_ZWAVE_REGIONID_IL, /**< Israel*/ - RAIL_ZWAVE_REGIONID_KR, /**< Korea*/ - RAIL_ZWAVE_REGIONID_CN, /**< China*/ - RAIL_ZWAVE_REGIONID_US_LR1, /**< United States, with first long range PHY*/ - RAIL_ZWAVE_REGIONID_US_LR2, /**< United States, with second long range PHY*/ - RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE, /**< United States long range end device PHY for both LR frequencies*/ - RAIL_ZWAVE_REGIONID_EU_LR1, /**< European Union, with first long range PHY*/ - RAIL_ZWAVE_REGIONID_EU_LR2, /**< European Union, with second long range PHY*/ - RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE, /**< European Union long range end device PHY for both LR frequencies*/ - RAIL_ZWAVE_REGIONID_COUNT /**< Count of known regions, must be last*/ + /** Unknown/Invalid. */ + RAIL_ZWAVE_REGIONID_UNKNOWN = 0, + /** European Union. */ + RAIL_ZWAVE_REGIONID_EU = 1, + /** United States. */ + RAIL_ZWAVE_REGIONID_US = 2, + /** Australia/New Zealand. */ + RAIL_ZWAVE_REGIONID_ANZ = 3, + /** Hong Kong. */ + RAIL_ZWAVE_REGIONID_HK = 4, + /** Malaysia. */ + RAIL_ZWAVE_REGIONID_MY = 5, + /** India. */ + RAIL_ZWAVE_REGIONID_IN = 6, + /** Japan. */ + RAIL_ZWAVE_REGIONID_JP = 7, + /** Russian Federation. */ + RAIL_ZWAVE_REGIONID_RU = 8, + /** Israel. */ + RAIL_ZWAVE_REGIONID_IL = 9, + /** Korea. */ + RAIL_ZWAVE_REGIONID_KR = 10, + /** China. */ + RAIL_ZWAVE_REGIONID_CN = 11, + /** United States, with first long range PHY. */ + RAIL_ZWAVE_REGIONID_US_LR1 = 12, + /** United States, with second long range PHY. */ + RAIL_ZWAVE_REGIONID_US_LR2 = 13, + /** United States, with third long range PHY. */ + RAIL_ZWAVE_REGIONID_US_LR3 = 14, + /** @deprecated Backwards compatible name. */ + RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE = RAIL_ZWAVE_REGIONID_US_LR3, + /** European Union, with first long range PHY. */ + RAIL_ZWAVE_REGIONID_EU_LR1 = 15, + /** European Union, with second long range PHY. */ + RAIL_ZWAVE_REGIONID_EU_LR2 = 16, + /** European Union, with third long range PHY. */ + RAIL_ZWAVE_REGIONID_EU_LR3 = 17, + /** @deprecated Backwards compatible name. */ + RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE = RAIL_ZWAVE_REGIONID_EU_LR3, + /** Count of known regions. Must be last. */ + RAIL_ZWAVE_REGIONID_COUNT }; #ifndef DOXYGEN_SHOULD_SKIP_THIS // Self-referencing defines minimize compiler complaints when using RAIL_ENUM #define RAIL_ZWAVE_REGIONID_UNKNOWN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_UNKNOWN) -#define RAIL_ZWAVE_REGIONID_EU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU) -#define RAIL_ZWAVE_REGIONID_US ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US) -#define RAIL_ZWAVE_REGIONID_ANZ ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_ANZ) -#define RAIL_ZWAVE_REGIONID_HK ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_HK) -#define RAIL_ZWAVE_REGIONID_MY ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_MY) -#define RAIL_ZWAVE_REGIONID_IN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IN) -#define RAIL_ZWAVE_REGIONID_JP ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_JP) -#define RAIL_ZWAVE_REGIONID_RU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_RU) -#define RAIL_ZWAVE_REGIONID_IL ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IL) -#define RAIL_ZWAVE_REGIONID_KR ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_KR) -#define RAIL_ZWAVE_REGIONID_CN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_CN) -#define RAIL_ZWAVE_REGIONID_US_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR1) -#define RAIL_ZWAVE_REGIONID_US_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR2) +#define RAIL_ZWAVE_REGIONID_EU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU) +#define RAIL_ZWAVE_REGIONID_US ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US) +#define RAIL_ZWAVE_REGIONID_ANZ ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_ANZ) +#define RAIL_ZWAVE_REGIONID_HK ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_HK) +#define RAIL_ZWAVE_REGIONID_MY ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_MY) +#define RAIL_ZWAVE_REGIONID_IN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IN) +#define RAIL_ZWAVE_REGIONID_JP ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_JP) +#define RAIL_ZWAVE_REGIONID_RU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_RU) +#define RAIL_ZWAVE_REGIONID_IL ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IL) +#define RAIL_ZWAVE_REGIONID_KR ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_KR) +#define RAIL_ZWAVE_REGIONID_CN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_CN) +#define RAIL_ZWAVE_REGIONID_US_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR1) +#define RAIL_ZWAVE_REGIONID_US_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR2) +#define RAIL_ZWAVE_REGIONID_US_LR3 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR3) #define RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE) -#define RAIL_ZWAVE_REGIONID_EU_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR1) -#define RAIL_ZWAVE_REGIONID_EU_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR2) +#define RAIL_ZWAVE_REGIONID_EU_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR1) +#define RAIL_ZWAVE_REGIONID_EU_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR2) +#define RAIL_ZWAVE_REGIONID_EU_LR3 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR3) #define RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE) -#define RAIL_ZWAVE_REGIONID_COUNT ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_COUNT) +#define RAIL_ZWAVE_REGIONID_COUNT ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_COUNT) #endif //DOXYGEN_SHOULD_SKIP_THIS #ifndef DOXYGEN_SHOULD_SKIP_THIS -// Largest ACK timeout period based on +// Largest Ack timeout period based on // aPhyTurnaroundTimeRxTx (1 ms max)+ (aMacTransferAckTimeTX (168 bits)* (1/data rate)) // For slowest Data Rate R1 (19.6 kbit/s) #define RAIL_ZWAVE_MAX_ACK_TIMEOUT_US (9600U) @@ -387,23 +423,22 @@ RAIL_ENUM(RAIL_ZWAVE_RegionId_t) { #define RAIL_ZWAVE_TIME_TX_TO_RX_US (0U) #define RAIL_ZWAVE_TIME_IDLE_TO_TX_US (0U) #define RAIL_ZWAVE_TIME_RX_TO_TX_US (1000U) - #endif //DOXYGEN_SHOULD_SKIP_THIS /** - * Invalid beam TX power value returned when \ref RAIL_ZWAVE_GetLrBeamTxPower + * Invalid beam TX power value returned when \ref RAIL_ZWAVE_GetLrBeamTxPower() * is called after receiving a regular non-long-range beam. */ #define RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID (0xFFU) /** * @struct RAIL_ZWAVE_LrAckData_t - * @brief Configuration structure for Z-Wave Long Range ACK. + * @brief Configuration structure for Z-Wave Long Range Ack. */ typedef struct RAIL_ZWAVE_LrAckData { /// Radio noise level measured on the channel the frame is transmitted on. int8_t noiseFloorDbm; - /// Transmit power used to transmit the ongoing Z-Wave Long Range ACK. + /// Transmit power used to transmit the ongoing Z-Wave Long Range Ack. int8_t txPowerDbm; /// Signal strength measured while receiving the Z-Wave Long Range frame. int8_t receiveRssiDbm; @@ -429,7 +464,7 @@ typedef struct RAIL_ZWAVE_BeamRxConfig { } RAIL_ZWAVE_BeamRxConfig_t; /** - * Number of channels in each of Z-Wave's region-based PHYs + * Number of channels in each of Z-Wave's region-based PHYs. */ #define RAIL_NUM_ZWAVE_CHANNELS (4U) @@ -438,11 +473,16 @@ typedef struct RAIL_ZWAVE_BeamRxConfig { * @brief Each Z-Wave region supports 3 channels. */ typedef struct RAIL_ZWAVE_RegionConfig { - uint32_t frequency[RAIL_NUM_ZWAVE_CHANNELS]; /**< Channel frequency in hertz*/ - RAIL_TxPower_t maxPower[RAIL_NUM_ZWAVE_CHANNELS]; /**< The maximum power allowed on the channel*/ - RAIL_ZWAVE_Baud_t baudRate[RAIL_NUM_ZWAVE_CHANNELS]; /**< Channel baud rate index*/ - RAIL_ZWAVE_RegionId_t regionId; /**< Identification number for the region*/ - RAIL_ZWAVE_RegionOptions_t regionSpecific; /**< Encapsulates region specific data*/ + /** Channel frequency in hertz. */ + uint32_t frequency[RAIL_NUM_ZWAVE_CHANNELS]; + /** The maximum power allowed on the channel, in dBm. */ + RAIL_TxPower_t maxPower[RAIL_NUM_ZWAVE_CHANNELS]; + /** Channel baud rate index. */ + RAIL_ZWAVE_Baud_t baudRate[RAIL_NUM_ZWAVE_CHANNELS]; + /** Identification number for the region. */ + RAIL_ZWAVE_RegionId_t regionId; + /** Encapsulates region-specific options. */ + RAIL_ZWAVE_RegionOptions_t regionSpecific; } RAIL_ZWAVE_RegionConfig_t; /** @@ -453,7 +493,8 @@ typedef struct RAIL_ZWAVE_RegionConfig { * while index 1 will hold the high side image rejection value (channel 1). */ typedef struct RAIL_ZWAVE_IrcalVal { - RAIL_IrCalValues_t imageRejection[2]; /**< Low side and high side image rejection values*/ + /** Low side and high side image rejection values. */ + RAIL_IrCalValues_t imageRejection[2]; } RAIL_ZWAVE_IrcalVal_t; /** @@ -465,14 +506,14 @@ typedef RAIL_RxChannelHoppingParameter_t RAIL_RxChannelHoppingParameters_t[RAIL_ /** * Switch the Z-Wave region. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] regionCfg Z-Wave channel configuration for the selected region + * @param[in] railHandle A RAIL instance handle. + * @param[in] regionCfg A pointer to a Z-Wave channel configuration for the selected region. * @return Status code indicating success of the function call. * * @note Setting a new Z-Wave Region will default any Low Power values to * Normal Power values for the region. * Z-Wave Region configuration must always be followed by a Low Power setup - * in case one desires to have the Low Power ACKing functionality. + * in case one desires to have the Low Power Acking functionality. */ RAIL_Status_t RAIL_ZWAVE_ConfigRegion(RAIL_Handle_t railHandle, const RAIL_ZWAVE_RegionConfig_t *regionCfg); @@ -481,7 +522,7 @@ RAIL_Status_t RAIL_ZWAVE_ConfigRegion(RAIL_Handle_t railHandle, * Perform image rejection calibration on all valid channels of a * Z-Wave region. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in,out] pIrCalVals An application-provided pointer of * type \ref RAIL_ZWAVE_IrcalVal_t. This is populated with image rejection * calibration values, if not NULL or initialized with @@ -499,18 +540,19 @@ RAIL_Status_t RAIL_ZWAVE_ConfigRegion(RAIL_Handle_t railHandle, RAIL_Status_t RAIL_ZWAVE_PerformIrcal(RAIL_Handle_t railHandle, RAIL_ZWAVE_IrcalVal_t *pIrCalVals, bool forceIrcal); + /** * Initialize RAIL for Z-Wave features. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] config A Z-Wave configuration structure. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @param[in] config A pointer to a Z-Wave configuration structure. + * @return Status code indicating success of the function call. * * This function is the entry point for working with Z-Wave within * RAIL. It sets up relevant hardware acceleration for Z-Wave-specific - * features, such as HomeId filtering and beam packets (as + * features, such as Home Id filtering and beam packets (as * specified in the configuration) and allows users to select the - * relevant Z-Wave region-specific PHY via \ref RAIL_ZWAVE_ConfigRegion. + * relevant Z-Wave region-specific PHY via \ref RAIL_ZWAVE_ConfigRegion(). */ RAIL_Status_t RAIL_ZWAVE_Init(RAIL_Handle_t railHandle, const RAIL_ZWAVE_Config_t *config); @@ -518,18 +560,18 @@ RAIL_Status_t RAIL_ZWAVE_Init(RAIL_Handle_t railHandle, /** * De-initialize Z-Wave hardware acceleration. * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. * * Disables and resets all Z-Wave hardware acceleration features. This - * function should only be called when the radio is IDLE. + * function should only be called when the radio is idle. */ RAIL_Status_t RAIL_ZWAVE_Deinit(RAIL_Handle_t railHandle); /** * Return whether Z-Wave hardware acceleration is currently enabled. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @return true if Z-Wave hardware acceleration was enabled to start with * and false otherwise. */ @@ -538,7 +580,7 @@ bool RAIL_ZWAVE_IsEnabled(RAIL_Handle_t railHandle); /** * Configure Z-Wave options. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] mask A bitmask containing which options should be modified. * @param[in] options A bitmask containing desired configuration settings. * Bit positions for each option are found in the \ref RAIL_ZWAVE_Options_t. @@ -549,31 +591,31 @@ RAIL_Status_t RAIL_ZWAVE_ConfigOptions(RAIL_Handle_t railHandle, RAIL_ZWAVE_Options_t options); /** - * Inform RAIL of the Z-Wave node's NodeId for receive filtering. + * Inform RAIL of the Z-Wave node's Node Id for receive filtering. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] nodeId A Z-Wave Node ID. + * @param[in] railHandle A RAIL instance handle. + * @param[in] nodeId A Z-Wave Node Id. * @return Status code indicating success of the function call. * - * @note Until this API is called, RAIL will assume the NodeId is + * @note Until this API is called, RAIL will assume the Node Id is * \ref RAIL_ZWAVE_NODE_ID_DEFAULT. */ RAIL_Status_t RAIL_ZWAVE_SetNodeId(RAIL_Handle_t railHandle, RAIL_ZWAVE_NodeId_t nodeId); /** - * Inform RAIL of the Z-Wave node's HomeId and its hash for receive filtering + * Inform RAIL of the Z-Wave node's Home Id and its hash for receive filtering. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] homeId A Z-Wave HomeId. - * @param[in] homeIdHash The hash of the HomeId expected in beam frames. + * @param[in] railHandle A RAIL instance handle. + * @param[in] homeId A Z-Wave Home Id. + * @param[in] homeIdHash The hash of the Home Id expected in beam frames. * If this is \ref RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, beam frame detection - * will not check the HomeIdHash in a received beam frame at all, and - * \ref RAIL_EVENT_ZWAVE_BEAM will trigger based solely on the NodeId + * will not check the Home Id hash in a received beam frame at all, and + * \ref RAIL_EVENT_ZWAVE_BEAM will trigger based solely on the Node Id * in the beam frame. * @return Status code indicating success of the function call. * - * @note Until this API is called, RAIL will assume the HomeId is an + * @note Until this API is called, RAIL will assume the Home Id is an * illegal one of \ref RAIL_ZWAVE_HOME_ID_DEFAULT, and its hash is \ref * RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE. */ @@ -582,10 +624,10 @@ RAIL_Status_t RAIL_ZWAVE_SetHomeId(RAIL_Handle_t railHandle, RAIL_ZWAVE_HomeIdHash_t homeIdHash); /** - * Get the NodeId of the most recently seen beam frame that triggered + * Get the Node Id of the most recently seen beam frame that triggered * \ref RAIL_EVENT_ZWAVE_BEAM. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[out] pNodeId A pointer to \ref RAIL_ZWAVE_NodeId_t to populate. * @return Status code indicating success of the function call. * @@ -597,15 +639,15 @@ RAIL_Status_t RAIL_ZWAVE_GetBeamNodeId(RAIL_Handle_t railHandle, RAIL_ZWAVE_NodeId_t *pNodeId); /** - * Get the HomeIdHash of the most recently seen beam frame that triggered + * Get the Home Id hash of the most recently seen beam frame that triggered * \ref RAIL_EVENT_ZWAVE_BEAM. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[out] pBeamHomeIdHash A pointer to \ref RAIL_ZWAVE_HomeIdHash_t to populate. * @return Status code indicating success of the function call. * * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM - * event; if multiple beams are received only the most recent beam's HomeIdHash + * event; if multiple beams are received only the most recent beam's Home Id hash * is provided. */ RAIL_Status_t RAIL_ZWAVE_GetBeamHomeIdHash(RAIL_Handle_t railHandle, @@ -615,7 +657,7 @@ RAIL_Status_t RAIL_ZWAVE_GetBeamHomeIdHash(RAIL_Handle_t railHandle, * Get the channel hopping index of the most recently seen beam frame that * triggered \ref RAIL_EVENT_ZWAVE_BEAM. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[out] pChannelIndex A pointer to a uint8_t to populate with * the channel hopping index. If channel-hopping was off at the time * the beam packet was received, \ref RAIL_CHANNEL_HOPPING_INVALID_INDEX @@ -633,7 +675,7 @@ RAIL_Status_t RAIL_ZWAVE_GetBeamChannelIndex(RAIL_Handle_t railHandle, * Get the TX power used by the transmitter of the most recently seen * long range beam frame that triggered \ref RAIL_EVENT_ZWAVE_BEAM. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[out] pLrBeamTxPower An application provided pointer to a uint8_t to * be populated with the TX power of the latest long range beam. This will * be set to \ref RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID if this API is called @@ -651,22 +693,22 @@ RAIL_Status_t RAIL_ZWAVE_GetBeamChannelIndex(RAIL_Handle_t railHandle, * * *
Tx Power Value Description - *
0 -6dBm - *
1 -2dBm - *
2 +2dBm - *
3 +6dBm - *
4 +10dBm - *
5 +13dBm - *
6 +16dBm - *
7 +19dBm - *
8 +21dBm - *
9 +23Bm - *
10 +25dBm - *
11 +26dBm - *
12 +27dBm - *
13 +28dBm - *
14 +29dBm - *
15 +30dBm + *
0 -6 dBm + *
1 -2 dBm + *
2 +2 dBm + *
3 +6 dBm + *
4 +10 dBm + *
5 +13 dBm + *
6 +16 dBm + *
7 +19 dBm + *
8 +21 dBm + *
9 +23 dBm + *
10 +25 dBm + *
11 +26 dBm + *
12 +27 dBm + *
13 +28 dBm + *
14 +29 dBm + *
15 +30 dBm *
*/ RAIL_Status_t RAIL_ZWAVE_GetLrBeamTxPower(RAIL_Handle_t railHandle, @@ -675,7 +717,7 @@ RAIL_Status_t RAIL_ZWAVE_GetLrBeamTxPower(RAIL_Handle_t railHandle, /** * Get the RSSI of the received beam frame. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[out] pBeamRssi An application provided pointer to a int8_t to * be populated with the latest beam's RSSI, in dBm. * @return Status code indicating success of the function call. This function @@ -688,30 +730,30 @@ RAIL_Status_t RAIL_ZWAVE_GetLrBeamTxPower(RAIL_Handle_t railHandle, */ RAIL_Status_t RAIL_ZWAVE_GetBeamRssi(RAIL_Handle_t railHandle, int8_t *pBeamRssi); + /** * Set the Raw Low Power settings. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] powerLevel Desired low power raw level. * @return Status code indicating success of the function call. * - * Low Power settings are required during ACK transmissions when + * Low Power settings are required during Ack transmissions when * the Low Power Bit is set. This setting is only valid for one * subsequent transmission, after which all transmissions will be * at the nominal power setting, until re-invoked. */ - RAIL_Status_t RAIL_ZWAVE_SetTxLowPower(RAIL_Handle_t railHandle, uint8_t powerLevel); /** - * Set the Low Power settings in dBm. + * Set the Low Power settings in deci-dBm. * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] powerLevel Desired low power level dBm. + * @param[in] railHandle A RAIL instance handle. + * @param[in] powerLevel Desired low power level deci-dBm. * @return Status code indicating success of the function call. * - * Low Power settings are required during ACK transmissions when + * Low Power settings are required during Ack transmissions when * the Low Power Bit is set. This setting is only valid for one * subsequent transmission, after which all transmissions will be * at the nominal power setting, until re-invoked. @@ -728,15 +770,15 @@ RAIL_Status_t RAIL_ZWAVE_SetTxLowPowerDbm(RAIL_Handle_t railHandle, * transmit power. * * This API returns the low raw power value that was set by - * \ref RAIL_ZWAVE_SetTxLowPower. + * \ref RAIL_ZWAVE_SetTxLowPower(). * * Calling this function before configuring the Low Power PA * (i.e., before a successful - * call to \ref RAIL_ZWAVE_SetTxLowPowerDbm or \ref RAIL_ZWAVE_SetTxLowPower) - * will return the low power value same as the nominal power. + * call to \ref RAIL_ZWAVE_SetTxLowPowerDbm() or \ref RAIL_ZWAVE_SetTxLowPower()) + * will return a low power value that is the same as the nominal power. * Also, calling this function before configuring the PA - * (i.e., before a successful call to \ref RAIL_ConfigTxPower) will return an error - * (RAIL_TX_POWER_LEVEL_INVALID). + * (i.e., before a successful call to \ref RAIL_ConfigTxPower()) will return + * \ref RAIL_TX_POWER_LEVEL_INVALID. */ RAIL_TxPowerLevel_t RAIL_ZWAVE_GetTxLowPower(RAIL_Handle_t railHandle); @@ -753,16 +795,17 @@ RAIL_TxPower_t RAIL_ZWAVE_GetTxLowPowerDbm(RAIL_Handle_t railHandle); * Implement beam detection and reception algorithms. * * @param[in] railHandle A RAIL instance handle. - * @param[out] beamDetectIndex Indicator of whether or not a beam was detected + * @param[out] beamDetectIndex A pointer to an indicator of whether or not a beam was detected * at all, regardless of if it was received, generally for use only by instruction * from Silicon Labs. Can be NULL. - * @param[out] schedulerInfo While Z-Wave is currently not supported in - * RAIL Multiprotocol, this scheduler info is added to future proof - * against any future version of multiprotocol which may support it. For now, - * this argument can be NULL. - * @return status indicating whether or not the radio was able to configure - * beam packet detection/reception. Reasons for failure include an un-idled - * radio or a non-Japan non-Korea region configured before calling this function. + * @param[in] schedulerInfo A pointer to information to allow the radio scheduler to place + * this operation appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * Note that Z-Wave currently does not support multiprotocol, so this + * scheduler info exists to future proof the API for when it does. + * @return Status code indicating success of the function call. + * Reasons for failure include an un-idled radio or a non-Japan non-Korea + * region configured before calling this function. * * This function takes care of all configuration and radio setup to * detect and receive beams in the current Z-Wave region. @@ -777,18 +820,18 @@ RAIL_TxPower_t RAIL_ZWAVE_GetTxLowPowerDbm(RAIL_Handle_t railHandle); * Until one of these events is received, users should not try to * reconfigure radio settings or start another radio operation. If an application * needs to do some other operation or configuration, it must first call - * \ref RAIL_Idle and wait for the radio to idle. + * \ref RAIL_Idle() and wait for the radio to idle. * * @note: The radio must be idle before calling this function. * - * @note: \ref RAIL_ConfigRxChannelHopping must have been called successfully + * @note: \ref RAIL_ConfigRxChannelHopping() must have been called successfully * in Z-Wave before this function is called to provide a valid memory buffer * for internal use (see \ref RAIL_RxChannelHoppingConfig_t::buffer). * * @note: This function alters radio functionality substantially. After calling - * it, the user should call \ref RAIL_ZWAVE_ConfigRegion, - * \ref RAIL_ConfigRxChannelHopping, \ref RAIL_EnableRxChannelHopping, - * and \ref RAIL_SetRxTransitions to reset these parameters to whatever + * it, the user should call \ref RAIL_ZWAVE_ConfigRegion(), + * \ref RAIL_ConfigRxChannelHopping(), \ref RAIL_EnableRxChannelHopping(), + * and \ref RAIL_SetRxTransitions() to reset these parameters to whatever * behaviors were desired before calling this function. Additionally, * this function will idle the radio upon on exit. */ @@ -797,15 +840,16 @@ RAIL_Status_t RAIL_ZWAVE_ReceiveBeam(RAIL_Handle_t railHandle, const RAIL_SchedulerInfo_t *schedulerInfo); /** - * Configure the receive algorithm used in \ref RAIL_ZWAVE_ReceiveBeam. + * Configure the receive algorithm used in \ref RAIL_ZWAVE_ReceiveBeam(). * * @param[in] railHandle A RAIL instance handle. - * @param[in] config Configuration for beam detection algorithm. + * @param[in] config A pointer to a configuration for the beam detection algorithm. * @return Status code indicating success of the function call. * * @warning This function should not be used without direct instruction by Silicon Labs. */ -RAIL_Status_t RAIL_ZWAVE_ConfigBeamRx(RAIL_Handle_t railHandle, RAIL_ZWAVE_BeamRxConfig_t *config); +RAIL_Status_t RAIL_ZWAVE_ConfigBeamRx(RAIL_Handle_t railHandle, + RAIL_ZWAVE_BeamRxConfig_t *config); /** * Set the default RX beam configuration. @@ -814,8 +858,8 @@ RAIL_Status_t RAIL_ZWAVE_ConfigBeamRx(RAIL_Handle_t railHandle, RAIL_ZWAVE_BeamR * @return Status code indicating success of the function call. * * @note This function resets any changes made to the beam configuration via - * \ref RAIL_ZWAVE_ConfigBeamRx and the default beam configuration will be in effect - * on subsequent call(s) to \ref RAIL_ZWAVE_ReceiveBeam. + * \ref RAIL_ZWAVE_ConfigBeamRx() and the default beam configuration will be in effect + * on subsequent call(s) to \ref RAIL_ZWAVE_ReceiveBeam(). */ RAIL_Status_t RAIL_ZWAVE_SetDefaultRxBeamConfig(RAIL_Handle_t railHandle); @@ -824,7 +868,7 @@ RAIL_Status_t RAIL_ZWAVE_SetDefaultRxBeamConfig(RAIL_Handle_t railHandle); * * @param[out] pConfig A pointer to \ref RAIL_ZWAVE_BeamRxConfig_t to be * populated with the current beam configuration. - * @return A status code indicating success of the function call. + * @return Status code indicating success of the function call. */ RAIL_Status_t RAIL_ZWAVE_GetRxBeamConfig(RAIL_ZWAVE_BeamRxConfig_t *pConfig); @@ -832,7 +876,7 @@ RAIL_Status_t RAIL_ZWAVE_GetRxBeamConfig(RAIL_ZWAVE_BeamRxConfig_t *pConfig); * Configure the channel hop timings for use in Z-Wave RX channel hop configuration. * * @param[in] railHandle A RAIL instance handle. - * @param[in,out] config Configuration for Z-Wave RX channel hopping. + * @param[in,out] config A pointer to a configuration for Z-Wave RX channel hopping. * This structure must be allocated in application global read-write memory. * RAIL will populate fields within or referenced by this structure during its * operation. Be sure to allocate \ref RAIL_RxChannelHoppingConfigEntry_t @@ -847,7 +891,8 @@ RAIL_Status_t RAIL_ZWAVE_GetRxBeamConfig(RAIL_ZWAVE_BeamRxConfig_t *pConfig); * API must never be called while the radio is on with RX Duty Cycle or Channel * Hopping enabled. */ -RAIL_Status_t RAIL_ZWAVE_ConfigRxChannelHopping(RAIL_Handle_t railHandle, RAIL_RxChannelHoppingConfig_t *config); +RAIL_Status_t RAIL_ZWAVE_ConfigRxChannelHopping(RAIL_Handle_t railHandle, + RAIL_RxChannelHoppingConfig_t *config); /** * Get the Z-Wave region. @@ -855,88 +900,92 @@ RAIL_Status_t RAIL_ZWAVE_ConfigRxChannelHopping(RAIL_Handle_t railHandle, RAIL_R * @param[in] railHandle A RAIL instance handle. * @return The \ref RAIL_ZWAVE_RegionId_t value. * - * @note \ref RAIL_ZWAVE_ConfigRegion must have been called successfully + * @note \ref RAIL_ZWAVE_ConfigRegion() must have been called successfully * before this function is called. Otherwise, \ref RAIL_ZWAVE_REGIONID_UNKNOWN * is returned. */ RAIL_ZWAVE_RegionId_t RAIL_ZWAVE_GetRegion(RAIL_Handle_t railHandle); /** - * Write the AutoACK FIFO for the next outgoing Z-Wave Long Range ACK. + * Write the Auto-Ack FIFO for the next outgoing Z-Wave Long Range Ack. * - * @param[in] railHandle A handle of RAIL instance. + * @param[in] railHandle A RAIL instance handle. * @param[in] pLrAckData An application provided pointer to a const * \ref RAIL_ZWAVE_LrAckData_t to populate the noise floor, TX power and receive - * rssi bytes of the outgoing Z-Wave Long Range ACK packet. - * @return A status code indicating success of the function call. + * rssi bytes of the outgoing Z-Wave Long Range Ack packet. + * @return Status code indicating success of the function call. * - * This function sets the AutoACK data to use in acknowledging the frame + * This function sets the Auto-Ack data to use in acknowledging the frame * being received. It must only be called while processing the \ref * RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND. * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to - * write the outgoing ACK. When successful, the ackData will - * only be sent once. Subsequent packets needing an Z-Wave Long Range ACK will - * each need to call this function to write the ACK information. + * write the outgoing Ack. When successful, the ackData will + * only be sent once. Subsequent packets needing an Z-Wave Long Range Ack will + * each need to call this function to write the Ack information. */ RAIL_Status_t RAIL_ZWAVE_SetLrAckData(RAIL_Handle_t railHandle, const RAIL_ZWAVE_LrAckData_t *pLrAckData); -/** EU-European Union, RAIL_ZWAVE_REGION_EU */ +/** EU-European Union */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU; -/** US-United States, RAIL_ZWAVE_REGION_US */ +/** US-United States */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US; -/** ANZ-Australia/New Zealand, RAIL_ZWAVE_REGION_ANZ */ +/** ANZ-Australia/New Zealand */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_ANZ; -/** HK-Hong Kong, RAIL_ZWAVE_REGION_HK */ +/** HK-Hong Kong */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_HK; -/** MY-Malaysia, RAIL_ZWAVE_REGION_MY */ +/** MY-Malaysia */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_MY; -/** IN-India, RAIL_ZWAVE_REGION_IN */ +/** IN-India */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IN; -/** JP-Japan, RAIL_ZWAVE_REGION_JP */ +/** JP-Japan */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JP; -/** JP-Japan, RAIL_ZWAVE_REGION_JP */ +/** JP-Japan Energy-Detect */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JPED; -/** RU-Russia, RAIL_ZWAVE_REGION_RU */ +/** RU-Russia */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_RU; -/** IL-Israel, RAIL_ZWAVE_REGION_IL */ +/** IL-Israel */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IL; -/** KR-Korea, RAIL_ZWAVE_REGION_KR */ +/** KR-Korea */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KR; -/** KR-Korea, RAIL_ZWAVE_REGION_KR */ +/** KR-Korea Energy-Detect */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KRED; -/** CN-China, RAIL_ZWAVE_REGION_CN */ +/** CN-China */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_CN; -/** US-Long Range 1, RAIL_ZWAVE_REGION_US_LR1 */ +/** US-Long Range 1 */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR1; -/** US-Long Range 2, RAIL_ZWAVE_REGION_US_LR2 */ +/** US-Long Range 2 */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR2; -/** US-Long Range End Device, RAIL_ZWAVE_REGION_US_LR_END_DEVICE */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR_END_DEVICE; +/** US-Long Range 3 */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR3; +/** Backwards-compatible define */ +#define RAIL_ZWAVE_REGION_US_LR_END_DEVICE RAIL_ZWAVE_REGION_US_LR3 -/** EU-Long Range 1, RAIL_ZWAVE_REGION_EU_LR1 */ +/** EU-Long Range 1 */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR1; -/** EU-Long Range 2, RAIL_ZWAVE_REGION_EU_LR2 */ +/** EU-Long Range 2 */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR2; -/** EU-Long Range End Device, RAIL_ZWAVE_REGION_EU_LR_END_DEVICE */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR_END_DEVICE; +/** EU-Long Range 3 */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR3; +/** Backwards-compatible define */ +#define RAIL_ZWAVE_REGION_EU_LR_END_DEVICE RAIL_ZWAVE_REGION_EU_LR3 /** Invalid Region */ extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_INVALID; diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager.h index 077fd6dd2..48570526e 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager.h @@ -30,11 +30,6 @@ #ifndef SL_SE_MANAGER_H #define SL_SE_MANAGER_H -#if defined(_SILICON_LABS_32B_SERIES_2) -// Not used by this file, but included for backwards compatibility -#include "em_se.h" -#endif - #include "sli_se_manager_features.h" #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h index fa808ab88..27e75008f 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h @@ -762,7 +762,8 @@ sl_status_t sl_se_cmac_multipart_finish(sl_se_cmac_multipart_context_t *cmac_ctx * Pointer to an SE command context object. * * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. + * Pointer to @c sl_se_key_descriptor_t structure specifying the key to use in + * the GCM computation. * * @param[in] mode * The operation to perform: SL_SE_ENCRYPT or SL_SE_DECRYPT. @@ -801,6 +802,13 @@ sl_status_t sl_se_gcm_multipart_starts(sl_se_gcm_multipart_context_t *gcm_ctx, * @param[in, out] gcm_ctx * Pointer to a GCM streaming context object. * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to @c sl_se_key_descriptor_t structure specifying the key to used in + * the GCM computation. + * * @param[in] length * The length of the input data. * @@ -833,6 +841,13 @@ sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, * @param[in, out] gcm_ctx * Pointer to a GCM streaming context object. * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to @c sl_se_key_descriptor_t structure specifying the key to use in + * the GCM computation. + * * @param[in, out] tag * Encryption: The buffer for holding the tag. * Decryption: The tag to authenticate. @@ -1101,6 +1116,129 @@ sl_status_t sl_se_poly1305_genkey_tag(sl_se_command_context_t *cmd_ctx, #endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +#if defined(_SILICON_LABS_32B_SERIES_3) + +/***************************************************************************//** + * @brief + * Prepare a HMAC streaming command context object to be used in subsequent + * HMAC streaming function calls. + * + * @param[in] cmd_ctx + * Pointer to a SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure specifying the key to use in + * the HMAC computation. + * + * @param[in] hash_type + * Which hashing algorithm to use. + * + * @param[in] message + * Pointer to the message buffer to compute the hash/digest from. + * + * @param[in] message_len + * Number of bytes in message. + * + * @param[out] state_out + * Pointer to memory buffer to store the final HMAC output. + * + * @param[in] state_out_len + * The length of the HMAC output memory buffer, must be at least the size + * of the corresponding hash type + 8 bytes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hmac_multipart_starts(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *state_out, + size_t state_out_len); + +/***************************************************************************//** + * @brief + * This function feeds an input buffer into an ongoing HMAC computation. + * + * @param[in] cmd_ctx + * Pointer to a SE command context object. + * + * @param[in] hash_type + * Which hashing algorithm to use. + * + * @param[in] message + * Pointer to the message buffer to compute the hash/digest from. + * + * @param[in] message_len + * Number of bytes in message. + * + * @param[in,out] state_in_out + * Pointer to memory buffer to store the HMAC state. + * + * @param[in] state_in_out_len + * The length of the HMAC state buffer, must be at least the size + * of the corresponding hash type + 8 bytes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hmac_multipart_update(sl_se_command_context_t *cmd_ctx, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *state_in_out, + size_t state_in_out_len); + +/***************************************************************************//** + * @brief + * Finish a HMAC streaming operation and return the resulting HMAC. + * + * @param[in] cmd_ctx + * Pointer to a SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure specifying the key to use in + * the HMAC computation. + * + * @param[in] hash_type + * Which hashing algorithm to use. + * + * @param[in] message + * Pointer to the message buffer to compute the hash/digest from. + * + * @param[in] message_len + * Number of bytes in message. + * + * @param[in] state_in + * Pointer to memory buffer containing the HMAC state. + * + * @param[in] state_in_out_len + * The length of the HMAC state buffer, must be at least the size + * of the corresponding hash type + 8 bytes. + * + * @param[out] output + * Pointer to memory buffer to store the final HMAC output. + * + * @param[in] output_len + * The length of the HMAC output memory buffer, must be at least the size + * of the corresponding hash type. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hmac_multipart_finish(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *state_in, + size_t state_in_len, + uint8_t *output, + size_t output_len); + +#endif // defined(_SILICON_LABS_32B_SERIES_3) + #ifdef __cplusplus } #endif diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h index 8efbedfc2..8489bdb94 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h @@ -60,6 +60,19 @@ extern "C" { // ----------------------------------------------------------------------------- // Defines +/// @addtogroup sl_se_manager_core +/// @{ + +/// Context initialization values. Some of the context values are not fully +/// initialized. The user will need to call the corresponding initialization +/// function in order to fully initialize the context objects for further use +/// in the SE Manager API. The purpose of these initialization values is to set +/// the context objects to a known safe state initially when the context object +/// is declared. +#define SL_SE_COMMAND_CONTEXT_INIT { SLI_SE_MAILBOX_COMMAND_DEFAULT(0), false } + +/// @} (end addtogroup sl_se_manager_core) + /// @addtogroup sl_se_manager_util /// @{ @@ -214,9 +227,15 @@ extern "C" { #define SL_SE_KEY_SLOT_VOLATILE_3 0x03 ///< Internal volatile slot 3 #endif +#if defined(SLI_SE_SUPPORTS_NVM3_INTERNAL_KEY) /// Minimum key slot value for internal keys -#define SL_SE_KEY_SLOT_INTERNAL_MIN 0xF7 - + #define SL_SE_KEY_SLOT_INTERNAL_MIN 0xF6 +/// Internal NVM3 key + #define SL_SE_KEY_SLOT_NVM3_KEY 0xF6 +#else +/// Minimum key slot value for internal keys + #define SL_SE_KEY_SLOT_INTERNAL_MIN 0xF7 +#endif /// Internal TrustZone root key #define SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY 0xF7 /// Internal immutable application secure debug key @@ -315,9 +334,9 @@ extern "C" { #define SL_SE_TAMPER_SIGNAL_SE_ICACHE_ERROR 0x1F ///< SE ICACHE checksum error #define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20 ///< Number of tamper signals -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) -// SE tamper signals for xG25, with ETAMPDET signal included. +// SE tamper signals for xG25 and xG29, with ETAMPDET signal included. #define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0 ///< Reserved tamper signal #define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1 ///< Filter counter exceeds threshold #define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2 ///< SE watchdog timeout @@ -443,23 +462,6 @@ extern "C" { /// @} (end addtogroup sl_se_manager_util) -/// @addtogroup sl_se_manager_core -/// @{ - -/// Context initialization values. Some of the context values are not fully -/// initialized. The user will need to call the corresponding initialization -/// function in order to fully initialize the context objects for further use -/// in the SE Manager API. The purpose of these initialization values is to set -/// the context objects to a known safe state initially when the context object -/// is declared. -#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) -#define SL_SE_COMMAND_CONTEXT_INIT { SLI_SE_MAILBOX_COMMAND_DEFAULT(0), false } -#else -#define SL_SE_COMMAND_CONTEXT_INIT { SLI_SE_MAILBOX_COMMAND_DEFAULT(0) } -#endif - -/// @} (end addtogroup sl_se_manager_core) - /// @addtogroup sl_se_manager_cipher /// @{ @@ -489,11 +491,22 @@ extern "C" { // ------------------------------- // Defines for Root code functionality -#define SL_SE_COMMAND_CONTEXT_INIT { SLI_SE_MAILBOX_COMMAND_DEFAULT(0) } #define SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT 16U #endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +#if defined(_SILICON_LABS_32B_SERIES_3) +/// @addtogroup sl_se_manager_extmem +/// @{ + +// The maximum number of code regions available on the device. +// The number of available code regions may be different on future devices. +#define SL_SE_MAX_CODE_REGIONS 8 + +/// @} (end addtogroup sl_se_manager_extmem) + +#endif // defined(_SILICON_LABS_32B_SERIES_3) + #ifdef __cplusplus } #endif diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h index daa5bd7a1..ad7ad318c 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h @@ -138,14 +138,12 @@ typedef struct { * sl_se_set_yield(). ******************************************************************************/ typedef struct sl_se_command_context_t { - sli_se_mailbox_command_t command; ///< SE mailbox command struct -#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - bool yield; ///< If true, yield the CPU core while + sli_se_mailbox_command_t command; ///< SE mailbox command struct + bool yield; ///< If true, yield the CPU core while ///< waiting for the SE mailbox command ///< to complete. If false, busy-wait, by ///< polling the SE mailbox response ///< register. -#endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION } sl_se_command_context_t; /// @} (end addtogroup sl_se_manager_core) @@ -360,7 +358,7 @@ typedef struct { union { uint8_t tagbuf[16]; ///< Tag uint8_t final_data[16]; ///< Input data saved for finish operation - } mode_specific_buffer; + } mode_specific_buffer; ///< Buffer containing Tag and input data saved for finish operation #endif uint8_t final_data_length; ///< Length of data saved } sl_se_ccm_multipart_context_t; @@ -534,8 +532,8 @@ typedef struct { /// Security level of code region typedef enum { SL_SE_CODE_REGION_SECURITY_LEVEL_PLAINTEXT = 0, - SL_SE_CODE_REGION_SECURITY_LEVEL_ENCRYPTED_ONLY, - SL_SE_CODE_REGION_SECURITY_LEVEL_ENCRYPTED_AUTHENTICATED, + SL_SE_CODE_REGION_SECURITY_LEVEL_ENC_ONLY, + SL_SE_CODE_REGION_SECURITY_LEVEL_ENC_AUTH, } sl_se_code_region_security_level_t; /// Code region configuration @@ -543,9 +541,8 @@ typedef struct { unsigned int region_idx; ///< Index of code region unsigned int region_size; ///< Size of code region sl_se_code_region_security_level_t security_level; ///< Security level of region - bool auto_secure_boot_enabled; ///< SE driven secure boot enabled (if true) bool bank_swapping_enabled; ///< Bank swapping enabled (if true) - bool active_banked_region; ///< Active banked region (if true) + bool locked; ///< Region is locked (if true) } sl_code_region_config_t; /// @} (end addtogroup sl_se_manager_extmem) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h index 975d58947..0a47846bf 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h @@ -83,8 +83,8 @@ extern "C" { * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_check_se_image(sl_se_command_context_t *cmd_ctx, void *image_addr); @@ -104,8 +104,8 @@ sl_status_t sl_se_check_se_image(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_apply_se_image(sl_se_command_context_t *cmd_ctx, void *image_addr); @@ -125,8 +125,8 @@ sl_status_t sl_se_apply_se_image(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_get_upgrade_status_se_image(sl_se_command_context_t *cmd_ctx, uint32_t *status, @@ -151,8 +151,8 @@ sl_status_t sl_se_get_upgrade_status_se_image(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_check_host_image(sl_se_command_context_t *cmd_ctx, void *image_addr, @@ -176,8 +176,8 @@ sl_status_t sl_se_check_host_image(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_apply_host_image(sl_se_command_context_t *cmd_ctx, void *image_addr, @@ -198,8 +198,8 @@ sl_status_t sl_se_apply_host_image(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_get_upgrade_status_host_image(sl_se_command_context_t *cmd_ctx, @@ -236,8 +236,8 @@ sl_se_get_upgrade_status_host_image(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_init_otp_key(sl_se_command_context_t *cmd_ctx, sl_se_device_key_type_t key_type, @@ -268,8 +268,8 @@ sl_status_t sl_se_init_otp_key(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_read_pubkey(sl_se_command_context_t *cmd_ctx, sl_se_device_key_type_t key_type, @@ -278,7 +278,10 @@ sl_status_t sl_se_read_pubkey(sl_se_command_context_t *cmd_ctx, /***************************************************************************//** * @brief - * Initialize SE OTP configuration. + * Initialize and commit SE OTP configuration to OTP. + * + * @warning + * When this function succeeds the configuration is committed to OTP and cannot be changed. * * @param[in] cmd_ctx * Pointer to an SE command context object. @@ -287,10 +290,11 @@ sl_status_t sl_se_read_pubkey(sl_se_command_context_t *cmd_ctx, * Pointer to OTP initialization structure. * * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - * @retval SL_STATUS_ABORT when the operation is not attempted. + * One of the following @ref sl_status_t codes: + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_ABORT when the operation is not attempted. + * ******************************************************************************/ sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, sl_se_otp_init_t *otp_init); @@ -307,10 +311,10 @@ sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, uint32_t *version); @@ -327,9 +331,9 @@ sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_COMMAND if OTP configuration isn't initialized - * @retval SL_STATUS_ABORT when the operation is not attempted. + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_COMMAND if OTP configuration isn't initialized + * - @c SL_STATUS_ABORT when the operation is not attempted. ******************************************************************************/ sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, sl_se_otp_init_t *otp_settings); @@ -346,12 +350,13 @@ sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_OWNERSHIP when the ownership is already taken - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_OWNERSHIP when the ownership is already taken + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SE_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, uint32_t *version); @@ -368,8 +373,8 @@ sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_get_debug_lock_status(sl_se_command_context_t *cmd_ctx, sl_se_debug_status_t *status); @@ -387,7 +392,7 @@ sl_status_t sl_se_get_debug_lock_status(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_OK when the command was executed successfully ******************************************************************************/ sl_status_t sl_se_apply_debug_lock(sl_se_command_context_t *cmd_ctx); @@ -409,10 +414,10 @@ sl_status_t sl_se_apply_debug_lock(sl_se_command_context_t *cmd_ctx); * Number of bytes to write to flash. NB: Must be divisable by four. * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_write_user_data(sl_se_command_context_t *cmd_ctx, uint32_t offset, @@ -428,10 +433,10 @@ sl_status_t sl_se_write_user_data(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_erase_user_data(sl_se_command_context_t *cmd_ctx); @@ -447,11 +452,11 @@ sl_status_t sl_se_erase_user_data(sl_se_command_context_t *cmd_ctx); * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK upon command completion. Errors are encoded in the + * - @c SL_STATUS_OK upon command completion. Errors are encoded in the * different parts of the returned status object. - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_get_status(sl_se_command_context_t *cmd_ctx, sl_se_status_t *status); @@ -468,10 +473,10 @@ sl_status_t sl_se_get_status(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_get_serialnumber(sl_se_command_context_t *cmd_ctx, void *serial); @@ -490,8 +495,8 @@ sl_status_t sl_se_get_serialnumber(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized ******************************************************************************/ sl_status_t sl_se_get_reset_cause(sl_se_command_context_t *cmd_ctx, uint32_t *reset_cause); @@ -517,9 +522,9 @@ sl_status_t sl_se_get_reset_cause(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_PARAMETER when cmd_ctx or reset_cause is NULL + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_PARAMETER when cmd_ctx or reset_cause is NULL ******************************************************************************/ sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, bool *was_tamper_reset, @@ -541,7 +546,7 @@ sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_OK when the command was executed successfully ******************************************************************************/ sl_status_t sl_se_enable_secure_debug(sl_se_command_context_t *cmd_ctx); @@ -558,7 +563,7 @@ sl_status_t sl_se_enable_secure_debug(sl_se_command_context_t *cmd_ctx); * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_OK when the command was executed successfully ******************************************************************************/ sl_status_t sl_se_disable_secure_debug(sl_se_command_context_t *cmd_ctx); @@ -579,7 +584,7 @@ sl_status_t sl_se_disable_secure_debug(sl_se_command_context_t *cmd_ctx); * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_OK when the command was executed successfully ******************************************************************************/ sl_status_t sl_se_set_debug_options(sl_se_command_context_t *cmd_ctx, const sl_se_debug_options_t *debug_options); @@ -603,8 +608,8 @@ sl_status_t sl_se_set_debug_options(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_COMMAND if device erase is disabled. + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_COMMAND if device erase is disabled. ******************************************************************************/ sl_status_t sl_se_erase_device(sl_se_command_context_t *cmd_ctx); @@ -627,7 +632,7 @@ sl_status_t sl_se_erase_device(sl_se_command_context_t *cmd_ctx); * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_OK when the command was executed successfully ******************************************************************************/ sl_status_t sl_se_disable_device_erase(sl_se_command_context_t *cmd_ctx); @@ -647,8 +652,8 @@ sl_status_t sl_se_disable_device_erase(sl_se_command_context_t *cmd_ctx); * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_get_challenge(sl_se_command_context_t *cmd_ctx, sl_se_challenge_t challenge); @@ -666,7 +671,7 @@ sl_status_t sl_se_get_challenge(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_OK when the command was executed successfully ******************************************************************************/ sl_status_t sl_se_roll_challenge(sl_se_command_context_t *cmd_ctx); @@ -688,10 +693,10 @@ sl_status_t sl_se_roll_challenge(sl_se_command_context_t *cmd_ctx); * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_open_debug(sl_se_command_context_t *cmd_ctx, void *cert, @@ -718,10 +723,10 @@ sl_status_t sl_se_open_debug(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * - @c SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed ******************************************************************************/ sl_status_t sl_se_disable_tamper(sl_se_command_context_t *cmd_ctx, void *cert, @@ -787,9 +792,9 @@ sl_status_t sl_se_read_cert(sl_se_command_context_t *cmd_ctx, * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - * @retval SL_STATUS_COMMAND_IS_INVALID when already in active mode + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_COMMAND_IS_INVALID when already in active mode ******************************************************************************/ sl_status_t sl_se_enter_active_mode(sl_se_command_context_t *cmd_ctx); @@ -805,9 +810,9 @@ sl_status_t sl_se_enter_active_mode(sl_se_command_context_t *cmd_ctx); * * @return * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - * @retval SL_STATUS_COMMAND_IS_INVALID when already not in active mode + * - @c SL_STATUS_OK when the command was executed successfully + * - @c SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * - @c SL_STATUS_COMMAND_IS_INVALID when already not in active mode ******************************************************************************/ sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx); @@ -844,6 +849,40 @@ sl_status_t sl_se_get_rollback_counter(sl_se_command_context_t *cmd_ctx, ******************************************************************************/ sl_status_t sl_se_increment_rollback_counter(sl_se_command_context_t *cmd_ctx); +/***************************************************************************//** + * @brief + * Reads back the stored upgrade file version. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * @param[out] version + * The stored upgrade file version. + * + * @return + * SL_STATUS_OK when the functions was successfully, or else, a status code + * of type sl_status_t that indicates why the function was not successful, + * ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_get_upgrade_file_version(sl_se_command_context_t *cmd_ctx, + uint32_t *version); + +/***************************************************************************//** + * @brief + * Records a new upgrade file version. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * @param[in] version + * New upgrade file version + * + * @return + * SL_STATUS_OK when the functions was successfully, or else, a status code + * of type sl_status_t that indicates why the function was not successful, + * ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_set_upgrade_file_version(sl_se_command_context_t *cmd_ctx, + uint32_t version); + #endif // defined(_SILICON_LABS_32B_SERIES_3) #endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h index 4f1ba2af4..3d1f8b2be 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h @@ -107,6 +107,10 @@ #define SLI_SE_MAJOR_VERSION_TWO #endif +#if defined(_SILICON_LABS_32B_SERIES_3) + #define SLI_SE_SUPPORTS_NVM3_INTERNAL_KEY +#endif + #if defined(SLI_SE_MAJOR_VERSION_ONE) #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h index 731a1ce3b..b13398f4c 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h @@ -156,6 +156,7 @@ sl_status_t sli_se_to_sl_status(sli_se_mailbox_response_t res); * @return * SL_STATUS_OK when successful, or else error code. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SE_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_se_lock_acquire(void); /***************************************************************************//** @@ -166,6 +167,7 @@ sl_status_t sli_se_lock_acquire(void); * @return * SL_STATUS_OK when successful, or else error code. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SE_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_se_lock_release(void); /***************************************************************************//** @@ -178,6 +180,7 @@ sl_status_t sli_se_lock_release(void); * @return * Status code, @ref sl_status.h. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SE_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx); #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h index 2024f5a6a..3155e3f51 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h +++ b/simplicity_sdk/platform/security/sl_component/se_manager/inc/sli_se_manager_mailbox.h @@ -123,6 +123,11 @@ extern "C" { #define SLI_SE_COMMAND_HASH 0x03000000UL #define SLI_SE_COMMAND_HASHUPDATE 0x03010000UL #define SLI_SE_COMMAND_HMAC 0x03020000UL +#if defined(_SILICON_LABS_32B_SERIES_3) + #define SLI_SE_COMMAND_HMAC_STREAMING_START 0x03040000UL + #define SLI_SE_COMMAND_HMAC_STREAMING_UPDATE 0x03050000UL + #define SLI_SE_COMMAND_HMAC_STREAMING_FINISH 0x03060000UL +#endif // _SILICON_LABS_32B_SERIES_3 #define SLI_SE_COMMAND_HASHFINISH 0x03030000UL #define SLI_SE_COMMAND_AES_ENCRYPT 0x04000000UL @@ -169,6 +174,11 @@ extern "C" { #define SLI_SE_COMMAND_READ_USER_CERT_SIZE 0x43FA0000UL #define SLI_SE_COMMAND_READ_USER_CERT 0x43FB0000UL + #if defined(_SILICON_LABS_32B_SERIES_3) + #define SLI_SE_COMMAND_GET_HOST_UPGRADE_FILE_VERSION 0x44000000UL + #define SLI_SE_COMMAND_SET_HOST_UPGRADE_FILE_VERSION 0x44010000UL + #endif // _SILICON_LABS_32B_SERIES_3 + #define SLI_SE_COMMAND_ENTER_ACTIVE_MODE 0x45000000UL #define SLI_SE_COMMAND_EXIT_ACTIVE_MODE 0x45010000UL @@ -192,11 +202,19 @@ extern "C" { #define SLI_SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL #define SLI_SE_COMMAND_INIT_AES_128_KEY 0xFF0B0001UL #if defined(_SILICON_LABS_32B_SERIES_3) - #define SLI_SE_COMMAND_ERASE_CODE_REGION 0xFF520000UL - #define SLI_SE_COMMAND_WRITE_CODE_REGION 0xFF560000UL - #define SLI_SE_COMMAND_ERASE_DATA_REGION 0xFF620000UL - #define SLI_SE_COMMAND_WRITE_DATA_REGION 0xFF630000UL - #define SLI_SE_COMMAND_GET_DATA_REGION_LOCATION 0xFF640000UL + #define SLI_SE_COMMAND_CONFIGURE_QSPI_REF_CLOCK 0xFF150000UL + #define SLI_SE_COMMAND_CONFIGURE_QSPI_REGS 0xFF160000UL + #define SLI_SE_COMMAND_GET_QSPI_FLPLL_CONFIG 0xFF170000UL + #define SLI_SE_COMMAND_APPLY_CODE_REGION_CONFIG 0xFF500000UL + #define SLI_SE_COMMAND_CLOSE_CODE_REGION 0xFF510000UL + #define SLI_SE_COMMAND_ERASE_CODE_REGION 0xFF520000UL + #define SLI_SE_COMMAND_GET_CODE_REGION_CONFIG 0xFF530000UL + #define SLI_SE_COMMAND_GET_CODE_REGION_VERSION 0xFF540000UL + #define SLI_SE_COMMAND_SET_ACTIVE_BANKED_CODE_REGION 0xFF550000UL + #define SLI_SE_COMMAND_WRITE_CODE_REGION 0xFF560000UL + #define SLI_SE_COMMAND_ERASE_DATA_REGION 0xFF620000UL + #define SLI_SE_COMMAND_WRITE_DATA_REGION 0xFF630000UL + #define SLI_SE_COMMAND_GET_DATA_REGION_LOCATION 0xFF640000UL #endif #endif // SLI_MAILBOX_COMMAND_SUPPORTED @@ -248,6 +266,14 @@ extern "C" { #define SLI_SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL /// Use SHA256 as hash algorithm #define SLI_SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL +#if defined(_SILICON_LABS_32B_SERIES_3) +/// Use SHA1 as hash algorithm for HMAC streaming operation + #define SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA1 0x00000700UL +/// Use SHA224 as hash algorithm for HMAC streaming operation + #define SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA224 0x00000800UL +/// Use SHA256 as hash algorithm for HMAC streaming operation + #define SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA256 0x00000900UL +#endif // _SILICON_LABS_32B_SERIES_3 /// Execute algorithm in ECB mode #define SLI_SE_COMMAND_OPTION_MODE_ECB 0x00000100UL @@ -283,6 +309,12 @@ extern "C" { #define SLI_SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL /// Use SHA512 as hash algorithm #define SLI_SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL +#if defined(_SILICON_LABS_32B_SERIES_3) +/// Use SHA384 as hash algorithm for HMAC streaming operation + #define SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA384 0x00000A00UL +/// Use SHA512 as hash algorithm for HMAC streaming operation + #define SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA512 0x00000B00UL +#endif // _SILICON_LABS_32B_SERIES_3 #endif // _SILICON_LABS_SECURITY_FEATURE_VAULT #endif // SLI_MAILBOX_COMMAND_SUPPORTED @@ -426,6 +458,7 @@ void sli_se_mailbox_command_add_output(sli_se_mailbox_command_t *command, sli_se * @param[in] parameter * Parameter to add. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SE_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) void sli_se_mailbox_command_add_parameter(sli_se_mailbox_command_t *command, uint32_t parameter); #if !defined(SLI_SE_MAILBOX_HOST_SYSTEM) @@ -442,6 +475,7 @@ void sli_se_mailbox_command_add_parameter(sli_se_mailbox_command_t *command, uin * @param[in] command * Pointer to a filled-out SE command structure. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SE_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) void sli_se_mailbox_execute_command(sli_se_mailbox_command_t *command); #endif //!defined(SLI_SE_MAILBOX_HOST_SYSTEM) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager.c b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager.c index f4733f737..01756c685 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager.c +++ b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager.c @@ -44,7 +44,7 @@ #endif #endif #if !defined(SLI_SE_MANAGER_HOST_SYSTEM) -#include "sli_se_manager_osal.h" +#include "sli_psec_osal.h" #endif #include @@ -55,6 +55,40 @@ // ----------------------------------------------------------------------------- // Locals +#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + #if defined(SL_SE_MANAGER_THREADING) +/// Priority to use for SEMBRX IRQ + #if defined(SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY) + #if (SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY >= (1U << __NVIC_PRIO_BITS) ) + #error Illegal SEMBRX priority level. + #endif + #if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + #if (SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY < (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8U - __NVIC_PRIO_BITS) ) ) + #error Illegal SEMBRX priority level. + #endif + #else + #if (SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY < CORE_ATOMIC_BASE_PRIORITY_LEVEL) + #error Illegal SEMBRX priority level. + #endif + #endif + #define SE_MANAGER_SEMBRX_IRQ_PRIORITY SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY + #else + #if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8U - __NVIC_PRIO_BITS) ) + #else + #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (CORE_ATOMIC_BASE_PRIORITY_LEVEL) + #endif + #endif + #else // defined(SL_SE_MANAGER_THREADING) +/// Priority to use for SEMBRX IRQ + #if defined(SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY) + #define SE_MANAGER_SEMBRX_IRQ_PRIORITY SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY + #else + #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (0) + #endif + #endif // defined(SL_SE_MANAGER_THREADING) +#endif // defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + #if defined(SL_SE_MANAGER_THREADING) \ || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) @@ -64,30 +98,13 @@ static volatile bool se_manager_initialized = false; #if defined(SL_SE_MANAGER_THREADING) // Lock mutex for synchronizing multiple threads calling into the // SE Manager API. -static se_manager_osal_mutex_t se_lock = { 0 }; - - #define SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START \ - int32_t kernel_lock_state = 0; \ - osKernelState_t kernel_state = se_manager_osal_kernel_get_state(); \ - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ - kernel_lock_state = se_manager_osal_kernel_lock(); \ - if (kernel_lock_state < 0) { \ - return SL_STATUS_FAIL; \ - } \ - } - - #define SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END \ - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ - if (se_manager_osal_kernel_restore_lock(kernel_lock_state) < 0) { \ - return SL_STATUS_FAIL; \ - } \ - } +static sli_psec_osal_lock_t se_lock = { 0 }; #endif // SL_SE_MANAGER_THREADING #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) // SE command completion. -static se_manager_osal_completion_t se_command_completion; +static sli_psec_osal_completion_t se_command_completion; // SE mailbox command response code. This value is read from the SEMAILBOX // in ISR in order to clear the command complete interrupt condition. static sli_se_mailbox_response_t se_manager_command_response = SLI_SE_RESPONSE_INTERNAL_ERROR; @@ -108,19 +125,23 @@ sl_status_t sl_se_init(void) #if defined (SL_SE_MANAGER_THREADING) \ || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + (void)se_manager_command_response; + #endif + #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START + SLI_PSEC_OSAL_KERNEL_CRITICAL_SECTION_START #endif if ( !se_manager_initialized ) { #if defined(SL_SE_MANAGER_THREADING) // Initialize SE lock - ret = se_manager_osal_init_mutex(&se_lock); + ret = sli_psec_osal_init_lock(&se_lock); #endif #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) if (ret == SL_STATUS_OK) { // Initialize command completion object. - ret = se_manager_osal_init_completion(&se_command_completion); + ret = sli_psec_osal_init_completion(&se_command_completion); if (ret == SL_STATUS_OK) { // Enable SE RX mailbox interrupt in NVIC, but not in SEMAILBOX // which will be enabled if the yield parameter in @@ -136,7 +157,7 @@ sl_status_t sl_se_init(void) } #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END + SLI_PSEC_OSAL_KERNEL_CRITICAL_SECTION_END #endif #endif // #if defined (SL_SE_MANAGER_THREADING) @@ -156,14 +177,14 @@ sl_status_t sl_se_deinit(void) || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START + SLI_PSEC_OSAL_KERNEL_CRITICAL_SECTION_START #endif if ( se_manager_initialized ) { // We need to exit the critical section in case the SE lock is held by a // thread, and we want to take it before de-initializing. #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END + SLI_PSEC_OSAL_KERNEL_CRITICAL_SECTION_END #endif // Acquire the SE lock to make sure no thread is executing SE commands @@ -178,13 +199,13 @@ sl_status_t sl_se_deinit(void) NVIC_ClearPendingIRQ(SEMBRX_IRQn); NVIC_DisableIRQ(SEMBRX_IRQn); // Free command completion object. - ret = se_manager_osal_free_completion(&se_command_completion); + ret = sli_psec_osal_free_completion(&se_command_completion); #endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION #if defined(SL_SE_MANAGER_THREADING) if (ret == SL_STATUS_OK) { // Free the SE lock mutex - ret = se_manager_osal_free_mutex(&se_lock); + ret = sli_psec_osal_free_lock(&se_lock); } #endif @@ -193,7 +214,7 @@ sl_status_t sl_se_deinit(void) } #if defined(SL_SE_MANAGER_THREADING) else { - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END + SLI_PSEC_OSAL_KERNEL_CRITICAL_SECTION_END } #endif @@ -208,7 +229,8 @@ sl_status_t sl_se_deinit(void) * Translate SE response codes to sl_status_t codes. * * @return - * Status code, @ref sl_status.h. + * Converted status code, their meaning is documented here @ref sl_status.h, + * Asserts and returns @c SL_STATUS_FAIL on unexpected response. ******************************************************************************/ sl_status_t sli_se_to_sl_status(sli_se_mailbox_response_t res) { @@ -253,7 +275,7 @@ sl_status_t sli_se_to_sl_status(sli_se_mailbox_response_t res) sl_status_t sli_se_lock_acquire(void) { #if defined(SL_SE_MANAGER_THREADING) - sl_status_t status = se_manager_osal_take_mutex(&se_lock); + sl_status_t status = sli_psec_osal_take_lock(&se_lock); #else sl_status_t status = SL_STATUS_OK; #endif @@ -264,6 +286,8 @@ sl_status_t sli_se_lock_acquire(void) #else BUS_RegBitWrite(&CMU->CLKEN1, _CMU_CLKEN1_SEMAILBOXHOST_SHIFT, 1); #endif + // Make sure the write to CMU->CLKEN1 is finished. + __DSB(); } #endif return status; @@ -283,7 +307,7 @@ sl_status_t sli_se_lock_release(void) #endif #endif #if defined(SL_SE_MANAGER_THREADING) - return se_manager_osal_give_mutex(&se_lock); + return sli_psec_osal_give_lock(&se_lock); #else return SL_STATUS_OK; #endif @@ -301,7 +325,7 @@ void SEMBRX_IRQHandler(void) // Check if the SE mailbox is the source of the interrupt. if (SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT) { // Signal SE mailbox completion. - status = se_manager_osal_complete(&se_command_completion); + status = sli_psec_osal_complete(&se_command_completion); EFM_ASSERT(status == SL_STATUS_OK); } // Get command response (clears interrupt condition in SEMAILBOX) @@ -340,13 +364,16 @@ sl_status_t sl_se_set_yield(sl_se_command_context_t *cmd_ctx, * Execute and wait for SE mailbox command to complete. * * @return - * Status code, @ref sl_status.h. + * One of the following status code, any other status codes relates to internal + * function errors see @ref sl_status.h for their meaning. + * - @c SL_STATUS_OK + * - @c SL_STATUS_INVALID_PARAMETER ******************************************************************************/ #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && !defined(SLI_SE_MANAGER_HOST_SYSTEM) sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) { - sl_status_t status; - sli_se_mailbox_response_t command_response; + sl_status_t status = SL_STATUS_FAIL; + sli_se_mailbox_response_t command_response = SLI_SE_RESPONSE_INTERNAL_ERROR; if (cmd_ctx == NULL) { return SL_STATUS_INVALID_PARAMETER; @@ -361,19 +388,25 @@ sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) // Execute SE mailbox command sli_se_mailbox_execute_command(&cmd_ctx->command); - #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \ + && !defined(_SILICON_LABS_32B_SERIES_3) if (cmd_ctx->yield) { // Enable SEMAILBOX RXINT interrupt sli_se_mailbox_enable_interrupt(SEMAILBOX_CONFIGURATION_RXINTEN); // Yield and Wait for the command completion signal - status = se_manager_osal_wait_completion(&se_command_completion, - SE_MANAGER_OSAL_WAIT_FOREVER); + status = sli_psec_osal_wait_completion(&se_command_completion, + SLI_PSEC_OSAL_WAIT_FOREVER); // Disable SEMAILBOX RXINT interrupt. sli_se_mailbox_disable_interrupt(SEMAILBOX_CONFIGURATION_RXINTEN); if (status != SL_STATUS_OK) { + #if (_SILICON_LABS_32B_SERIES == 3) + // Read the command handle word ( not used ) from the SEMAILBOX FIFO + SEMAILBOX_HOST->FIFO; + #endif // #if (_SILICON_LABS_32B_SERIES == 3) + sli_se_lock_release(); return status; } @@ -388,9 +421,18 @@ sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) #else // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + #if defined(_SILICON_LABS_32B_SERIES_3) + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + #endif + // Wait for command completion and get command response command_response = sli_se_mailbox_read_response(); + #if defined(_SILICON_LABS_32B_SERIES_3) + CORE_EXIT_ATOMIC(); + #endif + #endif // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) #if (_SILICON_LABS_32B_SERIES == 3) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c index 263de169b..2fc3ecca2 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c +++ b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c @@ -2880,4 +2880,267 @@ sl_status_t sl_se_poly1305_genkey_tag(sl_se_command_context_t *cmd_ctx, /** @} (end addtogroup sl_se) */ +#if defined(_SILICON_LABS_32B_SERIES_3) + +/***************************************************************************//** + * Prepare a HMAC streaming command context object to be used in subsequent + * HMAC streaming function calls. + ******************************************************************************/ +sl_status_t sl_se_hmac_multipart_starts(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *state_out, + size_t state_out_len) +{ + if (cmd_ctx == NULL || key == NULL || message == NULL || state_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + sl_status_t status = SL_STATUS_OK; + uint32_t command_word; + size_t hmac_state_len; + + switch (hash_type) { + case SL_SE_HASH_SHA1: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_START | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA1; + hmac_state_len = 20; + break; + + case SL_SE_HASH_SHA224: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_START | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA224; + hmac_state_len = 32; + break; + + case SL_SE_HASH_SHA256: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_START | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA256; + hmac_state_len = 32; + break; + + case SL_SE_HASH_SHA384: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_START | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA384; + hmac_state_len = 64; + break; + + case SL_SE_HASH_SHA512: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_START | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA512; + hmac_state_len = 64; + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + hmac_state_len += 8u; // adding 8 bytes for storing the HMAC multipart internal states + if (state_out_len < hmac_state_len) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, command_word); + + // Add key parameter to command. + sli_add_key_parameters(cmd_ctx, key, status); + + // Message size parameter. + sli_se_mailbox_command_add_parameter(se_cmd, message_len); + + // Key metadata. + sli_add_key_metadata(cmd_ctx, key, status); + + sli_add_key_input(cmd_ctx, key, status); + + // Data input. + sli_se_datatransfer_t in_data = SLI_SE_DATATRANSFER_DEFAULT(message, message_len); + sli_se_mailbox_command_add_input(se_cmd, &in_data); + + // Data output. + sli_se_datatransfer_t out_hmac_state = SLI_SE_DATATRANSFER_DEFAULT(state_out, hmac_state_len); + sli_se_mailbox_command_add_output(se_cmd, &out_hmac_state); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * This function feeds an input buffer into an ongoing HMAC computation. + ******************************************************************************/ +sl_status_t sl_se_hmac_multipart_update(sl_se_command_context_t *cmd_ctx, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *state_in_out, + size_t state_in_out_len) +{ + if (cmd_ctx == NULL || message == NULL || state_in_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + uint32_t command_word; + size_t hmac_state_len; + + switch (hash_type) { + case SL_SE_HASH_SHA1: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_UPDATE | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA1; + hmac_state_len = 20; + break; + + case SL_SE_HASH_SHA224: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_UPDATE | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA224; + hmac_state_len = 32; + break; + + case SL_SE_HASH_SHA256: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_UPDATE | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA256; + hmac_state_len = 32; + break; + + case SL_SE_HASH_SHA384: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_UPDATE | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA384; + hmac_state_len = 64; + break; + + case SL_SE_HASH_SHA512: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_UPDATE | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA512; + hmac_state_len = 64; + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + hmac_state_len += 8u; // adding 8 bytes for storing the HMAC multipart internal states + if (state_in_out_len != hmac_state_len) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, command_word); + + // Message size parameter. + sli_se_mailbox_command_add_parameter(se_cmd, message_len); + + // Data input. + sli_se_datatransfer_t in_out_hmac_state = SLI_SE_DATATRANSFER_DEFAULT(state_in_out, hmac_state_len); + sli_se_datatransfer_t in_data = SLI_SE_DATATRANSFER_DEFAULT(message, message_len); + sli_se_mailbox_command_add_input(se_cmd, &in_out_hmac_state); + sli_se_mailbox_command_add_input(se_cmd, &in_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Finish a HMAC streaming operation and return the resulting HMAC. + ******************************************************************************/ +sl_status_t sl_se_hmac_multipart_finish(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *state_in, + size_t state_in_len, + uint8_t *output, + size_t output_len) +{ + if (cmd_ctx == NULL || key == NULL || message == NULL || state_in == NULL || output == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + sl_status_t status = SL_STATUS_OK; + uint32_t command_word; + size_t hmac_state_len, hmac_len; + + switch (hash_type) { + case SL_SE_HASH_SHA1: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA1; + hmac_state_len = 20; + break; + + case SL_SE_HASH_SHA224: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA224; + hmac_state_len = 32; + break; + + case SL_SE_HASH_SHA256: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA256; + hmac_state_len = 32; + break; + + case SL_SE_HASH_SHA384: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA384; + hmac_state_len = 64; + break; + + case SL_SE_HASH_SHA512: + command_word = SLI_SE_COMMAND_HMAC_STREAMING_FINISH | SLI_SE_COMMAND_OPTION_HMAC_HASH_SHA512; + hmac_state_len = 64; + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + hmac_state_len += 8u; // adding 8 bytes for storing the HMAC multipart internal states + if (state_in_len != hmac_state_len) { + return SL_STATUS_INVALID_PARAMETER; + } + + switch (hash_type) { + case SL_SE_HASH_SHA1: + hmac_len = 20; + break; + + case SL_SE_HASH_SHA224: + hmac_len = 28; + break; + + case SL_SE_HASH_SHA256: + hmac_len = 32; + break; + + case SL_SE_HASH_SHA384: + hmac_len = 48; + break; + + case SL_SE_HASH_SHA512: + hmac_len = 64; + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + if (output_len < hmac_len) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, command_word); + + // Add key parameter to command. + sli_add_key_parameters(cmd_ctx, key, status); + + // Message size parameter. + sli_se_mailbox_command_add_parameter(se_cmd, message_len); + + // Key metadata. + sli_add_key_metadata(cmd_ctx, key, status); + + sli_add_key_input(cmd_ctx, key, status); + + // Data input. + sli_se_datatransfer_t state_in_data = SLI_SE_DATATRANSFER_DEFAULT(state_in, hmac_state_len); + sli_se_datatransfer_t in_data = SLI_SE_DATATRANSFER_DEFAULT(message, message_len); + sli_se_mailbox_command_add_input(se_cmd, &state_in_data); + sli_se_mailbox_command_add_input(se_cmd, &in_data); + + // Data output. + sli_se_datatransfer_t out_hmac = SLI_SE_DATATRANSFER_DEFAULT(output, hmac_len); + sli_se_mailbox_command_add_output(se_cmd, &out_hmac); + + return sli_se_execute_and_wait(cmd_ctx); +} + +#endif // defined(_SILICON_LABS_32B_SERIES_3) + #endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c index f0c224b68..0e8c591ea 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c +++ b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c @@ -134,7 +134,7 @@ sl_status_t sl_se_ecc_verify(sl_se_command_context_t *cmd_ctx, const unsigned char *signature, size_t signature_len) { - if (cmd_ctx == NULL || key == NULL || message == NULL || signature == NULL) { + if (cmd_ctx == NULL || key == NULL || (message == NULL && message_len != 0) || signature == NULL) { return SL_STATUS_INVALID_PARAMETER; } // Key needs to contain public key in order to verify signatures diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_util.c b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_util.c index 69f2d0d11..9ac2764ef 100644 --- a/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_util.c +++ b/simplicity_sdk/platform/security/sl_component/se_manager/src/sl_se_manager_util.c @@ -40,6 +40,8 @@ #include "em_system.h" #endif +#include "sl_core.h" + /// @addtogroup sl_se_manager /// @{ @@ -377,7 +379,9 @@ sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - // SE command structures + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + + // Get SE Version via SE Mailbox command sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_SE_VERSION); sli_se_datatransfer_t out_data = SLI_SE_DATATRANSFER_DEFAULT(version, sizeof(uint32_t)); @@ -386,6 +390,32 @@ sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, return sli_se_execute_and_wait(cmd_ctx); + #else + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + + // Read state of CMU_CLKEN0_SYSCFG + bool syscfg_clock_was_enabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + + // Read SE FW version from SYSCFG + *version = (uint32_t)(SYSCFG->ROOTSESWVERSION); + + if (!syscfg_clock_was_enabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + CORE_EXIT_CRITICAL(); + + #if defined(_SILICON_LABS_32B_SERIES_3) + // Omit compatibility information + *version = ((*version) & 0x00FFFFFF); + #endif + + return SL_STATUS_OK; + #endif + #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) sl_status_t status = SL_STATUS_OK; @@ -414,7 +444,6 @@ sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, #endif } - /***************************************************************************//** * Enables the debug lock for the part. ******************************************************************************/ @@ -925,7 +954,14 @@ sl_status_t sl_se_get_status(sl_se_command_context_t *cmd_ctx, // Update status object status->boot_status = output[4]; + + #if defined(_SILICON_LABS_32B_SERIES_3) + // Omit compatibility information + status->se_fw_version = output[5] & 0x00FFFFFF; + #else status->se_fw_version = output[5]; + #endif + status->host_fw_version = output[6]; // Decode debug status @@ -982,6 +1018,29 @@ sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, return SL_STATUS_INVALID_PARAMETER; } + #if defined(_SILICON_LABS_32B_SERIES_3) + /* TODO: Enable once register available: PSEC-5574 + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + + // Read state of CMU_CLKEN0_SYSCFG + bool syscfg_clock_was_enabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + + // Read SE FW version from SYSCFG + * version = (uint32_t)(((SYSCFG->ROOTSESWVERSION) & 0xFF000000) >> 24); + * version -= (uint32_t)((SYSCFG->ROMREVHW) & 0x000000FF); + + if (!syscfg_clock_was_enabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; + */ + return SL_STATUS_NOT_SUPPORTED; + #else // SE command structures sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_OTP_VERSION); @@ -990,6 +1049,7 @@ sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, sli_se_mailbox_command_add_output(se_cmd, &out_data); return sli_se_execute_and_wait(cmd_ctx); + #endif } #if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) @@ -1336,6 +1396,50 @@ sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx) #endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +#if defined(_SILICON_LABS_32B_SERIES_3) + +/***************************************************************************//** + * Reads back the stored upgrade file version. + ******************************************************************************/ +sl_status_t sl_se_get_upgrade_file_version(sl_se_command_context_t *cmd_ctx, + uint32_t *version) +{ + if ((cmd_ctx == NULL) || (version == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_GET_HOST_UPGRADE_FILE_VERSION); + + sli_se_datatransfer_t out_data + = SLI_SE_DATATRANSFER_DEFAULT(version, sizeof(uint32_t)); + sli_se_mailbox_command_add_output(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Records a new upgrade file version. + ******************************************************************************/ +sl_status_t sl_se_set_upgrade_file_version(sl_se_command_context_t *cmd_ctx, + uint32_t version) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + sli_se_mailbox_command_t *se_cmd = &cmd_ctx->command; + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_SET_HOST_UPGRADE_FILE_VERSION); + + sli_se_datatransfer_t in_data + = SLI_SE_DATATRANSFER_DEFAULT(&version, sizeof(uint32_t)); + sli_se_mailbox_command_add_input(se_cmd, &in_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +#endif // defined(_SILICON_LABS_32B_SERIES_3) + /// @} (end addtogroup sl_se) #endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal.h b/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal.h deleted file mode 100644 index c92b9487e..000000000 --- a/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal.h +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************/ /** - * @file - * @brief OS abstraction layer primitives for the SE Manager - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SE_MANAGER_OSAL_H -#define SE_MANAGER_OSAL_H - -#if !defined(SE_MANAGER_CONFIG_FILE) - #include "sl_se_manager_config.h" -#else - #include SE_MANAGER_CONFIG_FILE -#endif - -#if defined (SL_COMPONENT_CATALOG_PRESENT) - #include "sl_component_catalog.h" -#endif - -#include "sl_status.h" - -#if (defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT)) \ - && (defined(SL_SE_MANAGER_THREADING) \ - || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION)) -// Include CMSIS RTOS2 kernel abstraction layer: - #include "sli_se_manager_osal_cmsis_rtos2.h" -#else -// Include bare metal abstraction layer: - #include "sli_se_manager_osal_baremetal.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(SL_SE_MANAGER_THREADING) - -/***************************************************************************//** - * @brief Initialize a given mutex - * - * @param mutex Pointer to the mutex needing initialization - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_init_mutex(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Free a given mutex - * - * @param mutex Pointer to the mutex being freed - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_free_mutex(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Pend on a mutex - * - * @param mutex Pointer to the mutex being pended on - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_take_mutex(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Try to own a mutex without waiting - * - * @param mutex Pointer to the mutex being tested - * - * @return SL_STATUS_OK on success (= mutex successfully owned), error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_take_mutex_non_blocking(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Release a mutex - * - * @param mutex Pointer to the mutex being released - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_give_mutex(se_manager_osal_mutex_t *mutex); - -#endif // SL_SE_MANAGER_THREADING - -/***************************************************************************//** - * @brief Initialize a completion object. - * - * @param p_comp Pointer to an se_manager_osal_completion_t object allocated - * by the user. - * - * @return Status code, @ref sl_status.h. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_init_completion(se_manager_osal_completion_t *p_comp); - -/***************************************************************************//** - * @brief Free a completion object. - * - * @param p_comp Pointer to an se_manager_osal_completion_t object. - * - * @return Status code, @ref sl_status.h. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_free_completion(se_manager_osal_completion_t *p_comp); - -/***************************************************************************//** - * @brief Wait for completion event. - * - * @param p_comp Pointer to completion object which must be initialized by - * calling se_manager_osal_completion_init before calling this - * function. - * - * @param ticks Ticks to wait for the completion. - * Pass a value of SE_MANAGER_OSAL_WAIT_FOREVER in order to - * wait forever. - * Pass a value of SE_MANAGER_OSAL_NON_BLOCKING in order to - * return immediately. - * - * @return Status code, @ref sl_status.h. Typcally SL_STATUS_OK if success, - * or SL_STATUS_TIMEOUT if no completion within the given ticks. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_wait_completion(se_manager_osal_completion_t *p_comp, - int ticks); - -/***************************************************************************//** - * @brief Signal completion. - * - * @param p_comp Pointer to completion object which must be initialized by - * calling se_manager_osal_completion_init before calling this - * function. - * - * @return Status code, @ref sl_status.h. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_complete(se_manager_osal_completion_t *p_comp); - -#ifdef __cplusplus -} -#endif - -#endif // SE_MANAGER_OSAL_H diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal_baremetal.h b/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal_baremetal.h deleted file mode 100644 index 20880037a..000000000 --- a/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal_baremetal.h +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************/ /** - * @file - * @brief OS abstraction primitives for the SE Manager for bare metal apps - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SE_MANAGER_OSAL_BAREMETAL_H -#define SE_MANAGER_OSAL_BAREMETAL_H - -#include "sli_se_manager_features.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Defines - -/// In order to wait forever in blocking functions the user can pass the -/// following value. -#define SE_MANAGER_OSAL_WAIT_FOREVER (-1) -/// In order to return immediately in blocking functions the user can pass the -/// following value. -#define SE_MANAGER_OSAL_NON_BLOCKING (0) - -/// Priority to use for SEMBRX IRQ -#if defined(SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY) - #define SE_MANAGER_SEMBRX_IRQ_PRIORITY SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY -#else - #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (0) -#endif - -// ----------------------------------------------------------------------------- -// Typedefs - -/// Completion type used to wait for and signal end of operation. -typedef volatile unsigned int se_manager_osal_completion_t; - -/// SE manager mutex definition for Baremetal. -typedef volatile unsigned int se_manager_osal_mutex_t; - -// ----------------------------------------------------------------------------- -// Globals - -#if defined(SE_MANAGER_OSAL_TEST) -/// Global variable to keep track of ticks in bare metal test apps. -extern unsigned int sli_se_manager_test_ticks; -#endif - -// ----------------------------------------------------------------------------- -// Functions - -/// Initialize a completion object. -__STATIC_INLINE -sl_status_t se_manager_osal_init_completion(se_manager_osal_completion_t *p_comp) -{ - *p_comp = 0; - return SL_STATUS_OK; -} - -/// Free a completion object. -__STATIC_INLINE -sl_status_t se_manager_osal_free_completion(se_manager_osal_completion_t *p_comp) -{ - *p_comp = 0; - return SL_STATUS_OK; -} - -/// Wait for completion event. -__STATIC_INLINE sl_status_t -se_manager_osal_wait_completion(se_manager_osal_completion_t *p_comp, int ticks) -{ - int ret; - if (ticks == SE_MANAGER_OSAL_WAIT_FOREVER) { - while ( *p_comp == 0 ) { -#if defined(SE_MANAGER_OSAL_TEST) - sli_se_manager_test_ticks++; -#endif - } - *p_comp = 0; - ret = 0; - } else { - while ((*p_comp == 0) && (ticks > 0)) { - ticks--; -#if defined(SE_MANAGER_OSAL_TEST) - sli_se_manager_test_ticks++; -#endif - } - if (*p_comp == 1) { - *p_comp = 0; - ret = 0; - } else { - ret = SL_STATUS_TIMEOUT; - } - } - - return ret; -} - -/// Signal completion event. -__STATIC_INLINE -sl_status_t se_manager_osal_complete(se_manager_osal_completion_t* p_comp) -{ - *p_comp = 1; - return SL_STATUS_OK; -} - -#ifdef __cplusplus -} -#endif - -#endif // SE_MANAGER_OSAL_BAREMETAL_H diff --git a/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal_cmsis_rtos2.h b/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal_cmsis_rtos2.h deleted file mode 100644 index e048d401a..000000000 --- a/simplicity_sdk/platform/security/sl_component/se_manager/src/sli_se_manager_osal_cmsis_rtos2.h +++ /dev/null @@ -1,282 +0,0 @@ -/**************************************************************************/ /** - * @file - * @brief OS abstraction layer primitives for SE manager on CMSIS RTOS2 - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SE_MANAGER_OSAL_CMSIS_RTOS_H -#define SE_MANAGER_OSAL_CMSIS_RTOS_H - -#include "cmsis_os2.h" - -#if defined (SL_COMPONENT_CATALOG_PRESENT) - #include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) - #include "FreeRTOSConfig.h" - #if (configSUPPORT_STATIC_ALLOCATION == 1) - #include "FreeRTOS.h" // StaticSemaphore_t - #include - #endif -#else - #include "sl_core.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Defines - -/// In order to wait forever in blocking functions the user can pass the -/// following value. -#define SE_MANAGER_OSAL_WAIT_FOREVER (osWaitForever) -/// In order to return immediately in blocking functions the user can pass the -/// following value. -#define SE_MANAGER_OSAL_NON_BLOCKING (0) - -/// Priority to use for SEMBRX IRQ -#if defined(SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY) - #if (SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY >= (1U << __NVIC_PRIO_BITS) ) - #error Illegal SEMBRX priority level. - #endif - #if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) - #if (SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY < (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8U - __NVIC_PRIO_BITS) ) ) - #error Illegal SEMBRX priority level. - #endif - #else - #if (SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY < CORE_ATOMIC_BASE_PRIORITY_LEVEL) - #error Illegal SEMBRX priority level. - #endif - #endif - #define SE_MANAGER_SEMBRX_IRQ_PRIORITY SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY -#else - #if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) - #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8U - __NVIC_PRIO_BITS) ) - #else - #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (CORE_ATOMIC_BASE_PRIORITY_LEVEL) - #endif -#endif - -/// Determine if executing at interrupt level on ARM Cortex-M. -#define RUNNING_AT_INTERRUPT_LEVEL (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) - -// ----------------------------------------------------------------------------- -// Typedefs - -/// Completion object used to wait for and signal end of an operation. -typedef struct se_manager_osal_completion { -#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) - osSemaphoreAttr_t semaphore_attr; - StaticSemaphore_t static_sem_object; -#endif - osSemaphoreId_t semaphore_ID; -} se_manager_osal_completion_t; - -/// SE manager mutex definition for CMSIS RTOS2. -typedef struct se_manager_osal_mutex { -#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) - osMutexAttr_t mutex_attr; - StaticSemaphore_t static_sem_object; -#endif - osMutexId_t mutex_ID; -} se_manager_osal_mutex_t; - -// ----------------------------------------------------------------------------- -// Functions - -/// Initialize a mutex object. -__STATIC_INLINE -sl_status_t se_manager_osal_init_mutex(se_manager_osal_mutex_t *mutex) -{ - if (mutex == NULL) { - return SL_STATUS_FAIL; - } - -#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) - // Zeroize all members of the mutex attributes object and setup the static control block. - memset(&mutex->mutex_attr, 0, sizeof(mutex->mutex_attr)); - mutex->mutex_attr.cb_mem = &mutex->static_sem_object; - mutex->mutex_attr.cb_size = sizeof(mutex->static_sem_object); - mutex->mutex_ID = osMutexNew(&mutex->mutex_attr); -#else - mutex->mutex_ID = osMutexNew(NULL); -#endif - - return (mutex->mutex_ID == NULL ? SL_STATUS_FAIL : SL_STATUS_OK); -} - -/// Free a mutex object. -__STATIC_INLINE -sl_status_t se_manager_osal_free_mutex(se_manager_osal_mutex_t *mutex) -{ - if (mutex == NULL) { - return SL_STATUS_FAIL; - } - - osStatus_t status = osMutexDelete(mutex->mutex_ID); - return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); -} - -/// Acquire ownership of a mutex. If busy, wait until available. -__STATIC_INLINE -sl_status_t se_manager_osal_take_mutex(se_manager_osal_mutex_t *mutex) -{ - if (mutex == NULL) { - return SL_STATUS_FAIL; - } - - osStatus_t status = osOK; - if (osKernelGetState() == osKernelRunning) { - status = osMutexAcquire(mutex->mutex_ID, SE_MANAGER_OSAL_WAIT_FOREVER); - } - return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); -} - -/// Try to acquire ownership of a mutex without waiting. -__STATIC_INLINE -sl_status_t se_manager_osal_take_mutex_non_blocking(se_manager_osal_mutex_t *mutex) -{ - if (mutex == NULL) { - return SL_STATUS_FAIL; - } - - osStatus_t status = osOK; - if (osKernelGetState() == osKernelRunning) { - status = osMutexAcquire(mutex->mutex_ID, SE_MANAGER_OSAL_NON_BLOCKING); - } - return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); -} - -/// Release ownership of a mutex. -__STATIC_INLINE -sl_status_t se_manager_osal_give_mutex(se_manager_osal_mutex_t *mutex) -{ - if (mutex == NULL) { - return SL_STATUS_FAIL; - } - - osStatus_t status = osOK; - if (osKernelGetState() == osKernelRunning) { - status = osMutexRelease(mutex->mutex_ID); - } - return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); -} - -/// Initialize a completion object. -__STATIC_INLINE sl_status_t -se_manager_osal_init_completion(se_manager_osal_completion_t *p_comp) -{ - if (p_comp == NULL) { - return SL_STATUS_FAIL; - } - -#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) - // Zeroize all members of the semaphore attributes object and setup the static control block. - memset(&p_comp->semaphore_attr, 0, sizeof(p_comp->semaphore_attr)); - p_comp->semaphore_attr.cb_mem = &p_comp->static_sem_object; - p_comp->semaphore_attr.cb_size = sizeof(p_comp->static_sem_object); - p_comp->semaphore_ID = osSemaphoreNew(1u, 0u, &p_comp->semaphore_attr); -#else - p_comp->semaphore_ID = osSemaphoreNew(1u, 0u, NULL); -#endif - - return (p_comp->semaphore_ID == NULL ? SL_STATUS_FAIL : SL_STATUS_OK); -} - -/// Free a completion object. -__STATIC_INLINE sl_status_t -se_manager_osal_free_completion(se_manager_osal_completion_t *p_comp) -{ - if (p_comp == NULL) { - return SL_STATUS_FAIL; - } - - osStatus_t status = osSemaphoreDelete(p_comp->semaphore_ID); - return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); -} - -// Wait for a completion object to be completed. -__STATIC_INLINE sl_status_t -se_manager_osal_wait_completion(se_manager_osal_completion_t *p_comp, int ticks) -{ - if (p_comp == NULL) { - return SL_STATUS_FAIL; - } - - osStatus_t status = osOK; - if (osKernelGetState() == osKernelRunning) { - status = osSemaphoreAcquire(p_comp->semaphore_ID, - (uint32_t)ticks); - } - return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); -} - -// Complete a completion object. -__STATIC_INLINE sl_status_t -se_manager_osal_complete(se_manager_osal_completion_t* p_comp) -{ - if (p_comp == NULL) { - return SL_STATUS_FAIL; - } - - osStatus_t status = osOK; - osKernelState_t state = osKernelGetState(); - if ((state == osKernelRunning) || (state == osKernelLocked)) { - status = osSemaphoreRelease(p_comp->semaphore_ID); - } - return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); -} - -// Lock the RTOS Kernel scheduler. -__STATIC_INLINE int32_t -se_manager_osal_kernel_lock(void) -{ - return osKernelLock(); -} - -// Restore the RTOS Kernel scheduler lock state. -__STATIC_INLINE int32_t -se_manager_osal_kernel_restore_lock(int32_t lock) -{ - return osKernelRestoreLock(lock); -} - -// Current RTOS kernel state. -__STATIC_INLINE osKernelState_t -se_manager_osal_kernel_get_state(void) -{ - return osKernelGetState(); -} - -#ifdef __cplusplus -} -#endif - -#endif // SE_MANAGER_OSAL_CMSIS_RTOS_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_acceleration.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_acceleration.h new file mode 100644 index 000000000..4b597e480 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_acceleration.h @@ -0,0 +1,486 @@ +/***************************************************************************//** + * @file + * @brief Mbed TLS device acceleration capabilities. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_MBEDTLS_ACCELERATION_H +#define SLI_MBEDTLS_ACCELERATION_H + +// This condition makes it possible to disable alt-plugins for the classic +// Mbed TLS APIs (overriding the user-exposed config option). This is notably +// used on the NS side of TrustZone-enabled applications. +#if !defined(NO_CRYPTO_ACCELERATION) + +// ----------------------------------------------------------------------------- +// Acceleration enabling defines + +/** + * \def MBEDTLS_AES_ALT + * + * Enable hardware acceleration for the AES block cipher modes through + * the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/crypto_aes.c for devices with CRYPTO, + * sl_mbedtls_support/src/se_aes.c for devices with HSE, + * sl_mbedtls_support/src/cryptoacc_aes.c for devices with CRYPTOACC, + * sl_mbedtls_support/src/aes_aes.c for devices with AES + * + * See \ref MBEDTLS_AES_C for more information. + */ +#if defined(_SILICON_LABS_32B_SERIES) + #define MBEDTLS_AES_ALT +#endif +#if defined(CRYPTOACC_PRESENT) || defined(SEMAILBOX_PRESENT) + #define AES_192_SUPPORTED +#endif + +/** + * \def MBEDTLS_CCM_ALT + * + * Enable hardware acceleration of CCM through mbed TLS APIs. + * Not enabled when PSA Crypto is present in the build together with the PSA driver for CCM, + * as that would preclude software fallback for cases where the hardware capabilites do not + * cover the full potential usage of the PSA Driver API + * + * Module: sl_mbedtls_support/src/mbedtls_ccm.c for all devices, plus: + * - sl_psa_driver/src/sli_se_transparent_driver_aead.c and sl_psa_driver/src/sli_se_driver_aead.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c for devices with CRYPTOACC + * + * Requires: \ref MBEDTLS_AES_C and \ref MBEDTLS_CCM_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_CCM_C for more information. + */ +#if defined(CRYPTOACC_PRESENT) || defined(SEMAILBOX_PRESENT) +// Remove this when full multipart support is present in the CCM ALT driver +// Todo: remove guard when [PSEC-1954][PSEC-2109][PSEC-3133] are done + #if !(defined(MBEDTLS_PSA_CRYPTO_DRIVERS)) + #define MBEDTLS_CCM_ALT + #endif +#endif + +/** + * \def MBEDTLS_CMAC_ALT + * + * Enable hardware acceleration CMAC through mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_cmac.c for all devices, plus: + * - sl_psa_driver/src/sli_se_transparent_driver_mac.c and sl_psa_driver/src/sli_se_driver_mac.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c for devices with CRYPTOACC + * + * Requires: \ref MBEDTLS_AES_C and \ref MBEDTLS_CMAC_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_CMAC_C for more information. + */ +#if defined(CRYPTOACC_PRESENT) || defined(SEMAILBOX_PRESENT) + #define MBEDTLS_CMAC_ALT +#endif + +/** + * \def MBEDTLS_GCM_ALT + * + * Enable hardware acceleration GCM. + * + * Module: sl_mbedtls_support/src/se_gcm.c for devices with HSE, + * sl_mbedtls_support/src/cryptoacc_gcm.c for devices with CRYPTOACC + * + * Requires: \ref MBEDTLS_GCM_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_GCM_C for more information. + */ +#if defined(CRYPTOACC_PRESENT) || (defined(SEMAILBOX_PRESENT)) + #define MBEDTLS_GCM_ALT +#endif + +/** + * \def MBEDTLS_SHA1_ALT + * + * Enable hardware acceleration for the SHA1 cryptographic hash algorithm + * through the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_sha.c for all devices, plus: + * - sl_psa_driver/src/sli_se_transparent_driver_hash.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c for devices with CRYPTOACC + * + * Caller: library/mbedtls_md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509write_crt.c + * + * Requires: \ref MBEDTLS_SHA1_C and (CRYPTO_PRESENT or CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_SHA1_C for more information. + */ +#if defined(CRYPTOACC_PRESENT) || defined(SEMAILBOX_PRESENT) + #define MBEDTLS_SHA1_ALT +#endif + +/** + * \def MBEDTLS_SHA256_ALT + * + * Enable hardware acceleration for the SHA-224 and SHA-256 cryptographic + * hash algorithms through the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_sha.c for all devices, plus: + * - sl_psa_driver/src/sli_se_transparent_driver_hash.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c for devices with CRYPTOACC + * + * Caller: library/entropy.c + * library/mbedtls_md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * Requires: \ref MBEDTLS_SHA256_C and (CRYPTO_PRESENT or CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_SHA256_C for more information. + */ +#if defined(CRYPTOACC_PRESENT) || defined(SEMAILBOX_PRESENT) + #define MBEDTLS_SHA256_ALT +#endif + +/** + * \def MBEDTLS_SHA512_ALT + * + * Enable hardware acceleration for the SHA-384 and SHA-512 cryptographic + * hash algorithms through the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_sha.c + * sl_psa_driver/src/sli_se_transparent_driver_hash.c + * + * Requires: \ref MBEDTLS_SHA512_C + * + * See MBEDTLS_SHA512_C for more information. + */ +#if defined(SEMAILBOX_PRESENT) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define MBEDTLS_SHA512_ALT +#endif + +/** + * \def MBEDTLS_ECP_INTERNAL_ALT + * \def ECP_SHORTWEIERSTRASS + * \def MBEDTLS_ECP_ADD_MIXED_ALT + * \def MBEDTLS_ECP_DOUBLE_JAC_ALT + * \def MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT + * \def MBEDTLS_ECP_NORMALIZE_JAC_ALT + * + * Enable hardware acceleration for the elliptic curve over GF(p) library + * in mbed TLS. This accelerates the raw arithmetic operations. + * + * Module: sl_mbedtls_support/src/crypto_ecp.c + * + * Caller: library/ecp.c + * + * Requires: \ref MBEDTLS_BIGNUM_C, \ref MBEDTLS_ECP_C and at least one + * MBEDTLS_ECP_DP_XXX_ENABLED and CRYPTO_PRESENT + */ +#if defined(CRYPTO_PRESENT) \ + && (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED)) + #define MBEDTLS_ECP_INTERNAL_ALT + #define ECP_SHORTWEIERSTRASS + #define MBEDTLS_ECP_ADD_MIXED_ALT + #define MBEDTLS_ECP_DOUBLE_JAC_ALT + #define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT + #define MBEDTLS_ECP_NORMALIZE_JAC_ALT + #define MBEDTLS_ECP_RANDOMIZE_JAC_ALT +#endif + +/** + * \def MBEDTLS_ECDH_COMPUTE_SHARED_ALT + * \def MBEDTLS_ECDH_GEN_PUBLIC_ALT + * \def MBEDTLS_ECDSA_GENKEY_ALT + * \def MBEDTLS_ECDSA_SIGN_ALT + * \def MBEDTLS_ECDSA_VERIFY_ALT + * + * Enable hardware acceleration for certain ECC operations. + * + * Module: sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c for all devices, plus: + * - sl_psa_driver/src/sli_se_driver_signature.c and sl_psa_driver/src/sli_se_driver_key_management.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c and sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c for devices with CRYPTOACC + * + * Requires: \ref MBEDTLS_ECP_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See \ref MBEDTLS_ECP_C for more information. + */ +#if defined(CRYPTOACC_PRESENT) +#if !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) ) + #define MBEDTLS_ECDH_COMPUTE_SHARED_ALT + #define MBEDTLS_ECDH_GEN_PUBLIC_ALT +#endif // #if !( defined(MBEDTLS_ECP_DP_XXX_ENABLED) ... + +#if !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) ) + #define MBEDTLS_ECDSA_GENKEY_ALT + #define MBEDTLS_ECDSA_VERIFY_ALT + #if !defined(MBEDTLS_ECDSA_DETERMINISTIC) + #define MBEDTLS_ECDSA_SIGN_ALT + #endif +#endif // #if !( defined(MBEDTLS_ECP_DP_XXX_ENABLED) ... + +#endif /* CRYPTOACC */ + +#if defined(SEMAILBOX_PRESENT) + +#if !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + +/* Do not enable the ECDH and/or ECDSA ALT implementations when one or more + * non-accelerated curves are included, then the application needs to + * use the standard mbedTLS library. */ + + #if !( (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) \ + && (defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED))) + #define MBEDTLS_ECDH_GEN_PUBLIC_ALT + #define MBEDTLS_ECDH_COMPUTE_SHARED_ALT + #endif + + #if !( (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) \ + && (defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) ) ) + #define MBEDTLS_ECDSA_GENKEY_ALT + #if !defined(MBEDTLS_ECDSA_DETERMINISTIC) + #define MBEDTLS_ECDSA_SIGN_ALT + #endif + #define MBEDTLS_ECDSA_VERIFY_ALT + #endif + +#endif // #if !defined(MBEDTLS_ECP_DP_XXXX_ENABLED) && ... + +/** + * \def MBEDTLS_ECJPAKE_ALT + * + * Enable hardware acceleration JPAKE. + * + * Module: sl_mbedtls_support/src/se_jpake.c + * + * Requires: \ref MBEDTLS_ECJPAKE_C (SEMAILBOX_PRESENT) + * + * See \ref MBEDTLS_ECJPAKE_C for more information. + */ +#define MBEDTLS_ECJPAKE_ALT + +#endif /* SEMAILBOX_PRESENT */ + +/** + * \def MBEDTLS_ENTROPY_ADC_PRESENT + * + * Decode if device supports retrieving entropy data from the ADC + * incorporated on devices from Silicon Labs. + * + * Requires ADC_PRESENT && _ADC_SINGLECTRLX_VREFSEL_VENTROPY && + * _SILICON_LABS_32B_SERIES_1 + */ +#if defined(ADC_PRESENT) \ + && defined(_ADC_SINGLECTRLX_VREFSEL_VENTROPY) \ + && defined(_SILICON_LABS_32B_SERIES_1) +#define MBEDTLS_ENTROPY_ADC_PRESENT +#endif + +/** + * \def MBEDTLS_TRNG_PRESENT + * + * Determine whether mbedTLS supports the TRNG (if present) on the device. + * + * Requires TRNG_PRESENT and not _SILICON_LABS_GECKO_INTERNAL_SDID_95 (xg14) + */ +#if defined(TRNG_PRESENT) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#undef MBEDTLS_TRNG_PRESENT +#define MBEDTLS_TRNG_PRESENT +#endif + +/** + * \def MBEDTLS_ENTROPY_RAIL_PRESENT + * + * Determine whether mbedTLS supports RAIL entropy on the device. + * This is currently only available on a few series-1 devices + * where there is no functional TRNG. + * + * Requires _EFR_DEVICE and one of + * _SILICON_LABS_GECKO_INTERNAL_SDID_80 + * _SILICON_LABS_GECKO_INTERNAL_SDID_89 + * _SILICON_LABS_GECKO_INTERNAL_SDID_95 + */ +#if defined(_EFR_DEVICE) \ + && (defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) ) +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#undef MBEDTLS_ENTROPY_RAIL_PRESENT +#define MBEDTLS_ENTROPY_RAIL_PRESENT +#endif +#endif + +/* Default ECC configuration for Silicon Labs devices: */ + +/* Save RAM by adjusting to our exact needs */ +#ifndef MBEDTLS_MPI_MAX_SIZE +#define MBEDTLS_MPI_MAX_SIZE 32 // 384 bits is 48 bytes +#endif + +/* + Set MBEDTLS_ECP_WINDOW_SIZE to configure + ECC point multiplication window size, see ecp.h: + 2 = Save RAM at the expense of speed + 3 = Improve speed at the expense of RAM + 4 = Optimize speed at the expense of RAM + */ +#define MBEDTLS_ECP_WINDOW_SIZE 2 +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 0 + +#if defined(MBEDTLS_ECP_C) +/* First section: devices with ECP hardware acceleration enabled */ +#if defined(MBEDTLS_ECP_INTERNAL_ALT) +/* When the internal ECP implementation is overridden, apply optimisation + * only when it benefits us for curves we can't accelerate. */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_ECP_NIST_OPTIM +#endif /* Non-accelerated SECP R1 curves requested */ +/* If only accelerated curves are requested, and no non-accelerated ones, + * we can turn on the NO_FALLBACK flag to dead-strip a whole lot of ECC + * math software implementation. */ +#if (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) ) \ + && !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE448_ENABLED)) +#define MBEDTLS_ECP_NO_FALLBACK +#endif /* Only ECP-hardware-accelerated curves requested */ +/* Second section: devices with ECDSA / ECDH hardware acceleration (without ECP) */ +#elif defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ + || defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + || defined(MBEDTLS_ECDSA_GENKEY_ALT) \ + || defined(MBEDTLS_ECDSA_SIGN_ALT) \ + || defined(MBEDTLS_ECDSA_VERIFY_ALT) \ +/* When the upper layers calling into ECP_C are overridden, apply optimisation + * only when it benefits us for curves we can't accelerate. */ +#if (defined(SEMAILBOX_PRESENT) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) ) \ + || defined(CRYPTOACC_PRESENT) +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || (defined(MBEDTLS_ECDSA_DETERMINISTIC) \ + && (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED))) +#define MBEDTLS_ECP_NIST_OPTIM +#endif /* Non-accelerated SECP R1 curves requested */ +#endif /* Devices not implementing the full suite of SECP R1 curves */ +/* Third section: configurations without any ECP/ECC acceleration at all */ +#else +/* When there's no ECC acceleration at all, apply optimisation always when + * applicable curves are present. */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_ECP_NIST_OPTIM +#endif /* Software-optimisable curve requested */ +#endif /* Different acceleration constellations */ +#endif /* MBEDTLS_ECP_C */ + +/* + Set max CTR-DRBG seed input size to reasonable default in order to reduce + stack usage when using CTR-DRBG. + NOTE: + Due to existing dependencies we need to keep the setting of + MBEDTLS_CTR_DRBG_MAX_SEED_INPUT here. However this is subject to be moved + later, to sl_mbedtls_config.h or mbedtls_config_autogen.h in order to be more + practical for configuration. + */ +#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT) +#if !(defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ + && defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + && defined(MBEDTLS_ECDSA_GENKEY_ALT) \ + && defined(MBEDTLS_ECDSA_SIGN_ALT) \ + && defined(MBEDTLS_ECDSA_VERIFY_ALT)) +/* + If any of ECDH and/or ECDSA ALT is/are not enabled, then the ecp_mul_xxx() + functions will seed the internal drbg (for randomization of projective + coordinates) with the private key of size corresponding to the curve + hence we will need to adjust: + */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +// For key size 521 bits (=66 bytes) add 66 - 32 (256bits default) = 34 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 66 - 32) +#elif defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +// For key size 512 bits (=64 bytes) add 64 - 32 (256bits default) = 32 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 64 - 32) +#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +// For key size 448 bits (=56 bytes) add 56 - 32 (256bits default) = 24 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 56 - 32) +#elif defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +// For key size 384 bits (=48 bytes) add 48 - 32 (256bits default) = 16 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 48 - 32) +#elif defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +// For key size 384 bits (=48 bytes) add 48 - 32 (256bits default) = 16 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 48 - 32) +#else +// Default value to support curve sizes up to 256 bits ( 32 bytes ) +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2) +#endif +#endif +#endif + +#endif // !NO_CRYPTO_ACCELERATION + +#endif // SLI_MBEDTLS_ACCELERATION_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_omnipresent.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_omnipresent.h new file mode 100644 index 000000000..ea2a16135 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_omnipresent.h @@ -0,0 +1,155 @@ +/***************************************************************************//** + * @file + * @brief Mbed TLS 'omnipresent' config content. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_MBEDTLS_OMIPRESENT_H +#define SLI_MBEDTLS_OMIPRESENT_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +#if !defined(SL_CATALOG_SE_CPC_PRIMARY_PRESENT) + #include "em_device.h" +#endif + +// ----------------------------------------------------------------------------- +// Non-volatile seed function headers + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) + +// Provide the NV seed function signatures since we have no specific header +// for them. + +#include + +int sli_nv_seed_read(unsigned char *buf, size_t buf_len); +int sli_nv_seed_write(unsigned char *buf, size_t buf_len); + +#endif // MBEDTLS_PLATFORM_NV_SEED_ALT + +// ----------------------------------------------------------------------------- +// Platform macros + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && defined(MBEDTLS_PLATFORM_FREE_MACRO) + +// By default MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO are +// defined in mbedtls_platform_dynamic_memory_allocation_config_default.slcc. +// Alternative implementations can configure MBEDTLS_PLATFORM_CALLOC_MACRO and +// MBEDTLS_PLATFORM_FREE_MACRO to use other platform specific implementations. +// Alternatively some use cases may select runtime initialisation in the +// application by explicitly calling mbedtls_platform_set_calloc_free() by +// selecting mbedtls_platform_dynamic_memory_allocation_config_init_runtime. + +#include + +extern void *MBEDTLS_PLATFORM_CALLOC_MACRO(size_t n, size_t size); +extern void MBEDTLS_PLATFORM_FREE_MACRO(void *ptr); + +#endif // MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO + +// ----------------------------------------------------------------------------- +// Device differentiation logic + +#if defined(CRYPTO_PRESENT) + + #define SLI_MBEDTLS_DEVICE_S1 + + #if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + #define SLI_MBEDTLS_DEVICE_S1_WITH_TRNG + #endif + + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +// The TRNG may possibly not work depending on the die revision. + #define SLI_MBEDTLS_DEVICE_S1_WITH_TRNG_ERRATA + #endif + +#elif defined(SEMAILBOX_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2) + + #define SLI_MBEDTLS_DEVICE_S2 + #define SLI_MBEDTLS_DEVICE_HSE + + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + #define SLI_MBEDTLS_DEVICE_SE_V1 + #define SLI_MBEDTLS_DEVICE_HSE_V1 + #else + #define SLI_MBEDTLS_DEVICE_SE_V2 + #define SLI_MBEDTLS_DEVICE_HSE_V2 + #endif + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH + #else + #define SLI_MBEDTLS_DEVICE_HSE_VAULT_MID + #endif + +#elif defined(SEMAILBOX_PRESENT) && defined(_SILICON_LABS_32B_SERIES_3) + + #define SLI_MBEDTLS_DEVICE_S3 + #define SLI_MBEDTLS_DEVICE_HC + + #define SLI_MBEDTLS_DEVICE_HSE + #define SLI_MBEDTLS_DEVICE_SE_V2 + #define SLI_MBEDTLS_DEVICE_HSE_V2 + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH + #else + #define SLI_MBEDTLS_DEVICE_HSE_VAULT_MID + #endif + +#elif defined(CRYPTOACC_PRESENT) + + #define SLI_MBEDTLS_DEVICE_S2 + #define SLI_MBEDTLS_DEVICE_VSE + + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + #define SLI_MBEDTLS_DEVICE_SE_V1 + #define SLI_MBEDTLS_DEVICE_VSE_V1 + #else + #define SLI_MBEDTLS_DEVICE_SE_V2 + #define SLI_MBEDTLS_DEVICE_VSE_V2 + #endif + +#elif defined(SL_CATALOG_SE_CPC_PRIMARY_PRESENT) + + #define SLI_MBEDTLS_DEVICE_S2 + #define SLI_MBEDTLS_DEVICE_HSE + +// #define SLI_MBEDTLS_DEVICE_SE_V1 +// #define SLI_MBEDTLS_DEVICE_SE_V2 +// #define SLI_MBEDTLS_DEVICE_HSE_V1 +// #define SLI_MBEDTLS_DEVICE_HSE_V2 +// #define SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH +// #define SLI_MBEDTLS_DEVICE_HSE_VAULT_MID + +#elif defined(SLI_CRYPTOACC_PRESENT_SI91X) + #define SLI_MBEDTLS_DEVICE_SI91X +#endif + +#endif // SLI_MBEDTLS_OMIPRESENT_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h new file mode 100644 index 000000000..2ff07ea8f --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h @@ -0,0 +1,125 @@ +/***************************************************************************//** + * @file + * @brief PSA Crypto device acceleration capabilities. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_ACCELERATION_H +#define SLI_PSA_ACCELERATION_H + +// ------------------------------------- +// Hash + +#define MBEDTLS_PSA_ACCEL_ALG_SHA_1 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_224 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_256 + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined (SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ALG_SHA_384 + #define MBEDTLS_PSA_ACCEL_ALG_SHA_512 +#endif + +// ------------------------------------- +// Cipher + +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_AES +#define MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CTR + +#if !defined(SLI_MBEDTLS_DEVICE_SI91X) +#define MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7 +#define MBEDTLS_PSA_ACCEL_ALG_CFB +#define MBEDTLS_PSA_ACCEL_ALG_OFB +#endif + +#if (defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) && !defined(_SILICON_LABS_32B_SERIES_3)) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20 +#endif + +// ------------------------------------- +// AEAD + +#define MBEDTLS_PSA_ACCEL_ALG_GCM +#define MBEDTLS_PSA_ACCEL_ALG_CCM + +#if (defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) && !defined(_SILICON_LABS_32B_SERIES_3)) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305 +#endif + +// ------------------------------------- +// MAC + +#define MBEDTLS_PSA_ACCEL_ALG_CMAC + +#define MBEDTLS_PSA_ACCEL_ALG_HMAC + +#if defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define MBEDTLS_PSA_ACCEL_ALG_CBC_MAC +#endif + +// ------------------------------------- +// Elliptic curves + +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY +#define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_192 +#define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256 + +#if (defined(SLI_MBEDTLS_DEVICE_S2) && !defined(SLI_MBEDTLS_DEVICE_HSE_V1)) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) && !defined(_SILICON_LABS_32B_SERIES_3) + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384 + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + #define MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_V1) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) \ + || defined(SLI_MBEDTLS_DEVICE_HSE_V2) + #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) && !defined(_SILICON_LABS_32B_SERIES_3) + #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448 +#endif + +// ------------------------------------- +// Key agreement + +#define MBEDTLS_PSA_ACCEL_ALG_ECDH + +// ------------------------------------- +// Signature + +#define MBEDTLS_PSA_ACCEL_ALG_ECDSA + +#endif // SLI_PSA_ACCELERATION_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_tfm_translation.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_tfm_translation.h new file mode 100644 index 000000000..162e2fc48 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_tfm_translation.h @@ -0,0 +1,95 @@ +/***************************************************************************//** + * @file + * @brief PSA Crypto to TFM config option translation. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_TFM_TRANSLATION_H +#define SLI_PSA_TFM_TRANSLATION_H + +// Asymmetric Crypt module (RSA is not supported) +#define TFM_CRYPTO_ASYM_ENCRYPT_MODULE_DISABLED + +// HASH module +#if !defined(PSA_WANT_ALG_SHA_1) \ + && !defined(PSA_WANT_ALG_SHA_224) \ + && !defined(PSA_WANT_ALG_SHA_256) \ + && !defined(PSA_WANT_ALG_SHA_384) \ + && !defined(PSA_WANT_ALG_SHA_512) \ + && !defined(PSA_WANT_ALG_MD5) + #define TFM_CRYPTO_HASH_MODULE_DISABLED +#endif + +// AEAD module +#if !defined(PSA_WANT_ALG_CCM) \ + && !defined(PSA_WANT_ALG_GCM) \ + && !defined(PSA_WANT_ALG_CHACHA20_POLY1305) + #define TFM_CRYPTO_AEAD_MODULE_DISABLED +#endif + +// Asymmetric Sign module +#if !defined(PSA_WANT_ALG_ECDSA) \ + && !defined(PSA_WANT_ALG_EDDSA) \ + && !defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) + #define TFM_CRYPTO_ASYM_SIGN_MODULE_DISABLED +#endif + +// Cipher module +#if !defined(PSA_WANT_ALG_CFB) \ + && !defined(PSA_WANT_ALG_CTR) \ + && !defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + && !defined(PSA_WANT_ALG_CBC_PKCS7) \ + && !defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + && !defined(PSA_WANT_ALG_XTS) \ + && !defined(PSA_WANT_ALG_OFB) \ + && !defined(PSA_WANT_ALG_STREAM_CIPHER) + #define TFM_CRYPTO_CIPHER_MODULE_DISABLED +#endif + +// MAC module +#if !defined(PSA_WANT_ALG_HMAC) \ + && !defined(PSA_WANT_ALG_CMAC) \ + && !defined(PSA_WANT_ALG_CBC_MAC) + #define TFM_CRYPTO_MAC_MODULE_DISABLED +#endif + +// Key derivation module +#if !defined(PSA_WANT_ALG_PBKDF2_HMAC) \ + && !defined(PSA_WANT_ALG_HKDF) \ + && !defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) \ + && !defined(PSA_WANT_ALG_TLS12_PRF) \ + && !defined(PSA_WANT_ALG_TLS12_PSK_TO_MS) \ + && !defined(PSA_WANT_ALG_ECDH) + #define TFM_CRYPTO_KEY_DERIVATION_MODULE_DISABLED +#endif + +// PAKE module +#if !defined(PSA_WANT_ALG_JPAKE) + #define TFM_CRYPTO_PAKE_MODULE_DISABLED +#endif + +#endif // SLI_PSA_TFM_TRANSLATION_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/aes_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/aes_alt.h new file mode 100644 index 000000000..3f0feac60 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/aes_alt.h @@ -0,0 +1,92 @@ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS AES block cipher + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef AES_ALT_H +#define AES_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins Mbed TLS Plugins + * \brief These plugins are used to support acceleration on Silicon Labs + * Hardware for various algorithms. + * + * The APIs are not intended to be used directly, but hook into acceleration points + * in the relevant Mbed TLS APIs + * + * The plugins support sharing of cryptography hardware in multi-threaded applications, + * as well as a reduced overhead configuration for optimal performance in single-threaded + * applications. + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_aes Accelerated AES Block Cipher + * \brief Accelerated AES block cipher for the mbed TLS API using the AES, CRYPTO, + * CRYPTOACC or SE peripheral + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_AES_ALT) +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief AES context structure + */ +typedef struct { + unsigned int keybits; /*!< size of key */ + unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ +} +mbedtls_aes_context; + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief The AES XTS context-type definition. + */ +typedef struct mbedtls_aes_xts_context{ + mbedtls_aes_context crypt; /*!< The AES context to use for AES block + encryption or decryption. */ + mbedtls_aes_context tweak; /*!< The AES context used for tweak + computation. */ +} mbedtls_aes_xts_context; +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_AES_ALT */ + +/** \} (end addtogroup sl_mbedtls_plugins_aes) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* AES_ALT_H */ diff --git a/simplicity_sdk/platform/common/inc/sli_icache_disable.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/ccm_alt.h similarity index 66% rename from simplicity_sdk/platform/common/inc/sli_icache_disable.h rename to simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/ccm_alt.h index ab0046287..eae91d856 100644 --- a/simplicity_sdk/platform/common/inc/sli_icache_disable.h +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/ccm_alt.h @@ -1,9 +1,9 @@ /***************************************************************************//** * @file - * @brief Disable Instruction Cache (Internal) + * @brief Accelerated mbed TLS AES-CCM AEAD cipher ******************************************************************************* * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -27,28 +27,46 @@ * 3. This notice may not be removed or altered from any source distribution. * ******************************************************************************/ +#ifndef CCM_ALT_H +#define CCM_ALT_H -#ifndef _SLI_ICACHE_DISABLE_H_ -#define _SLI_ICACHE_DISABLE_H_ +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_ccm Accelerated AES-CCM AEAD Cipher + * \brief Accelerated AES-CCM AEAD cipher for the mbed TLS API using the CRYPTOACC + * or SE peripheral + * + * \{ + ******************************************************************************/ +#if defined(MBEDTLS_CCM_ALT) #ifdef __cplusplus extern "C" { #endif -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Disable the ICACHE by creating MPU entries for FLASH and RAM code with - * non-cacheable attributes. This will overwrite any previous MPU - * configuration. - ******************************************************************************/ -void sli_icache_disable(void); +/** + * \brief The CCM context-type definition. The CCM context is passed + * to the APIs called. + */ +typedef struct { + unsigned char key[32]; /*!< The key in use. */ + unsigned int keybits; +} +mbedtls_ccm_context; #ifdef __cplusplus } #endif -#endif /* _SLI_ICACHE_DISABLE_H_ */ +#endif /* MBEDTLS_CCM_ALT */ + +/** \} (end addtogroup sl_mbedtls_plugins_ccm) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* CCM_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/cmac_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/cmac_alt.h new file mode 100644 index 000000000..d4a89c22d --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/cmac_alt.h @@ -0,0 +1,77 @@ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS AES-CMAC cipher + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef CMAC_ALT_H +#define CMAC_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_cmac Accelerated AES-CMAC Cipher + * \brief Accelerated AES-CMAC cipher for the mbed TLS API using the CRYPTOACC or + * SE peripheral. This implementation builds on the PSA Crypto drivers + * (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ +#if defined(MBEDTLS_CMAC_ALT) + +#ifdef __cplusplus +extern "C" { +#endif + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_MAC_OPERATION_CTX_TYPE sli_se_transparent_mac_operation_t +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_types.h" +#define SL_MAC_OPERATION_CTX_TYPE sli_cryptoacc_transparent_mac_operation_t +#endif + +struct mbedtls_cmac_context_t { + SL_MAC_OPERATION_CTX_TYPE ctx; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CMAC_ALT */ + +/** \} (end addtogroup sl_mbedtls_plugins_cmac) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* CMAC_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/ecjpake_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/ecjpake_alt.h new file mode 100644 index 000000000..24ba87fea --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/ecjpake_alt.h @@ -0,0 +1,90 @@ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS Elliptic Curve J-PAKE + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef ECJPAKE_ALT_H +#define ECJPAKE_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_jpake Accelerated Elliptic Curve J-PAKE + * \brief Accelerated Elliptic Curve J-PAKE for the mbed TLS API using the SE + * peripheral + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_ECJPAKE_ALT) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * EC J-PAKE context structure. + * + * J-PAKE is a symmetric protocol, except for the identifiers used in + * Zero-Knowledge Proofs, and the serialization of the second message + * (KeyExchange) as defined by the Thread spec. + * + * In order to benefit from this symmetry, we choose a different naming + * convetion from the Thread v1.0 spec. Correspondance is indicated in the + * description as a pair C: client name, S: server name + */ +typedef struct { + uint32_t curve_flags; /**< Curve flags to use */ + mbedtls_ecjpake_role role; /**< Are we client or server? */ + int point_format; /**< Format for point export */ + + char pwd[33]; /**< J-PAKE password */ + size_t pwd_len; /**< J-PAKE password length */ + + uint8_t r[32]; /**< Random scalar for exchange */ + uint8_t Xm1[64]; /**< Our point 1 (round 1) */ + uint8_t Xm2[64]; /**< Our point 2 (round 1) */ + uint8_t Xp1[64]; /**< Their point 1 (round 1) */ + uint8_t Xp2[64]; /**< Their point 2 (round 1) */ + uint8_t Xp[64]; /**< Their point (round 2) */ +} mbedtls_ecjpake_context; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_ECJPAKE_ALT */ + +/** \} (end addtogroup sl_mbedtls_plugins_jpake) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* ECJPAKE_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/gcm_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/gcm_alt.h new file mode 100644 index 000000000..8f6529352 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/gcm_alt.h @@ -0,0 +1,122 @@ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS Galois/Counter Mode (GCM) for AES-128-bit block ciphers + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef GCM_ALT_H +#define GCM_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_gcm Accelerated GCM AES-128 Cipher + * \brief Accelerated AES-GCM-128 cipher for the mbed TLS API using the CRYPTOACC + * or SE peripheral + * + * \{ + * This module implements the GCM AES-128 cipher, as defined in + * D. McGrew, J. Viega, The Galois/Counter Mode of Operation + * (GCM), Natl. Inst. Stand. Technol. + * For more information on GCM, see NIST SP 800-38D: Recommendation for + * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. + * + ******************************************************************************/ + +#if defined(MBEDTLS_GCM_ALT) +/* SiliconLabs CRYPTO hardware acceleration implementation */ + +#include "em_device.h" +#include + +#if defined(CRYPTO_PRESENT) +#include "em_crypto.h" +#elif defined(CRYPTOACC_PRESENT) +#include "sx_aes.h" +#include "sl_enum.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(CRYPTOACC_PRESENT) +SL_ENUM(sli_gcm_mode_t) { + SLI_GCM_ENC = 1, + SLI_GCM_DEC = 2, +}; +#endif + +/** + * \brief The GCM context structure. + */ +typedef struct { + unsigned int keybits; /*!< Size of key */ + uint64_t len; /*!< Total length of encrypted data. */ + uint64_t add_len; /*!< Total length of additional data. */ + +#if defined(CRYPTO_PRESENT) + + CRYPTO_DData_TypeDef key; /*!< AES key, 128 or 256 bits */ + int mode; /*!< Encryption or decryption */ + CRYPTO_TypeDef* device; /*!< CRYPTO device to use */ + CRYPTO_Data_TypeDef ghash_state; /*!< GHASH state */ + CRYPTO_Data_TypeDef gctr_state; /*!< GCTR counter value */ + CRYPTO_Data_TypeDef ghash_key; /*!< GHASH key (is a constant value + which is faster to restore than + to reconstruct each time). */ +#elif defined(SEMAILBOX_PRESENT) + unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ + int mode; /*!< Encryption or decryption */ + size_t iv_len; /*!< IV length */ + bool last_op; /*!< Last streaming block identified */ + uint8_t tagbuf[16]; /*!< Buffer for storing tag */ + uint8_t se_ctx_enc[32]; /*!< SE GCM encryption state */ + uint8_t se_ctx_dec[32]; /*!< SE GCM decryption state */ + +#elif defined(CRYPTOACC_PRESENT) + unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ + sli_gcm_mode_t dir; /*!< Encryption or decryption */ + uint8_t sx_ctx[AES_CTX_xCM_SIZE]; /*!< CRYPTOACC GCM state */ +#endif +} +mbedtls_gcm_context; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_GCM_ALT */ + +/** \} (end addtogroup sl_mbedtls_plugins_gcm) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* GCM_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/se_management.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/se_management.h new file mode 100644 index 000000000..1c7484bb6 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/se_management.h @@ -0,0 +1,127 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs SE device management interface. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SE_MANAGEMENT_H +#define SE_MANAGEMENT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_se_management Peripheral Instance Management: Secure Engine + * \brief Concurrency management functions for Secure Engine mailbox access + * + * \{ + ******************************************************************************/ + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) + +#include "sli_se_manager_mailbox.h" +#include "sli_se_manager_internal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Get ownership of the SE mailbox + * + * \return 0 if successful, negative on error + */ +__STATIC_INLINE int se_management_acquire(void) +{ + // Acquire SE manager lock + return sli_se_lock_acquire() == SL_STATUS_OK ? 0 : -1; +} + +/** + * \brief Release ownership of the SE mailbox + * + * \return 0 if successful, negative on error + */ +__STATIC_INLINE int se_management_release(void) +{ + // Release SE manager lock + return sli_se_lock_release() == SL_STATUS_OK ? 0 : -1; +} + +/** + * \brief Handle the response of the previously executed command. + * + * \details This function handles the response of the previously + * executed HSE command by calling sli_se_mailbox_read_response + * to read the response value and returns it. For Series-3 this + * function executes sli_se_mailbox_read_response inside an + * atomic section and clears the SEMAILBOX FIFO at the end. + * + * \note This function implements a workaround that is planned to be + * replaced in https://jira.silabs.com/browse/PSEC-5643. + * + * \return Value returned by sli_se_mailbox_read_response. + ******************************************************************************/ +__STATIC_INLINE sli_se_mailbox_response_t sli_se_handle_mailbox_response(void) +{ + #if defined(_SILICON_LABS_32B_SERIES_3) + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + #endif + + // Read command response + sli_se_mailbox_response_t se_mailbox_response = sli_se_mailbox_read_response(); + + #if defined(_SILICON_LABS_32B_SERIES_3) + CORE_EXIT_ATOMIC(); + + // Read the command handle word ( not used ) from the SEMAILBOX FIFO + SEMAILBOX_HOST->FIFO; + #endif + + // Return command response + return se_mailbox_response; +} + +#ifdef __cplusplus +} +#endif + +#endif /* SEMAILBOX_PRESENT */ + +/** \} (end addtogroup sl_se_management) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ + +/// @endcond + +#endif /* SE_MANAGEMENT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha1_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha1_alt.h new file mode 100644 index 000000000..e0e9113a6 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha1_alt.h @@ -0,0 +1,81 @@ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS SHA-1 cryptographic hash function + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SHA1_ALT_H +#define SHA1_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_sha1 Accelerated SHA-1 Hash Function + * \brief Accelerated mbed TLS SHA-1 cryptographic hash function for the mbed + * TLS API using Silicon Labs peripherals. This implementation builds on + * the PSA Crypto drivers (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA1_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_cryptoacc_transparent_hash_operation_t +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-1 context structure + */ +typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha1_context; + +#ifdef __cplusplus +} +#endif + +#endif /* #if defined(MBEDTLS_SHA1_ALT) */ + +/** \} (end addtogroup sl_mbedtls_plugins_sha1) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* SHA1_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha256_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha256_alt.h new file mode 100644 index 000000000..b3cb2a07f --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha256_alt.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS SHA-224 and SHA-256 cryptographic hash functions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SHA256_ALT_H +#define SHA256_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_sha256 Accelerated SHA-224/SHA-256 Hash Function + * \brief Accelerated mbed TLS SHA-224/SHA-256 cryptographic hash functions for + * the mbed TLS API using Silicon Labs peripherals. This implementation + * builds on the PSA Crypto drivers (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA256_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_cryptoacc_transparent_hash_operation_t +#endif + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-256 context structure + */ +typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha256_context; + +#ifdef __cplusplus +} +#endif + +#endif /* #if defined(MBEDTLS_SHA256_ALT) */ + +/** \} (end addtogroup sl_mbedtls_plugins_sha256) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* SHA256_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha512_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha512_alt.h new file mode 100644 index 000000000..8eb32f2ff --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sha512_alt.h @@ -0,0 +1,80 @@ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS SHA-384 and SHA-512 cryptographic hash functions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SHA512_ALT_H +#define SHA512_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_sha512 Accelerated SHA-384/SHA-512 Hash Function + * \brief Accelerated mbed TLS SHA-384/SHA-512 cryptographic hash function for + * the mbed TLS API using Silicon Labs peripherals. This implementation + * builds on the PSA Crypto drivers (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA512_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t +#endif + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-512 context structure + */ +typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha512_context; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SHA512_ALT */ + +/** \} (end addtogroup sl_mbedtls_plugins_sha512) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* SHA512_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h new file mode 100644 index 000000000..c54332436 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h @@ -0,0 +1,42 @@ +/***************************************************************************//** + * @file + * @brief Silicon Laboratories platform integration for mbedTLS + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MBEDTLS_H +#define SL_MBEDTLS_H + +/** + * Initialize the Silicon Labs platform integration of mbedTLS. + * + * This function must be called by an application before using any mbedTLS + * functions. This function will make sure that the platform hooks in mbedTLS + * are configured to ensure correct runtime behavior. + */ +void sl_mbedtls_init(void); + +#endif // SL_MBEDTLS_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_crypto.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_crypto.h new file mode 100644 index 000000000..af7160fac --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_crypto.h @@ -0,0 +1,179 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PSA_CRYPTO_H +#define SL_PSA_CRYPTO_H + +#include "psa/crypto.h" + +#include "sl_psa_values.h" + +#include + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * \addtogroup sl_psa_key_management + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set the location attribute of a key in PSA Crypto according to a given + * persistence level, and a preferred location. If the preferred location is + * not available, perhaps because the device does not support this location, + * the primary local storage (PSA_KEY_LOCATION_LOCAL_STORAGE) will be used. + * + * @param[out] attributes + * The attribute structure to write to. + * + * @param[in] persistence + * The persistence level of the key. If this is #PSA_KEY_PERSISTENCE_VOLATILE, + * the key will be volatile, and the key identifier attribute is reset to 0. + * + * @param[in] preferred_location + * The location of the key. Can be \ref SL_PSA_KEY_LOCATION_WRAPPED, + * \ref SL_PSA_KEY_LOCATION_BUILTIN, or PSA_KEY_LOCATION_LOCAL_STORAGE. + ******************************************************************************/ +void sl_psa_set_key_lifetime_with_location_preference( + psa_key_attributes_t *attributes, + psa_key_persistence_t persistence, + psa_key_location_t preferred_location); + +/***************************************************************************//** + * @brief + * Get the 'most secure' location attribute of a key usable in this + * implementation of PSA Crypto. + * + * @return + * The 'most secure' usable location of a key. In order of preference, the + * following values can be returned: \ref SL_PSA_KEY_LOCATION_WRAPPED, + * or PSA_KEY_LOCATION_LOCAL_STORAGE. + ******************************************************************************/ +psa_key_location_t sl_psa_get_most_secure_key_location(void); + +/** \} (end addtogroup sl_psa_key_management) */ + +#ifdef __cplusplus +} +#endif + +#ifdef DOXYGEN +/***************************************************************************//** + * \defgroup sl_psa_crypto PSA Crypto Extensions + * @brief Silicon Labs specific extensions to the PSA Crypto API + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * \defgroup sl_psa_key_derivation Key Derivation + * @brief Key Derivation extensions to the PSA Crypto API + * @{ + ******************************************************************************/ + +// This function is declared in psa/crypto.h, which currently is not included with +// doxygen. Declared here for visibility on docs.silabs.com. + +/** Perform a single-shot key derivation operation and output the resulting key. + * + * This function supports HKDF and PBKDF2. + * + * \note + * - PBKDF2-CMAC is not suported on xG21 + * - PBKDF2-CMAC is only KDF supported for xG27 + * + * This function obtains its secret input from a key object, and any additional + * inputs such as buffers and integers. The output of this function is a key + * object containing the output of the selected key derivation function. + * + * + * \param alg The key derivation algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_KEY_DERIVATION(\p alg) is true). + * \param key_in Identifier of the secret key to input to the + * operation. It must allow the usage + * PSA_KEY_USAGE_DERIVE and be of a symmetric + * type. + * \param[in] info A context- and application specific + * information string. Only used for HKDF, but + * can be omitted. + * \param info_length The length of the provided info in bytes. + * \param[in] salt An optional salt value (a non-secret random value). + * Used for both HKDF and PBKDF2. Recommended for + * PBKDF2. + * \param salt_length The length of the provided salt in bytes. + * \param iterations The number of iterations to use. Maximum + * supported value is 16384. Only used for PBKDF2. + * \param[in] key_out_attributes The attributes for the new key output by the + * derivation operation. The key must be of a + * symmetric type. + * \param[out] key_out The identifier of the new key output by the + * derivation operation. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_NOT_PERMITTED + * The input key does not have the required usage policy set. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The input- or output key is not of a symmetric type. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The input- or output key is larger than what the SE can handle. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The requested algorithm is not supported. + * \retval #PSA_ERROR_HARDWARE_FAILURE + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t sl_psa_key_derivation_single_shot( + psa_algorithm_t alg, + mbedtls_svc_key_id_t key_in, + const uint8_t *info, + size_t info_length, + const uint8_t *salt, + size_t salt_length, + size_t iterations, + const psa_key_attributes_t *key_out_attributes, + mbedtls_svc_key_id_t *key_out); + +/** @} */ // end defgroup sl_psa_key_derivation +/** @} */ // end defgroup sl_psa_crypto + +#endif // DOXYGEN +#endif // SL_PSA_CRYPTO_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_values.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_values.h new file mode 100644 index 000000000..90a1842d6 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_values.h @@ -0,0 +1,192 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Values. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PSA_VALUES_H +#define SL_PSA_VALUES_H + +#include "sli_psa_driver_features.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +// include path: trusted-firmware-m/interface/include + #include "psa/crypto.h" +#else +// include path: mbedtls/include + #include "psa/crypto_driver_common.h" +#endif + +//------------------------------------------------------------------------------ +// Device Agnostic Values + +/***************************************************************************//** + * \addtogroup sl_psa_crypto + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_key_management Key Management + * \brief PSA Crypto key management on Silicon Labs devices + * + * @section built_in_keys Built-in Keys + * The PSA Crypto API provides a mechanism for accessing keys that are stored + * in the hardware. Available built-in key IDs vary for different family of devices. + * For devices vith a Virtual Secure Engine see + * \ref sl_psa_drivers_cryptoacc_builtin_keys , and for devices with a Hardware + * Secure Engine see \ref sl_psa_drivers_se_builtin_keys . + * + * Refer to AN1311 for more information on the + * usage of builtin keys through PSA Crypto. + * @{ + ******************************************************************************/ + +/// Location value for keys to be stored encrypted with the device-unique secret. +/// Wrapped key locations are vailable on Secure Vault High devices. +#define SL_PSA_KEY_LOCATION_WRAPPED ((psa_key_location_t)0x000001UL) + +/// Location value for usage of built-in keys. +/// Built-in key locations are available on Secure Vault Mid (and higher) devices +/// with PUF-key support. +// Identical to SL_PSA_KEY_LOCATION_WRAPPED for implementation-related reasons. +#define SL_PSA_KEY_LOCATION_BUILTIN ((psa_key_location_t)0x000001UL) + +// #define SLE_PSA_KEY_LOCATION_SE_VOLATILE ((psa_key_location_t)0x800000UL) +// #define SLE_PSA_KEY_LOCATION_KSU ((psa_key_location_t)0x800001UL) + +//------------------------------------------------------------------------------ +// Hardware Secure Engine + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +/// Location value for keys to be stored encrypted with the device-unique secret, +/// or for accessing the built-in keys on Vault-High devices. Users should use +/// SL_PSA_KEY_LOCATION_WRAPPED or SL_PSA_KEY_LOCATION_BUILTIN instead. +#define PSA_KEY_LOCATION_SL_SE_OPAQUE (SL_PSA_KEY_LOCATION_WRAPPED) + +#if defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) || defined(SL_TRUSTZONE_NONSECURE) + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se_builtin_keys Built-in keys on devices with a HSE + * \brief These key ID values allow access to the keys which respectively are and + * can be preprovisioned in Secure Engine (HSE) devices. + * + * The key IDs are within the the builtin range of PSA [MBEDTLS_PSA_KEY_ID_BUILTIN_MIN, + * MBEDLTS_PSA_KEY_ID_BUILTIN_MAX]. + * + * @{ + ******************************************************************************/ +#if defined(SLI_PSA_DRIVER_FEATURE_ATTESTATION) + #ifndef SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID +/// Vendor Key ID for the built-in application identity key on Vault High devices. + #define SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 5) + #endif + + #ifndef SL_SE_BUILTIN_KEY_SYSTEM_ATTESTATION_ID +/// Vendor Key ID for the built-in SE identity key on Vault High devices. + #define SL_SE_BUILTIN_KEY_SYSTEM_ATTESTATION_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 4) + #endif +#endif // SLI_PSA_DRIVER_FEATURE_ATTESTATION + +#ifndef SL_SE_BUILTIN_KEY_SECUREBOOT_ID +/// Vendor Key ID for the Secure Boot verifying key provisioned to the Secure Engine. + #define SL_SE_BUILTIN_KEY_SECUREBOOT_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 1) +#endif + +#ifndef SL_SE_BUILTIN_KEY_SECUREDEBUG_ID +/// Vendor Key ID for the Secure Debug verifying key provisioned to the Secure Engine. + #define SL_SE_BUILTIN_KEY_SECUREDEBUG_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 2) +#endif + +#ifndef SL_SE_BUILTIN_KEY_AES128_ID +/// Vendor Key ID for AES-128 key provisioned to the Secure Engine. + #define SL_SE_BUILTIN_KEY_AES128_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 3) +#endif + +#ifndef SL_SE_BUILTIN_KEY_TRUSTZONE_ID +/// Vendor Key ID for the TrustZone root key. + #define SL_SE_BUILTIN_KEY_TRUSTZONE_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 6) +#endif + +#ifndef SL_SE_BUILTIN_KEY_AES128_ALG +/// Algorithm with which the #SL_SE_BUILTIN_KEY_AES128_ID key will be used. +// PSA Crypto only allows one specific usage algorithm per built-in key ID. + #define SL_SE_BUILTIN_KEY_AES128_ALG (SL_SE_BUILTIN_KEY_AES128_ALG_CONFIG) +#endif + +/** @} (end addtogroup sl_psa_drivers_se_builtin_keys) */ + +#endif // SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS || SL_TRUSTZONE_NONSECURE + +#endif // SLI_MBEDTLS_DEVICE_HSE + +//------------------------------------------------------------------------------ +// Virtual Secure Engine + +#if defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) + +/// Location value for built-in keys on VSE archtectures +/// Users should use \ref SL_PSA_KEY_LOCATION_BUILTIN instead +#define PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE (SL_PSA_KEY_LOCATION_BUILTIN) + +#if defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) || defined(SL_TRUSTZONE_NONSECURE) + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc_builtin_keys Built-in keys on devices with a VSE + * \brief These key ID values allow access to the keys which respectively are and + * can be preprovisioned in Virtual Secure Engine (VSE) devices. + * + * The key ID's are within the the builtin range of PSA [MBEDTLS_PSA_KEY_ID_BUILTIN_MIN, + * MBEDLTS_PSA_KEY_ID_BUILTIN_MAX]. + * @{ + ******************************************************************************/ + +#ifndef SL_CRYPTOACC_BUILTIN_KEY_PUF_ID +/// Vendor Key ID for the PUF-derived hardware unique key. + #define SL_CRYPTOACC_BUILTIN_KEY_PUF_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 1) +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/// Internal ID for PUF-derived key. +#define SLI_CRYPTOACC_BUILTIN_KEY_PUF_SLOT (SL_CRYPTOACC_BUILTIN_KEY_PUF_ID && 0xFF) + +/// Version of opaque header struct. +#define SLI_CRYPTOACC_OPAQUE_KEY_CONTEXT_VERSION (0x00) + +/// @endcond + +/** @} (end addtogroup sl_psa_drivers_cryptoacc) */ + +#endif // SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS || SL_TRUSTZONE_NONSECURE + +/** @} (end addtogroup sl_psa_key_management) */ +/** @} (end addtogroup sl_psa_drivers) */ + +#endif // SLI_PSA_DRIVER_FEATURE_PUF_KEY + +#endif // SL_PSA_VALUES_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sli_psa_crypto.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sli_psa_crypto.h new file mode 100644 index 000000000..0461d8071 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/sli_psa_crypto.h @@ -0,0 +1,155 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs internal PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_CRYPTO_H +#define SLI_PSA_CRYPTO_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "psa/crypto.h" + +#include +#include + +// ----------------------------------------------------------------------------- +// Defines and Macros + +// Persistent key ID ranges. +#define SLI_PSA_KEY_ID_RANGE_THREAD_START (0x00020000) +#define SLI_PSA_KEY_ID_RANGE_THREAD_END (0x0002FFFF) +#define SLI_PSA_KEY_ID_RANGE_ZIGBEE_START (0x00030000) +#define SLI_PSA_KEY_ID_RANGE_ZIGBEE_END (0x0003FFFF) + +// Convert a type name into an enum entry name, since enum entries and type +// names share the same C namespace. +#define SLI_PSA_CONTEXT_ENUM_NAME(NAME) \ + NAME ## _e +#define SLI_MBEDTLS_CONTEXT_ENUM_NAME(NAME) \ + NAME ## _e + +// Convenience macros for getting the size of a context structure type +#define SLI_PSA_CONTEXT_GET_RUNTIME_SIZE(NAME) \ + (sli_psa_context_get_size(SLI_PSA_CONTEXT_ENUM_NAME(NAME))) +#define SLI_MBEDTLS_CONTEXT_GET_RUNTIME_SIZE(NAME) \ + (sli_mbedtls_context_get_size(SLI_MBEDTLS_CONTEXT_ENUM_NAME(NAME))) + +// ----------------------------------------------------------------------------- +// Type Definitions + +// Type names supported by sli_psa_context_get_size. +typedef enum { + SLI_PSA_CONTEXT_ENUM_NAME(psa_hash_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_cipher_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_pake_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_mac_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_aead_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_key_derivation_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_key_attributes_t) +} sli_psa_context_name_t; + +// Type names supported by sli_mbedtls_context_get_size. +typedef enum { + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_aes_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ccm_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_cipher_context_t), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ctr_drbg_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_entropy_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_md_context_t), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_nist_kw_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_pk_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha1_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha256_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_config), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_cookie_ctx), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_x509_crt) +} sli_mbedtls_context_name_t; + +// ----------------------------------------------------------------------------- +// Function Declarations + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @brief + * Get the size of a named PSA context structure. This is valuable for code + * shipping as precompiled libraries and needing to link with a source version + * of PSA Crypto, since the context structures can change in size based on + * configuration options which might not have been present at library + * compilation time. + * + * @param ctx_type + * Which context structure to get the size of. Use + * #SLI_PSA_CONTEXT_ENUM_NAME(psa_xxx_operation_t) as argument. + * + * @return + * Size (in bytes) of the context structure as expected by the current build. + ******************************************************************************/ +size_t sli_psa_context_get_size(sli_psa_context_name_t ctx_type); + +/***************************************************************************//** + * @brief + * Get the size of a named Mbed TLS context structure. This is valuable for + * code shipping as precompiled libraries and needing to link with a source + * version of PSA Crypto, since the context structures can change in size + * based on configuration options which might not have been present at library + * compilation time. + * + * @param ctx_type + * Which context structure to get the size of. Use + * #SLI_MBEDTLS_CONTEXT_ENUM_NAME() as argument. + * + * @return + * Size (in bytes) of the context structure as expected by the current build. + ******************************************************************************/ +size_t sli_mbedtls_context_get_size(sli_mbedtls_context_name_t ctx_type); + +/***************************************************************************//** + * @brief + * Check if a key is copyable even though the key attributes do not have the + * PSA_KEY_USAGE_COPY flag set. + * + * @param key_id + * The key ID of the key of interest. + * + * @return + * True if the key should be unconditionally copyable, otherwise false. + ******************************************************************************/ +bool sli_psa_key_is_unconditionally_copyable(psa_key_id_t key_id); + +#ifdef __cplusplus +} +#endif + +/// @endcond + +#endif // SLI_PSA_CRYPTO_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/threading_alt.h b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/threading_alt.h new file mode 100644 index 000000000..81aed2811 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/inc/threading_alt.h @@ -0,0 +1,259 @@ +/**************************************************************************/ /** + * @file + * @brief Threading primitive implementation for mbed TLS + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef THREADING_ALT_H +#define THREADING_ALT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_mbedtls_plugins_threading Threading Primitives + * \brief Threading primitive implementation for mbed TLS + * + * This module provides a threading implementation, based on CMSIS RTOS2, that + * can be used by Mbed TLS when threading is required. + * + * \note These plugins are automatically enabled when creating an SLC project + * with Micrium OS or FreeRTOS with Mbed TLS. + * + * \{ + ******************************************************************************/ + +#include + +#if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) + +#if defined(SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + +#include "sli_psec_osal.h" +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define SL_THREADING_ALT + +#define MUTEX_INIT = { 0 } + +/// Mbed TLS mutexes maps to SLI PSEC OSAL locks. +typedef sli_psec_osal_lock_t mbedtls_threading_mutex_t; + +typedef struct mbedtls_test_thread_t { + osThreadAttr_t thread_attr; + osThreadId_t thread_ID; +} mbedtls_test_thread_t; + +#include "mbedtls/threading.h" + +#ifndef MBEDTLS_ERR_THREADING_THREAD_ERROR +#define MBEDTLS_ERR_THREADING_THREAD_ERROR -0x001F +#endif +/** + * \brief Set mutex recursive + * + * \param mutex Pointer to the mutex + */ +static inline void THREADING_SetRecursive(mbedtls_threading_mutex_t *mutex) +{ + sl_status_t sl_status = sli_psec_osal_set_recursive_lock((sli_psec_osal_lock_t*)mutex); + EFM_ASSERT(sl_status == SL_STATUS_OK); +} + +/** + * \brief Initialize a given mutex + * + * \param mutex Pointer to the mutex needing initialization + */ +static inline void THREADING_InitMutex(mbedtls_threading_mutex_t *mutex) +{ + sl_status_t sl_status = sli_psec_osal_init_lock(mutex); + EFM_ASSERT(sl_status == SL_STATUS_OK); +} + +/** + * \brief Free a given mutex + * + * \param mutex Pointer to the mutex being freed + */ +static inline void THREADING_FreeMutex(mbedtls_threading_mutex_t *mutex) +{ + sl_status_t sl_status = sli_psec_osal_free_lock(mutex); + EFM_ASSERT(sl_status == SL_STATUS_OK); +} + +/** + * \brief Pend on a mutex + * + * \param mutex Pointer to the mutex being pended on + * + * \return RTOS_ERR_NONE on success, error code otherwise. + */ +static inline int THREADING_TakeMutexBlocking(mbedtls_threading_mutex_t *mutex) +{ + if (mutex == NULL) { + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; + } + sl_status_t sl_status = sli_psec_osal_take_lock(mutex); + return (sl_status == SL_STATUS_OK ? 0 : MBEDTLS_ERR_THREADING_MUTEX_ERROR); +} + +/** + * \brief Try to own a mutex without waiting + * + * \param mutex Pointer to the mutex being tested + * + * \return RTOS_ERR_NONE on success (= mutex successfully owned), error code otherwise. + */ +static inline int THREADING_TakeMutexNonBlocking(mbedtls_threading_mutex_t *mutex) +{ + if (mutex == NULL) { + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; + } + sl_status_t sl_status = sli_psec_osal_take_lock_non_blocking(mutex); + return (sl_status == SL_STATUS_OK ? 0 : MBEDTLS_ERR_THREADING_MUTEX_ERROR); +} + +/** + * \brief Release a mutex + * + * \param mutex Pointer to the mutex being released + * + * \return RTOS_ERR_NONE on success, error code otherwise. + */ +static inline int THREADING_GiveMutex(mbedtls_threading_mutex_t *mutex) +{ + if (mutex == NULL) { + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; + } + sl_status_t sl_status = sli_psec_osal_give_lock(mutex); + return (sl_status == SL_STATUS_OK ? 0 : MBEDTLS_ERR_THREADING_MUTEX_ERROR); +} + +/** + * \brief The thread create function implementation + * + * \param thread Pointer to the thread being created + * \param thread_func Pointer to the thread function + * \param thread_data Pointer to the thread data + */ +static inline int THREADING_ThreadCreate(mbedtls_test_thread_t *thread, + void (*thread_func)( + void *), + void *thread_data) +{ + if (thread == NULL || thread_func == NULL) { + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; + } + + thread->thread_ID = osThreadNew(thread_func, thread_data, &thread->thread_attr); + if (thread->thread_ID == NULL) { + return MBEDTLS_ERR_THREADING_THREAD_ERROR; + } + + return 0; +} + +/** + * \brief The thread join function implementation + * + * \param thread Pointer to the thread being joined + */ +static inline int THREADING_ThreadJoin(mbedtls_test_thread_t *thread) +{ + if (thread == NULL) { + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; + } + + if (osThreadJoin(thread->thread_ID) != 0) { + return MBEDTLS_ERR_THREADING_THREAD_ERROR; + } + + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif // SL_CATALOG_MICRIUMOS_KERNEL_PRESENT || SL_CATALOG_FREERTOS_KERNEL_PRESENT + +#ifdef __cplusplus +extern "C" { +#endif + +/* Forward declaration of threading_set_alt */ +void mbedtls_threading_set_alt(void (*mutex_init)(mbedtls_threading_mutex_t *), + void (*mutex_free)(mbedtls_threading_mutex_t *), + int (*mutex_lock)(mbedtls_threading_mutex_t *), + int (*mutex_unlock)(mbedtls_threading_mutex_t *) ); + +/* Forward declaration of test_thread_set_alt */ +void mbedtls_test_thread_set_alt(int (*thread_create)(mbedtls_test_thread_t *thread, + void (*thread_func)( + void *), + void *thread_data), + int (*thread_join)(mbedtls_test_thread_t *thread)); + +/** + * \brief Helper function for setting up the mbed TLS threading subsystem + */ +static inline void THREADING_setup(void) +{ + mbedtls_threading_set_alt(&THREADING_InitMutex, + &THREADING_FreeMutex, + &THREADING_TakeMutexBlocking, + &THREADING_GiveMutex); +} + +static inline void THREAD_test_setup(void) +{ + mbedtls_test_thread_set_alt(&THREADING_ThreadCreate, + &THREADING_ThreadJoin); +} +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_THREADING_ALT && MBEDTLS_THREADING_C */ + +/** \} (end addtogroup sl_mbedtls_plugins_threading) */ +/** \} (end addtogroup sl_mbedtls_plugins) */ +/// @endcond + +#endif /* THREADING_ALT_H */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c new file mode 100644 index 000000000..162b4422d --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c @@ -0,0 +1,774 @@ +/***************************************************************************//** + * @file + * @brief AES abstraction based on CRYPTOACC + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes alternative plugin implementations of various + * functions in aes.c using the cryptographic accelerator incorporated + * in Series-2 devices with CRYPTOACC from Silicon Laboratories. + */ + +/* + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include + +#if defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_AES_ALT) +#include "cryptoacc_management.h" +#include "sx_aes.h" +#include "sx_errors.h" +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include + +/* + * Initialize AES context + */ +void mbedtls_aes_init(mbedtls_aes_context *ctx) +{ + memset(ctx, 0, sizeof(mbedtls_aes_context) ); +} + +/* + * Clear AES context + */ +void mbedtls_aes_free(mbedtls_aes_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_aes_context) ); +} + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx) +{ + mbedtls_aes_init(&ctx->crypt); + mbedtls_aes_init(&ctx->tweak); +} + +void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + mbedtls_aes_free(&ctx->crypt); + mbedtls_aes_free(&ctx->tweak); +} + +static int mbedtls_aes_xts_decode_keys(const unsigned char *key, + unsigned int keybits, + const unsigned char **key1, + unsigned int *key1bits, + const unsigned char **key2, + unsigned int *key2bits) +{ + const unsigned int half_keybits = keybits / 2; + const unsigned int half_keybytes = half_keybits / 8; + + switch ( keybits ) { + case 256: break; + case 512: break; + default: return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); + } + + *key1bits = half_keybits; + *key2bits = half_keybits; + *key1 = &key[0]; + *key2 = &key[half_keybytes]; + + return 0; +} + +int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1 = NULL; + const unsigned char *key2 = NULL; + unsigned int key1bits = 0; + unsigned int key2bits = 0; + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, + &key2, &key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set the tweak key. Always set tweak key for the encryption mode. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set crypt key for encryption. */ + return mbedtls_aes_setkey_enc(&ctx->crypt, key1, key1bits); +} + +int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1 = NULL; + const unsigned char *key2 = NULL; + unsigned int key1bits = 0; + unsigned int key2bits = 0; + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, + &key2, &key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set the tweak key. Always set tweak key for encryption. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set crypt key for decryption. */ + return mbedtls_aes_setkey_dec(&ctx->crypt, key1, key1bits); +} + +/* Endianess with 64 bits values */ +#ifndef GET_UINT64_LE +#define GET_UINT64_LE(n, b, i) \ + { \ + (n) = ( (uint64_t) (b)[(i) + 7] << 56) \ + | ( (uint64_t) (b)[(i) + 6] << 48) \ + | ( (uint64_t) (b)[(i) + 5] << 40) \ + | ( (uint64_t) (b)[(i) + 4] << 32) \ + | ( (uint64_t) (b)[(i) + 3] << 24) \ + | ( (uint64_t) (b)[(i) + 2] << 16) \ + | ( (uint64_t) (b)[(i) + 1] << 8) \ + | ( (uint64_t) (b)[(i)]); \ + } +#endif + +#ifndef PUT_UINT64_LE +#define PUT_UINT64_LE(n, b, i) \ + { \ + (b)[(i) + 7] = (unsigned char) ( (n) >> 56); \ + (b)[(i) + 6] = (unsigned char) ( (n) >> 48); \ + (b)[(i) + 5] = (unsigned char) ( (n) >> 40); \ + (b)[(i) + 4] = (unsigned char) ( (n) >> 32); \ + (b)[(i) + 3] = (unsigned char) ( (n) >> 24); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 16); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 8); \ + (b)[(i)] = (unsigned char) ( (n) ); \ + } +#endif + +typedef unsigned char mbedtls_be128[16]; + +/* + * GF(2^128) multiplication function + * + * This function multiplies a field element by x in the polynomial field + * representation. It uses 64-bit word operations to gain speed but compensates + * for machine endianess and hence works correctly on both big and little + * endian machines. + */ +static void mbedtls_gf128mul_x_ble(unsigned char r[16], + const unsigned char x[16]) +{ + uint64_t a, b, ra, rb; + + GET_UINT64_LE(a, x, 0); + GET_UINT64_LE(b, x, 8); + + ra = (a << 1) ^ 0x0087 >> (8 - ( (b >> 63) << 3) ); + rb = (a >> 63) | (b << 1); + + PUT_UINT64_LE(ra, r, 0); + PUT_UINT64_LE(rb, r, 8); +} + +/* + * AES-XTS buffer encryption/decryption + */ +int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, + int mode, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output) +{ + int ret; + size_t blocks = length / 16; + size_t leftover = length % 16; + unsigned char tweak[16]; + unsigned char prev_tweak[16]; + unsigned char tmp[16]; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + /* Data units must be at least 16 bytes long. */ + if ( length < 16 ) { + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + /* NIST SP 800-38E disallows data units larger than 2**20 blocks. */ + if ( length > (1 << 20) * 16 ) { + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + /* Compute the tweak. */ + ret = mbedtls_aes_crypt_ecb(&ctx->tweak, MBEDTLS_AES_ENCRYPT, + data_unit, tweak); + if ( ret != 0 ) { + return(ret); + } + + while ( blocks-- ) { + size_t i; + + if ( leftover && (mode == MBEDTLS_AES_DECRYPT) && blocks == 0 ) { + /* We are on the last block in a decrypt operation that has + * leftover bytes, so we need to use the next tweak for this block, + * and this tweak for the lefover bytes. Save the current tweak for + * the leftovers and then update the current tweak for use on this, + * the last full block. */ + memcpy(prev_tweak, tweak, sizeof(tweak) ); + mbedtls_gf128mul_x_ble(tweak, tweak); + } + + for ( i = 0; i < 16; i++ ) { + tmp[i] = input[i] ^ tweak[i]; + } + + ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); + if ( ret != 0 ) { + return(ret); + } + + for ( i = 0; i < 16; i++ ) { + output[i] = tmp[i] ^ tweak[i]; + } + + /* Update the tweak for the next block. */ + mbedtls_gf128mul_x_ble(tweak, tweak); + + output += 16; + input += 16; + } + + if ( leftover ) { + /* If we are on the leftover bytes in a decrypt operation, we need to + * use the previous tweak for these bytes (as saved in prev_tweak). */ + unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak; + + /* We are now on the final part of the data unit, which doesn't divide + * evenly by 16. It's time for ciphertext stealing. */ + size_t i; + unsigned char *prev_output = output - 16; + + /* Copy ciphertext bytes from the previous block to our output for each + * byte of cyphertext we won't steal. At the same time, copy the + * remainder of the input for this final round (since the loop bounds + * are the same). */ + for ( i = 0; i < leftover; i++ ) { + output[i] = prev_output[i]; + tmp[i] = input[i] ^ t[i]; + } + + /* Copy ciphertext bytes from the previous block for input in this + * round. */ + for (; i < 16; i++ ) { + tmp[i] = prev_output[i] ^ t[i]; + } + + ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); + if ( ret != 0 ) { + return ret; + } + + /* Write the result back to the previous block, overriding the previous + * output we copied. */ + for ( i = 0; i < 16; i++ ) { + prev_output[i] = tmp[i] ^ t[i]; + } + } + + return(0); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/* + * AES key schedule (encryption) + */ +int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + memset(ctx, 0, sizeof(mbedtls_aes_context) ); + + if ( (128UL != keybits) && (192UL != keybits) && (256UL != keybits) ) { + /* Unsupported key size */ + return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); + } + + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +/* + * AES key schedule (decryption) + */ +int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + return mbedtls_aes_setkey_enc(ctx, key, keybits); +} + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]) +{ + int status; + uint32_t sx_ret; + block_t key; + block_t data_in; + block_t data_out; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL ) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + data_in = block_t_convert(input, 16); + data_out = block_t_convert(output, 16); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (mode == MBEDTLS_AES_ENCRYPT) { + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, (const block_t*)&data_in, &data_out); + } else { + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, (const block_t*)&data_in, &data_out); + } + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } else { + return 0; + } +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + int status; + uint32_t sx_ret; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + /* Input length must be a multiple of 16 bytes which is the AES block + length. */ + if ( length & 0xf ) { + return(MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH); + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + iv_block = block_t_convert(iv, 16); + data_in = block_t_convert(input, length); + data_out = block_t_convert(output, length); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (mode == MBEDTLS_AES_ENCRYPT) { + sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } else { + sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } else { + return 0; + } +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + int status; + size_t n = iv_off ? *iv_off : 0; + size_t processed = 0; + uint32_t sx_ret; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( n > 15 ) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + iv_block = block_t_convert(iv, 16); + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + if ( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + continue; + } else { + /* process one ore more blocks of data */ + size_t iterations = (length - processed) / 16; + + if ( iterations > 0 ) { + data_in = block_t_convert(&input[processed], iterations * 16); + data_out = block_t_convert(&output[processed], iterations * 16); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (mode == MBEDTLS_AES_ENCRYPT) { + sx_ret = sx_aes_cfb_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } else { + sx_ret = sx_aes_cfb_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + processed += iterations * 16; + } + + while ( length - processed > 0 ) { + if ( n == 0 ) { + // Need to update the IV but don't have a full block of input to pass to the SE + int ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); + if (ret != 0) { + return ret; + } + } + /* Save remainder to iv */ + if ( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + } + } + } + + if ( iv_off ) { + *iv_off = n; + } + + return 0; +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + unsigned char c; + unsigned char ov[17]; + int ret = 0; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + while ( length-- ) { + memcpy(ov, iv, 16); + if ( (ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv)) + != 0 ) { + return ret; + } + + if ( mode == MBEDTLS_AES_DECRYPT ) { + ov[16] = *input; + } + + c = *output++ = (unsigned char)(iv[0] ^ *input++); + + if ( mode == MBEDTLS_AES_ENCRYPT ) { + ov[16] = c; + } + + memcpy(iv, ov + 1, 16); + } + + return ret; +} +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output) +{ + int status; + size_t n = nc_off ? *nc_off : 0; + size_t processed = 0; + uint32_t sx_ret; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + iv_block = block_t_convert(nonce_counter, 16); + + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & 0x0F; + processed++; + } else { + /* process one or more blocks of data */ + size_t iterations = (length - processed) / 16; + + if ( iterations > 0 ) { + data_in = block_t_convert(&input[processed], iterations * 16); + data_out = block_t_convert(&output[processed], iterations * 16); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + // AES-CTR uses the only AES encrypt operation (for both encryption and decryption) + sx_ret = sx_aes_ctr_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + processed += iterations * 16; + } + + while ( length - processed > 0 ) { + if ( n == 0 ) { + // Get a new stream block + status = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, + nonce_counter, stream_block); + if (status != 0) { + return status; + } + // increment nonce counter... + for (size_t i = 0; i < 16; i++) { + nonce_counter[15 - i] = nonce_counter[15 - i] + 1; + if ( nonce_counter[15 - i] != 0 ) { + break; + } + } + } + /* Save remainder to iv */ + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & 0x0F; + processed++; + } + } + } + + if ( nc_off ) { + *nc_off = n; + } + + return 0; +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/* + * AES-OFB (Output Feedback Mode) buffer encryption/decryption + */ +int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + int ret = 0; + size_t n; + + n = *iv_off; + + if ( n > 15 ) { + return(MBEDTLS_ERR_AES_BAD_INPUT_DATA); + } + + while ( length-- ) { + if ( n == 0 ) { + ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); + if ( ret != 0 ) { + goto exit; + } + } + *output++ = *input++ ^ iv[n]; + + n = (n + 1) & 0x0F; + } + + *iv_off = n; + + exit: + return(ret); +} +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#endif /* MBEDTLS_AES_ALT */ + +#endif /* MBEDTLS_AES_C */ + +#endif /* CRYPTOACC_PRESENT */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c new file mode 100644 index 000000000..4db8831b4 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c @@ -0,0 +1,478 @@ +/***************************************************************************//** + * @file + * @brief AES-CMAC abstraction based on CRYPTOACC + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes alternative plugin implementations of various + * functions in gmac.c using the cryptographic accelerator incorporated + * in Series-2 devices with CRYPTOACC from Silicon Laboratories. + */ + +/* + * http://csrc.nist.gov/publications/nistpubs/800-38D/SP-800-38D.pdf + * + * See also: + * [MGV] http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf + * + * We use the algorithm described as Shoup's method with 4-bit tables in + * [MGV] 4.1, pp. 12-13, to enhance speed without using too much memory. + */ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include + +#if defined(MBEDTLS_GCM_ALT) && defined(MBEDTLS_GCM_C) +#include "cryptoacc_management.h" +#include "mbedtls/gcm.h" +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include "sx_aes.h" +#include "sx_math.h" +#include "sx_errors.h" +#include "cryptolib_def.h" +#include + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = v; while ( n-- ) *p++ = 0; +} + +static int sli_validate_gcm_params(size_t tag_len, + size_t iv_len, + size_t add_len) +{ + // NOTE: tag lengths != 16 byte are only supported as of SE FW v1.2.0. + // Earlier firmware versions will return an error trying to verify non-16-byte + // tags using this function. + if ( tag_len < 4 || tag_len > 16 || iv_len == 0 ) { + return (MBEDTLS_ERR_GCM_BAD_INPUT); + } + + /* AD are limited to 2^64 bits, so 2^61 bytes. Since the length of AAD is + * limited by the mbedtls API to a size_t, length checking only needs to be + * done on 64-bit platforms. */ +#if SIZE_MAX > 0xFFFFFFFFUL + if (add_len >> 61 != 0) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } +#else + (void) add_len; +#endif /* 64-bit size_t */ + + /* Library does not support non-12-byte IVs */ + if (iv_len != AES_IV_GCM_SIZE) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + return 0; +} + +/* + * Initialize a context + */ +void mbedtls_gcm_init(mbedtls_gcm_context *ctx) +{ + memset(ctx, 0, sizeof(mbedtls_gcm_context) ); +} + +// Set key +int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits) +{ + (void) cipher; + + if ( cipher != MBEDTLS_CIPHER_ID_AES ) { + return(MBEDTLS_ERR_GCM_BAD_INPUT); + } + + if ( keybits != 128 && keybits != 192 && keybits != 256 ) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + /* Store key in gcm context */ + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len) +{ + int status = sli_validate_gcm_params(16, iv_len, 0); + if (status) { + return status; + } + + /* Store input in context data structure. */ + ctx->dir = mode == MBEDTLS_AES_ENCRYPT ? SLI_GCM_ENC : SLI_GCM_DEC; + ctx->add_len = 0; + ctx->len = 0; + + memcpy(ctx->sx_ctx, iv, AES_IV_GCM_SIZE); + return 0; +} + +int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, + const unsigned char *add, + size_t add_len) +{ + uint32_t sx_ret; + block_t key; + block_t aad; + block_t nonce; + block_t hw_ctx; + block_t dummy = NULL_blk; + + int status = sli_validate_gcm_params(16, 12, add_len); + if (status) { + return status; + } + + if (add_len == 0) { + return 0; + } + + if (ctx->add_len > 0) { + // This accelerator does not support adding AD in chunks + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + ctx->add_len = add_len; + + key = block_t_convert(ctx->key, ctx->keybits / 8); + nonce = block_t_convert(ctx->sx_ctx, AES_IV_GCM_SIZE); + aad = block_t_convert(add, add_len); + hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_init((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&aad); + } else { + sx_ret = sx_aes_gcm_decrypt_init((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&aad); + } + status = cryptoacc_management_release(); + + if (sx_ret == CRYPTOLIB_SUCCESS) { + return status; + } else { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} + +int mbedtls_gcm_update(mbedtls_gcm_context *ctx, + const unsigned char *input, size_t input_length, + unsigned char *output, size_t output_size, + size_t *output_length) +{ + int status; + uint32_t sx_ret; + block_t data_in; + block_t data_out; + block_t key; + block_t nonce; + block_t hw_ctx; + block_t dummy = NULL_blk; + + *output_length = 0; + + if (input_length > output_size) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + if (input_length == 0) { + return 0; + } + + /* Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes + * Also check for possible overflow */ + if ( ctx->len + input_length < ctx->len + || (uint64_t) ctx->len + input_length > 0xFFFFFFFE0ull ) { + return(MBEDTLS_ERR_GCM_BAD_INPUT); + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); + + if (ctx->add_len == 0 && ctx->len == 0) { + /* If there were no additional authentcation data then + mbedtls_gcm_starts did not 'CTX_BEGIN' the GCM operation + in the CRYPTOACC, so we need to 'CTX_BEGIN' now. */ + nonce = block_t_convert(ctx->sx_ctx, AES_IV_GCM_SIZE); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_init((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&dummy); + } else { + sx_ret = sx_aes_gcm_decrypt_init((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&dummy); + } + status = cryptoacc_management_release(); + } else { + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&hw_ctx, &hw_ctx); + } else { + sx_ret = sx_aes_gcm_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&hw_ctx, &hw_ctx); + } + status = cryptoacc_management_release(); + } + + ctx->len += input_length; + + if (sx_ret == CRYPTOLIB_SUCCESS) { + *output_length = input_length; + return status; + } else { + memset(output, 0, output_size); + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} + +int mbedtls_gcm_finish(mbedtls_gcm_context *ctx, + unsigned char *output, size_t output_size, + size_t *output_length, + unsigned char *tag, + size_t tag_len) +{ + // Voiding these because our implementation does not support + // partial-block input (i.e. passing a partial block to + // update() will have caused the operation to finish already) + (void) output; + (void) output_size; + *output_length = 0; + + int status; + uint32_t sx_ret; + block_t key; + block_t _tag; + uint8_t tagbuf[16]; + uint8_t lena_lenc[16]; + block_t lena_lenc_blk = NULL_blk; + block_t dummy = NULL_blk; + block_t hw_ctx; + + status = sli_validate_gcm_params(tag_len, 12, 16); + if (status) { + return status; + } + + if (ctx->add_len == 0 && ctx->len == 0) { + /* If there were no data and additional authentcation data then + mbedtls_gcm_starts and update did not start the GCM operation, + so we need to run the whole GCM now. */ + return mbedtls_gcm_crypt_and_tag(ctx, + ctx->dir == SLI_GCM_ENC ? MBEDTLS_GCM_ENCRYPT + : MBEDTLS_GCM_DECRYPT, + 0, ctx->sx_ctx, AES_IV_GCM_SIZE, 0, 0, 0, 0, + tag_len, tag); + } else { + key = block_t_convert(ctx->key, ctx->keybits / 8); + _tag = block_t_convert(tagbuf, 16); // CRYPTOACC supports only 128bits tags + hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); + + // build lena_lenc block as big endian byte array + sx_math_u64_to_u8array(ctx->add_len << 3, &lena_lenc[0], sx_big_endian); + sx_math_u64_to_u8array(ctx->len << 3, &lena_lenc[8], sx_big_endian); + lena_lenc_blk = block_t_convert(lena_lenc, 16); + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_final((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&hw_ctx, &_tag, (const block_t *)&lena_lenc_blk); + } else { + sx_ret = sx_aes_gcm_decrypt_final((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&hw_ctx, &_tag, (const block_t *)&lena_lenc_blk); + } + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } + + memcpy(tag, tagbuf, tag_len); + return(status); + } +} + +int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag) +{ + int status; + uint32_t sx_ret; + sli_gcm_mode_t dir = mode == MBEDTLS_AES_ENCRYPT ? SLI_GCM_ENC : SLI_GCM_DEC; + block_t key; + block_t aad; + block_t _tag; + block_t nonce; + block_t data_in; + block_t data_out; + uint8_t tagbuf[16]; + + status = sli_validate_gcm_params(tag_len, iv_len, add_len); + if (status) { + return status; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + nonce = block_t_convert(iv, iv_len); + aad = block_t_convert(add, add_len); + _tag = block_t_convert(tagbuf, sizeof(tagbuf)); // CRYPTOACC supports only 128bits tags + data_in = block_t_convert(input, length); + data_out = block_t_convert(output, length); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &_tag, (const block_t *)&aad); + } else { + sx_ret = sx_aes_gcm_decrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &_tag, (const block_t *)&aad); + } + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + mbedtls_zeroize(output, length); + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } + + memcpy(tag, tagbuf, tag_len); + return(status); +} + +int mbedtls_gcm_auth_decrypt(mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output) +{ + int status; + uint32_t sx_ret; + block_t key; + block_t aad; + block_t _tag; + block_t nonce; + block_t data_in; + block_t data_out; + uint8_t tagbuf[16]; + + status = sli_validate_gcm_params(tag_len, iv_len, add_len); + if (status) { + return status; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + nonce = block_t_convert(iv, iv_len); + aad = block_t_convert(add, add_len); + _tag = block_t_convert(tagbuf, sizeof(tagbuf)); // CRYPTOACC supports only 128bits tags + data_in = block_t_convert(input, length); + data_out = block_t_convert(output, length); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + sx_ret = sx_aes_gcm_decrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &_tag, (const block_t *)&aad); + status = cryptoacc_management_release(); + + if (sx_ret == CRYPTOLIB_SUCCESS) { + if (memcmp_time_cst((uint8_t*)tag, tagbuf, tag_len) == 0) { + return(status); + } else { + mbedtls_zeroize(output, length); + return(MBEDTLS_ERR_GCM_AUTH_FAILED); + } + } else { + mbedtls_zeroize(output, length); + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } +} + +void mbedtls_gcm_free(mbedtls_gcm_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + mbedtls_zeroize(ctx, sizeof(mbedtls_gcm_context) ); +} + +#endif /* MBEDTLS_GCM_ALT && MBEDTLS_GCM_C */ + +#endif /* CRYPTOACC_PRESENT */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/error.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/error.c new file mode 100644 index 000000000..2656e13b9 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/error.c @@ -0,0 +1,890 @@ +/* + * Error message information + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#include "mbedtls/error.h" + +#if defined(MBEDTLS_ERROR_C) || defined(MBEDTLS_ERROR_STRERROR_DUMMY) + +#if defined(MBEDTLS_ERROR_C) + +#include "mbedtls/platform.h" + +#include +#include + +#if defined(MBEDTLS_AES_C) +#include "mbedtls/aes.h" +#endif + +#if defined(MBEDTLS_ARIA_C) +#include "mbedtls/aria.h" +#endif + +#if defined(MBEDTLS_ASN1_PARSE_C) +#include "mbedtls/asn1.h" +#endif + +#if defined(MBEDTLS_BASE64_C) +#include "mbedtls/base64.h" +#endif + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +#if defined(MBEDTLS_CAMELLIA_C) +#include "mbedtls/camellia.h" +#endif + +#if defined(MBEDTLS_CCM_C) +#include "mbedtls/ccm.h" +#endif + +#if defined(MBEDTLS_CHACHA20_C) +#include "mbedtls/chacha20.h" +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) +#include "mbedtls/chachapoly.h" +#endif + +#if defined(MBEDTLS_CIPHER_C) +#include "mbedtls/cipher.h" +#endif + +#if defined(MBEDTLS_CTR_DRBG_C) +#include "mbedtls/ctr_drbg.h" +#endif + +#if defined(MBEDTLS_DES_C) +#include "mbedtls/des.h" +#endif + +#if defined(MBEDTLS_DHM_C) +#include "mbedtls/dhm.h" +#endif + +#if defined(MBEDTLS_ECP_C) +#include "mbedtls/ecp.h" +#endif + +#if defined(MBEDTLS_ENTROPY_C) +#include "mbedtls/entropy.h" +#endif + +#if defined(MBEDTLS_ERROR_C) +#include "mbedtls/error.h" +#endif + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#endif + +#if defined(MBEDTLS_GCM_C) +#include "mbedtls/gcm.h" +#endif + +#if defined(MBEDTLS_HKDF_C) +#include "mbedtls/hkdf.h" +#endif + +#if defined(MBEDTLS_HMAC_DRBG_C) +#include "mbedtls/hmac_drbg.h" +#endif + +#if defined(MBEDTLS_LMS_C) +#include "mbedtls/lms.h" +#endif + +#if defined(MBEDTLS_MD_C) +#include "mbedtls/md.h" +#endif + +#if defined(MBEDTLS_NET_C) +#include "mbedtls/net_sockets.h" +#endif + +#if defined(MBEDTLS_OID_C) +#include "mbedtls/oid.h" +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) || defined(MBEDTLS_PEM_WRITE_C) +#include "mbedtls/pem.h" +#endif + +#if defined(MBEDTLS_PK_C) +#include "mbedtls/pk.h" +#endif + +#if defined(MBEDTLS_PKCS12_C) +#include "mbedtls/pkcs12.h" +#endif + +#if defined(MBEDTLS_PKCS5_C) +#include "mbedtls/pkcs5.h" +#endif + +#if defined(MBEDTLS_PKCS7_C) +#include "mbedtls/pkcs7.h" +#endif + +#if defined(MBEDTLS_POLY1305_C) +#include "mbedtls/poly1305.h" +#endif + +#if defined(MBEDTLS_RSA_C) +#include "mbedtls/rsa.h" +#endif + +#if defined(MBEDTLS_SHA1_C) +#include "mbedtls/sha1.h" +#endif + +#if defined(MBEDTLS_SHA256_C) +#include "mbedtls/sha256.h" +#endif + +#if defined(MBEDTLS_SHA3_C) +#include "mbedtls/sha3.h" +#endif + +#if defined(MBEDTLS_SHA512_C) +#include "mbedtls/sha512.h" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) +#include "mbedtls/ssl.h" +#endif + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C) +#include "mbedtls/x509.h" +#endif + + +const char *mbedtls_high_level_strerr(int error_code) +{ + int high_level_error_code; + + if (error_code < 0) { + error_code = -error_code; + } + + /* Extract the high-level part from the error code. */ + high_level_error_code = error_code & 0xFF80; + + switch (high_level_error_code) { + /* Begin Auto-Generated Code. */ + #if defined(MBEDTLS_CIPHER_C) + case -(MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE): + return( "CIPHER - The selected feature is not available" ); + case -(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA): + return( "CIPHER - Bad input parameters" ); + case -(MBEDTLS_ERR_CIPHER_ALLOC_FAILED): + return( "CIPHER - Failed to allocate memory" ); + case -(MBEDTLS_ERR_CIPHER_INVALID_PADDING): + return( "CIPHER - Input data contains invalid padding and is rejected" ); + case -(MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED): + return( "CIPHER - Decryption of block requires a full block" ); + case -(MBEDTLS_ERR_CIPHER_AUTH_FAILED): + return( "CIPHER - Authentication failed (for AEAD modes)" ); + case -(MBEDTLS_ERR_CIPHER_INVALID_CONTEXT): + return( "CIPHER - The context is invalid. For example, because it was freed" ); +#endif /* MBEDTLS_CIPHER_C */ + +#if defined(MBEDTLS_DHM_C) + case -(MBEDTLS_ERR_DHM_BAD_INPUT_DATA): + return( "DHM - Bad input parameters" ); + case -(MBEDTLS_ERR_DHM_READ_PARAMS_FAILED): + return( "DHM - Reading of the DHM parameters failed" ); + case -(MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED): + return( "DHM - Making of the DHM parameters failed" ); + case -(MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED): + return( "DHM - Reading of the public values failed" ); + case -(MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED): + return( "DHM - Making of the public value failed" ); + case -(MBEDTLS_ERR_DHM_CALC_SECRET_FAILED): + return( "DHM - Calculation of the DHM secret failed" ); + case -(MBEDTLS_ERR_DHM_INVALID_FORMAT): + return( "DHM - The ASN.1 data is not formatted correctly" ); + case -(MBEDTLS_ERR_DHM_ALLOC_FAILED): + return( "DHM - Allocation of memory failed" ); + case -(MBEDTLS_ERR_DHM_FILE_IO_ERROR): + return( "DHM - Read or write of file failed" ); + case -(MBEDTLS_ERR_DHM_SET_GROUP_FAILED): + return( "DHM - Setting the modulus and generator failed" ); +#endif /* MBEDTLS_DHM_C */ + +#if defined(MBEDTLS_ECP_C) + case -(MBEDTLS_ERR_ECP_BAD_INPUT_DATA): + return( "ECP - Bad input parameters to function" ); + case -(MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL): + return( "ECP - The buffer is too small to write to" ); + case -(MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE): + return( "ECP - The requested feature is not available, for example, the requested curve is not supported" ); + case -(MBEDTLS_ERR_ECP_VERIFY_FAILED): + return( "ECP - The signature is not valid" ); + case -(MBEDTLS_ERR_ECP_ALLOC_FAILED): + return( "ECP - Memory allocation failed" ); + case -(MBEDTLS_ERR_ECP_RANDOM_FAILED): + return( "ECP - Generation of random value, such as ephemeral key, failed" ); + case -(MBEDTLS_ERR_ECP_INVALID_KEY): + return( "ECP - Invalid private or public key" ); + case -(MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH): + return( "ECP - The buffer contains a valid signature followed by more data" ); + case -(MBEDTLS_ERR_ECP_IN_PROGRESS): + return( "ECP - Operation in progress, call again with the same parameters to continue" ); +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_MD_C) + case -(MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE): + return( "MD - The selected feature is not available" ); + case -(MBEDTLS_ERR_MD_BAD_INPUT_DATA): + return( "MD - Bad input parameters to function" ); + case -(MBEDTLS_ERR_MD_ALLOC_FAILED): + return( "MD - Failed to allocate memory" ); + case -(MBEDTLS_ERR_MD_FILE_IO_ERROR): + return( "MD - Opening or reading of file failed" ); +#endif /* MBEDTLS_MD_C */ + +#if defined(MBEDTLS_PEM_PARSE_C) || defined(MBEDTLS_PEM_WRITE_C) + case -(MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT): + return( "PEM - No PEM header or footer found" ); + case -(MBEDTLS_ERR_PEM_INVALID_DATA): + return( "PEM - PEM string is not as expected" ); + case -(MBEDTLS_ERR_PEM_ALLOC_FAILED): + return( "PEM - Failed to allocate memory" ); + case -(MBEDTLS_ERR_PEM_INVALID_ENC_IV): + return( "PEM - RSA IV is not in hex-format" ); + case -(MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG): + return( "PEM - Unsupported key encryption algorithm" ); + case -(MBEDTLS_ERR_PEM_PASSWORD_REQUIRED): + return( "PEM - Private key password can't be empty" ); + case -(MBEDTLS_ERR_PEM_PASSWORD_MISMATCH): + return( "PEM - Given private key password does not allow for correct decryption" ); + case -(MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE): + return( "PEM - Unavailable feature, e.g. hashing/encryption combination" ); + case -(MBEDTLS_ERR_PEM_BAD_INPUT_DATA): + return( "PEM - Bad input parameters to function" ); +#endif /* MBEDTLS_PEM_PARSE_C || MBEDTLS_PEM_WRITE_C */ + +#if defined(MBEDTLS_PK_C) + case -(MBEDTLS_ERR_PK_ALLOC_FAILED): + return( "PK - Memory allocation failed" ); + case -(MBEDTLS_ERR_PK_TYPE_MISMATCH): + return( "PK - Type mismatch, eg attempt to encrypt with an ECDSA key" ); + case -(MBEDTLS_ERR_PK_BAD_INPUT_DATA): + return( "PK - Bad input parameters to function" ); + case -(MBEDTLS_ERR_PK_FILE_IO_ERROR): + return( "PK - Read/write of file failed" ); + case -(MBEDTLS_ERR_PK_KEY_INVALID_VERSION): + return( "PK - Unsupported key version" ); + case -(MBEDTLS_ERR_PK_KEY_INVALID_FORMAT): + return( "PK - Invalid key tag or value" ); + case -(MBEDTLS_ERR_PK_UNKNOWN_PK_ALG): + return( "PK - Key algorithm is unsupported (only RSA and EC are supported)" ); + case -(MBEDTLS_ERR_PK_PASSWORD_REQUIRED): + return( "PK - Private key password can't be empty" ); + case -(MBEDTLS_ERR_PK_PASSWORD_MISMATCH): + return( "PK - Given private key password does not allow for correct decryption" ); + case -(MBEDTLS_ERR_PK_INVALID_PUBKEY): + return( "PK - The pubkey tag or value is invalid (only RSA and EC are supported)" ); + case -(MBEDTLS_ERR_PK_INVALID_ALG): + return( "PK - The algorithm tag or value is invalid" ); + case -(MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE): + return( "PK - Elliptic curve is unsupported (only NIST curves are supported)" ); + case -(MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE): + return( "PK - Unavailable feature, e.g. RSA disabled for RSA key" ); + case -(MBEDTLS_ERR_PK_SIG_LEN_MISMATCH): + return( "PK - The buffer contains a valid signature followed by more data" ); + case -(MBEDTLS_ERR_PK_BUFFER_TOO_SMALL): + return( "PK - The output buffer is too small" ); +#endif /* MBEDTLS_PK_C */ + +#if defined(MBEDTLS_PKCS12_C) + case -(MBEDTLS_ERR_PKCS12_BAD_INPUT_DATA): + return( "PKCS12 - Bad input parameters to function" ); + case -(MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE): + return( "PKCS12 - Feature not available, e.g. unsupported encryption scheme" ); + case -(MBEDTLS_ERR_PKCS12_PBE_INVALID_FORMAT): + return( "PKCS12 - PBE ASN.1 data not as expected" ); + case -(MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH): + return( "PKCS12 - Given private key password does not allow for correct decryption" ); +#endif /* MBEDTLS_PKCS12_C */ + +#if defined(MBEDTLS_PKCS5_C) + case -(MBEDTLS_ERR_PKCS5_BAD_INPUT_DATA): + return( "PKCS5 - Bad input parameters to function" ); + case -(MBEDTLS_ERR_PKCS5_INVALID_FORMAT): + return( "PKCS5 - Unexpected ASN.1 data" ); + case -(MBEDTLS_ERR_PKCS5_FEATURE_UNAVAILABLE): + return( "PKCS5 - Requested encryption or digest alg not available" ); + case -(MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH): + return( "PKCS5 - Given private key password does not allow for correct decryption" ); +#endif /* MBEDTLS_PKCS5_C */ + +#if defined(MBEDTLS_PKCS7_C) + case -(MBEDTLS_ERR_PKCS7_INVALID_FORMAT): + return( "PKCS7 - The format is invalid, e.g. different type expected" ); + case -(MBEDTLS_ERR_PKCS7_FEATURE_UNAVAILABLE): + return( "PKCS7 - Unavailable feature, e.g. anything other than signed data" ); + case -(MBEDTLS_ERR_PKCS7_INVALID_VERSION): + return( "PKCS7 - The PKCS #7 version element is invalid or cannot be parsed" ); + case -(MBEDTLS_ERR_PKCS7_INVALID_CONTENT_INFO): + return( "PKCS7 - The PKCS #7 content info is invalid or cannot be parsed" ); + case -(MBEDTLS_ERR_PKCS7_INVALID_ALG): + return( "PKCS7 - The algorithm tag or value is invalid or cannot be parsed" ); + case -(MBEDTLS_ERR_PKCS7_INVALID_CERT): + return( "PKCS7 - The certificate tag or value is invalid or cannot be parsed" ); + case -(MBEDTLS_ERR_PKCS7_INVALID_SIGNATURE): + return( "PKCS7 - Error parsing the signature" ); + case -(MBEDTLS_ERR_PKCS7_INVALID_SIGNER_INFO): + return( "PKCS7 - Error parsing the signer's info" ); + case -(MBEDTLS_ERR_PKCS7_BAD_INPUT_DATA): + return( "PKCS7 - Input invalid" ); + case -(MBEDTLS_ERR_PKCS7_ALLOC_FAILED): + return( "PKCS7 - Allocation of memory failed" ); + case -(MBEDTLS_ERR_PKCS7_VERIFY_FAIL): + return( "PKCS7 - Verification Failed" ); + case -(MBEDTLS_ERR_PKCS7_CERT_DATE_INVALID): + return( "PKCS7 - The PKCS #7 date issued/expired dates are invalid" ); +#endif /* MBEDTLS_PKCS7_C */ + +#if defined(MBEDTLS_RSA_C) + case -(MBEDTLS_ERR_RSA_BAD_INPUT_DATA): + return( "RSA - Bad input parameters to function" ); + case -(MBEDTLS_ERR_RSA_INVALID_PADDING): + return( "RSA - Input data contains invalid padding and is rejected" ); + case -(MBEDTLS_ERR_RSA_KEY_GEN_FAILED): + return( "RSA - Something failed during generation of a key" ); + case -(MBEDTLS_ERR_RSA_KEY_CHECK_FAILED): + return( "RSA - Key failed to pass the validity check of the library" ); + case -(MBEDTLS_ERR_RSA_PUBLIC_FAILED): + return( "RSA - The public key operation failed" ); + case -(MBEDTLS_ERR_RSA_PRIVATE_FAILED): + return( "RSA - The private key operation failed" ); + case -(MBEDTLS_ERR_RSA_VERIFY_FAILED): + return( "RSA - The PKCS#1 verification failed" ); + case -(MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE): + return( "RSA - The output buffer for decryption is not large enough" ); + case -(MBEDTLS_ERR_RSA_RNG_FAILED): + return( "RSA - The random generator failed to generate non-zeros" ); +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_SSL_TLS_C) + case -(MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS): + return( "SSL - A cryptographic operation is in progress. Try again later" ); + case -(MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE): + return( "SSL - The requested feature is not available" ); + case -(MBEDTLS_ERR_SSL_BAD_INPUT_DATA): + return( "SSL - Bad input parameters to function" ); + case -(MBEDTLS_ERR_SSL_INVALID_MAC): + return( "SSL - Verification of the message MAC failed" ); + case -(MBEDTLS_ERR_SSL_INVALID_RECORD): + return( "SSL - An invalid SSL record was received" ); + case -(MBEDTLS_ERR_SSL_CONN_EOF): + return( "SSL - The connection indicated an EOF" ); + case -(MBEDTLS_ERR_SSL_DECODE_ERROR): + return( "SSL - A message could not be parsed due to a syntactic error" ); + case -(MBEDTLS_ERR_SSL_NO_RNG): + return( "SSL - No RNG was provided to the SSL module" ); + case -(MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE): + return( "SSL - No client certification received from the client, but required by the authentication mode" ); + case -(MBEDTLS_ERR_SSL_UNSUPPORTED_EXTENSION): + return( "SSL - Client received an extended server hello containing an unsupported extension" ); + case -(MBEDTLS_ERR_SSL_NO_APPLICATION_PROTOCOL): + return( "SSL - No ALPN protocols supported that the client advertises" ); + case -(MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED): + return( "SSL - The own private key or pre-shared key is not set, but needed" ); + case -(MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED): + return( "SSL - No CA Chain is set, but required to operate" ); + case -(MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE): + return( "SSL - An unexpected message was received from our peer" ); + case -(MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE): + return( "SSL - A fatal alert message was received from our peer" ); + case -(MBEDTLS_ERR_SSL_UNRECOGNIZED_NAME): + return( "SSL - No server could be identified matching the client's SNI" ); + case -(MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY): + return( "SSL - The peer notified us that the connection is going to be closed" ); + case -(MBEDTLS_ERR_SSL_BAD_CERTIFICATE): + return( "SSL - Processing of the Certificate handshake message failed" ); + case -(MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET): + return( "SSL - * Received NewSessionTicket Post Handshake Message. This error code is experimental and may be changed or removed without notice" ); + case -(MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA): + return( "SSL - Not possible to read early data" ); + case -(MBEDTLS_ERR_SSL_CANNOT_WRITE_EARLY_DATA): + return( "SSL - Not possible to write early data" ); + case -(MBEDTLS_ERR_SSL_CACHE_ENTRY_NOT_FOUND): + return( "SSL - Cache entry not found" ); + case -(MBEDTLS_ERR_SSL_ALLOC_FAILED): + return( "SSL - Memory allocation failed" ); + case -(MBEDTLS_ERR_SSL_HW_ACCEL_FAILED): + return( "SSL - Hardware acceleration function returned with error" ); + case -(MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH): + return( "SSL - Hardware acceleration function skipped / left alone data" ); + case -(MBEDTLS_ERR_SSL_BAD_PROTOCOL_VERSION): + return( "SSL - Handshake protocol not within min/max boundaries" ); + case -(MBEDTLS_ERR_SSL_HANDSHAKE_FAILURE): + return( "SSL - The handshake negotiation failed" ); + case -(MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED): + return( "SSL - Session ticket has expired" ); + case -(MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH): + return( "SSL - Public key type mismatch (eg, asked for RSA key exchange and presented EC key)" ); + case -(MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY): + return( "SSL - Unknown identity received (eg, PSK identity)" ); + case -(MBEDTLS_ERR_SSL_INTERNAL_ERROR): + return( "SSL - Internal error (eg, unexpected failure in lower-level module)" ); + case -(MBEDTLS_ERR_SSL_COUNTER_WRAPPING): + return( "SSL - A counter would wrap (eg, too many messages exchanged)" ); + case -(MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO): + return( "SSL - Unexpected message at ServerHello in renegotiation" ); + case -(MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED): + return( "SSL - DTLS client must retry for hello verification" ); + case -(MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL): + return( "SSL - A buffer is too small to receive or write a message" ); + case -(MBEDTLS_ERR_SSL_WANT_READ): + return( "SSL - No data of requested type currently available on underlying transport" ); + case -(MBEDTLS_ERR_SSL_WANT_WRITE): + return( "SSL - Connection requires a write call" ); + case -(MBEDTLS_ERR_SSL_TIMEOUT): + return( "SSL - The operation timed out" ); + case -(MBEDTLS_ERR_SSL_CLIENT_RECONNECT): + return( "SSL - The client initiated a reconnect from the same port" ); + case -(MBEDTLS_ERR_SSL_UNEXPECTED_RECORD): + return( "SSL - Record header looks valid but is not expected" ); + case -(MBEDTLS_ERR_SSL_NON_FATAL): + return( "SSL - The alert message received indicates a non-fatal error" ); + case -(MBEDTLS_ERR_SSL_ILLEGAL_PARAMETER): + return( "SSL - A field in a message was incorrect or inconsistent with other fields" ); + case -(MBEDTLS_ERR_SSL_CONTINUE_PROCESSING): + return( "SSL - Internal-only message signaling that further message-processing should be done" ); + case -(MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS): + return( "SSL - The asynchronous operation is not completed yet" ); + case -(MBEDTLS_ERR_SSL_EARLY_MESSAGE): + return( "SSL - Internal-only message signaling that a message arrived early" ); + case -(MBEDTLS_ERR_SSL_UNEXPECTED_CID): + return( "SSL - An encrypted DTLS-frame with an unexpected CID was received" ); + case -(MBEDTLS_ERR_SSL_VERSION_MISMATCH): + return( "SSL - An operation failed due to an unexpected version or configuration" ); + case -(MBEDTLS_ERR_SSL_BAD_CONFIG): + return( "SSL - Invalid value in SSL config" ); +#endif /* MBEDTLS_SSL_TLS_C */ + +#if defined(MBEDTLS_X509_USE_C) || defined(MBEDTLS_X509_CREATE_C) + case -(MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE): + return( "X509 - Unavailable feature, e.g. RSA hashing/encryption combination" ); + case -(MBEDTLS_ERR_X509_UNKNOWN_OID): + return( "X509 - Requested OID is unknown" ); + case -(MBEDTLS_ERR_X509_INVALID_FORMAT): + return( "X509 - The CRT/CRL/CSR format is invalid, e.g. different type expected" ); + case -(MBEDTLS_ERR_X509_INVALID_VERSION): + return( "X509 - The CRT/CRL/CSR version element is invalid" ); + case -(MBEDTLS_ERR_X509_INVALID_SERIAL): + return( "X509 - The serial tag or value is invalid" ); + case -(MBEDTLS_ERR_X509_INVALID_ALG): + return( "X509 - The algorithm tag or value is invalid" ); + case -(MBEDTLS_ERR_X509_INVALID_NAME): + return( "X509 - The name tag or value is invalid" ); + case -(MBEDTLS_ERR_X509_INVALID_DATE): + return( "X509 - The date tag or value is invalid" ); + case -(MBEDTLS_ERR_X509_INVALID_SIGNATURE): + return( "X509 - The signature tag or value invalid" ); + case -(MBEDTLS_ERR_X509_INVALID_EXTENSIONS): + return( "X509 - The extension tag or value is invalid" ); + case -(MBEDTLS_ERR_X509_UNKNOWN_VERSION): + return( "X509 - CRT/CRL/CSR has an unsupported version number" ); + case -(MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG): + return( "X509 - Signature algorithm (oid) is unsupported" ); + case -(MBEDTLS_ERR_X509_SIG_MISMATCH): + return( "X509 - Signature algorithms do not match. (see \\c ::mbedtls_x509_crt sig_oid)" ); + case -(MBEDTLS_ERR_X509_CERT_VERIFY_FAILED): + return( "X509 - Certificate verification failed, e.g. CRL, CA or signature check failed" ); + case -(MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT): + return( "X509 - Format not recognized as DER or PEM" ); + case -(MBEDTLS_ERR_X509_BAD_INPUT_DATA): + return( "X509 - Input invalid" ); + case -(MBEDTLS_ERR_X509_ALLOC_FAILED): + return( "X509 - Allocation of memory failed" ); + case -(MBEDTLS_ERR_X509_FILE_IO_ERROR): + return( "X509 - Read/write of file failed" ); + case -(MBEDTLS_ERR_X509_BUFFER_TOO_SMALL): + return( "X509 - Destination buffer is too small" ); + case -(MBEDTLS_ERR_X509_FATAL_ERROR): + return( "X509 - A fatal error occurred, eg the chain is too long or the vrfy callback failed" ); +#endif /* MBEDTLS_X509_USE_C || MBEDTLS_X509_CREATE_C */ + /* End Auto-Generated Code. */ + + default: + break; + } + + return NULL; +} + +const char *mbedtls_low_level_strerr(int error_code) +{ + int low_level_error_code; + + if (error_code < 0) { + error_code = -error_code; + } + + /* Extract the low-level part from the error code. */ + low_level_error_code = error_code & ~0xFF80; + + switch (low_level_error_code) { + /* Begin Auto-Generated Code. */ + #if defined(MBEDTLS_AES_C) + case -(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH): + return( "AES - Invalid key length" ); + case -(MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH): + return( "AES - Invalid data input length" ); + case -(MBEDTLS_ERR_AES_BAD_INPUT_DATA): + return( "AES - Invalid input data" ); +#endif /* MBEDTLS_AES_C */ + +#if defined(MBEDTLS_ARIA_C) + case -(MBEDTLS_ERR_ARIA_BAD_INPUT_DATA): + return( "ARIA - Bad input data" ); + case -(MBEDTLS_ERR_ARIA_INVALID_INPUT_LENGTH): + return( "ARIA - Invalid data input length" ); +#endif /* MBEDTLS_ARIA_C */ + +#if defined(MBEDTLS_ASN1_PARSE_C) + case -(MBEDTLS_ERR_ASN1_OUT_OF_DATA): + return( "ASN1 - Out of data when parsing an ASN1 data structure" ); + case -(MBEDTLS_ERR_ASN1_UNEXPECTED_TAG): + return( "ASN1 - ASN1 tag was of an unexpected value" ); + case -(MBEDTLS_ERR_ASN1_INVALID_LENGTH): + return( "ASN1 - Error when trying to determine the length or invalid length" ); + case -(MBEDTLS_ERR_ASN1_LENGTH_MISMATCH): + return( "ASN1 - Actual length differs from expected length" ); + case -(MBEDTLS_ERR_ASN1_INVALID_DATA): + return( "ASN1 - Data is invalid" ); + case -(MBEDTLS_ERR_ASN1_ALLOC_FAILED): + return( "ASN1 - Memory allocation failed" ); + case -(MBEDTLS_ERR_ASN1_BUF_TOO_SMALL): + return( "ASN1 - Buffer too small when writing ASN.1 data structure" ); +#endif /* MBEDTLS_ASN1_PARSE_C */ + +#if defined(MBEDTLS_BASE64_C) + case -(MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL): + return( "BASE64 - Output buffer too small" ); + case -(MBEDTLS_ERR_BASE64_INVALID_CHARACTER): + return( "BASE64 - Invalid character in input" ); +#endif /* MBEDTLS_BASE64_C */ + +#if defined(MBEDTLS_BIGNUM_C) + case -(MBEDTLS_ERR_MPI_FILE_IO_ERROR): + return( "BIGNUM - An error occurred while reading from or writing to a file" ); + case -(MBEDTLS_ERR_MPI_BAD_INPUT_DATA): + return( "BIGNUM - Bad input parameters to function" ); + case -(MBEDTLS_ERR_MPI_INVALID_CHARACTER): + return( "BIGNUM - There is an invalid character in the digit string" ); + case -(MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL): + return( "BIGNUM - The buffer is too small to write to" ); + case -(MBEDTLS_ERR_MPI_NEGATIVE_VALUE): + return( "BIGNUM - The input arguments are negative or result in illegal output" ); + case -(MBEDTLS_ERR_MPI_DIVISION_BY_ZERO): + return( "BIGNUM - The input argument for division is zero, which is not allowed" ); + case -(MBEDTLS_ERR_MPI_NOT_ACCEPTABLE): + return( "BIGNUM - The input arguments are not acceptable" ); + case -(MBEDTLS_ERR_MPI_ALLOC_FAILED): + return( "BIGNUM - Memory allocation failed" ); +#endif /* MBEDTLS_BIGNUM_C */ + +#if defined(MBEDTLS_CAMELLIA_C) + case -(MBEDTLS_ERR_CAMELLIA_BAD_INPUT_DATA): + return( "CAMELLIA - Bad input data" ); + case -(MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH): + return( "CAMELLIA - Invalid data input length" ); +#endif /* MBEDTLS_CAMELLIA_C */ + +#if defined(MBEDTLS_CCM_C) + case -(MBEDTLS_ERR_CCM_BAD_INPUT): + return( "CCM - Bad input parameters to the function" ); + case -(MBEDTLS_ERR_CCM_AUTH_FAILED): + return( "CCM - Authenticated decryption failed" ); +#endif /* MBEDTLS_CCM_C */ + +#if defined(MBEDTLS_CHACHA20_C) + case -(MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA): + return( "CHACHA20 - Invalid input parameter(s)" ); +#endif /* MBEDTLS_CHACHA20_C */ + +#if defined(MBEDTLS_CHACHAPOLY_C) + case -(MBEDTLS_ERR_CHACHAPOLY_BAD_STATE): + return( "CHACHAPOLY - The requested operation is not permitted in the current state" ); + case -(MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED): + return( "CHACHAPOLY - Authenticated decryption failed: data was not authentic" ); +#endif /* MBEDTLS_CHACHAPOLY_C */ + +#if defined(MBEDTLS_CTR_DRBG_C) + case -(MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED): + return( "CTR_DRBG - The entropy source failed" ); + case -(MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG): + return( "CTR_DRBG - The requested random buffer length is too big" ); + case -(MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG): + return( "CTR_DRBG - The input (entropy + additional data) is too large" ); + case -(MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR): + return( "CTR_DRBG - Read or write error in file" ); +#endif /* MBEDTLS_CTR_DRBG_C */ + +#if defined(MBEDTLS_DES_C) + case -(MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH): + return( "DES - The data input has an invalid length" ); +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_ENTROPY_C) + case -(MBEDTLS_ERR_ENTROPY_SOURCE_FAILED): + return( "ENTROPY - Critical entropy source failure" ); + case -(MBEDTLS_ERR_ENTROPY_MAX_SOURCES): + return( "ENTROPY - No more sources can be added" ); + case -(MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED): + return( "ENTROPY - No sources have been added to poll" ); + case -(MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE): + return( "ENTROPY - No strong sources have been added to poll" ); + case -(MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR): + return( "ENTROPY - Read/write error in file" ); +#endif /* MBEDTLS_ENTROPY_C */ + +#if defined(MBEDTLS_ERROR_C) + case -(MBEDTLS_ERR_ERROR_GENERIC_ERROR): + return( "ERROR - Generic error" ); + case -(MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED): + return( "ERROR - This is a bug in the library" ); +#endif /* MBEDTLS_ERROR_C */ + +#if defined(MBEDTLS_PLATFORM_C) + case -(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED): + return( "PLATFORM - Hardware accelerator failed" ); + case -(MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED): + return( "PLATFORM - The requested feature is not supported by the platform" ); +#endif /* MBEDTLS_PLATFORM_C */ + +#if defined(MBEDTLS_GCM_C) + case -(MBEDTLS_ERR_GCM_AUTH_FAILED): + return( "GCM - Authenticated decryption failed" ); + case -(MBEDTLS_ERR_GCM_BAD_INPUT): + return( "GCM - Bad input parameters to function" ); + case -(MBEDTLS_ERR_GCM_BUFFER_TOO_SMALL): + return( "GCM - An output buffer is too small" ); +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_HKDF_C) + case -(MBEDTLS_ERR_HKDF_BAD_INPUT_DATA): + return( "HKDF - Bad input parameters to function" ); +#endif /* MBEDTLS_HKDF_C */ + +#if defined(MBEDTLS_HMAC_DRBG_C) + case -(MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG): + return( "HMAC_DRBG - Too many random requested in single call" ); + case -(MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG): + return( "HMAC_DRBG - Input too large (Entropy + additional)" ); + case -(MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR): + return( "HMAC_DRBG - Read/write error in file" ); + case -(MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED): + return( "HMAC_DRBG - The entropy source failed" ); +#endif /* MBEDTLS_HMAC_DRBG_C */ + +#if defined(MBEDTLS_LMS_C) + case -(MBEDTLS_ERR_LMS_BAD_INPUT_DATA): + return( "LMS - Bad data has been input to an LMS function" ); + case -(MBEDTLS_ERR_LMS_OUT_OF_PRIVATE_KEYS): + return( "LMS - Specified LMS key has utilised all of its private keys" ); + case -(MBEDTLS_ERR_LMS_VERIFY_FAILED): + return( "LMS - LMS signature verification failed" ); + case -(MBEDTLS_ERR_LMS_ALLOC_FAILED): + return( "LMS - LMS failed to allocate space for a private key" ); + case -(MBEDTLS_ERR_LMS_BUFFER_TOO_SMALL): + return( "LMS - Input/output buffer is too small to contain requited data" ); +#endif /* MBEDTLS_LMS_C */ + +#if defined(MBEDTLS_NET_C) + case -(MBEDTLS_ERR_NET_SOCKET_FAILED): + return( "NET - Failed to open a socket" ); + case -(MBEDTLS_ERR_NET_CONNECT_FAILED): + return( "NET - The connection to the given server / port failed" ); + case -(MBEDTLS_ERR_NET_BIND_FAILED): + return( "NET - Binding of the socket failed" ); + case -(MBEDTLS_ERR_NET_LISTEN_FAILED): + return( "NET - Could not listen on the socket" ); + case -(MBEDTLS_ERR_NET_ACCEPT_FAILED): + return( "NET - Could not accept the incoming connection" ); + case -(MBEDTLS_ERR_NET_RECV_FAILED): + return( "NET - Reading information from the socket failed" ); + case -(MBEDTLS_ERR_NET_SEND_FAILED): + return( "NET - Sending information through the socket failed" ); + case -(MBEDTLS_ERR_NET_CONN_RESET): + return( "NET - Connection was reset by peer" ); + case -(MBEDTLS_ERR_NET_UNKNOWN_HOST): + return( "NET - Failed to get an IP address for the given hostname" ); + case -(MBEDTLS_ERR_NET_BUFFER_TOO_SMALL): + return( "NET - Buffer is too small to hold the data" ); + case -(MBEDTLS_ERR_NET_INVALID_CONTEXT): + return( "NET - The context is invalid, eg because it was free()ed" ); + case -(MBEDTLS_ERR_NET_POLL_FAILED): + return( "NET - Polling the net context failed" ); + case -(MBEDTLS_ERR_NET_BAD_INPUT_DATA): + return( "NET - Input invalid" ); +#endif /* MBEDTLS_NET_C */ + +#if defined(MBEDTLS_OID_C) + case -(MBEDTLS_ERR_OID_NOT_FOUND): + return( "OID - OID is not found" ); + case -(MBEDTLS_ERR_OID_BUF_TOO_SMALL): + return( "OID - output buffer is too small" ); +#endif /* MBEDTLS_OID_C */ + +#if defined(MBEDTLS_POLY1305_C) + case -(MBEDTLS_ERR_POLY1305_BAD_INPUT_DATA): + return( "POLY1305 - Invalid input parameter(s)" ); +#endif /* MBEDTLS_POLY1305_C */ + +#if defined(MBEDTLS_SHA1_C) + case -(MBEDTLS_ERR_SHA1_BAD_INPUT_DATA): + return( "SHA1 - SHA-1 input data was malformed" ); +#endif /* MBEDTLS_SHA1_C */ + +#if defined(MBEDTLS_SHA256_C) + case -(MBEDTLS_ERR_SHA256_BAD_INPUT_DATA): + return( "SHA256 - SHA-256 input data was malformed" ); +#endif /* MBEDTLS_SHA256_C */ + +#if defined(MBEDTLS_SHA3_C) + case -(MBEDTLS_ERR_SHA3_BAD_INPUT_DATA): + return( "SHA3 - SHA-3 input data was malformed" ); +#endif /* MBEDTLS_SHA3_C */ + +#if defined(MBEDTLS_SHA512_C) + case -(MBEDTLS_ERR_SHA512_BAD_INPUT_DATA): + return( "SHA512 - SHA-512 input data was malformed" ); +#endif /* MBEDTLS_SHA512_C */ + +#if defined(MBEDTLS_THREADING_C) + case -(MBEDTLS_ERR_THREADING_BAD_INPUT_DATA): + return( "THREADING - Bad input parameters to function" ); + case -(MBEDTLS_ERR_THREADING_MUTEX_ERROR): + return( "THREADING - Locking / unlocking / free failed with error code" ); +#endif /* MBEDTLS_THREADING_C */ + /* End Auto-Generated Code. */ + + default: + break; + } + + return NULL; +} + +void mbedtls_strerror(int ret, char *buf, size_t buflen) +{ + size_t len; + int use_ret; + const char *high_level_error_description = NULL; + const char *low_level_error_description = NULL; + + if (buflen == 0) { + return; + } + + memset(buf, 0x00, buflen); + + if (ret < 0) { + ret = -ret; + } + + if (ret & 0xFF80) { + use_ret = ret & 0xFF80; + + // Translate high level error code. + high_level_error_description = mbedtls_high_level_strerr(ret); + + if (high_level_error_description == NULL) { + mbedtls_snprintf(buf, buflen, "UNKNOWN ERROR CODE (%04X)", (unsigned int) use_ret); + } else { + mbedtls_snprintf(buf, buflen, "%s", high_level_error_description); + } + +#if defined(MBEDTLS_SSL_TLS_C) + // Early return in case of a fatal error - do not try to translate low + // level code. + if (use_ret == -(MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE)) { + return; + } +#endif /* MBEDTLS_SSL_TLS_C */ + } + + use_ret = ret & ~0xFF80; + + if (use_ret == 0) { + return; + } + + // If high level code is present, make a concatenation between both + // error strings. + // + len = strlen(buf); + + if (len > 0) { + if (buflen - len < 5) { + return; + } + + mbedtls_snprintf(buf + len, buflen - len, " : "); + + buf += len + 3; + buflen -= len + 3; + } + + // Translate low level error code. + low_level_error_description = mbedtls_low_level_strerr(ret); + + if (low_level_error_description == NULL) { + mbedtls_snprintf(buf, buflen, "UNKNOWN ERROR CODE (%04X)", (unsigned int) use_ret); + } else { + mbedtls_snprintf(buf, buflen, "%s", low_level_error_description); + } +} + +#else /* MBEDTLS_ERROR_C */ + +/* + * Provide a dummy implementation when MBEDTLS_ERROR_C is not defined + */ +void mbedtls_strerror(int ret, char *buf, size_t buflen) +{ + ((void) ret); + + if (buflen > 0) { + buf[0] = '\0'; + } +} + +#endif /* MBEDTLS_ERROR_C */ + +#if defined(MBEDTLS_TEST_HOOKS) +void (*mbedtls_test_hook_error_add)(int, int, const char *, int); +#endif + +#endif /* MBEDTLS_ERROR_C || MBEDTLS_ERROR_STRERROR_DUMMY */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c new file mode 100644 index 000000000..b50356a6a --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c @@ -0,0 +1,344 @@ +/***************************************************************************//** + * @file + * @brief AES-CCM abstraction based on PSA accelerators + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of various functions in + * ccm.c, using the accelerators incorporated in devices from Silicon Labs. + * + * This alternative implementation calls the PSA Crypto drivers provided + * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. + */ + +#include + +#if defined(MBEDTLS_AES_C) && defined(MBEDTLS_CCM_C) && defined(MBEDTLS_CCM_ALT) + +#include "mbedtls/ccm.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#if defined(MBEDTLS_SELF_TEST) +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_SELF_TEST */ +#endif /* MBEDTLS_PLATFORM_C */ + +#include "psa/crypto.h" + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_functions.h" +#define AEAD_IMPLEMENTATION_PRESENT +#define SLI_DEVICE_HAS_AES_192 +#define AEAD_ENCRYPT_TAG_FCT sli_se_driver_aead_encrypt_tag +#define AEAD_DECRYPT_TAG_FCT sli_se_driver_aead_decrypt_tag +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_functions.h" +#define AEAD_IMPLEMENTATION_PRESENT +#define SLI_DEVICE_HAS_AES_192 +#define AEAD_ENCRYPT_TAG_FCT sli_cryptoacc_transparent_aead_encrypt_tag +#define AEAD_DECRYPT_TAG_FCT sli_cryptoacc_transparent_aead_decrypt_tag +#elif defined(SLI_CRYPTOACC_PRESENT_SI91X) +#include "sli_si91x_crypto_driver_functions.h" +#define AEAD_IMPLEMENTATION_PRESENT +#define AEAD_ENCRYPT_TAG_FCT sl_si91x_crypto_aead_encrypt +#define AEAD_DECRYPT_TAG_FCT sl_si91x_crypto_aead_decrypt +#endif + +#if defined(AEAD_IMPLEMENTATION_PRESENT) + +#include + +static int psa_status_to_mbedtls(psa_status_t status) +{ + switch ( status ) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_INVALID_SIGNATURE: + return MBEDTLS_ERR_CCM_AUTH_FAILED; + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + default: + return MBEDTLS_ERR_CCM_BAD_INPUT; + } +} + +/* + * Initialize CCM context + */ +void mbedtls_ccm_init(mbedtls_ccm_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_ccm_context) ); +} + +/* + * Clear CCM context + */ +void mbedtls_ccm_free(mbedtls_ccm_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_ccm_context) ); +} + +/* + * CCM key schedule + */ +int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits) +{ + if (ctx == NULL || key == NULL) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + memset(ctx, 0, sizeof(mbedtls_ccm_context) ); + + if ( cipher != MBEDTLS_CIPHER_ID_AES ) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + if ( (128UL != keybits) && (192UL != keybits) && (256UL != keybits) ) { + /* Unsupported key size */ + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + #if !defined(SLI_DEVICE_HAS_AES_192) + if (192UL == keybits) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + #endif + + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +int mbedtls_ccm_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len) +{ + // 'Regular' CCM always outputs a tag of at least 4 bytes + if (tag_len < 4) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + return mbedtls_ccm_star_encrypt_and_tag(ctx, length, iv, iv_len, add, add_len, + input, output, tag, tag_len); +} + +int mbedtls_ccm_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len) +{ + // 'Regular' CCM always verifies a tag of at least 4 bytes + if (tag_len < 4) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + return mbedtls_ccm_star_auth_decrypt(ctx, length, iv, iv_len, add, add_len, + input, output, tag, tag_len); +} + +int mbedtls_ccm_star_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len) +{ + if ( ctx == NULL || iv == NULL || iv_len == 0 + || (add_len > 0 && add == NULL) || add_len >= 0xFF00 + || (length > 0 && input == NULL) || length >= 0xFF00 + || (length > 0 && output == NULL) + || (tag_len > 0 && tag == NULL) ) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + psa_status_t psa_status; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attr, ctx->keybits); + + if (tag_len > 0) { + psa_status = AEAD_ENCRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, tag_len), + iv, iv_len, + add, add_len, + input, length, + output, length, &length, + tag, tag_len, &tag_len); + } else { + (void) tag; + uint8_t dummy_tag[4]; + psa_status = AEAD_ENCRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, sizeof(dummy_tag)), + iv, iv_len, + add, add_len, + input, length, + output, length, &length, + dummy_tag, sizeof(dummy_tag), &tag_len); + } + + psa_reset_key_attributes(&attr); + return psa_status_to_mbedtls(psa_status); +} + +int mbedtls_ccm_star_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len) +{ + if ( ctx == NULL || iv == NULL || iv_len == 0 + || (add_len > 0 && add == NULL) || add_len >= 0xFF00 + || (length > 0 && input == NULL) || length >= 0xFF00 + || (length > 0 && output == NULL) + || (tag_len > 0 && tag == NULL) ) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + psa_status_t psa_status; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attr, ctx->keybits); + + if (tag_len > 0) { + psa_status = AEAD_DECRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, tag_len), + iv, iv_len, + add, add_len, + input, length, + tag, tag_len, + output, length, &length); + } else { + // CCM(*) is symmetric in encryption/decryption of the data, so if we don't have + // to verify a tag we can transform ciphertext to plaintext by running an + // 'encrypt' operation and throwing away the tag. + (void) tag; + uint8_t dummy_tag[4]; + psa_status = AEAD_ENCRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, sizeof(dummy_tag)), + iv, iv_len, + add, add_len, + input, length, + output, length, &length, + dummy_tag, sizeof(dummy_tag), &tag_len); + } + + psa_reset_key_attributes(&attr); + return psa_status_to_mbedtls(psa_status); +} + +/* Provide stubs for linkage purposes. To be implemented when implementing + * support for multipart AEAD in the PSA drivers, see [PSEC-3221] */ +int mbedtls_ccm_starts(mbedtls_ccm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len) +{ + (void) ctx; + (void) mode; + (void) iv; + (void) iv_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_set_lengths(mbedtls_ccm_context *ctx, + size_t total_ad_len, + size_t plaintext_len, + size_t tag_len) +{ + (void) ctx; + (void) total_ad_len; + (void) plaintext_len; + (void) tag_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_update_ad(mbedtls_ccm_context *ctx, + const unsigned char *ad, + size_t ad_len) +{ + (void) ctx; + (void) ad; + (void) ad_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_update(mbedtls_ccm_context *ctx, + const unsigned char *input, size_t input_len, + unsigned char *output, size_t output_size, + size_t *output_len) +{ + (void) ctx; + (void) input; + (void) input_len; + (void) output; + (void) output_size; + (void) output_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_finish(mbedtls_ccm_context *ctx, + unsigned char *tag, size_t tag_len) +{ + (void) ctx; + (void) tag; + (void) tag_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +#endif /* AEAD_IMPLEMENTATION_PRESENT */ + +#endif /* MBEDTLS_AES_C && MBEDTLS_CCM_C && MBEDTLS_CCM_ALT */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c new file mode 100644 index 000000000..666242862 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c @@ -0,0 +1,403 @@ +/***************************************************************************//** + * @file + * @brief AES-CMAC abstraction based on PSA accelerators + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of various functions in + * cmac.c, using the accelerators incorporated in devices from Silicon Labs. + * + * This alternative implementation calls the PSA Crypto drivers provided + * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. + */ + +#include + +#if defined (MBEDTLS_CMAC_C) && defined(MBEDTLS_CMAC_ALT) + +#include "mbedtls/cmac.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#if defined(MBEDTLS_SELF_TEST) +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_SELF_TEST */ +#endif /* MBEDTLS_PLATFORM_C */ + +#include "psa/crypto.h" + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_functions.h" +#define SLI_DEVICE_HAS_AES_192 +#define MAC_IMPLEMENTATION_PRESENT +#define MAC_SETUP_EN_FCT sli_se_transparent_mac_sign_setup +#define MAC_SETUP_DE_FCT sli_se_transparent_mac_verify_setup +#define MAC_UPDATE_FCT sli_se_transparent_mac_update +#define MAC_FINISH_EN_FCT sli_se_transparent_mac_sign_finish +#define MAC_FINISH_DE_FCT sli_se_transparent_mac_verify_finish +#define MAC_ABORT_FCT sli_se_transparent_mac_abort +#define MAC_ONESHOT_EN_FCT sli_se_transparent_mac_compute +#define MAC_ONESHOT_DE_FCT sli_se_transparent_mac_verify + +#if defined(RADIOAES_PRESENT) +#include "sli_protocol_crypto.h" +#endif +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_functions.h" +#define SLI_DEVICE_HAS_AES_192 +#define MAC_IMPLEMENTATION_PRESENT +#define MAC_SETUP_EN_FCT sli_cryptoacc_transparent_mac_sign_setup +#define MAC_SETUP_DE_FCT sli_cryptoacc_transparent_mac_verify_setup +#define MAC_UPDATE_FCT sli_cryptoacc_transparent_mac_update +#define MAC_FINISH_EN_FCT sli_cryptoacc_transparent_mac_sign_finish +#define MAC_FINISH_DE_FCT sli_cryptoacc_transparent_mac_verify_finish +#define MAC_ABORT_FCT sli_cryptoacc_transparent_mac_abort +#define MAC_ONESHOT_EN_FCT sli_cryptoacc_transparent_mac_compute +#define MAC_ONESHOT_DE_FCT sli_cryptoacc_transparent_mac_verify +#endif + +#if defined(MAC_IMPLEMENTATION_PRESENT) + +#include + +static int psa_status_to_mbedtls(psa_status_t status) +{ + switch ( status ) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + default: + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } +} + +static inline void sl_psa_set_key_type(psa_key_attributes_t *attributes, + psa_key_type_t type) +{ + /* Common case: quick path */ + attributes->MBEDTLS_PRIVATE(type) = type; +} + +int mbedtls_cipher_cmac_starts(mbedtls_cipher_context_t *ctx, + const unsigned char *key, size_t keybits) +{ + mbedtls_cipher_type_t type; + mbedtls_cmac_context_t *cmac_ctx; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || key == NULL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + type = (mbedtls_cipher_type_t)ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(type); + + switch ( type ) { + case MBEDTLS_CIPHER_AES_128_ECB: + psa_set_key_bits(&attr, 128); + break; + case MBEDTLS_CIPHER_AES_192_ECB: + #if defined(SLI_DEVICE_HAS_AES_192) + psa_set_key_bits(&attr, 192); + #else + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + #endif + break; + case MBEDTLS_CIPHER_AES_256_ECB: + psa_set_key_bits(&attr, 256); + break; + default: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + if ( ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { + /* Allocate CMAC context memory if it hasn't already been allocated */ + cmac_ctx = mbedtls_calloc(1, sizeof(struct mbedtls_cmac_context_t) ); + if ( cmac_ctx == NULL ) { + return(MBEDTLS_ERR_CIPHER_ALLOC_FAILED); + } + + ctx->MBEDTLS_PRIVATE(cmac_ctx) = cmac_ctx; + } else { + mbedtls_platform_zeroize(ctx->MBEDTLS_PRIVATE(cmac_ctx), sizeof(*ctx->MBEDTLS_PRIVATE(cmac_ctx)) ); + } + + return psa_status_to_mbedtls( + MAC_SETUP_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + &attr, + key, + keybits / 8U, + PSA_ALG_CMAC) ); +} + +int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, + const unsigned char *input, size_t ilen) +{ + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || input == NULL + || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + return psa_status_to_mbedtls( + MAC_UPDATE_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + input, + ilen) ); +} + +int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, + unsigned char *output) +{ + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL + || output == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + size_t olen = 0; + + return psa_status_to_mbedtls( + MAC_FINISH_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + output, + MBEDTLS_AES_BLOCK_SIZE, + &olen) ); +} + +int mbedtls_cipher_cmac_reset(mbedtls_cipher_context_t *ctx) +{ + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + uint8_t key[32]; + size_t key_len; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + + if ( ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len > sizeof(key) ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + /* Save the key to be able to restart the operation */ + memcpy(key, + ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key, + ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len); + key_len = ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len; + psa_set_key_bits(&attr, key_len * 8); + + /* Abort and restart with the same key */ + MAC_ABORT_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx); + return psa_status_to_mbedtls( + MAC_SETUP_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + &attr, + key, + key_len, + PSA_ALG_CMAC) ); +} + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) +/* For speeding up PBKDF2-CMAC, which needs a lot of iterations with small-size + * CMAC operations, we can dispatch these to the RADIOAES instance if there is + * one available. + * + * Function limitations: can only be used with AES-128 or AES-256, and needs to + * have as short as possible execution time to not block other time-sensitive + * operations (such as BLE RPA). Will always output a full CMAC (16 bytes). + * + * \param key Raw key bytes, \p keylen bytes long + * \param keylen Length of \p key in bytes, either 16 (AES-128) or 32 (AES-256) + * \param input Data bytes to calculate the CMAC over, length \p ilen bytes + * \param ilen Length in bytes of \p input + * \param output Output buffer for the calculated CMAC tag (16 bytes) + * + * \return \c 0 on success, MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED on failure + */ +static int sli_short_cmac_operation(const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output) +{ + sl_status_t status = sli_aes_cmac_radio(key, + keylen, + input, + ilen, + output); + if (status == SL_STATUS_OK) { + return 0; + } else { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} +#endif + +int mbedtls_cipher_cmac(const mbedtls_cipher_info_t *cipher_info, + const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output) +{ + if ( cipher_info == NULL || key == NULL || input == NULL || output == NULL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + switch ( cipher_info->MBEDTLS_PRIVATE(type) ) { + case MBEDTLS_CIPHER_AES_128_ECB: + if ( keylen != 128UL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + break; + case MBEDTLS_CIPHER_AES_192_ECB: + #if defined(SLI_DEVICE_HAS_AES_192) + if ( keylen != 192UL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + break; + #else + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + #endif + case MBEDTLS_CIPHER_AES_256_ECB: + if ( keylen != 256UL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + break; + default: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) + /* Use the fast shortcut if available */ + if ( (keylen == 128UL || keylen == 256UL) && (ilen <= 2 * MBEDTLS_AES_BLOCK_SIZE) ) { + return sli_short_cmac_operation(key, keylen, + input, ilen, output); + } +#endif + + size_t olen = 0; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + + switch ( cipher_info->MBEDTLS_PRIVATE(type) ) { + case MBEDTLS_CIPHER_AES_128_ECB: + psa_set_key_bits(&attr, 128); + break; + case MBEDTLS_CIPHER_AES_192_ECB: + psa_set_key_bits(&attr, 192); + break; + case MBEDTLS_CIPHER_AES_256_ECB: + psa_set_key_bits(&attr, 256); + break; + default: + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return psa_status_to_mbedtls( + MAC_ONESHOT_EN_FCT(&attr, + key, keylen / 8U, + PSA_ALG_CMAC, + input, ilen, + output, MBEDTLS_AES_BLOCK_SIZE, &olen) ); +} + +/* + * Implementation of AES-CMAC-PRF-128 defined in RFC 4615 + */ +int mbedtls_aes_cmac_prf_128(const unsigned char *key, size_t key_length, + const unsigned char *input, size_t in_len, + unsigned char output[16]) +{ + int ret; + unsigned char zero_key[MBEDTLS_AES_BLOCK_SIZE]; + unsigned char int_key[MBEDTLS_AES_BLOCK_SIZE]; + + if ( key == NULL || input == NULL || output == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + size_t olen = 0; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attr, 128); + + if ( key_length == MBEDTLS_AES_BLOCK_SIZE ) { + /* Use key as is */ + memcpy(int_key, key, MBEDTLS_AES_BLOCK_SIZE); + } else { + memset(zero_key, 0, MBEDTLS_AES_BLOCK_SIZE); + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) + /* Use the fast shortcut if available */ + if ( key_length <= 2 * MBEDTLS_AES_BLOCK_SIZE ) { + ret = sli_short_cmac_operation(zero_key, MBEDTLS_AES_BLOCK_SIZE * 8, + key, key_length, int_key); + } else +#endif + { + ret = psa_status_to_mbedtls( + MAC_ONESHOT_EN_FCT(&attr, + zero_key, MBEDTLS_AES_BLOCK_SIZE, + PSA_ALG_CMAC, + key, key_length, + int_key, MBEDTLS_AES_BLOCK_SIZE, &olen) ); + } + if ( ret != 0 ) { + goto exit; + } + } + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) + /* Use the fast shortcut if available */ + if ( key_length <= 2 * MBEDTLS_AES_BLOCK_SIZE ) { + ret = sli_short_cmac_operation(int_key, MBEDTLS_AES_BLOCK_SIZE * 8, + input, in_len, (uint8_t*)output); + } else +#endif + { + ret = psa_status_to_mbedtls( + MAC_ONESHOT_EN_FCT(&attr, + int_key, MBEDTLS_AES_BLOCK_SIZE, + PSA_ALG_CMAC, + input, in_len, + (uint8_t*)output, in_len, &olen) ); + } + + exit: + mbedtls_platform_zeroize(int_key, sizeof(int_key) ); + + return(ret); +} + +#endif /* MAC_IMPLEMENTATION_PRESENT */ + +#endif /* MBEDTLS_CMAC_C && MBEDTLS_CMAC_ALT */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c new file mode 100644 index 000000000..54ca61c0a --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c @@ -0,0 +1,391 @@ +/***************************************************************************//** + * @file + * @brief mbed TLS elliptic curve operations accelerated by PSA crypto drivers + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of high-level ECDSA and ECDH + * functions from the mbed TLS API, using the relevant accelerators incorporated + * in devices from Silicon Labs. + * + * For Series-1 devices with a CRYPTO peripheral, see crypto_ecp.c. + * + * This alternative implementation calls the PSA Crypto drivers provided + * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. + */ + +#include + +#if defined(MBEDTLS_ECP_C) + +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + || defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ + || defined(MBEDTLS_ECDSA_GENKEY_ALT) \ + || defined(MBEDTLS_ECDSA_VERIFY_ALT) \ + || defined(MBEDTLS_ECDSA_SIGN_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_functions.h" +#define ECC_IMPLEMENTATION_PRESENT +#define ECC_KEYGEN_FCT sli_se_transparent_generate_key +#define ECC_PUBKEY_FCT sli_se_transparent_export_public_key +#define ECDSA_SIGN_FCT sli_se_transparent_sign_hash +#define ECDSA_VERIFY_FCT sli_se_transparent_verify_hash +#define ECDH_DERIVE_FCT sli_se_transparent_key_agreement +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_functions.h" +#define ECC_IMPLEMENTATION_PRESENT +#define ECC_KEYGEN_FCT sli_cryptoacc_transparent_generate_key +#define ECC_PUBKEY_FCT sli_cryptoacc_transparent_export_public_key +#define ECDSA_SIGN_FCT sli_cryptoacc_transparent_sign_hash +#define ECDSA_VERIFY_FCT sli_cryptoacc_transparent_verify_hash +#define ECDH_DERIVE_FCT sli_cryptoacc_transparent_key_agreement +#endif + +#include "mbedtls/ecdh.h" +#include "mbedtls/ecdsa.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/bignum.h" +#include "mbedtls/error.h" +#include "psa/crypto.h" + +#if defined(ECC_IMPLEMENTATION_PRESENT) +static int psa_status_to_mbedtls(psa_status_t status) +{ + switch ( status ) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_INVALID_SIGNATURE: + return MBEDTLS_ERR_ECP_VERIFY_FAILED; + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + default: + return MBEDTLS_ERR_ERROR_GENERIC_ERROR; + } +} + +static int mbedtls_grp_to_psa_attr(mbedtls_ecp_group_id id, + psa_key_attributes_t *attr) +{ + switch (id) { + case MBEDTLS_ECP_DP_SECP192R1: + attr->MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 192); + break; +#if defined(CRYPTOACC_PRESENT) + case MBEDTLS_ECP_DP_SECP224R1: + attr->MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 224); + break; + case MBEDTLS_ECP_DP_SECP256K1: + attr->MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_K1); + psa_set_key_bits(attr, 256); + break; +#endif + case MBEDTLS_ECP_DP_SECP256R1: + attr->MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 256); + break; + case MBEDTLS_ECP_DP_SECP384R1: + attr->MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 384); + break; + case MBEDTLS_ECP_DP_SECP521R1: + attr->MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 521); + break; + case MBEDTLS_ECP_DP_CURVE25519: + attr->MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_MONTGOMERY); + psa_set_key_bits(attr, 255); + break; + default: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + return PSA_SUCCESS; +} +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + || defined(MBEDTLS_ECDSA_GENKEY_ALT) +static int ecc_keygen(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q) +{ + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + uint8_t keybuf[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1u] = { 0 }; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr) ); + if ( status != PSA_SUCCESS ) { + return status; + } + + size_t keybytes; + status = psa_status_to_mbedtls( + ECC_KEYGEN_FCT(&attr, + keybuf, + sizeof(keybuf), + &keybytes) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + mbedtls_mpi_read_binary_le(d, keybuf, keybytes); + } else { + mbedtls_mpi_read_binary(d, keybuf, keybytes); + } + + status = psa_status_to_mbedtls( + ECC_PUBKEY_FCT(&attr, + keybuf, + keybytes, + keybuf, + sizeof(keybuf), + &keybytes) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + if ( PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY ) { + mbedtls_mpi_read_binary_le(&Q->MBEDTLS_PRIVATE(X), keybuf, keybytes); + } else { + // The first byte is used to store uncompressed representation byte. + mbedtls_mpi_read_binary(&Q->MBEDTLS_PRIVATE(X), keybuf + 1u, keybytes / 2); + mbedtls_mpi_read_binary(&Q->MBEDTLS_PRIVATE(Y), keybuf + keybytes / 2 + 1u, keybytes / 2); + mbedtls_mpi_lset(&Q->MBEDTLS_PRIVATE(Z), 1); + } + + return status; +} +#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) + || defined(MBEDTLS_ECDSA_GENKEY_ALT) */ + +#if defined(MBEDTLS_ECDSA_GENKEY_ALT) +/* + * Generate key pair + */ +int mbedtls_ecdsa_genkey(mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + mbedtls_ecp_group_load(&ctx->MBEDTLS_PRIVATE(grp), gid); + + return ecc_keygen(&ctx->MBEDTLS_PRIVATE(grp), &ctx->MBEDTLS_PRIVATE(d), &ctx->MBEDTLS_PRIVATE(Q)); +} +#endif /* MBEDTLS_ECDSA_GENKEY_ALT */ + +#if defined(MBEDTLS_ECDSA_SIGN_ALT) +int mbedtls_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + uint8_t key_signature_buf[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr)); + if ( status != PSA_SUCCESS ) { + return status; + } + psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_SIGN_HASH); + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + return PSA_ERROR_NOT_SUPPORTED; + } + + size_t keybytes = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); + + // Make sure d is in range 1..n-1 + if ((mbedtls_mpi_cmp_int(d, 1) < 0) || (mbedtls_mpi_cmp_mpi(d, &grp->N) >= 0)) { + return MBEDTLS_ERR_ECP_INVALID_KEY; + } + + mbedtls_mpi_write_binary(d, key_signature_buf, keybytes); + + status = psa_status_to_mbedtls( + ECDSA_SIGN_FCT(&attr, + key_signature_buf, + keybytes, + PSA_ALG_ECDSA_ANY, + buf, + blen, + key_signature_buf, + sizeof(key_signature_buf), + &keybytes) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + mbedtls_mpi_read_binary(r, key_signature_buf, keybytes / 2); + mbedtls_mpi_read_binary(s, key_signature_buf + (keybytes / 2), keybytes / 2); + + return status; +} +#endif /* MBEDTLS_ECDSA_SIGN_ALT */ + +#if defined(MBEDTLS_ECDSA_VERIFY_ALT) +int mbedtls_ecdsa_verify(mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, const mbedtls_mpi *r, const mbedtls_mpi *s) +{ + uint8_t pub[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1] = { 0 }; + uint8_t signature[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr) ); + if ( status != PSA_SUCCESS ) { + return status; + } + + /* Check signature components r, s or both are not negative. */ + if ( (r->MBEDTLS_PRIVATE(s) < 0) || (s->MBEDTLS_PRIVATE(s) < 0) ) { + return MBEDTLS_ERR_ECP_VERIFY_FAILED; + } + + psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_VERIFY_HASH); + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + return PSA_ERROR_NOT_SUPPORTED; + } + + attr.MBEDTLS_PRIVATE(type) = + PSA_KEY_TYPE_ECC_PUBLIC_KEY(PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr))); + + size_t keybytes = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); + + /* pull out signature info from mbedtls structures */ + mbedtls_mpi_write_binary(r, signature, keybytes); + mbedtls_mpi_write_binary(s, &signature[keybytes], keybytes); + + pub[0] = 0x04; // Uncompressed public key + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(X), &pub[1u], keybytes); + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(Y), &pub[keybytes + 1u], keybytes); + + return psa_status_to_mbedtls( + ECDSA_VERIFY_FCT(&attr, + pub, + keybytes * 2 + 1u, + PSA_ALG_ECDSA_ANY, + buf, + blen, + signature, + keybytes * 2) ); +} +#endif /* MBEDTLS_ECDSA_VERIFY_ALT */ + +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) +int mbedtls_ecdh_gen_public(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + return ecc_keygen(grp, d, Q); +} +#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) */ + +#if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) +int mbedtls_ecdh_compute_shared(mbedtls_ecp_group *grp, mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + uint8_t pub[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1u] = { 0 }; + uint8_t priv[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr) ); + if ( status != PSA_SUCCESS ) { + return status; + } + psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_DERIVE); + + size_t keylen = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); + size_t publen; + + /* pull out key info from mbedtls structures */ + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + publen = keylen; + mbedtls_mpi_write_binary_le(d, priv, keylen); + mbedtls_mpi_write_binary_le(&Q->MBEDTLS_PRIVATE(X), pub, keylen); + } else { + publen = 2 * keylen + 1u; + mbedtls_mpi_write_binary(d, priv, keylen); + pub[0] = 0x04; // uncompressed public key + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(X), pub + 1u, keylen); + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(Y), pub + keylen + 1u, keylen); + } + + status = psa_status_to_mbedtls( + ECDH_DERIVE_FCT(PSA_ALG_ECDH, + &attr, + priv, + keylen, + pub, + publen, + pub, + sizeof(pub), + &publen) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + mbedtls_mpi_read_binary_le(z, pub, publen); + } else { + mbedtls_mpi_read_binary(z, pub, publen); + } + return status; +} +#endif /* #if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) */ + +#endif /* ECC_IMPLEMENTATION_PRESENT */ + +#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) || defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) */ + +#endif /* #if defined(MBEDTLS_ECP_C) */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_sha.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_sha.c new file mode 100644 index 000000000..2fd1743a5 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_sha.c @@ -0,0 +1,242 @@ +/***************************************************************************//** + * @file + * @brief SHA-1, SHA-256 and SHA-512 mbedTLS plugin on top of PSA accelerators. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of the SHA functionality in + * mbed TLS' APIs, using the accelerators incorporated in devices from Silicon Labs. + * + * This alternative implementation calls the PSA Crypto drivers provided + * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. + */ + +#include + +#if (defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C)) \ + || (defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C)) \ + || (defined(MBEDTLS_SHA512_ALT) && defined(MBEDTLS_SHA512_C)) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_functions.h" +#define HASH_IMPLEMENTATION_PRESENT +#define HASH_SETUP_FCT sli_se_transparent_hash_setup +#define HASH_UPDATE_FCT sli_se_transparent_hash_update +#define HASH_FINISH_FCT sli_se_transparent_hash_finish +#define HASH_ABORT_FCT sli_se_transparent_hash_abort +#define HASH_ONESHOT_FCT sli_se_transparent_hash_compute +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_functions.h" +#define HASH_IMPLEMENTATION_PRESENT +#define HASH_SETUP_FCT sli_cryptoacc_transparent_hash_setup +#define HASH_UPDATE_FCT sli_cryptoacc_transparent_hash_update +#define HASH_FINISH_FCT sli_cryptoacc_transparent_hash_finish +#define HASH_ABORT_FCT sli_cryptoacc_transparent_hash_abort +#define HASH_ONESHOT_FCT sli_cryptoacc_transparent_hash_compute +#endif + +#include "mbedtls/error.h" +#include "mbedtls/platform.h" + +#if defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C) +#include "mbedtls/sha1.h" +#endif /* SHA1 acceleration active */ + +#if defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) +#include "mbedtls/sha256.h" +#endif /* SHA256 acceleration active */ + +#if defined(MBEDTLS_SHA512_ALT) && defined(MBEDTLS_SHA512_C) +#include "mbedtls/sha512.h" +#endif /* SHA512 acceleration active */ + +#if defined(HASH_IMPLEMENTATION_PRESENT) +static int psa_status_to_mbedtls(psa_status_t status, psa_algorithm_t alg) +{ + switch ( status ) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + case PSA_ERROR_INVALID_ARGUMENT: + switch ( alg ) { +#if defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C) + case PSA_ALG_SHA_1: + return MBEDTLS_ERR_SHA1_BAD_INPUT_DATA; +#endif +#if defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) + case PSA_ALG_SHA_256: + return MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; +#endif +#if defined(MBEDTLS_SHA512_ALT) && defined(MBEDTLS_SHA512_C) + case PSA_ALG_SHA_512: + return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; +#endif + default: + return MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + } + default: + return MBEDTLS_ERR_ERROR_GENERIC_ERROR; + } +} + +#if defined(MBEDTLS_SHA512_ALT) && (defined(MBEDTLS_SHA384_C) || defined(MBEDTLS_SHA512_C)) + +void mbedtls_sha512_init(mbedtls_sha512_context *ctx) +{ + HASH_ABORT_FCT(ctx); +} + +void mbedtls_sha512_free(mbedtls_sha512_context *ctx) +{ + HASH_ABORT_FCT(ctx); +} + +void mbedtls_sha512_clone(mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src) +{ + *dst = *src; +} + +int mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384) +{ + if (is384 > 1) { + return MBEDTLS_ERR_SHA512_BAD_INPUT_DATA; + } + + return psa_status_to_mbedtls(HASH_SETUP_FCT(ctx, is384 ? PSA_ALG_SHA_384 : PSA_ALG_SHA_512), PSA_ALG_SHA_512); +} + +int mbedtls_sha512_update(mbedtls_sha512_context *ctx, const unsigned char *input, + size_t ilen) +{ + return psa_status_to_mbedtls(HASH_UPDATE_FCT(ctx, input, ilen), PSA_ALG_SHA_512); +} + +int mbedtls_internal_sha512_process(mbedtls_sha512_context *ctx, const unsigned char data[128]) +{ + return psa_status_to_mbedtls(HASH_UPDATE_FCT(ctx, data, 128), PSA_ALG_SHA_512); +} + +int mbedtls_sha512_finish(mbedtls_sha512_context *ctx, unsigned char *output) +{ + size_t out_length = 0; + return psa_status_to_mbedtls(HASH_FINISH_FCT(ctx, output, 64, &out_length), PSA_ALG_SHA_512); +} +#endif /* SHA512 acceleration active */ + +#if defined(MBEDTLS_SHA256_ALT) && (defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA224_C)) +void mbedtls_sha256_init(mbedtls_sha256_context *ctx) +{ + HASH_ABORT_FCT((void *)ctx); +} + +void mbedtls_sha256_free(mbedtls_sha256_context *ctx) +{ + HASH_ABORT_FCT((void *)ctx); +} + +void mbedtls_sha256_clone(mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src) +{ + *dst = *src; +} + +int mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224) +{ + if (is224 > 1) { + return MBEDTLS_ERR_SHA256_BAD_INPUT_DATA; + } + + return psa_status_to_mbedtls(HASH_SETUP_FCT((void *)ctx, is224 ? PSA_ALG_SHA_224 : PSA_ALG_SHA_256), PSA_ALG_SHA_256); +} + +int mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, + size_t ilen) +{ + return psa_status_to_mbedtls(HASH_UPDATE_FCT((void *)ctx, input, ilen), PSA_ALG_SHA_256); +} + +int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64]) +{ + return psa_status_to_mbedtls(HASH_UPDATE_FCT((void *)ctx, data, 64), PSA_ALG_SHA_256); +} + +int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char *output) +{ + size_t out_length = 0; + return psa_status_to_mbedtls(HASH_FINISH_FCT((void *)ctx, output, 32, &out_length), PSA_ALG_SHA_256); +} +#endif /* SHA256 acceleration active */ + +#if defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C) + +void mbedtls_sha1_init(mbedtls_sha1_context *ctx) +{ + HASH_ABORT_FCT((void *)ctx); +} + +void mbedtls_sha1_free(mbedtls_sha1_context *ctx) +{ + HASH_ABORT_FCT((void *)ctx); +} + +void mbedtls_sha1_clone(mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src) +{ + *dst = *src; +} + +int mbedtls_sha1_starts(mbedtls_sha1_context *ctx) +{ + return psa_status_to_mbedtls(HASH_SETUP_FCT((void *)ctx, PSA_ALG_SHA_1), PSA_ALG_SHA_1); +} + +int mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen) +{ + return psa_status_to_mbedtls(HASH_UPDATE_FCT((void *)ctx, input, ilen), PSA_ALG_SHA_1); +} + +int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64]) +{ + return psa_status_to_mbedtls(HASH_UPDATE_FCT((void *)ctx, data, 64), PSA_ALG_SHA_1); +} + +int mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20]) +{ + size_t out_length = 0; + return psa_status_to_mbedtls(HASH_FINISH_FCT((void *)ctx, output, 20, &out_length), PSA_ALG_SHA_1); +} +#endif /* SHA1 acceleration active */ + +#endif /* HASH_IMPLEMENTATION_PRESENT */ +#endif /* (SHA1 or SHA256 or SHA512) acceleration active */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_aes.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_aes.c new file mode 100644 index 000000000..4614184a3 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_aes.c @@ -0,0 +1,780 @@ +/***************************************************************************//** + * @file + * @brief AES abstraction based on Secure Engine + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* + * This file includes alternative plugin implementations of various + * functions in aes.c using the Secure Engine accelerator incorporated + * in Series-2 devices with Secure Engine from Silicon Laboratories. + */ + +/** + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#include + +#if defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_AES_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) + +#include "sli_se_manager_mailbox.h" +#include "sli_se_manager_internal.h" +#include "se_management.h" +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include + +/* + * Initialize AES context + */ +void mbedtls_aes_init(mbedtls_aes_context *ctx) +{ + memset(ctx, 0, sizeof(mbedtls_aes_context) ); +} + +/* + * Clear AES context + */ +void mbedtls_aes_free(mbedtls_aes_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_aes_context) ); +} + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx) +{ + mbedtls_aes_init(&ctx->crypt); + mbedtls_aes_init(&ctx->tweak); +} + +void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + mbedtls_aes_free(&ctx->crypt); + mbedtls_aes_free(&ctx->tweak); +} + +static int mbedtls_aes_xts_decode_keys(const unsigned char *key, + unsigned int keybits, + const unsigned char **key1, + unsigned int *key1bits, + const unsigned char **key2, + unsigned int *key2bits) +{ + const unsigned int half_keybits = keybits / 2; + const unsigned int half_keybytes = half_keybits / 8; + + switch ( keybits ) { + case 256: break; + case 512: break; + default: return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); + } + + *key1bits = half_keybits; + *key2bits = half_keybits; + *key1 = &key[0]; + *key2 = &key[half_keybytes]; + + return 0; +} + +int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1 = NULL; + const unsigned char *key2 = NULL; + unsigned int key1bits = 0; + unsigned int key2bits = 0; + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, + &key2, &key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set the tweak key. Always set tweak key for the encryption mode. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set crypt key for encryption. */ + return mbedtls_aes_setkey_enc(&ctx->crypt, key1, key1bits); +} + +int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1 = NULL; + const unsigned char *key2 = NULL; + unsigned int key1bits = 0; + unsigned int key2bits = 0; + + if (ctx == NULL || key == NULL) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, + &key2, &key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set the tweak key. Always set tweak key for encryption. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set crypt key for decryption. */ + return mbedtls_aes_setkey_dec(&ctx->crypt, key1, key1bits); +} + +/* Endianess with 64 bits values */ +#ifndef GET_UINT64_LE +#define GET_UINT64_LE(n, b, i) \ + { \ + (n) = ( (uint64_t) (b)[(i) + 7] << 56) \ + | ( (uint64_t) (b)[(i) + 6] << 48) \ + | ( (uint64_t) (b)[(i) + 5] << 40) \ + | ( (uint64_t) (b)[(i) + 4] << 32) \ + | ( (uint64_t) (b)[(i) + 3] << 24) \ + | ( (uint64_t) (b)[(i) + 2] << 16) \ + | ( (uint64_t) (b)[(i) + 1] << 8) \ + | ( (uint64_t) (b)[(i)]); \ + } +#endif + +#ifndef PUT_UINT64_LE +#define PUT_UINT64_LE(n, b, i) \ + { \ + (b)[(i) + 7] = (unsigned char) ( (n) >> 56); \ + (b)[(i) + 6] = (unsigned char) ( (n) >> 48); \ + (b)[(i) + 5] = (unsigned char) ( (n) >> 40); \ + (b)[(i) + 4] = (unsigned char) ( (n) >> 32); \ + (b)[(i) + 3] = (unsigned char) ( (n) >> 24); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 16); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 8); \ + (b)[(i)] = (unsigned char) ( (n) ); \ + } +#endif + +/* + * GF(2^128) multiplication function + * + * This function multiplies a field element by x in the polynomial field + * representation. It uses 64-bit word operations to gain speed but compensates + * for machine endianess and hence works correctly on both big and little + * endian machines. + */ +static void mbedtls_gf128mul_x_ble(unsigned char r[16], + const unsigned char x[16]) +{ + uint64_t a, b, ra, rb; + + GET_UINT64_LE(a, x, 0); + GET_UINT64_LE(b, x, 8); + + ra = (a << 1) ^ 0x0087 >> (8 - ( (b >> 63) << 3) ); + rb = (a >> 63) | (b << 1); + + PUT_UINT64_LE(ra, r, 0); + PUT_UINT64_LE(rb, r, 8); +} + +/* + * AES-XTS buffer encryption/decryption + */ +int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, + int mode, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output) +{ + int ret; + size_t blocks = length / 16; + size_t leftover = length % 16; + unsigned char tweak[16]; + unsigned char prev_tweak[16]; + unsigned char tmp[16]; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + /* Data units must be at least 16 bytes long. */ + if ( length < 16 ) { + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + /* NIST SP 800-38E disallows data units larger than 2**20 blocks. */ + if ( length > (1 << 20) * 16 ) { + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + /* Compute the tweak. */ + ret = mbedtls_aes_crypt_ecb(&ctx->tweak, MBEDTLS_AES_ENCRYPT, + data_unit, tweak); + if ( ret != 0 ) { + return(ret); + } + + while ( blocks-- ) { + size_t i; + + if ( leftover && (mode == MBEDTLS_AES_DECRYPT) && blocks == 0 ) { + /* We are on the last block in a decrypt operation that has + * leftover bytes, so we need to use the next tweak for this block, + * and this tweak for the lefover bytes. Save the current tweak for + * the leftovers and then update the current tweak for use on this, + * the last full block. */ + memcpy(prev_tweak, tweak, sizeof(tweak) ); + mbedtls_gf128mul_x_ble(tweak, tweak); + } + + for ( i = 0; i < 16; i++ ) { + tmp[i] = input[i] ^ tweak[i]; + } + + ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); + if ( ret != 0 ) { + return(ret); + } + + for ( i = 0; i < 16; i++ ) { + output[i] = tmp[i] ^ tweak[i]; + } + + /* Update the tweak for the next block. */ + mbedtls_gf128mul_x_ble(tweak, tweak); + + output += 16; + input += 16; + } + + if ( leftover ) { + /* If we are on the leftover bytes in a decrypt operation, we need to + * use the previous tweak for these bytes (as saved in prev_tweak). */ + unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak; + + /* We are now on the final part of the data unit, which doesn't divide + * evenly by 16. It's time for ciphertext stealing. */ + size_t i; + unsigned char *prev_output = output - 16; + + /* Copy ciphertext bytes from the previous block to our output for each + * byte of cyphertext we won't steal. At the same time, copy the + * remainder of the input for this final round (since the loop bounds + * are the same). */ + for ( i = 0; i < leftover; i++ ) { + output[i] = prev_output[i]; + tmp[i] = input[i] ^ t[i]; + } + + /* Copy ciphertext bytes from the previous block for input in this + * round. */ + for (; i < 16; i++ ) { + tmp[i] = prev_output[i] ^ t[i]; + } + + ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); + if ( ret != 0 ) { + return ret; + } + + /* Write the result back to the previous block, overriding the previous + * output we copied. */ + for ( i = 0; i < 16; i++ ) { + prev_output[i] = tmp[i] ^ t[i]; + } + } + + return(0); +} + +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/* + * AES key schedule (encryption) + */ +int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + memset(ctx, 0, sizeof(mbedtls_aes_context) ); + + if ( (128UL != keybits) && (192UL != keybits) && (256UL != keybits) ) { + // Unsupported key size + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +/* + * AES key schedule (decryption) + */ +int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + return mbedtls_aes_setkey_enc(ctx, key, keybits); +} + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]) +{ + sli_se_mailbox_response_t command_status; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL && ctx->keybits != 192UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT((mode == MBEDTLS_AES_ENCRYPT ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) | SLI_SE_COMMAND_OPTION_MODE_ECB | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); + sli_se_datatransfer_t key = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, (ctx->keybits / 8)); + sli_se_datatransfer_t in = SLI_SE_DATATRANSFER_DEFAULT((void*)input, 16); + sli_se_datatransfer_t out = SLI_SE_DATATRANSFER_DEFAULT(output, 16); + + sli_se_mailbox_command_add_input(&command, &key); + sli_se_mailbox_command_add_input(&command, &in); + sli_se_mailbox_command_add_output(&command, &out); + sli_se_mailbox_command_add_parameter(&command, (ctx->keybits / 8)); + sli_se_mailbox_command_add_parameter(&command, 16); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + command_status = sli_se_handle_mailbox_response(); + + se_management_release(); + + if ( command_status == SLI_SE_RESPONSE_OK ) { + return 0; + } else { + return (int)command_status; + } +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + sli_se_mailbox_response_t command_status; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + // Input length must be a multiple of 16 bytes which is the AES block + // length. + if ( length & 0xf ) { + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + if ( ctx->keybits != 128UL && ctx->keybits != 192UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT((mode == MBEDTLS_AES_ENCRYPT ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) | SLI_SE_COMMAND_OPTION_MODE_CBC | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + sli_se_datatransfer_t key = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, (ctx->keybits / 8)); + sli_se_datatransfer_t iv_in = SLI_SE_DATATRANSFER_DEFAULT(iv, 16); + sli_se_datatransfer_t iv_out = SLI_SE_DATATRANSFER_DEFAULT(iv, 16); + sli_se_datatransfer_t in = SLI_SE_DATATRANSFER_DEFAULT((void*)input, length); + sli_se_datatransfer_t out = SLI_SE_DATATRANSFER_DEFAULT(output, length); + + sli_se_mailbox_command_add_input(&command, &key); + sli_se_mailbox_command_add_input(&command, &iv_in); + sli_se_mailbox_command_add_input(&command, &in); + sli_se_mailbox_command_add_output(&command, &out); + sli_se_mailbox_command_add_output(&command, &iv_out); + sli_se_mailbox_command_add_parameter(&command, (ctx->keybits / 8)); + sli_se_mailbox_command_add_parameter(&command, length); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + command_status = sli_se_handle_mailbox_response(); + + se_management_release(); + + if ( command_status == SLI_SE_RESPONSE_OK ) { + return 0; + } else { + return (int)command_status; + } +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + size_t n = iv_off ? *iv_off : 0; + size_t processed = 0; + sli_se_mailbox_response_t command_status = SLI_SE_RESPONSE_OK; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( n > 15 ) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL && ctx->keybits != 192UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + if ( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + } else { + /* process one ore more blocks of data */ + size_t iterations = (length - processed) / 16; + + if ( iterations > 0 ) { + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT((mode == MBEDTLS_AES_ENCRYPT ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) | SLI_SE_COMMAND_OPTION_MODE_CFB | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + sli_se_datatransfer_t key = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, (ctx->keybits / 8)); + sli_se_datatransfer_t iv_in = SLI_SE_DATATRANSFER_DEFAULT(iv, 16); + sli_se_datatransfer_t iv_out = SLI_SE_DATATRANSFER_DEFAULT(iv, 16); + sli_se_datatransfer_t in = SLI_SE_DATATRANSFER_DEFAULT((void*)&input[processed], iterations * 16); + sli_se_datatransfer_t out = SLI_SE_DATATRANSFER_DEFAULT(&output[processed], iterations * 16); + + sli_se_mailbox_command_add_input(&command, &key); + sli_se_mailbox_command_add_input(&command, &iv_in); + sli_se_mailbox_command_add_input(&command, &in); + sli_se_mailbox_command_add_output(&command, &out); + sli_se_mailbox_command_add_output(&command, &iv_out); + sli_se_mailbox_command_add_parameter(&command, (ctx->keybits / 8)); + sli_se_mailbox_command_add_parameter(&command, iterations * 16); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + command_status = sli_se_handle_mailbox_response(); + + se_management_release(); + processed += iterations * 16; + } + + if ( command_status != SLI_SE_RESPONSE_OK ) { + goto exit; + } + + while ( length - processed > 0 ) { + if ( n == 0 ) { + // Need to update the IV but don't have a full block of input to pass to the SE + int status = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); + if (status != 0) { + return status; + } + } + /* Save remainder to iv */ + if ( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + } + } + } + + if ( iv_off ) { + *iv_off = n; + } + + exit: + if ( command_status == SLI_SE_RESPONSE_OK ) { + return 0; + } else { + return (int)command_status; + } +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + unsigned char c; + unsigned char ov[17]; + int ret = 0; + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL && ctx->keybits != 192UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + while ( length-- ) { + memcpy(ov, iv, 16); + if ( (ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv) ) != 0 ) { + return ret; + } + + if ( mode == MBEDTLS_AES_DECRYPT ) { + ov[16] = *input; + } + + c = *output++ = (unsigned char)(iv[0] ^ *input++); + + if ( mode == MBEDTLS_AES_ENCRYPT ) { + ov[16] = c; + } + + memcpy(iv, ov + 1, 16); + } + + return ret; +} +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output) +{ + size_t n = nc_off ? *nc_off : 0; + size_t processed = 0; + sli_se_mailbox_response_t command_status = SLI_SE_RESPONSE_OK; + + if ( ctx->keybits != 128UL && ctx->keybits != 192UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & 0x0F; + processed++; + } else { + /* process one or more blocks of data */ + size_t iterations = (length - processed) / 16; + + if ( iterations > 0 ) { + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_ENCRYPT | SLI_SE_COMMAND_OPTION_MODE_CTR | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + sli_se_datatransfer_t key = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, (ctx->keybits / 8)); + sli_se_datatransfer_t iv_in = SLI_SE_DATATRANSFER_DEFAULT(nonce_counter, 16); + sli_se_datatransfer_t iv_out = SLI_SE_DATATRANSFER_DEFAULT(nonce_counter, 16); + sli_se_datatransfer_t in = SLI_SE_DATATRANSFER_DEFAULT((void*)&input[processed], iterations * 16); + sli_se_datatransfer_t out = SLI_SE_DATATRANSFER_DEFAULT(&output[processed], iterations * 16); + + sli_se_mailbox_command_add_input(&command, &key); + sli_se_mailbox_command_add_input(&command, &iv_in); + sli_se_mailbox_command_add_input(&command, &in); + sli_se_mailbox_command_add_output(&command, &out); + sli_se_mailbox_command_add_output(&command, &iv_out); + sli_se_mailbox_command_add_parameter(&command, (ctx->keybits / 8)); + sli_se_mailbox_command_add_parameter(&command, iterations * 16); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + command_status = sli_se_handle_mailbox_response(); + + se_management_release(); + processed += iterations * 16; + } + + if ( command_status != SLI_SE_RESPONSE_OK ) { + goto exit; + } + + while ( length - processed > 0 ) { + if ( n == 0 ) { + // Get a new stream block + int status = mbedtls_aes_crypt_ecb(ctx, + MBEDTLS_AES_ENCRYPT, + nonce_counter, + stream_block); + if (status != 0) { + return status; + } + // increment nonce counter... + for (size_t i = 0; i < 16; i++) { + nonce_counter[15 - i] = nonce_counter[15 - i] + 1; + if ( nonce_counter[15 - i] != 0 ) { + break; + } + } + } + /* Save remainder to iv */ + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & 0x0F; + processed++; + } + } + } + + if ( nc_off ) { + *nc_off = n; + } + + exit: + if ( command_status == SLI_SE_RESPONSE_OK ) { + return 0; + } else { + return (int)command_status; + } +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/* + * AES-OFB (Output Feedback Mode) buffer encryption/decryption + */ +int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + int ret = 0; + size_t n; + + n = *iv_off; + + if ( n > 15 ) { + return(MBEDTLS_ERR_AES_BAD_INPUT_DATA); + } + + while ( length-- ) { + if ( n == 0 ) { + ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); + if ( ret != 0 ) { + goto exit; + } + } + *output++ = *input++ ^ iv[n]; + + n = (n + 1) & 0x0F; + } + + *iv_off = n; + + exit: + return(ret); +} +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#endif /* SEMAILBOX_PRESENT */ + +#endif /* MBEDTLS_AES_ALT */ + +#endif /* MBEDTLS_AES_C */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_gcm.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_gcm.c new file mode 100644 index 000000000..462ec432c --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_gcm.c @@ -0,0 +1,724 @@ +/***************************************************************************//** + * @file + * @brief AES-GCM abstraction via Silicon Labs SE + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes alternative plugin implementations of various + * functions in gcm.c using the SE accelerator incorporated + * in Series-2 devices with Secure Engine from Silicon Laboratories. + */ + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_manager_mailbox.h" +#include "mbedtls/build_info.h" + +#if defined(MBEDTLS_GCM_ALT) && defined(MBEDTLS_GCM_C) +#include "mbedtls/gcm.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include "se_management.h" +#include + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize(void *v, size_t n) +{ + if (n == 0) { + return; + } + volatile unsigned char *p = v; + while ( n-- ) *p++ = 0; +} + +static void sx_math_u64_to_u8array(uint64_t in, uint8_t *out) +{ + uint32_t i = 0; + for (i = 0; i < 8; i++) { + out[7 - i] = (in >> 8 * i) & 0xFF; + } +} + +static int sli_validate_gcm_params(size_t tag_len, + size_t iv_len, + size_t add_len) +{ + // NOTE: tag lengths != 16 byte are only supported as of SE FW v1.2.0. + // Earlier firmware versions will return an error trying to verify non-16-byte + // tags using this function. + if ( tag_len < 4 || tag_len > 16 || iv_len == 0 ) { + return (MBEDTLS_ERR_GCM_BAD_INPUT); + } + + /* AD are limited to 2^64 bits, so 2^61 bytes. Since the length of AAD is + * limited by the mbedtls API to a size_t, length checking only needs to be + * done on 64-bit platforms. */ +#if SIZE_MAX > 0xFFFFFFFFUL + if (add_len >> 61 != 0) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } +#else + (void) add_len; +#endif /* 64-bit size_t */ + + /* Library does not support non-12-byte IVs */ + if (iv_len != 12) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + return 0; +} + +/* + * Initialize a context + */ +void mbedtls_gcm_init(mbedtls_gcm_context *ctx) +{ + if (ctx == NULL) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_gcm_context) ); +} + +// Set key +int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits) +{ + if (ctx == NULL + || key == NULL + || cipher != MBEDTLS_CIPHER_ID_AES + || (keybits != 128 && keybits != 192 && keybits != 256)) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + /* Store key in gcm context */ + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len) +{ + int status; + + /* Check input parameters. */ + if (ctx == NULL + || iv == NULL ) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + status = sli_validate_gcm_params(16, iv_len, 0); + if (status) { + return status; + } + + /* Store input in context data structure. */ + ctx->mode = mode; + ctx->len = 0; + ctx->add_len = 0; + ctx->last_op = false; + ctx->iv_len = iv_len; + memcpy(ctx->se_ctx_dec, iv, iv_len); + memcpy(ctx->se_ctx_enc, iv, iv_len); + + return 0; +} + +int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, + const unsigned char *add, + size_t add_len) +{ + int status; + sli_se_mailbox_response_t se_response; + + if (add_len > 0 && add == NULL) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + if (add_len == 0) { + return 0; + } + + // This implementation only supports adding the full AD in one shot + if ( ctx->add_len > 0 ) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + status = sli_validate_gcm_params(16, 12, add_len); + if (status) { + return status; + } + + // Start with encryption + // Need to do encryption twice: once to create the context, the other to pre-compute the tag in case there's no more data coming + // (SE doesn't support a type of 'finalize' command. All operations with 'END' set need to contain some data.) + sli_se_mailbox_command_t gcm_cmd_enc = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_ENCRYPT | SLI_SE_COMMAND_OPTION_CONTEXT_START); + sli_se_mailbox_command_t gcm_cmd_enc_full = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_ENCRYPT | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); + + sli_se_datatransfer_t key_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_dec, ctx->iv_len); + sli_se_datatransfer_t aad_in = SLI_SE_DATATRANSFER_DEFAULT((void*)add, add_len); + + sli_se_datatransfer_t key_in_full = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_in_full = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_dec, ctx->iv_len); + sli_se_datatransfer_t aad_in_full = SLI_SE_DATATRANSFER_DEFAULT((void*)add, add_len); + + sli_se_datatransfer_t ctx_out = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_enc, sizeof(ctx->se_ctx_enc)); + sli_se_datatransfer_t tag_out = SLI_SE_DATATRANSFER_DEFAULT(ctx->tagbuf, sizeof(ctx->tagbuf)); + + sli_se_mailbox_command_add_input(&gcm_cmd_enc, &key_in); + sli_se_mailbox_command_add_input(&gcm_cmd_enc, &iv_in); + sli_se_mailbox_command_add_input(&gcm_cmd_enc, &aad_in); + + sli_se_mailbox_command_add_input(&gcm_cmd_enc_full, &key_in_full); + sli_se_mailbox_command_add_input(&gcm_cmd_enc_full, &iv_in_full); + sli_se_mailbox_command_add_input(&gcm_cmd_enc_full, &aad_in_full); + + sli_se_mailbox_command_add_output(&gcm_cmd_enc, &ctx_out); + sli_se_mailbox_command_add_output(&gcm_cmd_enc_full, &tag_out); + + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc, add_len); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc, 0); + + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc_full, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc_full, add_len); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc_full, 0); + + status = se_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + sli_se_mailbox_execute_command(&gcm_cmd_enc_full); + se_response = sli_se_handle_mailbox_response(); + sli_se_mailbox_execute_command(&gcm_cmd_enc); + se_response |= sli_se_handle_mailbox_response(); + + se_management_release(); + + // Continue with decryption if needed + if (ctx->mode == MBEDTLS_GCM_DECRYPT) { + sli_se_mailbox_command_t gcm_cmd_dec = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_DECRYPT | SLI_SE_COMMAND_OPTION_CONTEXT_START); + + sli_se_datatransfer_t key_in_dec = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_in_dec = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_dec, ctx->iv_len); + sli_se_datatransfer_t aad_in_dec = SLI_SE_DATATRANSFER_DEFAULT((void*)add, add_len); + + sli_se_datatransfer_t ctx_out_dec = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_dec, sizeof(ctx->se_ctx_dec)); + + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &key_in_dec); + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &iv_in_dec); + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &aad_in_dec); + + sli_se_mailbox_command_add_output(&gcm_cmd_dec, &ctx_out_dec); + + sli_se_mailbox_command_add_parameter(&gcm_cmd_dec, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd_dec, add_len); + sli_se_mailbox_command_add_parameter(&gcm_cmd_dec, 0); + + status = se_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + sli_se_mailbox_execute_command(&gcm_cmd_dec); + se_response = sli_se_handle_mailbox_response(); + se_management_release(); + } + + if (se_response == SLI_SE_RESPONSE_OK) { + ctx->add_len = add_len; + return 0; + } else { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} + +int mbedtls_gcm_update(mbedtls_gcm_context *ctx, + const unsigned char *input, size_t input_length, + unsigned char *output, size_t output_size, + size_t *output_length) +{ + int status; + sli_se_mailbox_response_t se_response; + uint8_t lena_lenc[16]; + *output_length = 0; + + if (ctx == NULL + || (input_length > 0 && input == NULL) + || (input_length > 0 && output == NULL)) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + if (input_length > output_size) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + if (input_length == 0) { + return 0; + } + + /* Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes + * Also check for possible overflow */ + if ( ctx->len + input_length < ctx->len + || (uint64_t) ctx->len + input_length > 0xFFFFFFFE0ull ) { + return(MBEDTLS_ERR_GCM_BAD_INPUT); + } + + if ( ctx->last_op == true ) { + // We've already closed the input stream, no way back. + return (MBEDTLS_ERR_GCM_BAD_INPUT); + } + + // Approach: + // * Encryption: encrypt regularly with context store. If input length is not a block multiple, close the operation and store the resulting tag in a tag buffer. + // * Decryption: decrypt regularly with context store. For each decryption, re-encrypt the decrypted data with context store. If input length is not a block multiple, close both operations and store the tag from the re-encrypt in a tag buffer. + // * In both cases, the (re-)encryption is done twice: once assuming there is more data to follow, and once assuming this is the final block. + // Explanation: SE doesn't support a type of 'finalize' command. All operations with 'END' set need to contain some data. + + // Figure out whether we'll be closing out + bool first_op = (ctx->add_len == 0 && ctx->len == 0) ? true : false; + + if ( input_length % 16 != 0) { + // Indicate that this is our last op + ctx->last_op = true; + } + + if (first_op && ctx->last_op) { + // Need to store length in context for later. + ctx->len = input_length; + // optimisation: delegate to all-in-one handler + status = mbedtls_gcm_crypt_and_tag(ctx, ctx->mode, input_length, + ctx->se_ctx_dec, ctx->iv_len, + NULL, 0, + input, output, + // Compute max tag size (16 bytes) + 16, ctx->tagbuf); + if (status == 0) { + *output_length = input_length; + } + return status; + } + + sx_math_u64_to_u8array(ctx->add_len << 3, &lena_lenc[0]); + sx_math_u64_to_u8array((ctx->len + input_length) << 3, &lena_lenc[8]); + + // Need to be sure we can get the SE before starting to change any context variables + status = se_management_acquire(); + if (status != 0) { + return status; + } + + ctx->len += input_length; + + if (ctx->mode == MBEDTLS_GCM_DECRYPT) { + // Run decryption first + sli_se_mailbox_command_t gcm_cmd_dec = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_DECRYPT | (first_op ? SLI_SE_COMMAND_OPTION_CONTEXT_START : (ctx->last_op ? SLI_SE_COMMAND_OPTION_CONTEXT_END : SLI_SE_COMMAND_OPTION_CONTEXT_ADD))); + + sli_se_datatransfer_t key_in_dec = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_ctx_in_dec = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_dec, (first_op ? ctx->iv_len : sizeof(ctx->se_ctx_dec))); + sli_se_datatransfer_t data_in_dec = SLI_SE_DATATRANSFER_DEFAULT((void*)input, input_length); + sli_se_datatransfer_t lenalenc_in_dec = SLI_SE_DATATRANSFER_DEFAULT(lena_lenc, sizeof(lena_lenc)); + sli_se_datatransfer_t data_out_dec = SLI_SE_DATATRANSFER_DEFAULT(output, input_length); + sli_se_datatransfer_t ctx_out_dec = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_dec, sizeof(ctx->se_ctx_dec)); + sli_se_datatransfer_t mac_in_dec = SLI_SE_DATATRANSFER_DEFAULT(ctx->tagbuf, sizeof(ctx->tagbuf)); + + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &key_in_dec); + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &iv_ctx_in_dec); + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &data_in_dec); + + sli_se_mailbox_command_add_output(&gcm_cmd_dec, &data_out_dec); + if (!ctx->last_op) { + sli_se_mailbox_command_add_output(&gcm_cmd_dec, &ctx_out_dec); + } else { + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &lenalenc_in_dec); + sli_se_mailbox_command_add_input(&gcm_cmd_dec, &mac_in_dec); + } + + sli_se_mailbox_command_add_parameter(&gcm_cmd_dec, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd_dec, 0); + sli_se_mailbox_command_add_parameter(&gcm_cmd_dec, input_length); + + sli_se_mailbox_execute_command(&gcm_cmd_dec); + se_response = sli_se_handle_mailbox_response(); + // Getting an 'invalid signature' error here is acceptable, since we're not trying to verify the tag + if (se_response == SLI_SE_RESPONSE_INVALID_SIGNATURE) { + se_response = SLI_SE_RESPONSE_OK; + } + if (se_response != SLI_SE_RESPONSE_OK) { + goto exit; + } + } + + if (!ctx->last_op) { + // we need to do the final calculation first, such that we keep the input context intact + sli_se_mailbox_command_t gcm_cmd_enc_final = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_ENCRYPT | (first_op ? SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE : SLI_SE_COMMAND_OPTION_CONTEXT_END)); + + sli_se_datatransfer_t key_in_enc_final = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_ctx_in_enc_final = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_enc, (first_op ? ctx->iv_len : sizeof(ctx->se_ctx_enc))); + sli_se_datatransfer_t lenalenc_in_enc_final = SLI_SE_DATATRANSFER_DEFAULT(lena_lenc, sizeof(lena_lenc)); + sli_se_datatransfer_t data_in_enc_final = SLI_SE_DATATRANSFER_DEFAULT(ctx->mode == MBEDTLS_GCM_ENCRYPT ? (void*)input : (void*)output, input_length); + sli_se_datatransfer_t data_out_enc_final = SLI_SE_DATATRANSFER_DEFAULT(NULL, input_length); + data_out_enc_final.length |= SLI_SE_DATATRANSFER_DISCARD; + sli_se_datatransfer_t tag_out_final = SLI_SE_DATATRANSFER_DEFAULT(ctx->tagbuf, sizeof(ctx->tagbuf)); + + sli_se_mailbox_command_add_input(&gcm_cmd_enc_final, &key_in_enc_final); + sli_se_mailbox_command_add_input(&gcm_cmd_enc_final, &iv_ctx_in_enc_final); + sli_se_mailbox_command_add_input(&gcm_cmd_enc_final, &data_in_enc_final); + + if (!first_op) { + sli_se_mailbox_command_add_input(&gcm_cmd_enc_final, &lenalenc_in_enc_final); + } + + sli_se_mailbox_command_add_output(&gcm_cmd_enc_final, &data_out_enc_final); + sli_se_mailbox_command_add_output(&gcm_cmd_enc_final, &tag_out_final); + + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc_final, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc_final, 0); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc_final, input_length); + + sli_se_mailbox_execute_command(&gcm_cmd_enc_final); + se_response = sli_se_handle_mailbox_response(); + if (se_response != SLI_SE_RESPONSE_OK) { + goto exit; + } + } + + // Explicit scope block to help with stack usage optimisation + // Re-encrypt the decrypted data to keep the ongoing calculation alive in case we can + // continue calculation with another call to mbedtls_gcm_update. + { + sli_se_mailbox_command_t gcm_cmd_enc = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_ENCRYPT | (first_op ? SLI_SE_COMMAND_OPTION_CONTEXT_START : (ctx->last_op ? SLI_SE_COMMAND_OPTION_CONTEXT_END : SLI_SE_COMMAND_OPTION_CONTEXT_ADD))); + sli_se_datatransfer_t key_in_enc = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_ctx_in_enc = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_enc, (first_op ? ctx->iv_len : sizeof(ctx->se_ctx_enc))); + sli_se_datatransfer_t lenalenc_in_enc = SLI_SE_DATATRANSFER_DEFAULT(lena_lenc, sizeof(lena_lenc)); + sli_se_datatransfer_t data_in_enc = SLI_SE_DATATRANSFER_DEFAULT(ctx->mode == MBEDTLS_GCM_ENCRYPT ? (void*)input : (void*)output, input_length); + + sli_se_datatransfer_t data_out_enc = SLI_SE_DATATRANSFER_DEFAULT(output, input_length); + if (ctx->mode == MBEDTLS_GCM_DECRYPT) { + data_out_enc.data = NULL; + data_out_enc.length |= SLI_SE_DATATRANSFER_DISCARD; + } + + sli_se_datatransfer_t tag_out_enc = SLI_SE_DATATRANSFER_DEFAULT(ctx->tagbuf, sizeof(ctx->tagbuf)); + sli_se_datatransfer_t ctx_out_enc = SLI_SE_DATATRANSFER_DEFAULT(ctx->se_ctx_enc, sizeof(ctx->se_ctx_enc)); + + sli_se_mailbox_command_add_input(&gcm_cmd_enc, &key_in_enc); + sli_se_mailbox_command_add_input(&gcm_cmd_enc, &iv_ctx_in_enc); + sli_se_mailbox_command_add_input(&gcm_cmd_enc, &data_in_enc); + + if (ctx->last_op) { + sli_se_mailbox_command_add_input(&gcm_cmd_enc, &lenalenc_in_enc); + } + + sli_se_mailbox_command_add_output(&gcm_cmd_enc, &data_out_enc); + + if (ctx->last_op) { + sli_se_mailbox_command_add_output(&gcm_cmd_enc, &tag_out_enc); + } else { + sli_se_mailbox_command_add_output(&gcm_cmd_enc, &ctx_out_enc); + } + + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc, 0); + sli_se_mailbox_command_add_parameter(&gcm_cmd_enc, input_length); + + sli_se_mailbox_execute_command(&gcm_cmd_enc); + se_response = sli_se_handle_mailbox_response(); + } + + exit: + se_management_release(); + + if (se_response == SLI_SE_RESPONSE_OK) { + *output_length = input_length; + return(0); + } else { + mbedtls_zeroize(output, output_size); + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } +} + +int mbedtls_gcm_finish(mbedtls_gcm_context *ctx, + unsigned char *output, size_t output_size, + size_t *output_length, + unsigned char *tag, + size_t tag_len) +{ + // Voiding these because our implementation does not support + // partial-block input (i.e. passing a partial block to + // update() will have caused the operation to finish already) + (void) output; + (void) output_size; + *output_length = 0; + + if (ctx == NULL || tag == NULL) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + int status = sli_validate_gcm_params(tag_len, 12, 16); + if (status) { + return status; + } + + if (ctx->add_len == 0 && ctx->len == 0) { + return mbedtls_gcm_crypt_and_tag(ctx, MBEDTLS_GCM_ENCRYPT, + 0, ctx->se_ctx_enc, 12, + NULL, 0, + NULL, NULL, + tag_len, tag); + } + + memcpy(tag, ctx->tagbuf, tag_len); + return(0); +} + +int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag) +{ + sli_se_mailbox_response_t se_response; + uint8_t tagbuf[16]; + int status; + + /* Check input parameters. */ + if (ctx == NULL + || iv == NULL + || (add_len > 0 && add == NULL) + || (length > 0 && input == NULL) + || (length > 0 && output == NULL) + || tag == NULL) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + status = sli_validate_gcm_params(tag_len, iv_len, add_len); + if (status) { + return status; + } + + if ( mode == MBEDTLS_GCM_DECRYPT ) { + // Extract plaintext first + sli_se_mailbox_command_t gcm_cmd = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_DECRYPT | ((tag_len & 0xFF) << 8)); + + sli_se_datatransfer_t key_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_in = SLI_SE_DATATRANSFER_DEFAULT((void*)iv, iv_len); + sli_se_datatransfer_t aad_in = SLI_SE_DATATRANSFER_DEFAULT((void*)add, add_len); + sli_se_datatransfer_t data_in = SLI_SE_DATATRANSFER_DEFAULT((void*)input, length); + sli_se_datatransfer_t data_out = SLI_SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SLI_SE_DATATRANSFER_DISCARD; + } + sli_se_datatransfer_t tag_in = SLI_SE_DATATRANSFER_DEFAULT(tag, tag_len); + + sli_se_mailbox_command_add_input(&gcm_cmd, &key_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &iv_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &aad_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &data_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &tag_in); + + sli_se_mailbox_command_add_output(&gcm_cmd, &data_out); + + sli_se_mailbox_command_add_parameter(&gcm_cmd, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd, add_len); + sli_se_mailbox_command_add_parameter(&gcm_cmd, length); + + status = se_management_acquire(); + if (status != 0) { + return status; + } + sli_se_mailbox_execute_command(&gcm_cmd); + se_response = sli_se_handle_mailbox_response(); + se_management_release(); + // Getting an 'invalid signature' error here is acceptable, since we're not trying to verify the tag + if (se_response == SLI_SE_RESPONSE_INVALID_SIGNATURE) { + se_response = SLI_SE_RESPONSE_OK; + } + if (se_response != SLI_SE_RESPONSE_OK) { + goto exit; + } + // Re-encrypt the extracted plaintext to generate the tag to match + input = output; + output = NULL; + } + + // Explicit scope block to help with stack usage optimisation + { + sli_se_mailbox_command_t gcm_cmd = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_ENCRYPT); + + sli_se_datatransfer_t key_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_in = SLI_SE_DATATRANSFER_DEFAULT((void*)iv, iv_len); + sli_se_datatransfer_t aad_in = SLI_SE_DATATRANSFER_DEFAULT((void*)add, add_len); + sli_se_datatransfer_t data_in = SLI_SE_DATATRANSFER_DEFAULT((void*)input, length); + sli_se_datatransfer_t data_out = SLI_SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SLI_SE_DATATRANSFER_DISCARD; + } + sli_se_datatransfer_t mac_out = SLI_SE_DATATRANSFER_DEFAULT(tagbuf, sizeof(tagbuf)); + + sli_se_mailbox_command_add_input(&gcm_cmd, &key_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &iv_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &aad_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &data_in); + + sli_se_mailbox_command_add_output(&gcm_cmd, &data_out); + sli_se_mailbox_command_add_output(&gcm_cmd, &mac_out); + + sli_se_mailbox_command_add_parameter(&gcm_cmd, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd, add_len); + sli_se_mailbox_command_add_parameter(&gcm_cmd, length); + + status = se_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + sli_se_mailbox_execute_command(&gcm_cmd); + se_response = sli_se_handle_mailbox_response(); + se_management_release(); + } + + exit: + if (se_response == SLI_SE_RESPONSE_OK) { + // For encryption, copy requested tag size to output tag buffer. + memcpy(tag, tagbuf, tag_len); + return(0); + } else { + mbedtls_zeroize(output, length); + mbedtls_zeroize(tagbuf, sizeof(tagbuf)); + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } +} + +int mbedtls_gcm_auth_decrypt(mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output) +{ + sli_se_mailbox_response_t se_response; + int status; + + /* Check input parameters. */ + if (ctx == NULL + || iv == NULL + || (add_len > 0 && add == NULL) + || (length > 0 && input == NULL) + || (length > 0 && output == NULL) + || tag == NULL) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + status = sli_validate_gcm_params(tag_len, iv_len, add_len); + if (status) { + return status; + } + + // AES-GCM encryption and decryption are symmetrical. The SE only + // supports checking tag length of 16 bytes. In order to support + // smaller tag lengths, the decrypt-and-check routine is implemented + // as a call to encrypt-and-MAC, and a manual check of the MAC vs the + // expected MAC on the right tag length. + + sli_se_mailbox_command_t gcm_cmd = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_AES_GCM_DECRYPT | ((tag_len & 0xFF) << 8)); + + sli_se_datatransfer_t key_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->key, ctx->keybits / 8); + sli_se_datatransfer_t iv_in = SLI_SE_DATATRANSFER_DEFAULT((void*)iv, iv_len); + sli_se_datatransfer_t aad_in = SLI_SE_DATATRANSFER_DEFAULT((void*)add, add_len); + sli_se_datatransfer_t data_in = SLI_SE_DATATRANSFER_DEFAULT((void*)input, length); + sli_se_datatransfer_t data_out = SLI_SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SLI_SE_DATATRANSFER_DISCARD; + } + sli_se_datatransfer_t tag_in = SLI_SE_DATATRANSFER_DEFAULT((void*)tag, tag_len); + + sli_se_mailbox_command_add_input(&gcm_cmd, &key_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &iv_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &aad_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &data_in); + sli_se_mailbox_command_add_input(&gcm_cmd, &tag_in); + + sli_se_mailbox_command_add_output(&gcm_cmd, &data_out); + + sli_se_mailbox_command_add_parameter(&gcm_cmd, ctx->keybits / 8); + sli_se_mailbox_command_add_parameter(&gcm_cmd, add_len); + sli_se_mailbox_command_add_parameter(&gcm_cmd, length); + + status = se_management_acquire(); + if (status != 0) { + return status; + } + sli_se_mailbox_execute_command(&gcm_cmd); + se_response = sli_se_handle_mailbox_response(); + se_management_release(); + + if (se_response == SLI_SE_RESPONSE_OK) { + return(0); + } else { + mbedtls_zeroize(output, length); + if (se_response == SLI_SE_RESPONSE_INVALID_SIGNATURE) { + return(MBEDTLS_ERR_GCM_AUTH_FAILED); + } else { + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } + } +} + +void mbedtls_gcm_free(mbedtls_gcm_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + mbedtls_zeroize(ctx, sizeof(mbedtls_gcm_context) ); +} + +#endif /* MBEDTLS_GCM_ALT && MBEDTLS_GCM_C */ + +#endif /* CRYPTOACC_PRESENT */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_jpake.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_jpake.c new file mode 100644 index 000000000..fe57b5d8a --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/se_jpake.c @@ -0,0 +1,783 @@ +/***************************************************************************//** + * @file + * @brief ECC J-PAKE accelerated implementation + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of the standard + * mbedtls/libary/ecjpake.c using the secure engine incorporated in Series-2 + * devices with Secure Engine from Silicon Laboratories. + */ + +#include + +#if defined(MBEDTLS_ECJPAKE_ALT) && defined(MBEDTLS_ECJPAKE_C) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_manager_mailbox.h" +#include "se_management.h" +#include "mbedtls/ecjpake.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include + +static const char * const ecjpake_id[] = { + "client", + "server" +}; + +static int parse_tls_point(const uint8_t **ibuf, size_t *ilen, size_t *rlen, + uint8_t **obuf, size_t *olen) +{ + if (ilen == NULL || ibuf == NULL || obuf == NULL || olen == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + if (*ilen == 0 || *ibuf == NULL || *obuf == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // consume first byte, length of what follows + size_t field_length = **ibuf; + *ibuf += 1; + *ilen -= 1; + if (rlen != NULL) { + *rlen += 1; + } + + if (field_length > *ilen) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // consume second byte, point type + uint8_t point_type = **ibuf; + size_t point_length = field_length - 1; + *ibuf += 1; + *ilen -= 1; + + switch (point_type) { + case 0x0: + // Why would we ever get a zero-point? + return MBEDTLS_ERR_ECP_INVALID_KEY; + case 0x04: + break; + case 0x05: + // We don't support compressed points... + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // copy out binary point + if (point_length > *olen) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + memcpy(*obuf, *ibuf, point_length); + *ibuf += point_length; + *ilen -= point_length; + *obuf += point_length; + *olen -= point_length; + if (rlen != NULL) { + *rlen += field_length; + } + + return 0; +} + +static int parse_tls_zkp(const uint8_t **ibuf, size_t *ilen, size_t *rlen, + uint8_t **obuf, size_t *olen) +{ + if (ilen == NULL || ibuf == NULL || obuf == NULL || olen == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + if (*ilen == 0 || *ibuf == NULL || *obuf == NULL || *olen < 96) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + int ret = parse_tls_point(ibuf, ilen, rlen, obuf, olen); + if (ret != 0) { + return ret; + } + + if (*ilen < 1) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // consume first byte, length of what follows + size_t field_length = **ibuf; + *ibuf += 1; + *ilen -= 1; + if (rlen != NULL) { + *rlen += 1; + } + + if (field_length > *ilen || field_length > *olen) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + if (field_length == 0) { + // scalar cannot be zero + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // right-adjust + size_t adjust_length = 32 - field_length; + memset(*obuf, 0, adjust_length); + *obuf += adjust_length; + *olen -= adjust_length; + + // Consume field + memcpy(*obuf, *ibuf, field_length); + *obuf += field_length; + *olen -= field_length; + *ibuf += field_length; + *ilen -= field_length; + + if (rlen != NULL) { + *rlen += field_length; + } + + return 0; +} + +static int write_tls_point(uint8_t **obuf, size_t *olen, size_t *wlen, + const uint8_t **ibuf, size_t *ilen, size_t point_length) +{ + if (ibuf == NULL || obuf == NULL || olen == NULL || ilen == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + if (*obuf == NULL || *ibuf == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // We can only output uncompressed points here + if (*olen < point_length + 2) { + return MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL; + } + + if (*ilen < point_length) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + **obuf = point_length + 1; + *obuf += 1; + *olen -= 1; + + **obuf = 0x04; + *obuf += 1; + *olen -= 1; + + memcpy(*obuf, *ibuf, point_length); + + *obuf += point_length; + *olen -= point_length; + *ibuf += point_length; + *ilen -= point_length; + + if (wlen != NULL) { + *wlen += point_length + 2; + } + + return 0; +} + +static int write_tls_zkp(uint8_t **obuf, size_t *olen, size_t *wlen, + const uint8_t **ibuf, size_t *ilen, size_t point_length) +{ + int ret = 0; + + if (ibuf == NULL || obuf == NULL || olen == NULL || ilen == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + if (*obuf == NULL || *ibuf == NULL) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + ret = write_tls_point(obuf, olen, wlen, ibuf, ilen, point_length); + + if (ret != 0) { + return ret; + } + + size_t zkp_length = 32; + + if (*olen < zkp_length + 1 || *ilen < zkp_length) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + **obuf = zkp_length; + *obuf += 1; + *olen -= 1; + + memcpy(*obuf, *ibuf, zkp_length); + + *obuf += zkp_length; + *olen -= zkp_length; + *ibuf += zkp_length; + *ilen -= zkp_length; + + if (wlen != NULL) { + *wlen += zkp_length + 1; + } + + return 0; +} + +void mbedtls_ecjpake_init(mbedtls_ecjpake_context *ctx) +{ + memset(ctx, 0, sizeof(*ctx)); +} + +int mbedtls_ecjpake_setup(mbedtls_ecjpake_context *ctx, + mbedtls_ecjpake_role role, + mbedtls_md_type_t hash, + mbedtls_ecp_group_id curve, + const unsigned char *secret, + size_t len) +{ + if ( role != MBEDTLS_ECJPAKE_CLIENT && role != MBEDTLS_ECJPAKE_SERVER ) { + return(MBEDTLS_ERR_ECP_BAD_INPUT_DATA); + } + + // SE only supports passphrases of maximum 32 bytes + if (len > 32) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // SE currently only supports SHA256 as JPAKE hashing mechanism + if (hash != MBEDTLS_MD_SHA256) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + // SE currently only supports ECDSA secp256r1 as curve + if (curve != MBEDTLS_ECP_DP_SECP256R1) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + ctx->curve_flags = 0x8000001FUL; + ctx->role = role; + ctx->pwd_len = len; + memcpy(ctx->pwd, secret, len); + + return 0; +} + +int mbedtls_ecjpake_check(const mbedtls_ecjpake_context *ctx) +{ + if (ctx->curve_flags == 0) { + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + return 0; +} + +int mbedtls_ecjpake_set_point_format(mbedtls_ecjpake_context *ctx, + int point_format) +{ + switch (point_format) { + case MBEDTLS_ECP_PF_UNCOMPRESSED: + ctx->point_format = point_format; + return 0; + case MBEDTLS_ECP_PF_COMPRESSED: + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + default: + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } +} + +int mbedtls_ecjpake_write_round_one(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + // SE has internal RNG + (void)f_rng; + (void)p_rng; + + int ret = 0; + + // local storage for ZKPs + uint8_t zkp1[32 + 64]; + uint8_t zkp2[32 + 64]; + + *olen = 0; + + // SE command structures + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_JPAKE_R1_GENERATE); + sli_se_datatransfer_t domain_in = SLI_SE_DATATRANSFER_DEFAULT(NULL, 0); + sli_se_datatransfer_t userid = SLI_SE_DATATRANSFER_DEFAULT((void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); + sli_se_datatransfer_t r_out = SLI_SE_DATATRANSFER_DEFAULT(ctx->r, 32); + sli_se_datatransfer_t Xm1_out = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); + sli_se_datatransfer_t zkp1_out = SLI_SE_DATATRANSFER_DEFAULT(zkp1, sizeof(zkp1)); + sli_se_datatransfer_t Xm2_out = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xm2, 64); + sli_se_datatransfer_t zkp2_out = SLI_SE_DATATRANSFER_DEFAULT(zkp2, sizeof(zkp2)); + + sli_se_mailbox_command_add_input(&command, &domain_in); + sli_se_mailbox_command_add_input(&command, &userid); + sli_se_mailbox_command_add_output(&command, &r_out); + sli_se_mailbox_command_add_output(&command, &Xm1_out); + sli_se_mailbox_command_add_output(&command, &zkp1_out); + sli_se_mailbox_command_add_output(&command, &Xm2_out); + sli_se_mailbox_command_add_output(&command, &zkp2_out); + + sli_se_mailbox_command_add_parameter(&command, ctx->curve_flags); + sli_se_mailbox_command_add_parameter(&command, strlen(ecjpake_id[ctx->role])); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + + se_management_release(); + + if ( res == SLI_SE_RESPONSE_OK ) { + // To write TLS structures of ECJ-PAKE, we need to write: + // * Xm1 + // * zkp1 + // * Xm2 + // * zkp2 + uint8_t *obuf = buf; + const uint8_t *ibuf = ctx->Xm1; + size_t ilen = 64; + + ret = write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != 0) { + return ret; + } + + ibuf = zkp1; + ilen = 96; + ret = write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != 0) { + return ret; + } + + ibuf = ctx->Xm2; + ilen = 64; + ret = write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != 0) { + return ret; + } + + ibuf = zkp2; + ilen = 96; + ret = write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != 0) { + return ret; + } + + return 0; + } else { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} + +int mbedtls_ecjpake_read_round_one(mbedtls_ecjpake_context *ctx, + const unsigned char *buf, + size_t len) +{ + int ret = 0; + + // Should receive 2 binary points and 2 ZKPs + + // local storage for ZKPs + uint8_t zkp1[32 + 64] = { 0 }; + uint8_t zkp2[32 + 64] = { 0 }; + + uint8_t *obuf = ctx->Xp1; + size_t olen = 64; + + // Parse structures + ret = parse_tls_point(&buf, &len, NULL, &obuf, &olen); + if (ret != 0) { + return ret; + } + + obuf = zkp1; + olen = 96; + ret = parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); + if (ret != 0) { + return ret; + } + + obuf = ctx->Xp2; + olen = 64; + ret = parse_tls_point(&buf, &len, NULL, &obuf, &olen); + if (ret != 0) { + return ret; + } + + obuf = zkp2; + olen = 96; + ret = parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); + if (ret != 0) { + return ret; + } + + if (len > 0) { + // Too much input + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // SE command structures + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_JPAKE_R1_VERIFY); + sli_se_datatransfer_t domain_in = SLI_SE_DATATRANSFER_DEFAULT(NULL, 0); + sli_se_datatransfer_t userid_mine = SLI_SE_DATATRANSFER_DEFAULT((void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); + sli_se_datatransfer_t userid_peer = SLI_SE_DATATRANSFER_DEFAULT((void*)ecjpake_id[1 - ctx->role], strlen(ecjpake_id[1 - ctx->role])); + + sli_se_datatransfer_t Xp1_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); + sli_se_datatransfer_t zkp1_in = SLI_SE_DATATRANSFER_DEFAULT(zkp1, sizeof(zkp1)); + sli_se_datatransfer_t Xp2_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); + sli_se_datatransfer_t zkp2_in = SLI_SE_DATATRANSFER_DEFAULT(zkp2, sizeof(zkp2)); + + sli_se_mailbox_command_add_input(&command, &domain_in); + sli_se_mailbox_command_add_input(&command, &userid_mine); + sli_se_mailbox_command_add_input(&command, &userid_peer); + + sli_se_mailbox_command_add_input(&command, &Xp1_in); + sli_se_mailbox_command_add_input(&command, &zkp1_in); + sli_se_mailbox_command_add_input(&command, &Xp2_in); + sli_se_mailbox_command_add_input(&command, &zkp2_in); + + sli_se_mailbox_command_add_parameter(&command, ctx->curve_flags); + sli_se_mailbox_command_add_parameter(&command, strlen(ecjpake_id[ctx->role])); + sli_se_mailbox_command_add_parameter(&command, strlen(ecjpake_id[1 - ctx->role])); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + + se_management_release(); + + if ( res == SLI_SE_RESPONSE_OK ) { + return 0; + } else { + return MBEDTLS_ERR_ECP_VERIFY_FAILED; + } +} + +int mbedtls_ecjpake_write_round_two(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + // SE has internal RNG + (void)f_rng; + (void)p_rng; + + int ret = 0; + + *olen = 0; + + uint8_t zkpA[32 + 64]; + uint8_t xA[64]; + + // SE command structures + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_JPAKE_R2_GENERATE); + sli_se_datatransfer_t domain_in = SLI_SE_DATATRANSFER_DEFAULT(NULL, 0); + sli_se_datatransfer_t pwd_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->pwd, ctx->pwd_len); + sli_se_datatransfer_t userid = SLI_SE_DATATRANSFER_DEFAULT((void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); + sli_se_datatransfer_t r_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->r, 32); + sli_se_datatransfer_t Xm1_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); + sli_se_datatransfer_t Xp1_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); + sli_se_datatransfer_t Xp2_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); + + sli_se_datatransfer_t xA_out = SLI_SE_DATATRANSFER_DEFAULT(xA, sizeof(xA)); + sli_se_datatransfer_t zkpA_out = SLI_SE_DATATRANSFER_DEFAULT(zkpA, sizeof(zkpA)); + + sli_se_mailbox_command_add_input(&command, &domain_in); + sli_se_mailbox_command_add_input(&command, &pwd_in); + sli_se_mailbox_command_add_input(&command, &userid); + sli_se_mailbox_command_add_input(&command, &r_in); + sli_se_mailbox_command_add_input(&command, &Xm1_in); + sli_se_mailbox_command_add_input(&command, &Xp1_in); + sli_se_mailbox_command_add_input(&command, &Xp2_in); + + sli_se_mailbox_command_add_output(&command, &xA_out); + sli_se_mailbox_command_add_output(&command, &zkpA_out); + + sli_se_mailbox_command_add_parameter(&command, ctx->curve_flags); + sli_se_mailbox_command_add_parameter(&command, ctx->pwd_len); + sli_se_mailbox_command_add_parameter(&command, strlen(ecjpake_id[ctx->role])); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + + se_management_release(); + + if ( res == SLI_SE_RESPONSE_OK ) { + // If we are the server, we need to write out the ECParams + if ( ctx->role == MBEDTLS_ECJPAKE_SERVER ) { + if ( len < 3 + 66 + 66 + 33) { + return MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL; + } + const mbedtls_ecp_curve_info *curve_info; + + if ( (curve_info = mbedtls_ecp_curve_info_from_grp_id(MBEDTLS_ECP_DP_SECP256R1) ) == NULL ) { + return(MBEDTLS_ERR_ECP_BAD_INPUT_DATA); + } + + // First byte is curve_type, always named_curve + *(buf++) = MBEDTLS_ECP_TLS_NAMED_CURVE; + + // Next two bytes are the namedcurve value + *(buf++) = curve_info->tls_id >> 8; + *(buf++) = curve_info->tls_id & 0xFF; + + *olen += 3; + len -= 3; + } + + // To write TLS structures of ECJ-PAKE, we need to write: + // * XA in uncompressed form + // * zkpA in uncompressed form + uint8_t *obuf = buf; + const uint8_t *ibuf = xA; + size_t ilen = 64; + + ret = write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != 0) { + return ret; + } + + ibuf = zkpA; + ilen = 96; + ret = write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != 0) { + return ret; + } + + return 0; + } else { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} + +int mbedtls_ecjpake_read_round_two(mbedtls_ecjpake_context *ctx, + const unsigned char *buf, + size_t len) +{ + int ret = 0; + + // local storage for ZKP + uint8_t zkpB[32 + 64]; + + if ( ctx->role == MBEDTLS_ECJPAKE_CLIENT ) { + const mbedtls_ecp_curve_info *curve_info; + uint16_t tls_id; + + if ( len < 3 ) { + return(MBEDTLS_ERR_ECP_BAD_INPUT_DATA); + } + + // First byte is curve_type; only named_curve is handled + if ( *(buf++) != MBEDTLS_ECP_TLS_NAMED_CURVE ) { + return(MBEDTLS_ERR_ECP_BAD_INPUT_DATA); + } + + // Next two bytes are the namedcurve value + tls_id = *(buf++); + tls_id <<= 8; + tls_id |= *(buf++); + + if ( (curve_info = mbedtls_ecp_curve_info_from_tls_id(tls_id) ) == NULL ) { + return(MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED); + } + + if (curve_info->grp_id != MBEDTLS_ECP_DP_SECP256R1) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + len -= 3; + } + + // Should receive 1 binary point and 1 ZKP + uint8_t *obuf = ctx->Xp; + size_t olen = 64; + + // Parse structures + ret = parse_tls_point(&buf, &len, NULL, &obuf, &olen); + if (ret != 0) { + return ret; + } + + obuf = zkpB; + olen = sizeof(zkpB); + ret = parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); + if (ret != 0) { + return ret; + } + + if (len > 0) { + // Too much input + return MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + } + + // SE command structures + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_JPAKE_R2_VERIFY); + sli_se_datatransfer_t domain_in = SLI_SE_DATATRANSFER_DEFAULT(NULL, 0); + sli_se_datatransfer_t userid_peer = SLI_SE_DATATRANSFER_DEFAULT((void*)ecjpake_id[1 - ctx->role], strlen(ecjpake_id[1 - ctx->role])); + + sli_se_datatransfer_t Xm1_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); + sli_se_datatransfer_t Xm2_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xm2, 64); + sli_se_datatransfer_t Xp1_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); + sli_se_datatransfer_t Xp_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp, 64); + sli_se_datatransfer_t zkpB_in = SLI_SE_DATATRANSFER_DEFAULT(zkpB, sizeof(zkpB)); + + sli_se_mailbox_command_add_input(&command, &domain_in); + sli_se_mailbox_command_add_input(&command, &userid_peer); + + sli_se_mailbox_command_add_input(&command, &Xm1_in); + sli_se_mailbox_command_add_input(&command, &Xm2_in); + sli_se_mailbox_command_add_input(&command, &Xp1_in); + sli_se_mailbox_command_add_input(&command, &Xp_in); + sli_se_mailbox_command_add_input(&command, &zkpB_in); + + sli_se_mailbox_command_add_parameter(&command, ctx->curve_flags); + sli_se_mailbox_command_add_parameter(&command, strlen(ecjpake_id[1 - ctx->role])); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + + se_management_release(); + + if ( res == SLI_SE_RESPONSE_OK ) { + return 0; + } else { + return MBEDTLS_ERR_ECP_VERIFY_FAILED; + } +} + +int mbedtls_ecjpake_derive_secret(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + // SE has internal RNG + (void)f_rng; + (void)p_rng; + + if (len < 32) { + return MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL; + } + + // Generated session key needs to come out unprotected + uint32_t gen_key_flags = 32; + + // SE command structures + sli_se_mailbox_command_t command = SLI_SE_MAILBOX_COMMAND_DEFAULT(SLI_SE_COMMAND_JPAKE_GEN_SESSIONKEY | SLI_SE_COMMAND_OPTION_HASH_SHA256); + sli_se_datatransfer_t domain_in = SLI_SE_DATATRANSFER_DEFAULT(NULL, 0); + sli_se_datatransfer_t pwd_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->pwd, ctx->pwd_len); + + sli_se_datatransfer_t r_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->r, 32); + sli_se_datatransfer_t Xp2_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); + sli_se_datatransfer_t Xp_in = SLI_SE_DATATRANSFER_DEFAULT(ctx->Xp, 64); + sli_se_datatransfer_t key_out = SLI_SE_DATATRANSFER_DEFAULT(buf, 32); + + sli_se_mailbox_command_add_input(&command, &domain_in); + sli_se_mailbox_command_add_input(&command, &pwd_in); + + sli_se_mailbox_command_add_input(&command, &r_in); + sli_se_mailbox_command_add_input(&command, &Xp2_in); + sli_se_mailbox_command_add_input(&command, &Xp_in); + + sli_se_mailbox_command_add_output(&command, &key_out); + + sli_se_mailbox_command_add_parameter(&command, ctx->curve_flags); + sli_se_mailbox_command_add_parameter(&command, ctx->pwd_len); + sli_se_mailbox_command_add_parameter(&command, gen_key_flags); + + int status = se_management_acquire(); + if (status != 0) { + return status; + } + + sli_se_mailbox_execute_command(&command); + sli_se_mailbox_response_t res = sli_se_handle_mailbox_response(); + + se_management_release(); + + if ( res == SLI_SE_RESPONSE_OK ) { + *olen = 32; + return 0; + } else { + *olen = 0; + return MBEDTLS_ERR_ECP_VERIFY_FAILED; + } +} + +int mbedtls_ecjpake_write_shared_key(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + (void)ctx; + (void)buf; + (void)len; + (void)olen; + (void)f_rng; + (void)p_rng; + + return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; +} + +void mbedtls_ecjpake_free(mbedtls_ecjpake_context *ctx) +{ + if (ctx == NULL) { + return; + } + + memset(ctx, 0, sizeof(*ctx)); +} + +#endif /* #if defined(SEMAILBOX_PRESENT) */ + +#endif /* #if defined(MBEDTLS_ECJPAKE_ALT) && defined(MBEDTLS_ECJPAKE_C) */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c new file mode 100644 index 000000000..89b29b5f6 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_entropy_hardware.c @@ -0,0 +1,197 @@ +/***************************************************************************//** + * @file + * @brief Entropy driver for Silicon Labs devices. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// ------------------------------------- +// Includes + +#include + +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) +#include "entropy_poll.h" +#include "psa/crypto.h" + +#include "em_device.h" + +#if defined(MBEDTLS_TRNG_PRESENT) \ + || defined(SEMAILBOX_PRESENT) \ + || defined(CRYPTOACC_PRESENT) +#define SLI_ENTROPY_HAVE_TRNG +#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +/* If PSA is not configured with external RNG, do a forward declaration of the + * external RNG function here to allow us to call it for entropy as well. */ +psa_status_t mbedtls_psa_external_get_random( + void *context, + uint8_t *output, size_t output_size, size_t *output_length); +#endif +#endif + +#if !defined(MBEDTLS_ERR_ENTROPY_SOURCE_FAILED) +/* Repeat declaration of MBEDTLS_ERR_ENTROPY_SOURCE_FAILED since the full entropy.h + * header is not always a clean include. I.e. when mbedtls_hardware_poll is used + * without having the full entropy module (with collector) present, the header will + * potentially complain about missing a SHA256/SHA512 context structure definition. */ +#define MBEDTLS_ERR_ENTROPY_SOURCE_FAILED -0x003C +#endif + +/* For devices with an active TRNG errata, we need to rely on a different + * source of entropy. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + #define SLI_ENTROPY_REQUIRE_FALLBACK +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#include "em_system.h" // SYSTEM_ChipRevisionGet() +#endif + +// ------------------------------------- +// Local function definitions + +// Include radio entropy fallback if present & required +#if defined(MBEDTLS_ENTROPY_RAIL_PRESENT) \ + && (!defined(SLI_ENTROPY_HAVE_TRNG) || defined(SLI_ENTROPY_REQUIRE_FALLBACK)) +#include "rail.h" +static int rail_get_random(unsigned char *output, + size_t len, + size_t *out_len) +{ + uint16_t rail_entropy_request_len; + if (len > UINT16_MAX) { + rail_entropy_request_len = UINT16_MAX; + } else { + rail_entropy_request_len = (uint16_t)len; + } + + *out_len = (size_t)RAIL_GetRadioEntropy(RAIL_EFR32_HANDLE, + (uint8_t *)output, + rail_entropy_request_len); + return 0; +} +#endif // radio fallback + +#if defined(MBEDTLS_ENTROPY_ADC_C) \ + && (!defined(SLI_ENTROPY_HAVE_TRNG) || defined(SLI_ENTROPY_REQUIRE_FALLBACK)) +#if !defined(MBEDTLS_ENTROPY_ADC_INSTANCE) +#define MBEDTLS_ENTROPY_ADC_INSTANCE 0 +#endif + +#include "sl_entropy_adc.h" +static int adc_get_random(unsigned char *output, + size_t len, + size_t *out_len) +{ + mbedtls_entropy_adc_context adc_ctx; + int ret = -1; + + mbedtls_entropy_adc_init(&adc_ctx); + ret = mbedtls_entropy_adc_set_instance(&adc_ctx, MBEDTLS_ENTROPY_ADC_INSTANCE); + if (ret < 0) { + goto exit; + } + + ret = mbedtls_entropy_adc_poll(&adc_ctx, output, len, out_len); + + exit: + mbedtls_entropy_adc_free(&adc_ctx); + return ret; +} +#endif // ADC fallback + +#if (defined(MBEDTLS_ENTROPY_RAIL_PRESENT) || defined(MBEDTLS_ENTROPY_ADC_C)) \ + && (!defined(SLI_ENTROPY_HAVE_TRNG) || defined(SLI_ENTROPY_REQUIRE_FALLBACK)) +static int rail_adc_entropy(unsigned char *output, + size_t len, + size_t *olen) +{ + (void) output; + (void) len; + (void) olen; + + *olen = 0; + int ret = MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; + #if defined(MBEDTLS_ENTROPY_RAIL_PRESENT) + ret = rail_get_random(output, len, olen); + if (*olen > 0 && ret == 0) { + // Return if we actually gathered something + // Otherwise, fallback to the ADC source if it is available. + return ret; + } + #endif // MBEDTLS_ENTROPY_RAIL_PRESENT + #if defined(MBEDTLS_ENTROPY_ADC_C) + ret = adc_get_random(output, len, olen); + #endif // MBEDTLS_ENTROPY_ADC_C + return ret; +} +#endif // RAIL and ADC entropy + +// ------------------------------------- +// Global function definitions + +int mbedtls_hardware_poll(void *data, + unsigned char *output, + size_t len, + size_t *olen) +{ + (void)data; + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + // TRNG entropy on EFR32xG13 is under errata on revisions < A3 + SYSTEM_ChipRevision_TypeDef rev; + SYSTEM_ChipRevisionGet(&rev); + + if ((rev.major == 1) && (rev.minor < 3)) { + // On affected revisions, fall back to radio (prefered) or ADC entropy + return rail_adc_entropy(output, len, olen); + } +#elif defined(SLI_ENTROPY_REQUIRE_FALLBACK) + // Other devices for which this symbol is defined have TRNG erratas requiring + // fallback to other sources for all revisions. + return rail_adc_entropy(output, len, olen); +#endif + +#if !defined(SLI_ENTROPY_REQUIRE_FALLBACK) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + // Devices not requiring fallback (or fell through here because the active + // errata does not apply to the ICs revision) use a TRNG when available, but + // can also use the radio or ADC when no TRNG is present. + #if defined(SLI_ENTROPY_HAVE_TRNG) + psa_status_t status = mbedtls_psa_external_get_random(data, output, len, olen); + if (status == PSA_SUCCESS) { + return 0; + } else { + return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; + } + #else // SLI_ENTROPY_HAVE_TRNG + return rail_adc_entropy(output, len, olen); + #endif // SLI_ENTROPY_HAVE_TRNG +#endif +} + +#endif // MBEDTLS_ENTROPY_HARDWARE_ALT diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_entropy_nvseed.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_entropy_nvseed.c new file mode 100644 index 000000000..4ade21eda --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_entropy_nvseed.c @@ -0,0 +1,231 @@ +/***************************************************************************//** + * @file + * @brief Support for non-volatile-seed based entropy on Silicon Labs devices + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) + +#include +#include "em_device.h" +#include "nvm3_default.h" +#include "mbedtls/entropy.h" +#include "mbedtls/platform.h" + +#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) + #include "mbedtls/sha512.h" +#elif defined(MBEDTLS_ENTROPY_SHA256_ACCUMULATOR) + #include "mbedtls/sha256.h" +#else + #error "NV seed entropy requested, but no entropy accumulator available" +#endif + +// ----------------------------------------------------------------------------- +// Defines + +#ifndef SLI_NV_SEED_NVM3_ID +/** This NVM3 ID has been specifically allocated for the purpose of storing a + * non-volatile DRBG seed. The ID for where to store the seed can be overridden, + * but its default value should not be reused for any other purpose. */ +#define SLI_NV_SEED_NVM3_ID (0x870FFUL) +#endif + +// ----------------------------------------------------------------------------- +// Static variables + +static int sli_nv_seed_has_been_opened = 0; + +// ----------------------------------------------------------------------------- +// Static functions + +static int sli_nv_seed_init(void) +{ + if ( sli_nv_seed_has_been_opened == 0 ) { + Ecode_t nvm3_status = nvm3_initDefault(); + if ( nvm3_status != ECODE_NVM3_OK ) { + return MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR; + } + sli_nv_seed_has_been_opened = 1; + } + return 0; +} + +// If the seed hasn't been generated yet, or has somehow been lost (NVM3 area got wiped) +// then we generate a device unique seed by hashing the contents of the device unique +// data area (containing serial number, calibration data, etc) and the entire RAM content. +static int sli_nv_seed_generate(uint8_t *buffer, size_t requested_length) +{ + int ret; + #if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) + uint8_t hash_buffer[64]; + mbedtls_sha512_context ctx; + mbedtls_sha512_init(&ctx); + + ret = mbedtls_sha512_starts(&ctx, 0); + if (ret != 0) { + goto exit; + } + // Device info + ret = mbedtls_sha512_update(&ctx, (const unsigned char *)DEVINFO, sizeof(DEVINFO_TypeDef)); + if (ret != 0) { + goto exit; + } + // SRAM + ret = mbedtls_sha512_update(&ctx, (const unsigned char *)SRAM_BASE, SRAM_SIZE); + if (ret != 0) { + goto exit; + } + ret = mbedtls_sha512_finish(&ctx, hash_buffer); + if (ret != 0) { + goto exit; + } + #else + uint8_t hash_buffer[32]; + mbedtls_sha256_context ctx; + mbedtls_sha256_init(&ctx); + + ret = mbedtls_sha256_starts(&ctx, 0); + if (ret != 0) { + goto exit; + } + // Device info + ret = mbedtls_sha256_update(&ctx, (const unsigned char *)DEVINFO, sizeof(DEVINFO_TypeDef)); + if (ret != 0) { + goto exit; + } + // SRAM + ret = mbedtls_sha256_update(&ctx, (const unsigned char *)SRAM_BASE, SRAM_SIZE); + if (ret != 0) { + goto exit; + } + ret = mbedtls_sha256_finish(&ctx, hash_buffer); + if (ret != 0) { + goto exit; + } + #endif + if (sizeof(hash_buffer) < requested_length) { + ret = MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR; + } + + exit: + #if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) + mbedtls_sha512_free(&ctx); + #else + mbedtls_sha256_free(&ctx); + #endif + + if (ret == 0) { + memcpy(buffer, hash_buffer, requested_length); + } + return ret; +} + +// ----------------------------------------------------------------------------- +// Public functions + +/** + * This function implements the signature expected by the mbed TLS entropy + * module for reading a non-volatile seed. + * On Silicon Labs devices, this seed is auto-generated from the device- + * unique data (calibration data, serial number, ...) when no NV seed exists in + * non-volatile storage yet. + * When a seed is stored through sli_nv_seed_write it will be returned again + * by this function. + * + * The mbed TLS entropy module will call the seed write function itself each time + * the entropy module is initialised. + * + * This function is exposed to mbed TLS through setting the macro + * MBEDTLS_PLATFORM_STD_NV_SEED_READ to the function name (sli_nv_seed_read), + * in addition to MBEDTLS_PLATFORM_NV_SEED_ALT. + */ +int sli_nv_seed_read(unsigned char *buf, size_t buf_len) +{ + Ecode_t nvm3_status; + uint32_t obj_type; + size_t obj_len; + int ret; + + ret = sli_nv_seed_init(); + if ( ret != 0 ) { + return ret; + } + + nvm3_status = nvm3_getObjectInfo(nvm3_defaultHandle, SLI_NV_SEED_NVM3_ID, + &obj_type, &obj_len); + if ( nvm3_status == ECODE_NVM3_OK ) { + /* Fail safe when the NV seed is not large enough to satisfy the + * polling function from the entropy module. */ + if ( buf_len > obj_len ) { + return MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR; + } + + /* Read the requested amount of data from the seed */ + nvm3_status = nvm3_readPartialData(nvm3_defaultHandle, SLI_NV_SEED_NVM3_ID, + buf, 0, buf_len); + if ( nvm3_status != ECODE_NVM3_OK ) { + return MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR; + } + + return buf_len; + } else if ( nvm3_status == ECODE_NVM3_ERR_KEY_NOT_FOUND ) { + /* Generate a device-unique seed on first run */ + return sli_nv_seed_generate(buf, buf_len); + } else { + return MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR; + } +} + +/** + * This function implements the signature expected by the mbed TLS entropy + * module for writing a seed value to non-volatile memory. + * When the storage backend fails, it will return an error code. + * + * This function is exposed to mbed TLS through setting the macro + * MBEDTLS_PLATFORM_STD_NV_SEED_WRITE to the function name (sli_nv_seed_write), + * in addition to MBEDTLS_PLATFORM_NV_SEED_ALT. + */ +int sli_nv_seed_write(unsigned char *buf, size_t buf_len) +{ + Ecode_t nvm3_status; + int ret; + ret = sli_nv_seed_init(); + if ( ret != 0 ) { + return ret; + } + + nvm3_status = nvm3_writeData(nvm3_defaultHandle, SLI_NV_SEED_NVM3_ID, buf, buf_len); + if ( nvm3_status == ECODE_NVM3_OK ) { + return buf_len; + } else { + return MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR; + } +} + +#endif // MBEDTLS_PLATFORM_NV_SEED_ALT diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c new file mode 100644 index 000000000..82ebd2c35 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c @@ -0,0 +1,121 @@ +/***************************************************************************//** + * @file + * @brief Initialize the Silicon Labs platform integration of mbedTLS. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mbedtls.h" +#include "sl_assert.h" +#include "mbedtls/build_info.h" +#if !defined(SL_TRUSTZONE_NONSECURE) +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) +#include "sl_se_manager.h" +#endif +#if defined(CRYPTOACC_PRESENT) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + #include "cryptoacc_management.h" +#endif +#endif // #if !defined(SL_TRUSTZONE_NONSECURE) + +#if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#if defined(MBEDTLS_PSA_CRYPTO_C) +#include "cmsis_os2.h" +#include +static volatile bool mbedtls_psa_slots_mutex_inited = false; + +/** + * \brief Lock all task switches + * + * \return Previous lock state + * + */ +static inline int32_t lock_task_switches(void) +{ + int32_t kernel_lock_state = 0; + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + kernel_lock_state = osKernelLock(); + } + return kernel_lock_state; +} + +/** + * \brief Restores the previous lock state + */ +static inline void restore_lock_state(int32_t kernel_lock_state) +{ + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + if (osKernelRestoreLock(kernel_lock_state) < 0) { + EFM_ASSERT(false); + } + } +} + +#endif // defined(MBEDTLS_PSA_CRYPTO_C) +#endif // defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) + +void sl_mbedtls_init(void) +{ +#if !defined(SL_TRUSTZONE_NONSECURE) + +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + /* Initialize the SE Manager including the SE lock. + No need for critical region here since sl_se_init implements one. */ + sl_status_t ret; + ret = sl_se_init(); + EFM_ASSERT(ret == SL_STATUS_OK); +#endif + +#if defined(CRYPTOACC_PRESENT) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + // Set up SCA countermeasures in hardware + cryptoacc_initialize_countermeasures(); +#endif // SILICON_LABS_32B_SERIES_2_CONFIG > 2 + +#endif // #if !defined(SL_TRUSTZONE_NONSECURE) + +#if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) + mbedtls_threading_set_alt(&THREADING_InitMutex, + &THREADING_FreeMutex, + &THREADING_TakeMutexBlocking, + &THREADING_GiveMutex); + #if defined(MBEDTLS_PSA_CRYPTO_C) + // Initialize mutex for PSA slot access in psa_crypto_slot_management.c + if (!mbedtls_psa_slots_mutex_inited) { + int32_t kernel_lock_state = lock_task_switches(); + if (!mbedtls_psa_slots_mutex_inited) { + mbedtls_mutex_init(&mbedtls_threading_key_slot_mutex); + mbedtls_psa_slots_mutex_inited = true; + } + restore_lock_state(kernel_lock_state); + } + #endif // #if defined(MBEDTLS_PSA_CRYPTO_C) + #if defined(MBEDTLS_THREADING_TEST) + mbedtls_test_thread_set_alt(&THREADING_ThreadCreate, + &THREADING_ThreadJoin); + #endif //MBEDTLS_THREADING_TEST +#endif // #if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) +} diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c new file mode 100644 index 000000000..b3667279c --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c @@ -0,0 +1,77 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_psa_crypto.h" + +#include "sli_psa_driver_features.h" + +// ----------------------------------------------------------------------------- +// Global functions + +void sl_psa_set_key_lifetime_with_location_preference( + psa_key_attributes_t *attributes, + psa_key_persistence_t persistence, + psa_key_location_t preferred_location) +{ + psa_key_location_t selected_location = PSA_KEY_LOCATION_LOCAL_STORAGE; + + switch (preferred_location) { + // The underlying values for wrapped and built-in keys are the same. In + // order to avoid compiler errors, we therefore use #elif in order to make + // sure that we do not get identical switch labels. + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case SL_PSA_KEY_LOCATION_WRAPPED: + selected_location = SL_PSA_KEY_LOCATION_WRAPPED; + break; + #elif defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) + case SL_PSA_KEY_LOCATION_BUILTIN: + selected_location = SL_PSA_KEY_LOCATION_BUILTIN; + break; + #endif + + default: + // Use the already set PSA_KEY_LOCATION_LOCAL_STORAGE. + break; + } + + psa_key_lifetime_t lifetime = + PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, + selected_location); + psa_set_key_lifetime(attributes, lifetime); +} + +psa_key_location_t sl_psa_get_most_secure_key_location(void) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + return SL_PSA_KEY_LOCATION_WRAPPED; + #else + return PSA_KEY_LOCATION_LOCAL_STORAGE; + #endif +} diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c new file mode 100644 index 000000000..7d8cda687 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c @@ -0,0 +1,117 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs internal PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_crypto.h" + +#include "psa/crypto.h" + +#include "mbedtls/aes.h" +#include "mbedtls/ccm.h" +#include "mbedtls/cipher.h" +#include "mbedtls/ctr_drbg.h" +#include "mbedtls/entropy.h" +#include "mbedtls/md.h" +#include "mbedtls/nist_kw.h" +#include "mbedtls/pk.h" +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/ssl.h" +#include "mbedtls/ssl_cookie.h" +#include "mbedtls/x509_crt.h" + +// ----------------------------------------------------------------------------- +// Public function definitions + +size_t sli_psa_context_get_size(sli_psa_context_name_t ctx_type) +{ + switch (ctx_type) { + case SLI_PSA_CONTEXT_ENUM_NAME(psa_hash_operation_t): + return sizeof(psa_hash_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_cipher_operation_t): + return sizeof(psa_cipher_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_mac_operation_t): + return sizeof(psa_mac_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_aead_operation_t): + return sizeof(psa_aead_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_key_derivation_operation_t): + return sizeof(psa_key_derivation_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_pake_operation_t): + return sizeof(psa_pake_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_key_attributes_t): + return sizeof(psa_key_attributes_t); + default: + return 0; + } +} + +size_t sli_mbedtls_context_get_size(sli_mbedtls_context_name_t ctx_type) +{ + switch (ctx_type) { + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_aes_context): + return sizeof(mbedtls_aes_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ccm_context): + return sizeof(mbedtls_ccm_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_cipher_context_t): + return sizeof(mbedtls_cipher_context_t); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ctr_drbg_context): + return sizeof(mbedtls_ctr_drbg_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_entropy_context): + return sizeof(mbedtls_entropy_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_md_context_t): + return sizeof(mbedtls_md_context_t); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_nist_kw_context): + return sizeof(mbedtls_nist_kw_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_pk_context): + return sizeof(mbedtls_pk_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha1_context): + return sizeof(mbedtls_sha1_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha256_context): + return sizeof(mbedtls_sha256_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_config): + return sizeof(mbedtls_ssl_config); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_context): + return sizeof(mbedtls_ssl_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_cookie_ctx): + return sizeof(mbedtls_ssl_cookie_ctx); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_x509_crt): + return sizeof(mbedtls_x509_crt); + default: + return 0; + } +} + +bool sli_psa_key_is_unconditionally_copyable(psa_key_id_t key_id) +{ + bool is_persistent_zigbee_key = key_id >= SLI_PSA_KEY_ID_RANGE_ZIGBEE_START + && key_id <= SLI_PSA_KEY_ID_RANGE_ZIGBEE_END; + bool is_persistent_thread_key = key_id >= SLI_PSA_KEY_ID_RANGE_THREAD_START + && key_id <= SLI_PSA_KEY_ID_RANGE_THREAD_END; + return (is_persistent_zigbee_key || is_persistent_thread_key); +} diff --git a/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/version_features.c b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/version_features.c new file mode 100644 index 000000000..a89cef997 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_mbedtls_support/src/version_features.c @@ -0,0 +1,838 @@ +/* + * Version feature information + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_VERSION_C) + +#include "mbedtls/version.h" + +#include + +static const char * const features[] = { +#if defined(MBEDTLS_VERSION_FEATURES) + #if defined(MBEDTLS_HAVE_ASM) + "HAVE_ASM", //no-check-names +#endif /* MBEDTLS_HAVE_ASM */ +#if defined(MBEDTLS_NO_UDBL_DIVISION) + "NO_UDBL_DIVISION", //no-check-names +#endif /* MBEDTLS_NO_UDBL_DIVISION */ +#if defined(MBEDTLS_NO_64BIT_MULTIPLICATION) + "NO_64BIT_MULTIPLICATION", //no-check-names +#endif /* MBEDTLS_NO_64BIT_MULTIPLICATION */ +#if defined(MBEDTLS_HAVE_SSE2) + "HAVE_SSE2", //no-check-names +#endif /* MBEDTLS_HAVE_SSE2 */ +#if defined(MBEDTLS_HAVE_TIME) + "HAVE_TIME", //no-check-names +#endif /* MBEDTLS_HAVE_TIME */ +#if defined(MBEDTLS_HAVE_TIME_DATE) + "HAVE_TIME_DATE", //no-check-names +#endif /* MBEDTLS_HAVE_TIME_DATE */ +#if defined(MBEDTLS_PLATFORM_MEMORY) + "PLATFORM_MEMORY", //no-check-names +#endif /* MBEDTLS_PLATFORM_MEMORY */ +#if defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) + "PLATFORM_NO_STD_FUNCTIONS", //no-check-names +#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ +#if defined(MBEDTLS_PLATFORM_SETBUF_ALT) + "PLATFORM_SETBUF_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_SETBUF_ALT */ +#if defined(MBEDTLS_PLATFORM_EXIT_ALT) + "PLATFORM_EXIT_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_EXIT_ALT */ +#if defined(MBEDTLS_PLATFORM_TIME_ALT) + "PLATFORM_TIME_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_TIME_ALT */ +#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) + "PLATFORM_FPRINTF_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */ +#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) + "PLATFORM_PRINTF_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */ +#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) + "PLATFORM_SNPRINTF_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ +#if defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) + "PLATFORM_VSNPRINTF_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_VSNPRINTF_ALT */ +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) + "PLATFORM_NV_SEED_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */ +#if defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT) + "PLATFORM_SETUP_TEARDOWN_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ +#if defined(MBEDTLS_PLATFORM_MS_TIME_ALT) + "PLATFORM_MS_TIME_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_MS_TIME_ALT */ +#if defined(MBEDTLS_PLATFORM_GMTIME_R_ALT) + "PLATFORM_GMTIME_R_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_GMTIME_R_ALT */ +#if defined(MBEDTLS_PLATFORM_ZEROIZE_ALT) + "PLATFORM_ZEROIZE_ALT", //no-check-names +#endif /* MBEDTLS_PLATFORM_ZEROIZE_ALT */ +#if defined(MBEDTLS_DEPRECATED_WARNING) + "DEPRECATED_WARNING", //no-check-names +#endif /* MBEDTLS_DEPRECATED_WARNING */ +#if defined(MBEDTLS_DEPRECATED_REMOVED) + "DEPRECATED_REMOVED", //no-check-names +#endif /* MBEDTLS_DEPRECATED_REMOVED */ +#if defined(MBEDTLS_TIMING_ALT) + "TIMING_ALT", //no-check-names +#endif /* MBEDTLS_TIMING_ALT */ +#if defined(MBEDTLS_AES_ALT) + "AES_ALT", //no-check-names +#endif /* MBEDTLS_AES_ALT */ +#if defined(MBEDTLS_ARIA_ALT) + "ARIA_ALT", //no-check-names +#endif /* MBEDTLS_ARIA_ALT */ +#if defined(MBEDTLS_CAMELLIA_ALT) + "CAMELLIA_ALT", //no-check-names +#endif /* MBEDTLS_CAMELLIA_ALT */ +#if defined(MBEDTLS_CCM_ALT) + "CCM_ALT", //no-check-names +#endif /* MBEDTLS_CCM_ALT */ +#if defined(MBEDTLS_CHACHA20_ALT) + "CHACHA20_ALT", //no-check-names +#endif /* MBEDTLS_CHACHA20_ALT */ +#if defined(MBEDTLS_CHACHAPOLY_ALT) + "CHACHAPOLY_ALT", //no-check-names +#endif /* MBEDTLS_CHACHAPOLY_ALT */ +#if defined(MBEDTLS_CMAC_ALT) + "CMAC_ALT", //no-check-names +#endif /* MBEDTLS_CMAC_ALT */ +#if defined(MBEDTLS_DES_ALT) + "DES_ALT", //no-check-names +#endif /* MBEDTLS_DES_ALT */ +#if defined(MBEDTLS_DHM_ALT) + "DHM_ALT", //no-check-names +#endif /* MBEDTLS_DHM_ALT */ +#if defined(MBEDTLS_ECJPAKE_ALT) + "ECJPAKE_ALT", //no-check-names +#endif /* MBEDTLS_ECJPAKE_ALT */ +#if defined(MBEDTLS_GCM_ALT) + "GCM_ALT", //no-check-names +#endif /* MBEDTLS_GCM_ALT */ +#if defined(MBEDTLS_NIST_KW_ALT) + "NIST_KW_ALT", //no-check-names +#endif /* MBEDTLS_NIST_KW_ALT */ +#if defined(MBEDTLS_MD5_ALT) + "MD5_ALT", //no-check-names +#endif /* MBEDTLS_MD5_ALT */ +#if defined(MBEDTLS_POLY1305_ALT) + "POLY1305_ALT", //no-check-names +#endif /* MBEDTLS_POLY1305_ALT */ +#if defined(MBEDTLS_RIPEMD160_ALT) + "RIPEMD160_ALT", //no-check-names +#endif /* MBEDTLS_RIPEMD160_ALT */ +#if defined(MBEDTLS_RSA_ALT) + "RSA_ALT", //no-check-names +#endif /* MBEDTLS_RSA_ALT */ +#if defined(MBEDTLS_SHA1_ALT) + "SHA1_ALT", //no-check-names +#endif /* MBEDTLS_SHA1_ALT */ +#if defined(MBEDTLS_SHA256_ALT) + "SHA256_ALT", //no-check-names +#endif /* MBEDTLS_SHA256_ALT */ +#if defined(MBEDTLS_SHA512_ALT) + "SHA512_ALT", //no-check-names +#endif /* MBEDTLS_SHA512_ALT */ +#if defined(MBEDTLS_ECP_ALT) + "ECP_ALT", //no-check-names +#endif /* MBEDTLS_ECP_ALT */ +#if defined(MBEDTLS_MD5_PROCESS_ALT) + "MD5_PROCESS_ALT", //no-check-names +#endif /* MBEDTLS_MD5_PROCESS_ALT */ +#if defined(MBEDTLS_RIPEMD160_PROCESS_ALT) + "RIPEMD160_PROCESS_ALT", //no-check-names +#endif /* MBEDTLS_RIPEMD160_PROCESS_ALT */ +#if defined(MBEDTLS_SHA1_PROCESS_ALT) + "SHA1_PROCESS_ALT", //no-check-names +#endif /* MBEDTLS_SHA1_PROCESS_ALT */ +#if defined(MBEDTLS_SHA256_PROCESS_ALT) + "SHA256_PROCESS_ALT", //no-check-names +#endif /* MBEDTLS_SHA256_PROCESS_ALT */ +#if defined(MBEDTLS_SHA512_PROCESS_ALT) + "SHA512_PROCESS_ALT", //no-check-names +#endif /* MBEDTLS_SHA512_PROCESS_ALT */ +#if defined(MBEDTLS_DES_SETKEY_ALT) + "DES_SETKEY_ALT", //no-check-names +#endif /* MBEDTLS_DES_SETKEY_ALT */ +#if defined(MBEDTLS_DES_CRYPT_ECB_ALT) + "DES_CRYPT_ECB_ALT", //no-check-names +#endif /* MBEDTLS_DES_CRYPT_ECB_ALT */ +#if defined(MBEDTLS_DES3_CRYPT_ECB_ALT) + "DES3_CRYPT_ECB_ALT", //no-check-names +#endif /* MBEDTLS_DES3_CRYPT_ECB_ALT */ +#if defined(MBEDTLS_AES_SETKEY_ENC_ALT) + "AES_SETKEY_ENC_ALT", //no-check-names +#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */ +#if defined(MBEDTLS_AES_SETKEY_DEC_ALT) + "AES_SETKEY_DEC_ALT", //no-check-names +#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */ +#if defined(MBEDTLS_AES_ENCRYPT_ALT) + "AES_ENCRYPT_ALT", //no-check-names +#endif /* MBEDTLS_AES_ENCRYPT_ALT */ +#if defined(MBEDTLS_AES_DECRYPT_ALT) + "AES_DECRYPT_ALT", //no-check-names +#endif /* MBEDTLS_AES_DECRYPT_ALT */ +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) + "ECDH_GEN_PUBLIC_ALT", //no-check-names +#endif /* MBEDTLS_ECDH_GEN_PUBLIC_ALT */ +#if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) + "ECDH_COMPUTE_SHARED_ALT", //no-check-names +#endif /* MBEDTLS_ECDH_COMPUTE_SHARED_ALT */ +#if defined(MBEDTLS_ECDSA_VERIFY_ALT) + "ECDSA_VERIFY_ALT", //no-check-names +#endif /* MBEDTLS_ECDSA_VERIFY_ALT */ +#if defined(MBEDTLS_ECDSA_SIGN_ALT) + "ECDSA_SIGN_ALT", //no-check-names +#endif /* MBEDTLS_ECDSA_SIGN_ALT */ +#if defined(MBEDTLS_ECDSA_GENKEY_ALT) + "ECDSA_GENKEY_ALT", //no-check-names +#endif /* MBEDTLS_ECDSA_GENKEY_ALT */ +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + "ECP_INTERNAL_ALT", //no-check-names +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ +#if defined(MBEDTLS_ECP_NO_FALLBACK) + "ECP_NO_FALLBACK", //no-check-names +#endif /* MBEDTLS_ECP_NO_FALLBACK */ +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) + "ECP_RANDOMIZE_JAC_ALT", //no-check-names +#endif /* MBEDTLS_ECP_RANDOMIZE_JAC_ALT */ +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) + "ECP_ADD_MIXED_ALT", //no-check-names +#endif /* MBEDTLS_ECP_ADD_MIXED_ALT */ +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) + "ECP_DOUBLE_JAC_ALT", //no-check-names +#endif /* MBEDTLS_ECP_DOUBLE_JAC_ALT */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) + "ECP_NORMALIZE_JAC_MANY_ALT", //no-check-names +#endif /* MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) + "ECP_NORMALIZE_JAC_ALT", //no-check-names +#endif /* MBEDTLS_ECP_NORMALIZE_JAC_ALT */ +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) + "ECP_DOUBLE_ADD_MXZ_ALT", //no-check-names +#endif /* MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT */ +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) + "ECP_RANDOMIZE_MXZ_ALT", //no-check-names +#endif /* MBEDTLS_ECP_RANDOMIZE_MXZ_ALT */ +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) + "ECP_NORMALIZE_MXZ_ALT", //no-check-names +#endif /* MBEDTLS_ECP_NORMALIZE_MXZ_ALT */ +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) + "ENTROPY_HARDWARE_ALT", //no-check-names +#endif /* MBEDTLS_ENTROPY_HARDWARE_ALT */ +#if defined(MBEDTLS_AES_ROM_TABLES) + "AES_ROM_TABLES", //no-check-names +#endif /* MBEDTLS_AES_ROM_TABLES */ +#if defined(MBEDTLS_AES_FEWER_TABLES) + "AES_FEWER_TABLES", //no-check-names +#endif /* MBEDTLS_AES_FEWER_TABLES */ +#if defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + "AES_ONLY_128_BIT_KEY_LENGTH", //no-check-names +#endif /* MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH */ +#if defined(MBEDTLS_AES_USE_HARDWARE_ONLY) + "AES_USE_HARDWARE_ONLY", //no-check-names +#endif /* MBEDTLS_AES_USE_HARDWARE_ONLY */ +#if defined(MBEDTLS_CAMELLIA_SMALL_MEMORY) + "CAMELLIA_SMALL_MEMORY", //no-check-names +#endif /* MBEDTLS_CAMELLIA_SMALL_MEMORY */ +#if defined(MBEDTLS_CHECK_RETURN_WARNING) + "CHECK_RETURN_WARNING", //no-check-names +#endif /* MBEDTLS_CHECK_RETURN_WARNING */ +#if defined(MBEDTLS_CIPHER_MODE_CBC) + "CIPHER_MODE_CBC", //no-check-names +#endif /* MBEDTLS_CIPHER_MODE_CBC */ +#if defined(MBEDTLS_CIPHER_MODE_CFB) + "CIPHER_MODE_CFB", //no-check-names +#endif /* MBEDTLS_CIPHER_MODE_CFB */ +#if defined(MBEDTLS_CIPHER_MODE_CTR) + "CIPHER_MODE_CTR", //no-check-names +#endif /* MBEDTLS_CIPHER_MODE_CTR */ +#if defined(MBEDTLS_CIPHER_MODE_OFB) + "CIPHER_MODE_OFB", //no-check-names +#endif /* MBEDTLS_CIPHER_MODE_OFB */ +#if defined(MBEDTLS_CIPHER_MODE_XTS) + "CIPHER_MODE_XTS", //no-check-names +#endif /* MBEDTLS_CIPHER_MODE_XTS */ +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) + "CIPHER_NULL_CIPHER", //no-check-names +#endif /* MBEDTLS_CIPHER_NULL_CIPHER */ +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) + "CIPHER_PADDING_PKCS7", //no-check-names +#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ +#if defined(MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS) + "CIPHER_PADDING_ONE_AND_ZEROS", //no-check-names +#endif /* MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS */ +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN) + "CIPHER_PADDING_ZEROS_AND_LEN", //no-check-names +#endif /* MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN */ +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS) + "CIPHER_PADDING_ZEROS", //no-check-names +#endif /* MBEDTLS_CIPHER_PADDING_ZEROS */ +#if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) + "CTR_DRBG_USE_128_BIT_KEY", //no-check-names +#endif /* MBEDTLS_CTR_DRBG_USE_128_BIT_KEY */ +#if defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) + "ECDH_VARIANT_EVEREST_ENABLED", //no-check-names +#endif /* MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + "ECP_DP_SECP192R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + "ECP_DP_SECP224R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + "ECP_DP_SECP256R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + "ECP_DP_SECP384R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + "ECP_DP_SECP521R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + "ECP_DP_SECP192K1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + "ECP_DP_SECP224K1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + "ECP_DP_SECP256K1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + "ECP_DP_BP256R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + "ECP_DP_BP384R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + "ECP_DP_BP512R1_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + "ECP_DP_CURVE25519_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + "ECP_DP_CURVE448_ENABLED", //no-check-names +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ +#if defined(MBEDTLS_ECP_NIST_OPTIM) + "ECP_NIST_OPTIM", //no-check-names +#endif /* MBEDTLS_ECP_NIST_OPTIM */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + "ECP_RESTARTABLE", //no-check-names +#endif /* MBEDTLS_ECP_RESTARTABLE */ +#if defined(MBEDTLS_ECP_WITH_MPI_UINT) + "ECP_WITH_MPI_UINT", //no-check-names +#endif /* MBEDTLS_ECP_WITH_MPI_UINT */ +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) + "ECDSA_DETERMINISTIC", //no-check-names +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ +#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) + "KEY_EXCHANGE_PSK_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_PSK_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) + "KEY_EXCHANGE_DHE_PSK_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) + "KEY_EXCHANGE_ECDHE_PSK_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) + "KEY_EXCHANGE_RSA_PSK_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) + "KEY_EXCHANGE_RSA_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_RSA_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) + "KEY_EXCHANGE_DHE_RSA_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) + "KEY_EXCHANGE_ECDHE_RSA_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) + "KEY_EXCHANGE_ECDHE_ECDSA_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) + "KEY_EXCHANGE_ECDH_ECDSA_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) + "KEY_EXCHANGE_ECDH_RSA_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) + "KEY_EXCHANGE_ECJPAKE_ENABLED", //no-check-names +#endif /* MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ +#if defined(MBEDTLS_PK_PARSE_EC_EXTENDED) + "PK_PARSE_EC_EXTENDED", //no-check-names +#endif /* MBEDTLS_PK_PARSE_EC_EXTENDED */ +#if defined(MBEDTLS_PK_PARSE_EC_COMPRESSED) + "PK_PARSE_EC_COMPRESSED", //no-check-names +#endif /* MBEDTLS_PK_PARSE_EC_COMPRESSED */ +#if defined(MBEDTLS_ERROR_STRERROR_DUMMY) + "ERROR_STRERROR_DUMMY", //no-check-names +#endif /* MBEDTLS_ERROR_STRERROR_DUMMY */ +#if defined(MBEDTLS_GENPRIME) + "GENPRIME", //no-check-names +#endif /* MBEDTLS_GENPRIME */ +#if defined(MBEDTLS_FS_IO) + "FS_IO", //no-check-names +#endif /* MBEDTLS_FS_IO */ +#if defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) + "NO_DEFAULT_ENTROPY_SOURCES", //no-check-names +#endif /* MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES */ +#if defined(MBEDTLS_NO_PLATFORM_ENTROPY) + "NO_PLATFORM_ENTROPY", //no-check-names +#endif /* MBEDTLS_NO_PLATFORM_ENTROPY */ +#if defined(MBEDTLS_ENTROPY_FORCE_SHA256) + "ENTROPY_FORCE_SHA256", //no-check-names +#endif /* MBEDTLS_ENTROPY_FORCE_SHA256 */ +#if defined(MBEDTLS_ENTROPY_NV_SEED) + "ENTROPY_NV_SEED", //no-check-names +#endif /* MBEDTLS_ENTROPY_NV_SEED */ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + "PSA_CRYPTO_KEY_ID_ENCODES_OWNER", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ +#if defined(MBEDTLS_MEMORY_DEBUG) + "MEMORY_DEBUG", //no-check-names +#endif /* MBEDTLS_MEMORY_DEBUG */ +#if defined(MBEDTLS_MEMORY_BACKTRACE) + "MEMORY_BACKTRACE", //no-check-names +#endif /* MBEDTLS_MEMORY_BACKTRACE */ +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) + "PK_RSA_ALT_SUPPORT", //no-check-names +#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ +#if defined(MBEDTLS_PKCS1_V15) + "PKCS1_V15", //no-check-names +#endif /* MBEDTLS_PKCS1_V15 */ +#if defined(MBEDTLS_PKCS1_V21) + "PKCS1_V21", //no-check-names +#endif /* MBEDTLS_PKCS1_V21 */ +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + "PSA_CRYPTO_BUILTIN_KEYS", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ +#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) + "PSA_CRYPTO_CLIENT", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_CLIENT */ +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + "PSA_CRYPTO_EXTERNAL_RNG", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ +#if defined(MBEDTLS_PSA_CRYPTO_SPM) + "PSA_CRYPTO_SPM", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_SPM */ +#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) + "PSA_P256M_DRIVER_ENABLED", //no-check-names +#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) + "PSA_INJECT_ENTROPY", //no-check-names +#endif /* MBEDTLS_PSA_INJECT_ENTROPY */ +#if defined(MBEDTLS_RSA_NO_CRT) + "RSA_NO_CRT", //no-check-names +#endif /* MBEDTLS_RSA_NO_CRT */ +#if defined(MBEDTLS_SELF_TEST) + "SELF_TEST", //no-check-names +#endif /* MBEDTLS_SELF_TEST */ +#if defined(MBEDTLS_SHA256_SMALLER) + "SHA256_SMALLER", //no-check-names +#endif /* MBEDTLS_SHA256_SMALLER */ +#if defined(MBEDTLS_SHA512_SMALLER) + "SHA512_SMALLER", //no-check-names +#endif /* MBEDTLS_SHA512_SMALLER */ +#if defined(MBEDTLS_SSL_ALL_ALERT_MESSAGES) + "SSL_ALL_ALERT_MESSAGES", //no-check-names +#endif /* MBEDTLS_SSL_ALL_ALERT_MESSAGES */ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + "SSL_DTLS_CONNECTION_ID", //no-check-names +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT) + "SSL_DTLS_CONNECTION_ID_COMPAT", //no-check-names +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT */ +#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) + "SSL_ASYNC_PRIVATE", //no-check-names +#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ +#if defined(MBEDTLS_SSL_CONTEXT_SERIALIZATION) + "SSL_CONTEXT_SERIALIZATION", //no-check-names +#endif /* MBEDTLS_SSL_CONTEXT_SERIALIZATION */ +#if defined(MBEDTLS_SSL_DEBUG_ALL) + "SSL_DEBUG_ALL", //no-check-names +#endif /* MBEDTLS_SSL_DEBUG_ALL */ +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + "SSL_ENCRYPT_THEN_MAC", //no-check-names +#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */ +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) + "SSL_EXTENDED_MASTER_SECRET", //no-check-names +#endif /* MBEDTLS_SSL_EXTENDED_MASTER_SECRET */ +#if defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) + "SSL_KEEP_PEER_CERTIFICATE", //no-check-names +#endif /* MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ +#if defined(MBEDTLS_SSL_RENEGOTIATION) + "SSL_RENEGOTIATION", //no-check-names +#endif /* MBEDTLS_SSL_RENEGOTIATION */ +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) + "SSL_MAX_FRAGMENT_LENGTH", //no-check-names +#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ +#if defined(MBEDTLS_SSL_RECORD_SIZE_LIMIT) + "SSL_RECORD_SIZE_LIMIT", //no-check-names +#endif /* MBEDTLS_SSL_RECORD_SIZE_LIMIT */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + "SSL_PROTO_TLS1_2", //no-check-names +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + "SSL_PROTO_TLS1_3", //no-check-names +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ +#if defined(MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE) + "SSL_TLS1_3_COMPATIBILITY_MODE", //no-check-names +#endif /* MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE */ +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED) + "SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED", //no-check-names +#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED */ +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) + "SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED", //no-check-names +#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED */ +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) + "SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED", //no-check-names +#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED */ +#if defined(MBEDTLS_SSL_EARLY_DATA) + "SSL_EARLY_DATA", //no-check-names +#endif /* MBEDTLS_SSL_EARLY_DATA */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + "SSL_PROTO_DTLS", //no-check-names +#endif /* MBEDTLS_SSL_PROTO_DTLS */ +#if defined(MBEDTLS_SSL_ALPN) + "SSL_ALPN", //no-check-names +#endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) + "SSL_DTLS_ANTI_REPLAY", //no-check-names +#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */ +#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) + "SSL_DTLS_HELLO_VERIFY", //no-check-names +#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + "SSL_DTLS_SRTP", //no-check-names +#endif /* MBEDTLS_SSL_DTLS_SRTP */ +#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) + "SSL_DTLS_CLIENT_PORT_REUSE", //no-check-names +#endif /* MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE */ +#if defined(MBEDTLS_SSL_SESSION_TICKETS) + "SSL_SESSION_TICKETS", //no-check-names +#endif /* MBEDTLS_SSL_SESSION_TICKETS */ +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) + "SSL_SERVER_NAME_INDICATION", //no-check-names +#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ +#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) + "SSL_VARIABLE_BUFFER_LENGTH", //no-check-names +#endif /* MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH */ +#if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) + "TEST_CONSTANT_FLOW_MEMSAN", //no-check-names +#endif /* MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN */ +#if defined(MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND) + "TEST_CONSTANT_FLOW_VALGRIND", //no-check-names +#endif /* MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND */ +#if defined(MBEDTLS_TEST_HOOKS) + "TEST_HOOKS", //no-check-names +#endif /* MBEDTLS_TEST_HOOKS */ +#if defined(MBEDTLS_THREADING_ALT) + "THREADING_ALT", //no-check-names +#endif /* MBEDTLS_THREADING_ALT */ +#if defined(MBEDTLS_THREADING_PTHREAD) + "THREADING_PTHREAD", //no-check-names +#endif /* MBEDTLS_THREADING_PTHREAD */ +#if defined(MBEDTLS_USE_PSA_CRYPTO) + "USE_PSA_CRYPTO", //no-check-names +#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) + "PSA_CRYPTO_CONFIG", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_CONFIG */ +#if defined(MBEDTLS_VERSION_FEATURES) + "VERSION_FEATURES", //no-check-names +#endif /* MBEDTLS_VERSION_FEATURES */ +#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) + "X509_TRUSTED_CERTIFICATE_CALLBACK", //no-check-names +#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ +#if defined(MBEDTLS_X509_REMOVE_INFO) + "X509_REMOVE_INFO", //no-check-names +#endif /* MBEDTLS_X509_REMOVE_INFO */ +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) + "X509_RSASSA_PSS_SUPPORT", //no-check-names +#endif /* MBEDTLS_X509_RSASSA_PSS_SUPPORT */ +#if defined(MBEDTLS_AESNI_C) + "AESNI_C", //no-check-names +#endif /* MBEDTLS_AESNI_C */ +#if defined(MBEDTLS_AESCE_C) + "AESCE_C", //no-check-names +#endif /* MBEDTLS_AESCE_C */ +#if defined(MBEDTLS_AES_C) + "AES_C", //no-check-names +#endif /* MBEDTLS_AES_C */ +#if defined(MBEDTLS_ASN1_PARSE_C) + "ASN1_PARSE_C", //no-check-names +#endif /* MBEDTLS_ASN1_PARSE_C */ +#if defined(MBEDTLS_ASN1_WRITE_C) + "ASN1_WRITE_C", //no-check-names +#endif /* MBEDTLS_ASN1_WRITE_C */ +#if defined(MBEDTLS_BASE64_C) + "BASE64_C", //no-check-names +#endif /* MBEDTLS_BASE64_C */ +#if defined(MBEDTLS_BIGNUM_C) + "BIGNUM_C", //no-check-names +#endif /* MBEDTLS_BIGNUM_C */ +#if defined(MBEDTLS_CAMELLIA_C) + "CAMELLIA_C", //no-check-names +#endif /* MBEDTLS_CAMELLIA_C */ +#if defined(MBEDTLS_ARIA_C) + "ARIA_C", //no-check-names +#endif /* MBEDTLS_ARIA_C */ +#if defined(MBEDTLS_CCM_C) + "CCM_C", //no-check-names +#endif /* MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CHACHA20_C) + "CHACHA20_C", //no-check-names +#endif /* MBEDTLS_CHACHA20_C */ +#if defined(MBEDTLS_CHACHAPOLY_C) + "CHACHAPOLY_C", //no-check-names +#endif /* MBEDTLS_CHACHAPOLY_C */ +#if defined(MBEDTLS_CIPHER_C) + "CIPHER_C", //no-check-names +#endif /* MBEDTLS_CIPHER_C */ +#if defined(MBEDTLS_CMAC_C) + "CMAC_C", //no-check-names +#endif /* MBEDTLS_CMAC_C */ +#if defined(MBEDTLS_CTR_DRBG_C) + "CTR_DRBG_C", //no-check-names +#endif /* MBEDTLS_CTR_DRBG_C */ +#if defined(MBEDTLS_DEBUG_C) + "DEBUG_C", //no-check-names +#endif /* MBEDTLS_DEBUG_C */ +#if defined(MBEDTLS_DES_C) + "DES_C", //no-check-names +#endif /* MBEDTLS_DES_C */ +#if defined(MBEDTLS_DHM_C) + "DHM_C", //no-check-names +#endif /* MBEDTLS_DHM_C */ +#if defined(MBEDTLS_ECDH_C) + "ECDH_C", //no-check-names +#endif /* MBEDTLS_ECDH_C */ +#if defined(MBEDTLS_ECDSA_C) + "ECDSA_C", //no-check-names +#endif /* MBEDTLS_ECDSA_C */ +#if defined(MBEDTLS_ECJPAKE_C) + "ECJPAKE_C", //no-check-names +#endif /* MBEDTLS_ECJPAKE_C */ +#if defined(MBEDTLS_ECP_C) + "ECP_C", //no-check-names +#endif /* MBEDTLS_ECP_C */ +#if defined(MBEDTLS_ENTROPY_C) + "ENTROPY_C", //no-check-names +#endif /* MBEDTLS_ENTROPY_C */ +#if defined(MBEDTLS_ERROR_C) + "ERROR_C", //no-check-names +#endif /* MBEDTLS_ERROR_C */ +#if defined(MBEDTLS_GCM_C) + "GCM_C", //no-check-names +#endif /* MBEDTLS_GCM_C */ +#if defined(MBEDTLS_HKDF_C) + "HKDF_C", //no-check-names +#endif /* MBEDTLS_HKDF_C */ +#if defined(MBEDTLS_HMAC_DRBG_C) + "HMAC_DRBG_C", //no-check-names +#endif /* MBEDTLS_HMAC_DRBG_C */ +#if defined(MBEDTLS_LMS_C) + "LMS_C", //no-check-names +#endif /* MBEDTLS_LMS_C */ +#if defined(MBEDTLS_LMS_PRIVATE) + "LMS_PRIVATE", //no-check-names +#endif /* MBEDTLS_LMS_PRIVATE */ +#if defined(MBEDTLS_NIST_KW_C) + "NIST_KW_C", //no-check-names +#endif /* MBEDTLS_NIST_KW_C */ +#if defined(MBEDTLS_MD_C) + "MD_C", //no-check-names +#endif /* MBEDTLS_MD_C */ +#if defined(MBEDTLS_MD5_C) + "MD5_C", //no-check-names +#endif /* MBEDTLS_MD5_C */ +#if defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) + "MEMORY_BUFFER_ALLOC_C", //no-check-names +#endif /* MBEDTLS_MEMORY_BUFFER_ALLOC_C */ +#if defined(MBEDTLS_NET_C) + "NET_C", //no-check-names +#endif /* MBEDTLS_NET_C */ +#if defined(MBEDTLS_OID_C) + "OID_C", //no-check-names +#endif /* MBEDTLS_OID_C */ +#if defined(MBEDTLS_PADLOCK_C) + "PADLOCK_C", //no-check-names +#endif /* MBEDTLS_PADLOCK_C */ +#if defined(MBEDTLS_PEM_PARSE_C) + "PEM_PARSE_C", //no-check-names +#endif /* MBEDTLS_PEM_PARSE_C */ +#if defined(MBEDTLS_PEM_WRITE_C) + "PEM_WRITE_C", //no-check-names +#endif /* MBEDTLS_PEM_WRITE_C */ +#if defined(MBEDTLS_PK_C) + "PK_C", //no-check-names +#endif /* MBEDTLS_PK_C */ +#if defined(MBEDTLS_PK_PARSE_C) + "PK_PARSE_C", //no-check-names +#endif /* MBEDTLS_PK_PARSE_C */ +#if defined(MBEDTLS_PK_WRITE_C) + "PK_WRITE_C", //no-check-names +#endif /* MBEDTLS_PK_WRITE_C */ +#if defined(MBEDTLS_PKCS5_C) + "PKCS5_C", //no-check-names +#endif /* MBEDTLS_PKCS5_C */ +#if defined(MBEDTLS_PKCS7_C) + "PKCS7_C", //no-check-names +#endif /* MBEDTLS_PKCS7_C */ +#if defined(MBEDTLS_PKCS12_C) + "PKCS12_C", //no-check-names +#endif /* MBEDTLS_PKCS12_C */ +#if defined(MBEDTLS_PLATFORM_C) + "PLATFORM_C", //no-check-names +#endif /* MBEDTLS_PLATFORM_C */ +#if defined(MBEDTLS_POLY1305_C) + "POLY1305_C", //no-check-names +#endif /* MBEDTLS_POLY1305_C */ +#if defined(MBEDTLS_PSA_CRYPTO_C) + "PSA_CRYPTO_C", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_C */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + "PSA_CRYPTO_SE_C", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) + "PSA_CRYPTO_STORAGE_C", //no-check-names +#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ +#if defined(MBEDTLS_PSA_ITS_FILE_C) + "PSA_ITS_FILE_C", //no-check-names +#endif /* MBEDTLS_PSA_ITS_FILE_C */ +#if defined(MBEDTLS_RIPEMD160_C) + "RIPEMD160_C", //no-check-names +#endif /* MBEDTLS_RIPEMD160_C */ +#if defined(MBEDTLS_RSA_C) + "RSA_C", //no-check-names +#endif /* MBEDTLS_RSA_C */ +#if defined(MBEDTLS_SHA1_C) + "SHA1_C", //no-check-names +#endif /* MBEDTLS_SHA1_C */ +#if defined(MBEDTLS_SHA224_C) + "SHA224_C", //no-check-names +#endif /* MBEDTLS_SHA224_C */ +#if defined(MBEDTLS_SHA256_C) + "SHA256_C", //no-check-names +#endif /* MBEDTLS_SHA256_C */ +#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) + "SHA256_USE_A64_CRYPTO_IF_PRESENT", //no-check-names +#endif /* MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT */ +#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) + "SHA256_USE_A64_CRYPTO_ONLY", //no-check-names +#endif /* MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY */ +#if defined(MBEDTLS_SHA384_C) + "SHA384_C", //no-check-names +#endif /* MBEDTLS_SHA384_C */ +#if defined(MBEDTLS_SHA512_C) + "SHA512_C", //no-check-names +#endif /* MBEDTLS_SHA512_C */ +#if defined(MBEDTLS_SHA3_C) + "SHA3_C", //no-check-names +#endif /* MBEDTLS_SHA3_C */ +#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) + "SHA512_USE_A64_CRYPTO_IF_PRESENT", //no-check-names +#endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT */ +#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) + "SHA512_USE_A64_CRYPTO_ONLY", //no-check-names +#endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ +#if defined(MBEDTLS_SSL_CACHE_C) + "SSL_CACHE_C", //no-check-names +#endif /* MBEDTLS_SSL_CACHE_C */ +#if defined(MBEDTLS_SSL_COOKIE_C) + "SSL_COOKIE_C", //no-check-names +#endif /* MBEDTLS_SSL_COOKIE_C */ +#if defined(MBEDTLS_SSL_TICKET_C) + "SSL_TICKET_C", //no-check-names +#endif /* MBEDTLS_SSL_TICKET_C */ +#if defined(MBEDTLS_SSL_CLI_C) + "SSL_CLI_C", //no-check-names +#endif /* MBEDTLS_SSL_CLI_C */ +#if defined(MBEDTLS_SSL_SRV_C) + "SSL_SRV_C", //no-check-names +#endif /* MBEDTLS_SSL_SRV_C */ +#if defined(MBEDTLS_SSL_TLS_C) + "SSL_TLS_C", //no-check-names +#endif /* MBEDTLS_SSL_TLS_C */ +#if defined(MBEDTLS_THREADING_C) + "THREADING_C", //no-check-names +#endif /* MBEDTLS_THREADING_C */ +#if defined(MBEDTLS_TIMING_C) + "TIMING_C", //no-check-names +#endif /* MBEDTLS_TIMING_C */ +#if defined(MBEDTLS_VERSION_C) + "VERSION_C", //no-check-names +#endif /* MBEDTLS_VERSION_C */ +#if defined(MBEDTLS_X509_USE_C) + "X509_USE_C", //no-check-names +#endif /* MBEDTLS_X509_USE_C */ +#if defined(MBEDTLS_X509_CRT_PARSE_C) + "X509_CRT_PARSE_C", //no-check-names +#endif /* MBEDTLS_X509_CRT_PARSE_C */ +#if defined(MBEDTLS_X509_CRL_PARSE_C) + "X509_CRL_PARSE_C", //no-check-names +#endif /* MBEDTLS_X509_CRL_PARSE_C */ +#if defined(MBEDTLS_X509_CSR_PARSE_C) + "X509_CSR_PARSE_C", //no-check-names +#endif /* MBEDTLS_X509_CSR_PARSE_C */ +#if defined(MBEDTLS_X509_CREATE_C) + "X509_CREATE_C", //no-check-names +#endif /* MBEDTLS_X509_CREATE_C */ +#if defined(MBEDTLS_X509_CRT_WRITE_C) + "X509_CRT_WRITE_C", //no-check-names +#endif /* MBEDTLS_X509_CRT_WRITE_C */ +#if defined(MBEDTLS_X509_CSR_WRITE_C) + "X509_CSR_WRITE_C", //no-check-names +#endif /* MBEDTLS_X509_CSR_WRITE_C */ +#endif /* MBEDTLS_VERSION_FEATURES */ + NULL +}; + +int mbedtls_version_check_feature(const char *feature) +{ + const char * const *idx = features; + + if (*idx == NULL) { + return -2; + } + + if (feature == NULL) { + return -1; + } + + if (strncmp(feature, "MBEDTLS_", 8)) { + return -1; + } + + feature += 8; + + while (*idx != NULL) { + if (!strcmp(*idx, feature)) { + return 0; + } + idx++; + } + return -1; +} + +#endif /* MBEDTLS_VERSION_C */ diff --git a/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h b/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h index 73a0eee8c..a14c58e6e 100644 --- a/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h +++ b/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h @@ -50,6 +50,13 @@ extern "C" { #endif +/***************************************************************************//** + * @brief Initialise Silabs internal protocol crypto library + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_protocol_crypto_init(void); + /***************************************************************************//** * @brief AES-CTR block encryption/decryption optimized for radio * diff --git a/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c b/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c index deb542c02..7fab1a2bf 100644 --- a/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c +++ b/simplicity_sdk/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c @@ -33,11 +33,11 @@ /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN #include "sli_radioaes_management.h" -#include "sli_se_manager_osal.h" +#include "sli_psec_osal.h" #include "em_core.h" -#if defined(SL_SE_MANAGER_THREADING) -static se_manager_osal_mutex_t radioaes_lock = { 0 }; +#if defined(SLI_PSEC_THREADING) +static sli_psec_osal_lock_t radioaes_lock = { 0 }; static volatile bool radioaes_lock_initialized = false; #endif @@ -82,6 +82,46 @@ static void sli_radioaes_update_mask(void) } #endif // SLI_RADIOAES_REQUIRES_MASKING +// Initialize the RADIOAES lock (mutex) for mutual exclusive access +sl_status_t sli_protocol_crypto_init(void) +{ + sl_status_t sl_status = SL_STATUS_OK; + +#if defined(SLI_PSEC_THREADING) + // Check flag first before going into a critical section, to avoid going into + // a critical section on every single acquire() call. Since the _initialized + // flag only transitions false -> true, we can in 99% of the calls avoid the + // critical section. + if (!radioaes_lock_initialized) { + int32_t kernel_lock_state = 0; + osKernelState_t kernel_state = sli_psec_osal_kernel_get_state(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + kernel_lock_state = sli_psec_osal_kernel_lock(); + if (kernel_lock_state < 0) { + return SL_STATUS_SUSPENDED; + } + } + + // Check the flag again after entering the critical section. Now that we're + // in the critical section, we can be sure that we are the only ones looking + // at the flag and no-one is interrupting us during its manipulation. + if (!radioaes_lock_initialized) { + sl_status = sli_psec_osal_init_lock(&radioaes_lock); + if (sl_status == SL_STATUS_OK) { + radioaes_lock_initialized = true; + } + } + + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + if (sli_psec_osal_kernel_restore_lock(kernel_lock_state) < 0) { + return SL_STATUS_INVALID_STATE; + } + } + } +#endif + return sl_status; +} + sl_status_t sli_radioaes_acquire(void) { #if defined(_CMU_CLKEN0_MASK) @@ -101,53 +141,19 @@ sl_status_t sli_radioaes_acquire(void) #endif return SL_STATUS_ISR; } else { -#if defined(SL_SE_MANAGER_THREADING) +#if defined(SLI_PSEC_THREADING) sl_status_t ret = SL_STATUS_OK; - - // Non-IRQ, RTOS available: take mutex - // Initialize mutex if that hasn't happened yet - - // Check flag first before going into a critical section, to avoid going into - // a critical section on every single acquire() call. Since the _initialized - // flag only transitions false -> true, we can in 99% of the calls avoid the - // critical section. if (!radioaes_lock_initialized) { - int32_t kernel_lock_state = 0; - osKernelState_t kernel_state = se_manager_osal_kernel_get_state(); - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - kernel_lock_state = se_manager_osal_kernel_lock(); - if (kernel_lock_state < 0) { - return SL_STATUS_SUSPENDED; - } - } - - // Check the flag again after entering the critical section. Now that we're - // in the critical section, we can be sure that we are the only ones looking - // at the flag and no-one is interrupting us during its manipulation. - if (!radioaes_lock_initialized) { - ret = se_manager_osal_init_mutex(&radioaes_lock); - if (ret == SL_STATUS_OK) { - radioaes_lock_initialized = true; - } - } - - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - if (se_manager_osal_kernel_restore_lock(kernel_lock_state) < 0) { - return SL_STATUS_INVALID_STATE; - } - } - } - - if (ret == SL_STATUS_OK) { - ret = se_manager_osal_take_mutex(&radioaes_lock); + ret = sli_protocol_crypto_init(); } - - #if defined(SLI_RADIOAES_REQUIRES_MASKING) if (ret == SL_STATUS_OK) { - sli_radioaes_update_mask(); + ret = sli_psec_osal_take_lock(&radioaes_lock); + #if defined(SLI_RADIOAES_REQUIRES_MASKING) + if (ret == SL_STATUS_OK) { + sli_radioaes_update_mask(); + } + #endif } - #endif - return ret; #else // Non-IRQ, no RTOS: busywait @@ -168,9 +174,9 @@ sl_status_t sli_radioaes_release(void) if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { return SL_STATUS_OK; } -#if defined(SL_SE_MANAGER_THREADING) - // Non-IRQ, RTOS available: free mutex - return se_manager_osal_give_mutex(&radioaes_lock); +#if defined(SLI_PSEC_THREADING) + // Non-IRQ, RTOS available: free lock + return sli_psec_osal_give_lock(&radioaes_lock); #else // Non-IRQ, no RTOS: nothing to do. return SL_STATUS_OK; diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/cryptoacc_management.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/cryptoacc_management.h new file mode 100644 index 000000000..d8410a97f --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/cryptoacc_management.h @@ -0,0 +1,99 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs CRYPTOACC device management interface. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef CRYPTOACC_MANAGEMENT_H +#define CRYPTOACC_MANAGEMENT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_crypto_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_cryptoacc_management CRYPTOACC device instance management + * \brief Management functions for the CRYPTOACC. These functions take care + * of not having two 'owners' simultaneously for the same CRYPTOACC + * device, which could potentially be causing conflicts and system + * lock-up. + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +//------------------------------------------------------------------------------ +// Function Declarations + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Get ownership of the crypto device + * + * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error + */ +psa_status_t cryptoacc_management_acquire(void); + +/** + * \brief Release ownership of the crypto device + * + * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error + */ +psa_status_t cryptoacc_management_release(void); + +/** + * \brief Set up hardware SCA countermeasures + * + * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error + * + * \note Will try to set up CM even if errors are returned early on. + * In that case, the function will return the first error code that is + * encountered, but only after CM has been set up. + */ +psa_status_t cryptoacc_initialize_countermeasures(void); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_VSE + +/** \} (end addtogroup sl_cryptoacc_management) */ +/** \} (end addtogroup sl_crypto_plugins) */ + +/// @endcond + +#endif // CRYPTOACC_MANAGEMENT_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_driver_trng.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_driver_trng.h new file mode 100644 index 000000000..b2c47849b --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_driver_trng.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * @file + * @brief Silicon Labs PSA Crypto TRNG driver functions for VSE devices. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_CRYPTOACC_DRIVER_TRNG_H_ +#define SLI_CRYPTOACC_DRIVER_TRNG_H_ + +#include "psa/crypto.h" + +#include "stddef.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//------------------------------------------------------------------------------ +// Global Variable Declarations + +/* + * \brief + * Global struct to be used by functions in the LibCryptoSoC library when + * generating randomness. + * + * \note + * The function pointed to by tis struct expects to the CRYPTOACC peripheral + * to be clocked before being called. + * + * \attention + * The use of this wrapper struct should __not__ be replaced by a naive struct + * containing a pointer to sx_trng_fill_blk(). + * + * \warning + * Since the function pointed to by this wrapper is not able (or expected) to + * return an error code, any errors are therefore handled by resetting the + * system. This is deemed appropriate since a failed randomness generation may + * have severe security implications. + */ +extern const struct sx_rng sli_cryptoacc_trng_wrapper; + +//------------------------------------------------------------------------------ +// Function Declarations + +/* + * \brief + * Function for getting random data from the TRNG. + * + * \note + * This function will make attempted reads until the requested amount of + * randomness has been collected. If the function returns successfully, it + * can be assumed that the full length of requested data has been written. + * + * \return + * PSA_SUCCESS if no error was encountered, else PSA_ERROR_HARDWARE_FAILURE. + */ +psa_status_t sli_cryptoacc_trng_get_random(unsigned char *output, size_t len); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_CRYPTOACC_DRIVER_TRNG_H_ diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_opaque_functions.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_opaque_functions.h new file mode 100644 index 000000000..6d2101e6b --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_opaque_functions.h @@ -0,0 +1,102 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver functions for CRYPTOACC. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_CRYPTOACC_OPAQUE_FUNCTIONS_H +#define SLI_CRYPTOACC_OPAQUE_FUNCTIONS_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc CRYPTOACC opaque PSA driver + * \brief Driver plugin for Silicon Labs CRYPTOACC peripheral adhering to the + * PSA opaque accelerator specification. + * \{ + ******************************************************************************/ + +#include "em_device.h" + +#if defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) + +#include "sli_cryptoacc_opaque_types.h" +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. + +#include "psa/crypto_driver_common.h" + +/* NOTE: This header file will be autogenerated by PSA Crypto build system based on + * the definitions in sli_cryptoacc_opaque_driver.json. However, until such a system is + * in place, we rely on manually writing the file */ + +#ifdef __cplusplus +extern "C" { +#endif +psa_status_t sli_cryptoacc_driver_single_shot_pbkdf2(psa_algorithm_t alg, + const psa_key_attributes_t *key_in_attributes, + const uint8_t *key_in_buffer, + size_t key_in_buffer_size, + const uint8_t* salt, + size_t salt_length, + const psa_key_attributes_t *key_out_attributes, + uint32_t iterations, + uint8_t *key_out_buffer, + size_t key_out_buffer_size); + +psa_status_t sli_cryptoacc_opaque_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_cryptoacc_opaque_get_builtin_key(psa_drv_slot_number_t slot_number, + psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_PSA_DRIVER_FEATURE_PUF_KEY + +/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_CRYPTOACC_OPAQUE_FUNCTIONS_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_opaque_types.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_opaque_types.h new file mode 100644 index 000000000..55520aade --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_opaque_types.h @@ -0,0 +1,59 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver API Types for VSE. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_CRYPTOACC_OPAQUE_TYPES_H +#define SLI_CRYPTOACC_OPAQUE_TYPES_H + +#include "em_device.h" + +#define PSA_KEY_LOCATION_SLI_CRYPTOACC_OPAQUE PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE + +#if defined(CRYPTOACC_PRESENT) && defined(SEPUF_PRESENT) + +#include "sli_psa_driver_features.h" +#include "sl_psa_values.h" + +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + +/// Context struct for opaque registered keys +typedef struct { + /// Version field for the struct + uint8_t struct_version; + /// Builtin key ID + uint8_t builtin_key_id; + /// Reserved space (initialise to all-zero) + uint8_t reserved[2]; +} sli_cryptoacc_opaque_key_context_t; + +#endif // MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + +#endif // CRYPTOACC_PRESENT && SEPUF_PRESENT + +#endif // SLI_CRYPTOACC_OPAQUE_TYPES_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_functions.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_functions.h new file mode 100644 index 000000000..73881564d --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_functions.h @@ -0,0 +1,350 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver functions for CRYPTOACC. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H +#define SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc CRYPTOACC transparent PSA driver + * \brief Driver plugin for Silicon Labs CRYPTOACC peripheral adhering to the + * PSA transparent accelerator specification. + * \{ + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +/* NOTE: This header file will be autogenerated by PSA Crypto build system based on + * the definitions in sli_cryptoacc_transparent_driver.json. However, until such a system is + * in place, we rely on manually writing the file */ + +#ifdef __cplusplus +extern "C" { +#endif + +psa_status_t sli_cryptoacc_transparent_driver_init(void); + +psa_status_t sli_cryptoacc_transparent_driver_deinit(void); + +psa_status_t sli_cryptoacc_transparent_hash_setup(sli_cryptoacc_transparent_hash_operation_t *operation, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_hash_update(sli_cryptoacc_transparent_hash_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_cryptoacc_transparent_hash_finish(sli_cryptoacc_transparent_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +psa_status_t sli_cryptoacc_transparent_hash_abort(sli_cryptoacc_transparent_hash_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_hash_compute(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +psa_status_t sli_cryptoacc_transparent_hash_clone(const sli_cryptoacc_transparent_hash_operation_t *source_operation, + sli_cryptoacc_transparent_hash_operation_t *target_operation); + +psa_status_t sli_cryptoacc_transparent_cipher_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_encrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_cipher_decrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_cipher_set_iv(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length); + +psa_status_t sli_cryptoacc_transparent_cipher_update(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_finish(sli_cryptoacc_transparent_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_abort(sli_cryptoacc_transparent_cipher_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_sign_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +psa_status_t sli_cryptoacc_transparent_verify_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length); + +psa_status_t sli_cryptoacc_transparent_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_cryptoacc_transparent_mac_sign_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_mac_verify_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_mac_update(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_cryptoacc_transparent_mac_sign_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_cryptoacc_transparent_mac_verify_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length); + +psa_status_t sli_cryptoacc_transparent_mac_abort(sli_cryptoacc_transparent_mac_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length); + +psa_status_t sli_cryptoacc_transparent_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + const uint8_t* tag, + size_t tag_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_aead_set_nonce(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length); + +psa_status_t sli_cryptoacc_transparent_aead_set_lengths(sli_cryptoacc_transparent_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length); + +psa_status_t sli_cryptoacc_transparent_aead_update_ad(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_cryptoacc_transparent_aead_verify(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length); + +psa_status_t sli_cryptoacc_transparent_aead_abort(sli_cryptoacc_transparent_aead_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_generate_key(const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_length); + +psa_status_t sli_cryptoacc_transparent_export_public_key(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length); + +psa_status_t sli_cryptoacc_transparent_import_key(const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits); + +psa_status_t sli_cryptoacc_transparent_key_agreement(psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#ifdef __cplusplus +} +#endif + +#endif // CRYPTOACC_PRESENT + +/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_types.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_types.h new file mode 100644 index 000000000..6ddf0bd4b --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_types.h @@ -0,0 +1,136 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver API Types for CRYPTOACC. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_CRYPTOACC_TRANSPARENT_TYPES_H +#define SLI_CRYPTOACC_TRANSPARENT_TYPES_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc + * \{ + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sx_hash.h" +#include "sx_aes.h" +#include "sl_enum.h" +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +SL_ENUM(sli_aes_mode_t) { + SLI_AES_ENC = 1, + SLI_AES_DEC = 2, +}; + +typedef struct { + sx_hash_fct_t hash_type; ///< Hash type + uint32_t total; ///< Number of bytes processed + uint8_t state[32]; ///< Intermediate digest state + uint8_t buffer[64]; ///< Data block being processed +} sli_cryptoacc_transparent_hash_operation_t; + +typedef struct { + sli_aes_mode_t direction; ///< Cipher direction (encrypt/decrypt) + psa_algorithm_t alg; ///< Algorithm (cipher and mode of operation) + uint8_t key[32]; ///< Key buffer + size_t key_len; ///< Length of key in bytes + uint8_t iv[16]; ///< IV buffer + size_t iv_len; ///< Length of IV in bytes + uint8_t streaming_block[16]; ///< Buffer for intermediate results + size_t processed_length; ///< Number of bytes processed +} sli_cryptoacc_transparent_cipher_operation_t; + +typedef union { + struct { + psa_algorithm_t alg; ///< MAC type + uint8_t key[32]; ///< key buffer + size_t key_len; ///< key length + uint8_t current_block[16]; ///< current and potentially last block + size_t current_block_len; ///< current number of bytes in current block + uint8_t cmac_ctx[BLK_CIPHER_CTX_SIZE]; ///< CMAC state context + } cipher_mac; + #if defined(PSA_WANT_ALG_HMAC) + struct { + psa_algorithm_t alg; ///< HMAC type + sli_cryptoacc_transparent_hash_operation_t hash_ctx; ///< Hash context for multipart HMAC + uint8_t opad[64]; ///< opad for use during finalisation + } hmac; + #endif +} sli_cryptoacc_transparent_mac_operation_t; + +typedef struct { + uint8_t nonce_length; ///< Nonce length + uint8_t nonce[16]; ///< Nonce buffer +} sli_cryptoacc_transparent_aead_preinit_t; + +typedef struct { + sli_aes_mode_t direction; ///< xCM mode + psa_algorithm_t alg; ///< Algorithm + uint8_t key[32]; ///< Key buffer + size_t key_len; ///< Key length + size_t ad_len; ///< Length of additional data + size_t processed_len; ///< Current encrypted/decrypted message length + #if defined(PSA_WANT_ALG_CCM) + size_t total_length; ///< Total message length (only used for ccm) + #endif + uint8_t final_data[16]; ///< Input data saved for finish operation + uint8_t final_data_length; ///< Length of data saved + union { + sli_cryptoacc_transparent_aead_preinit_t preinit; ///< Values needed for initiating a multipart process + uint8_t xcm_ctx[BLK_CIPHER_CTX_xCM_SIZE]; ///< xCM state context + uint8_t tag_buf[16]; ///< Tag (only need for CCM when total message length is zero) + } ctx; +} sli_cryptoacc_transparent_aead_operation_t; + +#ifdef __cplusplus +} +#endif + +#endif // CRYPTOACC_PRESENT + +/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_CRYPTOACC_TRANSPARENT_TYPES_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h new file mode 100644 index 000000000..75c73bf18 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h @@ -0,0 +1,230 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto common driver functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_DRIVER_COMMON_H +#define SLI_PSA_DRIVER_COMMON_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "psa/crypto.h" + +#include + +// ----------------------------------------------------------------------------- +// Static inline functions + +/******************************************************************************* + * @brief + * Validate that a elliptic curve (in Weierstrass form) private key is valid. + * This fuction attempts to operate in constant time. + * + * @param[in] privkey + * A buffer containing the private key. + * + * @param padding_bytes + * A buffer containing the modulus (n) to compare the private key against. + * + * @return + * PSA_SUCCESS if the key is in [1, n-1], PSA_ERROR_INVALID_ARGUMENT otherwise. + ******************************************************************************/ +static inline psa_status_t sli_psa_validate_ecc_weierstrass_privkey( + const void *privkey, + const void *modulus, + size_t privkey_size) +{ + // Compare private key to maximum allowed value, n - 1, + // and also check that it is non-zero. + + // Initial values. + uint8_t non_zero_accumulator = 0; + int32_t memcmp_res = 0; + int32_t diff = 0; + + // Loop over every byte in the private key. We start from the end so that + // the final result we store reflects the first byte which differs between the + // two numbers (privkey and modulus). + for (size_t i = 0; i < privkey_size; ++i) { + // Partial non-zero check operation. + non_zero_accumulator |= ((uint8_t *)privkey)[privkey_size - 1 - i]; + + // Compute the difference between the current bytes being compared. + diff = ((uint8_t *)privkey)[privkey_size - 1 - i] + - ((uint8_t *)modulus)[privkey_size - 1 - i]; + + // This will only update memcmp_res if the difference is non-zero. + memcmp_res = (memcmp_res & - !diff) | diff; + } + + if ((non_zero_accumulator == 0) || (memcmp_res >= 0)) { + // We have either failed because the private key turned out to be empty, + // or because the result of the memcmp indicated that the privkey was not + // smaller than the modulus. + return PSA_ERROR_INVALID_ARGUMENT; + } else { + return PSA_SUCCESS; + } +} + +/***************************************************************************//** + * @brief + * Clear a memory location in a way that is guaranteed not be optimized away + * by the compiler. + * + * @param[in] v + * Pointer to memory location. + * + * @param[in] n + * Number of bytes to clear. + ******************************************************************************/ +static inline psa_status_t sli_psa_zeroize(void *v, size_t n) +{ + if (n == 0) { + return PSA_SUCCESS; + } + + volatile unsigned char *p = v; + while (n--) { + *p++ = 0; + } + return PSA_SUCCESS; +} + +/***************************************************************************//** + * @brief + * Perform a memcmp() in 'constant time'. + * + * @param[in] a + * Pointer to the first memory location. + * + * @param[in] a + * Pointer to the second memory location. + * + * @param[in] n + * Number of bytes to compare between the two memory locations. + * + * @return + * Zero if the buffer contents are equal, non-zero otherwise. + ******************************************************************************/ +static inline uint8_t sli_psa_safer_memcmp(const uint8_t *a, + const uint8_t *b, + size_t n) +{ + uint8_t diff = 0u; + + for (size_t i = 0; i < n; i++) { + diff |= a[i] ^ b[i]; + } + + return diff; +} + +// ----------------------------------------------------------------------------- +// Function declarations + +/******************************************************************************* + * @brief + * Validate the PKCS#7 padding contained in the final block of plaintext + * in certain block cipher modes of operation. Based on the get_pkcs_padding() + * implementation in Mbed TLS. + * + * @param[in] padded_data + * A buffer of (at least) size 16 containing the padded final block. + * + * @param padded_data_length + * The length of the paddad data (should be 16). Parameter is mainly kept used + * in order to make it harder for the compiler to optimize out some of the + * "time-constantness". + * + * @param[out] padding_bytes + * The amount of padding bytes that the data contains. + + * + * @return + * PSA_SUCCESS if the padding is valid, PSA_ERROR_INVALID_PADDING otherwise. + ******************************************************************************/ +psa_status_t sli_psa_validate_pkcs7_padding(uint8_t *padded_data, + size_t padded_data_length, + size_t *padding_bytes); + +/** + * \brief Initialize Galois field (2^128) multiplication table + * + * This function is used as part of a software-based GHASH (as defined in + * AES-GCM) algorithm, and originates from the mbed TLS implementation in gcm.c + * + * It takes the in the 'H' value for the GHASH operation (which is a block of + * zeroes encrypted using AES-ECB with the key to be used for GHASH/GCM), and + * converts it into a multiplication table for later use by the multiplication + * function. + * + * \param[in] Ek 'H' value for which to create the multiplication tables + * \param[out] HL Lower multiplication table for 'H' + * \param[out] HH Upper multiplication table for 'H' + */ +void sli_psa_software_ghash_setup(const uint8_t Ek[16], + uint64_t HL[16], + uint64_t HH[16]); + +/** + * \brief Galois field (2^128) multiplication operation + * + * This function is used as part of a software-based GHASH (as defined in + * AES-GCM) algorithm, and originates from the mbed TLS implementation in gcm.c + * + * This function takes in a 128-bit scalar and multiplies it with H (Galois + * field multiplication as defined in AES-GCM). H is not provided to this + * function directly. Instead, multiplication tables for the specific H need to + * be calculated first by \ref sli_psa_software_ghash_setup, and passed to this + * function. + * + * \param[in] HL Lower multiplication table for 'H' + * \param[in] HH Upper multiplication table for 'H' + * \param[out] output Output buffer for the multiplication result + * \param[in] input Input buffer for the scalar to multiply + */ +void sli_psa_software_ghash_multiply(const uint64_t HL[16], + const uint64_t HH[16], + uint8_t output[16], + const uint8_t input[16]); + +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) \ + && !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + +// Declare the TRNG function prototype if it's not already declared by PSA +psa_status_t mbedtls_psa_external_get_random(void *context, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#endif // MBEDTLS_ENTROPY_HARDWARE_ALT && MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +/// @endcond + +#endif // SLI_PSA_DRIVER_COMMON_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_features.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_features.h new file mode 100644 index 000000000..3c8ae15c6 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_features.h @@ -0,0 +1,393 @@ +/***************************************************************************//** + * @file + * @brief PSA Crypto driver feature enablement. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_DRIVER_FEATURES_H +#define SLI_PSA_DRIVER_FEATURES_H + +#include "mbedtls/build_info.h" + +// ----------------------------------------------------------------------------- +// Feature inclusion (available AND requested) + +// ------------------------------------- +// Keys + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + #define SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS +#endif + +#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SEPUF_PRESENT) + #define SLI_PSA_DRIVER_FEATURE_PUF_KEY +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) \ + && (defined(SLI_MBEDTLS_DEVICE_HSE) || defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY)) + #define SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + #define SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS +#endif + +// ------------------------------------- +// TRNG + +#if defined(SLI_MBEDTLS_DEVICE_HSE) \ + || defined(SLI_MBEDTLS_DEVICE_VSE) \ + || defined(SLI_MBEDTLS_DEVICE_S1_WITH_TRNG) \ + || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define SLI_PSA_DRIVER_FEATURE_TRNG +#endif + +#if defined(SLI_MBEDTLS_DEVICE_S1_WITH_TRNG_ERRATA) + #define SLI_PSA_DRIVER_FEATURE_TRNG_ERRATA_HANDLING +#endif + +// ------------------------------------- +// Attestation + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) && !defined(_SILICON_LABS_32B_SERIES_3_CONFIG_301) + #define SLI_PSA_DRIVER_FEATURE_ATTESTATION +#endif + +// ------------------------------------- +// AEAD + +#if defined(PSA_WANT_ALG_CCM) && defined(MBEDTLS_PSA_ACCEL_ALG_CCM) + #define SLI_PSA_DRIVER_FEATURE_AEAD + #define SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_CCM +#endif + +#if defined(PSA_WANT_ALG_GCM) && defined(MBEDTLS_PSA_ACCEL_ALG_GCM) + #define SLI_PSA_DRIVER_FEATURE_AEAD + #define SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_GCM + +// TODO: add public config option. + #if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) +// Can use software implementation in order to compute IVs. + #define SLI_PSA_DRIVER_FEATURE_GCM_IV_CALCULATION + #endif +#endif + +#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) && defined(MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305) + #define SLI_PSA_DRIVER_FEATURE_AEAD + #define SLI_PSA_DRIVER_FEATURE_CHACHAPOLY +#endif + +// ------------------------------------- +// Cipher + +#if defined(PSA_WANT_KEY_TYPE_AES) && defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_AES) + + #define SLI_PSA_DRIVER_FEATURE_AES + + #if defined(PSA_WANT_ALG_ECB_NO_PADDING) && defined(MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_ECB + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CTR) && defined(MBEDTLS_PSA_ACCEL_ALG_CTR) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CTR + #define SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CFB) && defined(MBEDTLS_PSA_ACCEL_ALG_CFB) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CFB + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_OFB) && defined(MBEDTLS_PSA_ACCEL_ALG_OFB) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_OFB + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CCM) && defined(MBEDTLS_PSA_ACCEL_ALG_CCM) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG + #define SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CBC_NO_PADDING) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_NO_PADDING + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CBC_PKCS7) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7 + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + +#endif + +#if defined(PSA_WANT_KEY_TYPE_CHACHA20) && defined(PSA_WANT_ALG_STREAM_CIPHER) \ + && defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_STREAM_CIPHER + #define SLI_PSA_DRIVER_FEATURE_CHACHA20 + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +#endif + +// ------------------------------------- +// Key derivation + +#if defined(PSA_WANT_ALG_HKDF) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_HKDF +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_HMAC) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_PBKDF2 + #define SLI_PSA_DRIVER_FEATURE_PBKDF2_HMAC +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) \ + && defined(SLI_MBEDTLS_DEVICE_HSE_V2) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_PBKDF2 + #define SLI_PSA_DRIVER_FEATURE_PBKDF2_CMAC +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) && defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_PBKDF2 + #define SLI_PSA_DRIVER_FEATURE_PBKDF2_CMAC +#endif + +// ------------------------------------- +// Hash + +#if defined(PSA_WANT_ALG_SHA_1) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA1 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 +#endif + +#if defined(PSA_WANT_ALG_SHA_224) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA224 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 +#endif + +#if defined(PSA_WANT_ALG_SHA_256) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA256 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 +#endif + +#if defined(PSA_WANT_ALG_SHA_384) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA384 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_64 +#endif + +#if defined(PSA_WANT_ALG_SHA_512) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA512 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_64 +#endif + +// ------------------------------------- +// MAC + +#if defined(PSA_WANT_ALG_HMAC) && defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) + #define SLI_PSA_DRIVER_FEATURE_MAC + #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_HMAC +#endif + +#if defined(PSA_WANT_ALG_CMAC) && defined(MBEDTLS_PSA_ACCEL_ALG_CMAC) + #define SLI_PSA_DRIVER_FEATURE_MAC + #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_CMAC +#endif + +#if defined(PSA_WANT_ALG_CBC_MAC) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_MAC) + #define SLI_PSA_DRIVER_FEATURE_MAC + #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_CBC_MAC +#endif + +// ------------------------------------- +// Elliptic curve cryptography + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_192) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P192R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_224) \ + && !defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P224R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_256) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P256R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_384) \ + && defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P384R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_521) \ + && defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P521R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_K1_256) \ + && defined(SLI_MBEDTLS_DEVICE_VSE) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPK1 + #define SLI_PSA_DRIVER_FEATURE_P256K1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_MONTGOMERY_255) \ + && defined(SLI_MBEDTLS_DEVICE_HSE) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_MONTGOMERY + #define SLI_PSA_DRIVER_FEATURE_CURVE25519 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_MONTGOMERY_448) \ + && defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_MONTGOMERY + #define SLI_PSA_DRIVER_FEATURE_CURVE448 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_TWISTED_EDWARDS_255) \ + && defined(SLI_MBEDTLS_DEVICE_HSE) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_EDWARDS + #define SLI_PSA_DRIVER_FEATURE_EDWARDS25519 +#endif + +// ------------------------------------- +// Key agreement + +#if defined(PSA_WANT_ALG_ECDH) && defined(MBEDTLS_PSA_ACCEL_ALG_ECDH) \ + && defined(SLI_PSA_DRIVER_FEATURE_ECC) + #define SLI_PSA_DRIVER_FEATURE_KEY_AGREEMENT + #define SLI_PSA_DRIVER_FEATURE_ECDH +#endif + +// ------------------------------------- +// Signature + +#if defined(PSA_WANT_ALG_ECDSA) && defined(MBEDTLS_PSA_ACCEL_ALG_ECDSA) \ + && (defined(SLI_PSA_DRIVER_FEATURE_SECPR1) \ + || defined(SLI_PSA_DRIVER_FEATURE_SECPK1)) + #define SLI_PSA_DRIVER_FEATURE_SIGNATURE + #define SLI_PSA_DRIVER_FEATURE_ECDSA +#endif + +#if defined(PSA_WANT_ALG_EDDSA) && defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) + #define SLI_PSA_DRIVER_FEATURE_SIGNATURE + #define SLI_PSA_DRIVER_FEATURE_EDDSA +#endif + +#endif // SLI_PSA_DRIVER_FEATURES_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_aead.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_aead.h new file mode 100644 index 000000000..3c491771f --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_aead.h @@ -0,0 +1,204 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Secure Engine Driver AEAD functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_DRIVER_AEAD_H +#define SLI_SE_DRIVER_AEAD_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +// ----------------------------------------------------------------------------- +// Types + +typedef struct { + sl_se_cipher_operation_t direction; + size_t ad_length; + size_t pt_length; + uint8_t nonce[16]; + size_t nonce_length; +} sli_se_driver_aead_preinit_t; + +typedef struct { + psa_algorithm_t alg; + sl_se_key_descriptor_t key_desc; + size_t ad_len; + size_t pt_len; + union { + sl_se_gcm_multipart_context_t gcm; + sl_se_ccm_multipart_context_t ccm; + sli_se_driver_aead_preinit_t preinit; + } ctx; +} sli_se_driver_aead_operation_t; + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +psa_status_t sli_se_driver_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length); + +psa_status_t sli_se_driver_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_se_driver_aead_encrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_se_driver_aead_decrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + const uint8_t* tag, + size_t tag_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_se_driver_aead_encrypt_decrypt_setup(sli_se_driver_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + sl_se_cipher_operation_t operation_direction, + uint8_t *key_storage_buffer, + size_t key_storage_buffer_size, + size_t key_storage_overhead); + +psa_status_t sli_se_driver_aead_set_nonce(sli_se_driver_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_size); + +psa_status_t sli_se_driver_aead_set_lengths(sli_se_driver_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length); + +psa_status_t sli_se_driver_aead_update_ad(sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_se_driver_aead_update(sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_driver_aead_finish(sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_se_driver_aead_verify(sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_DRIVER_AEAD_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_cipher.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_cipher.h new file mode 100644 index 000000000..fa5e8db6e --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_cipher.h @@ -0,0 +1,135 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Secure Engine Driver cipher functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_DRIVER_CIPHER_H +#define SLI_SE_DRIVER_CIPHER_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sl_se_manager_types.h" + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +// ----------------------------------------------------------------------------- +// Types + +typedef struct { + sl_se_key_descriptor_t key_desc; + sl_se_cipher_operation_t direction; + psa_algorithm_t alg; + uint8_t iv[16]; + size_t iv_len; + uint8_t streaming_block[16]; + size_t processed_length; +} sli_se_driver_cipher_operation_t; + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +psa_status_t sli_se_driver_cipher_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_driver_cipher_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_driver_cipher_encrypt_setup(sli_se_driver_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + psa_algorithm_t alg); + +psa_status_t sli_se_driver_cipher_decrypt_setup(sli_se_driver_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + psa_algorithm_t alg); + +psa_status_t sli_se_driver_cipher_set_iv(sli_se_driver_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length); + +psa_status_t sli_se_driver_cipher_update(sli_se_driver_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_driver_cipher_finish(sli_se_driver_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_driver_cipher_abort(sli_se_driver_cipher_operation_t *operation); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_DRIVER_CIPHER_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_key_derivation.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_key_derivation.h new file mode 100644 index 000000000..12f39de93 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_key_derivation.h @@ -0,0 +1,105 @@ +/***************************************************************************//** + * @file + * @brief SE Driver for Silicon Labs devices with an embedded SE, for use with + * PSA Crypto and Mbed TLS + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_DRIVER_KEY_DERIVATION +#define SLI_SE_DRIVER_KEY_DERIVATION + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sl_se_manager.h" +#include "sl_se_manager_defines.h" + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" +#include "psa/crypto_platform.h" + +// ----------------------------------------------------------------------------- +// Structs and typedefs + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_SE_MAX_ECP_PRIVATE_KEY_SIZE (PSA_BITS_TO_BYTES(521)) +#else + #define SLI_SE_MAX_ECP_PRIVATE_KEY_SIZE (PSA_BITS_TO_BYTES(256)) +#endif + +#define SLI_SE_MAX_ECP_PUBLIC_KEY_SIZE (SLI_SE_MAX_ECP_PRIVATE_KEY_SIZE * 2) + +#define SLI_SE_MAX_PADDED_ECP_PRIVATE_KEY_SIZE \ + (SLI_SE_MAX_ECP_PRIVATE_KEY_SIZE \ + + sli_se_get_padding(SLI_SE_MAX_ECP_PRIVATE_KEY_SIZE)) +#define SLI_SE_MAX_PADDED_ECP_PUBLIC_KEY_SIZE \ + (SLI_SE_MAX_PADDED_ECP_PRIVATE_KEY_SIZE * 2) + +// ----------------------------------------------------------------------------- +// Function declarations + +#ifdef __cplusplus +extern "C" { +#endif + +psa_status_t sli_se_driver_key_agreement( + psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_DRIVER_KEY_DERIVATION diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_key_management.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_key_management.h new file mode 100644 index 000000000..398d8acd9 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_key_management.h @@ -0,0 +1,351 @@ +/***************************************************************************//** + * @file + * @brief SE Driver for Silicon Labs devices with an embedded SE, for use with + * PSA Crypto and Mbed TLS + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_DRIVER_KEY_MANAGEMENT_H +#define SLI_SE_DRIVER_KEY_MANAGEMENT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sli_se_opaque_types.h" +#include "sli_se_version_dependencies.h" + +#include "sl_se_manager.h" + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +#include + +// ----------------------------------------------------------------------------- +// Defines and macros + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) +/// Max available curve size + #define SLI_SE_MAX_CURVE_SIZE (521) +#else +/// Max available curve size + #define SLI_SE_MAX_CURVE_SIZE (256) +#endif + +/// Byte size of maximum available ECC private key padded to word-alignment +#define SLI_SE_MAX_PADDED_KEY_PAIR_SIZE \ + (PSA_BITS_TO_BYTES(SLI_SE_MAX_CURVE_SIZE) \ + + sli_se_get_padding(PSA_BITS_TO_BYTES(SLI_SE_MAX_CURVE_SIZE))) + +/// Byte size of maximum available ECDSA signature padded to word-alignment +#define SLI_SE_MAX_PADDED_SIGNATURE_SIZE \ + (PSA_ECDSA_SIGNATURE_SIZE(SLI_SE_MAX_CURVE_SIZE) \ + + 2 * sli_se_get_padding(PSA_BITS_TO_BYTES(SLI_SE_MAX_CURVE_SIZE))) + +/// Byte size of maximum available ECC public key padded to word-alignment +#define SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE (SLI_SE_MAX_PADDED_SIGNATURE_SIZE) + +/** Determine the number of bytes necessary to pad size to a word-alignment + * @param size + * Unsigend integer type. + * @returns the number of padding bytes required + */ +#define sli_se_get_padding(size) ((4 - (size & 3)) & 3) + +/** Pad size to word alignment + * @param size + * Unsigend integer type. + * @returns the number of padding bytes required + */ +#define sli_se_word_align(size) ((size + 3) & ~3) + +// ----------------------------------------------------------------------------- +// Static inline functions + +/** + * @brief + * Pad the big endian number in buffer with zeros + * @param tmp_buffer + * A buffer to store the padded number + * @param buffer + * The buffer containing the number + * @param buffer_size + * Byte size of the number to pad + * @note + * Buffer sizes must be pre-validated. + */ +static inline void sli_se_pad_big_endian(uint8_t *tmp_buffer, + const uint8_t *buffer, + size_t buffer_size) +{ + size_t padding = sli_se_get_padding(buffer_size); + memset(tmp_buffer, 0, padding); // Set the preceeding 0s + memcpy(tmp_buffer + padding, buffer, buffer_size); // Copy actual content +} + +/** + * @brief + * Remove the padding from a zero-padded big endian number + * @param tmp_buffer + * Buffer containing the padded number + * @param buffer + * The buffer to write unpadded number to + * @param buffer_size + * Byte size of unpadded number + * @note + * Buffer sizes must be pre-validated. + */ +static inline void sli_se_unpad_big_endian(const uint8_t *tmp_buffer, + uint8_t *buffer, + size_t buffer_size) +{ + size_t padding = sli_se_get_padding(buffer_size); + memcpy(buffer, tmp_buffer + padding, buffer_size); +} + +/** + * @brief + * Pad each coordinate of a big endian curve point + * @param tmp_buffer + * A buffer to store the padded point + * @param buffer + * The buffer containing the point + * @param coord_size + * Byte size of each coordinate + * @note + * Buffer sizes must be pre-validated. + */ +static inline void sli_se_pad_curve_point(uint8_t *tmp_buffer, + const uint8_t *buffer, + size_t coord_size) +{ + size_t padding = sli_se_get_padding(coord_size); + sli_se_pad_big_endian(tmp_buffer, buffer, coord_size); + sli_se_pad_big_endian(tmp_buffer + coord_size + padding, + buffer + coord_size, + coord_size); +} + +/** + * @brief + * Strip away the padding from each coordinate of a big endian curve point + * @param tmp_buffer + * The buffer where the padded point is stored + * @param buffer + * A buffer to store the unpadded point + * @param coord_size + * Byte size of each coordinate + * @note + * Buffer sizes must be pre-validated. + */ +static inline void sli_se_unpad_curve_point(const uint8_t *tmp_buffer, + uint8_t *buffer, + size_t coord_size) +{ + size_t padding = sli_se_get_padding(coord_size); + sli_se_unpad_big_endian(tmp_buffer, buffer, coord_size); + sli_se_unpad_big_endian(tmp_buffer + coord_size + padding, + buffer + coord_size, + coord_size); +} + +/** + * @brief + * Set the key desc to a plaintext key type pointing to data. + * @param[out] key_desc + * The SE manager key struct representing a key + * @param[in] data + * Buffer containing the key + * @param[in] data_length + * Length of the buffer + */ +static inline +void sli_se_key_descriptor_set_plaintext(sl_se_key_descriptor_t *key_desc, + const uint8_t *data, + size_t data_length) +{ + key_desc->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT; + key_desc->storage.location.buffer.pointer = (uint8_t *)data; + // TODO: Improve SE manager alignment requirements + key_desc->storage.location.buffer.size = sli_se_word_align(data_length); +} + +/** + * @brief + * Determine if a format byte is necessary for the key type + * @param key_type + * PSA key type for the key in question + * @returns + * 1 if the key type requires a format byte, + * 0 otherwise + */ +static inline uint32_t sli_se_has_format_byte(psa_key_type_t key_type) +{ + if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { + if ((PSA_KEY_TYPE_ECC_GET_FAMILY(key_type) != PSA_ECC_FAMILY_MONTGOMERY) + && (PSA_KEY_TYPE_ECC_GET_FAMILY(key_type) != PSA_ECC_FAMILY_TWISTED_EDWARDS)) { + return 1U; + } + } + return 0U; +} + +// ----------------------------------------------------------------------------- +// Function declarations + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief + * Store the required parts of the key descriptor in the context placed the + * start of the given key buffer. + * + * @param key_desc[in] + * Key descriptor to export. + * @param key_buffer[out] + * Pointer to the key buffer containing key context. + * @param key_buffer_size[in] + * Size of key buffer. + * @returns + * PSA_SUCCESS stored key desc in context + * PSA_ERROR_BUFFER_TOO_SMALL output buffer is too small to hold an opaque key context + */ +psa_status_t store_key_desc_in_context(sl_se_key_descriptor_t *key_desc, + uint8_t *key_buffer, + size_t key_buffer_size); + +/** + * @brief + * Get the key descriptor from the key buffer and attributes + * + * @param[in] attributes + * The PSA attributes struct representing a key + * @param[in] key_buffer + * Buffer containing key context from PSA core + * @param[in] key_buffer_size + * Size of key_buffer + * @param[out] key_desc + * The SE manager key descriptor struct to populate + * @returns + * PSA_SUCCESS if everything is OK + * PSA_ERROR_INVALID_ARGUMENT if key buffer does not mach a valid key context + * @note + * The resulting key descriptor is only valid as long as the key_buffer + * array remains in scope. In practice, this is only guaranteed throughout a + * single driver function. + */ +psa_status_t sli_se_key_desc_from_input(const psa_key_attributes_t* attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + sl_se_key_descriptor_t *key_desc); + +/** + * @brief + * Build a key descriptor from a PSA attributest struct + * + * @param attributes + * The PSA attributes struct representing a key + * @param key_size + * Size of the key + * @param key_desc + * The SE manager key struct representing the same key + * @returns + * PSA_SUCCESS on success + * PSA_ERROR_INVALID_ARGUMENT on invalid attributes + */ +psa_status_t sli_se_key_desc_from_psa_attributes(const psa_key_attributes_t *attributes, + size_t key_size, + sl_se_key_descriptor_t *key_desc); + +/** + * @brief + * Set the relevant location field of the key descriptor + * + * @param[in] attributes + * The PSA attributes struct representing a key + * @param[in] key_buffer + * Buffer containing key context from PSA core + * @param[in] key_buffer_size + * Size of key_buffer + * @param[in] key_size + * Size of the key + * @param[out] key_desc + * The SE manager key descriptor struct to populate + * @returns + * PSA_SUCCESS if everything is OK + * PSA_ERROR_INVALID_ARGUMENT if key buffer does not mach a valid key context + */ +psa_status_t sli_se_set_key_desc_output(const psa_key_attributes_t* attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t key_size, + sl_se_key_descriptor_t *key_desc); + +// psa_generate_key entry point for both opaque and transparent drivers +psa_status_t sli_se_driver_generate_key(const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *output_length); + +#if defined(SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN) \ + && defined(MBEDTLS_ECP_C) \ + && defined(MBEDTLS_PSA_CRYPTO_C) \ + && SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 +psa_status_t sli_se_driver_validate_pubkey_with_fallback(psa_key_type_t key_type, + size_t key_bits, + const uint8_t *data, + size_t data_length); +#endif // Software fallback for SE < 1.2.2 + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_DRIVER_KEY_MANAGEMENT_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_mac.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_mac.h new file mode 100644 index 000000000..35f7f8f18 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_driver_mac.h @@ -0,0 +1,127 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Secure Engine Driver MAC functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_DRIVER_MAC_H +#define SLI_SE_DRIVER_MAC_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +#include "sl_se_manager.h" +#include "sl_se_manager_cipher.h" + +// ----------------------------------------------------------------------------- +// Types + +typedef struct { + psa_algorithm_t alg; + union { + sl_se_cmac_multipart_context_t cmac; + struct { + uint8_t iv[16]; + size_t iv_len; + uint8_t streaming_block[16]; + size_t processed_length; + } cbcmac; + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + struct { + #if defined(SLI_PSA_DRIVER_FEATURE_HASH_STATE_64) + uint8_t hmac_result[64]; + #else + uint8_t hmac_result[32]; + #endif // SLI_PSA_DRIVER_FEATURE_HASH_STATE_64 + size_t hmac_len; + } hmac; + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + } ctx; +} sli_se_driver_mac_operation_t; + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +sl_se_hash_type_t sli_se_hash_type_from_psa_hmac_alg(psa_algorithm_t alg, + size_t *length); + +psa_status_t sli_se_driver_mac_compute(sl_se_key_descriptor_t *key_desc, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_se_driver_mac_sign_setup(sli_se_driver_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + psa_algorithm_t alg); + +psa_status_t sli_se_driver_mac_update(sli_se_driver_mac_operation_t *operation, + sl_se_key_descriptor_t *key_desc, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_se_driver_mac_sign_finish(sli_se_driver_mac_operation_t *operation, + sl_se_key_descriptor_t *key_desc, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_DRIVER_MAC_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_opaque_functions.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_opaque_functions.h new file mode 100644 index 000000000..8cd053e88 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_opaque_functions.h @@ -0,0 +1,380 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver functions for SE. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_OPAQUE_FUNCTIONS_H +#define SLI_SE_OPAQUE_FUNCTIONS_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +#include "sli_se_opaque_types.h" +#include "sli_se_driver_key_management.h" + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" + +// NOTE: This header file will be autogenerated by PSA Crypto build system based +// on the definitions in sli_se_opaque_driver.json. However, until such a system +// is in place, we rely on manually writing the file. + +#ifdef __cplusplus +extern "C" { +#endif + +//------------------------------------------------------------------------------ +// General + +psa_status_t sli_se_opaque_driver_init(void); + +psa_status_t sli_se_opaque_driver_deinit(void); + +//------------------------------------------------------------------------------ +// Key handling + +psa_status_t sli_se_opaque_export_key(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length); + +psa_status_t sli_se_opaque_import_key(const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits); + +psa_status_t sli_se_opaque_generate_key(const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length); + +psa_status_t sli_se_opaque_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length); + +psa_status_t sli_se_opaque_get_builtin_key(psa_drv_slot_number_t slot_number, + psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length); + +psa_status_t sli_se_opaque_copy_key(const psa_key_attributes_t *attributes, + const uint8_t *source_key, + size_t source_key_length, + uint8_t *target_key_buffer, + size_t target_key_buffer_size, + size_t *target_key_buffer_length); + +//------------------------------------------------------------------------------ +// MAC + +psa_status_t sli_se_opaque_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_se_opaque_mac_sign_setup( + sli_se_opaque_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_opaque_mac_verify_setup( + sli_se_opaque_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_opaque_mac_update(sli_se_opaque_mac_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_se_opaque_mac_sign_finish( + sli_se_opaque_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_se_opaque_mac_verify_finish( + sli_se_opaque_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length); + +psa_status_t sli_se_opaque_mac_abort(sli_se_opaque_mac_operation_t *operation); + +//------------------------------------------------------------------------------ +// Signature + +psa_status_t sli_se_opaque_sign_message(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +psa_status_t sli_se_opaque_verify_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length); + +psa_status_t sli_se_opaque_sign_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +psa_status_t sli_se_opaque_verify_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length); + +//------------------------------------------------------------------------------ +// AEAD + +psa_status_t sli_se_opaque_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length); + +psa_status_t sli_se_opaque_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_se_opaque_aead_encrypt_setup( + sli_se_opaque_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_opaque_aead_decrypt_setup( + sli_se_opaque_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_opaque_aead_set_nonce( + sli_se_opaque_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_size); + +psa_status_t sli_se_opaque_aead_set_lengths( + sli_se_opaque_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length); + +psa_status_t sli_se_opaque_aead_update_ad( + sli_se_opaque_aead_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_se_opaque_aead_update( + sli_se_opaque_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_opaque_aead_finish( + sli_se_opaque_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_se_opaque_aead_verify( + sli_se_opaque_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length); + +psa_status_t sli_se_opaque_aead_abort( + sli_se_opaque_aead_operation_t *operation); + +//------------------------------------------------------------------------------ +// Cipher + +psa_status_t sli_se_opaque_cipher_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_opaque_cipher_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_opaque_cipher_encrypt_setup( + sli_se_opaque_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_opaque_cipher_decrypt_setup( + sli_se_opaque_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_opaque_cipher_set_iv( + sli_se_opaque_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length); + +psa_status_t sli_se_opaque_cipher_update( + sli_se_opaque_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_opaque_cipher_finish( + sli_se_opaque_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_opaque_cipher_abort( + sli_se_opaque_cipher_operation_t *operation); + +//------------------------------------------------------------------------------ +// Key agreement + +psa_status_t sli_se_opaque_key_agreement(psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_OPAQUE_FUNCTIONS_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_opaque_types.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_opaque_types.h new file mode 100644 index 000000000..b9764dddb --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_opaque_types.h @@ -0,0 +1,160 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver API Internal Types for SE. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_OPAQUE_TYPES_H +#define SLI_SE_OPAQUE_TYPES_H + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sl_se_manager_defines.h" +#include "sl_se_manager_types.h" + +#include "sl_psa_values.h" + +#include "sli_se_driver_aead.h" +#include "sli_se_driver_mac.h" +#include "sli_se_driver_key_derivation.h" +#include "sli_se_driver_cipher.h" + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" +#include "psa/crypto_platform.h" + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se PSA drivers for devices with Secure Engine + * \{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Defines + +/// Location value for keys to be stored encrypted with the device-unique secret, +/// or for accessing the built-in keys on Vault devices. Kept for backward +/// compatibility reasons. Users should use SL_PSA_KEY_LOCATION_WRAPPED or +/// SL_PSA_KEY_LOCATION_BUILTIN instead. +#define PSA_KEY_LOCATION_SLI_SE_OPAQUE ((psa_key_location_t)0x000001UL) + +/// Version of opaque header struct +#define SLI_SE_OPAQUE_KEY_CONTEXT_VERSION (0x01) + +// ----------------------------------------------------------------------------- +// Types + +#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +/// Key header for context struct of opaque registered keys +typedef struct { + /// Version field for the struct + uint8_t struct_version; + /// Builtin key ID. Set to zero for a key header which is part of a \ref + /// sli_se_opaque_wrapped_key_context_t, otherwise set to an SE Manager builtin + /// key ID. + uint8_t builtin_key_id; + /// Reserved space (initialise to all-zero) + uint8_t reserved[2]; +} sli_se_opaque_key_context_header_t; + +/// Key context for wrapped keys +typedef struct { + /// Key context header + sli_se_opaque_key_context_header_t header; + + /// Key information required to construct an SE manager key descriptor + // sl_se_key_descriptor_t key_desc; + uint32_t key_type; + uint32_t key_size; + uint32_t key_flags; + + /// wrapped_buffer is set to a distinctive size to make sizeof() result + /// in the overhead for storing a wrapped key. + /// A wrapped key will in reality consume more space than + /// SLI_SE_WRAPPED_KEY_OVERHEAD + uint8_t wrapped_buffer[SLI_SE_WRAPPED_KEY_OVERHEAD]; + /// Variable member, accounting for the extra space + uint8_t fill[]; +} sli_se_opaque_wrapped_key_context_t; + +// Notes for JSON entry for wrapped driver: +// "base_size": "sizeof(sli_se_opaque_wrapped_key_context_t)", +// "symmetric_factor": 1, +// "key_pair_size": 66, +// "public_key_size" 133 +// Is 66/133 the largest keys we accept? What about custom curves? + +// ---------------------------------- +// Potential format for internal volatile keys +// typedef struct { +// sl_se_key_descriptor_t key_desc; +// } sli_se_opaque_volatile_key_context; + +// Notes for JSON entry for internal volatile driver: +// "base_size": "sizeof(sli_se_opaque_volatile_key_context)", +// For the remaining entries, the defaults are fine. + +typedef struct { + sl_se_key_descriptor_t key_desc; + #if defined(PSA_WANT_ALG_HMAC) + uint8_t key[SLI_SE_WRAPPED_KEY_OVERHEAD + 64]; + #else + uint8_t key[SLI_SE_WRAPPED_KEY_OVERHEAD + 32]; + #endif + size_t key_len; + sli_se_driver_mac_operation_t operation; +} sli_se_opaque_mac_operation_t; + +typedef struct { + uint8_t key[SLI_SE_WRAPPED_KEY_OVERHEAD + 32]; + size_t key_len; + sli_se_driver_aead_operation_t operation; +} sli_se_opaque_aead_operation_t; + +typedef struct { + uint8_t key[SLI_SE_WRAPPED_KEY_OVERHEAD + 32]; + size_t key_len; + sli_se_driver_cipher_operation_t operation; +} sli_se_opaque_cipher_operation_t; + +#endif // SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ +/// @endcond +#endif // SLI_SE_OPAQUE_TYPES_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_transparent_functions.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_transparent_functions.h new file mode 100644 index 000000000..49276ddab --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_transparent_functions.h @@ -0,0 +1,400 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver functions for SE. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_SE_TRANSPARENT_FUNCTIONS_H +#define SLI_SE_TRANSPARENT_FUNCTIONS_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se CRYPTOACC transparent PSA driver + * \brief Driver plugin for Silicon Labs SE peripheral adhering to the PSA + * transparent accelerator specification. + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sli_se_transparent_types.h" + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +/* NOTE: This header file will be autogenerated by PSA Crypto build system based + * on the definitions in sli_se_transparent_driver.json. However, until such a + * system is in place, we rely on manually writing the file */ + +#ifdef __cplusplus +extern "C" { +#endif + +//------------------------------------------------------------------------------ +// General + +psa_status_t sli_se_transparent_driver_init(void); + +psa_status_t sli_se_transparent_driver_deinit(void); + +//------------------------------------------------------------------------------ +// Hashing + +psa_status_t sli_se_transparent_hash_setup( + sli_se_transparent_hash_operation_t *operation, + psa_algorithm_t alg); + +psa_status_t sli_se_transparent_hash_update( + sli_se_transparent_hash_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_se_transparent_hash_finish( + sli_se_transparent_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +psa_status_t sli_se_transparent_hash_abort( + sli_se_transparent_hash_operation_t *operation); + +psa_status_t sli_se_transparent_hash_compute(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +psa_status_t sli_se_transparent_hash_clone( + const sli_se_transparent_hash_operation_t *source_operation, + sli_se_transparent_hash_operation_t *target_operation); + +//------------------------------------------------------------------------------ +// Cipher + +psa_status_t sli_se_transparent_cipher_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_transparent_cipher_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_transparent_cipher_encrypt_setup( + sli_se_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_transparent_cipher_decrypt_setup( + sli_se_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_transparent_cipher_set_iv( + sli_se_transparent_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length); + +psa_status_t sli_se_transparent_cipher_update( + sli_se_transparent_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_transparent_cipher_abort( + sli_se_transparent_cipher_operation_t *operation); + +psa_status_t sli_se_transparent_cipher_finish( + sli_se_transparent_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length); + +//------------------------------------------------------------------------------ +// Signature + +psa_status_t sli_se_transparent_sign_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +psa_status_t sli_se_transparent_verify_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length); + +psa_status_t sli_se_transparent_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +psa_status_t sli_se_transparent_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length); + +//------------------------------------------------------------------------------ +// MAC + +psa_status_t sli_se_transparent_mac_compute( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_se_transparent_mac_sign_setup( + sli_se_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_transparent_mac_verify_setup( + sli_se_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_transparent_mac_update( + sli_se_transparent_mac_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_se_transparent_mac_sign_finish( + sli_se_transparent_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_se_transparent_mac_verify_finish( + sli_se_transparent_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length); + +psa_status_t sli_se_transparent_mac_abort( + sli_se_transparent_mac_operation_t *operation); + +//------------------------------------------------------------------------------ +// AEAD + +psa_status_t sli_se_transparent_aead_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length); + +psa_status_t sli_se_transparent_aead_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_se_transparent_aead_encrypt_setup( + sli_se_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_transparent_aead_decrypt_setup( + sli_se_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_se_transparent_aead_set_nonce( + sli_se_transparent_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length); + +psa_status_t sli_se_transparent_aead_set_lengths( + sli_se_transparent_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length); + +psa_status_t sli_se_transparent_aead_update_ad( + sli_se_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_se_transparent_aead_update( + sli_se_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_se_transparent_aead_finish( + sli_se_transparent_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_se_transparent_aead_verify( + sli_se_transparent_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length); + +psa_status_t sli_se_transparent_aead_abort( + sli_se_transparent_aead_operation_t *operation); + +//------------------------------------------------------------------------------ +// Key handling + +psa_status_t sli_se_transparent_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *output_length); + +psa_status_t sli_se_transparent_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length); + +psa_status_t sli_se_transparent_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits); + +//------------------------------------------------------------------------------ +// Key agreement + +psa_status_t sli_se_transparent_key_agreement( + psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_TRANSPARENT_FUNCTIONS_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_transparent_types.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_transparent_types.h new file mode 100644 index 000000000..c99fa9df4 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_transparent_types.h @@ -0,0 +1,117 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver API Types for SE. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_TRANSPARENT_TYPES_H +#define SLI_SE_TRANSPARENT_TYPES_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sl_se_manager_types.h" + +#include "sli_se_driver_aead.h" +#include "sli_se_driver_mac.h" +#include "sli_se_driver_cipher.h" + +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +// ----------------------------------------------------------------------------- +// Types + +#define PSA_KEY_LOCATION_SLI_SE_TRANSPARENT ((psa_key_location_t)0x000002UL) + +/// PSA transparent accelerator driver compatible context structure +typedef struct { + sl_se_hash_type_t hash_type; ///< Hash type + union { + sl_se_sha1_multipart_context_t sha1_context; + sl_se_sha224_multipart_context_t sha224_context; + sl_se_sha256_multipart_context_t sha256_context; + #if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + sl_se_sha384_multipart_context_t sha384_context; + sl_se_sha512_multipart_context_t sha512_context; + #endif + } streaming_contexts; +} sli_se_transparent_hash_operation_t; + +typedef struct { + uint8_t key[32]; + size_t key_len; + sli_se_driver_cipher_operation_t operation; +} sli_se_transparent_cipher_operation_t; + +typedef union { + struct { + sli_se_driver_mac_operation_t operation; + uint8_t key[32]; + size_t key_len; + } cipher_mac; + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + struct { + psa_algorithm_t alg; + sli_se_transparent_hash_operation_t hash_ctx; + #if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + uint8_t opad[128]; + #else + uint8_t opad[64]; + #endif + } hmac; + #endif /* SLI_PSA_DRIVER_FEATURE_HMAC */ +} sli_se_transparent_mac_operation_t; + +typedef struct { + uint8_t key[32]; + size_t key_len; + sli_se_driver_aead_operation_t operation; +} sli_se_transparent_aead_operation_t; + +#endif // SLI_MBEDTLS_DEVICE_HSE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_SE_TRANSPARENT_TYPES_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h new file mode 100644 index 000000000..355255112 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h @@ -0,0 +1,141 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver SE Version Dependencies. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_VERSION_DEPENDENCIES_H +#define SLI_SE_VERSION_DEPENDENCIES_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #include "psa/crypto.h" + #include "sl_se_manager_types.h" +#endif + +// ----------------------------------------------------------------------------- +// Version Constants + +// HSE specific constants +#if defined(SLI_MBEDTLS_DEVICE_HSE) +// The oldest firmware revision with support for checking the validity +// of public ECC keys. Also see SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 and +// SL_SE_ASSUME_FW_AT_LEAST_1_2_2. + #if !defined(SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION) + #define SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION (0x00010202U) + #endif + +// The SE version that first introduced a regression related to Ed25519. See +// SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA. + #if !defined(SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519) + #define SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519 (0x00010202U) + #endif + +// The final SE version containing a bug causing Ed25519 to be broken. See +// SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA. + #if !defined(SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519) + #define SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519 (0x00010208U) + #endif +#endif // SLI_MBEDTLS_DEVICE_HSE + +// Common HSE/VSE constants + +// The first SE version that supports TrustZone Storage Root Key (SRK) +#if !defined(SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT) + #if defined(SLI_MBEDTLS_DEVICE_SE_V2) + #define SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT (0x00020200) + #else + #define SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT (0x0001020c) + #endif +#endif + +// ----------------------------------------------------------------------------- +// Preprocessor Guard Helper Defines + +// ------------------------------- +// ECDH + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #if !SL_SE_ASSUME_FW_AT_LEAST_1_2_2 && defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN + #endif +#endif // SLI_MBEDTLS_DEVICE_HSE + +// ------------------------------- +// EdDSA + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #if !SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA \ + && defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define SLI_SE_VERSION_ED25519_ERRATA_UNCERTAIN + #endif + + #if defined(SLI_SE_VERSION_ED25519_ERRATA_UNCERTAIN) \ + && defined(SLI_PSA_DRIVER_FEATURE_EDWARDS25519) + #define SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED + #endif +#endif // SLI_MBEDTLS_DEVICE_HSE + +// ----------------------------------------------------------------------------- +// Version macros + +// HSE specific macros +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #define SLI_SE_VERSION_PUBKEY_VALIDATION_REQUIRED(se_version) \ + (se_version < SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION) + + #define SLI_SE_VERSION_ED25519_BROKEN(se_version) \ + (!((se_version < SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519) \ + || (se_version > SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519))) +#endif // SLI_MBEDTLS_DEVICE_HSE + +// Common HSE/VSE macros +#define SLI_VERSION_REMOVE_DIE_ID(version) ((version) & 0x00FFFFFFU) + +#define SLI_SE_VERSION_SUPPORTS_SRK(se_version) \ + (SLI_VERSION_REMOVE_DIE_ID(se_version) >= SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT) + +// ----------------------------------------------------------------------------- +// Function declarations + +#ifdef __cplusplus +extern "C" { +#endif + +psa_status_t sli_se_check_eddsa_errata(const psa_key_attributes_t* attributes, + sl_se_command_context_t* cmd_ctx); + +#ifdef __cplusplus +} +#endif + +/// @endcond + +#endif // SLI_SE_VERSION_DEPENDENCIES_H diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c new file mode 100644 index 000000000..07ae44eb8 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c @@ -0,0 +1,136 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs CRYPTOACC device management interface. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "sli_se_manager_internal.h" + +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_aes.h" +#include "ba414ep_config.h" + +//------------------------------------------------------------------------------ +// RTOS Synchronization and Clocking Functions + +// Get ownership of an available CRYPTOACC device. +psa_status_t cryptoacc_management_acquire(void) +{ + #if defined(MBEDTLS_THREADING_C) + if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Take SE lock - wait/block if taken by another thread. + sl_status_t ret = sli_se_lock_acquire(); + if (ret != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + #endif + + CMU->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC; + CMU->CRYPTOACCCLKCTRL_SET = (CMU_CRYPTOACCCLKCTRL_PKEN + | CMU_CRYPTOACCCLKCTRL_AESEN); + + return PSA_SUCCESS; +} + +// Release ownership of a reserved CRYPTOACC device. +psa_status_t cryptoacc_management_release(void) +{ + CMU->CLKEN1_CLR = CMU_CLKEN1_CRYPTOACC; + CMU->CRYPTOACCCLKCTRL_CLR = (CMU_CRYPTOACCCLKCTRL_PKEN + | CMU_CRYPTOACCCLKCTRL_AESEN); + + #if defined(MBEDTLS_THREADING_C) + if (sli_se_lock_release() != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + #endif + + return PSA_SUCCESS; +} + +//------------------------------------------------------------------------------ +// Countermeasure Initialization Functions + +#if defined(SLI_MBEDTLS_DEVICE_VSE_V2) + +psa_status_t cryptoacc_initialize_countermeasures(void) +{ + // Set to true when CM has been initialized + static bool cm_inited = false; + + // Note on the error handling: we want to try and set up the countermeasures + // even if some of the steps fail. Hence, the first error code is stored and + // returned in the end if something goes wrong. + psa_status_t final_status = PSA_SUCCESS; + if (!cm_inited) { + // Set up the PK engine with a TRNG wrapper function to use for randomness + // generation. This will be used for future ECC operations as well, not only + // during the lifetime of this function. + ba414ep_set_rng(sli_cryptoacc_trng_wrapper); + + // Seed the AES engine with a random mask. The highest bit must be set due + // to hardware requirements. + uint32_t mask = 0; + psa_status_t temp_status = sli_cryptoacc_trng_get_random((uint8_t *)&mask, + sizeof(mask)); + if (temp_status != PSA_SUCCESS) { + final_status = temp_status; + } + mask |= (1U << 31); + + temp_status = cryptoacc_management_acquire(); + if (temp_status != PSA_SUCCESS) { + final_status = temp_status; + } + sx_aes_load_mask(mask); + temp_status = cryptoacc_management_release(); + if ((temp_status != PSA_SUCCESS) && (final_status == PSA_SUCCESS)) { + final_status = temp_status; + } + + // Only track that init was successful if no error codes popped up. + if (final_status == PSA_SUCCESS) { + cm_inited = true; + } + } + + return final_status; +} + +#endif // SLI_MBEDTLS_DEVICE_VSE_V2 + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c new file mode 100644 index 000000000..70ae15134 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c @@ -0,0 +1,3303 @@ +/***************************************************************************//** + * @file + * @brief PSA ITS implementation based on Silicon Labs NVM3 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// The psa_driver_wrappers.h file that we're including here assumes that it has +// access to private struct members. Define this here in order to avoid +// compilation errors. +#define MBEDTLS_ALLOW_PRIVATE_ACCESS + +// ------------------------------------- +// Includes + +#include + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) && !defined(MBEDTLS_PSA_ITS_FILE_C) + +#include "psa/internal_trusted_storage.h" +#include "psa/sli_internal_trusted_storage.h" +#include "nvm3_default.h" +#include "mbedtls/platform.h" +#include +#include + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + #include + #include "psa/storage_common.h" +#endif // TFM_CONFIG_SL_SECURE_LIBRARY + +#if defined(SLI_PSA_ITS_ENCRYPTED) + #include "psa_crypto_core.h" + #include "psa_crypto_driver_wrappers.h" + #if defined(SEMAILBOX_PRESENT) + #include "psa/crypto_extra.h" + #include "sl_psa_values.h" + #include "sli_se_opaque_functions.h" + #endif // defined(SEMAILBOX_PRESENT) +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// SLI_STATIC_TESTABLE is used to expose otherwise-static variables during +// internal testing. +#if defined(SLI_STATIC_TESTABLE) + #define SLI_STATIC +#else + #define SLI_STATIC static +#endif + +// ------------------------------------- +// Threading support + +#if defined(MBEDTLS_THREADING_C) + #include "cmsis_os2.h" + #include "mbedtls/threading.h" + +// Mutex for protecting access to the ITS instance +SLI_STATIC mbedtls_threading_mutex_t its_mutex MUTEX_INIT; +static volatile bool its_mutex_inited = false; + +/** + * \brief Lock all task switches + * + * \return Previous lock state + * + */ +static inline int32_t lock_task_switches(void) +{ + int32_t kernel_lock_state = 0; + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + kernel_lock_state = osKernelLock(); + } + return kernel_lock_state; +} + +/** + * \brief Restores the previous lock state + */ +static inline void restore_lock_state(int32_t kernel_lock_state) +{ + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + if (osKernelRestoreLock(kernel_lock_state) < 0) { + EFM_ASSERT(false); + } + } +} + +#endif // defined(MBEDTLS_THREADING_C) + +/** + * \brief Pend on the ITS mutex + */ +void sli_its_acquire_mutex(void) +{ +#if defined(MBEDTLS_THREADING_C) + if (!its_mutex_inited) { + int32_t kernel_lock_state = lock_task_switches(); + if (!its_mutex_inited) { + // The ITS mutex needs to be recursive since the same thread may need + // to acquire it more than one time. + THREADING_SetRecursive(&its_mutex); + mbedtls_mutex_init(&its_mutex); + its_mutex_inited = true; + } + restore_lock_state(kernel_lock_state); + } + if (mbedtls_mutex_lock(&its_mutex) != 0) { + EFM_ASSERT(false); + } +#endif +} + +/** + * \brief Free the ITS mutex. + */ +void sli_its_release_mutex(void) +{ +#if defined(MBEDTLS_THREADING_C) + if (its_mutex_inited) { + mbedtls_mutex_unlock(&its_mutex); + } +#endif +} + +// ------------------------------------- +// Defines + +#if (!SL_PSA_ITS_SUPPORT_V3_DRIVER) +#define SLI_PSA_ITS_NVM3_RANGE_START SLI_PSA_ITS_NVM3_RANGE_BASE +#define SLI_PSA_ITS_NVM3_RANGE_END SLI_PSA_ITS_NVM3_RANGE_START + SL_PSA_ITS_MAX_FILES + +#define SLI_PSA_ITS_NVM3_INVALID_KEY (0) +#define SLI_PSA_ITS_NVM3_UNKNOWN_KEY (1) + +#if SL_PSA_ITS_MAX_FILES > SLI_PSA_ITS_NVM3_RANGE_SIZE +#error "Trying to store more ITS files then our NVM3 range allows for" +#endif + +#define SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE 16 + +// Enable backwards-compatibility with keys stored with a v1 header unless disabled. +#if !defined(SL_PSA_ITS_REMOVE_V1_HEADER_SUPPORT) +#define SLI_PSA_ITS_SUPPORT_V1_FORMAT +#endif + +// Internal error codes local to this compile unit +#define SLI_PSA_ITS_ECODE_NO_VALID_HEADER (ECODE_EMDRV_NVM3_BASE - 1) +#define SLI_PSA_ITS_ECODE_NEEDS_UPGRADE (ECODE_EMDRV_NVM3_BASE - 2) + +#if defined(SLI_PSA_ITS_ENCRYPTED) +// Define some cryptographic constants if not already set. This depends on the underlying +// crypto accelerator in use (CRYPTOACC has these defines, but not SEMAILBOX). +#if !defined(AES_MAC_SIZE) +#define AES_MAC_SIZE 16 +#endif + +#if !defined(AES_IV_GCM_SIZE) +#define AES_IV_GCM_SIZE 12 +#endif + +#define SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD (AES_IV_GCM_SIZE + AES_MAC_SIZE) +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Local global static variables + +SLI_STATIC bool nvm3_uid_set_cache_initialized = false; +SLI_STATIC uint32_t nvm3_uid_set_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; + +typedef struct { + psa_storage_uid_t uid; + nvm3_ObjectKey_t object_id; + bool set; +} previous_lookup_t; + +static previous_lookup_t previous_lookup = { + 0, 0, false +}; + +#if defined(SLI_PSA_ITS_ENCRYPTED) +// The root key is an AES-256 key, and is therefore 32 bytes. +#define ROOT_KEY_SIZE (32) +// The session key is derived from CMAC, which means it is equal to the AES block size, i.e. 16 bytes +#define SESSION_KEY_SIZE (16) + +#if !defined(SEMAILBOX_PRESENT) +typedef struct { + bool initialized; + uint8_t data[ROOT_KEY_SIZE]; +} root_key_t; + +static root_key_t g_root_key = { + .initialized = false, + .data = { 0 }, +}; +#endif // !defined(SEMAILBOX_PRESENT) + +typedef struct { + bool active; + psa_storage_uid_t uid; + uint8_t data[SESSION_KEY_SIZE]; +} session_key_t; + +static session_key_t g_cached_session_key = { + .active = false, + .uid = 0, + .data = { 0 }, +}; +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Structs + +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) +typedef struct { + uint32_t magic; + psa_storage_uid_t uid; + psa_storage_create_flags_t flags; +} sl_its_file_meta_v1_t; +#endif // defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) + +// Due to alignment constraints on the 64-bit UID, the v2 header struct is +// serialized to 16 bytes instead of the 24 bytes the v1 header compiles to. +typedef struct { + uint32_t magic; + psa_storage_create_flags_t flags; + psa_storage_uid_t uid; +} sli_its_file_meta_v2_t; + +#if defined(SLI_PSA_ITS_ENCRYPTED) +typedef struct { + uint8_t iv[AES_IV_GCM_SIZE]; + // When encrypted & authenticated, MAC is stored at the end of the data array + uint8_t data[]; +} sli_its_encrypted_blob_t; +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Local function prototypes + +static nvm3_ObjectKey_t get_nvm3_id(psa_storage_uid_t uid, bool find_empty_slot); +static nvm3_ObjectKey_t prepare_its_get_nvm3_id(psa_storage_uid_t uid); + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +static inline bool object_lives_in_s(const void *object, size_t object_size); +#endif // defined(TFM_CONFIG_SL_SECURE_LIBRARY) + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static psa_status_t derive_session_key(uint8_t *iv, + size_t iv_size, + uint8_t *session_key, + size_t session_key_size); + +static psa_status_t encrypt_its_file(sli_its_file_meta_v2_t *metadata, + uint8_t *plaintext, + size_t plaintext_size, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + size_t *blob_length); + +static psa_status_t decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid); +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Local function definitions + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +// If an object of given size is fully encapsulated in a region of +// secure domain the function returns true. +static inline bool object_lives_in_s(const void *object, size_t object_size) +{ + cmse_address_info_t cmse_flags; + + for (size_t i = 0u; i < object_size; i++) { + cmse_flags = cmse_TTA((uint32_t *)object + i); + if (!cmse_flags.flags.secure) { + return false; + } + } + + return true; +} +#endif // defined(TFM_CONFIG_SL_SECURE_LIBRARY) + +static inline void cache_set(nvm3_ObjectKey_t key) +{ + uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; + uint32_t bin = i / 32; + uint32_t offset = i - 32 * bin; + nvm3_uid_set_cache[bin] |= (1 << offset); +} + +static inline void cache_clear(nvm3_ObjectKey_t key) +{ + uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; + uint32_t bin = i / 32; + uint32_t offset = i - 32 * bin; + nvm3_uid_set_cache[bin] ^= (1 << offset); +} + +static inline bool cache_lookup(nvm3_ObjectKey_t key) +{ + uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; + uint32_t bin = i / 32; + uint32_t offset = i - 32 * bin; + return (bool)((nvm3_uid_set_cache[bin] >> offset) & 0x1); +} + +static void init_cache(void) +{ + size_t num_keys_referenced_by_nvm3; + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; + + for (nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START; + range_start < SLI_PSA_ITS_NVM3_RANGE_END; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE) { + nvm3_ObjectKey_t range_end = range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end > SLI_PSA_ITS_NVM3_RANGE_END) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + + for (size_t i = 0; i < num_keys_referenced_by_nvm3; i++) { + cache_set(keys_referenced_by_nvm3[i]); + } + } + + nvm3_uid_set_cache_initialized = true; +} + +// Read the file metadata for a specific NVM3 ID +static Ecode_t get_file_metadata(nvm3_ObjectKey_t key, + sli_its_file_meta_v2_t* metadata, + size_t* its_file_offset, + size_t* its_file_size) +{ + // Initialize output variables to safe default + if (its_file_offset != NULL) { + *its_file_offset = 0; + } + if (its_file_size != NULL) { + *its_file_size = 0; + } + + Ecode_t status = nvm3_readPartialData(nvm3_defaultHandle, + key, + metadata, + 0, + sizeof(sli_its_file_meta_v2_t)); + if (status != ECODE_NVM3_OK) { + return status; + } + +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) + // Re-read in v1 header format and translate to the latest structure version + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { + sl_its_file_meta_v1_t key_meta_v1 = { 0 }; + status = nvm3_readPartialData(nvm3_defaultHandle, + key, + &key_meta_v1, + 0, + sizeof(sl_its_file_meta_v1_t)); + + if (status != ECODE_NVM3_OK) { + return status; + } + + metadata->flags = key_meta_v1.flags; + metadata->uid = key_meta_v1.uid; + metadata->magic = SLI_PSA_ITS_META_MAGIC_V2; + + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sl_its_file_meta_v1_t); + } + + status = SLI_PSA_ITS_ECODE_NEEDS_UPGRADE; + } else +#endif + { + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sli_its_file_meta_v2_t); + } + } + + if (metadata->magic != SLI_PSA_ITS_META_MAGIC_V2) { + // No valid header found in this object + return SLI_PSA_ITS_ECODE_NO_VALID_HEADER; + } + + if (its_file_offset != NULL && its_file_size != NULL) { + // Calculate the ITS file size if requested + uint32_t obj_type; + Ecode_t info_status = nvm3_getObjectInfo(nvm3_defaultHandle, + key, + &obj_type, + its_file_size); + if (info_status != ECODE_NVM3_OK) { + return info_status; + } + + *its_file_size = *its_file_size - *its_file_offset; + } + + return status; +} + +// Search through NVM3 for uid +static nvm3_ObjectKey_t get_nvm3_id(psa_storage_uid_t uid, bool find_empty_slot) +{ + Ecode_t status; + sli_its_file_meta_v2_t key_meta; + + if (find_empty_slot) { + for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; i++) { + if (!cache_lookup(i + SLI_PSA_ITS_NVM3_RANGE_START)) { + return i + SLI_PSA_ITS_NVM3_RANGE_START; + } + } + } else { + if (previous_lookup.set) { + if (previous_lookup.uid == uid) { + return previous_lookup.object_id; + } + } + + for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; i++) { + if (!cache_lookup(i + SLI_PSA_ITS_NVM3_RANGE_START)) { + continue; + } + nvm3_ObjectKey_t object_id = i + SLI_PSA_ITS_NVM3_RANGE_START; + + status = get_file_metadata(object_id, &key_meta, NULL, NULL); + + if (status == ECODE_NVM3_OK + || status == SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + if (key_meta.uid == uid) { + previous_lookup.set = true; + previous_lookup.object_id = object_id; + previous_lookup.uid = uid; + + return object_id; + } else { + continue; + } + } + + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER + || status == ECODE_NVM3_ERR_READ_DATA_SIZE) { + // we don't expect any other data in our range then PSA ITS files. + // delete the file if the magic doesn't match or the object on disk + // is too small to even have full metadata. + status = nvm3_deleteObject(nvm3_defaultHandle, object_id); + if (status != ECODE_NVM3_OK) { + return SLI_PSA_ITS_NVM3_RANGE_END + 1U; + } + } + } + } + + return SLI_PSA_ITS_NVM3_RANGE_END + 1U; +} + +// Perform NVM3 open and fill the look-up table. +// Try to find the mapping NVM3 object ID with PSA ITS UID. +static nvm3_ObjectKey_t prepare_its_get_nvm3_id(psa_storage_uid_t uid) +{ +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + // With SKL the NVM3 instance must be initialized by the NS app. We therefore check that + // it has been opened (which is done on init) rather than actually doing the init. + if (!nvm3_defaultHandle->hasBeenOpened) { +#else + if (nvm3_initDefault() != ECODE_NVM3_OK) { +#endif + return SLI_PSA_ITS_NVM3_RANGE_END + 1U; + } + + if (nvm3_uid_set_cache_initialized == false) { + init_cache(); + } + + return get_nvm3_id(uid, false); +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static inline void cache_session_key(uint8_t *session_key, psa_storage_uid_t uid) +{ + // Cache the session key + memcpy(g_cached_session_key.data, session_key, sizeof(g_cached_session_key.data)); + g_cached_session_key.uid = uid; + g_cached_session_key.active = true; +} + +/** + * \brief Derive a session key for ITS file encryption from the initialized root key and provided IV. + * + * \param[in] iv Pointer to array containing the initialization vector to be used in the key derivation. + * \param[in] iv_size Size of the IV buffer in bytes. Must be 12 bytes (AES-GCM IV size). + * \param[out] session_key Pointer to array where derived session key shall be stored. + * \param[out] session_key_size Size of the derived session key output array. Must be at least 32 bytes (AES-256 key size). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because iv or session_key is NULL, or their sizes are incorrect. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t derive_session_key(uint8_t *iv, size_t iv_size, uint8_t *session_key, size_t session_key_size) +{ + if (iv == NULL + || iv_size != AES_IV_GCM_SIZE + || session_key == NULL + || session_key_size < SESSION_KEY_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + +#if defined(SEMAILBOX_PRESENT) + // For HSE devices, use the builtin TrustZone Root Key + psa_set_key_id(&attributes, SL_SE_BUILTIN_KEY_TRUSTZONE_ID); + + psa_key_lifetime_t reported_lifetime; + psa_drv_slot_number_t reported_slot; + status = mbedtls_psa_platform_get_builtin_key(psa_get_key_id(&attributes), + &reported_lifetime, + &reported_slot); + + if (status != PSA_SUCCESS) { + return status; + } + + psa_set_key_lifetime(&attributes, reported_lifetime); + + uint8_t key_buffer[sizeof(sli_se_opaque_key_context_header_t)]; + size_t key_buffer_size; + status = sli_se_opaque_get_builtin_key(reported_slot, + &attributes, + key_buffer, + sizeof(key_buffer), + &key_buffer_size); + if (status != PSA_SUCCESS) { + return status; + } +#else // defined(SEMAILBOX_PRESENT) + // For VSE devices, use the previously initialized root key + if (!g_root_key.initialized) { + return PSA_ERROR_BAD_STATE; + } + + // Prepare root key attributes + psa_set_key_algorithm(&attributes, PSA_ALG_CMAC); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, ROOT_KEY_SIZE * 8); + + // Point the key buffer to the global root key + uint8_t *key_buffer = (uint8_t*)g_root_key.data; + size_t key_buffer_size = sizeof(g_root_key.data); +#endif // defined(SEMAILBOX_PRESENT) + + // Use CMAC as a key derivation function + size_t session_key_length; + status = psa_driver_wrapper_mac_compute( + &attributes, + key_buffer, + key_buffer_size, + PSA_ALG_CMAC, + iv, + iv_size, + session_key, + session_key_size, + &session_key_length); + + // Verify that the key derivation was successful before transferring the key to the caller + if (status != PSA_SUCCESS || session_key_length != SESSION_KEY_SIZE) { + memset(session_key, 0, session_key_size); + return PSA_ERROR_HARDWARE_FAILURE; + } + + return status; +} + +/** + * \brief Encrypt and authenticate ITS data with AES-128-GCM, storing the result in an encrypted blob. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. + * \param[in] plaintext Pointer to array containing data to be encrypted. + * \param[in] plaintext_size Size of provided plaintext data array. + * \param[out] blob Pointer to array where the resulting encrypted blob shall be placed. + * \param[in] blob_size Size of the output array. Must be at least as big as plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + * \param[out] blob_length Resulting size of the output blob. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t encrypt_its_file(sli_its_file_meta_v2_t *metadata, + uint8_t *plaintext, + size_t plaintext_size, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + size_t *blob_length) +{ + if (metadata == NULL + || (plaintext == NULL && plaintext_size > 0) + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || blob_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Generate IV + size_t iv_length = 0; + psa_status_t psa_status = mbedtls_psa_external_get_random(NULL, blob->iv, AES_IV_GCM_SIZE, &iv_length); + + if (psa_status != PSA_SUCCESS || iv_length != AES_IV_GCM_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Prepare encryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + uint8_t session_key[SESSION_KEY_SIZE]; + psa_status = derive_session_key(blob->iv, AES_IV_GCM_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + cache_session_key(session_key, metadata->uid); + + // Retrieve data to be encrypted + if (plaintext_size != 0U) { + memcpy(blob->data, ((uint8_t*)plaintext), plaintext_size); + } + + // Encrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_encrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size, + blob->data, plaintext_size + AES_MAC_SIZE, // output == input for in-place encryption + &output_length); + + // Clear the local session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + if (psa_status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (output_length != plaintext_size + AES_MAC_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *blob_length = output_length + AES_IV_GCM_SIZE; + + return PSA_SUCCESS; +} + +/** + * \brief Decrypt and authenticate encrypted ITS data. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. Must be identical to the metadata used during encryption. + * \param[in] blob Encrypted blob containing data to be decrypted. + * \param[in] blob_size Size of the encrypted blob in bytes. + * \param[out] plaintext Pointer to array where the decrypted plaintext shall be placed. + * \param[in] plaintext_size Size of the plaintext array. Must be equal to sizeof(blob->data) - AES_MAC_SIZE. + * \param[out] plaintext_length Resulting length of the decrypted plaintext. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + if (metadata == NULL + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || (plaintext == NULL && plaintext_size > 0) + || plaintext_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Prepare decryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t session_key[SESSION_KEY_SIZE]; + + if (g_cached_session_key.active && g_cached_session_key.uid == metadata->uid) { + // Use cached session key if it's already set and UID matches + memcpy(session_key, g_cached_session_key.data, sizeof(session_key)); + } else { + psa_status = derive_session_key(blob->iv, AES_IV_GCM_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + cache_session_key(session_key, metadata->uid); + } + + // Decrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_decrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size + AES_MAC_SIZE, + plaintext, plaintext_size, + &output_length); + + // Clear the session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + // Invalid signature likely means that NVM data was tampered with + if (psa_status == PSA_ERROR_INVALID_SIGNATURE) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + if (psa_status != PSA_SUCCESS + || output_length != plaintext_size) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = output_length; + + return PSA_SUCCESS; +} + +/** + * \brief Authenticate encrypted ITS data and return the UID of the ITS file that was authenticated. + * + * \details NOTE: This function will run decrypt_its_file() internally. The difference from the decrypt_its_file() + * function is that authenticate_its_file() reads the NVM3 data, decrypts it in order to authenticate the + * stored data, and then discards the plaintext. This is needed since PSA Crypto doesn't support the + * GMAC primitive directly, which means we have to run a full GCM decrypt for authentication. + * + * \param[in] nvm3_object_id The NVM3 id corresponding to the stored ITS file. + * \param[out] authenticated_uid UID for the authenticated ITS file. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid) +{ + psa_status_t ret = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t *its_file_meta = NULL; + sli_its_encrypted_blob_t *blob = NULL; + + uint32_t obj_type; + size_t its_file_size = 0; + Ecode_t status = nvm3_getObjectInfo(nvm3_defaultHandle, + nvm3_object_id, + &obj_type, + &its_file_size); + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_STORAGE_FAILURE; + } + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size); + + status = nvm3_readData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status != ECODE_NVM3_OK) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto cleanup; + } + + its_file_meta = (sli_its_file_meta_v2_t*)its_file_buffer; + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Decrypt and authenticate blob + size_t plaintext_length; + ret = decrypt_its_file(its_file_meta, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + blob->data, + its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (ret != PSA_SUCCESS) { + goto cleanup; + } + + if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + ret = PSA_ERROR_INVALID_SIGNATURE; + goto cleanup; + } + + if (authenticated_uid != NULL) { + *authenticated_uid = its_file_meta->uid; + } + + ret = PSA_SUCCESS; + + cleanup: + + // Discard output, as we're only interested in whether the authentication check passed or not. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + + return ret; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Global function definitions + +/** + * \brief create a new or modify an existing uid/value pair + * + * \param[in] uid the identifier for the data + * \param[in] data_length The size in bytes of the data in `p_data` + * \param[in] p_data A buffer containing the data + * \param[in] create_flags The flags that the data will be stored with + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid + * \retval PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +psa_status_t psa_its_set(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags) +{ + if (data_length > NVM3_MAX_OBJECT_SIZE) { + return PSA_ERROR_STORAGE_FAILURE; + } + if ((data_length != 0U) && (p_data == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE + && create_flags != PSA_STORAGE_FLAG_NONE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) + && (!object_lives_in_s(p_data, data_length))) { + // The flag indicates that this data should not be set by the non-secure domain + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + Ecode_t status; + psa_status_t ret = PSA_SUCCESS; + sli_its_file_meta_v2_t* its_file_meta; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + psa_storage_uid_t authenticated_uid; + sli_its_encrypted_blob_t *blob = NULL; + size_t blob_length = 0u; + psa_status_t psa_status; + + size_t its_file_size = data_length + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + size_t its_file_size = data_length; +#endif + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); + if (its_file_buffer == NULL) { + ret = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + its_file_meta = (sli_its_file_meta_v2_t *)its_file_buffer; + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + // ITS UID was not found. Request a new. + nvm3_object_id = get_nvm3_id(0ULL, true); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + // The storage is full, or an error was returned during cleanup. + ret = PSA_ERROR_INSUFFICIENT_STORAGE; + } else { + its_file_meta->uid = uid; + its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V2; + } + } else { + // ITS UID was found. Read ITS meta data. + status = get_file_metadata(nvm3_object_id, its_file_meta, NULL, NULL); + + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + if (its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + ret = PSA_ERROR_NOT_PERMITTED; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. + ret = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (ret != PSA_SUCCESS) { + goto exit; + } + + if (authenticated_uid != uid) { + ret = PSA_ERROR_NOT_PERMITTED; + goto exit; + } +#endif + } + + its_file_meta->flags = create_flags; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Everything after the file metadata will make up the encrypted & authenticated blob + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Encrypt and authenticate the provided data + psa_status = encrypt_its_file(its_file_meta, + (uint8_t*)p_data, + data_length, + blob, + its_file_size, + &blob_length); + + if (psa_status != PSA_SUCCESS) { + ret = psa_status; + goto exit; + } + + if (blob_length != its_file_size) { + ret = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + +#else + if (data_length != 0U) { + memcpy(its_file_buffer + sizeof(sli_its_file_meta_v2_t), ((uint8_t*)p_data), data_length); + } +#endif + + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + cache_set(nvm3_object_id); + } else { + ret = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + if (its_file_buffer != NULL) { + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + } + sli_its_release_mutex(); + return ret; +} + +/** + * \brief Retrieve the value associated with a provided uid + * + * \param[in] uid The uid value + * \param[in] data_offset The starting offset of the data requested + * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) + * \param[out] p_data The buffer where the data will be placed upon successful completion + * \param[out] p_data_length The amount of data returned in the p_data buffer + * + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage + * \retval PSA_ERROR_BUFFER_TOO_SMALL The operation failed because the data associated with provided uid is larger than `data_size` + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) + * is invalid. For example is `NULL` or references memory the caller cannot access. + * In addition, this can also happen if an invalid offset was provided. + */ +psa_status_t psa_its_get(psa_storage_uid_t uid, + uint32_t data_offset, + uint32_t data_length, + void *p_data, + size_t *p_data_length) +{ + psa_status_t ret = PSA_ERROR_CORRUPTION_DETECTED; + + if ((data_length != 0U) && (p_data_length == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (data_length != 0U) { + // If the request amount of data is 0, allow invalid pointer of the output buffer. + if ((p_data == NULL) + || ((uint32_t)p_data < SRAM_BASE) + || ((uint32_t)p_data > (SRAM_BASE + SRAM_SIZE - data_length))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + sli_its_encrypted_blob_t *blob = NULL; + size_t plaintext_length; + psa_status_t psa_status; +#endif + size_t its_file_data_size = 0u; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + ret = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + ret = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE + && !object_lives_in_s(p_data, data_length)) { + // The flag indicates that this data should not be read back to the non-secure domain + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Subtract IV and MAC from ITS file as the below checks concern the actual data size + its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + its_file_data_size = its_file_size; +#endif + + if (data_length != 0U) { + if ((data_offset >= its_file_data_size) && (its_file_data_size != 0U)) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if ((its_file_data_size == 0U) && (data_offset != 0U)) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } else { + // Allow the offset at the data size boundary if the requested amount of data is zero. + if (data_offset > its_file_data_size) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } + + if (data_length > (its_file_data_size - data_offset)) { + *p_data_length = its_file_data_size - data_offset; + } else { + *p_data_length = data_length; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // its_file_size includes size of sli_its_encrypted_blob_t struct + blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); + if (blob == NULL) { + ret = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + memset(blob, 0, its_file_size); + + status = nvm3_readPartialData(nvm3_defaultHandle, + nvm3_object_id, + blob, + its_file_offset, + its_file_size); + if (status != ECODE_NVM3_OK) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + // Decrypt and authenticate blob + psa_status = decrypt_its_file(&its_file_meta, + blob, + its_file_size, + blob->data, + its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + ret = psa_status; + goto exit; + } + + if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + ret = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + + // Verify that the requested UID is equal to the retrieved and authenticated UID + if (uid != its_file_meta.uid) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if (*p_data_length > 0) { + memcpy(p_data, blob->data + data_offset, *p_data_length); + } + ret = PSA_SUCCESS; + + exit: + if (blob != NULL) { + memset(blob, 0, its_file_size); + mbedtls_free(blob); + } + sli_its_release_mutex(); +#else + // If no encryption is used, just read out the data and write it directly to the output buffer + status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, its_file_offset + data_offset, *p_data_length); + + if (status != ECODE_NVM3_OK) { + ret = PSA_ERROR_STORAGE_FAILURE; + } else { + ret = PSA_SUCCESS; + } + + exit: + sli_its_release_mutex(); +#endif + + return ret; +} + +/** + * \brief Retrieve the metadata about the provided uid + * + * \param[in] uid The uid value + * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the stored metadata failed. + */ +psa_status_t psa_its_get_info(psa_storage_uid_t uid, + struct psa_storage_info_t *p_info) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + if (p_info == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Authenticate the ITS file (both metadata and ciphertext) before returning the metadata. + // Note that this can potentially induce a significant performance hit. + psa_storage_uid_t authenticated_uid; + psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (authenticated_uid != uid) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } +#endif + + p_info->flags = its_file_meta.flags; + p_info->size = its_file_size; + + psa_status = PSA_SUCCESS; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Remove IV and MAC size from file size + p_info->size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#endif + exit: + sli_its_release_mutex(); + return psa_status; +} + +/** + * \brief Remove the provided key and its associated data from the storage + * + * \param[in] uid The uid value + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + */ +psa_status_t psa_its_remove(psa_storage_uid_t uid) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + psa_status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. + psa_storage_uid_t authenticated_uid; + psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (authenticated_uid != uid) { + psa_status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } +#endif + + status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + if (previous_lookup.set && previous_lookup.uid == uid) { + previous_lookup.set = false; + } + cache_clear(nvm3_object_id); + + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + sli_its_release_mutex(); + return psa_status; +} + +// ------------------------------------- +// Silicon Labs extensions +static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) +{ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + // Encode the owner in the upper 32 bits. This means that if + // owner values are nonzero (as they are on a PSA platform), + // no key file will ever have a value less than 0x100000000, so + // the whole range 0..0xffffffff is available for non-key files. + uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); + return ((uint64_t)unsigned_owner_id << 32) | MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); +#else + // Use the key id directly as a file name. + // psa_is_key_id_valid() in psa_crypto_slot_management.c + // is responsible for ensuring that key identifiers do not have a + // value that is reserved for non-key files. + return key; +#endif +} + +psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, + mbedtls_svc_key_id_t new_id) +{ + psa_storage_uid_t old_uid = psa_its_identifier_of_slot(old_id); + psa_storage_uid_t new_uid = psa_its_identifier_of_slot(new_id); + Ecode_t status; + uint32_t obj_type; + size_t its_file_size = 0; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + int8_t *its_file_buffer = NULL; + sli_its_file_meta_v2_t* metadata = NULL; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + sli_its_encrypted_blob_t *blob = NULL; + size_t plaintext_length; + size_t blob_length; + psa_status_t encrypt_status; + psa_status_t decrypt_status; +#endif + sli_its_acquire_mutex(); + + // Check whether the key to migrate exists on disk + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(old_uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + // Get total length to allocate + status = nvm3_getObjectInfo(nvm3_defaultHandle, + nvm3_object_id, + &obj_type, + &its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + // Allocate temporary buffer and cast it to the metadata format + its_file_buffer = mbedtls_calloc(1, its_file_size); + if (its_file_buffer == NULL) { + psa_status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + metadata = (sli_its_file_meta_v2_t*) its_file_buffer; + + // Read contents of pre-existing key into the temporary buffer + status = nvm3_readData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Decrypt and authenticate blob + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + decrypt_status = decrypt_its_file(metadata, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + blob->data, + its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (decrypt_status != PSA_SUCCESS) { + psa_status = decrypt_status; + goto exit; + } + + if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } +#endif + + // Swap out the old UID for the new one +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { + // Recast as v1 metadata + sl_its_file_meta_v1_t* metadata_v1 = (sl_its_file_meta_v1_t*) its_file_buffer; + if (metadata_v1->uid != old_uid) { + psa_status = PSA_ERROR_CORRUPTION_DETECTED; + goto exit; + } + metadata_v1->uid = new_uid; + } else +#endif + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V2) { + if (metadata->uid != old_uid) { + psa_status = PSA_ERROR_CORRUPTION_DETECTED; + goto exit; + } + metadata->uid = new_uid; + } else { + psa_status = PSA_ERROR_CORRUPTION_DETECTED; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Encrypt and authenticate the modified data data + encrypt_status = encrypt_its_file(metadata, + blob->data, + plaintext_length, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + &blob_length); + + if (encrypt_status != PSA_SUCCESS) { + psa_status = encrypt_status; + goto exit; + } + + if (blob_length != (its_file_size - sizeof(sli_its_file_meta_v2_t))) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } +#endif + + // Overwrite the NVM3 token with the changed buffer + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status == ECODE_NVM3_OK) { + // Update last lookup and report success + if (previous_lookup.set) { + if (previous_lookup.uid == old_uid) { + previous_lookup.uid = new_uid; + } + } + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + if (its_file_buffer != NULL) { + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + } + sli_its_release_mutex(); + return psa_status; +} + +/** + * \brief Check if the ITS encryption is enabled + */ +psa_status_t sli_psa_its_encrypted(void) +{ + #if defined(SLI_PSA_ITS_ENCRYPTED) + return PSA_SUCCESS; + #else + return PSA_ERROR_NOT_SUPPORTED; + #endif +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) +/** + * \brief Set the root key to be used when deriving session keys for ITS encryption. + * + * \param[in] root_key Buffer containing the root key. + * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The key was successfully set. + * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. + * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. + */ +psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size) +{ + // Check that arguments are valid + if (root_key == NULL || root_key_size != sizeof(g_root_key.data)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check that the root key has not already been set + // (This is possibly too restrictive. For TrustZone usage this can be enforced by + // not exposing the function to NS instead.) + if (g_root_key.initialized) { + return PSA_ERROR_ALREADY_EXISTS; + } + + // Store the provided root key and mark it as initialized + memcpy(g_root_key.data, root_key, sizeof(g_root_key.data)); + g_root_key.initialized = true; + + return PSA_SUCCESS; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) + +#else // (!SL_PSA_ITS_SUPPORT_V3_DRIVER) + +// ------------------------------------- +// Defines +#define SLI_PSA_ITS_V3_DRIVER (0x3A) +#define SLI_PSA_ITS_V2_DRIVER (0x74) +#define SLI_PSA_ITS_NOT_CHECKED (0xE8) +#define SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID (SLI_PSA_ITS_NVM3_RANGE_START - 1) +#define SLI_PSA_ITS_NVM3_INVALID_KEY (0) +#define SLI_PSA_ITS_NVM3_UNKNOWN_KEY (1) + +#if SL_PSA_ITS_MAX_FILES > SLI_PSA_ITS_NVM3_RANGE_SIZE +#error "Trying to store more ITS files then our NVM3 range allows for" +#endif + +#define SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE 16 + +// Internal error codes local to this compile unit +#define SLI_PSA_ITS_ECODE_NO_VALID_HEADER (ECODE_EMDRV_NVM3_BASE - 1) +#define SLI_PSA_ITS_ECODE_NEEDS_UPGRADE (ECODE_EMDRV_NVM3_BASE - 2) + +// ------------------------------------- +// Local global static variables + +SLI_STATIC bool nvm3_uid_set_cache_initialized = false; +SLI_STATIC uint32_t nvm3_uid_set_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; +SLI_STATIC uint32_t nvm3_uid_tomb_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +SLI_STATIC uint32_t its_driver_version = SLI_PSA_ITS_NOT_CHECKED; +#endif // SL_PSA_ITS_SUPPORT_V2_DRIVER + +#if defined(SLI_PSA_ITS_ENCRYPTED) +// The root key is an AES-256 key, and is therefore 32 bytes. +#define ROOT_KEY_SIZE (32) +// The session key is derived from CMAC, which means it is equal to the AES block size, i.e. 16 bytes +#define SESSION_KEY_SIZE (16) + +#if !defined(SEMAILBOX_PRESENT) +typedef struct { + bool initialized; + uint8_t data[ROOT_KEY_SIZE]; +} root_key_t; + +static root_key_t g_root_key = { + .initialized = false, + .data = { 0 }, +}; +#endif // !defined(SEMAILBOX_PRESENT) + +typedef struct { + bool active; + psa_storage_uid_t uid; + uint8_t data[SESSION_KEY_SIZE]; +} session_key_t; + +static session_key_t g_cached_session_key = { + .active = false, + .uid = 0, + .data = { 0 }, +}; +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Structs + +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) +typedef struct { + uint32_t magic; + psa_storage_uid_t uid; + psa_storage_create_flags_t flags; +} sl_its_file_meta_v1_t; +#endif // defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) + +// ------------------------------------- +// Local function prototypes + +static psa_status_t find_nvm3_id(psa_storage_uid_t uid, + bool find_empty_slot, + sli_its_file_meta_v2_t* its_file_meta, + size_t* its_file_offset, + size_t* its_file_size, + nvm3_ObjectKey_t * output_nvm3_id); +static nvm3_ObjectKey_t derive_nvm3_id(psa_storage_uid_t uid); + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +static inline bool object_lives_in_s(const void *object, size_t object_size); +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static psa_status_t derive_session_key(uint8_t *iv, + size_t iv_size, + uint8_t *session_key, + size_t session_key_size); + +static psa_status_t sli_decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid); +#endif + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +static psa_status_t psa_its_get_legacy(nvm3_ObjectKey_t nvm3_object_id, + sli_its_file_meta_v2_t* its_file_meta, + size_t its_file_size, + size_t its_file_offset, void *p_data); +static psa_status_t detect_legacy_versions(); +static psa_status_t upgrade_all_keys(); + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) +psa_status_t psa_its_set_v1(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags); +#endif // SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL +#endif // SL_PSA_ITS_SUPPORT_V2_DRIVER + +// ------------------------------------- +// Local function definitions +static inline uint32_t get_index(nvm3_ObjectKey_t key) +{ + return (key - (SLI_PSA_ITS_NVM3_RANGE_START)) / 32; +} + +static inline uint32_t get_offset(nvm3_ObjectKey_t key) +{ + return (key - (SLI_PSA_ITS_NVM3_RANGE_START)) % 32; +} + +static inline void set_cache(nvm3_ObjectKey_t key) +{ + nvm3_uid_set_cache[get_index(key)] |= (1 << get_offset(key)); + nvm3_uid_tomb_cache[get_index(key)] &= ~(1 << get_offset(key)); +} + +static inline void set_tomb(nvm3_ObjectKey_t key) +{ + nvm3_uid_tomb_cache[get_index(key)] |= (1 << get_offset(key)); + + uint32_t cache_not_empty = 0; + for ( size_t i = 0; i < (((SL_PSA_ITS_MAX_FILES) +31) / 32); i++ ) { + cache_not_empty += nvm3_uid_set_cache[i]; + } + if (cache_not_empty == 0) { + for ( size_t i = 0; i < (((SL_PSA_ITS_MAX_FILES) +31) / 32); i++ ) { + nvm3_uid_tomb_cache[i] = 0; + } + } +} + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +static inline psa_status_t write_driver_v3() +{ + uint8_t driver_verison = SLI_PSA_ITS_V3_DRIVER; + Ecode_t status; + status = nvm3_writeData(nvm3_defaultHandle, + SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID, + &driver_verison, sizeof(uint8_t)); + if ( status != ECODE_NVM3_OK ) { + return PSA_ERROR_STORAGE_FAILURE; + } + return PSA_SUCCESS; +} +#endif + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +// If an object of given size is fully encapsulated in a region of +// secure domain the function returns true. +static inline bool object_lives_in_s(const void *object, size_t object_size) +{ + cmse_address_info_t cmse_flags; + + for (size_t i = 0u; i < object_size; i++) { + cmse_flags = cmse_TTA((uint32_t *)object + i); + if (!cmse_flags.flags.secure) { + return false; + } + } + + return true; +} +#endif + +static inline void clear_cache(nvm3_ObjectKey_t key) +{ + nvm3_uid_set_cache[get_index(key)] ^= (1 << get_offset(key)); +} + +static inline bool lookup_cache(nvm3_ObjectKey_t key) +{ + return (bool)((nvm3_uid_set_cache[get_index(key)] >> get_offset(key)) & 0x1); +} + +static inline bool lookup_tomb(nvm3_ObjectKey_t key) +{ + return (bool)((nvm3_uid_tomb_cache[get_index(key)] >> get_offset(key)) & 0x1); +} + +static inline nvm3_ObjectKey_t increment_obj_id(nvm3_ObjectKey_t id) +{ + return SLI_PSA_ITS_NVM3_RANGE_START + ((id - SLI_PSA_ITS_NVM3_RANGE_START + 1) + % SL_PSA_ITS_MAX_FILES); +} +static inline nvm3_ObjectKey_t prng(psa_storage_uid_t uid) +{ +// Squash uid down to a 32 bit word + nvm3_ObjectKey_t uid_32 = uid & 0xFFFFFFFF; + nvm3_ObjectKey_t xored_32 = (uid >> 32) ^ uid_32; + nvm3_ObjectKey_t temp; +// Accumulate all "entropy" towards the LSB, since that is where we need it + for ( size_t i = 1; i < 4; i++ ) { + temp = xored_32 ^ (xored_32 >> (8 * i)); + if ((temp & 0x3) != 0 ) { + temp = temp << 2; + } + uid_32 = (uid_32 + temp); + } + return uid_32; +} + +static inline nvm3_ObjectKey_t derive_nvm3_id(psa_storage_uid_t uid) +{ + return SLI_PSA_ITS_NVM3_RANGE_START + (prng(uid) % (SL_PSA_ITS_MAX_FILES)); +} + +static void init_cache(void) +{ + size_t num_keys_referenced_by_nvm3; + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; + size_t num_del_keys_from_nvm3; + nvm3_ObjectKey_t deleted_keys_from_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; + for (nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START; + range_start < SLI_PSA_ITS_NVM3_RANGE_END; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE) { + nvm3_ObjectKey_t range_end = range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end > SLI_PSA_ITS_NVM3_RANGE_END) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + + for (size_t i = 0; i < num_keys_referenced_by_nvm3; i++) { + set_cache(keys_referenced_by_nvm3[i]); + } + num_del_keys_from_nvm3 = nvm3_enumDeletedObjects(nvm3_defaultHandle, + deleted_keys_from_nvm3, + sizeof(deleted_keys_from_nvm3) / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + for (size_t i = 0; i < num_del_keys_from_nvm3; i++) { + set_tomb(deleted_keys_from_nvm3[i]); + } + } + nvm3_uid_set_cache_initialized = true; +} + +// Read the file metadata for a specific NVM3 ID +static Ecode_t get_file_metadata(nvm3_ObjectKey_t key, + sli_its_file_meta_v2_t* metadata, + size_t* its_file_offset, + size_t* its_file_size) +{ + // Initialize output variables to safe default + if (its_file_offset != NULL) { + *its_file_offset = 0; + } + if (its_file_size != NULL) { + *its_file_size = 0; + } + + Ecode_t status = nvm3_readPartialData(nvm3_defaultHandle, + key, + metadata, + 0, + sizeof(sli_its_file_meta_v2_t)); + if (status != ECODE_NVM3_OK) { + return status; + } + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) + // Re-read in v1 header format and translate to the latest structure version + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { + sl_its_file_meta_v1_t key_meta_v1 = { 0 }; + status = nvm3_readPartialData(nvm3_defaultHandle, + key, + &key_meta_v1, + 0, + sizeof(sl_its_file_meta_v1_t)); + + if (status != ECODE_NVM3_OK) { + return status; + } + + metadata->flags = key_meta_v1.flags; + metadata->uid = key_meta_v1.uid; + metadata->magic = SLI_PSA_ITS_META_MAGIC_V2; + + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sl_its_file_meta_v1_t); + } + + status = SLI_PSA_ITS_ECODE_NEEDS_UPGRADE; + } else +#endif + { + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sli_its_file_meta_v2_t); + } + } + + if (metadata->magic != SLI_PSA_ITS_META_MAGIC_V2) { + // No valid header found in this object + return SLI_PSA_ITS_ECODE_NO_VALID_HEADER; + } + + if (its_file_offset != NULL && its_file_size != NULL) { + // Calculate the ITS file size if requested + uint32_t obj_type; + Ecode_t info_status = nvm3_getObjectInfo(nvm3_defaultHandle, + key, + &obj_type, + its_file_size); + if (info_status != ECODE_NVM3_OK) { + return info_status; + } + + *its_file_size = *its_file_size - *its_file_offset; + } + + return status; +} + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +static psa_status_t psa_its_get_legacy(nvm3_ObjectKey_t nvm3_object_id, + sli_its_file_meta_v2_t* its_file_meta, + size_t its_file_size, + size_t its_file_offset, + void *p_data) +{ + Ecode_t status; + if (its_file_size == 0) { + if (its_file_meta != NULL) { + return PSA_ERROR_DATA_INVALID; + } + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_encrypted_blob_t *blob = NULL; + size_t plaintext_length; + + // its_file_size includes size of sli_its_encrypted_blob_t struct + blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); + if (blob == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(blob, 0, its_file_size); + + status = nvm3_readPartialData(nvm3_defaultHandle, + nvm3_object_id, + blob, + its_file_offset, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto cleanup; + } + + // Decrypt and authenticate blob + psa_status = sli_decrypt_its_file(its_file_meta, + blob, + its_file_size, + blob->data, + its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + goto cleanup; + } + + if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto cleanup; + } + + if (its_file_size + its_file_offset > 0) { + memcpy(p_data, blob->data, its_file_size + its_file_offset); + } + psa_status = PSA_SUCCESS; + + cleanup: + if (blob != NULL) { + memset(blob, 0, its_file_size); + mbedtls_free(blob); + } + return psa_status; +#else + // If no encryption is used, just read out the data and write it directly to the output buffer + status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, + its_file_offset, its_file_size); + + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_STORAGE_FAILURE; + } else { + return PSA_SUCCESS; + } +#endif +} + +// Function sets detect the presence of v1 and v2 its driver. If there is something +// stored in v1/v2 driver range, it sets its_driver_version to SLI_PSA_ITS_V2_DRIVER. +static psa_status_t detect_legacy_versions() +{ + uint8_t driver_verison = 0; + Ecode_t status; + status = nvm3_readData(nvm3_defaultHandle, SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID, + &driver_verison, sizeof(uint8_t)); + if ((status != ECODE_NVM3_OK) && (status != ECODE_NVM3_ERR_KEY_NOT_FOUND)) { + return PSA_ERROR_STORAGE_FAILURE; + } + if (driver_verison == SLI_PSA_ITS_V3_DRIVER) { + its_driver_version = SLI_PSA_ITS_V3_DRIVER; + return PSA_SUCCESS; + } + + size_t num_keys_referenced_by_nvm3; + + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { + 0 + }; + + for ( nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER; + range_start < SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE ) { + nvm3_ObjectKey_t range_end = + range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end > SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER ) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) + / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + + if (num_keys_referenced_by_nvm3 > 0) { + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + status = get_file_metadata(keys_referenced_by_nvm3[0], + &its_file_meta, &its_file_offset, + &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + return PSA_ERROR_DOES_NOT_EXIST; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + return PSA_ERROR_STORAGE_FAILURE; + } + + if ((its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V1) + || (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V2)) { + its_driver_version = SLI_PSA_ITS_V2_DRIVER; + return PSA_SUCCESS; + } else { + return PSA_ERROR_STORAGE_FAILURE; + } + } + } + its_driver_version = SLI_PSA_ITS_V3_DRIVER; + return PSA_SUCCESS; +} + +static psa_status_t upgrade_all_keys() +{ + size_t num_keys_referenced_by_nvm3; + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { + 0 + }; + Ecode_t status; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_data_size; + uint8_t * its_file_buffer = NULL; + + size_t its_file_size = 0; + size_t its_file_offset; + + for ( nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER; + range_start < SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE ) { + nvm3_ObjectKey_t range_end = + range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end >= SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER ) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) + / + sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + for ( size_t i = 0; i < num_keys_referenced_by_nvm3; i++ ) { + its_file_size = 0; + its_file_offset = 0; + status = get_file_metadata(keys_referenced_by_nvm3[i], + &(its_file_meta), &its_file_offset, + &its_file_size); + if ( status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + return PSA_ERROR_DOES_NOT_EXIST; + } + if ( status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + return PSA_ERROR_STORAGE_FAILURE; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Subtract IV and MAC from ITS file as the below checks concern the actual data size + its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + its_file_data_size = its_file_size; +#endif + + if ((its_file_meta.magic != SLI_PSA_ITS_META_MAGIC_V2) + && (its_file_meta.magic != SLI_PSA_ITS_META_MAGIC_V1)) { + return PSA_ERROR_STORAGE_FAILURE; + } + its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } +#if defined(SLI_PSA_ITS_ENCRYPTED) + psa_status = psa_its_get_legacy(keys_referenced_by_nvm3[i], + &(its_file_meta), + its_file_size, + its_file_offset, + its_file_buffer); +#else + psa_status = psa_its_get_legacy(keys_referenced_by_nvm3[i], + NULL, + its_file_size, + its_file_offset, + its_file_buffer); +#endif + if (psa_status != PSA_SUCCESS) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) + if (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V1) { + psa_status = psa_its_set_v1(its_file_meta.uid, its_file_data_size, + its_file_buffer, its_file_meta.flags); + } else if (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V2) +#endif + { + psa_status = psa_its_set(its_file_meta.uid, its_file_data_size, + its_file_buffer, its_file_meta.flags); + } + + if ((psa_status != PSA_SUCCESS) && (psa_status + != PSA_ERROR_NOT_PERMITTED)) { + goto exit; + } + status = nvm3_deleteObject(nvm3_defaultHandle, + keys_referenced_by_nvm3[i]); + + if ( status != ECODE_NVM3_OK ) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + } + } + return PSA_SUCCESS; + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + return psa_status; +} + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) +psa_status_t psa_its_set_v1(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags) +{ + if ((data_length != 0U) && (p_data == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE + && create_flags != PSA_STORAGE_FLAG_NONE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) + && (!object_lives_in_s(p_data, data_length))) { + // The flag indicates that this data should not be set by the non-secure domain + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif + + Ecode_t status; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sl_its_file_meta_v1_t* its_file_meta; + nvm3_ObjectKey_t nvm3_object_id = 0; + size_t its_file_size = data_length; + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sl_its_file_meta_v1_t)); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sl_its_file_meta_v1_t)); + + its_file_meta = (sl_its_file_meta_v1_t *)its_file_buffer; + sli_its_file_meta_v2_t its_file_meta_v2; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, true, &its_file_meta_v2, NULL, NULL, + &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + if (psa_status == PSA_ERROR_DOES_NOT_EXIST) { + psa_status = PSA_ERROR_INSUFFICIENT_STORAGE; + } + goto exit; + } + + its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V1; + its_file_meta->uid = uid; + its_file_meta->flags = create_flags; + + if (data_length != 0U) { + memcpy(its_file_buffer + sizeof(sl_its_file_meta_v1_t), ((uint8_t*) + p_data), data_length); + } + + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, its_file_size + sizeof + (sl_its_file_meta_v1_t)); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + set_cache(nvm3_object_id); + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sl_its_file_meta_v1_t)); + mbedtls_free(its_file_buffer); + sli_its_release_mutex(); + return psa_status; +} +#endif //SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL +#endif //SL_PSA_ITS_SUPPORT_V1_DRIVER + +/** + * \brief Search through NVM3 for correct uid + * + * \param[in] uid UID under what we want to store the data + * \param[in] find_empty_slot Indicates whether we want to find existing data or empty space for storing new. + * \param[out] its_file_meta Meta information of ITS file + * \param[out] its_file_offset Offset of ITS file + * \param[out] its_file_size Size of ITS file + * \param[out] output_nvm3_id NVM3 ID corresponding to UID. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The data with this UID are not stored in NVM3 + * \retval PSA_ERROR_NOT_PERMITTED The requested operation is not permitted + */ +static psa_status_t find_nvm3_id(psa_storage_uid_t uid, + bool find_empty_slot, + sli_its_file_meta_v2_t* its_file_meta, + size_t* its_file_offset, + size_t* its_file_size, + nvm3_ObjectKey_t * output_nvm3_id) +{ + Ecode_t status; + nvm3_ObjectKey_t tmp_id = 0; + nvm3_ObjectKey_t nvm3_object_id = 0; + nvm3_object_id = derive_nvm3_id(uid); + + if (nvm3_uid_set_cache_initialized == false) { +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) \ + // With SKL the NVM3 instance must be initialized by the NS app. We therefore check that + // it has been opened (which is done on init) rather than actually doing the init. + if (!nvm3_defaultHandle->hasBeenOpened) { +#else + if (nvm3_initDefault() != ECODE_NVM3_OK) { +#endif + return PSA_ERROR_STORAGE_FAILURE; + } + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER + if ( its_driver_version == SLI_PSA_ITS_NOT_CHECKED ) { + if ( detect_legacy_versions() != PSA_SUCCESS ) { + return PSA_ERROR_STORAGE_FAILURE; + } + if ( its_driver_version == SLI_PSA_ITS_V2_DRIVER ) { + psa_status_t psa_status = upgrade_all_keys(); + if ( psa_status != PSA_SUCCESS ) { + return psa_status; + } + psa_status = write_driver_v3(); + if ( psa_status != PSA_SUCCESS ) { + return psa_status; + } + } else { + init_cache(); + } + } else { + init_cache(); + } +#else + init_cache(); +#endif + } + + for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; ++i ) { + if (!lookup_cache(nvm3_object_id)) { + // dont exist + if (lookup_tomb(nvm3_object_id)) { + // tombstone + if (tmp_id == 0 ) { + // mark first empty space + tmp_id = nvm3_object_id; + } + nvm3_object_id = increment_obj_id(nvm3_object_id); + continue; + } else { + // empty space + if (find_empty_slot) { + if (tmp_id != 0) { + *output_nvm3_id = tmp_id; + return PSA_SUCCESS; + } + *output_nvm3_id = nvm3_object_id; + return PSA_SUCCESS; + } else { + return PSA_ERROR_DOES_NOT_EXIST; + } + } + } + status = get_file_metadata(nvm3_object_id, its_file_meta, its_file_offset, + its_file_size); + + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER + || status == ECODE_NVM3_ERR_READ_DATA_SIZE) { + // we don't expect any other data in our range then PSA ITS files. + // delete the file if the magic doesn't match or the object on disk + // is too small to even have full metadata. + status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_DOES_NOT_EXIST; + } + } + + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + return PSA_ERROR_STORAGE_FAILURE; + } + + if (its_file_meta->uid != uid) { + nvm3_object_id = increment_obj_id(nvm3_object_id); + } else { + if (find_empty_slot) { + if (its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_PERMITTED; + } + } +#if defined(SLI_PSA_ITS_ENCRYPTED) + // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. + // Note that this can potentially induce a significant performance hit. + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_storage_uid_t authenticated_uid = 0; + psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + if (authenticated_uid != uid) { + return PSA_ERROR_INVALID_SIGNATURE; + } +#endif + *output_nvm3_id = nvm3_object_id; + return PSA_SUCCESS; + } + } + if (find_empty_slot) { + if (tmp_id != 0) { + *output_nvm3_id = tmp_id; + return PSA_SUCCESS; + } + } + return PSA_ERROR_DOES_NOT_EXIST; +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static inline void cache_session_key(uint8_t *session_key, psa_storage_uid_t uid) +{ + // Cache the session key + memcpy(g_cached_session_key.data, session_key, sizeof(g_cached_session_key.data)); + g_cached_session_key.uid = uid; + g_cached_session_key.active = true; +} + +/** + * \brief Derive a session key for ITS file encryption from the initialized root key and provided IV. + * + * \param[in] iv Pointer to array containing the initialization vector to be used in the key derivation. + * \param[in] iv_size Size of the IV buffer in bytes. Must be 12 bytes (AES-GCM IV size). + * \param[out] session_key Pointer to array where derived session key shall be stored. + * \param[out] session_key_size Size of the derived session key output array. Must be at least 32 bytes (AES-256 key size). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because iv or session_key is NULL, or their sizes are incorrect. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t derive_session_key(uint8_t *iv, size_t iv_size, uint8_t *session_key, size_t session_key_size) +{ + if (iv == NULL + || iv_size != AES_GCM_IV_SIZE + || session_key == NULL + || session_key_size < SESSION_KEY_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + +#if defined(SEMAILBOX_PRESENT) + // For HSE devices, use the builtin TrustZone Root Key + psa_set_key_id(&attributes, SL_SE_BUILTIN_KEY_TRUSTZONE_ID); + + psa_key_lifetime_t reported_lifetime; + psa_drv_slot_number_t reported_slot; + status = mbedtls_psa_platform_get_builtin_key(psa_get_key_id(&attributes), + &reported_lifetime, + &reported_slot); + + if (status != PSA_SUCCESS) { + return status; + } + + psa_set_key_lifetime(&attributes, reported_lifetime); + + uint8_t key_buffer[sizeof(sli_se_opaque_key_context_header_t)]; + size_t key_buffer_size; + status = sli_se_opaque_get_builtin_key(reported_slot, + &attributes, + key_buffer, + sizeof(key_buffer), + &key_buffer_size); + if (status != PSA_SUCCESS) { + return status; + } +#else // defined(SEMAILBOX_PRESENT) + // For VSE devices, use the previously initialized root key + if (!g_root_key.initialized) { + return PSA_ERROR_BAD_STATE; + } + + // Prepare root key attributes + psa_set_key_algorithm(&attributes, PSA_ALG_CMAC); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, ROOT_KEY_SIZE * 8); + + // Point the key buffer to the global root key + uint8_t *key_buffer = (uint8_t*)g_root_key.data; + size_t key_buffer_size = sizeof(g_root_key.data); +#endif // defined(SEMAILBOX_PRESENT) + + // Use CMAC as a key derivation function + size_t session_key_length; + status = psa_driver_wrapper_mac_compute( + &attributes, + key_buffer, + key_buffer_size, + PSA_ALG_CMAC, + iv, + iv_size, + session_key, + session_key_size, + &session_key_length); + + // Verify that the key derivation was successful before transferring the key to the caller + if (status != PSA_SUCCESS || session_key_length != SESSION_KEY_SIZE) { + memset(session_key, 0, session_key_size); + return PSA_ERROR_HARDWARE_FAILURE; + } + + return status; +} + +/** + * \brief Encrypt and authenticate ITS data with AES-128-GCM, storing the result in an encrypted blob. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. + * \param[in] plaintext Pointer to array containing data to be encrypted. + * \param[in] plaintext_size Size of provided plaintext data array. + * \param[out] blob Pointer to array where the resulting encrypted blob shall be placed. + * \param[in] blob_size Size of the output array. Must be at least as big as plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + * \param[out] blob_length Resulting size of the output blob. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +psa_status_t sli_encrypt_its_file(sli_its_file_meta_v2_t *metadata, + uint8_t *plaintext, + size_t plaintext_size, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + size_t *blob_length) +{ + if (metadata == NULL + || (plaintext == NULL && plaintext_size > 0) + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || blob_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Generate IV + size_t iv_length = 0; + psa_status_t psa_status = mbedtls_psa_external_get_random(NULL, blob->iv, AES_GCM_IV_SIZE, &iv_length); + + if (psa_status != PSA_SUCCESS || iv_length != AES_GCM_IV_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Prepare encryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + uint8_t session_key[SESSION_KEY_SIZE]; + psa_status = derive_session_key(blob->iv, AES_GCM_IV_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + cache_session_key(session_key, metadata->uid); + + // Retrieve data to be encrypted + if (plaintext_size != 0U) { + memcpy(blob->data, ((uint8_t*)plaintext), plaintext_size); + } + + // Encrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_encrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size, + blob->data, plaintext_size + AES_GCM_MAC_SIZE, // output == input for in-place encryption + &output_length); + + // Clear the local session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + if (psa_status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (output_length != plaintext_size + AES_GCM_MAC_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *blob_length = output_length + AES_GCM_IV_SIZE; + + return PSA_SUCCESS; +} + +/** + * \brief Decrypt and authenticate encrypted ITS data. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. Must be identical to the metadata used during encryption. + * \param[in] blob Encrypted blob containing data to be decrypted. + * \param[in] blob_size Size of the encrypted blob in bytes. + * \param[out] plaintext Pointer to array where the decrypted plaintext shall be placed. + * \param[in] plaintext_size Size of the plaintext array. Must be equal to sizeof(blob->data) - AES_GCM_MAC_SIZE. + * \param[out] plaintext_length Resulting length of the decrypted plaintext. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t sli_decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + if (metadata == NULL + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || (plaintext == NULL && plaintext_size > 0) + || plaintext_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Prepare decryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t session_key[SESSION_KEY_SIZE]; + + if (g_cached_session_key.active && g_cached_session_key.uid == metadata->uid) { + // Use cached session key if it's already set and UID matches + memcpy(session_key, g_cached_session_key.data, sizeof(session_key)); + } else { + psa_status = derive_session_key(blob->iv, AES_GCM_IV_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + cache_session_key(session_key, metadata->uid); + } + + // Decrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_decrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size + AES_GCM_MAC_SIZE, + plaintext, plaintext_size, + &output_length); + + // Clear the session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + // Invalid signature likely means that NVM data was tampered with + if (psa_status == PSA_ERROR_INVALID_SIGNATURE) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + if (psa_status != PSA_SUCCESS + || output_length != plaintext_size) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = output_length; + + return PSA_SUCCESS; +} + +/** + * \brief Authenticate encrypted ITS data and return the UID of the ITS file that was authenticated. + * + * \details NOTE: This function will run sli_decrypt_its_file() internally. The difference from the sli_decrypt_its_file() + * function is that authenticate_its_file() reads the NVM3 data, decrypts it in order to authenticate the + * stored data, and then discards the plaintext. This is needed since PSA Crypto doesn't support the + * GMAC primitive directly, which means we have to run a full GCM decrypt for authentication. + * + * \param[in] nvm3_object_id The NVM3 id corresponding to the stored ITS file. + * \param[out] authenticated_uid UID for the authenticated ITS file. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t *its_file_meta = NULL; + sli_its_encrypted_blob_t *blob = NULL; + + uint32_t obj_type; + size_t its_file_size = 0; + Ecode_t status = nvm3_getObjectInfo(nvm3_defaultHandle, + nvm3_object_id, + &obj_type, + &its_file_size); + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_STORAGE_FAILURE; + } + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size); + + status = nvm3_readData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto cleanup; + } + + its_file_meta = (sli_its_file_meta_v2_t*)its_file_buffer; + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Decrypt and authenticate blob + size_t plaintext_length; + psa_status = sli_decrypt_its_file(its_file_meta, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + blob->data, + its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + goto cleanup; + } + + if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto cleanup; + } + + if (authenticated_uid != NULL) { + *authenticated_uid = its_file_meta->uid; + } + + psa_status = PSA_SUCCESS; + + cleanup: + + // Discard output, as we're only interested in whether the authentication check passed or not. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + + return psa_status; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Global function definitions + +/** + * \brief create a new or modify an existing uid/value pair + * + * \param[in] uid the identifier for the data + * \param[in] data_length The size in bytes of the data in `p_data` + * \param[in] p_data A buffer containing the data + * \param[in] create_flags The flags that the data will be stored with + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid + * \retval PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + * \retval PSA_ERROR_INVALID_SIGNATURE The operation failed because the provided `uid` doesnt match the autenticated uid from the storage + */ +psa_status_t psa_its_set(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags) +{ + if ((data_length != 0U) && (p_data == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if ((data_length > NVM3_MAX_OBJECT_SIZE)) { + return PSA_ERROR_STORAGE_FAILURE; + } + + if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE + && create_flags != PSA_STORAGE_FLAG_NONE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) + && (!object_lives_in_s(p_data, data_length))) { + // The flag indicates that this data should not be set by the non-secure domain + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif + + Ecode_t status; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t* its_file_meta; + nvm3_ObjectKey_t nvm3_object_id = 0; +#if defined(SLI_PSA_ITS_ENCRYPTED) + sli_its_encrypted_blob_t *blob = NULL; + size_t its_file_size = data_length + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; + size_t blob_length = 0u; +#else + size_t its_file_size = data_length; +#endif + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + its_file_meta = (sli_its_file_meta_v2_t *)its_file_buffer; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, true, its_file_meta, NULL, NULL, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + if (psa_status == PSA_ERROR_DOES_NOT_EXIST) { + psa_status = PSA_ERROR_INSUFFICIENT_STORAGE; + } + goto exit; + } + + its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V2; + its_file_meta->uid = uid; + its_file_meta->flags = create_flags; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Everything after the the file metadata will make up the encrypted & authenticated blob + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Encrypt and authenticate the provided data + psa_status = sli_encrypt_its_file(its_file_meta, + (uint8_t*)p_data, + data_length, + blob, + its_file_size, + &blob_length); + + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (blob_length != its_file_size) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + +#else + if (data_length != 0U) { + memcpy(its_file_buffer + sizeof(sli_its_file_meta_v2_t), ((uint8_t*)p_data), data_length); + } +#endif + + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + set_cache(nvm3_object_id); + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + sli_its_release_mutex(); + return psa_status; +} + +/** + * \brief Retrieve the value associated with a provided uid + * + * \param[in] uid The uid value + * \param[in] data_offset The starting offset of the data requested + * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) + * \param[out] p_data The buffer where the data will be placed upon successful completion + * \param[out] p_data_length The amount of data returned in the p_data buffer + * + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage + * \retval PSA_ERROR_BUFFER_TOO_SMALL The operation failed because the data associated with provided uid is larger than `data_size` + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) + * is invalid. For example is `NULL` or references memory the caller cannot access. + * In addition, this can also happen if an invalid offset was provided. + */ +psa_status_t psa_its_get(psa_storage_uid_t uid, + uint32_t data_offset, + uint32_t data_length, + void *p_data, + size_t *p_data_length) +{ + if ((data_length != 0U) && (p_data_length == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (data_length != 0U) { + // If the request amount of data is 0, allow invalid pointer of the output buffer. + if ((p_data == NULL) + || ((uint32_t)p_data < SRAM_BASE) + || ((uint32_t)p_data > (SRAM_BASE + SRAM_SIZE - data_length))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + size_t plaintext_length; + sli_its_encrypted_blob_t *blob = NULL; +#endif + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0u; + size_t its_file_data_size = 0u; + size_t its_file_offset = 0u; + nvm3_ObjectKey_t nvm3_object_id; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + goto exit; + } +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE + && !object_lives_in_s(p_data, data_length)) { + // The flag indicates that this data should not be read back to the non-secure domain + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Subtract IV and MAC from ITS file as the below checks concern the actual data size + its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + its_file_data_size = its_file_size; +#endif + + if (data_length != 0U) { + if ((data_offset >= its_file_data_size) && (its_file_data_size != 0U)) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if ((its_file_data_size == 0U) && (data_offset != 0U)) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } else { + // Allow the offset at the data size boundary if the requested amount of data is zero. + if (data_offset > its_file_data_size) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } + + if (data_length > (its_file_data_size - data_offset)) { + *p_data_length = its_file_data_size - data_offset; + } else { + *p_data_length = data_length; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // its_file_size includes size of sli_its_encrypted_blob_t struct + blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); + if (blob == NULL) { + psa_status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + memset(blob, 0, its_file_size); + + status = nvm3_readPartialData(nvm3_defaultHandle, + nvm3_object_id, + blob, + its_file_offset, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + // Decrypt and authenticate blob + psa_status = sli_decrypt_its_file(&its_file_meta, + blob, + its_file_size, + blob->data, + its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + + // Verify that the requested UID is equal to the retrieved and authenticated UID + if (uid != its_file_meta.uid) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if (*p_data_length > 0) { + memcpy(p_data, blob->data + data_offset, *p_data_length); + } + psa_status = PSA_SUCCESS; + + exit: + if (blob != NULL) { + memset(blob, 0, its_file_size); + mbedtls_free(blob); + } + sli_its_release_mutex(); +#else + // If no encryption is used, just read out the data and write it directly to the output buffer + status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, its_file_offset + data_offset, *p_data_length); + + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } else { + psa_status = PSA_SUCCESS; + } + + exit: + sli_its_release_mutex(); +#endif + + return psa_status; +} + +/** + * \brief Retrieve the metadata about the provided uid + * + * \param[in] uid The uid value + * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the stored metadata failed. + */ +psa_status_t psa_its_get_info(psa_storage_uid_t uid, + struct psa_storage_info_t *p_info) +{ + if (p_info == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + nvm3_ObjectKey_t nvm3_object_id; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + sli_its_release_mutex(); + return psa_status; + } + + p_info->flags = its_file_meta.flags; + p_info->size = its_file_size; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Remove IV and MAC size from file size + p_info->size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#endif + sli_its_release_mutex(); + return PSA_SUCCESS; +} + +/** + * \brief Remove the provided key and its associated data from the storage + * + * \param[in] uid The uid value + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + */ +psa_status_t psa_its_remove(psa_storage_uid_t uid) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + nvm3_ObjectKey_t nvm3_object_id; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) +#endif + ) { + psa_status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } + status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + clear_cache(nvm3_object_id); + set_tomb(nvm3_object_id); + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + sli_its_release_mutex(); + return psa_status; +} + +// ------------------------------------- +// Silicon Labs extensions + +static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) +{ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + /* Encode the owner in the upper 32 bits. This means that if + * owner values are nonzero (as they are on a PSA platform), + * no key file will ever have a value less than 0x100000000, so + * the whole range 0..0xffffffff is available for non-key files. */ + uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); + return ((uint64_t) unsigned_owner_id << 32) | MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); +#else + /* Use the key id directly as a file name. + * psa_is_key_id_valid() in psa_crypto_slot_management.c + * is responsible for ensuring that key identifiers do not have a + * value that is reserved for non-key files. */ + return key; +#endif +} + +psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, + mbedtls_svc_key_id_t new_id) +{ + psa_storage_uid_t old_uid = psa_its_identifier_of_slot(old_id); + psa_storage_uid_t new_uid = psa_its_identifier_of_slot(new_id); + size_t its_file_size = 0; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + if (old_id == new_id) { + return PSA_SUCCESS; + } + // Check whether the key to migrate exists on disk + struct psa_storage_info_t p_info; + status = psa_its_get_info(old_uid, &p_info); + if (status != PSA_SUCCESS) { + return status; + } + + // Allocate temporary buffer and cast it to the metadata format + uint8_t *its_file_buffer = mbedtls_calloc(1, p_info.size); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + // Read contents of pre-existing key into the temporary buffer + status = psa_its_get(old_uid, 0, p_info.size, its_file_buffer, + &its_file_size); + + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_its_set(new_uid, its_file_size, its_file_buffer, + p_info.flags); + + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_its_remove(old_uid); + + if (status != PSA_SUCCESS) { + goto exit; + } + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + return status; +} + +/** + * \brief Check if the ITS encryption is enabled + */ +psa_status_t sli_psa_its_encrypted(void) +{ +#if defined(SLI_PSA_ITS_ENCRYPTED) + return PSA_SUCCESS; +#else + return PSA_ERROR_NOT_SUPPORTED; +#endif +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) +/** + * \brief Set the root key to be used when deriving session keys for ITS encryption. + * + * \param[in] root_key Buffer containing the root key. + * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The key was successfully set. + * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. + * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. + */ +psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size) +{ + // Check that arguments are valid + if (root_key == NULL || root_key_size != sizeof(g_root_key.data)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check that the root key has not already been set + // (This is possibly too restrictive. For TrustZone usage this can be enforced by + // not exposing the function to NS instead.) + if (g_root_key.initialized) { + return PSA_ERROR_ALREADY_EXISTS; + } + + // Store the provided root key and mark it as initialized + memcpy(g_root_key.data, root_key, sizeof(g_root_key.data)); + g_root_key.initialized = true; + + return PSA_SUCCESS; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) +#endif // (!SL_PSA_ITS_SUPPORT_V3_DRIVER) +#endif // MBEDTLS_PSA_CRYPTO_STORAGE_C && !MBEDTLS_PSA_ITS_FILE_C diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_key_derivation.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_key_derivation.c new file mode 100644 index 000000000..54500723a --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_key_derivation.c @@ -0,0 +1,304 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver Key Derivation functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#include "psa/crypto.h" +#include "sli_mbedtls_omnipresent.h" +#include "sli_cryptoacc_opaque_types.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +#include "cryptolib_def.h" +#include "sx_errors.h" +#include "sx_aes.h" + +#include + +// ----------------------------------------------------------------------------- +// Defines + +#if defined(SLI_PSA_DRIVER_FEATURE_PBKDF2) +#define PBKDF2_COUNTER_ENCODING_SIZE (4u) + +// ----------------------------------------------------------------------------- +// Static helper functions + +/// @brief +/// Converting a value to a big endian octet string. +static void uint32_to_octet_string(uint32_t value, uint8_t buffer[4]) +{ + for (uint8_t i = 0; i < 4; i++) { + buffer[i] = (uint8_t)((value >> (8 * (3 - i))) & 0xFF); + } +} + +/// @brief +/// XOR the data pointed to by the two input blocks (of len 16 B). Result is +/// stored in dk. +/// +/// @note +/// This function assumes that both block_t:s point to word-aligned addresses. +static void xorbuf(block_t dk, block_t u) +{ + for (uint32_t i = 0; i < u.len; i += 4) { + *(uint32_t*)((uint32_t)dk.addr + i) ^= *(uint32_t*)((uint32_t)u.addr + i); + } +} + +// ----------------------------------------------------------------------------- +// Custom implementation of PBKDF2 using AES-CMAC-128-PRF + +/// @brief +/// Perform the PBKDF2 algorithm with AES-CMAC-128-PRF. +static psa_status_t derive_key_pbkdf2_aes_cmac_128_prf( + block_t *password, + block_t *salt, + uint32_t iterations, + uint32_t derived_key_length, + block_t *derived_key) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + // Buffers for storing temporary/partial results of the operation. + uint8_t temp_buf_1[AES_MAC_SIZE]; + block_t temp_blk_1 = block_t_convert(temp_buf_1, AES_MAC_SIZE); + uint8_t temp_buf_2[AES_MAC_SIZE]; + block_t temp_blk_2 = block_t_convert(temp_buf_2, AES_MAC_SIZE); + + // Make sure that we can handle the length of the salt input. + if (salt->len > DERIV_MAX_SALT_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Make sure that the output key length is sufficient. + if (derived_key->len < derived_key_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Buffer for appending the iteration counter to the input salt before + // applying the PRF. + uint8_t internal_data_buf[DERIV_MAX_SALT_SIZE + PBKDF2_COUNTER_ENCODING_SIZE] + = { 0 }; + block_t internal_data_blk = + block_t_convert(internal_data_buf, + salt->len + PBKDF2_COUNTER_ENCODING_SIZE); + + uint8_t *counter_encoding = &internal_data_buf[salt->len]; + + // Read the user provided salt into our internal buffer. + memcpy(internal_data_buf, salt->addr, salt->len); + + // It is possible that the password provided is not of the expected size for + // AES-128. In those cases, we will have to expand the password to 16 bytes; + // this is done as described in RFC4615. + uint8_t internal_password_buf[AES_KEYSIZE_128] = { 0 }; + if (password->len != AES_KEYSIZE_128) { + block_t internal_password_blk = + block_t_convert(internal_password_buf, sizeof(internal_password_buf)); + // Acquire hardware lock and execute CMAC operation + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + uint32_t sx_ret = sx_aes_cmac_generate(&internal_password_blk, + password, + &internal_password_blk); + status = cryptoacc_management_release(); + if (status != PSA_SUCCESS) { + return status; + } + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + *password = internal_password_blk; + } + + uint32_t output_key_length = 0; + uint32_t i = 1; + while (output_key_length < derived_key_length) { + // Encode counter value. + uint32_to_octet_string(i, counter_encoding); + + // First Block (U_1). + // Acquire hardware lock and execute CMAC operation + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + uint32_t sx_ret = sx_aes_cmac_generate(password, + &internal_data_blk, + &temp_blk_1); + status = cryptoacc_management_release(); + if (status != PSA_SUCCESS) { + return status; + } + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + memcpy(temp_blk_2.addr, temp_blk_1.addr, AES_MAC_SIZE); + + // Remaining blocks (U_j). + for (uint32_t j = 1; j < iterations; j++) { + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_cmac_generate(password, &temp_blk_1, &temp_blk_1); + status = cryptoacc_management_release(); + if (status != PSA_SUCCESS) { + return status; + } + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + xorbuf(temp_blk_2, temp_blk_1); + } + + uint32_t partial_output_length = + (derived_key_length - output_key_length >= AES_MAC_SIZE) + ? (AES_MAC_SIZE) : (derived_key_length - output_key_length); + + output_key_length += partial_output_length; + + memcpy(derived_key->addr, temp_blk_2.addr, partial_output_length); + derived_key->len -= partial_output_length; + if (!(derived_key->flags & BLOCK_S_CONST_ADDR)) { + derived_key->addr += partial_output_length; + } + + i += 1; + } + + return PSA_SUCCESS; +} + +psa_status_t sli_cryptoacc_driver_single_shot_pbkdf2( + psa_algorithm_t alg, + const psa_key_attributes_t *key_in_attributes, + const uint8_t *key_in_buffer, + size_t key_in_buffer_size, + const uint8_t* salt, + size_t salt_length, + const psa_key_attributes_t *key_out_attributes, + uint32_t iterations, + uint8_t *key_out_buffer, + size_t key_out_buffer_size) +{ + if (key_in_buffer == NULL + || key_in_attributes == NULL + || salt == NULL + || key_out_attributes == NULL + || key_out_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + size_t key_out_size = PSA_BITS_TO_BYTES(psa_get_key_bits(key_out_attributes)); + psa_status_t psa_status = PSA_ERROR_NOT_SUPPORTED; + + if (key_out_buffer_size < key_out_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (iterations == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_lifetime_t lifetime = psa_get_key_lifetime(key_in_attributes); + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(lifetime); + block_t key_block = NULL_blk; + + switch (location) { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + { +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + if (PSA_KEY_TYPE_IS_ECC(psa_get_key_type(key_in_attributes))) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#endif // SLI_PSA_DRIVER_FEATURE_ECC + + key_block = block_t_convert(key_in_buffer, key_in_buffer_size); + break; + } + +#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE: + { + if (key_in_buffer_size < sizeof(sli_cryptoacc_opaque_key_context_t)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // The only opaque key that is currently supported is the PUF key + sli_cryptoacc_opaque_key_context_t *key_context = + (sli_cryptoacc_opaque_key_context_t *)key_in_buffer; + if (key_context->builtin_key_id != 0) { + switch (key_context->builtin_key_id) { + case SLI_CRYPTOACC_BUILTIN_KEY_PUF_SLOT: + // Using this key block as input will make the AES engine use the PUF- + // derived key for the operation. + // Make sure that the attributes and so on match our expectations + if (psa_get_key_bits(key_in_attributes) != 256) { + return PSA_ERROR_INVALID_ARGUMENT; + } + key_block = AES_KEY1_256; + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + + break; + } +#endif // SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + + default: + return PSA_ERROR_DOES_NOT_EXIST; + } + + switch (alg) { + case PSA_ALG_PBKDF2_AES_CMAC_PRF_128: + { + #define AES_CMAC_PRF_128_BLOCK_SIZE 128 + // The out key length can atmost be 128 bits long. + if ( !key_out_size || (key_out_size > PSA_BITS_TO_BYTES(AES_CMAC_PRF_128_BLOCK_SIZE)) ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + block_t salt_block = block_t_convert(salt, salt_length); + block_t key_out_block = block_t_convert(key_out_buffer, key_out_buffer_size); + psa_status = derive_key_pbkdf2_aes_cmac_128_prf(&key_block, &salt_block, iterations, key_out_size, &key_out_block); + break; + } + default: + psa_status = PSA_ERROR_NOT_SUPPORTED; + } + return psa_status; +} + +#endif // defined(SLI_PSA_DRIVER_FEATURE_PBKDF2) diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c new file mode 100644 index 000000000..472597719 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c @@ -0,0 +1,434 @@ +/******************************************************************************* + * @file + * @brief Driver for TRNG randomness generation through the TRNG peripheral on + VSE devices. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "cryptoacc_management.h" +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_errors.h" +#include "cryptolib_types.h" +#include "sx_trng.h" +#include "sx_rng.h" +#include "sx_memcpy.h" +#include "ba431_config.h" + +#include "sl_assert.h" +#include "em_device.h" + +#if (SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP) + #include "sl_component_catalog.h" + #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + #include "sl_power_manager.h" + #else + #error "The 'Power Manager' component must be included in the project" + #endif // SL_CATALOG_POWER_MANAGER_PRESENT +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +//------------------------------------------------------------------------------ +// Defines + +// Perform the TRNG conditioning test on startup. +#define DO_TRNG_COND_TEST (1) + +// Allow performing a few retries before determining that the TRNG is in a +// seriously bad state and cannot be initialized properly. +#define MAX_INITIALIZATION_ATTEMPTS (4) + +// Magic word written to the random data buffer in RAM. Used as a basic sanity +// check to make sure that the data actually has been retained during sleep. +#define BUFFERED_RANDOMNESS_MAGIC_WORD (0xF55E0830) + +//------------------------------------------------------------------------------ +// Forward Declarations + +static void cryptoacc_trng_get_random_wrapper(void *unused_state, + block_t output); + +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +static void store_trng_fifo_data(sl_power_manager_em_t from, + sl_power_manager_em_t to); + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +//------------------------------------------------------------------------------ +// Static Constants + +static const block_t trng_fifo_block = { + .addr = (uint8_t *)ADDR_BA431_FIFO, + .len = 0, + .flags = BLOCK_S_CONST_ADDR, +}; + +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +static const sl_power_manager_em_transition_event_info_t buffer_trng_data_event = { + .event_mask = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 + | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3, + .on_event = store_trng_fifo_data, +}; + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +//------------------------------------------------------------------------------ +// Global Constants + +const struct sx_rng sli_cryptoacc_trng_wrapper = { + .param = NULL, + .get_rand_blk = cryptoacc_trng_get_random_wrapper, +}; + +//------------------------------------------------------------------------------ +// Static Variables + +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +static sl_power_manager_em_transition_event_handle_t buffer_trng_handle = { 0 }; + +// Keep all of the buffered randomness in the .bss section. Powering down the +// RAM bank containing this section would be a clear user error. We prefer to +// not use the heap for this data since the heap section expands (based on the +// linkerfile) into RAM banks that technically would be OK to power down. +static uint32_t buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP + 1] + = { 0 }; +static size_t n_buffered_random_bytes = 0; + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +//------------------------------------------------------------------------------ +// Static Function Definitions + +#if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +/* + * \brief + * Callback function for buffering all bytes currently in the TRNG FIFO. + * + * \details + * Will be called by the Power Manager on EM2/EM3 entry. Before this function + * returns, it will unsubscribe to the Power Manager event that caused it to + * trigger. + * + * \attention + * This function will disable the TRNG (NDRBG). + */ +static void store_trng_fifo_data(sl_power_manager_em_t from, + sl_power_manager_em_t to) +{ + (void)to; + (void)from; + + // It should be safe to assume that the CRYPTOACC resource won't be acquired + // by anyone when we're entering EM2/EM2. + if (cryptoacc_management_acquire() != PSA_SUCCESS) { + return; + } + + // We don't want the TRNG to start refilling the FIFO after we've read all of + // the remaining data (since we'll necessarily go below the refill threshold). + ba431_disable_ndrng(); + + block_t buffered_randomness_block = + block_t_convert(buffered_randomness, + SX_MIN(sizeof(uint32_t) * ba431_read_fifolevel(), + SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP * sizeof(uint32_t))); + + memcpy_blk(buffered_randomness_block, + trng_fifo_block, + buffered_randomness_block.len); + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return; + } + + n_buffered_random_bytes = buffered_randomness_block.len; + + // Write a magic word to the end of the RAM buffer. This will be checked + // before the buffered data is used, as a basic sanity check that the data was + // actually retained in EM2/EM3. + buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP] + = BUFFERED_RANDOMNESS_MAGIC_WORD; + + // We are no longer interested in knowing if the device goes to sleep now that + // we have buffered the TRNG data. + sl_power_manager_unsubscribe_em_transition_event(&buffer_trng_handle); +} + +#endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + +static psa_status_t wait_until_trng_is_ready_for_sleep(void) +{ + // We do not want to risk clocking down the CRYPTOACC while the ring + // oscillators are still spinning, since that means that they will not be + // shut down (unless EM2 or lower is entered). + uint32_t current_trng_status = BA431_STATE_RESET; + while (((current_trng_status = ba431_read_status()) & BA431_STAT_MASK_STATE) + != BA431_STATE_FIFOFULLOFF) { + switch (current_trng_status & BA431_STAT_MASK_STATE) { + case BA431_STATE_STARTUP: + case BA431_STATE_RUNNING: + case BA431_STATE_FIFOFULLON: + // These are the only valid states that we would expect the TRNG to be + // in now that we have read randomness from it. + break; + default: + return PSA_ERROR_HARDWARE_FAILURE; + break; + } + } + + // Make sure that no new alarms have been triggered while the FIFO was being + // filled. All other (more serious) continous test failures will result in the + // TRNG control finite state machine moving to the error state: meaning that + // we would have already returned in the switch statement above. + if (current_trng_status & BA431_STAT_MASK_PREALM_INT) { + // The severity of a preliminary noise alarm is lower than other alarms that + // will put the TRNG in an error state. Instead of (potentially) triggering + // a system reset, we will make sure to disable the TRNG such that it needs + // to be re-initialized before the next use: that will cause startup tests + // to run again. + ba431_disable_ndrng(); + } + + return PSA_SUCCESS; +} + +static psa_status_t wait_until_trng_has_started(void) +{ + uint32_t ba431_status = 0; + ba431_state_t ba431_state = BA431_STATE_RESET; + + // Poll the status until the startup routine has finished. + do { + ba431_status = ba431_read_status(); + ba431_state = (ba431_state_t) (ba431_status & BA431_STAT_MASK_STATE); + } while ((ba431_state == BA431_STATE_RESET) + || (ba431_state == BA431_STATE_STARTUP)); + + // Make sure that the NIST-800-90B startup test passed (the fact that we have + // left the startup state means that the corresponding AIS31 test also + // passed). + if (ba431_status & BA431_STAT_MASK_STARTUP_FAIL) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // This would have been caught by the above startup failure check. + EFM_ASSERT(ba431_state != BA431_STATE_ERROR); + + return PSA_SUCCESS; +} + +static psa_status_t initialize_trng(void) +{ + size_t attempts_remaining = MAX_INITIALIZATION_ATTEMPTS; + + while (attempts_remaining--) { + if (sx_trng_init(DO_TRNG_COND_TEST) != CRYPTOLIB_SUCCESS) { + continue; + } + + // The implementation of sx_trng_get_rand_blk() doesn't actually assert + // that the startup check passed successfully (only that the TRNG is no + // longer in a reset- or startup state). Therefore, we will implement our + // own functions for waiting until the startup has completed and then + // getting randomness from the TRNG FIFO. + if (wait_until_trng_has_started() != PSA_SUCCESS) { + continue; + } + + // When we reach this point, the TRNG has started successfully and is ready + // to be used. + return PSA_SUCCESS; + } + + // If we against all odds reach this point, we have not been able to + // initialize the TRNG even after multiple retries. + return PSA_ERROR_HARDWARE_FAILURE; +} + +static bool trng_needs_initialization(void) +{ + // If the TRNG (NDRNG) is not enabled, it most definitely is not initialized. + if ((ba431_read_controlreg() & BA431_CTRL_NDRNG_ENABLE) == 0u) { + return true; + } + + // If a full word of the conditioning (whitening) key is all zero, it probably + // hasn't been initialized properly. + uint32_t cond_key[4] = { 0 }; + ba431_read_conditioning_key(cond_key); + if ((cond_key[0] == 0) + || (cond_key[1] == 0) + || (cond_key[2] == 0) + || (cond_key[3] == 0)) { + return true; + } + + // No conditions were met, which means that the TRNG must have already been + // initialized. + return false; +} + +static psa_status_t cryptoacc_trng_get_random(block_t output) +{ + EFM_ASSERT(!(output.flags & BLOCK_S_CONST_ADDR)); + + #if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + // Service as much of the request as possible from the already collected + // randomness which was buffered when EM2/EM3 was entered previously. + if ((n_buffered_random_bytes > 0) + && (buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP] + == BUFFERED_RANDOMNESS_MAGIC_WORD)) { + block_t chunk_block = block_t_convert(output.addr, + SX_MIN(output.len, + n_buffered_random_bytes)); + uint8_t *start_of_unused_randomness + = (uint8_t *)buffered_randomness + + SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP * sizeof(uint32_t) + - n_buffered_random_bytes; + block_t buffered_randomness_block = + block_t_convert(start_of_unused_randomness, n_buffered_random_bytes); + memcpy_blk(chunk_block, buffered_randomness_block, chunk_block.len); + + n_buffered_random_bytes -= chunk_block.len; + output.len -= chunk_block.len; + output.addr += chunk_block.len; + + if (n_buffered_random_bytes == 0) { + // Remove the magic word from RAM. + buffered_randomness[SL_VSE_MAX_TRNG_WORDS_BUFFERED_DURING_SLEEP] = 0; + } + if (output.len == 0) { + return PSA_SUCCESS; + } + } + #endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + + if (trng_needs_initialization()) { + // In addition to configuring the TRNG, this function will also wait until + // the hardware is fully ready for usage. + psa_status_t status = initialize_trng(); + if (status != PSA_SUCCESS) { + return status; + } + + #if SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + // Now that we have initialized the TRNG, we know that its FIFO level will + // never go below the threshold level (outside of the duration of this + // function). In order to avoid wasting already generated random words, we + // will now register a callback function for storing randomness on EM2/EM3 + // entry. + sl_power_manager_subscribe_em_transition_event(&buffer_trng_handle, + &buffer_trng_data_event); + #endif // SL_VSE_BUFFER_TRNG_DATA_DURING_SLEEP + } + + size_t n_bytes_generated = 0; + while (n_bytes_generated < output.len) { + // Don't attempt to read more from the TRNG FIFO than the amount of random + // words that it currently holds. + block_t chunk_block = block_t_convert( + output.addr + n_bytes_generated, + SX_MIN(output.len - n_bytes_generated, + sizeof(uint32_t) * (ba431_read_fifolevel()))); + memcpy_blk(chunk_block, trng_fifo_block, chunk_block.len); + n_bytes_generated += chunk_block.len; + } + + // Potential bad states reached by the TRNG during the above randomness + // generation will be handled by this function. + psa_status_t status = wait_until_trng_is_ready_for_sleep(); + if (status != PSA_SUCCESS) { + return status; + } + + return PSA_SUCCESS; +} + +//------------------------------------------------------------------------------ +// Public Function Definitions + +/* + * \brief + * Wrapper function for getting random data from the TRNG. + * + * \details + * Even though it is declared with a static scope, a function pointer to this + * function will be exposed so that it is indirectly usable for other + * compilation units as well. + * + * \note + * This function does not assume any responsibility to acquire and release + * ownership of the CRYPTOACC peripheral. + * + * \warning + * This function is called from contexts where it is not possible to return an + * error code. Any errors are therefore handled by resetting the system. This + * is deemed appropriate since a failed randomness generation may have severe + * security implications. + */ +static void cryptoacc_trng_get_random_wrapper(void *unused_state, + block_t output) +{ + (void)unused_state; + + if (cryptoacc_trng_get_random(output) != PSA_SUCCESS) { + EFM_ASSERT(false); + sx_trng_apply_soft_reset(); + NVIC_SystemReset(); + } +} + +psa_status_t sli_cryptoacc_trng_get_random(unsigned char *output, size_t len) +{ + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + status = cryptoacc_trng_get_random(block_t_convert(output, len)); + if (status != PSA_SUCCESS) { + // Soft reset such that the next attempt (if the function is called again) + // is more likely to succeed. + sx_trng_apply_soft_reset(); + cryptoacc_management_release(); + return status; + } + + return cryptoacc_management_release(); +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_opaque_driver_builtin_keys.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_opaque_driver_builtin_keys.c new file mode 100644 index 000000000..4cc4ab509 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_opaque_driver_builtin_keys.c @@ -0,0 +1,115 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver Builtin key functions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#include "sl_psa_values.h" +#include +#include "mbedtls/platform.h" +#include "sli_cryptoacc_opaque_types.h" +#include + +#if defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) && defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + +psa_status_t sli_cryptoacc_opaque_get_builtin_key(psa_drv_slot_number_t slot_number, + psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length) +{ + sli_cryptoacc_opaque_key_context_t header = { 0 }; + + // Set key type and permissions according to key ID + switch (slot_number) { + case SLI_CRYPTOACC_BUILTIN_KEY_PUF_SLOT: + psa_set_key_bits(attributes, 256); + psa_set_key_type(attributes, PSA_KEY_TYPE_AES); + if (PSA_ALG_IS_KEY_DERIVATION(SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG)) { + psa_set_key_usage_flags(attributes, PSA_KEY_USAGE_DERIVE); + } else if (PSA_ALG_IS_MAC(SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG)) { + psa_set_key_usage_flags(attributes, (PSA_KEY_USAGE_SIGN_MESSAGE | PSA_KEY_USAGE_VERIFY_MESSAGE)); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + psa_set_key_algorithm(attributes, SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG); + break; + default: + return PSA_ERROR_DOES_NOT_EXIST; + } + + psa_set_key_lifetime(attributes, + PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( + PSA_KEY_PERSISTENCE_READ_ONLY, + PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE) ); + + // Check the key buffer size after populating the key attributes: + // From mbedTLS, psa-driver-interface.md (snippet): + // + // This entry point may return the following status values: + // (...) + // * PSA_ERROR_BUFFER_TOO_SMALL: key_buffer_size is insufficient. + // In this case, the driver must pass the key's attributes in + // *attributes. In particular, get_builtin_key(slot_number, + // &attributes, NULL, 0) is a way for the core to obtain the + // key's attributes. + if (key_buffer_size < sizeof(sli_cryptoacc_opaque_key_context_t)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + header.struct_version = SLI_CRYPTOACC_OPAQUE_KEY_CONTEXT_VERSION; + header.builtin_key_id = (uint8_t)slot_number; + + memcpy(key_buffer, &header, sizeof(sli_cryptoacc_opaque_key_context_t)); + *key_buffer_length = sizeof(sli_cryptoacc_opaque_key_context_t); + return PSA_SUCCESS; +} + +#if !defined(PSA_CRYPTO_DRIVER_TEST) +psa_status_t mbedtls_psa_platform_get_builtin_key( + mbedtls_svc_key_id_t key_id, + psa_key_lifetime_t *lifetime, + psa_drv_slot_number_t *slot_number) +{ + switch (MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key_id)) { + case SL_CRYPTOACC_BUILTIN_KEY_PUF_ID: + // Slot number is just the same as the key ID + *slot_number = SLI_CRYPTOACC_BUILTIN_KEY_PUF_SLOT; + break; + default: + return PSA_ERROR_DOES_NOT_EXIST; + } + *lifetime = PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( + PSA_KEY_PERSISTENCE_READ_ONLY, + PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE); + return PSA_SUCCESS; +} + +#endif // !PSA_CRYPTO_DRIVER_TEST + +#endif // SLI_PSA_DRIVER_FEATURE_PUF_KEY && MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_opaque_driver_mac.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_opaque_driver_mac.c new file mode 100644 index 000000000..6f8c081bb --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_opaque_driver_mac.c @@ -0,0 +1,150 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver Mac functions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) && defined(SEPUF_PRESENT) + +#include + +#include "sli_cryptoacc_opaque_types.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver common +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" +#include "psa/crypto_extra.h" +#include "cryptolib_def.h" +#include "sx_errors.h" +#include "sx_aes.h" + +psa_status_t sli_cryptoacc_opaque_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + if (key_buffer == NULL + || attributes == NULL + || mac == NULL + || mac_length == NULL + || ((input == NULL) && (input_length > 0))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (key_buffer_size < sizeof(sli_cryptoacc_opaque_key_context_t)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // The only opaque key that is currently supported is the PUF key + sli_cryptoacc_opaque_key_context_t *key_context = + (sli_cryptoacc_opaque_key_context_t *)key_buffer; + block_t key_block = NULL_blk; + switch (key_context->builtin_key_id) { + case SLI_CRYPTOACC_BUILTIN_KEY_PUF_SLOT: + // Using this key block as input will make the AES engine use the PUF- + // derived key for the operation. + // Make sure that the attributes and so on match our expectations + if (psa_get_key_bits(attributes) != 256) { + return PSA_ERROR_INVALID_ARGUMENT; + } + key_block = AES_KEY1_256; + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + + switch (alg) { + case PSA_ALG_CMAC: + { + // The builting key specifies PSA_ALG_CMAC without a truncated length. + // Therefore, we only support full size MAC output. + if (mac_size < BLK_CIPHER_MAC_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + uint8_t sx_mac_buf[BLK_CIPHER_MAC_SIZE]; + block_t input_block = block_t_convert(input, input_length); + block_t mac_block = block_t_convert(sx_mac_buf, sizeof(sx_mac_buf)); + + // Acquire hardware lock and execute CMAC operation + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + uint32_t sx_ret = sx_aes_cmac_generate(&key_block, + &input_block, + &mac_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS) { + status = PSA_ERROR_HARDWARE_FAILURE; + } + + // Output mac if operation is successful + if (status == PSA_SUCCESS) { + memcpy(mac, sx_mac_buf, BLK_CIPHER_MAC_SIZE); + *mac_length = BLK_CIPHER_MAC_SIZE; + } else { + *mac_length = 0; + } + memset(sx_mac_buf, 0, BLK_CIPHER_MAC_SIZE); + break; + } + default: + status = PSA_ERROR_NOT_SUPPORTED; + } + + return status; + +#else // MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS +} + +#endif // defined(CRYPTOACC_PRESENT) || defined(SEPUF_PRESENT) diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c new file mode 100644 index 000000000..932d95e17 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c @@ -0,0 +1,1836 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver AEAD functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver common +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" +#include "sx_aes.h" +#include "sx_errors.h" +#include "cryptolib_types.h" + +#include + +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + +static psa_status_t check_aead_parameters(const psa_key_attributes_t *attributes, + psa_algorithm_t alg, + size_t nonce_length, + size_t additional_data_length) +{ + size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (tag_length < 4 + || tag_length > 16 + || tag_length % 2 != 0 + || nonce_length < 7 + || nonce_length > 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + // AD are limited to 2^64 bits, so 2^61 bytes. + // We need not check if SIZE_MAX (max of size_t) is less than 2^61 (0x2000000000000000) +#if SIZE_MAX > 0x2000000000000000ull + if (additional_data_length >> 61 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } +#else // SIZE_MAX > 0x2000000000000000ull + (void) additional_data_length; +#endif // SIZE_MAX > 0x2000000000000000ull + if ((tag_length < 4) || (tag_length > 16)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (nonce_length == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } +#if !defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + if (nonce_length != AES_IV_GCM_SIZE) { + // Libcryptosoc only supports 12 bytes long IVs. + return PSA_ERROR_NOT_SUPPORTED; + } +#endif // ! SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; +#endif // PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } + +#if !defined(PSA_WANT_ALG_GCM) + (void) additional_data_length; +#endif // !PSA_WANT_ALG_GCM + + switch (psa_get_key_bits(attributes)) { + case 128: // fallthrough + case 192: // fallthrough + case 256: + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + +#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) && defined(PSA_WANT_ALG_GCM) +/* Do GCM in software in case the IV isn't 12 bytes, since that's the only + * thing the accelerator supports. */ +static psa_status_t sli_cryptoacc_software_gcm(const uint8_t* keybuf, + size_t key_length, + const uint8_t* nonce, + size_t nonce_length, + const uint8_t* additional_data, + size_t additional_data_length, + const uint8_t* input, + uint8_t* output, + size_t plaintext_length, + size_t tag_length, + uint8_t* tag, + bool encrypt_ndecrypt) +{ + // Step 1: calculate H = Ek(0) + uint8_t Ek[16] = { 0 }; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key = block_t_convert(keybuf, key_length); + block_t data_in = block_t_convert(Ek, sizeof(Ek)); + block_t data_out = block_t_convert(Ek, sizeof(Ek)); + + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ecb_encrypt(&key, + &data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Step 2: calculate IV = GHASH(H, {}, IV) + uint8_t iv[16] = { 0 }; + uint64_t HL[16], HH[16]; + + sli_psa_software_ghash_setup(Ek, HL, HH); + + for (size_t i = 0; i < nonce_length; i += 16) { + // Mix in IV + for (size_t j = 0; j < (nonce_length - i > 16 ? 16 : nonce_length - i); j++) { + iv[j] ^= nonce[i + j]; + } + // Update result + sli_psa_software_ghash_multiply(HL, HH, iv, iv); + } + + iv[12] ^= (nonce_length * 8) >> 24; + iv[13] ^= (nonce_length * 8) >> 16; + iv[14] ^= (nonce_length * 8) >> 8; + iv[15] ^= (nonce_length * 8) >> 0; + + sli_psa_software_ghash_multiply(HL, HH, iv, iv); + + // Step 3: Calculate first counter block for tag generation + uint8_t tagbuf[16] = { 0 }; + data_in = block_t_convert(iv, sizeof(iv)); + data_out = block_t_convert(tagbuf, sizeof(tagbuf)); + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ecb_encrypt(&key, + &data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // If we're decrypting, mix in the to-be-checked tag value before transforming + if (!encrypt_ndecrypt) { + for (size_t i = 0; i < tag_length; i++) { + tagbuf[i] ^= tag[i]; + } + } + + // Step 4: increment IV (ripple increment) + for (size_t i = 0; i < 16; i++) { + iv[15 - i]++; + + if (iv[15 - i] != 0) { + break; + } + } + + // Step 5: Accumulate additional data + memset(Ek, 0, sizeof(Ek)); + for (size_t i = 0; i < additional_data_length; i += 16) { + // Mix in additional data as much as we have + for (size_t j = 0; + j < (additional_data_length - i > 16 ? 16 : additional_data_length - i); + j++) { + Ek[j] ^= additional_data[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + + // Step 6: If we're decrypting, accumulate the ciphertext before it gets transformed + if (!encrypt_ndecrypt) { + for (size_t i = 0; i < plaintext_length; i += 16) { + // Mix in ciphertext + for (size_t j = 0; + j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); + j++) { + Ek[j] ^= input[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + } + + // Step 7: transform data using AES-CTR + if (plaintext_length) { + data_in = block_t_convert(input, plaintext_length); + data_out = block_t_convert(output, plaintext_length); + block_t nonce_internal = block_t_convert(iv, sizeof(iv)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ctr_encrypt(&key, + &data_in, + &data_out, + &nonce_internal); + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Step 8: If we're encrypting, accumulate the ciphertext now + if (encrypt_ndecrypt) { + for (size_t i = 0; i < plaintext_length; i += 16) { + // Mix in ciphertext + for (size_t j = 0; + j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); + j++) { + Ek[j] ^= output[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + } + + // Step 9: add len(A) || len(C) block to tag calculation + uint64_t bitlen = additional_data_length * 8; + Ek[0] ^= bitlen >> 56; + Ek[1] ^= bitlen >> 48; + Ek[2] ^= bitlen >> 40; + Ek[3] ^= bitlen >> 32; + Ek[4] ^= bitlen >> 24; + Ek[5] ^= bitlen >> 16; + Ek[6] ^= bitlen >> 8; + Ek[7] ^= bitlen >> 0; + + bitlen = plaintext_length * 8; + Ek[8] ^= bitlen >> 56; + Ek[9] ^= bitlen >> 48; + Ek[10] ^= bitlen >> 40; + Ek[11] ^= bitlen >> 32; + Ek[12] ^= bitlen >> 24; + Ek[13] ^= bitlen >> 16; + Ek[14] ^= bitlen >> 8; + Ek[15] ^= bitlen >> 0; + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + + // Step 10: calculate tag value + for (size_t i = 0; i < tag_length; i++) { + tagbuf[i] ^= Ek[i]; + } + + // Step 11: output tag for encrypt operation, check tag for decrypt + if (encrypt_ndecrypt) { + memcpy(tag, tagbuf, tag_length); + } else { + uint8_t accumulator = 0; + for (size_t i = 0; i < tag_length; i++) { + accumulator |= tagbuf[i]; + } + if (accumulator != 0) { + return PSA_ERROR_INVALID_SIGNATURE; + } + } + + return PSA_SUCCESS; +} +#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION && PSA_WANT_ALG_GCM + +psa_status_t sli_cryptoacc_transparent_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (ciphertext_size <= plaintext_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + size_t tag_length = 0; + psa_status_t psa_status = sli_cryptoacc_transparent_aead_encrypt_tag( + attributes, key_buffer, key_buffer_size, alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, plaintext_length, ciphertext_length, + &ciphertext[plaintext_length], ciphertext_size - plaintext_length, &tag_length); + + if (psa_status == PSA_SUCCESS) { + *ciphertext_length += tag_length; + } + + return psa_status; + +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + if (ciphertext_length < tag_length + || ciphertext == NULL + || (tag_length > 16)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Split the tag in its own buffer to avoid potential issues when the + // plaintext buffer extends into the tag area + uint8_t check_tag[16]; + memcpy(check_tag, &ciphertext[ciphertext_length - tag_length], tag_length); + + return sli_cryptoacc_transparent_aead_decrypt_tag( + attributes, key_buffer, key_buffer_size, alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length - tag_length, + check_tag, tag_length, + plaintext, plaintext_size, plaintext_length); +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (key_buffer == NULL + || attributes == NULL + || nonce == NULL + || (additional_data == NULL && additional_data_length > 0) + || (plaintext == NULL && plaintext_length > 0) + || (plaintext_length > 0 && (ciphertext == NULL || ciphertext_size == 0)) + || ciphertext_length == NULL || tag_length == NULL + || tag_size == 0 || tag == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t key_bits = psa_get_key_bits(attributes); + *tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + // Verify that the driver supports the given parameters. + psa_status_t status = check_aead_parameters(attributes, alg, nonce_length, additional_data_length); + if (status != PSA_SUCCESS) { + return status; + } + + // Check input-key size. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if ((ciphertext_size < plaintext_length) + || (tag_size < *tag_length)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((ciphertext > plaintext) && (ciphertext < (plaintext + plaintext_length))) { + memmove(ciphertext, plaintext, plaintext_length); + plaintext = ciphertext; + } + + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + block_t key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t aad_block = block_t_convert(additional_data, additional_data_length); + block_t nonce_internal = block_t_convert(nonce, nonce_length); + block_t data_in = block_t_convert(plaintext, plaintext_length); + block_t data_out = block_t_convert(ciphertext, plaintext_length); + block_t tag_block = block_t_convert(tag, *tag_length); + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + + // Check length of plaintext. + { + unsigned char q = 16 - 1 - (unsigned char) nonce_length; + if (q < sizeof(plaintext_length) + && plaintext_length >= (1UL << (q * 8))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ccm_encrypt(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return_status = PSA_SUCCESS; + break; +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (nonce_length == AES_IV_GCM_SIZE) { + uint8_t tagbuf[16]; + tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_gcm_encrypt(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + // Copy only requested part of computed tag to user output buffer. + memcpy(tag, tagbuf, *tag_length); + return_status = PSA_SUCCESS; + } +#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + else { + return_status = sli_cryptoacc_software_gcm(key_buffer, PSA_BITS_TO_BYTES(key_bits), + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, + ciphertext, + plaintext_length, + *tag_length, + tag, + true); + } +#else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + else { + return_status = PSA_ERROR_NOT_SUPPORTED; + } +#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; +#endif // PSA_WANT_ALG_GCM + } + + if (return_status == PSA_SUCCESS) { + *ciphertext_length = plaintext_length; + } else { + *ciphertext_length = 0; + *tag_length = 0; + } + + return return_status; + +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + (void)tag; + (void)tag_size; + (void)tag_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + const uint8_t* tag, + size_t tag_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (attributes == NULL + || key_buffer == NULL + || nonce == NULL + || (additional_data == NULL && additional_data_length > 0) + || (ciphertext == NULL && ciphertext_length > 0) + || (plaintext == NULL && plaintext_size > 0) + || plaintext_length == NULL + || tag == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Verify that the driver supports the given parameters. + size_t key_bits = psa_get_key_bits(attributes); + psa_status_t status = check_aead_parameters(attributes, alg, nonce_length, additional_data_length); + if (status != PSA_SUCCESS) { + return status; + } + + // Check input-key size. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if (plaintext_size < ciphertext_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((plaintext > ciphertext) && (plaintext < (ciphertext + ciphertext_length))) { + memmove(plaintext, ciphertext, ciphertext_length); + ciphertext = plaintext; + } + + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key = NULL_blk; + block_t aad_block = NULL_blk; + block_t tag_block = NULL_blk; + block_t nonce_internal = NULL_blk; + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + + { + // Check length of ciphertext. + unsigned char q = 16 - 1 - (unsigned char) nonce_length; + if (q < sizeof(ciphertext_length) + && ciphertext_length >= (1UL << (q * 8))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + aad_block = block_t_convert(additional_data, additional_data_length); + tag_block = block_t_convert(tag, tag_length); + nonce_internal = block_t_convert(nonce, nonce_length); + data_in = block_t_convert(ciphertext, ciphertext_length); + data_out = block_t_convert(plaintext, ciphertext_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ccm_decrypt_verify(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return_status = PSA_ERROR_INVALID_SIGNATURE; + } else if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + *plaintext_length = ciphertext_length; + return_status = PSA_SUCCESS; + } + break; +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + uint8_t tagbuf[16]; + uint32_t diff = 0; + + if (nonce_length == AES_IV_GCM_SIZE) { + key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + aad_block = block_t_convert(additional_data, additional_data_length); + tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); + nonce_internal = block_t_convert(nonce, nonce_length); + data_in = block_t_convert(ciphertext, ciphertext_length); + data_out = block_t_convert(plaintext, ciphertext_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_gcm_decrypt(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + // Check that the provided tag equals the calculated one + // (in constant time). Note that the tag returned by ccm_auth_crypt + // is encrypted, so we don't have to decrypt the tag. + diff = sli_psa_safer_memcmp(tag, tagbuf, tag_length); + sli_psa_zeroize(tagbuf, tag_length); + + if (diff != 0) { + return_status = PSA_ERROR_INVALID_SIGNATURE; + } else { + *plaintext_length = ciphertext_length; + return_status = PSA_SUCCESS; + } + + break; + } + } +#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + else { + return_status = sli_cryptoacc_software_gcm(key_buffer, PSA_BITS_TO_BYTES(key_bits), + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, + plaintext, + ciphertext_length, + tag_length, + (uint8_t*)tag, + false); + if (return_status == PSA_SUCCESS) { + *plaintext_length = ciphertext_length; + } + } +#else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + else { + return_status = PSA_ERROR_NOT_SUPPORTED; + } +#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; + } +#endif // PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + if (return_status != PSA_SUCCESS) { + *plaintext_length = 0; + sli_psa_zeroize(plaintext, plaintext_size); + } + + return return_status; + +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_length; + (void)tag; + (void)tag_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) +static psa_status_t transparent_aead_encrypt_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + sli_aes_mode_t operation_direction) +{ + if (operation == NULL + || attributes == NULL + || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + + size_t key_bits = psa_get_key_bits(attributes); + size_t key_size = PSA_BITS_TO_BYTES(key_bits); + + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (sizeof(operation->key) < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Validate key type. + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Validate tag length. + if ( PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), key_bits, alg) > 16 ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Validate operation. + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined (PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + operation->alg = alg; + break; + } + #endif + #if defined (PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + operation->alg = alg; + break; + } + #endif + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + memcpy(operation->key, key_buffer, key_size); + operation->key_len = key_size; + + operation->direction = operation_direction; + + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + return transparent_aead_encrypt_decrypt_setup(operation, attributes, key_buffer, key_buffer_size, alg, SLI_AES_ENC); + + #else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + #endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + return transparent_aead_encrypt_decrypt_setup(operation, attributes, key_buffer, key_buffer_size, alg, SLI_AES_DEC); + + #else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + return PSA_ERROR_NOT_SUPPORTED; + #endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_set_nonce(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_size) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL || nonce == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Not able to set nonce twice. + if (operation->ctx.preinit.nonce_length != 0) { + return PSA_ERROR_BAD_STATE; + } + + if (nonce_size > sizeof(operation->ctx.preinit.nonce)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Validate operation. + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + if (nonce_size != 12) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + } +#endif +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + if (nonce_size < 7 || nonce_size > 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + } +#endif + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + memcpy(operation->ctx.preinit.nonce, nonce, nonce_size); + operation->ctx.preinit.nonce_length = nonce_size; + return PSA_SUCCESS; + +#else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)nonce; + (void)nonce_size; + return PSA_ERROR_NOT_SUPPORTED; +#endif +} + +psa_status_t sli_cryptoacc_transparent_aead_set_lengths(sli_cryptoacc_transparent_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + (void)ad_length; + + // Check if operation has already started + if (operation->ad_len != 0 || operation->processed_len != 0) { + return PSA_ERROR_BAD_STATE; + } + + // To pass current PSA Crypto test suite, tag length encoded in the + // algorithm needs to be checked at this point. + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + if ((PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) % 2 != 0) + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->total_length = plaintext_length; + + break; +#endif +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + (void)plaintext_length; + if (PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif + default: + return PSA_ERROR_BAD_STATE; + } + + return PSA_SUCCESS; + #else//PSA_WANT_ALG_CCM + (void)operation; + (void)ad_length; + (void)plaintext_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif//PSA_WANT_ALG_CCM +} + +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) +static psa_status_t cryptoacc_aead_start(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + psa_algorithm_t alg = operation->alg; + + block_t ctx_out_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + + block_t key = block_t_convert(operation->key, operation->key_len); + block_t aad_block = block_t_convert(input, input_length); + block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + + // Get ownership. + return_status = cryptoacc_management_acquire(); + if (return_status != PSA_SUCCESS) { + return return_status; + } + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + uint32_t tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + if (operation->direction == SLI_AES_ENC) { + // CCM finish must have input data, in the case of pt_len = 0 and aad_len != 0 we + // need to precompute the tag. (Only needed for encrypt) + if (operation->total_length == 0 && input_length != 0) { + block_t tag_block = block_t_convert(operation->ctx.tag_buf, tag_length); + sx_ret = sx_aes_ccm_encrypt(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + + goto exit; + } else { + sx_ret = sx_aes_ccm_encrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block, + tag_length, + operation->total_length); + } + } else { + sx_ret = sx_aes_ccm_decrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block, + tag_length, + operation->total_length); + } + break; + } +#endif//PSA_WANT_ALG_CCM +#if defined (PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block); + } else { + sx_ret = sx_aes_gcm_decrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block); + } + goto exit; + break; +#endif//PSA_WANT_ALG_GCM + } + + exit: + + // Release ownership. + return_status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + operation->ad_len += input_length; + return PSA_SUCCESS; +} +#endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + +psa_status_t sli_cryptoacc_transparent_aead_update_ad(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + if (operation->ad_len > 0 || operation->processed_len > 0) { + return PSA_ERROR_BAD_STATE; + } + + // No additional data. + if (input_length == 0) { + return PSA_SUCCESS; + } + + return cryptoacc_aead_start(operation, input, input_length); +#else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)operation; + (void)input; + (void)input_length; + return PSA_ERROR_NOT_SUPPORTED; +#endif//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Check output buffer size is not too small. The required size = + // input_length + residual data stored in context object from previous update + // The PSA Crypto tests require output buffer can hold the residual bytes in + // the last AES block even if these are not processed and written in this call + // ( they are postponed to the next call to update or finish ). + + if (output_size < input_length + operation->final_data_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (((input == NULL || output == NULL) && input_length > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check variable overflow + if (operation->processed_len > 0xFFFFFFFF - input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + *output_length = 0; + + if (input_length == 0) { + return PSA_SUCCESS; + } + + psa_algorithm_t alg = operation->alg; + + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + block_t key = block_t_convert(operation->key, operation->key_len); + + block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + block_t ctx_out_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + + block_t input_block = block_t_convert(input, input_length); + block_t output_block = block_t_convert(output, input_length); + + // The extra logic is to support non-blocksize input data. + + // Store data in context if there is space in the data buffer. + if ((input_length + operation->final_data_length) < 16 && input_length < 16) { + if (operation->final_data_length > 16) { + // Invalid context. + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(operation->final_data + operation->final_data_length, input, input_length); + operation->final_data_length += input_length; + return PSA_SUCCESS; + } + + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->ad_len == 0 && operation->processed_len == 0) { + cryptoacc_aead_start(operation, NULL, 0); + } + } + + uint8_t input_offset = 0; + +#if defined(PSA_WANT_ALG_GCM) + block_t aad_block = NULL_blk; + block_t nonce_block = NULL_blk; + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Operation is not initialized. + nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + } +#endif + + if (operation->final_data_length) { + if (operation->final_data_length > 16) { + // Invalid context. + return PSA_ERROR_INVALID_ARGUMENT; + } + + // If there is data stored in context: fill final_data buffer and process it first. + input_offset = 16 - operation->final_data_length; + memcpy(operation->final_data + operation->final_data_length, input, input_offset); + +#if defined(PSA_WANT_ALG_CCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->processed_len + 16 == operation->total_length) { + operation->final_data_length = 16; + return PSA_SUCCESS; + } + } +#endif + + block_t input_block_final = block_t_convert(operation->final_data, 16); + block_t output_block_final = block_t_convert(output, 16); + + return_status = cryptoacc_management_acquire(); + if (return_status != PSA_SUCCESS) { + return return_status; + } + + #if defined(PSA_WANT_ALG_GCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Not initialized. + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_init(&key, + &input_block_final, + &output_block_final, + &nonce_block, + &ctx_out_block, + &aad_block); + } else { + sx_ret = sx_aes_gcm_decrypt_init(&key, + &input_block_final, + &output_block_final, + &nonce_block, + &ctx_out_block, + &aad_block); + } + } else { + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_gcm_decrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } + } + } + #endif //PSA_WANT_ALG_GCM + + #if defined(PSA_WANT_ALG_CCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_ccm_encrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_ccm_decrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } + } + #endif //PSA_WANT_ALG_CCM + + // Release ownership. + return_status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + operation->final_data_length = 0; + input_length -= input_offset; + operation->processed_len += 16; + output += 16; + *output_length += 16; + } + + // Store data in context if there is space in the data buffer. + if (input_length < 16 && !operation->final_data_length && input_length < 16) { + memcpy(operation->final_data, input + input_offset, input_length); + operation->final_data_length = input_length; + return PSA_SUCCESS; + } + + // Store data that is not a multiple of 16 in context. + uint8_t res_data_length = input_length % 16; + memcpy(operation->final_data, input + input_offset + (input_length - res_data_length), res_data_length); + operation->final_data_length = res_data_length; + input_length -= res_data_length; + + // Get ownership. + return_status = cryptoacc_management_acquire(); + if (return_status != PSA_SUCCESS) { + return return_status; + } + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + // CCM multipart finish will hardfault without input data, so we must always save + // some data for the final operation. + if ((operation->processed_len + input_length) == operation->total_length) { + memcpy(operation->final_data, input + (input_length - 16), 16); + operation->final_data_length = 16; + input_length -= operation->final_data_length; + if (!input_length) { + return_status = cryptoacc_management_release(); + return return_status; + } + } + + input_block = block_t_convert(input + input_offset, input_length); + output_block = block_t_convert(output, input_length); + + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_ccm_encrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_ccm_decrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } + break; + #endif //PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + + input_block = block_t_convert(input + input_offset, input_length); + output_block = block_t_convert(output, input_length); + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Not initialized. + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_init(&key, + &input_block, + &output_block, + &nonce_block, + &ctx_out_block, + &aad_block); + } else { + sx_ret = sx_aes_gcm_decrypt_init(&key, + &input_block, + &output_block, + &nonce_block, + &ctx_out_block, + &aad_block); + } + } else { + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_gcm_decrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } + } + break; + #endif //PSA_WANT_ALG_GCM + default: + (void) cryptoacc_management_release(); + return PSA_ERROR_NOT_SUPPORTED; + } + // Release ownership. + return_status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length += input_length; + operation->processed_len += input_length; + return return_status; + + #else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (ciphertext_size < operation->final_data_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + + if (tag_size < tag_len) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t key = block_t_convert(operation->key, operation->key_len); + + uint8_t tagbuf[16]; + block_t tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + psa_algorithm_t alg = operation->alg; + + if (operation->direction != SLI_AES_ENC) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Operation is not initialized. + + block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + block_t aad_block = NULL_blk; + + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + tag_block = block_t_convert(tagbuf, tag_len); + sx_ret = sx_aes_ccm_encrypt(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + *ciphertext_length = 0; + break; + } + #endif //PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + data_in = block_t_convert(operation->final_data, operation->final_data_length); + data_out = block_t_convert(ciphertext, operation->final_data_length); + sx_ret = sx_aes_gcm_encrypt(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + *ciphertext_length = operation->final_data_length; + break; + } + #endif //PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + // Release ownership. + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS ) { + *ciphertext_length = 0; + return PSA_ERROR_HARDWARE_FAILURE; + } + memcpy(tag, tagbuf, tag_len); + return PSA_SUCCESS; + } + + #if defined(PSA_WANT_ALG_GCM) + uint32_t lena_lenc[4]; + lena_lenc[0] = __REV(operation->ad_len >> 29); + lena_lenc[1] = __REV((operation->ad_len << 3) & 0xFFFFFFFFUL); + lena_lenc[2] = __REV((operation->processed_len + operation->final_data_length) >> 29); + lena_lenc[3] = __REV(((operation->processed_len + operation->final_data_length) << 3) & 0xFFFFFFFFUL); + + block_t len_a_c = block_t_convert(lena_lenc, sizeof(lena_lenc)); + #endif + + block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + + block_t data_in_block = block_t_convert(operation->final_data, operation->final_data_length); + block_t data_out_block = block_t_convert(ciphertext, operation->final_data_length); + + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + if (operation->ad_len != 0 && operation->total_length == 0) { + // Tag is calculated in update_ad. + memcpy(tag, operation->ctx.tag_buf, tag_len); + return PSA_SUCCESS; + } + + sx_ret = sx_aes_ccm_encrypt_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block); + break; + } + #endif //PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + sx_ret = sx_aes_gcm_encrypt_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block, + &len_a_c); + break; + } + #endif //PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + // Release ownership. + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + memcpy(tag, tagbuf, tag_size); + *ciphertext_length = operation->final_data_length; + *tag_length = tag_len; + return status; + + #else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + (void)tag; + (void)tag_size; + (void)tag_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM) +} + +psa_status_t sli_cryptoacc_transparent_aead_verify(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (tag == NULL || tag_length == 0 ) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + if (plaintext_size < operation->final_data_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + block_t key = block_t_convert(operation->key, operation->key_len); + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + psa_algorithm_t alg = operation->alg; + if (operation->direction != SLI_AES_DEC) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Operation is not initialized. + block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + block_t aad_block = NULL_blk; + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + block_t tag_block = block_t_convert(tag, tag_length); + sx_ret = sx_aes_ccm_decrypt_verify(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + *plaintext_length = 0; + break; + } + #endif//PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + block_t tag_block = block_t_convert(tag, tag_length); + + data_in = block_t_convert(operation->final_data, operation->final_data_length); + data_out = block_t_convert(plaintext, operation->final_data_length); + + sx_ret = sx_aes_gcm_decrypt_verify(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return PSA_ERROR_INVALID_SIGNATURE; + } + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = operation->final_data_length; + break; + } + #endif//PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; + } + + #if defined(PSA_WANT_ALG_GCM) + uint32_t lena_lenc[4]; + lena_lenc[0] = __REV(operation->ad_len >> 29); + lena_lenc[1] = __REV((operation->ad_len << 3) & 0xFFFFFFFFUL); + lena_lenc[2] = __REV((operation->processed_len + operation->final_data_length) >> 29); + lena_lenc[3] = __REV(((operation->processed_len + operation->final_data_length) << 3) & 0xFFFFFFFFUL); + block_t len_a_c = block_t_convert(lena_lenc, sizeof(lena_lenc)); + #endif + + block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + block_t tag_block = block_t_convert(tag, tag_length); + + block_t data_in_block = block_t_convert(operation->final_data, operation->final_data_length); + block_t data_out_block = block_t_convert(plaintext, operation->final_data_length); + + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + if (tag_length != tag_len) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + sx_ret = sx_aes_ccm_decrypt_verify_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block); + break; + } + #endif//PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + sx_ret = sx_aes_gcm_decrypt_verify_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block, + &len_a_c); + break; + } + #endif//PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Release ownership. + status = cryptoacc_management_release(); + + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return PSA_ERROR_INVALID_SIGNATURE; + } + if (sx_ret != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = operation->final_data_length; + + return PSA_SUCCESS; + + #else//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)tag; + (void)tag_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_abort(sli_cryptoacc_transparent_aead_operation_t *operation) +{ + // No state is ever left in HW, so zeroing context should do the trick + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + return PSA_SUCCESS; +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c new file mode 100644 index 000000000..59eb04932 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c @@ -0,0 +1,2168 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Cipher functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" +#include "psa/crypto_extra.h" +#include "cryptolib_def.h" +#include "sx_errors.h" +#include "sx_aes.h" + +#include + +/** Encrypt a message using a symmetric cipher. + * + * This function encrypts a message with a random IV (initialization + * vector). Use the multipart operation interface with a + * #psa_cipher_operation_t object to provide other forms of IV. + * + * \param handle Handle to the key to use for the operation. + * It must remain valid until the operation + * terminates. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] input Buffer containing the message to encrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * The output contains the IV followed by + * the ciphertext proper. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_NOT_PERMITTED + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p handle is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_COMMUNICATION_FAILURE + * \retval #PSA_ERROR_HARDWARE_FAILURE + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t sli_cryptoacc_transparent_cipher_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t data_in; + block_t data_out; +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + uint8_t tmp_buf[16] = { 0 }; +#endif +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + block_t iv_block; +#endif +#endif // MBEDTLS_PSA_CRYPTO_C + // Argument check + if (key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || (iv == NULL && iv_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check key type and size. + switch (alg) { + case PSA_ALG_ECB_NO_PADDING: +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif +#endif /* MBEDTLS_PSA_CRYPTO_C */ + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (key_buffer_size < (psa_get_key_bits(attributes) / 8) + || !(psa_get_key_bits(attributes) == 128 + || psa_get_key_bits(attributes) == 192 + || psa_get_key_bits(attributes) == 256)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // 0-length encrypt/decrypt is allowed according to the unit tests in PSA + if (input_length == 0) { + *output_length = 0; + return PSA_SUCCESS; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + // Encrypt. + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // We cannot do ECB on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(PSA_WANT_KEY_TYPE_AES) && defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + +#if defined(PSA_WANT_ALG_CCM) + if (alg == PSA_ALG_CCM_STAR_NO_TAG) { + if (iv_length != 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // AES-CCM*-no-tag is basically AES-CTR with preformatted IV + tmp_buf[0] = 1; + memcpy(&tmp_buf[1], iv, 13); + tmp_buf[14] = 0; + tmp_buf[15] = 1; + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + } else +#endif + { + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + iv_block = block_t_convert(iv, AES_IV_SIZE); + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ctr_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Copy final input bytes before they are overwritten (in case of overlap with output buffer). + memcpy(tmp_buf, input + (input_length / 16) * 16, input_length % 16); + + key = block_t_convert(key_buffer, key_buffer_size); + + size_t input_length_full_blocks = (input_length / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + iv_block = block_t_convert(iv, AES_IV_SIZE); + data_in = block_t_convert(input, input_length_full_blocks); + data_out = block_t_convert(output, + input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final bytes. + if (input_length % 16 != 0) { + iv_block = block_t_convert(&output[input_length_full_blocks - 16], + AES_IV_SIZE); + data_in = block_t_convert(tmp_buf, 16); + data_out = block_t_convert(tmp_buf, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + tmp_buf, + input_length % 16); + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: { + uint8_t final_block[16]; + + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Copy final input bytes before they are overwritten (in case of overlap with output buffer). + memcpy(final_block, input + (input_length / 16) * 16, input_length % 16); + + // Copy IV to tmp buf in order to avoid overwriting it with intermediate IV. + memcpy(tmp_buf, iv, AES_IV_SIZE); + + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + + size_t input_length_full_blocks = (input_length / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + data_in = block_t_convert(input, input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process leftover bytes. + if (input_length % 16 != 0) { + data_in = block_t_convert(final_block, 16); + data_out = block_t_convert(final_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + final_block, + input_length % 16); + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // We cannot do CBC without padding on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // fall through + case PSA_ALG_CBC_PKCS7: { + uint8_t final_block[16]; + + // Check buffer sizes. + if (alg == PSA_ALG_CBC_NO_PADDING) { + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } else { + if (output_size < (input_length & ~0xF) + 16) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Copy IV to tmp buf in order to avoid overwriting it with intermediate IV. + memcpy(tmp_buf, iv, AES_IV_SIZE); + + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + data_in = block_t_convert(input, input_length & ~0xF); + data_out = block_t_convert(output, input_length & ~0xF); + + // Store last block (if non-blocksize input-length) to temporary buffer to be used in padding. + if (alg == PSA_ALG_CBC_PKCS7) { + memcpy(final_block, + &input[input_length & ~0xF], + input_length & 0xF); + } + + if ((input_length & ~0xF) > 0) { + // CBC-encrypt all but the last block. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final block. + if (alg == PSA_ALG_CBC_PKCS7) { + // Add PKCS7 padding. + memset(&final_block[input_length & 0xF], + 16 - (input_length & 0xF), + 16 - (input_length & 0xF)); + + // CBC-encrypt the last block. + data_in = block_t_convert(final_block, 16); + data_out = block_t_convert(final_block, 16); + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Copy to output. + memcpy(&output[(input_length & ~0xF)], + final_block, + 16); + + *output_length = (input_length & ~0xF) + 16; + } else { + *output_length = input_length; + } + break; + } +#endif // PSA_WANT_ALG_CBC_PKCS7 || PSA_WANT_ALG_CBC_NO_PADDING +#endif /* MBEDTLS_PSA_CRYPTO_C */ + default: + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES +} + +/** Decrypt a message using a symmetric cipher. + * + * This function decrypts a message encrypted with a symmetric cipher. + * + * \param handle Handle to the key to use for the operation. + * It must remain valid until the operation + * terminates. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] input Buffer containing the message to decrypt. + * This consists of the IV followed by the + * ciphertext proper. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the plaintext is to be written. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_NOT_PERMITTED + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p handle is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_COMMUNICATION_FAILURE + * \retval #PSA_ERROR_HARDWARE_FAILURE + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t sli_cryptoacc_transparent_cipher_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t data_in; + block_t data_out; + +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + block_t iv_block; +#endif +#if defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + uint8_t tmp_buf[16]; +#endif + + // Argument check + if (key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check key type and size. + switch (alg) { + case PSA_ALG_ECB_NO_PADDING: +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (key_buffer_size < (psa_get_key_bits(attributes) / 8) + || !(psa_get_key_bits(attributes) == 128 + || psa_get_key_bits(attributes) == 192 + || psa_get_key_bits(attributes) == 256)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // 0-length encrypt/decrypt is allowed according to the unit tests in Mbed TLS. + if (input_length == 0) { + *output_length = 0; + return PSA_SUCCESS; + } + // Only passing an IV should also be OK (all modes use an IV except ECB). + if ((input_length == AES_IV_SIZE) + && (alg != PSA_ALG_ECB_NO_PADDING)) { + *output_length = 0; + return PSA_SUCCESS; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // We cannot do ECB on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: { + // Check buffer sizes. +#if defined(PSA_WANT_ALG_CCM) + if (alg == PSA_ALG_CCM_STAR_NO_TAG) { + if (output_size < input_length - 13) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // AES-CCM*-no-tag is basically AES-CTR with preformatted IV + tmp_buf[0] = 1; + memcpy(&tmp_buf[1], input, 13); + tmp_buf[14] = 0; + tmp_buf[15] = 1; + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + + input += 13; + input_length -= 13; + } else +#endif + { + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + iv_block = block_t_convert(input, AES_IV_SIZE); + + input += AES_IV_SIZE; + input_length -= AES_IV_SIZE; + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ctr_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: { + // Check buffer sizes. + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + key = block_t_convert(key_buffer, key_buffer_size); + + size_t input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + iv_block = block_t_convert(input, AES_IV_SIZE); + data_in = block_t_convert(input + AES_IV_SIZE, + input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final bytes. + if (input_length % 16 != 0) { + iv_block = block_t_convert(input + input_length_full_blocks, + AES_IV_SIZE); + data_in = block_t_convert(input + AES_IV_SIZE + input_length_full_blocks, + 16); + data_out = block_t_convert(tmp_buf, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + tmp_buf, + input_length % 16); + } + + *output_length = input_length - AES_IV_SIZE; + break; + } +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: { + // Check buffer sizes. + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Move IV into tmp buffer in order to avoid messing up output (in case of overlap with input). + memcpy(tmp_buf, input, AES_IV_SIZE); + + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + + size_t input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + data_in = block_t_convert(input + AES_IV_SIZE, + input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final bytes. + if (input_length % 16 != 0) { + data_in = block_t_convert(input + AES_IV_SIZE + input_length_full_blocks, + 16); + data_out = block_t_convert(tmp_buf, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + tmp_buf, + input_length % 16); + } + + *output_length = input_length - AES_IV_SIZE; + break; + } +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // fall through + case PSA_ALG_CBC_PKCS7: { + size_t input_length_full_blocks; + uint8_t iv_buf[AES_IV_SIZE]; + + // We cannot do CBC decryption on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (alg == PSA_ALG_CBC_NO_PADDING) { + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; + } else { + // Check output has enough room for at least n-1 blocks. + if (input_length < AES_IV_SIZE + 16 + || output_size < (input_length - AES_IV_SIZE - 16)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + input_length_full_blocks = ((input_length - AES_IV_SIZE - 16) / 16) * 16; + } + + // Write IV to temporary buf to be used by sx_aes_cbc_decrypt_update. + memcpy(iv_buf, input, AES_IV_SIZE); + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(iv_buf, AES_IV_SIZE); + + if (input_length_full_blocks > 0) { + data_in = block_t_convert(input + AES_IV_SIZE, + input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + // CBC-decrypt all but the last block. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final block. + if (alg == PSA_ALG_CBC_PKCS7) { + // Store last block to temporary buffer to be used in removing the padding. + memcpy(tmp_buf, &input[input_length - 16], 16); + + data_in = block_t_convert(tmp_buf, 16); + data_out = block_t_convert(tmp_buf, 16); + + // CBC-decrypt the last block. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Check all padding bytes. + size_t pad_bytes = 0; + status = sli_psa_validate_pkcs7_padding(tmp_buf, + 16, + &pad_bytes); + if (status != PSA_SUCCESS) { + return status; + } + + if (output_size < (input_length - AES_IV_SIZE - pad_bytes)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Copy non-padding bytes. + memcpy(&output[input_length_full_blocks], tmp_buf, 16 - pad_bytes); + + *output_length = input_length - AES_IV_SIZE - pad_bytes; + } else { + *output_length = input_length - AES_IV_SIZE; + } + break; + } +#endif // PSA_WANT_ALG_CBC_PKCS7 || PSA_WANT_ALG_CBC_NO_PADDING + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_encrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); + + // Set up context. + memcpy(&operation->alg, &alg, sizeof(alg)); + operation->direction = SLI_AES_ENC; + + // Validate combination of key and algorithm. + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif // PSA_WANT_ALG_CTR +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif // PSA_WANT_ALG_CBC_PKCS7 + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Copy key into context. + switch (psa_get_key_bits(attributes)) { + case 128: + if (key_buffer_size < 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 16); + operation->key_len = 16; + break; + case 192: + if (key_buffer_size < 24) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 24); + operation->key_len = 24; + break; + case 256: + if (key_buffer_size < 32) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 32); + operation->key_len = 32; + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_decrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); + + // Set up context. + memcpy(&operation->alg, &alg, sizeof(alg)); + operation->direction = SLI_AES_DEC; + + // Validate combination of key and algorithm. + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif // PSA_WANT_ALG_CTR +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif // PSA_WANT_ALG_CBC_PKCS7 + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Copy key into context. + switch (psa_get_key_bits(attributes)) { + case 128: + if (key_buffer_size < 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 16); + operation->key_len = 16; + break; + case 192: + if (key_buffer_size < 24) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 24); + operation->key_len = 24; + break; + case 256: + if (key_buffer_size < 32) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 32); + operation->key_len = 32; + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_set_iv(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation == NULL || iv == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (iv_length > sizeof(operation->iv)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->iv_len != 0) { + // IV was set previously. + return PSA_ERROR_BAD_STATE; + } + + if (operation->key_len == 0) { + // context hasn't been properly initialised. + return PSA_ERROR_BAD_STATE; + } + +#if defined(PSA_WANT_ALG_CCM) + if (operation->alg == PSA_ALG_CCM_STAR_NO_TAG) { + // Preformat the IV for CCM*-no-tag here, such that the remainder + // of the processing for this algorithm boils down to AES-CTR + if (iv_length != 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->iv[0] = 1; + memcpy(&operation->iv[1], iv, iv_length); + operation->iv[14] = 0; + operation->iv[15] = 1; + operation->iv_len = 16; + } else +#endif // PSA_WANT_ALG_CCM + if (operation->alg != PSA_ALG_ECB_NO_PADDING) { + if (iv_length != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->iv_len = iv_length; + memcpy(operation->iv, iv, iv_length); + } else { + if (iv_length > 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)iv; + (void)iv_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_update(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t data_in; + block_t data_out; + + // Argument check. + if (operation == NULL + || (input == NULL && input_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check if IV has been set. + if ((operation->alg != PSA_ALG_ECB_NO_PADDING) + && (operation->iv_len == 0)) { + return PSA_ERROR_BAD_STATE; + } + +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) + uint8_t tmp_buf[16]; + block_t tmp_iv_block = block_t_convert(tmp_buf, 16); +#endif +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + block_t iv_block = block_t_convert(operation->iv, operation->iv_len); +#endif + + // Figure out whether the operation is on a lagging or forward-looking cipher + // Lagging: needs a full block of input data before being able to output + // Non-lagging: can output the same amount of data as getting fed + bool lagging = true; + switch (operation->alg) { + case PSA_ALG_ECB_NO_PADDING: + case PSA_ALG_CBC_NO_PADDING: + case PSA_ALG_CBC_PKCS7: + lagging = true; + break; + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_CFB: + case PSA_ALG_OFB: + lagging = false; + break; + default: + return PSA_ERROR_BAD_STATE; + } + + size_t bytes_to_boundary = 16 - (operation->processed_length % 16); + size_t actual_output_length = 0; + *output_length = 0; + + if ( input_length == 0 ) { + return PSA_SUCCESS; + } + + // We need to cache (not return) the whole last block for decryption with + // padding, otherwise it won't be possible to remove a potential padding block + // during finish. + bool cache_full_block = (operation->alg == PSA_ALG_CBC_PKCS7 + && operation->direction == SLI_AES_DEC); + + // Early processing if not getting to a full block for lagging ciphers. + if (lagging) { + if (cache_full_block + && bytes_to_boundary == 16 + && operation->processed_length > 0) { + // Don't overwrite the streaming block yet if it's currently full. + } else if (input_length < bytes_to_boundary) { + memcpy(&operation->streaming_block[operation->processed_length % 16], + input, + input_length); + operation->processed_length += input_length; + *output_length = actual_output_length; + return PSA_SUCCESS; + } + + // We know we'll be computing at least the completed streaming block + size_t output_blocks = 1; + if (input_length > bytes_to_boundary) { + // plus however many full blocks are left over after filling the stream buffer + output_blocks += (input_length - bytes_to_boundary) / 16; + // If we're caching and the sum of already-input and to-be-input data + // ends up at a block boundary, we won't be outputting the last block + if (cache_full_block && ((input_length - bytes_to_boundary) % 16 == 0)) { + output_blocks -= 1; + } + } + + if (output_size < (output_blocks * 16)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } else { + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + key = block_t_convert(operation->key, operation->key_len); + + if (bytes_to_boundary != 16) { + // Read in up to full streaming input block. + memcpy(&operation->streaming_block[operation->processed_length % 16], + input, + bytes_to_boundary); + + data_in = block_t_convert(operation->streaming_block, 16); + data_out = block_t_convert(operation->streaming_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (operation->direction == SLI_AES_ENC) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: + sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: + if (cache_full_block && (bytes_to_boundary == input_length)) { + // Don't process the streaming block if there is no more input data + sx_ret = CRYPTOLIB_SUCCESS; + } else { + sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + } + break; +#endif // PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } else { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: + if (cache_full_block && (bytes_to_boundary == input_length)) { + // Don't process the streaming block if there is no more input data + sx_ret = CRYPTOLIB_SUCCESS; + } else { + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + } + break; +#endif // PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (lagging) { + memcpy(output, operation->streaming_block, 16); + // Don't increase output if no encryption/decryption was done + if (!(cache_full_block && (bytes_to_boundary == input_length))) { + output += 16; + actual_output_length += 16; + } + operation->processed_length += bytes_to_boundary; + input += bytes_to_boundary; + input_length -= bytes_to_boundary; + } else { + if (input_length < bytes_to_boundary) { + bytes_to_boundary = input_length; + } + + memcpy(output, operation->streaming_block + (operation->processed_length % 16), bytes_to_boundary); + output += bytes_to_boundary; + actual_output_length += bytes_to_boundary; + operation->processed_length += bytes_to_boundary; + input += bytes_to_boundary; + input_length -= bytes_to_boundary; + +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) + // Only want to update IV if we actually finished an entire block. + if (operation->processed_length % 16 == 0) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + if (operation->direction == SLI_AES_ENC) { + memcpy(operation->iv, output - 16, 16); + } else { + memcpy(operation->iv, input - 16, 16); + } + break; +#endif +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_OFB) + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_OFB: + memcpy(operation->iv, tmp_buf, 16); + break; +#endif + } + } +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_CFB || PSA_WANT_ALG_OFB + } + } +#if defined(PSA_WANT_ALG_CBC_PKCS7) + else if (cache_full_block && operation->processed_length > 0) { + // We know there's processing to be done, and that we haven't processed + // the full block in the streaming buffer yet. Process it now. + data_in = block_t_convert(operation->streaming_block, 16); + data_out = block_t_convert(operation->streaming_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output, operation->streaming_block, 16); + output += 16; + actual_output_length += 16; + } +#endif + + // Do multi-block operation if applicable. + if (input_length >= 16) { + size_t operation_size = (input_length / 16) * 16; + + if (cache_full_block && (input_length % 16 == 0)) { + // Don't decrypt the last block until finish is called, so that we + // can properly remove the padding before returning it. + operation_size -= 16; + } + + if (operation_size > 0) { + data_in = block_t_convert(input, operation_size); + data_out = block_t_convert(output, operation_size); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (operation->direction == SLI_AES_ENC) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // fall through + case PSA_ALG_CBC_PKCS7: + sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING || PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } else { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // fall through + case PSA_ALG_CBC_PKCS7: + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING || PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + input += operation_size; + input_length -= operation_size; + actual_output_length += operation_size; + output += operation_size; + operation->processed_length += operation_size; + } + + // Process final block. + if (input_length > 0) { + if (!lagging) { +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_CFB) || defined(PSA_WANT_ALG_OFB) + data_in = block_t_convert(input, 16); + data_out = block_t_convert(operation->streaming_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (operation->direction == SLI_AES_ENC) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_OFB + default: + return PSA_ERROR_BAD_STATE; + } + } else { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_OFB + default: + return PSA_ERROR_BAD_STATE; + } + } + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output, + operation->streaming_block, + input_length); + + actual_output_length += input_length; + operation->processed_length += input_length; +#else + return PSA_ERROR_BAD_STATE; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_CFB || PSA_WANT_ALG_OFB + } else { + if ((input_length >= 16 && !cache_full_block) + || (input_length > 16 && cache_full_block)) { + *output_length = 0; + return PSA_ERROR_BAD_STATE; + } + memcpy(operation->streaming_block, + input, + input_length); + operation->processed_length += input_length; + } + } + + *output_length = actual_output_length; + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_finish(sli_cryptoacc_transparent_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + +#if defined(PSA_WANT_ALG_CBC_PKCS7) + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; +#endif // PSA_WANT_ALG_CBC_PKCS7 + + // Argument check. + if (operation == NULL) { + *output_length = 0; + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) || defined(PSA_WANT_ALG_CBC_NO_PADDING) + // Blocksize-only modes without padding. + case PSA_ALG_ECB_NO_PADDING: + case PSA_ALG_CBC_NO_PADDING: + // Can't finish if they haven't processed block-size input. + if (operation->processed_length % 16 != 0) { + status = PSA_ERROR_INVALID_ARGUMENT; + } else { + status = PSA_SUCCESS; + } + *output_length = 0; + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING || PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_CFB) || defined(PSA_WANT_ALG_OFB) + // Stream cipher modes. + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_CFB: + case PSA_ALG_OFB: + status = PSA_SUCCESS; + *output_length = 0; + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_*FB +#if defined(PSA_WANT_ALG_CBC_PKCS7) + // Padding mode. + case PSA_ALG_CBC_PKCS7: + if ((output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + key = block_t_convert(operation->key, operation->key_len); + iv_block = block_t_convert(operation->iv, operation->iv_len); + data_in = block_t_convert(operation->streaming_block, 16); + data_out = block_t_convert(output, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (operation->direction == SLI_AES_ENC) { + if (output_size < 16) { + status = cryptoacc_management_release(); + if (status == PSA_SUCCESS) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + } + break; + } + size_t padding_bytes = 16 - (operation->processed_length % 16); + memset(&operation->streaming_block[16 - padding_bytes], + padding_bytes, + padding_bytes); + + sx_ret = sx_aes_cbc_encrypt((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + status = PSA_ERROR_HARDWARE_FAILURE; + } else { + *output_length = 16; + status = PSA_SUCCESS; + } + } else { + // Expect full-block input. + if (operation->processed_length % 16 != 0 + || operation->processed_length < 16) { + status = PSA_ERROR_INVALID_ARGUMENT; + break; + } + + uint8_t out_buf[16]; + block_t out_buf_block = block_t_convert(&out_buf, 16); + + // Decrypt the last block + sx_ret = sx_aes_cbc_decrypt((const block_t *)&key, + (const block_t *)&data_in, + &out_buf_block, + (const block_t *)&iv_block); + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + status = PSA_ERROR_HARDWARE_FAILURE; + break; + } + + size_t padding_bytes = 0; + status = sli_psa_validate_pkcs7_padding(out_buf, + 16, + &padding_bytes); + + if (status == PSA_SUCCESS) { + // The padding was valid. + if (output_size < 16 - padding_bytes) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + break; + } + memcpy(output, out_buf, 16 - padding_bytes); + *output_length = 16 - padding_bytes; + } + } + break; +#endif // PSA_WANT_ALG_CBC_PKCS7 + default: + status = PSA_ERROR_BAD_STATE; + break; + } + +#if !defined(PSA_WANT_ALG_CBC_PKCS7) + (void)output; + (void)output_size; +#endif // PSA_WANT_ALG_CBC_PKCS7 + + if (status != PSA_SUCCESS) { + *output_length = 0; + } + + // Wipe context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); + + return status; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_* + + (void)operation; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_* +} + +psa_status_t sli_cryptoacc_transparent_cipher_abort(sli_cryptoacc_transparent_cipher_operation_t *operation) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation != NULL) { + // Wipe context. + memset(operation, 0, sizeof(*operation)); + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c new file mode 100644 index 000000000..65b46eca0 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c @@ -0,0 +1,490 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Hash functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" + +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + +#include "cryptoacc_management.h" +#include "sx_hash.h" +#include "sx_errors.h" +#include + +// Define all init vectors. +#if defined(PSA_WANT_ALG_SHA_1) +static const uint8_t init_state_sha1[32] = { + 0x67, 0x45, 0x23, 0x01, + 0xEF, 0xCD, 0xAB, 0x89, + 0x98, 0xBA, 0xDC, 0xFE, + 0x10, 0x32, 0x54, 0x76, + 0xC3, 0xD2, 0xE1, 0xF0, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) +static const uint8_t init_state_sha224[32] = { + 0xC1, 0x05, 0x9E, 0xD8, + 0x36, 0x7C, 0xD5, 0x07, + 0x30, 0x70, 0xDD, 0x17, + 0xF7, 0x0E, 0x59, 0x39, + 0xFF, 0xC0, 0x0B, 0x31, + 0x68, 0x58, 0x15, 0x11, + 0x64, 0xF9, 0x8F, 0xA7, + 0xBE, 0xFA, 0x4F, 0xA4 +}; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) +static const uint8_t init_state_sha256[32] = { + 0x6A, 0x09, 0xE6, 0x67, + 0xBB, 0x67, 0xAE, 0x85, + 0x3C, 0x6E, 0xF3, 0x72, + 0xA5, 0x4F, 0xF5, 0x3A, + 0x51, 0x0E, 0x52, 0x7F, + 0x9B, 0x05, 0x68, 0x8C, + 0x1F, 0x83, 0xD9, 0xAB, + 0x5B, 0xE0, 0xCD, 0x19 +}; +#endif // PSA_WANT_ALG_SHA_256 + +#endif // PSA_WANT_ALG_SHA_* + +psa_status_t sli_cryptoacc_transparent_hash_setup(sli_cryptoacc_transparent_hash_operation_t *operation, + psa_algorithm_t alg) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (!PSA_ALG_IS_HASH(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); + + switch (alg) { +#if defined(PSA_WANT_ALG_SHA_1) + case PSA_ALG_SHA_1: + operation->hash_type = e_SHA1; + memcpy(operation->state, init_state_sha1, SHA1_STATESIZE); + break; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case PSA_ALG_SHA_224: + operation->hash_type = e_SHA224; + memcpy(operation->state, init_state_sha224, SHA224_STATESIZE); + break; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case PSA_ALG_SHA_256: + operation->hash_type = e_SHA256; + memcpy(operation->state, init_state_sha256, SHA256_STATESIZE); + break; +#endif // PSA_WANT_ALG_SHA_256 + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + operation->total = 0; + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_update(sli_cryptoacc_transparent_hash_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + size_t blocks, fill, left; + block_t data_in; + block_t state; + uint32_t sx_ret; + psa_status_t status; + + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (operation->hash_type) { +#if defined(PSA_WANT_ALG_SHA_1) + case e_SHA1: +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case e_SHA224: +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case e_SHA256: +#endif // PSA_WANT_ALG_SHA_256 + break; + default: + // State must have not been initialized by the setup function. + return PSA_ERROR_BAD_STATE; + } + + if (input_length == 0) { + return PSA_SUCCESS; + } + + state = block_t_convert((uint8_t*)operation->state, + sx_hash_get_state_size(operation->hash_type)); + + // Same blocksize for all of SHA-256, SHA-224, and SHA-256. + left = (operation->total & (SHA256_BLOCKSIZE - 1)); + fill = SHA256_BLOCKSIZE - left; + + operation->total += input_length; + + if ((left > 0) && (input_length >= fill)) { + memcpy((void *)(operation->buffer + left), input, fill); + + data_in = block_t_convert(operation->buffer, SHA256_BLOCKSIZE); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_hash_update_blk(operation->hash_type, state, data_in); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + input += fill; + input_length -= fill; + left = 0; + } + + if (input_length >= SHA256_BLOCKSIZE) { + blocks = input_length / SHA256_BLOCKSIZE; + + data_in = block_t_convert((uint8_t*)input, SHA256_BLOCKSIZE * blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_hash_update_blk(operation->hash_type, state, data_in); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + input += SHA256_BLOCKSIZE * blocks; + input_length -= SHA256_BLOCKSIZE * blocks; + } + + if (input_length > 0) { + memcpy((void *)(operation->buffer + left), input, input_length); + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + (void)input; + (void)input_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_finish(sli_cryptoacc_transparent_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + psa_status_t status; + uint32_t sx_ret; + block_t state; + block_t data_in; + block_t data_out; + + if (operation == NULL + || (hash_length == NULL && hash_size > 0) + || (hash == NULL && hash_size > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (operation->hash_type) { +#if defined(PSA_WANT_ALG_SHA_1) + case e_SHA1: +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case e_SHA224: +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case e_SHA256: +#endif // PSA_WANT_ALG_SHA_256 + break; + default: + // State must have not been initialized by the setup function. + return PSA_ERROR_BAD_STATE; + } + + if (hash_size < sx_hash_get_digest_size(operation->hash_type)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + state = block_t_convert((uint8_t*)operation->state, + sx_hash_get_state_size(operation->hash_type)); + data_in = block_t_convert((uint8_t*)operation->buffer, + (operation->total & (SHA256_BLOCKSIZE - 1))); + + data_out = block_t_convert((uint8_t*)operation->state, + sx_hash_get_state_size(operation->hash_type)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_hash_finish_blk(operation->hash_type, + state, + data_in, + data_out, + operation->total); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *hash_length = sx_hash_get_digest_size(operation->hash_type); + memcpy(hash, operation->state, *hash_length); + memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + (void)hash; + (void)hash_size; + (void)hash_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_abort(sli_cryptoacc_transparent_hash_operation_t *operation) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + if (operation != NULL) { + // Accelerator does not keep state, so just zero out the context and we're good. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_compute(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + psa_status_t status; + uint32_t sx_ret = CRYPTOLIB_INVALID_PARAM; + block_t data_in; + block_t data_out; + + if ((input == NULL && input_length > 0) + || (hash == NULL && hash_size > 0) + || (hash_length == NULL && hash_size > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (alg) { +#if defined(PSA_WANT_ALG_SHA_1) + case PSA_ALG_SHA_1: + if (hash_size < SHA1_DIGESTSIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + break; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case PSA_ALG_SHA_224: + if (hash_size < SHA224_DIGESTSIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + break; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case PSA_ALG_SHA_256: + if (hash_size < SHA256_DIGESTSIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + break; +#endif // PSA_WANT_ALG_SHA_256 + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(hash, hash_size); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + switch (alg) { +#if defined(PSA_WANT_ALG_SHA_1) + case PSA_ALG_SHA_1: + sx_ret = sx_hash_blk(e_SHA1, data_in, data_out); + *hash_length = SHA1_DIGESTSIZE; + break; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case PSA_ALG_SHA_224: + sx_ret = sx_hash_blk(e_SHA224, data_in, data_out); + *hash_length = SHA224_DIGESTSIZE; + break; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case PSA_ALG_SHA_256: + sx_ret = sx_hash_blk(e_SHA256, data_in, data_out); + *hash_length = SHA256_DIGESTSIZE; + break; +#endif // PSA_WANT_ALG_SHA_256 + } + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + *hash_length = 0; + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)alg; + (void)input; + (void)input_length; + (void)hash; + (void)hash_size; + (void)hash_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_clone(const sli_cryptoacc_transparent_hash_operation_t *source_operation, + sli_cryptoacc_transparent_hash_operation_t *target_operation) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + if (source_operation == NULL + || target_operation == NULL) { + return PSA_ERROR_BAD_STATE; + } + + // Source operation must be active (setup has been called) + if (source_operation->hash_type == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Target operation must be inactive (setup has not been called) + if (target_operation->hash_type != 0) { + return PSA_ERROR_BAD_STATE; + } + + // The operation context does not contain any pointers, and the target operation + // have already have been initialized, so we can do a direct copy. + *target_operation = *source_operation; + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)source_operation; + (void)target_operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c new file mode 100644 index 000000000..ed9130497 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c @@ -0,0 +1,196 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Key Derivation functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "sli_psa_driver_common.h" // sli_psa_zeroize +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" + +#include "sx_dh_alg.h" +#include "sx_ecc_curves.h" +#include "sx_errors.h" +#include "cryptolib_types.h" +#include + +// ----------------------------------------------------------------------------- +// Driver entry points + +psa_status_t sli_cryptoacc_transparent_key_agreement( + psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECDH) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || peer_key == NULL + || output == NULL + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + uint32_t curve_flags = 0; + block_t domain = NULL_blk; + uint8_t tmp_output_buf[64] = { 0 }; + size_t key_bits = psa_get_key_bits(attributes); + psa_key_type_t key_type = psa_get_key_type(attributes); + + // Check that key_buffer contains private key. + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(key_type)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Only accelerate ECDH over secp{192, 224, 256}r1 and secp256k1 curves. + if (!PSA_ALG_IS_ECDH(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (key_type != PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { + return PSA_ERROR_NOT_SUPPORTED; + } + curve_flags = sx_ecc_curve_p192.pk_flags; + domain = block_t_convert(sx_ecc_curve_p192.params.addr, + 6 * sx_ecc_curve_p192.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (key_type != PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { + return PSA_ERROR_NOT_SUPPORTED; + } + curve_flags = sx_ecc_curve_p224.pk_flags; + domain = block_t_convert(sx_ecc_curve_p224.params.addr, + 6 * sx_ecc_curve_p224.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + if (key_type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { + curve_flags = sx_ecc_curve_p256.pk_flags; + domain = block_t_convert(sx_ecc_curve_p256.params.addr, + 6 * sx_ecc_curve_p256.bytesize); + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + if (key_type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_K1)) { + curve_flags = sx_ecc_curve_p256k1.pk_flags; + domain = block_t_convert(sx_ecc_curve_p256k1.params.addr, + 6 * sx_ecc_curve_p256k1.bytesize); + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check input-keys sizes. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits) + || peer_key_length < PSA_BITS_TO_BYTES(key_bits) * 2 + 1) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if (output_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t pub = block_t_convert(peer_key + 1, PSA_BITS_TO_BYTES(key_bits) * 2); + block_t shared_key = block_t_convert(tmp_output_buf, PSA_BITS_TO_BYTES(key_bits) * 2); + + // Check peer_key is a public key of correct format. + if (peer_key[0] != 0x04) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Compute shared key. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = dh_shared_key_ecdh(domain, priv, pub, shared_key, PSA_BITS_TO_BYTES(key_bits), curve_flags); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + // If the ECDH libcryptosoc operation failed, this is most likely due to + // the peer key being an invalid elliptic curve point. Other sources for + // failure should hopefully have been caught during parameter validation. + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(output, tmp_output_buf, PSA_BITS_TO_BYTES(key_bits)); + sli_psa_zeroize(tmp_output_buf, sizeof(tmp_output_buf)); + *output_length = PSA_BITS_TO_BYTES(key_bits); + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECDH + + (void) alg; + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) peer_key; + (void) peer_key_length; + (void) output; + (void) output_size; + (void) output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECDH +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c new file mode 100644 index 000000000..db49f1db5 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c @@ -0,0 +1,484 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Key Management functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "cryptoacc_management.h" + +#include "sli_psa_driver_common.h" +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_errors.h" +#include "sx_ecc_curves.h" +#include "sx_ecc_keygen_alg.h" +#include "sx_primitives.h" + +#include + +// ----------------------------------------------------------------------------- +// Driver entry points + +psa_status_t sli_cryptoacc_transparent_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || key_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + // Check key type. PSA Crypto defines generate_key to be an invalid call with a key type + // of public key. + if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // We currently only support R1 or K1 + if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check sufficient buffer size. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Grab the correct order for the requested curve + block_t n = NULL_blk; + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + // The order n is stored as the second element in the curve-parameter tuple + // consisting of (q, n, Gx, Gy, a, b). The length of the parameters is + // dependent on the length of the corresponding key. + n = block_t_convert(sx_ecc_curve_p192.params.addr + (1 * sx_ecc_curve_p192.bytesize), + sx_ecc_curve_p192.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + n = block_t_convert(sx_ecc_curve_p224.params.addr + (1 * sx_ecc_curve_p224.bytesize), + sx_ecc_curve_p224.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + n = block_t_convert(sx_ecc_curve_p256.params.addr + (1 * sx_ecc_curve_p256.bytesize), + sx_ecc_curve_p256.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + n = block_t_convert(sx_ecc_curve_p256k1.params.addr + (1 * sx_ecc_curve_p256k1.bytesize), + sx_ecc_curve_p256k1.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + + // Get random number < n -> private key. + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + uint32_t sx_ret = ecc_generate_private_key(n, + priv, + sli_cryptoacc_trng_wrapper); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *key_length = PSA_BITS_TO_BYTES(key_bits); + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) key_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +psa_status_t sli_cryptoacc_transparent_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || data == NULL + || data_size == 0 + || data_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + // If the key is stored transparently and is already a public key, + // let the core handle it. + if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (!PSA_KEY_TYPE_IS_ECC(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // We currently only support R1 or K1 + if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if (data_size < PSA_BITS_TO_BYTES(key_bits) * 2 + 1) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t *domain_ptr = NULL; + uint32_t curve_flags = 0; + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p192.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p192.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p224.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p224.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + curve_flags = sx_ecc_curve_p256.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + curve_flags = sx_ecc_curve_p256k1.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256k1.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t pub = block_t_convert(data + 1, PSA_BITS_TO_BYTES(key_bits) * 2); + + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + uint32_t sx_ret = ecc_generate_public_key(*domain_ptr, + pub, + priv, + PSA_BITS_TO_BYTES(key_bits), + curve_flags); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + data[0] = 0x04; + *data_length = PSA_BITS_TO_BYTES(key_bits) * 2 + 1; + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) data; + (void) data_size; + (void) data_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +psa_status_t sli_cryptoacc_transparent_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + // Argument check. + if (attributes == NULL + || data == NULL + || data_length == 0 + || bits == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + + // Transparent driver is not involved in validation of symmetric keys. + if (!PSA_KEY_TYPE_IS_ECC(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // We currently only support R1 or K1 + if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { // Private key. + void *modulus_ptr = NULL; + *bits = psa_get_key_bits(attributes); + + // Determine key bit-size + if (*bits == 0) { + *bits = data_length * 8; + } else { + if (PSA_BITS_TO_BYTES(*bits) != data_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + switch (*bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + // The order n is stored as the second element in the curve-parameter tuple + // consisting of (q, n, Gx, Gy, a, b). The length of the parameters is + // dependent on the length of the corresponding key. + modulus_ptr = sx_ecc_curve_p192.params.addr + (1 * sx_ecc_curve_p192.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + modulus_ptr = sx_ecc_curve_p224.params.addr + (1 * sx_ecc_curve_p224.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + modulus_ptr = sx_ecc_curve_p256.params.addr + (1 * sx_ecc_curve_p256.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + modulus_ptr = sx_ecc_curve_p256k1.params.addr + (1 * sx_ecc_curve_p256k1.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + status = sli_psa_validate_ecc_weierstrass_privkey(data, + modulus_ptr, + data_length); + } else { // Public key. + block_t *domain_ptr = NULL; + uint32_t curve_flags = 0; + + // Check that uncompressed representation is given. + if (data[0] != 0x04) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Determine key bit size. + *bits = (data_length - 1) * 8 / 2; + + switch (*bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p192.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p192.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p224.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p224.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + curve_flags = sx_ecc_curve_p256.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + curve_flags = sx_ecc_curve_p256k1.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256k1.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + block_t point = block_t_convert(data + 1, PSA_BITS_TO_BYTES(*bits) * 2); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + uint32_t sx_ret = ecc_is_point_on_curve(*domain_ptr, + point, + PSA_BITS_TO_BYTES(*bits), + curve_flags); + status = cryptoacc_management_release(); + if (status != PSA_SUCCESS) { + return status; + } + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; + } else { + status = PSA_SUCCESS; + } + } + + if ( status == PSA_SUCCESS ) { + if ( key_buffer_size >= data_length ) { + memcpy(key_buffer, data, data_length); + *key_buffer_length = data_length; + } else { + status = PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + return status; + +#else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) attributes; + (void) data; + (void) data_length; + (void) key_buffer; + (void) key_buffer_size; + (void) key_buffer_length; + (void) bits; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c new file mode 100644 index 000000000..109bb9dd9 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c @@ -0,0 +1,740 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Mac functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_functions.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" +#include "sx_aes.h" +#include "sx_hash.h" +#include "sx_errors.h" +#include + +#if defined(PSA_WANT_ALG_HMAC) +static psa_status_t sli_cryptoacc_hmac_validate_key( + const psa_key_attributes_t *attributes, + psa_algorithm_t alg, + sx_hash_fct_t *hash_fct, + size_t *digest_length) +{ + // Check key type and output size + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_HMAC) { + // For HMAC, key type is strictly enforced + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (PSA_ALG_HMAC_GET_HASH(alg)) { + case PSA_ALG_SHA_1: + *hash_fct = e_SHA1; + *digest_length = 20; + break; + case PSA_ALG_SHA_224: + *hash_fct = e_SHA224; + *digest_length = 28; + break; + case PSA_ALG_SHA_256: + *hash_fct = e_SHA256; + *digest_length = 32; + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_HMAC + +#if defined(PSA_WANT_ALG_CMAC) +static psa_status_t sli_cryptoacc_cmac_validate_key( + const psa_key_attributes_t *attributes) +{ + // Check key type and size + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + // CMAC could be used with DES + return PSA_ERROR_NOT_SUPPORTED; + } + + switch (psa_get_key_bits(attributes) / 8) { + case 16: + case 24: + case 32: + break; + default: + // There's no other AES algorithm in existence + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_CMAC + +psa_status_t sli_cryptoacc_transparent_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (key_buffer == NULL + || attributes == NULL + || mac == NULL + || mac_length == NULL + || ((input == NULL) && (input_length > 0))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + uint32_t sx_ret; + size_t key_size = psa_get_key_bits(attributes) / 8; + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + sx_hash_fct_t sx_hash_alg; + size_t digest_length; + + status = sli_cryptoacc_hmac_validate_key(attributes, alg, &sx_hash_alg, &digest_length); + if (status != PSA_SUCCESS) { + return status; + } + + if ((PSA_MAC_TRUNCATED_LENGTH(alg) > 0) + && (PSA_MAC_TRUNCATED_LENGTH(alg) < digest_length)) { + digest_length = PSA_MAC_TRUNCATED_LENGTH(alg); + } + + if (mac_size < digest_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // Execute the HMAC operation + sx_ret = sx_hmac_blk(sx_hash_alg, + block_t_convert(key_buffer, key_size), + block_t_convert(input, input_length), + block_t_convert(mac, digest_length)); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (status != PSA_SUCCESS) { + return status; + } + + // Report generated hmac length + *mac_length = digest_length; + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_HMAC + + // If not HMAC, continue with the regular MAC algos + switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + { + status = sli_cryptoacc_cmac_validate_key(attributes); + if (status != PSA_SUCCESS) { + return status; + } + + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t output_length = PSA_MAC_TRUNCATED_LENGTH(alg); + if (output_length == 0) { + output_length = 16; + } else if (output_length > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (mac_size < output_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + uint8_t sx_mac_buf[BLK_CIPHER_MAC_SIZE]; + + // Setup DMA descriptors + block_t key_sxblk = block_t_convert(key_buffer, key_size); + block_t input_sxblk = block_t_convert(input, input_length); + block_t mac_sxblk = block_t_convert(sx_mac_buf, BLK_CIPHER_MAC_SIZE); + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // Execute the CMAC operation + sx_ret = sx_aes_cmac_generate((const block_t *)&key_sxblk, + (const block_t *)&input_sxblk, + &mac_sxblk); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + status = PSA_ERROR_HARDWARE_FAILURE; + } + + if (status == PSA_SUCCESS) { + memcpy(mac, sx_mac_buf, output_length); + *mac_length = output_length; + } else { + *mac_length = 0; + } + + memset(sx_mac_buf, 0, BLK_CIPHER_MAC_SIZE); + break; + } +#endif // PSA_WANT_ALG_CMAC + default: + status = PSA_ERROR_NOT_SUPPORTED; + } + +#if !defined(PSA_WANT_ALG_CMAC) + (void)key_buffer_size; +#endif // !PSA_WANT_ALG_CMAC + + return status; + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +// Make sure that the two locations of 'alg' are in the same place, since we access them +// interchangeably. +#if defined(PSA_WANT_ALG_HMAC) +_Static_assert(offsetof(sli_cryptoacc_transparent_mac_operation_t, hmac.alg) + == offsetof(sli_cryptoacc_transparent_mac_operation_t, cipher_mac.alg), + "hmac.alg and cipher_mac.alg are not aliases"); +#endif // PSA_WANT_ALG_HMAC + +psa_status_t sli_cryptoacc_transparent_mac_sign_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (operation == NULL + || attributes == NULL + || (key_buffer == NULL && key_buffer_size > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t key_size = psa_get_key_bits(attributes) / 8; + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + + if (key_size > key_buffer_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // start by resetting context + memset(operation, 0, sizeof(*operation)); + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + sx_hash_fct_t sx_hash_alg; + size_t digest_length; + status = sli_cryptoacc_hmac_validate_key(attributes, alg, &sx_hash_alg, &digest_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (PSA_MAC_TRUNCATED_LENGTH(alg) > digest_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // CRYPTOACC does not support multipart HMAC. Construct it from hashing instead. + psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH(alg); + + // Reduce the key if larger than a block + if (key_size > sizeof(operation->hmac.opad)) { + status = sli_cryptoacc_transparent_hash_compute( + hash_alg, + key_buffer, + key_size, + operation->hmac.opad, + sizeof(operation->hmac.opad), + &key_size); + if (status != PSA_SUCCESS) { + return status; + } + } else if (key_size > 0) { + memcpy(operation->hmac.opad, key_buffer, key_size); + } + + // Calculate inner padding in opad buffer and start a multipart hash with it + for (size_t i = 0; i < key_size; i++) { + operation->hmac.opad[i] ^= 0x36; + } + memset(&operation->hmac.opad[key_size], 0x36, sizeof(operation->hmac.opad) - key_size); + + status = sli_cryptoacc_transparent_hash_setup( + &operation->hmac.hash_ctx, + hash_alg); + if (status != PSA_SUCCESS) { + return status; + } + + status = sli_cryptoacc_transparent_hash_update( + &operation->hmac.hash_ctx, + operation->hmac.opad, sizeof(operation->hmac.opad)); + if (status != PSA_SUCCESS) { + return status; + } + + // Calculate outer padding and store it for finalisation + for (size_t i = 0; i < sizeof(operation->hmac.opad); i++) { + operation->hmac.opad[i] ^= 0x36 ^ 0x5C; + } + + operation->hmac.alg = alg; + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_HMAC + + // If not HMAC, check other algos + switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + status = sli_cryptoacc_cmac_validate_key(attributes); + if (status != PSA_SUCCESS) { + return status; + } + + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(operation->cipher_mac.key, key_buffer, key_size); + operation->cipher_mac.key_len = key_size; + + operation->cipher_mac.alg = alg; + status = PSA_SUCCESS; + break; +#endif // PSA_WANT_ALG_CMAC + default: + status = PSA_ERROR_NOT_SUPPORTED; + break; + } + +#if !defined(PSA_WANT_ALG_CMAC) + (void)key_buffer_size; +#endif // !PSA_WANT_ALG_CMAC + + return status; + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +psa_status_t sli_cryptoacc_transparent_mac_verify_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + // Since the PSA Crypto core exposes the verify functionality of the drivers without + // actually implementing the fallback to 'sign' when the driver doesn't support verify, + // we need to do this ourselves for the time being. + return sli_cryptoacc_transparent_mac_sign_setup(operation, + attributes, + key_buffer, + key_buffer_size, + alg); +} + +#if defined(PSA_WANT_ALG_CMAC) +static psa_status_t cryptoacc_cmac_update_blk(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *input, size_t input_length) +{ + psa_status_t status; + uint32_t sx_ret; + + const block_t key_blk = block_t_convert(operation->cipher_mac.key, operation->cipher_mac.key_len); + const block_t input_blk = block_t_convert(input, input_length); + block_t ctx_blk = block_t_convert(operation->cipher_mac.cmac_ctx, sizeof(operation->cipher_mac.cmac_ctx)); + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // CMAC state context is already initialized, do update. + sx_ret = sx_aes_cmac_generate_update(&key_blk, + &input_blk, + (const block_t*)&ctx_blk, + &ctx_blk); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (status != PSA_SUCCESS) { + return status; + } + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_CMAC + +psa_status_t sli_cryptoacc_transparent_mac_update(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (operation == NULL + || input == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (input_length == 0 ) { + return PSA_SUCCESS; + } + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { + return sli_cryptoacc_transparent_hash_update( + &operation->hmac.hash_ctx, + input, + input_length); + } +#endif // PSA_WANT_ALG_HMAC + + switch (PSA_ALG_FULL_LENGTH_MAC(operation->cipher_mac.alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + { + psa_status_t status; + size_t current_block_len; + + // if the potential last block include data + // we need to process them first + current_block_len = operation->cipher_mac.current_block_len; + if (current_block_len) { + size_t bytes_to_boundary = 16 - current_block_len; + // if the total of bytes is smaller than a block, just copy and return + // else fill up the potential last block + if (input_length < bytes_to_boundary) { + memcpy(&operation->cipher_mac.current_block[current_block_len], input, input_length); + operation->cipher_mac.current_block_len = current_block_len + input_length; + return PSA_SUCCESS; + } else { + // fill up the potential last block + memcpy(&operation->cipher_mac.current_block[current_block_len], input, bytes_to_boundary); + operation->cipher_mac.current_block_len = 16; + input_length -= bytes_to_boundary; + input += bytes_to_boundary; + } + + // if there are more input data, the potential last block is not + // the last block, which means we can process it now, + if (input_length) { + // Execute CMAC operation on the single context block + status = cryptoacc_cmac_update_blk(operation, operation->cipher_mac.current_block, 16); + if (status != PSA_SUCCESS) { + return status; + } + operation->cipher_mac.current_block_len = 0; + } + } + + // Process complete input blocks + if (input_length > 16) { + // Calculate the number of bytes in complete blocks to process. + // If the last block is complete we need to postpone processing it + // since it may be the last block which should go to sx_aes_cmac_generate_final. + size_t bytes_to_copy = (input_length - 1) & ~0xFUL; + + // Execute CMAC operation on the single context block + status = cryptoacc_cmac_update_blk(operation, input, bytes_to_copy); + if (status != PSA_SUCCESS) { + return status; + } + + input_length -= bytes_to_copy; + input += bytes_to_copy; + } + + // Store remaining input bytes + if (input_length) { + memcpy(operation->cipher_mac.current_block, input, input_length); + operation->cipher_mac.current_block_len = input_length; + } + + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_CMAC + default: + return PSA_ERROR_BAD_STATE; + } + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + (void)input; + (void)input_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +psa_status_t sli_cryptoacc_transparent_mac_sign_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (operation == NULL + || mac == NULL + || mac_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { + uint8_t buffer[64 + 32]; + size_t olen; + + // Construct outer hash input from opad and hash result + memcpy(buffer, operation->hmac.opad, sizeof(operation->hmac.opad)); + memset(operation->hmac.opad, 0, sizeof(operation->hmac.opad)); + + status = sli_cryptoacc_transparent_hash_finish( + &operation->hmac.hash_ctx, + &buffer[sizeof(operation->hmac.opad)], + sizeof(buffer) - sizeof(operation->hmac.opad), + &olen); + + if (status != PSA_SUCCESS) { + return status; + } + + // Calculate HMAC + status = sli_cryptoacc_transparent_hash_compute( + PSA_ALG_HMAC_GET_HASH(operation->hmac.alg), + buffer, + sizeof(operation->hmac.opad) + olen, + buffer, + sizeof(buffer), + &olen); + if (status != PSA_SUCCESS) { + return status; + } + + // Copy out a potentially truncated HMAC + size_t requested_length = PSA_MAC_TRUNCATED_LENGTH(operation->hmac.alg); + if (requested_length == 0) { + requested_length = olen; + } + + if (requested_length > mac_size) { + memset(buffer, 0, sizeof(buffer)); + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(mac, buffer, requested_length); + *mac_length = requested_length; + memset(buffer, 0, sizeof(buffer)); + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_HMAC + + // Check algorithm and store if supported + switch (PSA_ALG_FULL_LENGTH_MAC(operation->cipher_mac.alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + { + // Check output size + size_t requested_length = PSA_MAC_TRUNCATED_LENGTH(operation->cipher_mac.alg); + if (requested_length == 0) { + requested_length = BLK_CIPHER_MAC_SIZE; + } else if (requested_length > BLK_CIPHER_MAC_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (mac_size < requested_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // Setup DMA descriptors + block_t input_blk = block_t_convert(operation->cipher_mac.current_block, + operation->cipher_mac.current_block_len); + const block_t key_blk = block_t_convert(operation->cipher_mac.key, operation->cipher_mac.key_len); + block_t ctx_blk = block_t_convert(operation->cipher_mac.cmac_ctx, sizeof(operation->cipher_mac.cmac_ctx)); + + // Execute the first CMAC operation. + // Receive the final mac in the cmac_ctx buffer and copy the requested + // number of bytes to the user buffer after. + uint32_t sx_ret = sx_aes_cmac_generate_final(&key_blk, + (const block_t *)&input_blk, + (const block_t *)&ctx_blk, + &ctx_blk); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (status != PSA_SUCCESS) { + return status; + } + + // Copy the requested number of bytes (max 16 for CMAC) to the user buffer. + memcpy(mac, operation->cipher_mac.cmac_ctx, requested_length); + *mac_length = requested_length; + + return PSA_SUCCESS; + } + break; +#endif // PSA_WANT_ALG_CMAC + default: + return PSA_ERROR_NOT_SUPPORTED; + } + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +psa_status_t sli_cryptoacc_transparent_mac_verify_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length) +{ + // Since the PSA Crypto core exposes the verify functionality of the drivers without + // actually implementing the fallback to 'sign' when the driver doesn't support verify, + // we need to do this ourselves for the time being. + uint8_t calculated_mac[PSA_MAC_MAX_SIZE] = { 0 }; + size_t calculated_length = PSA_MAC_MAX_SIZE; + + psa_status_t status = sli_cryptoacc_transparent_mac_sign_finish( + operation, + calculated_mac, sizeof(calculated_mac), &calculated_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (mac_length > sizeof(calculated_mac)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (sli_psa_safer_memcmp(mac, calculated_mac, mac_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + } else { + status = PSA_SUCCESS; + } + + memset(calculated_mac, 0, sizeof(calculated_mac)); + return status; +} + +psa_status_t sli_cryptoacc_transparent_mac_abort(sli_cryptoacc_transparent_mac_operation_t *operation) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + // There's no state in hardware that we need to preserve, so zeroing out the context suffices. + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c new file mode 100644 index 000000000..62471b12b --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c @@ -0,0 +1,336 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Signature functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "cryptoacc_management.h" + +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_errors.h" +#include "sx_ecdsa_alg.h" +#include "sx_ecc_keygen_alg.h" + +// ----------------------------------------------------------------------------- +// Driver entry points + +psa_status_t sli_cryptoacc_transparent_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || hash == NULL + || hash_length == 0 + || signature == NULL + || signature_size == 0 + || signature_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check the requested algorithm is ECDSA with randomized k. + if (!PSA_ALG_IS_RANDOMIZED_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + // Not able to sign using non-ECC keys, or using public keys. + return PSA_ERROR_INVALID_ARGUMENT; + } + + sx_ecc_curve_t *curve = NULL; + + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p192; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p224; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p256; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + if (curve_type == PSA_ECC_FAMILY_SECP_K1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p256k1; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check sufficient output buffer size. + if (signature_size < PSA_ECDSA_SIGNATURE_SIZE(key_bits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t data_in = block_t_convert(hash, hash_length); + block_t data_out = block_t_convert(signature, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + uint32_t sx_ret = ecdsa_generate_signature_digest(curve, + data_in, + priv, + data_out, + sli_cryptoacc_trng_wrapper); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *signature_length = PSA_ECDSA_SIGNATURE_SIZE(key_bits); + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECDSA + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_size; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECDSA +} + +psa_status_t sli_cryptoacc_transparent_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || hash == NULL + || hash_length == 0 + || (signature == NULL && signature_length != 0) ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + if (!PSA_KEY_TYPE_IS_ECC(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (PSA_ALG_IS_RSA_PSS(alg) || PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { + // We shouldn't have a RSA-type alg for a ECC key. + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (!PSA_ALG_IS_ECDSA(alg)) { + // We only support ECDSA. + return PSA_ERROR_NOT_SUPPORTED; + } + + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (signature_length == 0) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + uint32_t curve_flags = 0; + sx_ecc_curve_t *curve_ptr = NULL; + + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p192; + curve_flags = sx_ecc_curve_p192.pk_flags; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p224; + curve_flags = sx_ecc_curve_p224.pk_flags; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p256; + curve_flags = sx_ecc_curve_p256.pk_flags; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + if (curve_type == PSA_ECC_FAMILY_SECP_K1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p256k1; + curve_flags = sx_ecc_curve_p256k1.pk_flags; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + if (signature_length != PSA_ECDSA_SIGNATURE_SIZE(key_bits)) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + // Export public key if necessary. + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t pub = NULL_blk; + uint8_t pub_buf[64] = { 0 }; + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + block_t curve = block_t_convert(curve_ptr->params.addr, 6 * PSA_BITS_TO_BYTES(key_bits)); + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + pub = block_t_convert(pub_buf, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + + // Perform point multiplication in order to get public key. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = ecc_generate_public_key(curve, pub, priv, PSA_BITS_TO_BYTES(key_bits), curve_flags); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } else { + pub = block_t_convert(key_buffer + 1, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + } + + block_t digest = block_t_convert(hash, hash_length); + block_t signature_internal = block_t_convert(signature, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = ecdsa_verify_signature_digest(curve_ptr, + digest, + pub, + signature_internal); + status = cryptoacc_management_release(); + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return PSA_ERROR_INVALID_SIGNATURE; + } + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECDSA + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECDSA +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c new file mode 100644 index 000000000..83c3e32ae --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c @@ -0,0 +1,65 @@ +/***************************************************************************/ /** + * @file + * @brief PSA Driver common utility functions + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_common.h" + +#include "constant_time_internal.h" +#include "constant_time_impl.h" + +//------------------------------------------------------------------------------ +// Function definitions + +psa_status_t sli_psa_validate_pkcs7_padding(uint8_t *padded_data, + size_t padded_data_length, + size_t *padding_bytes) +{ + size_t i, pad_idx; + unsigned char padding_len; + + padding_len = padded_data[padded_data_length - 1]; + *padding_bytes = padding_len; + + mbedtls_ct_condition_t bad = + mbedtls_ct_uint_gt(padding_len, padded_data_length); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); + + // The number of bytes checked must be independent of padding_len, so pick + // input_len, which is 16 bytes (one block) for our use cases. + pad_idx = padded_data_length - padding_len; + for (i = 0; i < padded_data_length; i++) { + mbedtls_ct_condition_t in_padding = mbedtls_ct_uint_ge(i, pad_idx); + mbedtls_ct_condition_t different = + mbedtls_ct_uint_ne(padded_data[i], padding_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool_and(in_padding, different)); + } + + return (psa_status_t)mbedtls_ct_error_if_else_0(bad, + PSA_ERROR_INVALID_PADDING); +} diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_ghash.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_ghash.c new file mode 100644 index 000000000..d6d2a292d --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_ghash.c @@ -0,0 +1,162 @@ +/***************************************************************************//** + * @file + * @brief PSA Driver software GHASH support + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_PSA_DRIVER_FEATURE_GCM_IV_CALCULATION) + +#include "psa/crypto.h" + +#include "sli_psa_driver_common.h" + +// ----------------------------------------------------------------------------- +// Macros + +#ifndef GET_UINT32_BE +#define GET_UINT32_BE(n, b, i) \ + { \ + (n) = ( (uint32_t) (b)[(i)] << 24) \ + | ( (uint32_t) (b)[(i) + 1] << 16) \ + | ( (uint32_t) (b)[(i) + 2] << 8) \ + | ( (uint32_t) (b)[(i) + 3]); \ + } +#endif + +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n, b, i) \ + { \ + (b)[(i)] = (unsigned char) ( (n) >> 24); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ + } +#endif + +// ----------------------------------------------------------------------------- +// Static constants + +static const uint64_t last4[16] = +{ + 0x0000, 0x1c20, 0x3840, 0x2460, + 0x7080, 0x6ca0, 0x48c0, 0x54e0, + 0xe100, 0xfd20, 0xd940, 0xc560, + 0x9180, 0x8da0, 0xa9c0, 0xb5e0 +}; + +// ----------------------------------------------------------------------------- +// Global functions + +void sli_psa_software_ghash_setup(const uint8_t Ek[16], + uint64_t HL[16], + uint64_t HH[16]) +{ + int i, j; + uint64_t hi, lo; + uint64_t vl, vh; + + /* pack Ek as two 64-bits ints, big-endian */ + GET_UINT32_BE(hi, Ek, 0); + GET_UINT32_BE(lo, Ek, 4); + vh = (uint64_t) hi << 32 | lo; + + GET_UINT32_BE(hi, Ek, 8); + GET_UINT32_BE(lo, Ek, 12); + vl = (uint64_t) hi << 32 | lo; + + /* 8 = 1000 corresponds to 1 in GF(2^128) */ + HL[8] = vl; + HH[8] = vh; + + /* 0 corresponds to 0 in GF(2^128) */ + HH[0] = 0; + HL[0] = 0; + + for ( i = 4; i > 0; i >>= 1 ) { + uint32_t T = (vl & 1) * 0xe1000000U; + vl = (vh << 63) | (vl >> 1); + vh = (vh >> 1) ^ ( (uint64_t) T << 32); + + HL[i] = vl; + HH[i] = vh; + } + + for ( i = 2; i <= 8; i *= 2 ) { + uint64_t *HiL = HL + i, *HiH = HH + i; + vh = *HiH; + vl = *HiL; + for ( j = 1; j < i; j++ ) { + HiH[j] = vh ^ HH[j]; + HiL[j] = vl ^ HL[j]; + } + } +} + +void sli_psa_software_ghash_multiply(const uint64_t HL[16], + const uint64_t HH[16], + uint8_t output[16], + const uint8_t input[16]) +{ + int i = 0; + unsigned char lo, hi, rem; + uint64_t zh, zl; + + lo = input[15] & 0xf; + + zh = HH[lo]; + zl = HL[lo]; + + for ( i = 15; i >= 0; i-- ) { + lo = input[i] & 0xf; + hi = (input[i] >> 4) & 0xf; + + if ( i != 15 ) { + rem = (unsigned char) zl & 0xf; + zl = (zh << 60) | (zl >> 4); + zh = (zh >> 4); + zh ^= (uint64_t) last4[rem] << 48; + zh ^= HH[lo]; + zl ^= HL[lo]; + } + + rem = (unsigned char) zl & 0xf; + zl = (zh << 60) | (zl >> 4); + zh = (zh >> 4); + zh ^= (uint64_t) last4[rem] << 48; + zh ^= HH[hi]; + zl ^= HL[hi]; + } + + PUT_UINT32_BE(zh >> 32, output, 0); + PUT_UINT32_BE(zh, output, 4); + PUT_UINT32_BE(zl >> 32, output, 8); + PUT_UINT32_BE(zl, output, 12); +} + +#endif // SLI_PSA_DRIVER_FEATURE_GCM_IV_CALCULATION diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c new file mode 100644 index 000000000..f53587736 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c @@ -0,0 +1,114 @@ +/***************************************************************************//** + * @file + * @brief PSA Driver initialization interface. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#include "psa/crypto.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #include "sli_se_transparent_functions.h" + #include "sl_se_manager.h" + #include "sli_se_opaque_functions.h" +#endif // SLI_MBEDTLS_DEVICE_HSE + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + #include "sli_cryptoacc_transparent_functions.h" + #include "cryptoacc_management.h" +#endif // SLI_MBEDTLS_DEVICE_VSE + +// ----------------------------------------------------------------------------- +// Driver entry points + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +psa_status_t sli_se_transparent_driver_init(void) +{ + sl_status_t sl_status = sl_se_init(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +psa_status_t sli_se_transparent_driver_deinit(void) +{ + sl_status_t sl_status = sl_se_deinit(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +psa_status_t sli_se_opaque_driver_init(void) +{ + sl_status_t sl_status = sl_se_init(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +psa_status_t sli_se_opaque_driver_deinit(void) +{ + sl_status_t sl_status = sl_se_deinit(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + +#elif defined(SLI_MBEDTLS_DEVICE_VSE) + +psa_status_t sli_cryptoacc_transparent_driver_init(void) +{ + // Consider moving the clock init and etc. here, which is performed by the + // management functions. + + #if defined(SLI_MBEDTLS_DEVICE_VSE_V2) + return cryptoacc_initialize_countermeasures(); + #else + return PSA_SUCCESS; + #endif +} + +psa_status_t sli_cryptoacc_transparent_driver_deinit(void) +{ + return PSA_SUCCESS; +} + +#endif diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c new file mode 100644 index 000000000..88af97416 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c @@ -0,0 +1,160 @@ +/***************************************************************************//** + * @file + * @brief Default PSA TRNG hook for Silicon Labs devices. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) || defined(MBEDTLS_ENTROPY_HARDWARE_ALT) + +#include "psa/crypto.h" +#include "psa/crypto_extra.h" +#include "psa/crypto_platform.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #include "sl_se_manager.h" + #include "sl_se_manager_entropy.h" +#elif defined(SLI_MBEDTLS_DEVICE_VSE) + #include "sli_cryptoacc_driver_trng.h" +#elif defined(SLI_TRNG_DEVICE_SI91X) + #include "sl_si91x_psa_trng.h" +#endif + +// ----------------------------------------------------------------------------- +// Typedefs + +#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +typedef void mbedtls_psa_external_random_context_t; +#endif + +// ----------------------------------------------------------------------------- +// Static functions + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +static psa_status_t se_get_random(unsigned char *output, + size_t len, + size_t *out_len) +{ + sl_status_t ret; + sl_se_command_context_t cmd_ctx; + + // Initialize the SE manager. + ret = sl_se_init(); + if (ret != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Initialize command context + ret = sl_se_init_command_context(&cmd_ctx); + if (ret != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Get entropy + ret = sl_se_get_random(&cmd_ctx, output, len); + + if (ret == SL_STATUS_OK) { + *out_len = len; + return PSA_SUCCESS; + } + + *out_len = 0; + return PSA_ERROR_HARDWARE_FAILURE; +} + +#endif // SLI_MBEDTLS_DEVICE_HSE + +// ----------------------------------------------------------------------------- +// Global entry points + +psa_status_t mbedtls_psa_external_get_random( + mbedtls_psa_external_random_context_t *context, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + (void)context; + + #if defined(SLI_PSA_DRIVER_FEATURE_TRNG) + + psa_status_t entropy_status = PSA_ERROR_CORRUPTION_DETECTED; + *output_length = 0; + + #if defined(SLI_MBEDTLS_DEVICE_HSE) + + entropy_status = se_get_random(output, + output_size, + output_length); + + #elif defined(SLI_MBEDTLS_DEVICE_VSE) + + entropy_status = sli_cryptoacc_trng_get_random(output, output_size); + if (entropy_status == PSA_SUCCESS) { + *output_length = output_size; + } + + #else + + size_t entropy_max_retries = 5; + while (entropy_max_retries > 0 && entropy_status != PSA_SUCCESS) { + size_t offset = *output_length; + + // Read random bytes + #if defined(SLI_TRNG_DEVICE_SI91X) + entropy_status = sl_si91x_psa_get_random(&output[offset], + output_size - offset, + output_length); + #endif + + *output_length += offset; + + if (*output_length >= output_size) { + entropy_status = PSA_SUCCESS; + } + + // Consume a retry before going through another loop + entropy_max_retries--; + } + + #endif + + return entropy_status; + + #else // SLI_PSA_DRIVER_FEATURE_TRNG + + (void) output; + (void) output_size; + (void) output_length; + + return PSA_ERROR_HARDWARE_FAILURE; + + #endif // SLI_PSA_DRIVER_FEATURE_TRNG +} + +#endif // MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG || MBEDTLS_ENTROPY_HARDWARE_ALT diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_aead.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_aead.c new file mode 100644 index 000000000..781dbe161 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_aead.c @@ -0,0 +1,1657 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver AEAD functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_psa_driver_common.h" +#include "sli_se_driver_key_management.h" +#include "sli_se_driver_aead.h" + +#include "sl_se_manager.h" +#include "sl_se_manager_cipher.h" +#include "sli_se_manager_internal.h" + +#include + +// ----------------------------------------------------------------------------- +// Static functions + +#if defined(SLI_PSA_DRIVER_FEATURE_AEAD) + +static psa_status_t check_aead_parameters(const psa_key_attributes_t *attributes, + psa_algorithm_t alg, + size_t nonce_length, + size_t additional_data_length) +{ + size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + #if !defined(SLI_PSA_DRIVER_FEATURE_GCM) + (void)additional_data_length; + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + // verify key type + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + switch (psa_get_key_bits(attributes)) { + case 128: // Fallthrough + case 192: // Fallthrough + case 256: + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + // verify nonce and tag lengths + if (tag_length < 4 || tag_length > 16 || tag_length % 2 != 0 + || nonce_length < 7 || nonce_length > 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + // AD are limited to 2^64 bits, so 2^61 bytes. + // We need not check if SIZE_MAX (max of size_t) is less than 2^61. + #if SIZE_MAX > 0x2000000000000000ull + if (additional_data_length >> 61 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + #else + (void) additional_data_length; + #endif + // verify key type + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + switch (psa_get_key_bits(attributes)) { + case 128: // Fallthrough + case 192: // Fallthrough + case 256: + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + // verify nonce and tag lengths + if ((tag_length < 4) || (tag_length > 16)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (nonce_length == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + #if !defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + if (nonce_length != 12) { + return PSA_ERROR_NOT_SUPPORTED; + } + #endif + break; + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHAPOLY) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): + // verify key type + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_CHACHA20 + || psa_get_key_bits(attributes) != 256) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // verify nonce and tag lengths + if (nonce_length != 12 || tag_length != 16) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CHACHAPOLY + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_AEAD + +#if defined(SLI_PSA_DRIVER_FEATURE_GCM_IV_CALCULATION) + +// Do GCM in software in case the IV isn't 12 bytes, since that's the only +// thing the accelerator supports. +static psa_status_t sli_se_driver_software_gcm(sl_se_command_context_t *cmd_ctx, + sl_se_key_descriptor_t *key_desc, + const uint8_t* nonce, + size_t nonce_length, + const uint8_t* additional_data, + size_t additional_data_length, + const uint8_t* input, + uint8_t* output, + size_t plaintext_length, + size_t tag_length, + uint8_t* tag, + bool encrypt_ndecrypt) +{ + // Step 1: calculate H = Ek(0) + uint8_t Ek[16] = { 0 }; + psa_status_t status = sl_se_aes_crypt_ecb(cmd_ctx, + key_desc, + SL_SE_ENCRYPT, + sizeof(Ek), + (const unsigned char *)Ek, + Ek); + + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Step 2: calculate IV = GHASH(H, {}, IV) + uint8_t iv[16] = { 0 }; + uint64_t HL[16], HH[16]; + + sli_psa_software_ghash_setup(Ek, HL, HH); + + for (size_t i = 0; i < nonce_length; i += 16) { + // Mix in IV + for (size_t j = 0; j < (nonce_length - i > 16 ? 16 : nonce_length - i); j++) { + iv[j] ^= nonce[i + j]; + } + // Update result + sli_psa_software_ghash_multiply(HL, HH, iv, iv); + } + + iv[12] ^= (nonce_length * 8) >> 24; + iv[13] ^= (nonce_length * 8) >> 16; + iv[14] ^= (nonce_length * 8) >> 8; + iv[15] ^= (nonce_length * 8) >> 0; + + sli_psa_software_ghash_multiply(HL, HH, iv, iv); + + // Step 3: Calculate first counter block for tag generation + uint8_t tagbuf[16] = { 0 }; + status = sl_se_aes_crypt_ecb(cmd_ctx, + key_desc, + SL_SE_ENCRYPT, + sizeof(iv), + (const unsigned char *)iv, + tagbuf); + + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // If we're decrypting, mix in the to-be-checked tag value before transforming + if (!encrypt_ndecrypt) { + for (size_t i = 0; i < tag_length; i++) { + tagbuf[i] ^= tag[i]; + } + } + + // Step 4: increment IV (ripple increment) + for (size_t i = 0; i < 16; i++) { + iv[15 - i]++; + + if (iv[15 - i] != 0) { + break; + } + } + + // Step 5: Accumulate additional data + memset(Ek, 0, sizeof(Ek)); + for (size_t i = 0; i < additional_data_length; i += 16) { + // Mix in additional data as much as we have + for (size_t j = 0; + j < (additional_data_length - i > 16 ? 16 : additional_data_length - i); + j++) { + Ek[j] ^= additional_data[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + + // Step 6: If we're decrypting, accumulate the ciphertext before it gets transformed + if (!encrypt_ndecrypt) { + for (size_t i = 0; i < plaintext_length; i += 16) { + // Mix in ciphertext + for (size_t j = 0; + j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); + j++) { + Ek[j] ^= input[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + } + + // Step 7: transform data using AES-CTR + uint32_t nc = 0; + uint8_t nc_buff[16]; + status = sl_se_aes_crypt_ctr(cmd_ctx, + key_desc, + plaintext_length, + &nc, + iv, + nc_buff, + input, + output); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Step 8: If we're encrypting, accumulate the ciphertext now + if (encrypt_ndecrypt) { + for (size_t i = 0; i < plaintext_length; i += 16) { + // Mix in ciphertext + for (size_t j = 0; + j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); + j++) { + Ek[j] ^= output[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + } + + // Step 9: add len(A) || len(C) block to tag calculation + uint64_t bitlen = additional_data_length * 8; + Ek[0] ^= bitlen >> 56; + Ek[1] ^= bitlen >> 48; + Ek[2] ^= bitlen >> 40; + Ek[3] ^= bitlen >> 32; + Ek[4] ^= bitlen >> 24; + Ek[5] ^= bitlen >> 16; + Ek[6] ^= bitlen >> 8; + Ek[7] ^= bitlen >> 0; + + bitlen = plaintext_length * 8; + Ek[8] ^= bitlen >> 56; + Ek[9] ^= bitlen >> 48; + Ek[10] ^= bitlen >> 40; + Ek[11] ^= bitlen >> 32; + Ek[12] ^= bitlen >> 24; + Ek[13] ^= bitlen >> 16; + Ek[14] ^= bitlen >> 8; + Ek[15] ^= bitlen >> 0; + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + + // Step 10: calculate tag value + for (size_t i = 0; i < tag_length; i++) { + tagbuf[i] ^= Ek[i]; + } + + // Step 11: output tag for encrypt operation, check tag for decrypt + if (encrypt_ndecrypt) { + memcpy(tag, tagbuf, tag_length); + } else { + uint8_t accumulator = 0; + for (size_t i = 0; i < tag_length; i++) { + accumulator |= tagbuf[i]; + } + if (accumulator != 0) { + return PSA_ERROR_INVALID_SIGNATURE; + } + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_GCM_IV_CALCULATION + +#if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + +static psa_status_t aead_start(sli_se_driver_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + // Ephemeral contexts + sli_se_driver_aead_preinit_t preinit = operation->ctx.preinit; + + sl_se_command_context_t cmd_ctx = { 0 }; + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + uint8_t tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + psa_algorithm_t alg = PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(operation->alg); + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_GCM: + status = sl_se_gcm_multipart_starts(&operation->ctx.gcm, + &cmd_ctx, + &operation->key_desc, + preinit.direction, + preinit.nonce, + preinit.nonce_length, + input, + input_length); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + operation->ad_len += input_length; + return PSA_SUCCESS; + break; + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_CCM: + status = sl_se_ccm_multipart_starts(&operation->ctx.ccm, + &cmd_ctx, + &operation->key_desc, + preinit.direction, + preinit.pt_length, + preinit.nonce, + preinit.nonce_length, + input, + input_length, + tag_length); + + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + operation->ad_len += input_length; + return PSA_SUCCESS; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } +} + +#endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + +// ----------------------------------------------------------------------------- +// Single-shot driver entry points + +psa_status_t sli_se_driver_aead_encrypt_tag( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD) + + if (key_buffer == NULL + || attributes == NULL + || nonce == NULL + || (additional_data == NULL && additional_data_length > 0) + || (plaintext == NULL && plaintext_length > 0) + || (plaintext_length > 0 && (ciphertext == NULL || ciphertext_size == 0)) + || ciphertext_length == NULL || tag_length == NULL + || tag_size == 0 || tag == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + sl_status_t status; + psa_status_t psa_status; + *tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + // Verify that the driver supports the given parameters + psa_status = check_aead_parameters(attributes, + alg, + nonce_length, + additional_data_length); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Check sufficient output buffer size. + if ((ciphertext_size < plaintext_length) + || (tag_size < *tag_length)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((ciphertext > plaintext) && (ciphertext < (plaintext + plaintext_length))) { + memmove(ciphertext, plaintext, plaintext_length); + plaintext = ciphertext; + } + + psa_status = PSA_ERROR_BAD_STATE; + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + status = sl_se_ccm_encrypt_and_tag(&cmd_ctx, + &key_desc, + plaintext_length, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + ciphertext, + tag, + *tag_length); + if (status == SL_STATUS_INVALID_PARAMETER) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + } else if (status == SL_STATUS_OK) { + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (nonce_length == 12) { + status = sl_se_gcm_crypt_and_tag(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + plaintext_length, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + ciphertext, + *tag_length, + tag); + + if (status == SL_STATUS_INVALID_PARAMETER) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + } else if (status == SL_STATUS_OK) { + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + } + #if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + else { + psa_status = sli_se_driver_software_gcm(&cmd_ctx, + &key_desc, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + ciphertext, + plaintext_length, + *tag_length, + tag, + true); + } + #else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + else { + psa_status = PSA_ERROR_NOT_SUPPORTED; + } + #endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHAPOLY) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): + { + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + // EFR32xG21 doesn't support the special case where both the message + // and additional data length are zero. + if (plaintext_length == 0 && additional_data_length == 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + #endif + + uint8_t tagbuf[16]; + + status = sl_se_chacha20_poly1305_encrypt_and_tag(&cmd_ctx, + &key_desc, + plaintext_length, + nonce, + additional_data, + additional_data_length, + plaintext, + ciphertext, + tagbuf); + + if (status == SL_STATUS_INVALID_PARAMETER) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + } else if (status == SL_STATUS_OK) { + memcpy(tag, tagbuf, *tag_length); + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CHACHAPOLY + } + + if (psa_status == PSA_SUCCESS) { + *ciphertext_length = plaintext_length; + } else { + *ciphertext_length = 0; + *tag_length = 0; + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + (void)tag; + (void)tag_size; + (void)tag_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD +} + +psa_status_t sli_se_driver_aead_decrypt_tag( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + const uint8_t* tag, + size_t tag_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD) + + if (attributes == NULL + || key_buffer == NULL + || nonce == NULL + || (additional_data == NULL && additional_data_length > 0) + || (ciphertext == NULL && ciphertext_length > 0) + || (plaintext == NULL && plaintext_size > 0) + || plaintext_length == NULL + || tag == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + sl_status_t status; + psa_status_t psa_status; + + // Verify that the driver supports the given parameters + psa_status = check_aead_parameters(attributes, + alg, + nonce_length, + additional_data_length); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Check sufficient output buffer size. + if (plaintext_size < ciphertext_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((plaintext > ciphertext) && (plaintext < (ciphertext + ciphertext_length))) { + memmove(plaintext, ciphertext, ciphertext_length); + ciphertext = plaintext; + } + + psa_status = PSA_ERROR_BAD_STATE; + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + status = sl_se_ccm_auth_decrypt(&cmd_ctx, + &key_desc, + ciphertext_length, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + plaintext, + tag, + tag_length); + if (status == SL_STATUS_INVALID_PARAMETER) { + return PSA_ERROR_INVALID_ARGUMENT; + } else if (status == SL_STATUS_INVALID_SIGNATURE) { + return PSA_ERROR_INVALID_SIGNATURE; + } else if (status == SL_STATUS_OK) { + *plaintext_length = ciphertext_length; + psa_status = PSA_SUCCESS; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (nonce_length == 12) { + status = sl_se_gcm_auth_decrypt(&cmd_ctx, + &key_desc, + ciphertext_length, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + plaintext, + tag_length, + tag); + + if (status == SL_STATUS_INVALID_PARAMETER) { + return PSA_ERROR_INVALID_ARGUMENT; + } else if (status == SL_STATUS_INVALID_SIGNATURE) { + return PSA_ERROR_INVALID_SIGNATURE; + } else if (status == SL_STATUS_OK) { + *plaintext_length = ciphertext_length; + psa_status = PSA_SUCCESS; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + #if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + else { + psa_status = sli_se_driver_software_gcm(&cmd_ctx, + &key_desc, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + plaintext, + ciphertext_length, + tag_length, + (uint8_t*) tag, + false); + if (psa_status == PSA_SUCCESS) { + *plaintext_length = ciphertext_length; + } + } + #else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + else { + psa_status = PSA_ERROR_NOT_SUPPORTED; + } + #endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHAPOLY) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): + + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + // EFR32xG21 doesn't support the special case where both the message + // and additional data length are zero. + if (ciphertext_length == 0 && additional_data_length == 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + #endif + + // Vault devices currently do not support ChaCha20-Poly1305 with truncated + // tag lengths. RFC8439 also disallows truncating the tag. + if (tag_length != 16) { + return PSA_ERROR_NOT_SUPPORTED; + } + + status = sl_se_chacha20_poly1305_auth_decrypt(&cmd_ctx, + &key_desc, + ciphertext_length, + nonce, + additional_data, + additional_data_length, + ciphertext, + plaintext, + tag); + + if (status == SL_STATUS_INVALID_PARAMETER) { + return PSA_ERROR_INVALID_ARGUMENT; + } else if (status == SL_STATUS_INVALID_SIGNATURE) { + return PSA_ERROR_INVALID_SIGNATURE; + } else if (status == SL_STATUS_OK) { + *plaintext_length = ciphertext_length; + psa_status = PSA_SUCCESS; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CHACHAPOLY + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)ciphertext; + (void)ciphertext_length; + (void)tag; + (void)tag_length; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD +} + +psa_status_t sli_se_driver_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD) + + if (ciphertext_size <= plaintext_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + size_t tag_length = 0; + psa_status_t psa_status = sli_se_driver_aead_encrypt_tag( + attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + plaintext_length, + ciphertext, + plaintext_length, + ciphertext_length, + &ciphertext[plaintext_length], + ciphertext_size - plaintext_length, + &tag_length); + + if (psa_status == PSA_SUCCESS) { + *ciphertext_length += tag_length; + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD +} + +psa_status_t sli_se_driver_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD) + + if (attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + if (ciphertext_length < tag_length + || ciphertext == NULL + || (tag_length > 16)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Split the tag in its own buffer to avoid potential issues when the + // plaintext buffer extends into the tag area + uint8_t check_tag[16]; + memcpy(check_tag, &ciphertext[ciphertext_length - tag_length], tag_length); + + return sli_se_driver_aead_decrypt_tag( + attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + ciphertext_length - tag_length, + check_tag, + tag_length, + plaintext, + plaintext_size, + plaintext_length); + + #else // SLI_PSA_DRIVER_FEATURE_AEAD + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD +} + +psa_status_t sli_se_driver_aead_encrypt_decrypt_setup( + sli_se_driver_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + sl_se_cipher_operation_t operation_direction, + uint8_t *key_storage_buffer, + size_t key_storage_buffer_size, + size_t key_storage_overhead) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + + if (operation == NULL + || attributes == NULL + || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t key_bits = psa_get_key_bits(attributes); + size_t key_size = PSA_BITS_TO_BYTES(key_bits); + + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Validate key type + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Validate tag length. + if ( PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), key_bits, alg) > 16 ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context + memset(operation, 0, sizeof(*operation)); + + // Validate operation + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + operation->alg = alg; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + operation->alg = alg; + break; + #endif + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Prepare key descriptor + psa_status_t psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &(operation->key_desc)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Verify length and copy key material to context + uint32_t key_len = 0; + sl_status_t status = sli_key_get_size(&(operation->key_desc), &key_len); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + switch (key_len) { + case 16: // Fallthrough + case 24: // Fallthrough + case 32: + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (key_storage_buffer_size < key_storage_overhead + key_len) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(key_storage_buffer, + operation->key_desc.storage.location.buffer.pointer, + key_storage_overhead + key_len); + + // Point key_descriptor at internal copy of key + operation->key_desc.storage.location.buffer.pointer = key_storage_buffer; + + // Set direction of operation + operation->ctx.preinit.direction = operation_direction; + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)operation_direction; + (void)key_storage_buffer; + (void)key_storage_buffer_size; + (void)key_storage_overhead; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART +} + +psa_status_t sli_se_driver_aead_set_nonce( + sli_se_driver_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_size) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + + if (operation == NULL + || nonce == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Setting nonce twice isn't supported + if (operation->ctx.preinit.nonce_length != 0) { + return PSA_ERROR_BAD_STATE; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + // Non-12-byte IV is not supported for multipart GCM + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0) + == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { + if (nonce_size != 12) { + return PSA_ERROR_NOT_SUPPORTED; + } + } + #endif + + if (nonce_size <= sizeof(operation->ctx.preinit.nonce)) { + memcpy(operation->ctx.preinit.nonce, nonce, nonce_size); + operation->ctx.preinit.nonce_length = nonce_size; + return PSA_SUCCESS; + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + + #else // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + + (void)operation; + (void)nonce; + (void)nonce_size; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART +} + +psa_status_t sli_se_driver_aead_set_lengths( + sli_se_driver_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // To pass current PSA Crypto test suite, tag length encoded in the + // algorithm needs to be checked at this point. + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + if ((PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) % 2 != 0) + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + #endif + + default: + return PSA_ERROR_BAD_STATE; + } + + if (operation->ad_len != 0 || operation->pt_len != 0) { + return PSA_ERROR_BAD_STATE; + } + + operation->ctx.preinit.ad_length = ad_length; + operation->ctx.preinit.pt_length = plaintext_length; + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + + (void)operation; + (void)ad_length; + (void)plaintext_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART +} + +psa_status_t sli_se_driver_aead_update_ad( + sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + const uint8_t *input, + size_t input_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + + if (operation == NULL + || key_buffer == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + if (operation->ad_len > 0 || operation->pt_len > 0) { + return PSA_ERROR_BAD_STATE; + } + + // Start operation + if (input_length == 0) { + return PSA_SUCCESS; + } + + return aead_start(operation, input, input_length); + + #else // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + + (void)operation; + (void)key_buffer; + (void)input; + (void)input_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART +} + +psa_status_t sli_se_driver_aead_update(sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + + (void)key_buffer; + sl_status_t status; + size_t final_data_length = 0; + + sl_se_command_context_t cmd_ctx = { 0 }; + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check output buffer size is not too small. The required size = + // input_length + residual data stored in context object from previous update + // The PSA Crypto tests require output buffer can hold the residual bytes in + // the last AES block even if these are not processed and written in this call + // ( they are postponed to the next call to update or finish ). + psa_algorithm_t alg = PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(operation->alg); + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_GCM: + { + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + // On xG21 devices, if the final_data_length is 16 from the previous call + // to the sl_se_gcm_multipart_update function we should not count in the + // final_data since it should be processed already. + if (operation->ctx.gcm.final_data_length == 16) { + final_data_length = 0; + } else + #endif + { + final_data_length = operation->ctx.gcm.final_data_length; + } + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_CCM: + { + final_data_length = operation->ctx.ccm.final_data_length; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + if (output_size < input_length + final_data_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (((input == NULL || output == NULL) && input_length > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Start operation + if (input_length == 0) { + return PSA_SUCCESS; + } + + psa_status_t psa_status; + + // Operation isn't initialised unless we have either AD or PT, so if we are + // still at 0, we need to run the start step. + if (operation->ad_len == 0 && operation->pt_len == 0) { + psa_status = aead_start(operation, NULL, 0); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + } + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_GCM: + { + status = sl_se_gcm_multipart_update(&operation->ctx.gcm, + &cmd_ctx, + &operation->key_desc, + input_length, + input, + output, + output_length); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + psa_status = PSA_SUCCESS; + operation->pt_len += input_length; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_CCM: + { + status = sl_se_ccm_multipart_update(&operation->ctx.ccm, + &cmd_ctx, + &operation->key_desc, + input_length, + input, + output, + output_length); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + psa_status = PSA_SUCCESS; + operation->pt_len += input_length; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CCM + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + + (void)operation; + (void)key_buffer; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART +} + +psa_status_t sli_se_driver_aead_finish(sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + + (void)key_buffer; + + sl_status_t status; + psa_status_t psa_status; + + sl_se_command_context_t cmd_ctx = { 0 }; + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + + if (tag_size < tag_len) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (ciphertext_length == NULL + || tag == NULL + || tag_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + *ciphertext_length = 0; + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Operation isn't initialised unless we have either AD or PT, so if we are + // still at 0, we need to run the start step. + if (operation->ad_len == 0 && operation->pt_len == 0) { + psa_status = aead_start(operation, NULL, 0); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + } + + psa_algorithm_t alg = PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(operation->alg); + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_GCM: + if (operation->ctx.gcm.mode != SL_SE_ENCRYPT) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + status = sl_se_gcm_multipart_finish(&operation->ctx.gcm, + &cmd_ctx, + &operation->key_desc, + tag, + tag_len, + ciphertext, + ciphertext_size, + (uint8_t *)ciphertext_length); + if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + *tag_length = tag_len; + psa_status = PSA_SUCCESS; + break; + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_CCM: + if (operation->ctx.ccm.mode != SL_SE_ENCRYPT) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + status = sl_se_ccm_multipart_finish(&operation->ctx.ccm, + &cmd_ctx, + &operation->key_desc, + tag, + tag_len, + ciphertext, + ciphertext_size, + (uint8_t *)ciphertext_length); + + if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + *tag_length = operation->ctx.ccm.tag_len; + psa_status = PSA_SUCCESS; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + default: + (void)tag_size; + psa_status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + exit: + + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + + (void)operation; + (void)key_buffer; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + (void)tag; + (void)tag_size; + (void)tag_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART +} + +psa_status_t sli_se_driver_aead_verify(sli_se_driver_aead_operation_t *operation, + uint8_t *key_buffer, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART) + + (void)key_buffer; + + sl_status_t status; + psa_status_t psa_status; + + sl_se_command_context_t cmd_ctx = { 0 }; + + if (operation == NULL || plaintext_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + *plaintext_length = 0; + + if (tag == NULL || tag_length == 0 ) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + psa_algorithm_t alg = PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(operation->alg); + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Operation isn't initialised unless we have either AD or PT, so if we are + // still at 0, we need to run the start step. + if (operation->ad_len == 0 && operation->pt_len == 0) { + psa_status = aead_start(operation, NULL, 0); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + } + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_GCM) + case PSA_ALG_GCM: + if (operation->ctx.gcm.mode != SL_SE_DECRYPT) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + status = sl_se_gcm_multipart_finish(&operation->ctx.gcm, + &cmd_ctx, + &operation->key_desc, + (uint8_t *)tag, + tag_length, + plaintext, + plaintext_size, + (uint8_t *)plaintext_length); + if (status == SL_STATUS_INVALID_SIGNATURE) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } else if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + psa_status = PSA_SUCCESS; + break; + #endif // SLI_PSA_DRIVER_FEATURE_GCM + + #if defined(SLI_PSA_DRIVER_FEATURE_CCM) + case PSA_ALG_CCM: + { + uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + if (tag_length != tag_len) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + if (operation->ctx.ccm.mode != SL_SE_DECRYPT) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + status = sl_se_ccm_multipart_finish(&operation->ctx.ccm, + &cmd_ctx, + &operation->key_desc, + (uint8_t *)tag, + tag_length, + plaintext, + plaintext_size, + (uint8_t *)plaintext_length); + + if (status == SL_STATUS_INVALID_SIGNATURE) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } else if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + psa_status = PSA_SUCCESS; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CCM + + default: + psa_status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + exit: + + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + + (void)operation; + (void)key_buffer; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)tag; + (void)tag_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_builtin_keys.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_builtin_keys.c new file mode 100644 index 000000000..2172c7756 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_builtin_keys.c @@ -0,0 +1,170 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver Builtin key functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include + +#include "sli_se_opaque_types.h" +#include "sl_psa_values.h" + +#include + +// ----------------------------------------------------------------------------- +// Driver entry points + +#if defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) + +psa_status_t sli_se_opaque_get_builtin_key(psa_drv_slot_number_t slot_number, + psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length) +{ + sli_se_opaque_key_context_header_t header; + memset(&header, 0, sizeof(header)); + + // Set key type and permissions according to key ID + switch ( slot_number ) { + #if defined(SLI_PSA_DRIVER_FEATURE_ATTESTATION) + case SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY: + psa_set_key_bits(attributes, 256); + psa_set_key_type(attributes, PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1) ); + psa_set_key_usage_flags(attributes, PSA_KEY_USAGE_SIGN_HASH | PSA_KEY_USAGE_VERIFY_HASH); + psa_set_key_algorithm(attributes, PSA_ALG_ECDSA(PSA_ALG_ANY_HASH)); + break; + case SL_SE_KEY_SLOT_SE_ATTESTATION_KEY: + psa_set_key_bits(attributes, 256); + psa_set_key_type(attributes, PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1) ); + psa_set_key_usage_flags(attributes, PSA_KEY_USAGE_VERIFY_HASH); + psa_set_key_algorithm(attributes, PSA_ALG_ECDSA(PSA_ALG_ANY_HASH)); + break; + #endif // SLI_PSA_DRIVER_FEATURE_ATTESTATION + case SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY: + psa_set_key_bits(attributes, 256); + psa_set_key_type(attributes, PSA_KEY_TYPE_ECC_PUBLIC_KEY(PSA_ECC_FAMILY_SECP_R1) ); + psa_set_key_usage_flags(attributes, PSA_KEY_USAGE_VERIFY_HASH); + psa_set_key_algorithm(attributes, PSA_ALG_ECDSA(PSA_ALG_ANY_HASH)); + break; + case SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY: + psa_set_key_bits(attributes, 256); + psa_set_key_type(attributes, PSA_KEY_TYPE_ECC_PUBLIC_KEY(PSA_ECC_FAMILY_SECP_R1) ); + psa_set_key_usage_flags(attributes, PSA_KEY_USAGE_VERIFY_HASH); + psa_set_key_algorithm(attributes, PSA_ALG_ECDSA(PSA_ALG_ANY_HASH)); + break; + case SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY: + psa_set_key_bits(attributes, 128); + psa_set_key_type(attributes, PSA_KEY_TYPE_AES); + psa_set_key_usage_flags(attributes, PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT); + psa_set_key_algorithm(attributes, SL_SE_BUILTIN_KEY_AES128_ALG); + break; + case SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY: + psa_set_key_bits(attributes, 256); + psa_set_key_type(attributes, PSA_KEY_TYPE_AES); + psa_set_key_usage_flags(attributes, PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT); + psa_set_key_algorithm(attributes, PSA_ALG_CMAC); + break; + default: + return(PSA_ERROR_DOES_NOT_EXIST); + } + + psa_set_key_lifetime(attributes, + PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( + PSA_KEY_PERSISTENCE_READ_ONLY, + PSA_KEY_LOCATION_SLI_SE_OPAQUE) ); + + // Check the key buffer size after populating the key attributes: + // From mbedTLS, psa-driver-interface.md (snippet): + // + // This entry point may return the following status values: + // (...) + // * PSA_ERROR_BUFFER_TOO_SMALL: key_buffer_size is insufficient. + // In this case, the driver must pass the key's attributes in + // *attributes. In particular, get_builtin_key(slot_number, + // &attributes, NULL, 0) is a way for the core to obtain the + // key's attributes. + if (key_buffer_size < sizeof(sli_se_opaque_key_context_header_t)) { + return(PSA_ERROR_BUFFER_TOO_SMALL); + } + + header.struct_version = SLI_SE_OPAQUE_KEY_CONTEXT_VERSION; + header.builtin_key_id = (uint8_t) slot_number; + + memcpy(key_buffer, &header, sizeof(sli_se_opaque_key_context_header_t)); + *key_buffer_length = sizeof(sli_se_opaque_key_context_header_t); + + return(PSA_SUCCESS); +} + +#if !defined(PSA_CRYPTO_DRIVER_TEST) + +psa_status_t mbedtls_psa_platform_get_builtin_key( + mbedtls_svc_key_id_t key_id, + psa_key_lifetime_t *lifetime, + psa_drv_slot_number_t *slot_number) +{ + switch (MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key_id)) { + #if defined(SLI_PSA_DRIVER_FEATURE_ATTESTATION) + case SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID: + *slot_number = SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY; + break; + case SL_SE_BUILTIN_KEY_SYSTEM_ATTESTATION_ID: + *slot_number = SL_SE_KEY_SLOT_SE_ATTESTATION_KEY; + break; + #endif // SLI_PSA_DRIVER_FEATURE_ATTESTATION + case SL_SE_BUILTIN_KEY_SECUREBOOT_ID: + *slot_number = SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY; + break; + case SL_SE_BUILTIN_KEY_SECUREDEBUG_ID: + *slot_number = SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY; + break; + case SL_SE_BUILTIN_KEY_AES128_ID: + *slot_number = SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY; + break; + case SL_SE_BUILTIN_KEY_TRUSTZONE_ID: + *slot_number = SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY; + break; + default: + return(PSA_ERROR_DOES_NOT_EXIST); + } + *lifetime = PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( + PSA_KEY_PERSISTENCE_READ_ONLY, + PSA_KEY_LOCATION_SLI_SE_OPAQUE); + + return(PSA_SUCCESS); +} + +#endif // !PSA_CRYPTO_DRIVER_TEST + +#endif // SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_cipher.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_cipher.c new file mode 100644 index 000000000..9e8103bbb --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_cipher.c @@ -0,0 +1,1776 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver Cipher functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" +#include "psa/crypto_extra.h" + +#include "sli_psa_driver_common.h" + +#include "sli_se_driver_cipher.h" +#include "sli_se_driver_key_management.h" + +#include "sl_se_manager.h" +#include "sl_se_manager_cipher.h" + +#include + +// ----------------------------------------------------------------------------- +// Static functions + +#if defined(SLI_PSA_DRIVER_FEATURE_CIPHER) + +/** + * @brief + * Validate that the given key desc has the correct properties + * to be used for a cipher operation + * @param key_desc + * Pointer to a key descriptor + * @return + * PSA_SUCCESS if all is good + * PSA_ERROR_INVALID_ARGUMENT otherwise + */ +static psa_status_t validate_key_type(const sl_se_key_descriptor_t *key_desc) +{ + sl_se_key_type_t sl_key_type = key_desc->type; + // Check with if (..) since switch does not support multiple equal entries + // (AES 256 and CHACHA20 has same sl_key_type value) + if (sl_key_type == SL_SE_KEY_TYPE_AES_128 + || sl_key_type == SL_SE_KEY_TYPE_AES_192 + || sl_key_type == SL_SE_KEY_TYPE_AES_256 + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + || sl_key_type == SL_SE_KEY_TYPE_CHACHA20 + #endif + ) { + return PSA_SUCCESS; + } + + return PSA_ERROR_INVALID_ARGUMENT; +} + +// Validate combination of key and algorithm +static psa_status_t validate_key_algorithm_match( + psa_algorithm_t alg, + const psa_key_attributes_t *attributes) +{ + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER) + #if defined(SLI_PSA_DRIVER_FEATURE_AES_ECB) + case PSA_ALG_ECB_NO_PADDING: + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR) + case PSA_ALG_CTR: + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CFB) + case PSA_ALG_CFB: + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) + case PSA_ALG_OFB: + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) + case PSA_ALG_CCM_STAR_NO_TAG: + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: + #endif + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + case PSA_ALG_STREAM_CIPHER: + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_CHACHA20) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_CIPHER + +// ----------------------------------------------------------------------------- +// Single-shot driver entry points + +psa_status_t sli_se_driver_cipher_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER) + + #if defined(MBEDTLS_PSA_CRYPTO_C) + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CFB) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_NO_PADDING) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7) \ + || defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + uint8_t tmp_buf[16] = { 0 }; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CFB) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_NO_PADDING) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7) + uint8_t final_block[16] = { 0 }; + #endif + + #endif // MBEDTLS_PSA_CRYPTO_C + + // Argument check + if (key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || (iv == NULL && iv_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t psa_status = validate_key_algorithm_match(alg, attributes); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + psa_status = validate_key_type(&key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + if (input_length == 0) { + *output_length = 0; + return PSA_SUCCESS; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_AES_ECB) + case PSA_ALG_ECB_NO_PADDING: + // Check buffer sizes + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // We cannot do ECB on non-block sizes + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // do the operation + status = sl_se_aes_crypt_ecb(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + input_length, + input, + output); + if (status != PSA_SUCCESS) { + goto exit; + } + *output_length = input_length; + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_ECB + + #if defined(MBEDTLS_PSA_CRYPTO_C) + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) + case PSA_ALG_CCM_STAR_NO_TAG: // Explicit fallthrough + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT) + case PSA_ALG_CTR: { + uint8_t iv_buf[16] = { 0 }; + // Check buffer sizes + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) + if (alg == PSA_ALG_CCM_STAR_NO_TAG) { + if (iv_length != 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // AES-CCM*-no-tag is basically AES-CTR with preformatted IV + iv_buf[0] = 1; + memcpy(&iv_buf[1], iv, 13); + iv_buf[14] = 0; + iv_buf[15] = 1; + } else + #endif // SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG + { + if (iv_length != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Write nonce to temporary buf to be used internally by + // sl_se_aes_crypt_ctr. + memcpy(iv_buf, iv, 16); + } + + // Store final block in a temporary buffer in order to avoid in being + // overwritten inside of sl_se_aes_crypt_ctr() (hence the separation + // into two calls). + if ((input_length & 0x0F) > 0) { + memcpy(final_block, &input[input_length & ~0x0F], 16); + } + + // Do multi-block operation if applicable. + if ((input_length & ~0x0F) > 0) { + status = sl_se_aes_crypt_ctr(&cmd_ctx, + &key_desc, + input_length & ~0x0F, + NULL, + iv_buf, + tmp_buf, + input, + output); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + // Encrypt final block if there is any. + if ((input_length & 0x0F) > 0) { + status = sl_se_aes_crypt_ctr(&cmd_ctx, + &key_desc, + input_length & 0x0F, + NULL, + iv_buf, + tmp_buf, + final_block, + &output[(input_length & ~0x0F)]); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + *output_length = input_length; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CFB) + case PSA_ALG_CFB: + // Check buffer sizes + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (iv_length != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Write IV to temporary buf to be used internally by + // sl_se_aes_crypt_cbf128. + memcpy(tmp_buf, iv, 16); + + // Store final block in a temporary buffer in order to avoid in being + // overwritten inside of sl_se_aes_crypt_ctr() (hence the separation + // into two calls). + if ((input_length & 0x0F) > 0) { + memcpy(final_block, &input[input_length & ~0x0F], 16); + } + + // Do multi-block operation if applicable. + if ((input_length & ~0x0F) > 0) { + status = sl_se_aes_crypt_cfb128(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + input_length & ~0x0F, + NULL, + tmp_buf, + input, + output); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + // Encrypt final block if there is any. + if ((input_length & 0x0F) > 0) { + status = sl_se_aes_crypt_cfb128(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + input_length & 0x0F, + NULL, + tmp_buf, + final_block, + &output[(input_length & ~0x0F)]); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + *output_length = input_length; + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_CFB + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) + case PSA_ALG_OFB: + { + // Check buffer sizes + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (iv_length != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Write IV to temporary buf to be used internally by + // sl_se_aes_crypt_ecb. + memcpy(tmp_buf, iv, 16); + + size_t data_length = input_length; + size_t n = 0; + + // Use final_block as a temporary storage in order to avoid input being + // overwritten by the output (in case of buffer overlap). + memcpy(final_block, input, 16); + + // Loop over input data to create output. + do { + if (n == 0) { + status = sl_se_aes_crypt_ecb(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + 16, + tmp_buf, + tmp_buf); + if (status != SL_STATUS_OK) { + goto exit; + } + } + uint8_t tmp_input_val = final_block[n]; + final_block[n] = input[16 + input_length - data_length]; + output[input_length - data_length] = tmp_input_val ^ tmp_buf[n]; + n = (n + 1) & 0x0F; + } while (data_length--); + + *output_length = input_length; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_OFB + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT) + case PSA_ALG_CBC_NO_PADDING: + // We cannot do CBC without padding on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // fall through + case PSA_ALG_CBC_PKCS7: + // Check buffer sizes + if (alg == PSA_ALG_CBC_NO_PADDING) { + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } else { + if (output_size < 16 + (input_length & ~0xF)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + if (iv_length != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Write IV to temporary buf to be used internally by + // sl_se_aes_crypt_cbf128. + memcpy(tmp_buf, iv, 16); + + // Store last block (if non-blocksize input-length) to temporary + // buffer to be used in padding. + if (alg == PSA_ALG_CBC_PKCS7) { + memcpy(final_block, &input[input_length & ~0xF], input_length & 0xF); + } + + // CBC-encrypt all but the last block + if (input_length >= 16) { + status = sl_se_aes_crypt_cbc(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + input_length & ~0xF, + tmp_buf, + input, + output); + if (status != SL_STATUS_OK) { + goto exit; + } + } + + // Process final block. + if (alg == PSA_ALG_CBC_PKCS7) { + // Add PKCS7 padding. + memset(&final_block[input_length & 0xF], + 16 - (input_length & 0xF), + 16 - (input_length & 0xF)); + + // Store IV (last ciphertext block) in temp buffer to avoid messing + // up output. + if (input_length >= 16) { + memcpy(tmp_buf, &output[(input_length & ~0xF) - 16], 16); + } + + // CBC-encrypt the last block. + status = sl_se_aes_crypt_cbc(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + 16, + tmp_buf, + final_block, + final_block); + + if (status != SL_STATUS_OK) { + goto exit; + } + + // Copy to output. + memcpy(&output[(input_length & ~0xF)], final_block, 16); + *output_length = (input_length & ~0xF) + 16; + } else { + *output_length = input_length; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + case PSA_ALG_STREAM_CIPHER: + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_CHACHA20) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // check buffer sizes + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (iv_length != 12) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // PSA Crypto dictates that the initial counter for ChaCha20 starts + // at zero (unless using the multi-part API) + memset(tmp_buf, 0, 4); + memcpy(&tmp_buf[4], iv, 12); + + status = sl_se_chacha20_crypt(&cmd_ctx, + SL_SE_ENCRYPT, + &key_desc, + input_length, + tmp_buf, + &tmp_buf[4], + input, + output); + if (status != SL_STATUS_OK) { + goto exit; + } + + *output_length = input_length; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CHACHA20 + + #endif // MBEDTLS_PSA_CRYPTO_C + + default: + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + return PSA_ERROR_NOT_SUPPORTED; + } + + exit: + if (status != SL_STATUS_OK) { + memset(output, 0, output_size); + *output_length = 0; + if (status == SL_STATUS_FAIL) { + // This specific code maps to 'does not exist' for builtin keys + return PSA_ERROR_DOES_NOT_EXIST; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + } else { + return PSA_SUCCESS; + } + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER +} + +psa_status_t sli_se_driver_cipher_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER) + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT) + uint8_t tmp_buf[16] = { 0 }; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CFB) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_NO_PADDING) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7) \ + || defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + uint8_t iv_buf[16] = { 0 }; + #endif + + // Argument check. + if (key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t psa_status = validate_key_algorithm_match(alg, attributes); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Ephemeral contexts. + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + psa_status = validate_key_type(&key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + if (input_length == 0) { + *output_length = 0; + return PSA_SUCCESS; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_AES_ECB) + case PSA_ALG_ECB_NO_PADDING: + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // We cannot do ECB on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Do the operation. + status = sl_se_aes_crypt_ecb(&cmd_ctx, + &key_desc, + SL_SE_DECRYPT, + input_length, + input, + output); + + *output_length = input_length; + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_ECB + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) + case PSA_ALG_CCM_STAR_NO_TAG: // Explicit fallthrough + #endif // SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT) + case PSA_ALG_CTR: + // Check buffer sizes. + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) + if (alg == PSA_ALG_CCM_STAR_NO_TAG) { + if (output_size < input_length - 13) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // AES-CCM*-no-tag is basically AES-CTR with preformatted IV + iv_buf[0] = 1; + memcpy(&iv_buf[1], input, 13); + iv_buf[14] = 0; + iv_buf[15] = 1; + input += 13; + input_length -= 13; + } else + #endif // SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG + { + if (output_size < input_length - 16) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Write IV to temporary buf to be used internally by + // sl_se_aes_crypt_ctr. + memcpy(iv_buf, input, 16); + input += 16; + input_length -= 16; + } + + status = sl_se_aes_crypt_ctr(&cmd_ctx, + &key_desc, + input_length, + NULL, + iv_buf, + tmp_buf, + input, + output); + + *output_length = input_length; + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CFB) + case PSA_ALG_CFB: + // Check buffer sizes. + if (output_size < input_length - 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Write IV to temporary buf to be used internally by + // sl_se_aes_crypt_cfb128. + memcpy(iv_buf, input, 16); + + status = sl_se_aes_crypt_cfb128(&cmd_ctx, + &key_desc, + SL_SE_DECRYPT, + input_length - 16, + NULL, + iv_buf, + &input[16], + output); + + *output_length = input_length - 16; + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_CFB + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) + case PSA_ALG_OFB: + { + // Check buffer sizes. + if (output_size < input_length - 16) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Write IV to temporary buf to be used internally by + // sl_se_aes_crypt_ecb. + memcpy(iv_buf, input, 16); + + input += 16; + size_t data_length = input_length - 16; + size_t n = 0; + + // Loop over input data to create output. + while (data_length--) { + if (n == 0) { + status = sl_se_aes_crypt_ecb(&cmd_ctx, + &key_desc, + SL_SE_ENCRYPT, + 16, + iv_buf, + iv_buf); + if (status != SL_STATUS_OK) { + goto exit; + } + } + *output++ = *input++ ^ iv_buf[n]; + + n = (n + 1) & 0x0F; + } + + *output_length = input_length - 16; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_OFB + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT) + case PSA_ALG_CBC_NO_PADDING: + // We cannot do CBC without padding on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // fall through + + case PSA_ALG_CBC_PKCS7: { + size_t full_blocks; + if (alg == PSA_ALG_CBC_NO_PADDING) { + if (output_size < input_length - 16) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + full_blocks = (input_length - 16) / 16; + } else { + // Check correct input amount + if (input_length < 32 + || ((input_length & 0xF) != 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // Check output has enough room for at least n-1 blocks. + if (output_size < (input_length - 32)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + full_blocks = (input_length - 32) / 16; + } + + // Write IV to temporary buf to be used internally by + // sl_se_aes_crypt_cbc. + memcpy(iv_buf, input, 16); + + // CBC-decrypt all but the last block. + if (full_blocks > 0) { + status = sl_se_aes_crypt_cbc(&cmd_ctx, + &key_desc, + SL_SE_DECRYPT, + full_blocks * 16, + iv_buf, + &input[16], + output); + if (status != SL_STATUS_OK) { + goto exit; + } + } + + // Process final block. + if (alg == PSA_ALG_CBC_PKCS7) { + // Store last block to temporary buffer to be used in removing the + // padding. + memcpy(tmp_buf, &input[input_length - 16], 16); + + // CBC-decrypt the last block. + status = sl_se_aes_crypt_cbc(&cmd_ctx, + &key_desc, + SL_SE_DECRYPT, + 16, + iv_buf, + tmp_buf, + tmp_buf); + if (status != SL_STATUS_OK) { + goto exit; + } + + // Validate padding. + size_t pad_bytes = 0; + psa_status = sli_psa_validate_pkcs7_padding(tmp_buf, + 16, + &pad_bytes); + if (psa_status != PSA_SUCCESS) { + *output_length = 0; + return psa_status; + } + + if (output_size < (input_length - 16 - pad_bytes)) { + *output_length = 0; + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Copy non-padding bytes. + memcpy(&output[full_blocks * 16], tmp_buf, 16 - pad_bytes); + *output_length = input_length - 16 - pad_bytes; + } else { + *output_length = input_length - 16; + } + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + case PSA_ALG_STREAM_CIPHER: + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_CHACHA20) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // check buffer sizes. + if (output_size < input_length - 12) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // PSA Crypto dictates that the initial counter for ChaCha20 starts + // at zero (unless using the multi-part API) + memset(iv_buf, 0, 4); + + status = sl_se_chacha20_crypt(&cmd_ctx, + SL_SE_DECRYPT, + &key_desc, + input_length - 12, // - 12 due to the nonce. + iv_buf, + input, + &input[12], + output); + + *output_length = input_length - 12; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CHACHA20 + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT) \ + || defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) + exit: + #endif + + if (status != SL_STATUS_OK) { + memset(output, 0, output_size); + *output_length = 0; + if (status == SL_STATUS_FAIL) { + // This specific code maps to 'does not exist' for builtin keys + return PSA_ERROR_DOES_NOT_EXIST; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + } else { + return PSA_SUCCESS; + } + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER +} + +// ----------------------------------------------------------------------------- +// Multi-part driver entry points + +psa_status_t sli_se_driver_cipher_encrypt_setup( + sli_se_driver_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL || attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context + memset(operation, 0, sizeof(*operation)); + + // Set up context + memcpy(&operation->alg, &alg, sizeof(alg)); + operation->direction = SL_SE_ENCRYPT; + + // Validate combination of key and algorithm + return validate_key_algorithm_match(alg, attributes); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)attributes; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_driver_cipher_decrypt_setup( + sli_se_driver_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL || attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context + memset(operation, 0, sizeof(*operation)); + + // Set up context + memcpy(&operation->alg, &alg, sizeof(alg)); + operation->direction = SL_SE_DECRYPT; + + // Validate combination of key and algorithm + return validate_key_algorithm_match(alg, attributes); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)attributes; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_driver_cipher_set_iv( + sli_se_driver_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL || iv == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (iv_length > sizeof(operation->iv)) { + // IV can't be larger than what our state can store + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->iv_len != 0) { + // IV was set previously + return PSA_ERROR_BAD_STATE; + } + + switch (operation->alg) { + case PSA_ALG_ECB_NO_PADDING: + if (iv_length > 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } else { + return PSA_SUCCESS; + } + break; + + case PSA_ALG_CTR: // Explicit fallthrough + case PSA_ALG_CFB: // Explicit fallthrough + case PSA_ALG_OFB: // Explicit fallthrough + case PSA_ALG_CBC_NO_PADDING: // Explicit fallthrough + case PSA_ALG_CBC_PKCS7: // Explicit fallthrough + if (iv_length != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->iv, iv, iv_length); + break; + + case PSA_ALG_CCM_STAR_NO_TAG: + // Preformat the IV for CCM*-no-tag here, such that the remainder + // of the processing for this algorithm boils down to AES-CTR + if (iv_length != 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->iv[0] = 1; + memcpy(&operation->iv[1], iv, iv_length); + operation->iv[14] = 0; + operation->iv[15] = 1; + iv_length = 16; + break; + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + case PSA_ALG_STREAM_CIPHER: + // PSA Crypto supports multiple IV input lengths for ChaCha20 + // refer to the doc for PSA_ALG_STREAM_CIPHER + if (iv_length == 12) { + // Set initial counter value to zero + memset(operation->iv, 0, 4); + memcpy(&operation->iv[4], iv, iv_length); + } else if (iv_length == 16) { + // Initial counter value is stored little-endian in the first four + // bytes. This makes our lives easier: since this driver will only + // run on little-endian machines, we can just cast it to a uint32. + memcpy(operation->iv, iv, iv_length); + } else if (iv_length == 8) { + // "Original" ChaCha20: 8-byte IV and 8-byte counter (0-initialised). + // We currently don't support this format. + return PSA_ERROR_NOT_SUPPORTED; + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CHACHA20 + + default: + return PSA_ERROR_BAD_STATE; + } + + operation->iv_len = iv_length; + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)iv; + (void)iv_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_driver_cipher_update( + sli_se_driver_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + // Argument check + if (operation == NULL + || (input == NULL && input_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Key desc has been properly set by wrapper function + const sl_se_key_descriptor_t *key_desc = &operation->key_desc; + psa_status_t psa_status = validate_key_type(key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + bool lagging; + size_t bytes_to_boundary = 16 - (operation->processed_length % 16); + size_t actual_output_length = 0; + + // We need to cache (not return) the whole last block for decryption with + // padding, otherwise it won't be possible to remove a potential padding + // block during finish. + bool cache_full_block = (operation->alg == PSA_ALG_CBC_PKCS7 + && operation->direction == SL_SE_DECRYPT); + + // Figure out whether the operation is on a lagging or forward-looking cipher + // Lagging: needs a full block of input data before being able to output + // Non-lagging: can output the same amount of data as getting fed + switch (operation->alg) { + case PSA_ALG_ECB_NO_PADDING: + case PSA_ALG_CBC_NO_PADDING: + case PSA_ALG_CBC_PKCS7: + lagging = true; + break; + + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_CFB: + case PSA_ALG_OFB: + lagging = false; + break; + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + case PSA_ALG_STREAM_CIPHER: + lagging = false; + break; + #endif + + default: + return PSA_ERROR_BAD_STATE; + } + + if (input_length == 0) { + // We don't need to do anything if the input length is zero. + *output_length = 0; + return PSA_SUCCESS; + } + + if (lagging) { + // Early processing if not getting to a full block + if (cache_full_block + && bytes_to_boundary == 16 + && operation->processed_length > 0) { + // Don't overwrite the streaming block if it's currently full. + } else { + if (input_length < bytes_to_boundary) { + memcpy(&operation->streaming_block[operation->processed_length % 16], + input, + input_length); + operation->processed_length += input_length; + *output_length = actual_output_length; + return PSA_SUCCESS; + } + } + + // We know we'll be computing and outputing at least the completed + // streaming block. + size_t output_blocks = 1; + + if (input_length > bytes_to_boundary) { + // plus however many full blocks are left over after filling the stream buffer + output_blocks += (input_length - bytes_to_boundary) / 16; + // If we're caching and the sum of already-input and to-be-input data + // ends up at a block boundary, we won't be outputting the last block + if (cache_full_block && ((input_length - bytes_to_boundary) % 16 == 0)) { + output_blocks -= 1; + } + } + + if (output_size < (output_blocks * 16)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } else { + // Early failure if output buffer is too small + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + switch (operation->alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_AES_ECB) + case PSA_ALG_ECB_NO_PADDING: + // Read in up to full streaming input block + if (bytes_to_boundary != 16) { + memcpy(&operation->streaming_block[operation->processed_length % 16], + input, + bytes_to_boundary); + input += bytes_to_boundary; + input_length -= bytes_to_boundary; + + status = sl_se_aes_crypt_ecb(&cmd_ctx, + key_desc, + operation->direction, + 16, + operation->streaming_block, + output); + if (status != SL_STATUS_OK) { + goto exit; + } + + output += 16; + actual_output_length += 16; + operation->processed_length += bytes_to_boundary; + } + + // Do multi-block operation if applicable + if (input_length >= 16) { + size_t operation_size = (input_length / 16) * 16; + status = sl_se_aes_crypt_ecb(&cmd_ctx, + key_desc, + operation->direction, + operation_size, + input, + output); + + if (status != SL_STATUS_OK) { + goto exit; + } + + input += operation_size; + input_length -= operation_size; + actual_output_length += operation_size; + operation->processed_length += operation_size; + } + + // What's left over in the input buffer will be cleaned up after switch-case + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_ECB + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT) + case PSA_ALG_CBC_NO_PADDING: // fall through + case PSA_ALG_CBC_PKCS7: + if (bytes_to_boundary != 16) { + memcpy(&operation->streaming_block[operation->processed_length % 16], + input, + bytes_to_boundary); + if (cache_full_block && (bytes_to_boundary == input_length)) { + // Don't process the streaming block if there is no more input data + } else { + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + operation->direction, + 16, + operation->iv, + operation->streaming_block, + output); + if (status != PSA_SUCCESS) { + goto exit; + } + output += 16; + actual_output_length += 16; + } + + input += bytes_to_boundary; + input_length -= bytes_to_boundary; + operation->processed_length += bytes_to_boundary; + } else if (input_length > 0 + && cache_full_block + && operation->processed_length > 0) { + // We know there's processing to be done, and that we haven't processed + // the full block in the streaming buffer yet. Process it now. + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + operation->direction, + 16, + operation->iv, + operation->streaming_block, + output); + if (status != PSA_SUCCESS) { + goto exit; + } + output += 16; + actual_output_length += 16; + } + + // Do multi-block operation if applicable + if (input_length >= 16) { + size_t operation_size = (input_length / 16) * 16; + if (cache_full_block && (input_length % 16 == 0)) { + // Don't decrypt the last block until finish is called, so that we + // can properly remove the padding before returning it. + operation_size -= 16; + } + + if (operation_size > 0) { + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + operation->direction, + operation_size, + operation->iv, + input, + output); + if (status != PSA_SUCCESS) { + goto exit; + } + } else { + status = PSA_SUCCESS; + } + + input += operation_size; + input_length -= operation_size; + actual_output_length += operation_size; + operation->processed_length += operation_size; + } + + // What's left over in the input buffer will be cleaned up after switch-case + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG) + case PSA_ALG_CCM_STAR_NO_TAG: // Explicit fallthrough + #endif // SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT) + case PSA_ALG_CTR: + { + uint32_t offset = operation->processed_length % 16; + + status = sl_se_aes_crypt_ctr(&cmd_ctx, + key_desc, + input_length, + &offset, + operation->iv, + operation->streaming_block, + input, + output); + + if (status != SL_STATUS_OK) { + goto exit; + } + + input += input_length; + actual_output_length += input_length; + operation->processed_length += input_length; + input_length -= input_length; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CFB) + case PSA_ALG_CFB: + { + uint32_t offset = operation->processed_length % 16; + status = sl_se_aes_crypt_cfb128(&cmd_ctx, + key_desc, + operation->direction, + input_length, + &offset, + operation->iv, + input, + output); + + if (status != SL_STATUS_OK) { + goto exit; + } + + input += input_length; + actual_output_length += input_length; + operation->processed_length += input_length; + input_length -= input_length; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_AES_CFB + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_OFB) + case PSA_ALG_OFB: + { + size_t data_length = input_length; + size_t n = operation->processed_length % 16; + + // loop over input data to create output + while (data_length--) { + if (n == 0) { + status = sl_se_aes_crypt_ecb(&cmd_ctx, + key_desc, + SL_SE_ENCRYPT, + 16, + operation->iv, + operation->iv); + if (status != SL_STATUS_OK) { + goto exit; + } + } + *output++ = *input++ ^ operation->iv[n]; + + n = (n + 1) & 0x0F; + } + + input += input_length; + actual_output_length += input_length; + operation->processed_length += input_length; + input_length -= input_length; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_AES_OFB + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) + case PSA_ALG_STREAM_CIPHER: + { + // counter value is at the start of the IV buffer + uint32_t ctr_value = *((uint32_t*)operation->iv); + + // If the counter would wrap, refuse the operation + if (ctr_value > (ctr_value + (input_length / 64))) { + return PSA_ERROR_BAD_STATE; + } + + if (operation->processed_length % 64 != 0) { + // Perform partial block operation until block boundary or end of input + uint8_t chacha20_block[64] = { 0 }; + size_t offset_in_block = operation->processed_length + % sizeof(chacha20_block); + size_t length_in_block = + input_length < (sizeof(chacha20_block) - offset_in_block) + ? input_length + : (sizeof(chacha20_block) - offset_in_block); + uint32_t counter_bytes = __REV(ctr_value); + + // Retrieve streaming block + status = sl_se_chacha20_crypt(&cmd_ctx, + SL_SE_ENCRYPT, + key_desc, + sizeof(chacha20_block), + (const unsigned char*)&counter_bytes, + &operation->iv[4], + chacha20_block, + chacha20_block); + + if (status != SL_STATUS_OK) { + goto exit; + } + + // Calculate stream output + for (size_t i = 0; i < length_in_block; i++) { + output[i] = input[i] ^ chacha20_block[offset_in_block + i]; + } + + input += length_in_block; + actual_output_length += length_in_block; + operation->processed_length += length_in_block; + input_length -= length_in_block; + + // Update the counter if the block is complete + if (offset_in_block + length_in_block == sizeof(chacha20_block)) { + ctr_value++; + } + } + + if (input_length > 0) { + // Perform remainder of operation in a single call + uint32_t counter_bytes = __REV(ctr_value); + + status = sl_se_chacha20_crypt(&cmd_ctx, + SL_SE_ENCRYPT, + key_desc, + input_length, + (const unsigned char*)&counter_bytes, + &operation->iv[4], + input, + &output[actual_output_length]); + + if (status != SL_STATUS_OK) { + goto exit; + } + + // Update the counter with the amount of full blocks processed + ctr_value += input_length / 64; + + input += input_length; + actual_output_length += input_length; + operation->processed_length += input_length; + input_length -= input_length; + } + + // Store the updated counter number to the IV buffer + *((uint32_t*)operation->iv) = ctr_value; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CHACHA20 + + default: + return PSA_ERROR_BAD_STATE; + } + + // If there's anything left in the input buffer, copy it to the context + // This'll only be the case for lagging ciphers + if (input_length > 0) { + if (!lagging + || (input_length >= 16 && !cache_full_block) + || (input_length > 16 && cache_full_block)) { + *output_length = 0; + return PSA_ERROR_BAD_STATE; + } + + memcpy(operation->streaming_block, + input, + input_length); + operation->processed_length += input_length; + } + + exit: + if (status != SL_STATUS_OK) { + *output_length = 0; + if (status == SL_STATUS_FAIL) { + // This specific code maps to 'does not exist' for builtin keys + return PSA_ERROR_DOES_NOT_EXIST; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + } else { + *output_length = actual_output_length; + return PSA_SUCCESS; + } + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_driver_cipher_finish( + sli_se_driver_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + // Finalize cipher operation. This will only output data for algorithms + // which include padding. This is currently only AES-CBC with PKCS#7. + + // Argument check + if (operation == NULL + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Key desc has been properly set by wrapper function + const sl_se_key_descriptor_t *key_desc = &operation->key_desc; + psa_status_t psa_status = validate_key_type(key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + switch (operation->alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_AES_ECB) || defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT) + case PSA_ALG_ECB_NO_PADDING: // Explicit fallthrough + case PSA_ALG_CBC_NO_PADDING: + // No-padding operations can't finish if they haven't processed block-size input + *output_length = 0; + if (operation->processed_length % 16 != 0) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + } else { + psa_status = PSA_SUCCESS; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_ECB || SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + + #if defined(SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: + { + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + break; + } + + // Calculate padding, update, output final block + if (operation->direction == SL_SE_ENCRYPT) { + if (output_size < 16) { + psa_status = PSA_ERROR_BUFFER_TOO_SMALL; + break; + } + size_t padding_bytes = 16 - (operation->processed_length % 16); + memset(&operation->streaming_block[16 - padding_bytes], + padding_bytes, + padding_bytes); + + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + SL_SE_ENCRYPT, + 16, + operation->iv, + operation->streaming_block, + output); + if (status != SL_STATUS_OK) { + *output_length = 0; + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + *output_length = 16; + psa_status = PSA_SUCCESS; + } + } else { + // Expect full-block input + if (operation->processed_length % 16 != 0 + || operation->processed_length < 16) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + break; + } + + uint8_t out_buf[16]; + + // Decrypt the last block + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + SL_SE_DECRYPT, + 16, + operation->iv, + operation->streaming_block, + out_buf); + + if (status != SL_STATUS_OK) { + *output_length = 0; + psa_status = PSA_ERROR_HARDWARE_FAILURE; + break; + } else { + psa_status = PSA_SUCCESS; + } + + size_t padding_bytes = 0; + psa_status = sli_psa_validate_pkcs7_padding(out_buf, + 16, + &padding_bytes); + + if (psa_status == PSA_SUCCESS) { + // The padding was valid + if (output_size < 16 - padding_bytes) { + psa_status = PSA_ERROR_BUFFER_TOO_SMALL; + break; + } + memcpy(output, out_buf, 16 - padding_bytes); + *output_length = 16 - padding_bytes; + } + } + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7 + + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_CFB: + case PSA_ALG_OFB: + case PSA_ALG_STREAM_CIPHER: + // Actual stream ciphers: nothing to do here. + *output_length = 0; + psa_status = PSA_SUCCESS; + break; + + default: + psa_status = PSA_ERROR_BAD_STATE; + } + if (psa_status != PSA_SUCCESS) { + *output_length = 0; + } + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_key_derivation.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_key_derivation.c new file mode 100644 index 000000000..ddc3b8aa9 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_key_derivation.c @@ -0,0 +1,589 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver Key Derivation functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sli_psa_driver_common.h" // sli_psa_zeroize() +#include "sli_se_opaque_functions.h" +#include "sli_se_driver_key_management.h" +#include "sli_se_driver_key_derivation.h" +#include "sli_se_version_dependencies.h" +#include "psa/crypto.h" + +#include "sl_se_manager.h" +#include "sl_se_manager_key_derivation.h" +#include "sl_se_manager_util.h" +#include "sli_se_manager_internal.h" + +#include + +// ----------------------------------------------------------------------------- +// Custom SL PSA driver entry points + +#if defined(SLI_PSA_DRIVER_FEATURE_HKDF) + +psa_status_t sli_se_driver_single_shot_hkdf( + psa_algorithm_t alg, + const psa_key_attributes_t *key_in_attributes, + const uint8_t *key_in_buffer, + size_t key_in_buffer_size, + const uint8_t* info, + size_t info_length, + const uint8_t* salt, + size_t salt_length, + const psa_key_attributes_t *key_out_attributes, + uint8_t *key_out_buffer, + size_t key_out_buffer_size) +{ + // This driver function will not be called unless alg is of HKDF type. + sl_se_hash_type_t sl_hash_alg = SL_SE_HASH_NONE; + psa_algorithm_t psa_hash_alg = PSA_ALG_HKDF_GET_HASH(alg); + switch (psa_hash_alg) { + case PSA_ALG_SHA_1: + sl_hash_alg = SL_SE_HASH_SHA1; + break; + case PSA_ALG_SHA_224: + sl_hash_alg = SL_SE_HASH_SHA224; + break; + case PSA_ALG_SHA_256: + sl_hash_alg = SL_SE_HASH_SHA256; + break; + case PSA_ALG_SHA_384: + sl_hash_alg = SL_SE_HASH_SHA384; + break; + case PSA_ALG_SHA_512: + sl_hash_alg = SL_SE_HASH_SHA512; + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Create input key descriptor. + sl_se_key_descriptor_t key_in_desc = { 0 }; + psa_status_t psa_status = sli_se_key_desc_from_input(key_in_attributes, + key_in_buffer, + key_in_buffer_size, + &key_in_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + size_t key_out_size = PSA_BITS_TO_BYTES(psa_get_key_bits(key_out_attributes)); + + // Check that we don't request more than 255 times the hash digest size. + // This limitation comes from RFC-5869. + if (key_out_size > 255 * PSA_HASH_LENGTH(psa_hash_alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Create output key descriptor. + sl_se_key_descriptor_t key_out_desc = { 0 }; + psa_status = sli_se_key_desc_from_psa_attributes( + key_out_attributes, + key_out_size, + &key_out_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + psa_status = sli_se_set_key_desc_output(key_out_attributes, + key_out_buffer, + key_out_buffer_size, + key_out_size, + &key_out_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Prepare SE command context. + sl_se_command_context_t cmd_ctx = { 0 }; + sl_status_t sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Execute the SE command. + sl_status = sl_se_derive_key_hkdf(&cmd_ctx, + &key_in_desc, + sl_hash_alg, + salt, + salt_length, + info, + info_length, + &key_out_desc); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } else { + psa_status = PSA_SUCCESS; + } + + if (PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(key_out_attributes)) + == PSA_KEY_LOCATION_SLI_SE_OPAQUE) { + // Add the key desc to the output array for opaque keys. + psa_status = store_key_desc_in_context(&key_out_desc, + key_out_buffer, + key_out_buffer_size); + } + + return psa_status; +} + +#endif // SLI_PSA_DRIVER_FEATURE_HKDF + +#if defined(SLI_PSA_DRIVER_FEATURE_PBKDF2) + +psa_status_t sli_se_driver_single_shot_pbkdf2( + psa_algorithm_t alg, + const psa_key_attributes_t *key_in_attributes, + const uint8_t *key_in_buffer, + size_t key_in_buffer_size, + const uint8_t* salt, + size_t salt_length, + const psa_key_attributes_t *key_out_attributes, + uint32_t iterations, + uint8_t *key_out_buffer, + size_t key_out_buffer_size) +{ + sl_se_hash_type_t sl_prf = SL_SE_HASH_NONE; + psa_algorithm_t psa_hash_alg = PSA_ALG_GET_HASH(alg); + + switch (psa_hash_alg) { + case PSA_ALG_SHA_1: + sl_prf = SL_SE_PRF_HMAC_SHA1; + break; + case PSA_ALG_SHA_224: + sl_prf = SL_SE_PRF_HMAC_SHA224; + break; + case PSA_ALG_SHA_256: + sl_prf = SL_SE_PRF_HMAC_SHA256; + break; + case PSA_ALG_SHA_384: + sl_prf = SL_SE_PRF_HMAC_SHA384; + break; + case PSA_ALG_SHA_512: + sl_prf = SL_SE_PRF_HMAC_SHA512; + break; + default: + if (alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { + sl_prf = SL_SE_PRF_AES_CMAC_128; + break; + } + return PSA_ERROR_NOT_SUPPORTED; + } + + // Create input key descriptor. + sl_se_key_descriptor_t key_in_desc = { 0 }; + psa_status_t psa_status = sli_se_key_desc_from_input(key_in_attributes, + key_in_buffer, + key_in_buffer_size, + &key_in_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + size_t key_out_size = PSA_BITS_TO_BYTES(psa_get_key_bits(key_out_attributes)); + + if ( alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128 ) { + #define AES_CMAC_PRF_128_BLOCK_SIZE 128 + // The out key length can atmost be 128 bits long. + if ( !key_out_size || (key_out_size > PSA_BITS_TO_BYTES(AES_CMAC_PRF_128_BLOCK_SIZE)) ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } else { // HMAC based + // In conformance with rfc 8018 (sec 5.2), max output length should not exceed + // 2 ^ 32 -1 * hlen. + // Our max key size is limited by type of key bits in attributes, so no further + // validation is necessary.Our key out size is narrower than the rfc specification. + if ( !key_out_size ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + if ( !iterations ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Create output key descriptor. + sl_se_key_descriptor_t key_out_desc = { 0 }; + psa_status = sli_se_key_desc_from_psa_attributes( + key_out_attributes, + key_out_size, + &key_out_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + psa_status = sli_se_set_key_desc_output(key_out_attributes, + key_out_buffer, + key_out_buffer_size, + key_out_size, + &key_out_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Prepare SE command context. + sl_se_command_context_t cmd_ctx = { 0 }; + sl_status_t sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Execute the SE command. + sl_status = sl_se_derive_key_pbkdf2(&cmd_ctx, + &key_in_desc, + sl_prf, + salt, + salt_length, + iterations, + &key_out_desc); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } else { + psa_status = PSA_SUCCESS; + } + + if (PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(key_out_attributes)) + == PSA_KEY_LOCATION_SLI_SE_OPAQUE) { + // Add the key desc to the output array for opaque keys. + psa_status = store_key_desc_in_context(&key_out_desc, + key_out_buffer, + key_out_buffer_size); + } + + return psa_status; +} + +#endif // SLI_PSA_DRIVER_FEATURE_PBKDF2 + +// ----------------------------------------------------------------------------- +// Driver entry points + +psa_status_t sli_se_driver_key_agreement(psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_ECDH) + + sl_se_key_descriptor_t priv_desc = { 0 }; + sl_se_key_descriptor_t pub_desc = { 0 }; + sl_se_key_descriptor_t shared_desc = { 0 }; + sl_se_command_context_t cmd_ctx = SL_SE_COMMAND_CONTEXT_INIT; + sl_status_t sl_status = SL_STATUS_FAIL; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + size_t padding_bytes = 0; + uint8_t tmp_output_buf[SLI_SE_MAX_PADDED_ECP_PUBLIC_KEY_SIZE] = { 0 }; + #else + uint8_t tmp_output_buf[SLI_SE_MAX_ECP_PUBLIC_KEY_SIZE] = { 0 }; + #endif // SLI_SE_KEY_PADDING_REQUIRED + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || peer_key == NULL + || output == NULL + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + size_t key_bits = psa_get_key_bits(attributes); + + // Check that key_buffer contains private key. + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(key_type)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Only accelerate ECDH. + if (!PSA_ALG_IS_ECDH(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check private key buffer. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if (output_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + #if defined(SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN) + sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + uint32_t se_version = 0; + sl_status = sl_se_get_se_version(&cmd_ctx, &se_version); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + se_version = SLI_VERSION_REMOVE_DIE_ID(se_version); + + // External public key validation is required for older versions of SE FW. + if (SLI_SE_VERSION_PUBKEY_VALIDATION_REQUIRED(se_version)) { + #if defined(MBEDTLS_ECP_C) \ + && defined(MBEDTLS_PSA_CRYPTO_C) \ + && SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 + psa_status = sli_se_driver_validate_pubkey_with_fallback(key_type, + key_bits, + peer_key, + peer_key_length); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + #else + // No fallback code is compiled in, cannot do public key validation. + return PSA_ERROR_NOT_SUPPORTED; + #endif + } + #endif // SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN + + switch (key_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_SECPR1) + case PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1): + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + pub_desc.type = SL_SE_KEY_TYPE_ECC_P192; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + pub_desc.type = SL_SE_KEY_TYPE_ECC_P224; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case 256: + pub_desc.type = SL_SE_KEY_TYPE_ECC_P256; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P384R1) + case 384: + pub_desc.type = SL_SE_KEY_TYPE_ECC_P384; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P384R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P521R1) + case 521: + pub_desc.type = SL_SE_KEY_TYPE_ECC_P521; + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + padding_bytes = SLI_SE_P521_PADDING_BYTES; + #endif + break; + #endif // SLI_PSA_DRIVER_FEATURE_P521R1 + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Set key descriptor attributes. + // If padding is required, the descriptor will be set later as part of + // the padding. If padding is not required, set the descriptor here. + if (pub_desc.type != 0 + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + && padding_bytes == 0 + #endif + ) { + sli_se_key_descriptor_set_plaintext(&pub_desc, + peer_key + 1, + peer_key_length - 1); + sli_se_key_descriptor_set_plaintext(&shared_desc, + tmp_output_buf, + sizeof(tmp_output_buf)); + shared_desc.size = PSA_BITS_TO_BYTES(key_bits) * 2; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_SECPR1 + + #if defined(SLI_PSA_DRIVER_FEATURE_MONTGOMERY) + case PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_MONTGOMERY): + + // Check peer_key is of sufficient size. + if (peer_key_length < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE25519) + case 255: + pub_desc.type = SL_SE_KEY_TYPE_ECC_X25519; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE25519 + + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE448) + case 448: + pub_desc.type = SL_SE_KEY_TYPE_ECC_X448; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE448 + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Set key descriptor attributes. + sli_se_key_descriptor_set_plaintext(&pub_desc, + peer_key, + peer_key_length); + sli_se_key_descriptor_set_plaintext(&shared_desc, + output, + output_size); + shared_desc.size = PSA_BITS_TO_BYTES(key_bits); + break; + #endif // SLI_PSA_DRIVER_FEATURE_MONTGOMERY + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Generate a key descriptor for private key. + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &priv_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Panther crypto engine requires alignment on word boundries instead of byte + // boundaries which is used in the PSA crypto API. + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + uint8_t tmp_priv_padded_buf[SLI_SE_MAX_PADDED_ECP_PRIVATE_KEY_SIZE] = { 0 }; + uint8_t tmp_pub_padded_buf[SLI_SE_MAX_PADDED_ECP_PUBLIC_KEY_SIZE] = { 0 }; + + // Should currently only happen for curve P521. + if (padding_bytes > 0) { + // Can only do padding on non-wrapped keys. + if (PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)) + == PSA_KEY_LOCATION_LOCAL_STORAGE) { + // Pad private key. + sli_se_pad_big_endian(tmp_priv_padded_buf, key_buffer, + PSA_BITS_TO_BYTES(key_bits)); + + // Re-set key descriptor attributes. + sli_se_key_descriptor_set_plaintext(&priv_desc, + tmp_priv_padded_buf, + sizeof(tmp_priv_padded_buf)); + } + + // Pad public key. + sli_se_pad_curve_point(tmp_pub_padded_buf, peer_key + 1, + PSA_BITS_TO_BYTES(key_bits)); + + // Set key descriptor attributes. + sli_se_key_descriptor_set_plaintext(&pub_desc, + tmp_pub_padded_buf, + sizeof(tmp_pub_padded_buf)); + sli_se_key_descriptor_set_plaintext(&shared_desc, + tmp_output_buf, + sizeof(tmp_output_buf)); + shared_desc.size = (PSA_BITS_TO_BYTES(key_bits) + padding_bytes) * 2; + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + // Set key descriptor attributes that are common to all supported curves. + pub_desc.flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; + shared_desc.type = SL_SE_KEY_TYPE_SYMMETRIC; + + // Re-init SE command context. + sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Perform key agreement algorithm (ECDH). + sl_status = sl_se_ecdh_compute_shared_secret(&cmd_ctx, + &priv_desc, + &pub_desc, + &shared_desc); + if (sl_status != SL_STATUS_OK) { + if (sl_status == SL_STATUS_COMMAND_IS_INVALID) { + // This error will be returned if the key type isn't supported. + return PSA_ERROR_NOT_SUPPORTED; + } else { + // If the ECDH operation failed, this is most likely due to the peer key + // being an invalid elliptic curve point. Other sources for failure should + // hopefully have been caught during parameter validation. + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Remove padding bytes and clean up temporary key storage. + if (padding_bytes > 0) { + sli_se_unpad_curve_point(tmp_output_buf, + tmp_output_buf, + PSA_BITS_TO_BYTES(key_bits)); + sli_psa_zeroize(tmp_priv_padded_buf, sizeof(tmp_priv_padded_buf)); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + // Montgomery curve computations do not require the temporary buffer to store the y-coord. + if (key_type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { + memcpy(output, tmp_output_buf, PSA_BITS_TO_BYTES(key_bits)); + sli_psa_zeroize(tmp_output_buf, sizeof(tmp_output_buf)); + } + + *output_length = PSA_BITS_TO_BYTES(key_bits); + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_ECDH + + (void) attributes; + (void) key_buffer; + (void) peer_key; + (void) output; + (void) output_length; + (void) alg; + (void) key_buffer_size; + (void) peer_key_length; + (void) output_size; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_ECDH +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_key_management.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_key_management.c new file mode 100644 index 000000000..f105233e3 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_key_management.c @@ -0,0 +1,1853 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver Key Management functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_opaque_types.h" +#include "sli_se_opaque_functions.h" +#include "sli_se_driver_key_management.h" +#include "sli_psa_driver_common.h" // sli_psa_zeroize() +#include "sli_se_version_dependencies.h" + +#include "sl_se_manager_key_derivation.h" +#include "sl_se_manager_internal_keys.h" +#include "sl_se_manager_util.h" +#include "sli_se_manager_internal.h" + +#include + +// ----------------------------------------------------------------------------- +// Static constants + +#if defined(SLI_PSA_DRIVER_FEATURE_P192R1) +static const uint8_t ecc_p192_n[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x99, 0xde, 0xf8, 0x36, 0x14, 0x6b, 0xc9, 0xb1, 0xb4, 0xd2, 0x28, 0x31 +}; +#endif + +#if defined(SLI_PSA_DRIVER_FEATURE_P224R1) +static const uint8_t ecc_p224_n[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x16, 0xa2, 0xe0, 0xb8, 0xf0, 0x3e, 0x13, 0xdd, 0x29, 0x45, 0x5c, 0x5c, 0x2a, 0x3d +}; +#endif + +#if defined(SLI_PSA_DRIVER_FEATURE_P256R1) +static const uint8_t ecc_p256_n[] = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51 +}; +#endif + +#if defined(SLI_PSA_DRIVER_FEATURE_P384R1) +static const uint8_t ecc_p384_n[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x63, 0x4d, 0x81, 0xf4, 0x37, 0x2d, 0xdf, 0x58, 0x1a, 0x0d, 0xb2, 0x48, 0xb0, 0xa7, 0x7a, 0xec, 0xec, 0x19, 0x6a, 0xcc, 0xc5, 0x29, 0x73 +}; +#endif + +#if defined(SLI_PSA_DRIVER_FEATURE_P521R1) +static const uint8_t ecc_p521_n[] = { + 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x51, 0x86, 0x87, 0x83, 0xbf, 0x2f, 0x96, 0x6b, 0x7f, 0xcc, 0x01, 0x48, 0xf7, 0x09, 0xa5, 0xd0, 0x3b, 0xb5, 0xc9, 0xb8, 0x89, 0x9c, 0x47, 0xae, 0xbb, 0x6f, 0xb7, 0x1e, 0x91, 0x38, 0x64, 0x09 +}; +#endif + +// ----------------------------------------------------------------------------- +// Static functions + +/** + * @brief + * Clamp if Montgomery or Twisted Edwards private key + * + * @param attributes + * The PSA attributes struct representing a key + * @param key_data + * Key data + * @param key_bits + * Key size in bits + * @returns + * N/A + */ +static void clamp_private_key_if_needed(const psa_key_attributes_t* attributes, + uint8_t *key_data, + size_t key_bits) +{ + psa_key_type_t key_type = psa_get_key_type(attributes); + + // Apply clamping + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type) + && ((PSA_KEY_TYPE_ECC_GET_FAMILY(key_type) == PSA_ECC_FAMILY_MONTGOMERY))) { + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE25519) + case 255: + key_data[0] &= 248U; + key_data[31] &= 127U; + key_data[31] |= 64U; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE25519 + + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE448) + case 448: + key_data[0] &= 252U; + key_data[55] |= 128U; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE448 + + default: + (void) attributes; + (void) key_data; + (void) key_bits; + break; + } + } +} + +/** + * @brief + * Validate that the key descriptor mathces the PSA attributes struct. + * + * @param attributes + * The PSA attributes struct representing a key + * @param key_size + * Size of the key + * @param key_desc + * The SE manager key struct representing the same key + * @returns + * PSA_SUCCESS if the structures match, + * PSA_ERROR_INVALID_ARGUMENT otherwise + */ +static psa_status_t validate_key_desc(const psa_key_attributes_t* attributes, + size_t key_size, + const sl_se_key_descriptor_t *key_desc) +{ + if (key_desc == NULL || attributes == NULL || key_size == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // Build a new key descriptor from attributes and check that they match + sl_se_key_descriptor_t new_key_desc = { 0 }; + psa_status_t status = + sli_se_key_desc_from_psa_attributes(attributes, key_size, &new_key_desc); + if (status != PSA_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (new_key_desc.type != key_desc->type + || new_key_desc.size != key_desc->size + || new_key_desc.flags != key_desc->flags + || new_key_desc.password != key_desc->password + || new_key_desc.domain != key_desc->domain) { + return PSA_ERROR_INVALID_ARGUMENT; + } + return PSA_SUCCESS; +} + +/** + * @brief + * Set the number of bytes of key buffer used for storing the key. + * + * @param attributes[in] + * The PSA attributes struct representing a key + * @param data_size[in] + * Size of the data that has been stored (excluding the 0x04 byte for public + * keys) + * @param key_buffer_length[out] + * Actually used key buffer space + * @returns + * PSA_SUCCESS if key_buffer_length can be set properly, + * PSA_ERROR_NOT_SUPPORTED if unsupported location is encountered. + */ +static psa_status_t set_key_buffer_length( + const psa_key_attributes_t *attributes, + size_t data_size, + size_t *key_buffer_length) +{ + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); + *key_buffer_length = 0; + switch (location) { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + if (sli_se_has_format_byte(psa_get_key_type(attributes))) { + data_size++; // Add the format byte offset + } + *key_buffer_length = data_size; + break; + + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + data_size = sli_se_word_align(data_size); + #endif + *key_buffer_length = sizeof(sli_se_opaque_wrapped_key_context_t) + + data_size; + break; + #endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } + + return PSA_SUCCESS; +} + +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + +static psa_status_t sli_se_driver_validate_ecc_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + size_t *bits) +{ + // Argument check. + if (attributes == NULL + || data == NULL + || data_length == 0 + || bits == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_type_t key_type = psa_get_key_type(attributes); + + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_SECPR1) + case PSA_ECC_FAMILY_SECP_R1: { + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { // Private key. + const void *modulus_ptr = NULL; + *bits = psa_get_key_bits(attributes); + + // Determine key bit-size + if (*bits == 0) { + *bits = data_length * 8; + } else { + if (PSA_BITS_TO_BYTES(*bits) != data_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + switch (*bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + modulus_ptr = ecc_p192_n; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + // Series-2-config-1 devices do not support SECP224R1. + case 224: + modulus_ptr = ecc_p224_n; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case 256: + modulus_ptr = ecc_p256_n; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P384R1) + case 384: + modulus_ptr = ecc_p384_n; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P384R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P521R1) + case 521: + modulus_ptr = ecc_p521_n; + break; + case 528: + // Maybe a 521 bit long key which has been padded to 66 bytes. + // Make sure the key size is not actually 528 + if (psa_get_key_bits(attributes) == 528) { + return PSA_ERROR_NOT_SUPPORTED; + } + // Actually a 521 bit long key which has been padded to 66 bytes. + *bits = 521; + modulus_ptr = ecc_p521_n; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P521R1 + + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } + + // Validate the private key. + return_status = sli_psa_validate_ecc_weierstrass_privkey(data, + modulus_ptr, + data_length); + } else if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { // Public key. + // Check that uncompressed representation is given. + if (data[0] != 0x04) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Create ephemeral SE command context. + sl_se_command_context_t cmd_ctx = SL_SE_COMMAND_CONTEXT_INIT; + sl_status_t sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #if defined(SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN) + // SE version 1.2.2 is first version with public key validation + // inside of the SE. + uint32_t se_version = 0; + sl_status = sl_se_get_se_version(&cmd_ctx, &se_version); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if ((se_version & 0x00FFFFFFU) < SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION) { + #if defined(MBEDTLS_ECP_C) \ + && defined(MBEDTLS_PSA_CRYPTO_C) \ + && SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 + return_status = sli_se_driver_validate_pubkey_with_fallback( + key_type, + psa_get_key_bits(attributes), + data, + data_length); + #else + // No fallback code is compiled in, cannot do public key validation + return_status = PSA_ERROR_NOT_SUPPORTED; + #endif + break; + } + #endif // SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN + + // Temporary buffer for storing ECDH input private key, + // possibly padded input public key, and output shared key. + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + + // If input public key requires padding, it will be stored + // starting from the third element. By doing this, and setting + // the first half-word equal to 1, we are guaranteed to not end up + // with a private key that is acidentally greater than the order + // n of the curve group (since the fields size q is greater than n). + uint8_t tmp_key_buffer[2 + SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE] = { 0 }; + #else // SLI_SE_KEY_PADDING_REQUIRED + uint8_t tmp_key_buffer[SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE] = { 0 }; + #endif // SLI_SE_KEY_PADDING_REQUIRED + + // Make sure that ECDH private key is non-zero. + tmp_key_buffer[0] = 1; + + // Input public key descriptor. + sl_se_key_descriptor_t input_public_key_desc = { + .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, + .storage.location.buffer.pointer = (uint8_t*)data + 1, + .storage.location.buffer.size = data_length - 1, + }; + + // Temporary private key descriptor. + sl_se_key_descriptor_t tmp_private_key_desc = { + .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, + .storage.location.buffer.pointer = tmp_key_buffer, + .storage.location.buffer.size = sizeof(tmp_key_buffer), + }; + + // Temporary shared key descriptor. + sl_se_key_descriptor_t tmp_shared_key_desc = { + .type = SL_SE_KEY_TYPE_SYMMETRIC, + .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, + .storage.location.buffer.pointer = tmp_key_buffer, + .storage.location.buffer.size = sizeof(tmp_key_buffer), + }; + + // Determine key bit size (including padding). + *bits = (data_length - 1) * 8 / 2; + + uint8_t padding_bytes = 0; + switch (*bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + input_public_key_desc.type = SL_SE_KEY_TYPE_ECC_P192; + tmp_private_key_desc.type = SL_SE_KEY_TYPE_ECC_P192; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + + case 224: + #if defined(SLI_MBEDTLS_DEVICE_HSE_V1) + // Series-2-config-1 devices do not support SECP224R1. + return PSA_ERROR_NOT_SUPPORTED; + break; + #elif defined(SLI_PSA_DRIVER_FEATURE_P224R1) + input_public_key_desc.type = SL_SE_KEY_TYPE_ECC_P224; + tmp_private_key_desc.type = SL_SE_KEY_TYPE_ECC_P224; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case 256: + input_public_key_desc.type = SL_SE_KEY_TYPE_ECC_P256; + tmp_private_key_desc.type = SL_SE_KEY_TYPE_ECC_P256; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + + #if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) && !defined(_SILICON_LABS_32B_SERIES_3) + + #if defined(SLI_PSA_DRIVER_FEATURE_P384R1) + case 384: + input_public_key_desc.type = SL_SE_KEY_TYPE_ECC_P384; + tmp_private_key_desc.type = SL_SE_KEY_TYPE_ECC_P384; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P384R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P521R1) + case 528: + // Actually a 521 bit long key which has been padded to 66 bytes. + *bits = 521; + padding_bytes = SLI_SE_P521_PADDING_BYTES; + input_public_key_desc.type = SL_SE_KEY_TYPE_ECC_P521; + tmp_private_key_desc.type = SL_SE_KEY_TYPE_ECC_P521; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P521R1 + + #else // SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH && !defined(_SILICON_LABS_32B_SERIES_3) + + case 384: // fall through + case 528: + return PSA_ERROR_NOT_SUPPORTED; + break; + + #endif // SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH && !defined(_SILICON_LABS_32B_SERIES_3) + + default: + return PSA_ERROR_INVALID_ARGUMENT; + break; + } + + // Set missing key descriptor attributes. + input_public_key_desc.flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; + tmp_private_key_desc.flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY; + tmp_shared_key_desc.size = (PSA_BITS_TO_BYTES(*bits) + padding_bytes) * 2; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Should currently only happen for curve P521. + if (padding_bytes > 0) { + // Pad public key. Offset +2 in order to avoid problem with invalid private key. + sli_se_pad_curve_point(tmp_key_buffer + 2, + (uint8_t*)data + 1, + PSA_BITS_TO_BYTES(*bits)); + sli_se_key_descriptor_set_plaintext(&input_public_key_desc, + tmp_key_buffer + 2, + sizeof(tmp_key_buffer) - 2); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + // Perform key agreement algorithm (ECDH). + sl_status = sl_se_ecdh_compute_shared_secret(&cmd_ctx, + &tmp_private_key_desc, + &input_public_key_desc, + &tmp_shared_key_desc); + + // Zero out intermediate results. + if (padding_bytes == 0) { + sli_psa_zeroize(tmp_key_buffer, (PSA_BITS_TO_BYTES(*bits)) * 2); + } + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + else { + sli_psa_zeroize(tmp_key_buffer, + 2 + (PSA_BITS_TO_BYTES(*bits) + padding_bytes) * 2); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_INVALID_ARGUMENT; + } else { + return_status = PSA_SUCCESS; + } + } + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_SECPR1 + + #if defined(SLI_PSA_DRIVER_FEATURE_MONTGOMERY) || defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) + case PSA_ECC_FAMILY_MONTGOMERY: // Explicit fallthrough + case PSA_ECC_FAMILY_TWISTED_EDWARDS: + // Determine key bit-size + if (*bits == 0) { + *bits = data_length * 8; + } else { + if (PSA_BITS_TO_BYTES(*bits) != data_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + switch (*bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE25519) || defined(SLI_PSA_DRIVER_FEATURE_EDWARDS25519) + case 255: + return_status = PSA_SUCCESS; + break; + case 256: + // Maybe a 255 bit long key which has been padded to 32 bytes. + // Make sure the key size is not actually 256 + if (psa_get_key_bits(attributes) == 256) { + return PSA_ERROR_NOT_SUPPORTED; + } + *bits = 255; + return_status = PSA_SUCCESS; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE25519 || SLI_PSA_DRIVER_FEATURE_EDWARDS25519 + + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE448) + case 448: + return_status = PSA_SUCCESS; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE448 + + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_MONTGOMERY || SLI_PSA_DRIVER_FEATURE_EDWARDS + + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } + + return return_status; +} + +#endif // SLI_PSA_DRIVER_FEATURE_ECC + +// ----------------------------------------------------------------------------- +// Global helper functions + +// ------------------------------------- +// Generic helper functions + +/** + * @brief + * Build a key descriptor from a PSA attributes struct + * + * @param attributes + * The PSA attributes struct representing a key + * @param key_size + * Size of the key + * @param key_desc + * The SE manager key struct representing the same key + * @returns + * PSA_SUCCESS on success + * PSA_ERROR_INVALID_ARGUMENT on invalid attributes + */ +psa_status_t sli_se_key_desc_from_psa_attributes( + const psa_key_attributes_t *attributes, + size_t key_size, + sl_se_key_descriptor_t *key_desc) +{ + size_t attributes_key_size = + PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + if (attributes_key_size != 0) { + // If attributes key size is nonzero, it must be equal to key_size + if (attributes_key_size != key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + psa_key_type_t type = psa_get_key_type(attributes); + psa_key_usage_t usage = psa_get_key_usage_flags(attributes); + psa_key_lifetime_t lifetime = psa_get_key_lifetime(attributes); + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(lifetime); + + memset(key_desc, 0, sizeof(sl_se_key_descriptor_t)); + + switch (location) { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + key_desc->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT; + break; + + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + // For the time being, volatile keys directly in SE internal RAM are not + // supported. Once they are, use the persistence info from the key + // lifetime to switch between EXTERNAL_WRAPPED and INTERNAL_VOLATILE. + key_desc->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED; + break; + #endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + + default: + return PSA_ERROR_DOES_NOT_EXIST; + } + + // Dont't accept zero-length keys + if (key_size == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (type == PSA_KEY_TYPE_RAW_DATA + || type == PSA_KEY_TYPE_HMAC + || type == PSA_KEY_TYPE_DERIVE) { + // Set attributes + key_desc->type = SL_SE_KEY_TYPE_SYMMETRIC; + key_desc->size = key_size; + } else + + #if defined(SLI_PSA_DRIVER_FEATURE_AES) + if (type == PSA_KEY_TYPE_AES) { + switch (key_size) { + case 16: + key_desc->type = SL_SE_KEY_TYPE_AES_128; + break; + case 24: + key_desc->type = SL_SE_KEY_TYPE_AES_192; + break; + case 32: + key_desc->type = SL_SE_KEY_TYPE_AES_256; + break; + default: + // SE doesn't support off-size AES keys + return PSA_ERROR_INVALID_ARGUMENT; + } + key_desc->size = key_size; + } else + #endif // SLI_PSA_DRIVER_FEATURE_AES + + #if defined(SLI_PSA_DRIVER_FEATURE_CHACHA20) \ + || defined(SLI_PSA_DRIVER_FEATURE_CHACHAPOLY) + if (type == PSA_KEY_TYPE_CHACHA20) { + if (key_size != 0x20) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // Set attributes + key_desc->type = SL_SE_KEY_TYPE_CHACHA20; + key_desc->size = 0x20; + } else + #endif // SLI_PSA_DRIVER_FEATURE_CHACHA20 || SLI_PSA_DRIVER_FEATURE_CHACHAPOLY + + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + if (PSA_KEY_TYPE_IS_ECC(type)) { + #if defined(SLI_PSA_DRIVER_FEATURE_SECPR1) + if (PSA_KEY_TYPE_ECC_GET_FAMILY(type) == PSA_ECC_FAMILY_SECP_R1) { + // Find key size and set key type + switch (key_size) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 24: + key_desc->type = SL_SE_KEY_TYPE_ECC_P192; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + // Series-2-config-1 devices do not support SECP224R1. + case 28: + key_desc->type = SL_SE_KEY_TYPE_ECC_P224; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case 32: + key_desc->type = SL_SE_KEY_TYPE_ECC_P256; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P384R1) + case 48: + key_desc->type = SL_SE_KEY_TYPE_ECC_P384; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P384R1 + + #if defined(SLI_PSA_DRIVER_FEATURE_P521R1) + case 66: + key_desc->type = SL_SE_KEY_TYPE_ECC_P521; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P521R1 + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + } else + #endif // SLI_PSA_DRIVER_FEATURE_SECPR1 + + #if defined(SLI_PSA_DRIVER_FEATURE_MONTGOMERY) + if (PSA_KEY_TYPE_ECC_GET_FAMILY(type) == PSA_ECC_FAMILY_MONTGOMERY) { + // Find key size and set key type + switch (key_size) { + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE25519) + case 32: + key_desc->type = SL_SE_KEY_TYPE_ECC_X25519; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE25519 + + #if defined(SLI_PSA_DRIVER_FEATURE_CURVE448) + case 56: + key_desc->type = SL_SE_KEY_TYPE_ECC_X448; + break; + #endif // SLI_PSA_DRIVER_FEATURE_CURVE448 + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + } else + #endif // SLI_PSA_DRIVER_FEATURE_MONTGOMERY + + #if defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) + if (PSA_KEY_TYPE_ECC_GET_FAMILY(type) == PSA_ECC_FAMILY_TWISTED_EDWARDS) { + // Find key size and set key type + switch (key_size) { + #if defined(SLI_PSA_DRIVER_FEATURE_EDWARDS25519) + case 32: + key_desc->type = SL_SE_KEY_TYPE_ECC_ED25519; + break; + #endif // SLI_PSA_DRIVER_FEATURE_EDWARDS25519 + default: + return PSA_ERROR_NOT_SUPPORTED; + } + } else + #endif // SLI_PSA_DRIVER_FEATURE_EDWARDS + + { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Set asymmetric args + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(type)) { + key_desc->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY; + } else if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(type)) { + key_desc->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Decide whether the key will be used for signing or derivation + bool is_signing = (usage & (PSA_KEY_USAGE_SIGN_HASH | PSA_KEY_USAGE_VERIFY_HASH | PSA_KEY_USAGE_SIGN_MESSAGE | PSA_KEY_USAGE_VERIFY_MESSAGE)) != 0; + bool is_deriving = (usage & (PSA_KEY_USAGE_DERIVE | PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT)) != 0; + + if (is_signing && !is_deriving) { + key_desc->flags |= SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY; + } else if (!is_signing && is_deriving) { + key_desc->flags = (key_desc->flags & ~SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY); + } else if (is_signing && is_deriving) { + // SE does not support a key to be used for both signing and derivation operations. + return PSA_ERROR_NOT_SUPPORTED; + } else { + // ECC key is not setup for either signing or deriving. Default to not setting + // the 'sign' flag (legacy behaviour) + key_desc->flags = (key_desc->flags & ~SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY); + } + } else + #endif // SLI_PSA_DRIVER_FEATURE_ECC + { + return PSA_ERROR_NOT_SUPPORTED; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + // Add key restrictions. Only relevant for opaque drivers. If these properties + // are set for transparent drivers, key generation becomes illegal, as the SE + // does not allow writing a protected key to a plaintext buffer. + if (location != PSA_KEY_LOCATION_LOCAL_STORAGE) { + bool can_export = usage & PSA_KEY_USAGE_EXPORT; + bool can_copy = usage & PSA_KEY_USAGE_COPY; + + if (can_copy) { + // We do not support copying opaque keys (currently). + return PSA_ERROR_NOT_SUPPORTED; + } + if (!can_export) { + key_desc->flags |= SL_SE_KEY_FLAG_NON_EXPORTABLE; + } + } + #else // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + (void)usage; + #endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + + return PSA_SUCCESS; +} + +/** + * @brief + * Get the key descriptor from the key buffer and attributes + */ +psa_status_t sli_se_key_desc_from_input(const psa_key_attributes_t* attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + sl_se_key_descriptor_t *key_desc) +{ + psa_key_lifetime_t lifetime = psa_get_key_lifetime(attributes); + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(lifetime); + uint32_t key_size = 0; // Retrieved in different ways for different locations + switch (location) { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + { + uint8_t *actual_key_buffer = (uint8_t *)key_buffer; + size_t actual_key_buffer_size = key_buffer_size; + + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + psa_key_type_t key_type = psa_get_key_type(attributes); + if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { + // For ECC public keys, the attributes key size is always the factor + // determining the curve size + key_size = PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + if (sli_se_has_format_byte(key_type)) { + // Need to account for the format byte + if (*key_buffer != 0x04) { + return PSA_ERROR_INVALID_ARGUMENT; + } + actual_key_buffer += 1; + actual_key_buffer_size -= 1; + if (actual_key_buffer_size != 2 * key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + #if defined(SLI_PSA_DRIVER_FEATURE_MONTGOMERY) \ + || defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) + } else if ((PSA_KEY_TYPE_ECC_GET_FAMILY(key_type) + == PSA_ECC_FAMILY_MONTGOMERY) + || (PSA_KEY_TYPE_ECC_GET_FAMILY(key_type) + == PSA_ECC_FAMILY_TWISTED_EDWARDS)) { + if (actual_key_buffer_size != key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + #endif // SLI_PSA_DRIVER_FEATURE_MONTGOMERY || SLI_PSA_DRIVER_FEATURE_EDWARDS + } else { + // No other curves supported yet. + return PSA_ERROR_NOT_SUPPORTED; + } + } else + #endif // SLI_PSA_DRIVER_FEATURE_ECC + + { + key_size = key_buffer_size; + } + + // Fill the key desc from attributes + psa_status_t psa_status = sli_se_key_desc_from_psa_attributes(attributes, + key_size, + key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + sli_se_key_descriptor_set_plaintext(key_desc, + actual_key_buffer, + actual_key_buffer_size); + break; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + { + if (key_buffer_size < sizeof(sli_se_opaque_key_context_header_t)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + sli_se_opaque_key_context_header_t *key_context_header = + (sli_se_opaque_key_context_header_t *)key_buffer; + + if (key_context_header->struct_version != SLI_SE_OPAQUE_KEY_CONTEXT_VERSION) { + return PSA_ERROR_STORAGE_FAILURE; + } + + if (key_context_header->builtin_key_id != 0) { + sl_se_key_descriptor_t builtin_key_desc; + switch (key_context_header->builtin_key_id) { + case SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY: + builtin_key_desc = (sl_se_key_descriptor_t) SL_SE_APPLICATION_SECURE_BOOT_KEY; + break; + case SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY: + builtin_key_desc = (sl_se_key_descriptor_t) SL_SE_APPLICATION_SECURE_DEBUG_KEY; + break; + case SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY: + builtin_key_desc = (sl_se_key_descriptor_t) SL_SE_APPLICATION_AES_128_KEY; + break; + case SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY: + builtin_key_desc = (sl_se_key_descriptor_t) SL_SE_TRUSTZONE_ROOT_KEY; + break; + #if defined(SLI_PSA_DRIVER_FEATURE_ATTESTATION) + case SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY: + builtin_key_desc = (sl_se_key_descriptor_t) SL_SE_APPLICATION_ATTESTATION_KEY; + break; + case SL_SE_KEY_SLOT_SE_ATTESTATION_KEY: + builtin_key_desc = (sl_se_key_descriptor_t) SL_SE_SYSTEM_ATTESTATION_KEY; + break; + #endif // SLI_PSA_DRIVER_FEATURE_ATTESTATION + default: + return PSA_ERROR_DOES_NOT_EXIST; + } + memcpy(key_desc, &builtin_key_desc, sizeof(*key_desc)); + return PSA_SUCCESS; + } else { + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + if (key_buffer_size < sizeof(sli_se_opaque_wrapped_key_context_t)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reconstruct key_desc from the key context + memset(key_desc, 0, sizeof(sl_se_key_descriptor_t)); + + // Refer to wrapped key context in input + sli_se_opaque_wrapped_key_context_t key_context_temp; + sli_se_opaque_wrapped_key_context_t *key_context = + (sli_se_opaque_wrapped_key_context_t *)key_buffer; + key_desc->storage.location.buffer.pointer = + (uint8_t *)&(key_context->wrapped_buffer); + + // If the key buffer is unaligned, copy the content into a + // temporary buffer in order to prevent hardfaults caused by + // instructions that do not support unaligned words (e.g. LDRD, LDM). + if ((uintptr_t)key_buffer & 0x3) { + memcpy(&key_context_temp, key_buffer, sizeof(sli_se_opaque_wrapped_key_context_t)); + key_context = &key_context_temp; + } + + key_desc->type = key_context->key_type; + key_desc->size = key_context->key_size; + key_desc->flags = key_context->key_flags; + + key_desc->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED; + key_desc->storage.location.buffer.size = + key_buffer_size - offsetof(sli_se_opaque_wrapped_key_context_t, + wrapped_buffer); + + // Clear temporary key context + if ((uintptr_t)key_buffer & 0x3) { + memset(&key_context_temp, 0, sizeof(sli_se_opaque_wrapped_key_context_t)); + } + + if (sli_key_get_size(key_desc, &key_size) != SL_STATUS_OK) { + memset(key_desc, 0, sizeof(sl_se_key_descriptor_t)); + return PSA_ERROR_INVALID_ARGUMENT; + } + + uint32_t key_full_size = key_size; + + #if defined(SLI_PSA_DRIVER_FEATURE_SECPR1) + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(attributes)) + == PSA_ECC_FAMILY_SECP_R1 + && PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(psa_get_key_type(attributes))) { + key_full_size = 2 * key_full_size; + } + #endif // SLI_PSA_DRIVER_FEATURE_SECPR1 + + if (key_desc->storage.location.buffer.size < key_full_size + SLI_SE_WRAPPED_KEY_OVERHEAD) { + memset(key_desc, 0, sizeof(sl_se_key_descriptor_t)); + return PSA_ERROR_INVALID_ARGUMENT; + } + + #else // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + return PSA_ERROR_NOT_SUPPORTED; + #endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + } + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + + default: + return PSA_ERROR_DOES_NOT_EXIST; + } + + // Run a general validation routine once the key desc has been populated + psa_status_t status = validate_key_desc(attributes, key_size, key_desc); + if (status != PSA_SUCCESS) { + memset(key_desc, 0, sizeof(sl_se_key_descriptor_t)); + return PSA_ERROR_INVALID_ARGUMENT; + } + return PSA_SUCCESS; +} + +/** + * @brief + * Set the relevant location field of the key descriptor + */ +psa_status_t sli_se_set_key_desc_output(const psa_key_attributes_t* attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t key_size, + sl_se_key_descriptor_t *key_desc) +{ + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); + switch (location) { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + if (key_buffer_size < key_size) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + key_desc->storage.location.buffer.pointer = key_buffer; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + key_buffer_size = sli_se_word_align(key_buffer_size); + #endif + + key_desc->storage.location.buffer.size = key_buffer_size; + break; + + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + key_size = sli_se_word_align(key_size); + #endif + + if (key_buffer_size < sizeof(sli_se_opaque_wrapped_key_context_t) + + key_size) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + key_desc->storage.location.buffer.pointer = + key_buffer + offsetof(sli_se_opaque_wrapped_key_context_t, + wrapped_buffer); + key_desc->storage.location.buffer.size = + key_size + SLI_SE_WRAPPED_KEY_OVERHEAD; + break; + #endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + + default: + return PSA_ERROR_DOES_NOT_EXIST; + } + return PSA_SUCCESS; +} + +#if defined(SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN) \ + && defined(MBEDTLS_ECP_C) \ + && defined(MBEDTLS_PSA_CRYPTO_C) \ + && SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 + +#include "mbedtls/ecp.h" +#include "psa_crypto_core.h" +#include "mbedtls/psa_util.h" + +psa_status_t sli_se_driver_validate_pubkey_with_fallback(psa_key_type_t key_type, + size_t key_bits, + const uint8_t *data, + size_t data_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_group_id grp_id = MBEDTLS_ECP_DP_NONE; + + mbedtls_ecp_group pubkey_grp; + mbedtls_ecp_point pubkey_point; + + mbedtls_ecp_group_init(&pubkey_grp); + mbedtls_ecp_point_init(&pubkey_point); + + // Get software-defined curve structure + grp_id = mbedtls_ecc_group_from_psa(PSA_KEY_TYPE_ECC_GET_FAMILY(key_type), + key_bits); + if (grp_id == MBEDTLS_ECP_DP_NONE) { + goto exit; + } + + psa_status = mbedtls_to_psa_error(mbedtls_ecp_group_load(&pubkey_grp, + grp_id)); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + // Load public key into mbed TLS structure + psa_status = mbedtls_to_psa_error(mbedtls_ecp_point_read_binary( + &pubkey_grp, + &pubkey_point, + data, + data_length) ); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + // Validate key. + psa_status = mbedtls_to_psa_error(mbedtls_ecp_check_pubkey(&pubkey_grp, + &pubkey_point)); + + exit: + mbedtls_ecp_group_free(&pubkey_grp); + mbedtls_ecp_point_free(&pubkey_point); + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) key_type; + (void) key_bits; + (void) data; + (void) data_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +#endif // SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN ... + +// ------------------------------------- +// Opaque helper functions + +#if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + +/** + * @brief + * Store the required parts of the key descriptor in the context placed the + * start of the given key buffer. + */ +psa_status_t store_key_desc_in_context(sl_se_key_descriptor_t *key_desc, + uint8_t *key_buffer, + size_t key_buffer_size) +{ + if (key_buffer_size < sizeof(sli_se_opaque_wrapped_key_context_t)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + sli_se_opaque_wrapped_key_context_t *key_context = + (sli_se_opaque_wrapped_key_context_t *)key_buffer; + key_context->header.struct_version = SLI_SE_OPAQUE_KEY_CONTEXT_VERSION; + key_context->header.builtin_key_id = 0; + memset(&key_context->header.reserved, 0, sizeof(key_context->header.reserved)); + key_context->key_type = key_desc->type; + key_context->key_size = key_desc->size; + key_context->key_flags = key_desc->flags; + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + +// ----------------------------------------------------------------------------- +// Driver entry points + +// ------------------------------------- +// Generic driver entry points + +psa_status_t sli_se_driver_generate_key(const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length) +{ + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t key_bits = psa_get_key_bits(attributes); + size_t key_size = PSA_BITS_TO_BYTES(key_bits); + if (key_size == 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + if (PSA_KEY_TYPE_IS_UNSTRUCTURED(key_type) + && ((key_bits & 0x7) != 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } else if (PSA_KEY_TYPE_IS_PUBLIC_KEY(key_type)) { + // PSA Crypto defines generate_key to be an invalid call with a key type + // of public key. + return PSA_ERROR_NOT_SUPPORTED; + } + + // Generate a key desc + sl_se_key_descriptor_t key_desc = { 0 }; + psa_status_t psa_status = + sli_se_key_desc_from_psa_attributes(attributes, + key_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + psa_status = sli_se_set_key_desc_output(attributes, + key_buffer, + key_buffer_size, + key_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Generate the key using SE manager + sl_se_command_context_t cmd_ctx = { 0 }; + sl_status_t sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sl_status = sl_se_generate_key(&cmd_ctx, &key_desc); + if (sl_status != SL_STATUS_OK) { + if (sl_status == SL_STATUS_COMMAND_IS_INVALID) { + // This error will be returned if the key type isn't supported. + psa_status = PSA_ERROR_NOT_SUPPORTED; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + goto exit; + } else { + if (PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)) + == PSA_KEY_LOCATION_LOCAL_STORAGE) { + // Apply clamping if this is a Montgomery key. + clamp_private_key_if_needed(attributes, key_buffer, key_bits); + } + + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + else { + // Add the key desc to the output array for opaque keys. + psa_status = store_key_desc_in_context(&key_desc, + key_buffer, + key_buffer_size); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + } + #endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + + psa_status = set_key_buffer_length(attributes, key_size, key_buffer_length); + } + // Cleanup + exit: + sl_status = sl_se_deinit_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + return psa_status; +} + +psa_status_t sli_se_driver_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || data == NULL + || data_size == 0 + || data_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Build key descs for the private key + sl_se_key_descriptor_t priv_key_desc = { 0 }; + psa_status_t psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &priv_key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // ECC public keys are written in uncompressed format with a preceeding 0x04 + // format byte. This byte should however not be present for Montgomery keys + uint32_t prepend_format_byte = 1; + #if defined(SLI_PSA_DRIVER_FEATURE_MONTGOMERY) || defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) + if ((PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(attributes)) + == PSA_ECC_FAMILY_MONTGOMERY) + || (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(attributes)) + == PSA_ECC_FAMILY_TWISTED_EDWARDS)) { + prepend_format_byte = 0; + } + #endif // SLI_PSA_DRIVER_FEATURE_MONTGOMERY || SLI_PSA_DRIVER_FEATURE_EDWARDS + + sl_se_key_descriptor_t pub_key_desc = priv_key_desc; + size_t padding = 0; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Since we were able to successfully build a key desc, we know that the key + // is supported. However, we must also account for non-word-aligned keys + uint8_t temp_pub_buffer[SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE] = { 0 }; + uint8_t temp_priv_buffer[SLI_SE_MAX_PADDED_KEY_PAIR_SIZE] = { 0 }; + size_t priv_key_size = PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + if (PSA_KEY_TYPE_IS_ECC(psa_get_key_type(attributes))) { + padding = sli_se_get_padding(PSA_BITS_TO_BYTES(psa_get_key_bits(attributes))); + } + if (padding > 0) { + if (priv_key_desc.storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { + // We must only fix the padding for plaintext private keys. Opaque padding + // is already handled in import_key + if (key_buffer_size < priv_key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_big_endian(temp_priv_buffer, key_buffer, priv_key_size); + sli_se_key_descriptor_set_plaintext(&priv_key_desc, + temp_priv_buffer, + sizeof(temp_priv_buffer)); + } + // Point the key desc to the temp buffer + sli_se_key_descriptor_set_plaintext(&pub_key_desc, + temp_pub_buffer, + sizeof(temp_pub_buffer)); + } else + #endif // SLI_SE_KEY_PADDING_REQUIRED + + { + // Account for format byte where applicable + sli_se_key_descriptor_set_plaintext(&pub_key_desc, + data + prepend_format_byte, + data_size - prepend_format_byte); + } + + // Clear non exportable and private key flags from the public key desc, + // And set the public flag + pub_key_desc.flags &= ~(SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY + | SL_SE_KEY_FLAG_NON_EXPORTABLE); + pub_key_desc.flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; + uint32_t storage_size = 0; + sl_status_t sl_status = + sli_key_get_storage_size(&pub_key_desc, &storage_size); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + // We must fit entire output key + possibly a format byte + // We don't have to fit the padding bytes into the data buffer. + storage_size = storage_size + prepend_format_byte - (2 * padding); + if (data_size < storage_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + sl_se_command_context_t cmd_ctx = { 0 }; + sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #if defined(SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED) + psa_status = sli_se_check_eddsa_errata(attributes, &cmd_ctx); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + #endif // SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED + + sl_status = sl_se_export_public_key(&cmd_ctx, &priv_key_desc, &pub_key_desc); + if (sl_status == SL_STATUS_FAIL) { + // This specific code maps to 'does not exist' for builtin keys + psa_status = PSA_ERROR_DOES_NOT_EXIST; + } else if (sl_status != SL_STATUS_OK) { + if (sl_status == SL_STATUS_COMMAND_IS_INVALID) { + // This error will be returned if the key type isn't supported. + psa_status = PSA_ERROR_NOT_SUPPORTED; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + } else { + psa_status = PSA_SUCCESS; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + if (padding > 0) { + // Now it is time to copy the actual ket from the temp buffer to the + // output buffer. Write to an offset if applicable, to account for the + // format byte + sli_se_unpad_curve_point(temp_pub_buffer, + data + prepend_format_byte, + (storage_size - prepend_format_byte) / 2); + sli_psa_zeroize(temp_priv_buffer, priv_key_size); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + // Write the uncompressed format byte and actual data length + if (prepend_format_byte == 1) { + *data = 0x04; + } + *data_length = storage_size; + } + + // Cleanup + sl_status = sl_se_deinit_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) data; + (void) data_size; + (void) data_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +// ------------------------------------- +// Opaque driver entry points + +psa_status_t sli_se_opaque_generate_key(const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length) +{ + return sli_se_driver_generate_key(attributes, + key_buffer, + key_buffer_size, + key_buffer_length); +} + +psa_status_t sli_se_opaque_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + return sli_se_driver_export_public_key(attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length); +} + +#if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + +psa_status_t sli_se_opaque_copy_key(const psa_key_attributes_t *attributes, + const uint8_t *source_key, + size_t source_key_length, + uint8_t *target_key_buffer, + size_t target_key_buffer_size, + size_t *target_key_buffer_length) +{ + size_t bits = 0; + return sli_se_opaque_import_key(attributes, + source_key, + source_key_length, + target_key_buffer, + target_key_buffer_size, + target_key_buffer_length, + &bits); +} + +psa_status_t sli_se_opaque_import_key(const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || data == NULL + || data_length == 0 + || key_buffer_length == NULL + || bits == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + *key_buffer_length = 0; + + psa_key_type_t key_type = psa_get_key_type(attributes); + + // Store bits value for imported key + *bits = 8 * data_length; + + switch (PSA_KEY_TYPE_ECC_GET_FAMILY(key_type)) { + #if defined(SLI_PSA_DRIVER_FEATURE_SECPR1) + case PSA_ECC_FAMILY_SECP_R1: + if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { + *bits -= 8; + *bits /= 2; + } + if (*bits == PSA_BITS_TO_BYTES(521) * 8) { + *bits = 521; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_SECPR1 + + #if defined(SLI_PSA_DRIVER_FEATURE_MONTGOMERY) || defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) + case PSA_ECC_FAMILY_MONTGOMERY: + case PSA_ECC_FAMILY_TWISTED_EDWARDS: + if (data_length == 32) { + *bits = 255; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_MONTGOMERY || SLI_PSA_DRIVER_FEATURE_EDWARDS + + default: + break; + } + + size_t offset = 0; + size_t padding = 0; + size_t key_size = 0; + + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + if (PSA_KEY_TYPE_IS_ECC(key_type)) { + // Validate key and get size. + psa_status = sli_se_driver_validate_ecc_key(attributes, + data, + data_length, + &key_size); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + key_size = PSA_BITS_TO_BYTES(key_size); + if (sli_se_has_format_byte(key_type)) { + data_length -= 1; + data += 1; + } + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + if (PSA_KEY_TYPE_ECC_GET_FAMILY(key_type) == PSA_ECC_FAMILY_SECP_R1) { + // We must add some padding if offset is nonzero + offset = sli_se_get_padding(key_size); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + } else + #endif // SLI_PSA_DRIVER_FEATURE_ECC + + { + key_size = data_length; + } + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Size must at least fit max ECC key size plus padding + uint8_t temp_buffer[SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE] = { 0 }; + #endif + + // Create a key desc that will represent the wrapped key + sl_se_key_descriptor_t imported_key_desc = { 0 }; + psa_status = + sli_se_key_desc_from_psa_attributes(attributes, + key_size, + &imported_key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + // Create a key desc representing the plaintext input key + sl_se_key_descriptor_t plaintext_key_desc = imported_key_desc; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + if (offset == 0) { + sli_se_key_descriptor_set_plaintext(&plaintext_key_desc, data, data_length); + } else { + // We must account for the offset. + // Write the key data to offset position in temp buffer + if (sizeof(temp_buffer) < data_length + 2 * offset) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + if (PSA_KEY_TYPE_ECC_GET_FAMILY(key_type) == PSA_ECC_FAMILY_SECP_R1) { + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + sli_se_pad_big_endian(temp_buffer, data, key_size); + padding = offset; + } else { + // Must be public key + sli_se_pad_curve_point(temp_buffer, data, key_size); + padding = 2 * offset; + } + sli_se_key_descriptor_set_plaintext(&plaintext_key_desc, + temp_buffer, + data_length + padding); + } else + #endif // SLI_PSA_DRIVER_FEATURE_ECC + { + return PSA_ERROR_CORRUPTION_DETECTED; + } + } + #else // SLI_SE_KEY_PADDING_REQUIRED + (void)offset; + sli_se_key_descriptor_set_plaintext(&plaintext_key_desc, data, data_length); + #endif // SLI_SE_KEY_PADDING_REQUIRED + + sl_se_command_context_t cmd_ctx = SL_SE_COMMAND_CONTEXT_INIT; + sl_status_t sl_status = SL_STATUS_OK; + // Set location specific properties for the output key buffer + psa_status = sli_se_set_key_desc_output(attributes, + key_buffer, + key_buffer_size, + data_length + padding, + &imported_key_desc); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + + // Call SE manager to import the key + sl_status = sl_se_import_key(&cmd_ctx, + &plaintext_key_desc, + &imported_key_desc); + if (sl_status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + // Add the key desc parameters to the output array + psa_status = store_key_desc_in_context(&imported_key_desc, + key_buffer, + key_buffer_size); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + psa_status = set_key_buffer_length(attributes, + data_length + padding, + key_buffer_length); + } + + // Cleanup + sl_status = sl_se_deinit_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + + exit: + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + sli_psa_zeroize(temp_buffer, sizeof(temp_buffer)); + #endif + + return psa_status; +} + +psa_status_t sli_se_opaque_export_key(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || data == NULL + || data_size == 0 + || data_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // Check that key can be exported + if (!(psa_get_key_usage_flags(attributes) & PSA_KEY_USAGE_EXPORT)) { + return PSA_ERROR_NOT_PERMITTED; + } + + sl_se_key_descriptor_t imported_key = { 0 }; + psa_status_t psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &imported_key); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Create a plaintext key for the output + sl_se_key_descriptor_t plaintext_key = imported_key; + uint32_t storage_size = 0; + psa_key_type_t key_type = psa_get_key_type(attributes); + sl_status_t sl_status = sli_key_get_storage_size(&plaintext_key, &storage_size); + uint32_t prepend_format_byte = sli_se_has_format_byte(key_type); + if (prepend_format_byte == 1) { + // Make room for the format byte + *data = 0x04; + data += 1; + data_size -= 1; + } + + size_t key_bits = psa_get_key_bits(attributes); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // We must handle non-word-aligned keys with a temporary buffer + uint8_t temp_key_buffer[SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE] = { 0 }; + size_t padding = 0; + + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + size_t key_size = PSA_BITS_TO_BYTES(key_bits); + if (PSA_KEY_TYPE_IS_ECC(key_type)) { + padding = sli_se_get_padding(key_size); + } + #endif // SLI_PSA_DRIVER_FEATURE_ECC + + if (padding > 0) { + if (storage_size > sizeof(temp_key_buffer)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + sli_se_key_descriptor_set_plaintext(&plaintext_key, + temp_key_buffer, + sizeof(temp_key_buffer)); + storage_size -= padding; + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { + // Padding must be applied twice for public keys + storage_size -= padding; + } + #endif // SLI_PSA_DRIVER_FEATURE_ECC + } else { + if ((storage_size - imported_key.size) < 4) { + // SE manager has rounded the storage size up for word-alignment + storage_size = imported_key.size; + } + sli_se_key_descriptor_set_plaintext(&plaintext_key, data, data_size); + } + #else // SLI_SE_KEY_PADDING_REQUIRED + sli_se_key_descriptor_set_plaintext(&plaintext_key, data, data_size); + #endif // SLI_SE_KEY_PADDING_REQUIRED + + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (storage_size > data_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Export key + sl_se_command_context_t cmd_ctx = { 0 }; + sl_status = sl_se_init_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sl_status = sl_se_export_key(&cmd_ctx, &imported_key, &plaintext_key); + if (sl_status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + psa_status = PSA_SUCCESS; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Handle padding. + if (padding > 0) { + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + // Copy out the padded key + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + sli_se_unpad_big_endian(temp_key_buffer, data, key_size); + sli_psa_zeroize(temp_key_buffer, key_size); + } else if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { + sli_se_unpad_curve_point(temp_key_buffer, data, key_size); + } else + #endif // SLI_PSA_DRIVER_FEATURE_ECC + { + // This should never happen + return PSA_ERROR_BAD_STATE; + } + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + // Apply clamping if this is a Montgomery key. + clamp_private_key_if_needed(attributes, data, key_bits); + + // Successful operation. Set ouput length + *data_length = storage_size + prepend_format_byte; + } + + // Cleanup + sl_status = sl_se_deinit_command_context(&cmd_ctx); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + return psa_status; +} + +#endif // SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS + +// ------------------------------------- +// Transparent driver entry points + +psa_status_t sli_se_transparent_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length) +{ + psa_key_type_t type = psa_get_key_type(attributes); + + // We don't support generating symmetric keys with transparent drivers; + // it should be done by the core instead. + if (PSA_KEY_TYPE_IS_UNSTRUCTURED(type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + return sli_se_driver_generate_key(attributes, + key_buffer, + key_buffer_size, + key_buffer_length); +} + +psa_status_t sli_se_transparent_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + // If the key is stored transparently and is already a public key, + // let the core handle it. + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(psa_get_key_type(attributes))) { + return PSA_ERROR_NOT_SUPPORTED; + } + + return sli_se_driver_export_public_key(attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length); +} + +psa_status_t sli_se_transparent_import_key(const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + // Our driver only handles ECC keys (since they are better done accelerated). + if (PSA_KEY_TYPE_IS_ECC(psa_get_key_type(attributes))) { + psa_status_t status = sli_se_driver_validate_ecc_key(attributes, + data, + data_length, + bits); + if (status != PSA_SUCCESS) { + return status; + } + + if ( key_buffer_size < data_length ) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(key_buffer, data, data_length); + clamp_private_key_if_needed(attributes, key_buffer, *bits); + *key_buffer_length = data_length; + + return PSA_SUCCESS; + } + + #else // SLI_PSA_DRIVER_FEATURE_ECC + + (void)attributes; + (void)data; + (void)data_length; + (void)key_buffer; + (void)key_buffer_size; + (void)key_buffer_length; + (void)bits; + + #endif // SLI_PSA_DRIVER_FEATURE_ECC + + return PSA_ERROR_NOT_SUPPORTED; +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_mac.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_mac.c new file mode 100644 index 000000000..3c580a32b --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_mac.c @@ -0,0 +1,582 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver Mac functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "sli_psa_driver_common.h" // sli_psa_zeroize() +#include "psa/crypto.h" + +#include "mbedtls/platform.h" + +#include "sli_se_driver_mac.h" +#include "sli_se_manager_internal.h" +#include "sli_se_driver_key_management.h" +#include "sli_psa_driver_common.h" + +#include + +//------------------------------------------------------------------------------ +// Static functions + +#if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + +sl_se_hash_type_t sli_se_hash_type_from_psa_hmac_alg(psa_algorithm_t alg, + size_t *length) +{ + if (!PSA_ALG_IS_HMAC(alg)) { + return SL_SE_HASH_NONE; + } + + psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH(alg); + switch (hash_alg) { + case PSA_ALG_SHA_1: + *length = 20; + return SL_SE_HASH_SHA1; + case PSA_ALG_SHA_224: + *length = 28; + return SL_SE_HASH_SHA224; + case PSA_ALG_SHA_256: + *length = 32; + return SL_SE_HASH_SHA256; + + #if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + case PSA_ALG_SHA_384: + *length = 48; + return SL_SE_HASH_SHA384; + case PSA_ALG_SHA_512: + *length = 64; + return SL_SE_HASH_SHA512; + #endif + + default: + return SL_SE_HASH_NONE; + } +} + +#endif // SLI_PSA_DRIVER_FEATURE_HMAC + +//------------------------------------------------------------------------------ +// Single-shot driver entry points + +psa_status_t sli_se_driver_mac_compute(sl_se_key_descriptor_t *key_desc, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC) + + if (mac == NULL + || mac_length == NULL + || key_desc == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + sl_status_t status; + psa_status_t psa_status = PSA_ERROR_INVALID_ARGUMENT; + sl_se_command_context_t cmd_ctx = { 0 }; + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + #if defined(SLI_PSA_DRIVER_FEATURE_HASH_STATE_64) + uint8_t tmp_hmac[64]; + #else + uint8_t tmp_hmac[32]; + #endif + + size_t requested_length = 0; + sl_se_hash_type_t hash_type = + sli_se_hash_type_from_psa_hmac_alg(alg, &requested_length); + if (hash_type == SL_SE_HASH_NONE) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (PSA_MAC_TRUNCATED_LENGTH(alg) > requested_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (PSA_MAC_TRUNCATED_LENGTH(alg) > 0) { + requested_length = PSA_MAC_TRUNCATED_LENGTH(alg); + } + + if (mac_size < requested_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + uint8_t *temp_key_buf = NULL; + uint32_t key_buffer_size = key_desc->storage.location.buffer.size; + size_t padding = sli_se_get_padding(key_buffer_size); + size_t word_aligned_buffer_size = 0; + + if (padding > 0u) { + // We can only manipulate the transparent keys. + if (key_desc->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { + word_aligned_buffer_size + = sli_se_word_align(key_desc->storage.location.buffer.size); + temp_key_buf = mbedtls_calloc(1, word_aligned_buffer_size); + if (temp_key_buf == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + // Since we know that this must be a plaintext key, we can freely + // modify the key descriptor + memcpy(temp_key_buf, + key_desc->storage.location.buffer.pointer, + key_desc->storage.location.buffer.size); + key_desc->storage.location.buffer.pointer = temp_key_buf; + key_desc->storage.location.buffer.size = word_aligned_buffer_size; + } + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + status = sl_se_hmac(&cmd_ctx, + key_desc, + hash_type, + input, + input_length, + tmp_hmac, + sizeof(tmp_hmac)); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + if (padding > 0u) { + sli_psa_zeroize(temp_key_buf, word_aligned_buffer_size); + mbedtls_free(temp_key_buf); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + if (status == PSA_SUCCESS) { + memcpy(mac, tmp_hmac, requested_length); + *mac_length = requested_length; + } else { + *mac_length = 0; + } + + sli_psa_zeroize(tmp_hmac, sizeof(tmp_hmac)); + + goto exit; + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) \ + && (defined(SLI_PSA_DRIVER_FEATURE_CMAC) \ + || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC)) + else + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + { + size_t output_length = PSA_MAC_TRUNCATED_LENGTH(alg); + if (output_length == 0) { + output_length = 16; + } else if (output_length > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (mac_size < output_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { + #if defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + case PSA_ALG_CBC_MAC: { + uint8_t tmp_buf[16] = { 0 }; + uint8_t tmp_mac[16] = { 0 }; + + if (input_length % 16 != 0 || input_length < 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Do an AES-CBC encrypt with zero IV, keeping only the last block. + while (input_length > 0) { + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + SL_SE_ENCRYPT, + 16, + tmp_mac, + input, + tmp_buf); + + input_length -= 16; + input += 16; + } + + // Copy the requested number of bytes (max 16) to the user buffer. + if (status == SL_STATUS_OK) { + memcpy(mac, tmp_mac, output_length); + sli_psa_zeroize(tmp_mac, sizeof(tmp_mac)); + *mac_length = output_length; + } + + goto exit; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) + case PSA_ALG_CMAC: { + uint8_t tmp_mac[16] = { 0 }; + + status = sl_se_cmac(&cmd_ctx, + key_desc, + input, + input_length, + tmp_mac); + + // Copy the requested number of bytes (max 16) to the user buffer. + if (status == SL_STATUS_OK) { + memcpy(mac, tmp_mac, output_length); + sli_psa_zeroize(tmp_mac, sizeof(tmp_mac)); + *mac_length = output_length; + } + + goto exit; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CMAC + + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } + } + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + exit: + + if (status == SL_STATUS_INVALID_PARAMETER) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + } else if (status == SL_STATUS_FAIL) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + } else if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + psa_status = PSA_SUCCESS; + } + + // Cleanup + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_MAC + + (void)key_desc; + (void)alg; + (void)input; + (void)input_length; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC +} + +//------------------------------------------------------------------------------ +// Multi-part driver entry points + +#if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + +psa_status_t sli_se_driver_mac_sign_setup( + sli_se_driver_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + psa_algorithm_t alg) +{ + if (operation == NULL + || attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Start by resetting context + memset(operation, 0, sizeof(*operation)); + + switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { + #if defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + case PSA_ALG_CBC_MAC: + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (PSA_MAC_TRUNCATED_LENGTH(alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) + case PSA_ALG_CMAC: + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (PSA_MAC_TRUNCATED_LENGTH(alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_CMAC + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + operation->alg = alg; + return PSA_SUCCESS; +} + +psa_status_t sli_se_driver_mac_update(sli_se_driver_mac_operation_t *operation, + sl_se_key_descriptor_t *key_desc, + const uint8_t *input, + size_t input_length) +{ + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + psa_status_t psa_status = PSA_ERROR_NOT_SUPPORTED; + switch (PSA_ALG_FULL_LENGTH_MAC(operation->alg)) { + #if defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + case PSA_ALG_CBC_MAC: + if (input_length == 0) { + psa_status = PSA_SUCCESS; + goto exit; + } + + // Add bytes to the streaming buffer up to the next block boundary + if (operation->ctx.cbcmac.processed_length % 16 != 0) { + size_t bytes_to_boundary + = 16 - operation->ctx.cbcmac.processed_length % 16; + if (input_length < bytes_to_boundary) { + memcpy(&operation->ctx.cbcmac.streaming_block[16 - bytes_to_boundary], + input, + input_length); + operation->ctx.cbcmac.processed_length += input_length; + psa_status = PSA_SUCCESS; + goto exit; + } + + memcpy(&operation->ctx.cbcmac.streaming_block[16 - bytes_to_boundary], + input, + bytes_to_boundary); + input_length -= bytes_to_boundary; + input += bytes_to_boundary; + operation->ctx.cbcmac.processed_length += bytes_to_boundary; + + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + SL_SE_ENCRYPT, + 16, + operation->ctx.cbcmac.iv, + operation->ctx.cbcmac.streaming_block, + operation->ctx.cbcmac.iv); + + if (status == SL_STATUS_FAIL) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } else if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + } + + // Draw all full blocks + while (input_length >= 16) { + status = sl_se_aes_crypt_cbc(&cmd_ctx, + key_desc, + SL_SE_ENCRYPT, + 16, + operation->ctx.cbcmac.iv, + input, + operation->ctx.cbcmac.iv); + + if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + + operation->ctx.cbcmac.processed_length += 16; + input += 16; + input_length -= 16; + } + + if (input_length > 0) { + memcpy(operation->ctx.cbcmac.streaming_block, + input, + input_length); + operation->ctx.cbcmac.processed_length += input_length; + } + + psa_status = PSA_SUCCESS; + goto exit; + #endif // SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) + case PSA_ALG_CMAC: + if (input_length == 0) { + psa_status = PSA_SUCCESS; + goto exit; + } + + status = sl_se_cmac_multipart_update(&operation->ctx.cmac, + &cmd_ctx, + key_desc, + input, + input_length); + if (status == SL_STATUS_FAIL) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } else if (status != SL_STATUS_OK) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + psa_status = PSA_SUCCESS; + goto exit; + #endif // SLI_PSA_DRIVER_FEATURE_CMAC + + default: + psa_status = PSA_ERROR_BAD_STATE; + goto exit; + } + + exit: + // Cleanup + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return psa_status; +} + +psa_status_t sli_se_driver_mac_sign_finish( + sli_se_driver_mac_operation_t *operation, + sl_se_key_descriptor_t *key_desc, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + if (operation == NULL + || mac == NULL + || mac_size == 0 + || mac_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Set maximum output size to 16 or truncated length + if (mac_size > 16) { + mac_size = 16; + } + + size_t truncated_length = PSA_MAC_TRUNCATED_LENGTH(operation->alg); + if (truncated_length != 0 + && mac_size > truncated_length) { + mac_size = truncated_length; + } + + switch (PSA_ALG_FULL_LENGTH_MAC(operation->alg)) { + #if defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + case PSA_ALG_CBC_MAC: { + (void)key_desc; + + if (operation->ctx.cbcmac.processed_length % 16 != 0) { + return PSA_ERROR_BAD_STATE; + } + + // Copy the requested number of bytes (max 16) to the user buffer. + memcpy(mac, operation->ctx.cbcmac.iv, mac_size); + *mac_length = mac_size; + + return PSA_SUCCESS; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) + case PSA_ALG_CMAC: { + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + uint8_t tmp_mac[16] = { 0 }; + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + status = sl_se_cmac_multipart_finish(&operation->ctx.cmac, + &cmd_ctx, + key_desc, + tmp_mac); + if (status != SL_STATUS_OK) { + *mac_length = 0; + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Cleanup + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + *mac_length = 0; + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Copy the requested number of bytes (max 16) to the user buffer. + memcpy(mac, tmp_mac, mac_size); + *mac_length = mac_size; + + return PSA_SUCCESS; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CMAC + + default: + return PSA_ERROR_BAD_STATE; + } +} + +#endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_signature.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_signature.c new file mode 100644 index 000000000..23873cad2 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_driver_signature.c @@ -0,0 +1,1065 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Secure Engine Signature Driver functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_psa_driver_common.h" // sli_psa_zeroize() +#include "sli_se_transparent_types.h" +#include "sli_se_transparent_functions.h" +#include "sli_se_driver_key_management.h" +#include "sli_se_version_dependencies.h" + +#include "sl_se_manager.h" +#include "sli_se_manager_internal.h" +#include "sl_se_manager_signature.h" + +#include + +// ----------------------------------------------------------------------------- +// Static functions + +// ------------------------------------- +// Helpers + +#if defined(SLI_PSA_DRIVER_FEATURE_SIGNATURE) + +/** + * @brief + * Validate that the curve and algorithm combination is supported by hardware + */ +static psa_status_t check_curve_availability( + const psa_key_attributes_t *attributes, + psa_algorithm_t alg) +{ + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curvetype = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + + if (PSA_ALG_IS_RSA_PSS(alg) || PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { + // We shouldn't have a RSA-type alg for a ECC key. + return PSA_ERROR_INVALID_ARGUMENT; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + if (curvetype == PSA_ECC_FAMILY_SECP_R1) { + switch (psa_get_key_bits(attributes)) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: // Intentional + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: // Intentional + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case 256: // Intentional + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_P384R1) + case 384: // Intentional + #endif + #if defined(SLI_PSA_DRIVER_FEATURE_P521R1) + case 521: + #endif + // Only randomized ECDSA is supported on secp-r1 curves + if (!PSA_ALG_IS_RANDOMIZED_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; // This break catches all the supported curves + default: + return PSA_ERROR_NOT_SUPPORTED; + } + } else if (curvetype == PSA_ECC_FAMILY_SECP_K1) { + // Only randomized ECDSA is supported on secp-k1 curves + if (!PSA_ALG_IS_RANDOMIZED_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + // TODO: introduce custom domains to enable secpxxxk1 + return PSA_ERROR_NOT_SUPPORTED; + } else + #endif // SLI_PSA_DRIVER_FEATURE_ECDSA + + #if defined(SLI_PSA_DRIVER_FEATURE_EDDSA) + if (curvetype == PSA_ECC_FAMILY_TWISTED_EDWARDS) { + switch (psa_get_key_bits(attributes)) { + #if defined(SLI_PSA_DRIVER_FEATURE_EDWARDS25519) + case 255: + // Only Ed25519 is supported (and only in context of EdDSA) + if (alg != PSA_ALG_PURE_EDDSA) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_EDWARDS25519 + default: + return PSA_ERROR_NOT_SUPPORTED; + } + } else + #endif // SLI_PSA_DRIVER_FEATURE_EDDSA + + { + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} + +static sl_se_hash_type_t get_hash_for_algorithm(psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_EDDSA) + if (alg == PSA_ALG_PURE_EDDSA) { + // The hash alg parameter is ignored for EdDSA, as it is decided uniqely by + // the alorithm. Return magic value which isn't SL_SE_HASH_NONE. + return (sl_se_hash_type_t)255; + } + #endif // SLI_PSA_DRIVER_FEATURE_EDDSA + + switch (PSA_ALG_SIGN_GET_HASH(alg)) { + #if defined(SLI_PSA_DRIVER_FEATURE_SHA1) + case PSA_ALG_SHA_1: + return SL_SE_HASH_SHA1; + #endif // SLI_PSA_DRIVER_FEATURE_SHA1 + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA224) + case PSA_ALG_SHA_224: + return SL_SE_HASH_SHA224; + #endif // SLI_PSA_DRIVER_FEATURE_SHA224 + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA256) + case PSA_ALG_SHA_256: + return SL_SE_HASH_SHA256; + #endif // SLI_PSA_DRIVER_FEATURE_SHA256 + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA384) + case PSA_ALG_SHA_384: + return SL_SE_HASH_SHA384; + #endif // SLI_PSA_DRIVER_FEATURE_SHA384 + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA512) + case PSA_ALG_SHA_512: + return SL_SE_HASH_SHA512; + #endif // SLI_PSA_DRIVER_FEATURE_SHA512 + + default: + return SL_SE_HASH_NONE; + } +} + +#endif // SLI_PSA_DRIVER_FEATURE_SIGNATURE + +// ------------------------------------- +// Generic (indirect) driver entry points + +static psa_status_t sli_se_sign_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_SIGNATURE) + + uint8_t* tmp_signature_p = signature; + size_t tmp_signature_size = signature_size; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + // Argument check + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || signature == NULL + || signature_size == 0 + || signature_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check the requested algorithm is supported + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(psa_get_key_type(attributes))) { + psa_status = check_curve_availability(attributes, alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + } else { + // Not able to sign using non-ECC keys, or using public keys + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check the requested hashing algorithm is supported + if (get_hash_for_algorithm(alg) == SL_SE_HASH_NONE) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + // Initialize key descriptor and verify key buffer size + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Validate that the output buffer can contain the full signature. + // Both ECDSA and EdDSA share the same signature size. + if (signature_size + < PSA_ECDSA_SIGNATURE_SIZE(psa_get_key_bits(attributes))) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + size_t key_size = PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + size_t offset = sli_se_get_padding(key_size); + #else + size_t offset = 0; + #endif + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) && defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + // P-521 (or any curve size that's not word-multiple) requires alignment on + // word boundaries, instead of byte boundaries such as PSA Crypto defines as + // input here. + uint8_t temp_key_buf[SLI_SE_MAX_PADDED_KEY_PAIR_SIZE] = { 0 }; + uint8_t temp_signature_buffer[SLI_SE_MAX_PADDED_SIGNATURE_SIZE] = { 0 }; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); + + if (offset > 0) { + // We can only manipulate the input key for transparent keys. + // For opaque keys, we will just have to rely on the key import operation + // handling this + if (location == PSA_KEY_LOCATION_LOCAL_STORAGE) { + if ((offset + key_buffer_size) > sizeof(temp_key_buf)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_big_endian(temp_key_buf, key_buffer, key_buffer_size); + // Since we know that this must be a plaintext key, we can freely + // modify the key descriptor + key_desc.storage.location.buffer.pointer = temp_key_buf; + key_desc.storage.location.buffer.size = sizeof(temp_key_buf); + } + + tmp_signature_p = temp_signature_buffer; + tmp_signature_size = sizeof(temp_signature_buffer); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED || SLI_PSA_DRIVER_FEATURE_ECDSA + + if (tmp_signature_size < 2 * (offset + key_size)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + tmp_signature_size = 2 * (offset + key_size); + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #if defined(SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED) + psa_status = sli_se_check_eddsa_errata(attributes, &cmd_ctx); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + #endif // SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED + + // Run signature generation + status = sl_se_ecc_sign(&cmd_ctx, + &key_desc, + get_hash_for_algorithm(alg), + false, + input, + input_length, + tmp_signature_p, + tmp_signature_size + ); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) && defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + if (offset > 0) { + sli_psa_zeroize(temp_key_buf, sizeof(temp_key_buf)); + // Copy over from temp signature + sli_se_unpad_curve_point(temp_signature_buffer, signature, key_size); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED && SLI_PSA_DRIVER_FEATURE_ECDSA + + if (status == SL_STATUS_OK) { + *signature_length = PSA_ECDSA_SIGNATURE_SIZE(psa_get_key_bits(attributes)); + psa_status = PSA_SUCCESS; + } else { + if (status == SL_STATUS_FAIL) { + // Will be returned for missing built-in keys. + psa_status = PSA_ERROR_DOES_NOT_EXIST; + } else if (status == SL_STATUS_COMMAND_IS_INVALID) { + // Will be returned if a key type is not supported (for example). + psa_status = PSA_ERROR_NOT_SUPPORTED; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Cleanup + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_SIGNATURE + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) input; + (void) input_length; + (void) signature; + (void) signature_size; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_SIGNATURE +} + +static psa_status_t sli_se_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + uint8_t* tmp_signature_p = signature; + size_t tmp_signature_size = signature_size; + + // Argument check + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || hash == NULL + || hash_length == 0 + || signature == NULL + || signature_size == 0 + || signature_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check the requested algorithm is ECDSA with randomized k + if (!PSA_ALG_IS_RANDOMIZED_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + // Initialize key descriptor and verify key buffer size + psa_status_t psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Verify and set key attributes + psa_key_type_t keytype = psa_get_key_type(attributes); + + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(keytype)) { + // Validate that the input + psa_status = check_curve_availability(attributes, alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + if (signature_size + < PSA_ECDSA_SIGNATURE_SIZE(psa_get_key_bits(attributes))) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } else { + // Not able to sign using non-ECC keys, or using public keys + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t key_bits = psa_get_key_bits(attributes); + size_t key_size = PSA_BITS_TO_BYTES(key_bits); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + size_t offset = sli_se_get_padding(key_size); + #else + size_t offset = 0; + #endif + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // P-521 (or any curve size that's not word-multiple) requires alignment on + // word boundaries, instead of byte boundaries such as PSA Crypto defines as + // input here. + uint8_t temp_key_buf[SLI_SE_MAX_PADDED_KEY_PAIR_SIZE] = { 0 }; + uint8_t temp_signature_buffer[SLI_SE_MAX_PADDED_SIGNATURE_SIZE] = { 0 }; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); + + if (offset > 0) { + // We can only manipulate the input key for transparent keys. + // For opaque keys, we will just have to rely on the key import operation + // handling this + if (location == PSA_KEY_LOCATION_LOCAL_STORAGE) { + if ((offset + key_buffer_size) > sizeof(temp_key_buf)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_big_endian(temp_key_buf, key_buffer, key_buffer_size); + // Since we know that this must be a plaintext key, we can freely + // modify the key descriptor + key_desc.storage.location.buffer.pointer = temp_key_buf; + key_desc.storage.location.buffer.size = sizeof(temp_key_buf); + } + + tmp_signature_p = temp_signature_buffer; + tmp_signature_size = sizeof(temp_signature_buffer); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + if (tmp_signature_size < 2 * (offset + key_size)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + tmp_signature_size = 2 * (offset + key_size); + + sl_status_t status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Run signature generation + status = sl_se_ecc_sign(&cmd_ctx, + &key_desc, + SL_SE_HASH_NONE, + true, + hash, + hash_length, + tmp_signature_p, + tmp_signature_size); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + if (offset > 0) { + sli_psa_zeroize(temp_key_buf, sizeof(temp_key_buf)); + // Copy over from temp signature + sli_se_unpad_curve_point(temp_signature_buffer, signature, key_size); + } + #endif // SLI_SE_KEY_PADDING_REQUIRED + + if (status == SL_STATUS_OK) { + *signature_length = PSA_ECDSA_SIGNATURE_SIZE(key_bits); + psa_status = PSA_SUCCESS; + } else { + if (status == SL_STATUS_FAIL) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Cleanup + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_ECDSA + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_size; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_ECDSA +} + +static psa_status_t sli_se_verify_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_SIGNATURE) + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || (signature == NULL && signature_length != 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Verify can happen with a public or private key + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(psa_get_key_type(attributes)) + || PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(psa_get_key_type(attributes))) { + // Check the requested algorithm is supported and matches the key type + psa_status = check_curve_availability(attributes, alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check the requested hashing algorithm is supported + if (get_hash_for_algorithm(alg) == SL_SE_HASH_NONE) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (signature_length == 0) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Validate that the signature input is of the expected length. + // Both ECDSA and EdDSA share the same signature size. + if (signature_length + != PSA_ECDSA_SIGNATURE_SIZE(psa_get_key_bits(attributes))) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + // Verify and set key attributes + uint8_t temp_key_buf[SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE] = { 0 }; + psa_key_type_t keytype = psa_get_key_type(attributes); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) && defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + // P-521 (or any curve size that's not word-multiple) requires alignment on word + // boundaries, instead of byte boundaries such as PSA Crypto defines as input here. + uint8_t temp_signature_buffer[SLI_SE_MAX_PADDED_SIGNATURE_SIZE] = { 0 }; + size_t key_size = PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + size_t offset = sli_se_get_padding(key_size); + if (offset > 0) { + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); + + // Only pad transparent keys. + if (location == PSA_KEY_LOCATION_LOCAL_STORAGE) { + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(keytype)) { + if (offset + key_size > sizeof(temp_key_buf)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_big_endian(temp_key_buf, + key_desc.storage.location.buffer.pointer, + key_size); + } else if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(keytype)) { + if ((2 * (offset + key_size)) > sizeof(temp_key_buf)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_curve_point(temp_key_buf, + key_desc.storage.location.buffer.pointer, + key_size); + } else { + return PSA_ERROR_CORRUPTION_DETECTED; + } + key_desc.storage.location.buffer.pointer = temp_key_buf; + key_desc.storage.location.buffer.size = sizeof(temp_key_buf); + } + + // Always pad signature + if ((2 * (offset + key_size)) > sizeof(temp_signature_buffer)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_curve_point(temp_signature_buffer, signature, key_size); + + signature = temp_signature_buffer; + signature_length = signature_length + 2 * offset; + } + #endif // SLI_SE_KEY_PADDING_REQUIRED && SLI_PSA_DRIVER_FEATURE_ECDSA + + // SE manager only accepts public keys for signature verification, + // so we must generate a public key if we are passed a private one + sl_status_t status = SL_STATUS_INVALID_PARAMETER; + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(keytype)) { + #if defined(SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED) + psa_status = sli_se_check_eddsa_errata(attributes, &cmd_ctx); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + #endif // SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED + + // Create similar key descriptor for temporary public key. + sl_se_key_descriptor_t pubkey_desc = key_desc; + pubkey_desc.flags &= ~SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY; + pubkey_desc.flags &= ~SL_SE_KEY_FLAG_IS_RESTRICTED; + pubkey_desc.flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; + sli_se_key_descriptor_set_plaintext(&pubkey_desc, temp_key_buf, sizeof(temp_key_buf)); + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + status = sl_se_export_public_key(&cmd_ctx, &key_desc, &pubkey_desc); + if (status != SL_STATUS_OK) { + if (status == SL_STATUS_COMMAND_IS_INVALID) { + // This error will be returned if the key type isn't supported. + return PSA_ERROR_NOT_SUPPORTED; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Set the key desc to the public key, and move on. + key_desc = pubkey_desc; + } + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Run signature verification + status = sl_se_ecc_verify(&cmd_ctx, + &key_desc, + get_hash_for_algorithm(alg), + false, + input, + input_length, + signature, + signature_length); + + if (status == SL_STATUS_OK) { + psa_status = PSA_SUCCESS; + } else if (status == SL_STATUS_INVALID_SIGNATURE) { + // Signature was invalid. + psa_status = PSA_ERROR_INVALID_SIGNATURE; + } else if (status == SL_STATUS_FAIL) { + // Built-in key does not exist. + psa_status = PSA_ERROR_DOES_NOT_EXIST; + } else if (status == SL_STATUS_COMMAND_IS_INVALID) { + // Key type is not supported. + psa_status = PSA_ERROR_NOT_SUPPORTED; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + + // Cleanup + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_SIGNATURE + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) input; + (void) input_length; + (void) signature; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_SIGNATURE +} + +static psa_status_t sli_se_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || hash == NULL + || hash_length == 0 + || (signature == NULL && signature_length != 0) ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (signature_length == 0) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + // Check the requested algorithm is ECDSA with randomized k + if (!PSA_ALG_IS_RANDOMIZED_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Ephemeral contexts + sl_se_command_context_t cmd_ctx = { 0 }; + sl_se_key_descriptor_t key_desc = { 0 }; + + psa_status_t psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Verify and set key attributes + if (signature_length + != PSA_ECDSA_SIGNATURE_SIZE(psa_get_key_bits(attributes))) { + return PSA_ERROR_INVALID_SIGNATURE; + } + psa_status = check_curve_availability(attributes, alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + uint8_t temp_key_buf[SLI_SE_MAX_PADDED_PUBLIC_KEY_SIZE] = { 0 }; + psa_key_type_t keytype = psa_get_key_type(attributes); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) && defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + // P-521 (or any curve size that's not word-multiple) requires alignment on word + // boundaries, instead of byte boundaries such as PSA Crypto defines as input here. + uint8_t temp_signature_buffer[SLI_SE_MAX_PADDED_SIGNATURE_SIZE] = { 0 }; + size_t key_size = PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + size_t offset = sli_se_get_padding(key_size); + if (offset > 0) { + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); + + // Only pad transparent keys. + if (location == PSA_KEY_LOCATION_LOCAL_STORAGE) { + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(keytype)) { + if (offset + key_size > sizeof(temp_key_buf)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_big_endian(temp_key_buf, + key_desc.storage.location.buffer.pointer, + key_size); + } else if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(keytype)) { + if ((2 * (offset + key_size)) > sizeof(temp_key_buf)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_curve_point(temp_key_buf, + key_desc.storage.location.buffer.pointer, + key_size); + } else { + return PSA_ERROR_CORRUPTION_DETECTED; + } + key_desc.storage.location.buffer.pointer = temp_key_buf; + key_desc.storage.location.buffer.size = sizeof(temp_key_buf); + } + + // Always pad signature + if ((2 * (offset + key_size)) > sizeof(temp_signature_buffer)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + sli_se_pad_curve_point(temp_signature_buffer, signature, key_size); + + signature = temp_signature_buffer; + signature_length = signature_length + 2 * offset; + } + #endif // SLI_SE_KEY_PADDING_REQUIRED && SLI_PSA_DRIVER_FEATURE_ECDSA + + // SE manager only accepts public keys for signature verification, + // so we must generate a public key if we are passed a private one + sl_status_t status = SL_STATUS_INVALID_PARAMETER; + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(keytype)) { + sl_se_key_descriptor_t pubkey_desc = key_desc; + // Unset private key flag and set public + pubkey_desc.flags &= ~SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY; + pubkey_desc.flags &= ~SL_SE_KEY_FLAG_IS_RESTRICTED; + pubkey_desc.flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; + sli_se_key_descriptor_set_plaintext(&pubkey_desc, temp_key_buf, sizeof(temp_key_buf)); + // Same input output region + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + status = sl_se_export_public_key(&cmd_ctx, &key_desc, &pubkey_desc); + if (sl_se_deinit_command_context(&cmd_ctx) != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (status) { + return PSA_ERROR_HARDWARE_FAILURE; + } + // Set the key desc to the public key, and go on + key_desc = pubkey_desc; + } + + status = sl_se_init_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Run signature verification + status = sl_se_ecc_verify(&cmd_ctx, + &key_desc, + SL_SE_HASH_NONE, + true, + hash, + hash_length, + signature, + signature_length); + + if (status == SL_STATUS_OK) { + psa_status = PSA_SUCCESS; + } else if (status == SL_STATUS_INVALID_SIGNATURE) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + } else if (status == SL_STATUS_FAIL) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + } else { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + } + + // Cleanup + status = sl_se_deinit_command_context(&cmd_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_ECDSA + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_ECDSA +} + +// ----------------------------------------------------------------------------- +// Opaque driver entry points + +psa_status_t sli_se_opaque_sign_message(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + return sli_se_sign_message(attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length); +} + +psa_status_t sli_se_opaque_sign_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + return sli_se_sign_hash(attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length); +} + +psa_status_t sli_se_opaque_verify_message(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t * input, + size_t input_length, + const uint8_t * signature, + size_t signature_length) +{ + return sli_se_verify_message(attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length); +} + +psa_status_t sli_se_opaque_verify_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length) +{ + return sli_se_verify_hash(attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length); +} + +// ----------------------------------------------------------------------------- +// Transparent driver entry points + +psa_status_t sli_se_transparent_sign_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + return sli_se_sign_message(attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length); +} + +psa_status_t sli_se_transparent_sign_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + return sli_se_sign_hash(attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length); +} + +psa_status_t sli_se_transparent_verify_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length) +{ + return sli_se_verify_message(attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length); +} + +psa_status_t sli_se_transparent_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length) +{ + return sli_se_verify_hash(attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length); +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_aead.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_aead.c new file mode 100644 index 000000000..db683cc51 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_aead.c @@ -0,0 +1,278 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver AEAD functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +#include "psa/crypto.h" + +#include "sli_se_opaque_types.h" +#include "sli_se_opaque_functions.h" + +#include + +// ----------------------------------------------------------------------------- +// Single-shot driver entry points + +psa_status_t sli_se_opaque_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length) +{ + return sli_se_driver_aead_encrypt(attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + plaintext_length, + ciphertext, + ciphertext_size, + ciphertext_length); +} + +psa_status_t sli_se_opaque_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + return sli_se_driver_aead_decrypt(attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + ciphertext_length, + plaintext, + plaintext_size, + plaintext_length); +} + +// ----------------------------------------------------------------------------- +// Multi-part driver entry points + +psa_status_t sli_se_opaque_aead_encrypt_setup( + sli_se_opaque_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Start by resetting context + memset(operation, 0, sizeof(*operation)); + + // Setup generic context struct + return sli_se_driver_aead_encrypt_decrypt_setup(&(operation->operation), + attributes, + key_buffer, + key_buffer_size, + alg, + SL_SE_ENCRYPT, + operation->key, + sizeof(operation->key), + SLI_SE_WRAPPED_KEY_OVERHEAD); +} + +psa_status_t sli_se_opaque_aead_decrypt_setup( + sli_se_opaque_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Start by resetting context + memset(operation, 0, sizeof(*operation)); + + // Setup generic context struct + return sli_se_driver_aead_encrypt_decrypt_setup(&(operation->operation), + attributes, + key_buffer, + key_buffer_size, + alg, + SL_SE_DECRYPT, + operation->key, + sizeof(operation->key), + SLI_SE_WRAPPED_KEY_OVERHEAD); +} + +psa_status_t sli_se_opaque_aead_set_nonce( + sli_se_opaque_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_size) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_set_nonce(&(operation->operation), + nonce, + nonce_size); +} + +psa_status_t sli_se_opaque_aead_set_lengths( + sli_se_opaque_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_set_lengths(&(operation->operation), + ad_length, + plaintext_length); +} + +psa_status_t sli_se_opaque_aead_update_ad( + sli_se_opaque_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_update_ad(&(operation->operation), + operation->key, + input, + input_length); +} + +psa_status_t sli_se_opaque_aead_update( + sli_se_opaque_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_update(&(operation->operation), + operation->key, + input, + input_length, + output, + output_size, + output_length); +} + +psa_status_t sli_se_opaque_aead_finish( + sli_se_opaque_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_finish(&(operation->operation), + operation->key, + ciphertext, + ciphertext_size, + ciphertext_length, + tag, + tag_size, + tag_length); +} + +psa_status_t sli_se_opaque_aead_verify( + sli_se_opaque_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_verify(&(operation->operation), + operation->key, + plaintext, + plaintext_size, + plaintext_length, + tag, + tag_length); +} + +psa_status_t sli_se_opaque_aead_abort( + sli_se_opaque_aead_operation_t *operation) +{ + // No state is ever left in HW, so zeroing context should do the trick + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + return PSA_SUCCESS; +} + +#endif // SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_cipher.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_cipher.c new file mode 100644 index 000000000..1e7675eca --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_cipher.c @@ -0,0 +1,417 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver Cipher functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +#include "psa/crypto.h" + +#include "sli_se_opaque_types.h" +#include "sli_se_opaque_functions.h" + +#include "sli_se_driver_cipher.h" +#include "sli_se_driver_key_management.h" + +#include "sl_se_manager.h" +#include "sl_se_manager_cipher.h" + +#include + +// ----------------------------------------------------------------------------- +// Static functions + +#if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + +static void update_key_from_context(sli_se_opaque_cipher_operation_t* ctx) +{ + // Point the key to the buffer + ctx->operation.key_desc.storage.location.buffer.pointer = ctx->key; +} + +static psa_status_t initialize_key_in_context( + const psa_key_attributes_t *attributes, + sli_se_opaque_cipher_operation_t *operation, + const uint8_t *key_buffer, + size_t key_buffer_size) +{ + // Double check that the location of the key actually is + // as expected for this driver. + if (PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)) + != PSA_KEY_LOCATION_SLI_SE_OPAQUE) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Initialize the key descriptor. + psa_status_t psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &operation->operation.key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Copy the key material -- could be either a built-in or a wrapped key. + sli_se_opaque_key_context_header_t *key_context_header = + (sli_se_opaque_key_context_header_t *)key_buffer; + if (key_context_header->builtin_key_id != 0) { // Built-in key. + memcpy(operation->key, + key_buffer, + sizeof(sli_se_opaque_key_context_header_t)); + operation->key_len = sizeof(sli_se_opaque_key_context_header_t); + } else { // Wrapped key. + size_t key_size = PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + size_t offset = offsetof(sli_se_opaque_wrapped_key_context_t, wrapped_buffer); + if (key_buffer_size < key_size + sizeof(sli_se_opaque_wrapped_key_context_t)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (sizeof(operation->key) < key_size + SLI_SE_WRAPPED_KEY_OVERHEAD) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, + key_buffer + offset, + key_size + SLI_SE_WRAPPED_KEY_OVERHEAD); + operation->key_len = key_size + SLI_SE_WRAPPED_KEY_OVERHEAD; + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + +// ----------------------------------------------------------------------------- +// Single-shot driver entry points + +psa_status_t sli_se_opaque_cipher_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined (SLI_PSA_DRIVER_FEATURE_CIPHER) + + return sli_se_driver_cipher_encrypt(attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER +} + +psa_status_t sli_se_opaque_cipher_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined (SLI_PSA_DRIVER_FEATURE_CIPHER) + + return sli_se_driver_cipher_decrypt(attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER +} + +// ----------------------------------------------------------------------------- +// Multi-part driver entry points + +psa_status_t sli_se_opaque_cipher_encrypt_setup( + sli_se_opaque_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // Reset context + memset(operation, 0, sizeof(*operation)); + + psa_status_t psa_status = sli_se_driver_cipher_encrypt_setup(&operation->operation, + attributes, + alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Copy key into context + psa_status = initialize_key_in_context(attributes, + operation, + key_buffer, + key_buffer_size); + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_opaque_cipher_decrypt_setup( + sli_se_opaque_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context + memset(operation, 0, sizeof(*operation)); + + psa_status_t psa_status = sli_se_driver_cipher_decrypt_setup(&operation->operation, + attributes, + alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Copy key into context + psa_status = initialize_key_in_context(attributes, + operation, + key_buffer, + key_buffer_size); + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_opaque_cipher_set_iv( + sli_se_opaque_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->key_len == 0) { + // context hasn't been properly initialised + return PSA_ERROR_BAD_STATE; + } + + return sli_se_driver_cipher_set_iv(&operation->operation, iv, iv_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)iv; + (void)iv_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_opaque_cipher_update( + sli_se_opaque_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + // Argument check + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // For wrapped keys, set the key correctly + sli_se_opaque_key_context_header_t *key_context_header = + (sli_se_opaque_key_context_header_t *)operation->key; + if (key_context_header->builtin_key_id == 0) { + update_key_from_context(operation); + } + + // Compute + return sli_se_driver_cipher_update(&operation->operation, + input, + input_length, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_opaque_cipher_finish( + sli_se_opaque_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // For wrapped keys, set the key correctly + sli_se_opaque_key_context_header_t *key_context_header = + (sli_se_opaque_key_context_header_t *)operation->key; + if (key_context_header->builtin_key_id == 0) { + update_key_from_context(operation); + } + + // Compute + return sli_se_driver_cipher_finish(&operation->operation, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_opaque_cipher_abort( + sli_se_opaque_cipher_operation_t *operation) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation != NULL) { + // Wipe context + memset(operation, 0, sizeof(sli_se_opaque_cipher_operation_t)); + } + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +#endif // SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_mac.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_mac.c new file mode 100644 index 000000000..37555326e --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_driver_mac.c @@ -0,0 +1,426 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver Mac functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +#include "psa/crypto.h" + +#include "sli_se_driver_key_management.h" +#include "sli_se_opaque_types.h" +#include "sli_se_opaque_functions.h" +#include "sli_se_manager_internal.h" +#include "sli_psa_driver_common.h" + +#include + +//------------------------------------------------------------------------------ +// Single-shot driver entry points + +psa_status_t sli_se_opaque_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC) + + if (key_buffer == NULL + || attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Ephemeral contexts + sl_se_key_descriptor_t key_desc = { 0 }; + psa_status_t psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + return sli_se_driver_mac_compute(&key_desc, + alg, + input, + input_length, + mac, + mac_size, + mac_length); + + #else // SLI_PSA_DRIVER_FEATURE_MAC + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC +} + +//------------------------------------------------------------------------------ +// Multi-part driver entry points + +psa_status_t sli_se_opaque_mac_sign_setup( + sli_se_opaque_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + if (operation == NULL + || attributes == NULL + || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t psa_status; + + // start by resetting context + memset(operation, 0, sizeof(*operation)); + + // Add support for one-shot HMAC through the multipart interface + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + // SE does not support multipart HMAC. Construct it from hashing instead. + // Check key type and output size + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_HMAC) { + // For HMAC, key type is strictly enforced + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t output_size = 0; + sl_se_hash_type_t hash = sli_se_hash_type_from_psa_hmac_alg(alg, + &output_size); + if (hash == SL_SE_HASH_NONE) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (output_size > sizeof(operation->operation.ctx.hmac.hmac_result)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + operation->operation.alg = alg; + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) \ + && (defined(SLI_PSA_DRIVER_FEATURE_CMAC) \ + || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC)) + else + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + { + psa_status = sli_se_driver_mac_sign_setup(&(operation->operation), + attributes, + alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + } + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + psa_status = sli_se_key_desc_from_input(attributes, + key_buffer, + key_buffer_size, + &(operation->key_desc)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + size_t padding = 0; + operation->key_len = psa_get_key_bits(attributes) / 8; + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + padding = sli_se_get_padding(operation->key_len); + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + if ((operation->key_len < sizeof(uint32_t)) + || ((operation->key_len + padding) + > (sizeof(operation->key) - SLI_SE_WRAPPED_KEY_OVERHEAD))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) \ + && (defined(SLI_PSA_DRIVER_FEATURE_CMAC) \ + || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC)) + else + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + { + switch (operation->key_len) { + case 16: // Fallthrough + case 24: // Fallthrough + case 32: + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + } + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + if (operation->key_desc.storage.location.buffer.size + < (SLI_SE_WRAPPED_KEY_OVERHEAD + operation->key_len + padding)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(operation->key, + operation->key_desc.storage.location.buffer.pointer, + SLI_SE_WRAPPED_KEY_OVERHEAD + operation->key_len + padding); + + // Point key_descriptor at internal copy of key + operation->key_desc.storage.location.buffer.pointer = operation->key; + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif +} + +psa_status_t sli_se_opaque_mac_verify_setup( + sli_se_opaque_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + // Since the PSA Crypto core exposes the verify functionality of the drivers + // without actually implementing the fallback to 'sign' when the driver + // doesn't support verify, we need to do this ourselves for the time being. + return sli_se_opaque_mac_sign_setup(operation, + attributes, + key_buffer, + key_buffer_size, + alg); +} + +psa_status_t sli_se_opaque_mac_update(sli_se_opaque_mac_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(operation->operation.alg)) { + if ( operation->operation.ctx.hmac.hmac_len > 0 ) { + return PSA_ERROR_BAD_STATE; + } + + return sli_se_driver_mac_compute( + &(operation->key_desc), + operation->operation.alg, + input, + input_length, + operation->operation.ctx.hmac.hmac_result, + sizeof(operation->operation.ctx.hmac.hmac_result), + &operation->operation.ctx.hmac.hmac_len); + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + return sli_se_driver_mac_update(&(operation->operation), + &(operation->key_desc), + input, + input_length); + #else + return PSA_ERROR_NOT_SUPPORTED; + #endif + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)input; + (void)input_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +psa_status_t sli_se_opaque_mac_sign_finish( + sli_se_opaque_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + if (operation == NULL + || mac == NULL + || mac_size == 0 + || mac_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(operation->operation.alg)) { + if ( operation->operation.ctx.hmac.hmac_len == 0 ) { + return PSA_ERROR_BAD_STATE; + } + + if ( mac_size < operation->operation.ctx.hmac.hmac_len ) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(mac, + operation->operation.ctx.hmac.hmac_result, + operation->operation.ctx.hmac.hmac_len); + *mac_length = operation->operation.ctx.hmac.hmac_len; + + return PSA_SUCCESS; + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + return sli_se_driver_mac_sign_finish(&(operation->operation), + &(operation->key_desc), + mac, + mac_size, + mac_length); + #else + return PSA_ERROR_NOT_SUPPORTED; + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +psa_status_t sli_se_opaque_mac_verify_finish( + sli_se_opaque_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + // Since the PSA Crypto core exposes the verify functionality of the drivers + // without actually implementing the fallback to 'sign' when the driver + // doesn't support verify, we need to do this ourselves for the time being. + uint8_t calculated_mac[PSA_MAC_MAX_SIZE] = { 0 }; + size_t calculated_length = PSA_MAC_MAX_SIZE; + + psa_status_t status = sli_se_opaque_mac_sign_finish(operation, + calculated_mac, + sizeof(calculated_mac), + &calculated_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (mac_length > sizeof(calculated_mac)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (sli_psa_safer_memcmp(mac, calculated_mac, mac_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + } else { + status = PSA_SUCCESS; + } + + sli_psa_zeroize(calculated_mac, sizeof(calculated_mac)); + + return status; + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)mac; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +psa_status_t sli_se_opaque_mac_abort(sli_se_opaque_mac_operation_t *operation) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + // There's no state in hardware that we need to preserve, so zeroing out the + // context suffices. + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +#endif // SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_key_derivation.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_key_derivation.c new file mode 100644 index 000000000..40773ddac --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_opaque_key_derivation.c @@ -0,0 +1,63 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Opaque Driver Key Derivation functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +#include "psa/crypto.h" + +#include "sli_se_driver_key_derivation.h" + +//------------------------------------------------------------------------------ +// Driver entry points + +psa_status_t sli_se_opaque_key_agreement(psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + return sli_se_driver_key_agreement(alg, + attributes, + key_buffer, + key_buffer_size, + peer_key, + peer_key_length, + output, + output_size, + output_length); +} + +#endif // SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_aead.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_aead.c new file mode 100644 index 000000000..d22e18707 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_aead.c @@ -0,0 +1,279 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver AEAD functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_transparent_types.h" +#include "sli_se_transparent_functions.h" + +#include + +//------------------------------------------------------------------------------ +// One-shot driver entry points + +psa_status_t sli_se_transparent_aead_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length) +{ + return sli_se_driver_aead_encrypt(attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + plaintext_length, + ciphertext, + ciphertext_size, + ciphertext_length); +} + +psa_status_t sli_se_transparent_aead_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + return sli_se_driver_aead_decrypt(attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + ciphertext_length, + plaintext, + plaintext_size, + plaintext_length); +} + +//------------------------------------------------------------------------------ +// Multi-part driver entry points + +psa_status_t sli_se_transparent_aead_encrypt_setup( + sli_se_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Start by resetting context + memset(operation, 0, sizeof(*operation)); + + // Setup generic context struct + return sli_se_driver_aead_encrypt_decrypt_setup(&(operation->operation), + attributes, + key_buffer, + key_buffer_size, + alg, + SL_SE_ENCRYPT, + operation->key, + sizeof(operation->key), + 0); +} + +psa_status_t sli_se_transparent_aead_decrypt_setup( + sli_se_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Start by resetting context + memset(operation, 0, sizeof(*operation)); + + // Setup generic context struct + return sli_se_driver_aead_encrypt_decrypt_setup(&(operation->operation), + attributes, + key_buffer, + key_buffer_size, + alg, + SL_SE_DECRYPT, + operation->key, + sizeof(operation->key), + 0); +} + +psa_status_t sli_se_transparent_aead_set_nonce( + sli_se_transparent_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_size) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_set_nonce(&(operation->operation), + nonce, + nonce_size); +} + +psa_status_t sli_se_transparent_aead_set_lengths( + sli_se_transparent_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_set_lengths(&(operation->operation), + ad_length, + plaintext_length); +} + +psa_status_t sli_se_transparent_aead_update_ad( + sli_se_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + return sli_se_driver_aead_update_ad(&(operation->operation), + operation->key, + input, + input_length); +} + +psa_status_t sli_se_transparent_aead_update( + sli_se_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + return sli_se_driver_aead_update(&(operation->operation), + operation->key, + input, + input_length, + output, + output_size, + output_length); +} + +psa_status_t sli_se_transparent_aead_finish( + sli_se_transparent_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_finish(&(operation->operation), + operation->key, + ciphertext, + ciphertext_size, + ciphertext_length, + tag, + tag_size, + tag_length); +} + +psa_status_t sli_se_transparent_aead_verify( + sli_se_transparent_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length) +{ + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return sli_se_driver_aead_verify(&(operation->operation), + operation->key, + plaintext, + plaintext_size, + plaintext_length, + tag, + tag_length); +} + +psa_status_t sli_se_transparent_aead_abort( + sli_se_transparent_aead_operation_t *operation) +{ + // No state is ever left in HW, so zeroing context should do the trick + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + + return PSA_SUCCESS; +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_cipher.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_cipher.c new file mode 100644 index 000000000..14ec4478d --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_cipher.c @@ -0,0 +1,388 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Cipher functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_transparent_types.h" +#include "sli_se_transparent_functions.h" + +#include "sl_se_manager.h" +#include "sl_se_manager_cipher.h" + +#include "sli_se_driver_cipher.h" +#include "sli_se_driver_key_management.h" + +#include + +// ----------------------------------------------------------------------------- +// Static functions + +#if defined(SLI_PSA_DRIVER_FEATURE_CIPHER) + +static void update_key_from_context( + sli_se_transparent_cipher_operation_t* operation) +{ + // Point to transparent key buffer as storage location + sli_se_key_descriptor_set_plaintext(&operation->operation.key_desc, + operation->key, + sizeof(operation->key)); +} + +static psa_status_t initialize_key_in_context( + const psa_key_attributes_t *attributes, + sli_se_transparent_cipher_operation_t *operation, + const uint8_t *key_buffer, + size_t key_buffer_size) +{ + const size_t key_size = PSA_BITS_TO_BYTES(psa_get_key_bits(attributes)); + psa_status_t psa_status = + sli_se_key_desc_from_psa_attributes(attributes, + key_size, + &operation->operation.key_desc); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (sizeof(operation->key) < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, key_size); + operation->key_len = key_size; + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_CIPHER + +// ----------------------------------------------------------------------------- +// Single-shot driver entry points + +psa_status_t sli_se_transparent_cipher_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER) + + return sli_se_driver_cipher_encrypt(attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER +} + +psa_status_t sli_se_transparent_cipher_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER) + + return sli_se_driver_cipher_decrypt(attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER +} + +// ----------------------------------------------------------------------------- +// Multi-part driver entry points + +psa_status_t sli_se_transparent_cipher_encrypt_setup( + sli_se_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // Reset context + memset(operation, 0, sizeof(*operation)); + + psa_status_t psa_status = + sli_se_driver_cipher_encrypt_setup(&operation->operation, + attributes, + alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Copy key into context + psa_status = initialize_key_in_context(attributes, + operation, + key_buffer, + key_buffer_size); + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_transparent_cipher_decrypt_setup( + sli_se_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context + memset(operation, 0, sizeof(*operation)); + + psa_status_t psa_status = + sli_se_driver_cipher_decrypt_setup(&operation->operation, + attributes, + alg); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + // Copy key into context + psa_status = initialize_key_in_context(attributes, + operation, + key_buffer, + key_buffer_size); + return psa_status; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_transparent_cipher_set_iv( + sli_se_transparent_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->key_len == 0) { + // context hasn't been properly initialised + return PSA_ERROR_BAD_STATE; + } + + return sli_se_driver_cipher_set_iv(&operation->operation, iv, iv_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)iv; + (void)iv_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_transparent_cipher_update( + sli_se_transparent_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + // Argument check + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Set the key correctly + update_key_from_context(operation); + + // Compute + return sli_se_driver_cipher_update(&operation->operation, + input, + input_length, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_transparent_cipher_finish( + sli_se_transparent_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + update_key_from_context(operation); + return sli_se_driver_cipher_finish(&operation->operation, + output, + output_size, + output_length); + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +psa_status_t sli_se_transparent_cipher_abort( + sli_se_transparent_cipher_operation_t *operation) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART) + + if (operation != NULL) { + // Wipe context + memset(operation, 0, sizeof(sli_se_transparent_cipher_operation_t)); + } + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_hash.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_hash.c new file mode 100644 index 000000000..45dad46d9 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_hash.c @@ -0,0 +1,409 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Hash functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_transparent_types.h" +#include "sli_se_transparent_functions.h" + +#include "sl_se_manager.h" +#include "sl_se_manager_hash.h" + +#include + +// ----------------------------------------------------------------------------- +// Single-shot driver entry points + +psa_status_t sli_se_transparent_hash_compute(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_HASH) + + if ((input == NULL && input_length > 0) + || (hash == NULL && hash_size > 0) + || hash_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + sl_se_hash_type_t hash_type; + sl_se_command_context_t ephemeral_se_ctx; + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_SHA1) + case PSA_ALG_SHA_1: + hash_type = SL_SE_HASH_SHA1; + *hash_length = 20; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA224) + case PSA_ALG_SHA_224: + hash_type = SL_SE_HASH_SHA224; + *hash_length = 28; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA256) + case PSA_ALG_SHA_256: + hash_type = SL_SE_HASH_SHA256; + *hash_length = 32; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA384) + case PSA_ALG_SHA_384: + hash_type = SL_SE_HASH_SHA384; + *hash_length = 48; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA512) + case PSA_ALG_SHA_512: + hash_type = SL_SE_HASH_SHA512; + *hash_length = 64; + break; + #endif + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + if (hash_size < *hash_length) { + *hash_length = 0; + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + sl_status_t status = sl_se_init_command_context(&ephemeral_se_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + status = sl_se_hash(&ephemeral_se_ctx, + hash_type, + input, + input_length, + hash, + hash_size); + + if (status == SL_STATUS_OK) { + return PSA_SUCCESS; + } else { + *hash_length = 0; + return PSA_ERROR_HARDWARE_FAILURE; + } + + #else // SLI_PSA_DRIVER_FEATURE_HASH + + (void)alg; + (void)input; + (void)input_length; + (void)hash; + (void)hash_size; + (void)hash_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_HASH +} + +// ----------------------------------------------------------------------------- +// Multi-part driver entry points + +psa_status_t sli_se_transparent_hash_setup( + sli_se_transparent_hash_operation_t *operation, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // reset context + memset(&operation->streaming_contexts, 0, sizeof(operation->streaming_contexts)); + + // create ephemeral contexts + sl_se_command_context_t ephemeral_se_ctx; + sl_status_t status = SL_STATUS_INVALID_PARAMETER; + + switch (alg) { + #if defined(SLI_PSA_DRIVER_FEATURE_SHA1) + case PSA_ALG_SHA_1: + operation->hash_type = SL_SE_HASH_SHA1; + status = sl_se_hash_sha1_multipart_starts(&(operation->streaming_contexts.sha1_context), + &ephemeral_se_ctx); + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA224) + case PSA_ALG_SHA_224: + operation->hash_type = SL_SE_HASH_SHA224; + status = sl_se_hash_sha224_multipart_starts(&(operation->streaming_contexts.sha224_context), + &ephemeral_se_ctx); + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA256) + case PSA_ALG_SHA_256: + operation->hash_type = SL_SE_HASH_SHA256; + status = sl_se_hash_sha256_multipart_starts(&(operation->streaming_contexts.sha256_context), + &ephemeral_se_ctx); + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA384) + case PSA_ALG_SHA_384: + operation->hash_type = SL_SE_HASH_SHA384; + status = sl_se_hash_sha384_multipart_starts(&(operation->streaming_contexts.sha384_context), + &ephemeral_se_ctx); + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA512) + case PSA_ALG_SHA_512: + operation->hash_type = SL_SE_HASH_SHA512; + status = sl_se_hash_sha512_multipart_starts(&(operation->streaming_contexts.sha512_context), + &ephemeral_se_ctx); + break; + #endif + + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + if (status == SL_STATUS_OK) { + return PSA_SUCCESS; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #else // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + + (void) operation; + (void) alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART +} + +psa_status_t sli_se_transparent_hash_update( + sli_se_transparent_hash_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART) + + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // create ephemeral contexts + sl_se_command_context_t ephemeral_se_ctx; + sl_status_t status = sl_se_init_command_context(&ephemeral_se_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + status = sl_se_hash_multipart_update((void*)&(operation->streaming_contexts), + &ephemeral_se_ctx, + input, + input_length); + + if (status == SL_STATUS_OK) { + return PSA_SUCCESS; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #else // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + + (void) operation; + (void) input; + (void) input_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART +} + +psa_status_t sli_se_transparent_hash_finish( + sli_se_transparent_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART) + + if (operation == NULL + || (hash == NULL && hash_size > 0) + || hash_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // create ephemeral contexts + sl_se_command_context_t ephemeral_se_ctx; + sl_status_t status = sl_se_init_command_context(&ephemeral_se_ctx); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + status = sl_se_hash_multipart_finish((void*)&(operation->streaming_contexts), + &ephemeral_se_ctx, + hash, + hash_size); + + // reset context + memset(&operation->streaming_contexts, + 0, + sizeof(operation->streaming_contexts)); + + if (status == SL_STATUS_OK) { + switch (operation->hash_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_SHA1) + case SL_SE_HASH_SHA1: + *hash_length = 20; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA224) + case SL_SE_HASH_SHA224: + *hash_length = 28; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA256) + case SL_SE_HASH_SHA256: + *hash_length = 32; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA384) + case SL_SE_HASH_SHA384: + *hash_length = 48; + break; + #endif + + #if defined(SLI_PSA_DRIVER_FEATURE_SHA512) + case SL_SE_HASH_SHA512: + *hash_length = 64; + break; + #endif + + default: + return PSA_ERROR_BAD_STATE; + } + return PSA_SUCCESS; + } else if ( status == SL_STATUS_INVALID_PARAMETER) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } else { + return PSA_ERROR_HARDWARE_FAILURE; + } + + #else // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + + (void) operation; + (void) hash; + (void) hash_size; + (void) hash_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART +} + +psa_status_t sli_se_transparent_hash_abort( + sli_se_transparent_hash_operation_t *operation) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART) + + if (operation != NULL) { + // Accelerator does not keep state, so just zero out the context and we're good + memset(operation, 0, sizeof(sli_se_transparent_hash_operation_t)); + } + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + + (void) operation; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART +} + +psa_status_t sli_se_transparent_hash_clone( + const sli_se_transparent_hash_operation_t *source_operation, + sli_se_transparent_hash_operation_t *target_operation) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART) + + if (source_operation == NULL + || target_operation == NULL) { + return PSA_ERROR_BAD_STATE; + } + + // Source operation must be active (setup has been called) + if (source_operation->hash_type == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Target operation must be inactive (setup has not been called) + if (target_operation->hash_type != 0) { + return PSA_ERROR_BAD_STATE; + } + + // The operation context does not contain any pointers, and the target + // operation have already have been initialized, so we can do a direct copy. + *target_operation = *source_operation; + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + + (void) source_operation; + (void) target_operation; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_mac.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_mac.c new file mode 100644 index 000000000..1beee7b2e --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_driver_mac.c @@ -0,0 +1,598 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Mac functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_transparent_types.h" +#include "sli_se_transparent_functions.h" +#include "sli_psa_driver_common.h" + +#include + +//------------------------------------------------------------------------------ +// Static asserts + +// Make sure that the two locations of 'alg' are in the same place, since we +// access them interchangeably. +#if defined(SLI_PSA_DRIVER_FEATURE_HMAC) +_Static_assert(offsetof(sli_se_transparent_mac_operation_t, hmac.alg) + == offsetof(sli_se_transparent_mac_operation_t, + cipher_mac.operation.alg), + "hmac.alg and cipher_mac.oepration.alg are not aliases"); +#endif // SLI_PSA_DRIVER_FEATURE_MAC + +//------------------------------------------------------------------------------ +// Static functions + +#if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + +static psa_status_t sli_se_transparent_driver_symmetric_key_from_context( + sl_se_key_descriptor_t* key_desc, + sli_se_transparent_mac_operation_t* operation) +{ + // Point to transparent key buffer as storage location + key_desc->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT; + key_desc->storage.location.buffer.pointer = operation->cipher_mac.key; + key_desc->storage.location.buffer.size = sizeof(operation->cipher_mac.key); + key_desc->size = operation->cipher_mac.key_len; + + switch (PSA_ALG_FULL_LENGTH_MAC(operation->cipher_mac.operation.alg)) { + case PSA_ALG_CBC_MAC: + case PSA_ALG_CMAC: + if (key_desc->size == 16) { + key_desc->type = SL_SE_KEY_TYPE_AES_128; + } else if (key_desc->size == 24) { + key_desc->type = SL_SE_KEY_TYPE_AES_192; + } else if (key_desc->size == 32) { + key_desc->type = SL_SE_KEY_TYPE_AES_256; + } else { + return PSA_ERROR_BAD_STATE; + } + break; + default: + return PSA_ERROR_BAD_STATE; + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + +#if defined(SLI_PSA_DRIVER_FEATURE_MAC) + +static psa_status_t sli_se_transparent_driver_symmetric_key_from_psa( + sl_se_key_descriptor_t* key_desc, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size) +{ + // Point to transparent key buffer as storage location + key_desc->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT; + key_desc->storage.location.buffer.pointer = (uint8_t *)key_buffer; + key_desc->storage.location.buffer.size = key_buffer_size; + + // Verify and set key attributes + psa_key_type_t keytype = psa_get_key_type(attributes); + + switch (keytype) { + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + case PSA_KEY_TYPE_AES: { + switch (psa_get_key_bits(attributes)) { + case 128: + key_desc->size = 16; + key_desc->type = SL_SE_KEY_TYPE_AES_128; + break; + case 192: + key_desc->size = 24; + key_desc->type = SL_SE_KEY_TYPE_AES_192; + break; + case 256: + key_desc->size = 32; + key_desc->type = SL_SE_KEY_TYPE_AES_256; + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + case PSA_KEY_TYPE_HMAC: { + key_desc->size = psa_get_key_bits(attributes) / 8; + key_desc->type = SL_SE_KEY_TYPE_SYMMETRIC; + break; + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + default: + return PSA_ERROR_INVALID_ARGUMENT; + break; + } + + if (key_buffer_size < key_desc->size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_MAC + +//------------------------------------------------------------------------------ +// Single-shot driver entry points + +psa_status_t sli_se_transparent_mac_compute( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC) + + if (key_buffer == NULL + || attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Ephemeral contexts + sl_se_key_descriptor_t key_desc = { 0 }; + psa_status_t psa_status + = sli_se_transparent_driver_symmetric_key_from_psa(&key_desc, + attributes, + key_buffer, + key_buffer_size); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + return sli_se_driver_mac_compute(&key_desc, + alg, + input, + input_length, + mac, + mac_size, + mac_length); + + #else // SLI_PSA_DRIVER_FEATURE_MAC + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC +} + +//------------------------------------------------------------------------------ +// Multi-part driver entry points + +psa_status_t sli_se_transparent_mac_sign_setup( + sli_se_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + if (operation == NULL + || attributes == NULL + || (key_buffer == NULL && key_buffer_size > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + + // start by resetting context + memset(operation, 0, sizeof(*operation)); + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + // SE does not support multipart HMAC. Construct it from hashing instead. + // Check key type and output size + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_HMAC) { + // For HMAC, key type is strictly enforced + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH(alg); + size_t digest_len = PSA_HASH_LENGTH(hash_alg); + + if (PSA_MAC_TRUNCATED_LENGTH(alg) > digest_len) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Setup the hash accumulator first, such that we can return early for non- + // supported hash functions and avoid potentially overflowing buffer lengths. + status = sli_se_transparent_hash_setup(&operation->hmac.hash_ctx, + hash_alg); + if (status != PSA_SUCCESS) { + return status; + } + + size_t keylen = psa_get_key_bits(attributes) / 8; + size_t blocklen + = (hash_alg == PSA_ALG_SHA_384 || hash_alg == PSA_ALG_SHA_512) ? 128 : 64; + + if (key_buffer_size < keylen) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reduce the key if larger than a block + if (keylen > blocklen) { + status = sli_se_transparent_hash_compute( + hash_alg, + key_buffer, + keylen, + operation->hmac.opad, + sizeof(operation->hmac.opad), + &keylen); + if (status != PSA_SUCCESS) { + return status; + } + } else if (keylen > 0) { + memcpy(operation->hmac.opad, key_buffer, keylen); + } + + // Calculate inner padding in opad buffer and start a multipart hash with it + for (size_t i = 0; i < keylen; i++) { + operation->hmac.opad[i] ^= 0x36; + } + memset(&operation->hmac.opad[keylen], 0x36, blocklen - keylen); + + status = sli_se_transparent_hash_update( + &operation->hmac.hash_ctx, + operation->hmac.opad, blocklen); + if (status != PSA_SUCCESS) { + return status; + } + + // Calculate outer padding and store it for finalisation + for (size_t i = 0; i < blocklen; i++) { + operation->hmac.opad[i] ^= 0x36 ^ 0x5C; + } + + operation->hmac.alg = alg; + return PSA_SUCCESS; + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + status = sli_se_driver_mac_sign_setup(&(operation->cipher_mac.operation), + attributes, + alg); + if (status != PSA_SUCCESS) { + return status; + } + + operation->cipher_mac.key_len = psa_get_key_bits(attributes) / 8; + switch (operation->cipher_mac.key_len) { + case 16: + if (key_buffer_size < 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->cipher_mac.key, key_buffer, 16); + break; + case 24: + if (key_buffer_size < 24) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->cipher_mac.key, key_buffer, 24); + break; + case 32: + if (key_buffer_size < 32) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->cipher_mac.key, key_buffer, 32); + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; + #else // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + return PSA_ERROR_NOT_SUPPORTED; + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +psa_status_t sli_se_transparent_mac_verify_setup( + sli_se_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + // Since the PSA Crypto core exposes the verify functionality of the drivers + // without actually implementing the fallback to 'sign' when the driver + // doesn't support verify, we need to do this ourselves for the time being. + return sli_se_transparent_mac_sign_setup(operation, + attributes, + key_buffer, + key_buffer_size, + alg); +} + +psa_status_t sli_se_transparent_mac_update( + sli_se_transparent_mac_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { + return sli_se_transparent_hash_update( + &operation->hmac.hash_ctx, + input, + input_length); + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + // Ephemeral contexts + sl_se_key_descriptor_t key_desc = { 0 }; + + psa_status_t psa_status + = sli_se_transparent_driver_symmetric_key_from_context(&key_desc, + operation); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + return sli_se_driver_mac_update(&(operation->cipher_mac.operation), + &key_desc, + input, + input_length); + #else // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + return PSA_ERROR_NOT_SUPPORTED; + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)input; + (void)input_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +psa_status_t sli_se_transparent_mac_sign_finish( + sli_se_transparent_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + if (operation == NULL + || mac == NULL + || mac_size == 0 + || mac_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + #if defined(SLI_PSA_DRIVER_FEATURE_HMAC) + if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { + uint8_t buffer[sizeof(operation->hmac.opad) + + (sizeof(operation->hmac.opad) / 2)]; + size_t olen = 0; + psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH(operation->hmac.alg); + + #if !defined(SLI_PSA_DRIVER_FEATURE_HASH_STATE_64) + if (hash_alg == PSA_ALG_SHA_384 || hash_alg == PSA_ALG_SHA_512) { + // Could only reach here if the programmer has made some errors. Take the + // safe approach of checking just in case, in order to avoid certain + // buffer overflows. + return PSA_ERROR_BAD_STATE; + } + size_t blocklen = 64; + #else + size_t blocklen + = (hash_alg == PSA_ALG_SHA_384 || hash_alg == PSA_ALG_SHA_512) ? 128 : 64; + #endif + + // Construct outer hash input from opad and hash result + memcpy(buffer, operation->hmac.opad, blocklen); + memset(operation->hmac.opad, 0, sizeof(operation->hmac.opad)); + + psa_status_t status = sli_se_transparent_hash_finish( + &operation->hmac.hash_ctx, + &buffer[blocklen], + sizeof(buffer) - blocklen, + &olen); + if (status != PSA_SUCCESS) { + return status; + } + + // Calculate HMAC + status = sli_se_transparent_hash_compute( + hash_alg, + buffer, + blocklen + olen, + buffer, + sizeof(buffer), + &olen); + if (status != PSA_SUCCESS) { + return status; + } + + // Copy out a potentially truncated HMAC + size_t requested_length = PSA_MAC_TRUNCATED_LENGTH(operation->hmac.alg); + if (requested_length == 0) { + requested_length = olen; + } + + if (requested_length > mac_size) { + memset(buffer, 0, sizeof(buffer)); + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(mac, buffer, requested_length); + *mac_length = requested_length; + memset(buffer, 0, sizeof(buffer)); + return PSA_SUCCESS; + } + #endif // SLI_PSA_DRIVER_FEATURE_HMAC + + #if defined(SLI_PSA_DRIVER_FEATURE_CMAC) || defined(SLI_PSA_DRIVER_FEATURE_CBC_MAC) + // Ephemeral contexts + sl_se_key_descriptor_t key_desc = { 0 }; + + psa_status_t status = sli_se_transparent_driver_symmetric_key_from_context( + &key_desc, + operation); + if (status != PSA_SUCCESS) { + return status; + } + + return sli_se_driver_mac_sign_finish(&(operation->cipher_mac.operation), + &key_desc, + mac, + mac_size, + mac_length); + #else // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + return PSA_ERROR_NOT_SUPPORTED; + #endif // SLI_PSA_DRIVER_FEATURE_CMAC || SLI_PSA_DRIVER_FEATURE_CBC_MAC + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +psa_status_t sli_se_transparent_mac_verify_finish( + sli_se_transparent_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + // Since the PSA Crypto core exposes the verify functionality of the drivers + // without actually implementing the fallback to 'sign' when the driver + // doesn't support verify, we need to do this ourselves for the time being. + uint8_t calculated_mac[PSA_MAC_MAX_SIZE] = { 0 }; + size_t calculated_length = PSA_MAC_MAX_SIZE; + + psa_status_t status = sli_se_transparent_mac_sign_finish( + operation, + calculated_mac, sizeof(calculated_mac), &calculated_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (mac_length > sizeof(calculated_mac)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (sli_psa_safer_memcmp(mac, calculated_mac, mac_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + } else { + status = PSA_SUCCESS; + } + + memset(calculated_mac, 0, sizeof(calculated_mac)); + return status; + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + (void)mac; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +psa_status_t sli_se_transparent_mac_abort( + sli_se_transparent_mac_operation_t *operation) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART) + + // There's no state in hardware that we need to preserve, so zeroing out the + // context suffices. + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + + return PSA_SUCCESS; + + #else // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + #endif // SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_key_derivation.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_key_derivation.c new file mode 100644 index 000000000..8c04078a5 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_transparent_key_derivation.c @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Key derivation functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_driver_key_derivation.h" + +//------------------------------------------------------------------------------ +// Driver entry points + +psa_status_t sli_se_transparent_key_agreement( + psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + return sli_se_driver_key_agreement(alg, + attributes, + key_buffer, + key_buffer_size, + peer_key, + peer_key_length, + output, + output_size, + output_length); +} + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c new file mode 100644 index 000000000..4713902e3 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c @@ -0,0 +1,72 @@ +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver SE Version Dependencies. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_version_dependencies.h" +#include "sli_se_driver_key_management.h" + +#include "sl_se_manager_util.h" + +// ----------------------------------------------------------------------------- +// Global functions + +#if defined(SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED) + +// Check for an errata causing the SE to emit a faulty EdDSA public key for +// operations where only a private key is provided. Assumes that an already +// initalized SE command context is passed as input. +psa_status_t sli_se_check_eddsa_errata(const psa_key_attributes_t* attributes, + sl_se_command_context_t* cmd_ctx) +{ + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(attributes)) + == PSA_ECC_FAMILY_TWISTED_EDWARDS) { + uint32_t se_version = 0; + sl_status_t status = sl_se_get_se_version(cmd_ctx, &se_version); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + se_version = SLI_VERSION_REMOVE_DIE_ID(se_version); + + if (SLI_SE_VERSION_ED25519_BROKEN(se_version)) { + return PSA_ERROR_NOT_SUPPORTED; + } + } + + return PSA_SUCCESS; +} + +#endif // SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/simplicity_sdk/platform/security/sl_component/sli_crypto/inc/sli_crypto.h b/simplicity_sdk/platform/security/sl_component/sli_crypto/inc/sli_crypto.h new file mode 100644 index 000000000..f948449fc --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sli_crypto/inc/sli_crypto.h @@ -0,0 +1,206 @@ +/***************************************************************************//** + * @file + * @brief Provides hardware accelerated cryptographic primitives. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_CRYPTO_H +#define SLI_CRYPTO_H + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) + #include "sli_crypto_s2.h" +#elif defined(_SILICON_LABS_32B_SERIES_3) + #include "sli_crypto_s3.h" +#elif + #error Unsupported device. +#endif +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @brief CCM buffer authenticated decryption optimized for BLE + * + * @param key_descriptor AES key descriptor + * @param data Input/output buffer of payload data of BLE packet + * @param length length of input data + * @param iv nonce (initialization vector) + * must be 13 bytes + * @param header header of BLE packet (1 byte) + * @param tag authentication tag of BLE packet (4 bytes) + * + * @return SL_STATUS_OK if successful and authenticated, + * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, + * relevant status code on other error + ******************************************************************************/ +sl_status_t sli_crypto_ccm_auth_decrypt_ble(sli_crypto_descriptor_t *key_descriptor, + unsigned char *data, + size_t length, + const unsigned char *iv, + unsigned char header, + unsigned char *tag); + +/***************************************************************************//** + * @brief CCM buffer encryption optimized for BLE + * + * @param key_descriptor AES key descriptor + * @param data Input/output buffer of payload data of BLE packet + * @param length length of input data + * @param iv nonce (initialization vector) + * must be 13 bytes + * @param header header of BLE packet (1 byte) + * @param tag buffer where the BLE packet tag (4 bytes) will be written + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_crypto_ccm_encrypt_and_tag_ble(sli_crypto_descriptor_t *key_descriptor, + unsigned char *data, + size_t length, + const unsigned char *iv, + unsigned char header, + unsigned char *tag); + +/***************************************************************************//** + * @brief CCM buffer authenticated decryption optimized for Zigbee + * + * @param key_descriptor AES key descriptor + * @param encrypt Encrypt operation + * @param data_in Input buffer of payload data (decrypt-in-place) + * @param data_out output buffer of payload data (decrypt-in-place) + * @param length length of input data + * @param iv nonce (initialization vector) + * must be 13 bytes + * @param aad Input buffer of Additional Authenticated Data + * @param aad_len Length of buffer aad + * @param tag authentication tag + * @param tag_len Length of authentication tag + * + * @return SL_STATUS_OK if successful and authenticated, + * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, + * relevant status code on other error + ******************************************************************************/ +sl_status_t sli_crypto_ccm_zigbee(sli_crypto_descriptor_t *key_descriptor, + bool encrypt, + const unsigned char *data_in, + unsigned char *data_out, + size_t length, + const unsigned char *iv, + const unsigned char *aad, + size_t aad_len, + unsigned char *tag, + size_t tag_len); + +/***************************************************************************//** + * @brief Process a table of BLE RPA device keys and look for a + * match against the supplied hash + * + * @param key_descriptor SLI crypto descriptor. If plaintext keys are used the + * descriptor provides a pointer to an array of AES-128 keys. + * If KSU stored keys are used, the descriptor provides the + * starting key slot ID of the KSU RAM where the IRK list is + * located + * @param irk_len Number of IRK to be resolved for the RPA operation + * @param keymask Bitmask indicating with key indices in key table are valid + * @param prand 24-bit BLE nonce to encrypt with each key and match against + * hash + * @param hash BLE RPA hash to match against (last 24 bits of AES result) + * @param irk_index 0-based index of matching key if a match is found, + * -1 for no match or error + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_crypto_process_rpa(sli_crypto_descriptor_t *key_descriptor, + size_t irk_len, + uint64_t keymask, + uint32_t prand, + uint32_t hash, + int *irk_index); + +/***************************************************************************//** + * @brief AES-CTR block encryption/decryption optimized for radio + * + * @param key_descriptor AES key descriptor + * @param keybits must be 128 or 256 + * @param input 16-byte input block + * @param iv_in 16-byte counter/IV starting value + * @param iv_out 16-byte counter/IV output after block round + * @param output 16-byte output block + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_crypto_aes_ctr_radio(sli_crypto_descriptor_t *key_descriptor, + unsigned int keybits, + const unsigned char input[SLI_CRYPTO_AES_BLOCK_SIZE], + const unsigned char iv_in[SLI_CRYPTO_AES_BLOCK_SIZE], + volatile unsigned char iv_out[SLI_CRYPTO_AES_BLOCK_SIZE], + volatile unsigned char output[SLI_CRYPTO_AES_BLOCK_SIZE]); + +/***************************************************************************//** + * @brief AES-ECB block encryption/decryption optimized for radio + * + * @param encrypt true for encryption, false for decryption + * @param key_descriptor AES key descriptor + * @param keybits must be 128 or 256 + * @param input 16-byte input block + * @param output 16-byte output block + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_crypto_aes_ecb_radio(bool encrypt, + sli_crypto_descriptor_t *key_descriptor, + unsigned int keybits, + const unsigned char input[SLI_CRYPTO_AES_BLOCK_SIZE], + volatile unsigned char output[SLI_CRYPTO_AES_BLOCK_SIZE]); + +/***************************************************************************//** + * @brief AES-CMAC calculation optimized for radio + * + * @param key_descriptor AES key descriptor + * @param keybits Must be 128 or 256 + * @param input Input buffer containing the message to be signed + * @param length Amount of bytes in the input buffer + * @param output 16-byte output block for calculated CMAC + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_crypto_aes_cmac_radio(sli_crypto_descriptor_t *key_descriptor, + unsigned int keybits, + const unsigned char *input, + unsigned int length, + volatile unsigned char output[SLI_CRYPTO_AES_BLOCK_SIZE]); +// #endif + +#ifdef __cplusplus +} +#endif + +#endif // SLI_CRYPTO_H diff --git a/simplicity_sdk/platform/security/sl_component/sli_crypto/inc/sli_crypto_s2.h b/simplicity_sdk/platform/security/sl_component/sli_crypto/inc/sli_crypto_s2.h new file mode 100644 index 000000000..79a2431e1 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sli_crypto/inc/sli_crypto_s2.h @@ -0,0 +1,83 @@ +/***************************************************************************//** + * @file + * @brief Hardware accelerated cryptographic defintions specific to series-2 + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_CRYPTO_S2_H +#define SLI_CRYPTO_S2_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// Standard buffer size in bytes +#define SLI_CRYPTO_AES_BLOCK_SIZE 16 +/// Location value for keys stored in plaintext +#define SLI_CRYPTO_KEY_LOCATION_PLAINTEXT ((sli_crypto_key_location_t)0x00000000UL) +/// The SLI Crypto API supports only the RADIOAES crypto engine on Series-2 +#define SLI_CRYPTO_ENGINE_RADIOAES ((sli_crypto_engine_t)0x00000001UL) +#define SLI_CRYPTO_ENGINE_DEFAULT (SLI_CRYPTO_ENGINE_RADIOAES) + +/// Used to choose a crypto engine. +/// @ref SLI_CRYPTO_LPWAES. +typedef uint32_t sli_crypto_engine_t; + +/// Key storage location. Can either +/// @ref SLI_CRYPTO_KEY_LOCATION_PLAINTEXT +typedef uint32_t sli_crypto_key_location_t; + +/// Describes where the plaintext key is stored +typedef struct { + uint8_t* pointer; ///< Pointer to a key buffer. + uint32_t size; ///< Size of buffer. +} sli_crypto_key_buffer_t; + +/// Describes the plaintext key +typedef struct { + sli_crypto_key_buffer_t buffer; ///< Key buffer. + uint32_t key_size; ///< Key size. +} sli_crypto_plaintext_key_t; + +typedef struct { + /// Key storage location. + sli_crypto_key_location_t location; + /// Crypto engine. + sli_crypto_engine_t engine; + /// Describes key storage location. + union { + sli_crypto_plaintext_key_t plaintext_key; + } key; +} sli_crypto_descriptor_t; + +#ifdef __cplusplus +} +#endif + +#endif // SLI_CRYPTO_S2_H diff --git a/simplicity_sdk/platform/security/sl_component/sli_crypto/src/sl_crypto_s2.c b/simplicity_sdk/platform/security/sl_component/sli_crypto/src/sl_crypto_s2.c new file mode 100644 index 000000000..aeef1df65 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sli_crypto/src/sl_crypto_s2.c @@ -0,0 +1,220 @@ +/***************************************************************************//** + * @file + * @brief Provides hardware accelerated cryptographic primitives for series-2. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" +#include "sli_crypto.h" +#include "sl_assert.h" +#include "sli_protocol_crypto.h" + +/***************************************************************************//** + * @brief CCM buffer authenticated decryption optimized for BLE + ******************************************************************************/ +sl_status_t sli_crypto_ccm_auth_decrypt_ble(sli_crypto_descriptor_t *key_descriptor, + unsigned char *data, + size_t length, + const unsigned char *iv, + unsigned char header, + unsigned char *tag) +{ + EFM_ASSERT(key_descriptor != NULL); + EFM_ASSERT(data != NULL); + EFM_ASSERT(iv != NULL); + EFM_ASSERT(tag != NULL); + EFM_ASSERT(key_descriptor->location == SLI_CRYPTO_KEY_LOCATION_PLAINTEXT); + EFM_ASSERT(key_descriptor->key.plaintext_key.buffer.pointer != NULL); + + return sli_ccm_auth_decrypt_ble(data, + length, + (const unsigned char *)key_descriptor->key.plaintext_key.buffer.pointer, + iv, + header, + tag); +} + +/***************************************************************************//** + * @brief CCM buffer encryption optimized for BLE + ******************************************************************************/ +sl_status_t sli_crypto_ccm_encrypt_and_tag_ble(sli_crypto_descriptor_t *key_descriptor, + unsigned char *data, + size_t length, + const unsigned char *iv, + unsigned char header, + unsigned char *tag) +{ + EFM_ASSERT(key_descriptor != NULL); + EFM_ASSERT(data != NULL); + EFM_ASSERT(iv != NULL); + EFM_ASSERT(tag != NULL); + EFM_ASSERT(key_descriptor->location == SLI_CRYPTO_KEY_LOCATION_PLAINTEXT); + EFM_ASSERT(key_descriptor->key.plaintext_key.buffer.pointer != NULL); + + return sli_ccm_encrypt_and_tag_ble(data, + length, + (const unsigned char *)key_descriptor->key.plaintext_key.buffer.pointer, + iv, + header, + tag); +} + +/***************************************************************************//** + * @brief CCM buffer authenticated decryption optimized for Zigbee + ******************************************************************************/ +sl_status_t sli_crypto_ccm_zigbee(sli_crypto_descriptor_t *key_descriptor, + bool encrypt, + const unsigned char *data_in, + unsigned char *data_out, + size_t length, + const unsigned char *iv, + const unsigned char *aad, + size_t aad_len, + unsigned char *tag, + size_t tag_len) +{ + EFM_ASSERT(key_descriptor != NULL); + EFM_ASSERT(data_in != NULL); + EFM_ASSERT(iv != NULL); + EFM_ASSERT(key_descriptor->location == SLI_CRYPTO_KEY_LOCATION_PLAINTEXT); + EFM_ASSERT(key_descriptor->key.plaintext_key.buffer.pointer != NULL); + + return sli_ccm_zigbee(encrypt, + data_in, + data_out, + length, + (const unsigned char *)key_descriptor->key.plaintext_key.buffer.pointer, + iv, + aad, + aad_len, + tag, + tag_len); +} + +/***************************************************************************//** + * @brief Process a table of BLE RPA device keys and look for a + * match against the supplied hash + ******************************************************************************/ +sl_status_t sli_crypto_process_rpa(sli_crypto_descriptor_t *key_descriptor, + size_t irk_len, + uint64_t keymask, + uint32_t prand, + uint32_t hash, + int *irk_index) +{ + EFM_ASSERT(key_descriptor != NULL); + EFM_ASSERT(irk_index != NULL); + EFM_ASSERT(key_descriptor->location == SLI_CRYPTO_KEY_LOCATION_PLAINTEXT); + EFM_ASSERT(key_descriptor->key.plaintext_key.buffer.pointer != NULL); + (void)irk_len; + const unsigned char *keytable + = (const unsigned char *)key_descriptor->key.plaintext_key.buffer.pointer; + *irk_index = sli_process_ble_rpa(keytable, + (uint32_t)keymask, + prand, + hash); + if (*irk_index == -1) { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +// /***************************************************************************//** +// * @brief AES-CTR block encryption/decryption optimized for radio +// *******************************************************************************/ +sl_status_t sli_crypto_aes_ctr_radio(sli_crypto_descriptor_t *key_descriptor, + unsigned int keybits, + const unsigned char input[SLI_CRYPTO_AES_BLOCK_SIZE], + const unsigned char iv_in[SLI_CRYPTO_AES_BLOCK_SIZE], + volatile unsigned char iv_out[SLI_CRYPTO_AES_BLOCK_SIZE], + volatile unsigned char output[SLI_CRYPTO_AES_BLOCK_SIZE]) +{ + EFM_ASSERT(key_descriptor != NULL); + EFM_ASSERT(keybits == 128 || keybits == 192 || keybits == 256); + EFM_ASSERT(input != NULL); + EFM_ASSERT(iv_in != NULL); + EFM_ASSERT(output != NULL); + EFM_ASSERT(key_descriptor->location == SLI_CRYPTO_KEY_LOCATION_PLAINTEXT); + EFM_ASSERT(key_descriptor->key.plaintext_key.key_size == keybits / 8); + EFM_ASSERT(key_descriptor->key.plaintext_key.buffer.pointer != NULL); + + return sli_aes_crypt_ctr_radio( (const unsigned char *)key_descriptor->key.plaintext_key.buffer.pointer, + keybits, + input, + iv_in, + iv_out, + output); +} + +/***************************************************************************//** + * @brief AES-ECB block encryption/decryption optimized for radio + ********************************************************************************/ +sl_status_t sli_crypto_aes_ecb_radio(bool encrypt, + sli_crypto_descriptor_t *key_descriptor, + unsigned int keybits, + const unsigned char input[SLI_CRYPTO_AES_BLOCK_SIZE], + volatile unsigned char output[SLI_CRYPTO_AES_BLOCK_SIZE]) +{ + EFM_ASSERT(key_descriptor != NULL); + EFM_ASSERT(keybits == 128 || keybits == 192 || keybits == 256); + EFM_ASSERT(input != NULL); + EFM_ASSERT(output != NULL); + EFM_ASSERT(key_descriptor->location == SLI_CRYPTO_KEY_LOCATION_PLAINTEXT); + EFM_ASSERT(key_descriptor->key.plaintext_key.key_size == keybits / 8); + EFM_ASSERT(key_descriptor->key.plaintext_key.buffer.pointer != NULL); + + return sli_aes_crypt_ecb_radio(encrypt, + (const unsigned char *)key_descriptor->key.plaintext_key.buffer.pointer, + keybits, + input, + output); +} + +/***************************************************************************//** + * @brief AES-CMAC calculation optimized for radio + ********************************************************************************/ +sl_status_t sli_crypto_aes_cmac_radio(sli_crypto_descriptor_t *key_descriptor, + unsigned int keybits, + const unsigned char *input, + unsigned int length, + volatile unsigned char output[SLI_CRYPTO_AES_BLOCK_SIZE]) +{ + EFM_ASSERT(key_descriptor != NULL); + EFM_ASSERT(keybits == 128 || keybits == 192 || keybits == 256); + EFM_ASSERT(input != NULL); + EFM_ASSERT(length == SLI_CRYPTO_AES_BLOCK_SIZE); + EFM_ASSERT(output != NULL); + EFM_ASSERT(key_descriptor->location == SLI_CRYPTO_KEY_LOCATION_PLAINTEXT); + EFM_ASSERT(key_descriptor->key.plaintext_key.key_size == keybits / 8); + EFM_ASSERT(key_descriptor->key.plaintext_key.buffer.pointer != NULL); + + return sli_aes_cmac_radio((const unsigned char *)key_descriptor->key.plaintext_key.buffer.pointer, + keybits, + input, + length, + output); +} diff --git a/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal.h b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal.h new file mode 100644 index 000000000..1f2faf478 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal.h @@ -0,0 +1,57 @@ +/**************************************************************************/ /** + * @file + * @brief OS abstraction layer primitives for the platform/security components. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSEC_OSAL_H +#define SLI_PSEC_OSAL_H + +// ----------------------------------------------------------------------------- +// Includes + +#if defined(SLI_PSEC_CONFIG_FILE) + #include SLI_PSEC_CONFIG_FILE +#endif + +#if defined (SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +#if defined(__ZEPHYR__) + #include "sli_psec_osal_zephyr.h" + #define SLI_PSEC_THREADING +#elif defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) +// Include CMSIS RTOS2 kernel abstraction layer: + #include "sli_psec_osal_cmsis_rtos2.h" + #define SLI_PSEC_THREADING +#else +// Include bare metal abstraction layer: + #include "sli_psec_osal_baremetal.h" +#endif + +#endif // SLI_PSEC_OSAL_H diff --git a/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_baremetal.h b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_baremetal.h new file mode 100644 index 000000000..fef28f8a5 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_baremetal.h @@ -0,0 +1,166 @@ +/**************************************************************************/ /** + * @file + * @brief OS abstraction primitives for the platform/security components + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSEC_OSAL_BAREMETAL_H +#define SLI_PSEC_OSAL_BAREMETAL_H + +// ----------------------------------------------------------------------------- +// Includes +#include "sl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Defines + +/// In order to wait forever in blocking functions the user can pass the +/// following value. +#define SLI_PSEC_OSAL_WAIT_FOREVER (-1) +/// In order to return immediately in blocking functions the user can pass the +/// following value. +#define SLI_PSEC_OSAL_NON_BLOCKING (0) + +// ----------------------------------------------------------------------------- +// Typedefs + +/// Completion type used to wait for and signal end of operation. +typedef volatile unsigned int sli_psec_osal_completion_t; + +/// SLI PSEC lock definition for Baremetal. +typedef volatile unsigned int sli_psec_osal_lock_t; + +// ----------------------------------------------------------------------------- +// Globals + +#if defined(SLI_PSEC_OSAL_TEST) +/// Global variable to keep track of ticks in bare metal test apps. +extern unsigned int sli_sli_psec_test_ticks; +#endif + +// ----------------------------------------------------------------------------- +// Functions + +/***************************************************************************//** + * @brief Initialize a completion object. + * + * @param p_comp Pointer to an sli_psec_osal_completion_t object allocated + * by the user. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE +sl_status_t sli_psec_osal_init_completion(sli_psec_osal_completion_t *p_comp) +{ + *p_comp = 0; + return SL_STATUS_OK; +} + +/***************************************************************************//** + * @brief Free a completion object. + * + * @param p_comp Pointer to an sli_psec_osal_completion_t object. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE +sl_status_t sli_psec_osal_free_completion(sli_psec_osal_completion_t *p_comp) +{ + *p_comp = 0; + return SL_STATUS_OK; +} + +/***************************************************************************//** + * @brief Wait for completion event. + * + * @param p_comp Pointer to completion object which must be initialized by + * calling sli_psec_osal_completion_init before calling this + * function. + * + * @param ticks Ticks to wait for the completion. + * Pass a value of SLI_PSEC_OSAL_WAIT_FOREVER in order to + * wait forever. + * Pass a value of SLI_PSEC_OSAL_NON_BLOCKING in order to + * return immediately. + * + * @return Status code, @ref sl_status.h. Typcally SL_STATUS_OK if success, + * or SL_STATUS_TIMEOUT if no completion within the given ticks. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +sli_psec_osal_wait_completion(sli_psec_osal_completion_t *p_comp, int ticks) +{ + int ret = SL_STATUS_TIMEOUT; + + if (ticks == SLI_PSEC_OSAL_WAIT_FOREVER) { + while ( *p_comp == 0 ) { +#if defined(SLI_PSEC_OSAL_TEST) + sli_sli_psec_test_ticks++; +#endif + } + *p_comp = 0; + ret = SL_STATUS_OK; + } else { + while ((*p_comp == 0) && (ticks > 0)) { + ticks--; +#if defined(SLI_PSEC_OSAL_TEST) + sli_sli_psec_test_ticks++; +#endif + } + if (*p_comp == 1) { + *p_comp = 0; + ret = SL_STATUS_OK; + } + } + + return ret; +} + +/***************************************************************************//** + * @brief Signal completion. + * + * @param p_comp Pointer to completion object which must be initialized by + * calling sli_psec_osal_completion_init before calling this + * function. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE +sl_status_t sli_psec_osal_complete(sli_psec_osal_completion_t* p_comp) +{ + *p_comp = 1; + return SL_STATUS_OK; +} + +#ifdef __cplusplus +} +#endif + +#endif // SLI_PSEC_OSAL_BAREMETAL_H diff --git a/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_cmsis_rtos2.h b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_cmsis_rtos2.h new file mode 100644 index 000000000..6c388aab2 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/inc/sli_psec_osal_cmsis_rtos2.h @@ -0,0 +1,358 @@ +/**************************************************************************/ /** + * @file + * @brief OS abstraction layer primitives for platform/security on CMSIS RTOS2 + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSEC_OSAL_CMSIS_RTOS_H +#define SLI_PSEC_OSAL_CMSIS_RTOS_H + +// ----------------------------------------------------------------------------- +// Includes +#include "sl_common.h" +#include "sl_status.h" +#include "cmsis_os2.h" +#include "sl_core.h" +#include "sl_code_classification.h" + +#if defined (SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) + #include "FreeRTOSConfig.h" + #if (configSUPPORT_STATIC_ALLOCATION == 1) + #include "FreeRTOS.h" // StaticSemaphore_t + #include + #endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Defines + +/// In order to wait forever in blocking functions the user can pass the +/// following value. +#define SLI_PSEC_OSAL_WAIT_FOREVER (osWaitForever) +/// In order to return immediately in blocking functions the user can pass the +/// following value. +#define SLI_PSEC_OSAL_NON_BLOCKING (0) + +// Checks if kernel is running +#define SLI_PSEC_OSAL_KERNEL_RUNNING (osKernelGetState() == osKernelRunning) + +// Lock kernel (task scheduler) to enter critical section +#define SLI_PSEC_OSAL_KERNEL_CRITICAL_SECTION_START \ + int32_t kernel_lock_state = 0; \ + osKernelState_t kernel_state = osKernelGetState(); \ + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ + kernel_lock_state = osKernelLock(); \ + if (kernel_lock_state < 0) { \ + return SL_STATUS_FAIL; \ + } \ + } + +// Resume kernel to exit critical section +#define SLI_PSEC_OSAL_KERNEL_CRITICAL_SECTION_END \ + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ + if (osKernelRestoreLock(kernel_lock_state) < 0) { \ + return SL_STATUS_FAIL; \ + } \ + } + +// ----------------------------------------------------------------------------- +// Typedefs + +/// Completion object used to wait for and signal end of an operation. +typedef struct sli_psec_osal_completion { +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) + osSemaphoreAttr_t semaphore_attr; + StaticSemaphore_t static_sem_object; +#endif + osSemaphoreId_t semaphore_ID; +} sli_psec_osal_completion_t; + +/// SLI PSEC lock definition for CMSIS RTOS2. +typedef struct sli_psec_osal_lock { +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t static_sem_object; +#endif + osMutexAttr_t mutex_attr; + osMutexId_t mutex_ID; +} sli_psec_osal_lock_t; + +// ----------------------------------------------------------------------------- +// Functions + +/***************************************************************************//** + * @brief Set recursive attribute of lock + * + * @details If recursive lock is needed, this function must be called + * before calling sli_psec_osal_init_lock. + * + * @param lock Pointer to the lock + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE +sl_status_t sli_psec_osal_set_recursive_lock(sli_psec_osal_lock_t *lock) +{ + if (lock == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + lock->mutex_attr.attr_bits |= osMutexRecursive; + return SL_STATUS_OK; +} + +/***************************************************************************//** + * @brief Initialize a given lock + * + * @param lock Pointer to the lock needing initialization + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t sli_psec_osal_init_lock(sli_psec_osal_lock_t *lock) +{ + if (lock == NULL) { + return SL_STATUS_FAIL; + } + +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) + // Zeroize all members of the lock attributes object and setup the static control block. + lock->mutex_attr.cb_mem = &lock->static_sem_object; + lock->mutex_attr.cb_size = sizeof(lock->static_sem_object); +#endif + + lock->mutex_ID = osMutexNew(&lock->mutex_attr); + + return (lock->mutex_ID == NULL ? SL_STATUS_FAIL : SL_STATUS_OK); +} + +/***************************************************************************//** + * @brief Free a given lock + * + * @param lock Pointer to the lock being freed + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t sli_psec_osal_free_lock(sli_psec_osal_lock_t *lock) +{ + if (lock == NULL) { + return SL_STATUS_FAIL; + } + + osStatus_t status = osMutexDelete(lock->mutex_ID); + return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); +} + +/***************************************************************************//** + * @brief Pend on a lock with timeout + * + * @param lock Pointer to the lock being pended on + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PSEC_OSAL, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_psec_osal_take_lock_timeout(sli_psec_osal_lock_t *lock, + uint32_t timeout); + +/***************************************************************************//** + * @brief Pend on a lock forever + * + * @param lock Pointer to the lock being pended on + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t sli_psec_osal_take_lock(sli_psec_osal_lock_t *lock) +{ + return sli_psec_osal_take_lock_timeout(lock, SLI_PSEC_OSAL_WAIT_FOREVER); +} + +/***************************************************************************//** + * @brief Try to acquire ownership of a lock without waiting. + * + * @param lock Pointer to the lock being tested + * + * @return SL_STATUS_OK on success (= lock successfully owned), + * error code otherwise. + *****************************************************************************/ +__STATIC_INLINE +sl_status_t sli_psec_osal_take_lock_non_blocking(sli_psec_osal_lock_t *lock) +{ + return sli_psec_osal_take_lock_timeout(lock, SLI_PSEC_OSAL_NON_BLOCKING); +} + +/***************************************************************************//** + * @brief Release a lock + * + * @param lock Pointer to the lock being released + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PSEC_OSAL, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_psec_osal_give_lock(sli_psec_osal_lock_t *lock); + +/***************************************************************************//** + * @brief Initialize a completion object. + * + * @param p_comp Pointer to an sli_psec_osal_completion_t object allocated + * by the user. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +sli_psec_osal_init_completion(sli_psec_osal_completion_t *p_comp) +{ + if (p_comp == NULL) { + return SL_STATUS_FAIL; + } + +#if defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) && (configSUPPORT_STATIC_ALLOCATION == 1) + // Zeroize all members of the semaphore attributes object and setup the static control block. + memset(&p_comp->semaphore_attr, 0, sizeof(p_comp->semaphore_attr)); + p_comp->semaphore_attr.cb_mem = &p_comp->static_sem_object; + p_comp->semaphore_attr.cb_size = sizeof(p_comp->static_sem_object); + p_comp->semaphore_ID = osSemaphoreNew(1u, 0u, &p_comp->semaphore_attr); +#else + p_comp->semaphore_ID = osSemaphoreNew(1u, 0u, NULL); +#endif + + return (p_comp->semaphore_ID == NULL ? SL_STATUS_FAIL : SL_STATUS_OK); +} + +/***************************************************************************//** + * @brief Free a completion object. + * + * @param p_comp Pointer to an sli_psec_osal_completion_t object. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +sli_psec_osal_free_completion(sli_psec_osal_completion_t *p_comp) +{ + if (p_comp == NULL) { + return SL_STATUS_FAIL; + } + + osStatus_t status = osSemaphoreDelete(p_comp->semaphore_ID); + return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); +} + +/***************************************************************************//** + * @brief Wait for completion event. + * + * @param p_comp Pointer to completion object which must be initialized by + * calling sli_psec_osal_completion_init before calling this + * function. + * + * @param ticks Ticks to wait for the completion. + * Pass a value of SLI_PSEC_OSAL_WAIT_FOREVER in order to + * wait forever. + * Pass a value of SLI_PSEC_OSAL_NON_BLOCKING in order to + * return immediately. + * + * @return Status code, @ref sl_status.h. Typcally SL_STATUS_OK if success, + * or SL_STATUS_TIMEOUT if no completion within the given ticks. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +sli_psec_osal_wait_completion(sli_psec_osal_completion_t *p_comp, int ticks) +{ + if (p_comp == NULL) { + return SL_STATUS_FAIL; + } + + osStatus_t status = osOK; + if (osKernelGetState() == osKernelRunning) { + status = osSemaphoreAcquire(p_comp->semaphore_ID, + (uint32_t)ticks); + } + return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); +} + +/***************************************************************************//** + * @brief Signal completion. + * + * @param p_comp Pointer to completion object which must be initialized by + * calling sli_psec_osal_completion_init before calling this + * function. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE +sl_status_t sli_psec_osal_complete(sli_psec_osal_completion_t* p_comp) +{ + if (p_comp == NULL) { + return SL_STATUS_FAIL; + } + + osStatus_t status = osOK; + osKernelState_t state = osKernelGetState(); + if ((state == osKernelRunning) || (state == osKernelLocked)) { + status = osSemaphoreRelease(p_comp->semaphore_ID); + } + return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); +} + +/***************************************************************************//** + * @brief Lock the RTOS Kernel scheduler. + * + * @return Status code, @ref cmsis_os2.h + *****************************************************************************/ +__STATIC_INLINE int32_t sli_psec_osal_kernel_lock(void) +{ + return osKernelLock(); +} + +/***************************************************************************//** + * @brief Restore the RTOS Kernel scheduler lock state. + * + * @return Status code, @ref cmsis_os2.h + *****************************************************************************/ +__STATIC_INLINE int32_t sli_psec_osal_kernel_restore_lock(int32_t lock) +{ + return osKernelRestoreLock(lock); +} + +/***************************************************************************//** + * @brief Get current RTOS kernel state. + * + * @return Status code, @ref cmsis_os2.h + *****************************************************************************/ +__STATIC_INLINE osKernelState_t +sli_psec_osal_kernel_get_state(void) +{ + return osKernelGetState(); +} + +#ifdef __cplusplus +} +#endif + +#endif // SLI_PSEC_OSAL_CMSIS_RTOS_H diff --git a/simplicity_sdk/platform/security/sl_component/sli_psec_osal/src/sli_psec_osal_cmsis_rtos2.c b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/src/sli_psec_osal_cmsis_rtos2.c new file mode 100644 index 000000000..f0e8d63d8 --- /dev/null +++ b/simplicity_sdk/platform/security/sl_component/sli_psec_osal/src/sli_psec_osal_cmsis_rtos2.c @@ -0,0 +1,102 @@ +/**************************************************************************/ /** + * @file + * @brief OS abstraction layer primitives for platform/security on CMSIS RTOS2 + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Includes +#include "sl_common.h" +#include "sli_psec_osal_cmsis_rtos2.h" + +// ----------------------------------------------------------------------------- +// Functions + +/// Check if lock is open for calling thread +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_PSEC_OSAL, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_psec_osal_lock_is_accessible(sli_psec_osal_lock_t *lock) +{ + sl_status_t sl_status; + CORE_DECLARE_IRQ_STATE; + if (lock == NULL) { + return SL_STATUS_FAIL; + } + CORE_ENTER_CRITICAL(); + osThreadId_t mutex_owner = osMutexGetOwner(lock->mutex_ID); + if (mutex_owner == NULL) { + sl_status = SL_STATUS_OK; + } else { + if (mutex_owner != osThreadGetId()) { + sl_status = SL_STATUS_FAIL; + } else { + if (lock->mutex_attr.attr_bits & osMutexRecursive) { + sl_status = SL_STATUS_OK; + } else { + sl_status = SL_STATUS_FAIL; + } + } + } + CORE_EXIT_CRITICAL(); + return sl_status; +} + +/// Attempt to take ownership or lock. Wait until available if already locked, or timeout. +sl_status_t sli_psec_osal_take_lock_timeout(sli_psec_osal_lock_t *lock, uint32_t timeout) +{ + if (lock == NULL) { + return SL_STATUS_FAIL; + } + + osStatus_t status = osOK; + if (osKernelGetState() == osKernelRunning) { + if (CORE_IRQ_DISABLED()) { + return sli_psec_osal_lock_is_accessible(lock); + } else { + status = osMutexAcquire(lock->mutex_ID, timeout); + } + } + return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); +} + +/// Release ownership of a lock. +sl_status_t sli_psec_osal_give_lock(sli_psec_osal_lock_t *lock) +{ + if (lock == NULL) { + return SL_STATUS_FAIL; + } + + osStatus_t status = osOK; + if (osKernelGetState() == osKernelRunning) { + if (CORE_IRQ_DISABLED()) { + return sli_psec_osal_lock_is_accessible(lock); + } else { + status = osMutexRelease(lock->mutex_ID); + } + } + + return (status == osOK ? SL_STATUS_OK : SL_STATUS_FAIL); +} diff --git a/simplicity_sdk/platform/service/clock_manager/config/BGM21/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/BGM21/sl_clock_manager_tree_config.h deleted file mode 100644 index 924916d18..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/BGM21/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,217 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// HCLK -// HFRCOEM23 -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_HCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_HCLK -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// HFRCOEM23 -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// HFRCOEM23 -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/BGM24/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/BGM24/sl_clock_manager_tree_config.h deleted file mode 100644 index ef8ba96ee..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/BGM24/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,282 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG22/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFM32PG22/sl_clock_manager_oscillator_config.h deleted file mode 100644 index cd8e16413..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG22/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,230 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 76800000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG22/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFM32PG22/sl_clock_manager_tree_config.h deleted file mode 100644 index 30e358fff..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG22/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPBCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// CLKIN0 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPBCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUARTCLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// Selection of the Clock source for EUARTCLK -// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG23/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFM32PG23/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG23/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG26/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFM32PG26/sl_clock_manager_tree_config.h deleted file mode 100644 index 5a5097c54..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG26/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,293 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG28/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFM32PG28/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG28/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG28/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFM32PG28/sl_clock_manager_tree_config.h deleted file mode 100644 index ac5e7bd6c..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG28/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG21/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32BG21/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 191a766fe..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG21/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 80000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3999 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3999 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG22/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32BG22/sl_clock_manager_oscillator_config.h deleted file mode 100644 index cd8e16413..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG22/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,230 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 76800000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG22/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32BG22/sl_clock_manager_tree_config.h deleted file mode 100644 index 30e358fff..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG22/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPBCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// CLKIN0 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPBCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUARTCLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// Selection of the Clock source for EUARTCLK -// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG24/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32BG24/sl_clock_manager_tree_config.h deleted file mode 100644 index ef8ba96ee..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG24/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,282 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG26/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32BG26/sl_clock_manager_tree_config.h deleted file mode 100644 index 5a5097c54..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG26/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,293 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG27/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32BG27/sl_clock_manager_tree_config.h deleted file mode 100644 index c0a51b65c..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG27/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,241 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLED -// SYSCLK -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPBCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// CLKIN0 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPBCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG22/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32FG22/sl_clock_manager_oscillator_config.h deleted file mode 100644 index cd8e16413..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG22/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,230 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 76800000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG22/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32FG22/sl_clock_manager_tree_config.h deleted file mode 100644 index 30e358fff..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG22/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPBCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// CLKIN0 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPBCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUARTCLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// Selection of the Clock source for EUARTCLK -// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG23/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32FG23/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG23/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG23/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32FG23/sl_clock_manager_tree_config.h deleted file mode 100644 index d3fa48fcf..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG23/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,290 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG28/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32FG28/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG28/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG22/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MG22/sl_clock_manager_oscillator_config.h deleted file mode 100644 index cd8e16413..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG22/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,230 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 76800000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG22/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MG22/sl_clock_manager_tree_config.h deleted file mode 100644 index 30e358fff..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG22/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPBCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// CLKIN0 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPBCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUARTCLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// Selection of the Clock source for EUARTCLK -// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG24/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MG24/sl_clock_manager_oscillator_config.h deleted file mode 100644 index bbceeee43..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG24/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,321 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG24/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MG24/sl_clock_manager_tree_config.h deleted file mode 100644 index ef8ba96ee..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG24/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,282 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG26/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MG26/sl_clock_manager_oscillator_config.h deleted file mode 100644 index bbceeee43..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG26/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,321 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG26/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MG26/sl_clock_manager_tree_config.h deleted file mode 100644 index 5a5097c54..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG26/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,293 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG27/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MG27/sl_clock_manager_oscillator_config.h deleted file mode 100644 index cd8e16413..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG27/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,230 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 76800000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MR21/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MR21/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 191a766fe..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MR21/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 80000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3999 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3999 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MR21/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32MR21/sl_clock_manager_tree_config.h deleted file mode 100644 index 5f860fef7..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MR21/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,207 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// HCLK -// HFRCOEM23 -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_HCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_HCLK -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// HFRCOEM23 -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG23/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32SG23/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG23/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG23/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32SG23/sl_clock_manager_tree_config.h deleted file mode 100644 index d3fa48fcf..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG23/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,290 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG28/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32SG28/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG28/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG23/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG23/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG23/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG23/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG23/sl_clock_manager_tree_config.h deleted file mode 100644 index d3fa48fcf..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG23/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,290 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG28/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG28/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG28/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG21/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_oscillator_config.h similarity index 82% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32MG21/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_oscillator_config.h index 191a766fe..e156b6ee8 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG21/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -50,7 +72,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 38400000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 @@ -62,12 +84,12 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -141,7 +163,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 80000000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -167,6 +189,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -222,8 +245,25 @@ #endif // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG21/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_tree_config.h similarity index 93% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32MG21/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_tree_config.h index 924916d18..ab95b171d 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG21/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG21/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -92,9 +106,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG29/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_oscillator_config.h similarity index 83% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32MG29/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_oscillator_config.h index 5998ff54e..517d85a1c 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG29/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -50,7 +72,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 38400000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 @@ -62,12 +84,12 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -141,7 +163,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 76800000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -224,8 +246,25 @@ #endif // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/BGM22/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_tree_config.h similarity index 93% rename from simplicity_sdk/platform/service/clock_manager/config/BGM22/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_tree_config.h index 30e358fff..36636df03 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/BGM22/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG22/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -94,9 +108,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG26/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_oscillator_config.h similarity index 87% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32BG26/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_oscillator_config.h index bbceeee43..0c9f5747e 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG26/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -51,7 +73,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 39000000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 @@ -63,7 +85,7 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 @@ -140,7 +162,7 @@ #define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 #endif // -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -214,7 +236,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 78000000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -240,6 +262,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -295,27 +318,25 @@ #endif // -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 #endif // // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG23/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_tree_config.h similarity index 95% rename from simplicity_sdk/platform/service/clock_manager/config/EFM32PG23/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_tree_config.h index d3fa48fcf..c12324894 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG23/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG23/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -94,9 +108,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG26/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_oscillator_config.h similarity index 88% rename from simplicity_sdk/platform/service/clock_manager/config/EFM32PG26/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_oscillator_config.h index bbceeee43..20cc0d452 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFM32PG26/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -51,7 +73,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 39000000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 @@ -63,7 +85,7 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 @@ -140,7 +162,7 @@ #define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 #endif // -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -214,7 +236,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 78000000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -240,6 +262,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -314,8 +337,25 @@ #endif // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG28/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_tree_config.h similarity index 91% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32ZG28/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_tree_config.h index ac5e7bd6c..472741a24 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32ZG28/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG24/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -94,9 +108,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // @@ -167,15 +181,6 @@ #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK #endif -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - // // Low Frequency Clock Branches Settings @@ -237,17 +242,6 @@ #define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE #endif -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - // Clock Source Selection for PCNT0CLK branch // DISABLED // EM23GRPACLK @@ -294,6 +288,18 @@ #define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK #endif +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + // // diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG25/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_oscillator_config.h similarity index 89% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32FG25/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_oscillator_config.h index c1819debf..d18036a86 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG25/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -51,7 +73,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 39000000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 @@ -63,7 +85,7 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 @@ -140,7 +162,7 @@ #define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 #endif // -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -215,7 +237,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 78000000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -241,6 +263,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -357,8 +380,25 @@ // // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG25/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_tree_config.h similarity index 95% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32FG25/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_tree_config.h index 279832813..992643d9c 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG25/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG25/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // RFFPLL0SYS // Selection of the Clock source for SYSCLK // CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS @@ -95,9 +109,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG24/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_oscillator_config.h similarity index 88% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32BG24/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_oscillator_config.h index bbceeee43..20cc0d452 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG24/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -51,7 +73,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 39000000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 @@ -63,7 +85,7 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 @@ -140,7 +162,7 @@ #define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 #endif // -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -214,7 +236,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 78000000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -240,6 +262,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -314,8 +337,25 @@ #endif // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG28/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_tree_config.h similarity index 91% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32SG28/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_tree_config.h index ac5e7bd6c..6ec4ee981 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32SG28/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG26/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -94,9 +108,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // @@ -167,15 +181,6 @@ #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK #endif -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - // // Low Frequency Clock Branches Settings @@ -294,6 +299,18 @@ #define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK #endif +// Clock Source Selection for VDAC1CLK branch +// DISABLED +// EM01GRPACLK +// EM23GRPACLK +// FSRCO +// HFRCOEM23 +// Selection of the Clock source for VDAC1CLK +// CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#ifndef SL_CLOCK_MANAGER_VDAC1CLK_SOURCE +#define SL_CLOCK_MANAGER_VDAC1CLK_SOURCE CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK +#endif + // // diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG27/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_oscillator_config.h similarity index 83% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32BG27/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_oscillator_config.h index cd8e16413..517d85a1c 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG27/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -50,7 +72,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 38400000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 @@ -62,12 +84,12 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -141,7 +163,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 76800000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -167,6 +189,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -223,8 +246,25 @@ #endif // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG27/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_tree_config.h similarity index 94% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32MG27/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_tree_config.h index c0a51b65c..3f788869d 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG27/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG27/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -94,9 +108,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // diff --git a/simplicity_sdk/platform/service/clock_manager/config/BGM24/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_oscillator_config.h similarity index 87% rename from simplicity_sdk/platform/service/clock_manager/config/BGM24/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_oscillator_config.h index bbceeee43..0c9f5747e 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/BGM24/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -51,7 +73,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 39000000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 @@ -63,7 +85,7 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 @@ -140,7 +162,7 @@ #define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 #endif // -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -214,7 +236,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 78000000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -240,6 +262,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -295,27 +318,25 @@ #endif // -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 #endif // // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG28/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_tree_config.h similarity index 95% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32FG28/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_tree_config.h index ac5e7bd6c..7f8119fb7 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32FG28/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG28/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -94,9 +108,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // diff --git a/simplicity_sdk/platform/service/clock_manager/config/BGM22/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_oscillator_config.h similarity index 83% rename from simplicity_sdk/platform/service/clock_manager/config/BGM22/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_oscillator_config.h index cd8e16413..517d85a1c 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/BGM22/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -50,7 +72,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 38400000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 @@ -62,12 +84,12 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -141,7 +163,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 76800000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -167,6 +189,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -223,8 +246,25 @@ #endif // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG29/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_tree_config.h similarity index 94% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32MG29/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_tree_config.h index 3b4980f6b..850679a7d 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32MG29/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XG29/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -95,9 +108,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // @@ -108,9 +121,9 @@ // SYSCLK // HFRCODPLLRT // Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_DISABLED +// CMU_TRACECLKCTRL_CLKSEL_SYSCLK #ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_DISABLED +#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK #endif // TRACECLK branch Divider diff --git a/simplicity_sdk/platform/service/clock_manager/config/BGM21/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_oscillator_config.h similarity index 82% rename from simplicity_sdk/platform/service/clock_manager/config/BGM21/sl_clock_manager_oscillator_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_oscillator_config.h index 191a766fe..e156b6ee8 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/BGM21/sl_clock_manager_oscillator_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_oscillator_config.h @@ -28,17 +28,39 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H + #ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H #define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + +// Internal Defines: DO NOT MODIFY +#define SL_CLOCK_MANAGER_HFXO_EN_ENABLE 1 +#define SL_CLOCK_MANAGER_HFXO_EN_DISABLE 0 + +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_ENABLE +#else +#define SL_CLOCK_MANAGER_HFXO_EN_AUTO SL_CLOCK_MANAGER_HFXO_EN_DISABLE +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Oscillators Settings -// HFXO Settings (if High Frequency crystal is used) +// HFXO Settings (if High Frequency crystal is used) + +// Enable // Enable to configure HFXO +// AUTO enables HFXO if a radio is used +// AUTO +// ENABLE +// DISABLE +// SL_CLOCK_MANAGER_HFXO_EN_AUTO #ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 +#define SL_CLOCK_MANAGER_HFXO_EN SL_CLOCK_MANAGER_HFXO_EN_AUTO #endif // Mode @@ -50,7 +72,7 @@ #define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL #endif -// Frequency <38000000-40000000> +// Frequency in Hz <38000000-40000000> // 38400000 #ifndef SL_CLOCK_MANAGER_HFXO_FREQ #define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 @@ -62,12 +84,12 @@ #define SL_CLOCK_MANAGER_HFXO_CTUNE 140 #endif -// Precision <0-65535> +// Precision in PPM <0-65535> // 50 #ifndef SL_CLOCK_MANAGER_HFXO_PRECISION #define SL_CLOCK_MANAGER_HFXO_PRECISION 50 #endif -// +// // LFXO Settings (if Low Frequency crystal is used) // Enable to configure LFXO @@ -141,7 +163,7 @@ #define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 #endif -// Target Frequency <1000000-80000000> +// Target Frequency in Hz <1000000-80000000> // DPLL target frequency // 80000000 #ifndef SL_CLOCK_MANAGER_DPLL_FREQ @@ -167,6 +189,7 @@ // DISABLED // HFXO // LFXO +// CLKIN0 // CMU_DPLLREFCLKCTRL_CLKSEL_HFXO #ifndef SL_CLOCK_MANAGER_DPLL_REFCLK #define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO @@ -222,8 +245,25 @@ #endif // +// CLKIN0 Settings +// Frequency in Hz <1000000-38000000> +// 38000000 +#ifndef SL_CLOCK_MANAGER_CLKIN0_FREQ +#define SL_CLOCK_MANAGER_CLKIN0_FREQ 38000000 +#endif // -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ +// // <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_CLOCK_MANAGER_CLKIN0 +// $[CMU_SL_CLOCK_MANAGER_CLKIN0] + +// [CMU_SL_CLOCK_MANAGER_CLKIN0]$ + +// <<< sl:end pin_tool >>> + +#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG21/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_tree_config.h similarity index 93% rename from simplicity_sdk/platform/service/clock_manager/config/EFR32BG21/sl_clock_manager_tree_config.h rename to simplicity_sdk/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_tree_config.h index 924916d18..47a508dee 100644 --- a/simplicity_sdk/platform/service/clock_manager/config/EFR32BG21/sl_clock_manager_tree_config.h +++ b/simplicity_sdk/platform/service/clock_manager/config/EFX32XR21/sl_clock_manager_tree_config.h @@ -28,11 +28,14 @@ * ******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> - #ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H #define SL_CLOCK_MANAGER_TREE_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif + // Internal Defines: DO NOT MODIFY // Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE // selection of each clock branch to the right HW register value. @@ -43,16 +46,26 @@ #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB #define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO +#else +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + // Clock Tree Settings // Default Clock Source Selection for HF clock branches +// AUTO // HFRCODPLL // HFXO // FSRCO // Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +// AUTO uses HFXO if a radio is used and HFRCODPLL otherwise +// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL +#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO #endif // Default Clock Source Selection for LF clock branches @@ -72,6 +85,7 @@ // FSRCO // HFRCODPLL // HFXO +// CLKIN0 // Selection of the Clock source for SYSCLK // SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE @@ -92,9 +106,9 @@ // DIV1 // DIV2 // PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +// CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 +#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1 #endif // @@ -126,16 +140,6 @@ #define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE #endif -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// HFRCOEM23 -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - // // Low Frequency Clock Branches Settings diff --git a/simplicity_sdk/platform/service/clock_manager/config/FGM23/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/FGM23/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/FGM23/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/FGM23/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/FGM23/sl_clock_manager_tree_config.h deleted file mode 100644 index d3fa48fcf..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/FGM23/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,290 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/MGM21/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/MGM21/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 191a766fe..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/MGM21/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 80000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 80000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3999 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3999 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/MGM21/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/MGM21/sl_clock_manager_tree_config.h deleted file mode 100644 index 924916d18..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/MGM21/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,217 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// HCLK -// HFRCOEM23 -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_HCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_HCLK -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// HFRCOEM23 -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// HFRCOEM23 -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/MGM22/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/MGM22/sl_clock_manager_oscillator_config.h deleted file mode 100644 index cd8e16413..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/MGM22/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,230 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 38400000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 38400000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 76800000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 76800000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/MGM22/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/MGM22/sl_clock_manager_tree_config.h deleted file mode 100644 index 30e358fff..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/MGM22/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,229 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPBCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// CLKIN0 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPBCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for RTCCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_RTCCCLK_SOURCE -#define SL_CLOCK_MANAGER_RTCCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUARTCLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// Selection of the Clock source for EUARTCLK -// CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_EUART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUART0CLK_SOURCE CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/MGM24/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/MGM24/sl_clock_manager_oscillator_config.h deleted file mode 100644 index bbceeee43..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/MGM24/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,321 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// LFRCO Settings -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// cmuPrecisionDefault -#ifndef SL_CLOCK_MANAGER_LFRCO_PRECISION -#define SL_CLOCK_MANAGER_LFRCO_PRECISION cmuPrecisionDefault -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/MGM24/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/MGM24/sl_clock_manager_tree_config.h deleted file mode 100644 index ef8ba96ee..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/MGM24/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,282 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// Clock Source Selection for TRACECLK branch -// DISABLE -// SYSCLK -// HFRCOEM23 -// HFRCODPLLRT -// Selection of the Clock source for TRACECLK -// CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#ifndef SL_CLOCK_MANAGER_TRACECLK_SOURCE -#define SL_CLOCK_MANAGER_TRACECLK_SOURCE CMU_TRACECLKCTRL_CLKSEL_SYSCLK -#endif - -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV3 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/ZGM23/sl_clock_manager_oscillator_config.h b/simplicity_sdk/platform/service/clock_manager/config/ZGM23/sl_clock_manager_oscillator_config.h deleted file mode 100644 index 46d50f675..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/ZGM23/sl_clock_manager_oscillator_config.h +++ /dev/null @@ -1,302 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Oscillators configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H -#define SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H - -// Oscillators Settings - -// HFXO Settings (if High Frequency crystal is used) -// Enable to configure HFXO -#ifndef SL_CLOCK_MANAGER_HFXO_EN -#define SL_CLOCK_MANAGER_HFXO_EN 0 -#endif - -// Mode -// -// XTAL -// EXTCLK -// EXTCLKPKDET -// HFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_HFXO_MODE -#define SL_CLOCK_MANAGER_HFXO_MODE HFXO_CFG_MODE_XTAL -#endif - -// Frequency <38000000-40000000> -// 39000000 -#ifndef SL_CLOCK_MANAGER_HFXO_FREQ -#define SL_CLOCK_MANAGER_HFXO_FREQ 39000000 -#endif - -// CTUNE <0-255> -// 140 -#ifndef SL_CLOCK_MANAGER_HFXO_CTUNE -#define SL_CLOCK_MANAGER_HFXO_CTUNE 140 -#endif - -// Precision <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_HFXO_PRECISION -#define SL_CLOCK_MANAGER_HFXO_PRECISION 50 -#endif - -// HFXO crystal sharing feature -// Enable to configure HFXO crystal sharing leader or follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN 0 -#endif - -// Crystal sharing leader -// Enable to configure HFXO crystal sharing leader -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN 0 -#endif - -// Crystal sharing leader minimum startup delay -// If enabled, BUFOUT does not start until timeout set in -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP expires. -// This prevents waste of power if BUFOUT is ready too early. -// 1 -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_MIN_STARTUP_DELAY_EN 1 -#endif - -// Wait duration of oscillator startup sequence -// -// T42US -// T83US -// T108US -// T133US -// T158US -// T183US -// T208US -// T233US -// T258US -// T283US -// T333US -// T375US -// T417US -// T458US -// T500US -// T667US -// HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_TIMEOUT_STARTUP HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US -#endif -// -// - -// Crystal sharing follower -// Enable to configure HFXO crystal sharing follower -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN 0 -#endif -// - -// GPIO Port -// Bufout request GPIO port. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this port will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this port -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT 0 -#endif - -// GPIO Pin -// Bufout request GPIO pin. If SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_LEADER_EN -// is enabled, this pin will be used to receive the BUFOUT request. If -// SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_FOLLOWER_EN is enabled this pin -// will be used to request BUFOUT from the crystal sharing leader. -#ifndef SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN -#define SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PIN 10 -#endif -// -// - -// LFXO Settings (if Low Frequency crystal is used) -// Enable to configure LFXO -#ifndef SL_CLOCK_MANAGER_LFXO_EN -#define SL_CLOCK_MANAGER_LFXO_EN 0 -#endif - -// Mode -// -// XTAL -// BUFEXTCLK -// DIGEXTCLK -// LFXO_CFG_MODE_XTAL -#ifndef SL_CLOCK_MANAGER_LFXO_MODE -#define SL_CLOCK_MANAGER_LFXO_MODE LFXO_CFG_MODE_XTAL -#endif - -// CTUNE <0-127> -// 63 -#ifndef SL_CLOCK_MANAGER_LFXO_CTUNE -#define SL_CLOCK_MANAGER_LFXO_CTUNE 63 -#endif - -// LFXO precision in PPM <0-65535> -// 50 -#ifndef SL_CLOCK_MANAGER_LFXO_PRECISION -#define SL_CLOCK_MANAGER_LFXO_PRECISION 50 -#endif - -// Startup Timeout Delay -// -// CYCLES2 -// CYCLES256 -// CYCLES1K -// CYCLES2K -// CYCLES4K -// CYCLES8K -// CYCLES16K -// CYCLES32K -// LFXO_CFG_TIMEOUT_CYCLES4K -#ifndef SL_CLOCK_MANAGER_LFXO_TIMEOUT -#define SL_CLOCK_MANAGER_LFXO_TIMEOUT LFXO_CFG_TIMEOUT_CYCLES4K -#endif -// - -// HFRCO and DPLL Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 7 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 38 MHz -// 48 MHz -// 56 MHz -// 64 MHz -// 80 MHz -// cmuHFRCODPLLFreq_80M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCO_BAND -#define SL_CLOCK_MANAGER_HFRCO_BAND cmuHFRCODPLLFreq_80M0Hz -#endif - -// Use DPLL -// Enable to use the DPLL with HFRCO -#ifndef SL_CLOCK_MANAGER_HFRCO_DPLL_EN -#define SL_CLOCK_MANAGER_HFRCO_DPLL_EN 0 -#endif - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// 78000000 -#ifndef SL_CLOCK_MANAGER_DPLL_FREQ -#define SL_CLOCK_MANAGER_DPLL_FREQ 78000000 -#endif - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// 3839 -#ifndef SL_CLOCK_MANAGER_DPLL_N -#define SL_CLOCK_MANAGER_DPLL_N 3839 -#endif - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// 1919 -#ifndef SL_CLOCK_MANAGER_DPLL_M -#define SL_CLOCK_MANAGER_DPLL_M 1919 -#endif - -// Reference Clock -// Reference clock source for DPLL -// DISABLED -// HFXO -// LFXO -// CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#ifndef SL_CLOCK_MANAGER_DPLL_REFCLK -#define SL_CLOCK_MANAGER_DPLL_REFCLK CMU_DPLLREFCLKCTRL_CLKSEL_HFXO -#endif - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// cmuDPLLEdgeSel_Fall -#ifndef SL_CLOCK_MANAGER_DPLL_EDGE -#define SL_CLOCK_MANAGER_DPLL_EDGE cmuDPLLEdgeSel_Fall -#endif - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// cmuDPLLLockMode_Freq -#ifndef SL_CLOCK_MANAGER_DPLL_LOCKMODE -#define SL_CLOCK_MANAGER_DPLL_LOCKMODE cmuDPLLLockMode_Phase -#endif - -// Automatic Lock Recovery -// 1 -#ifndef SL_CLOCK_MANAGER_DPLL_AUTORECOVER -#define SL_CLOCK_MANAGER_DPLL_AUTORECOVER 1 -#endif - -// Enable Dither -// 0 -#ifndef SL_CLOCK_MANAGER_DPLL_DITHER -#define SL_CLOCK_MANAGER_DPLL_DITHER 0 -#endif -// -// - -// HFRCOEM23 Settings -// Frequency Band -// RC Oscillator Frequency Band -// 1 MHz -// 2 MHz -// 4 MHz -// 13 MHz -// 16 MHz -// 19 MHz -// 26 MHz -// 32 MHz -// 40 MHz -// cmuHFRCOEM23Freq_19M0Hz -#ifndef SL_CLOCK_MANAGER_HFRCOEM23_BAND -#define SL_CLOCK_MANAGER_HFRCOEM23_BAND cmuHFRCOEM23Freq_19M0Hz -#endif -// - -// - -#endif /* SL_CLOCK_MANAGER_OSCILLATOR_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/config/ZGM23/sl_clock_manager_tree_config.h b/simplicity_sdk/platform/service/clock_manager/config/ZGM23/sl_clock_manager_tree_config.h deleted file mode 100644 index d3fa48fcf..000000000 --- a/simplicity_sdk/platform/service/clock_manager/config/ZGM23/sl_clock_manager_tree_config.h +++ /dev/null @@ -1,290 +0,0 @@ -/***************************************************************************//** - * @file - * @brief Clock Manager - Clock Tree configuration file. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_CLOCK_MANAGER_TREE_CONFIG_H -#define SL_CLOCK_MANAGER_TREE_CONFIG_H - -// Internal Defines: DO NOT MODIFY -// Those defines are used internally to help converting the DEFAULT_HF_CLOCK_SOURCE and DEFAULT_LF_CLOCK_SOURCE -// selection of each clock branch to the right HW register value. -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL 0xFF -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFXO 0xFE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_FSRCO 0xFD -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO 0xFC -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFXO 0xFB -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_ULFRCO 0xFA - -// Clock Tree Settings - -// Default Clock Source Selection for HF clock branches -// HFRCODPLL -// HFXO -// FSRCO -// Selection of the high frequency clock source. HF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#ifndef SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_HFRCODPLL -#endif - -// Default Clock Source Selection for LF clock branches -// LFRCO -// LFXO -// ULFRCO -// Selection of the low frequency clock source. LF clock branches can select this value by chosing the DEFAULT_HF value. -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#ifndef SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#define SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE_LFRCO -#endif - -// System Clock Branch Settings - -// Clock Source Selection for SYSCLK branch -// DEFAULT_HF -// FSRCO -// HFRCODPLL -// HFXO -// Selection of the Clock source for SYSCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// HCLK branch divider -// DIV1 -// DIV2 -// DIV4 -// DIV8 -// DIV16 -// HCLK branch is derived from SYSCLK. This clock drives the AHB bus interface. -// CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_HCLK_DIVIDER -#define SL_CLOCK_MANAGER_HCLK_DIVIDER CMU_SYSCLKCTRL_HCLKPRESC_DIV1 -#endif - -// PCLK branch divider -// DIV1 -// DIV2 -// PCLK branch is derived from HCLK. This clock drives the APB bus interface. -// CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER -#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV2 -#endif - -// - -// Trace Clock Branches Settings -// TRACECLK branch Divider -// DIV1 -// DIV2 -// DIV4 -// Selection of the divider value for TRACECLK branch -// CMU_TRACECLKCTRL_PRESC_DIV1 -#ifndef SL_CLOCK_MANAGER_TRACECLK_DIVIDER -#define SL_CLOCK_MANAGER_TRACECLK_DIVIDER CMU_TRACECLKCTRL_PRESC_DIV1 -#endif - -// - -// High Frequency Clock Branches Settings -// Each HF Clock Tree branch can be customized, else the same clock source as for SYSCLK will be used when possible -// EM01GRPACLK clock the Timer peripherals -// Clock Source Selection for EM01GRPACLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM01GRPCCLK branch -// DEFAULT_HF -// HFRCODPLL -// HFXO -// FSRCO -// HFRCOEM23 -// HFRCODPLLRT -// HFXORT -// Selection of the Clock source for EM01GRPCCLK -// SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE -#define SL_CLOCK_MANAGER_EM01GRPCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE -#endif - -// Clock Source Selection for IADCCLK branch -// EM01GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for IADCCLK -// CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_IADCCLK_SOURCE -#define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// Clock Source Selection for LESENSEHFCLK branch -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for LESENSEHFCLK -// CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#ifndef SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE -#define SL_CLOCK_MANAGER_LESENSEHFCLK_SOURCE CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO -#endif - -// - -// Low Frequency Clock Branches Settings - -// Clock Source Selection for EM23GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM23GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM23GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for EM4GRPACLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for EM4GRPACLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE -#define SL_CLOCK_MANAGER_EM4GRPACLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for SYSRTCCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for SYSRTCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSRTCCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG0CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG0CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG0CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG0CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for WDOG1CLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// HCLKDIV1024 -// Selection of the Clock source for WDOG1CLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_WDOG1CLK_SOURCE -#define SL_CLOCK_MANAGER_WDOG1CLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for LCDCLK branch -// DEFAULT_LF -// LFRCO -// LFXO -// ULFRCO -// Selection of the Clock source for LDCCLK -// SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#ifndef SL_CLOCK_MANAGER_LCDCLK_SOURCE -#define SL_CLOCK_MANAGER_LCDCLK_SOURCE SL_CLOCK_MANAGER_DEFAULT_LF_CLOCK_SOURCE -#endif - -// Clock Source Selection for PCNT0CLK branch -// DISABLED -// EM23GRPACLK -// PCNTS0 -// Selection of the Clock source for PCNT0CLK -// CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#ifndef SL_CLOCK_MANAGER_PCNT0CLK_SOURCE -#define SL_CLOCK_MANAGER_PCNT0CLK_SOURCE CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK -#endif - -// - -// Mixed Frequency Clock Branch Settings -// Clock Source Selection for EUSART0CLK branch -// DISABLED -// EM01GRPCCLK -// HFRCOEM23 -// LFRCO -// LFXO -// Selection of the Clock source for EUSART0CLK -// CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#ifndef SL_CLOCK_MANAGER_EUSART0CLK_SOURCE -#define SL_CLOCK_MANAGER_EUSART0CLK_SOURCE CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK -#endif - -// Clock Source Selection for SYSTICKCLK branch -// <0=> HCLK -// <1=> EM23GRPACLK -// Selection of the Clock source for SYSTICKCLK -// 0 -#ifndef SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE -#define SL_CLOCK_MANAGER_SYSTICKCLK_SOURCE 0 -#endif - -// Clock Source Selection for VDAC0CLK branch -// DISABLED -// EM01GRPACLK -// EM23GRPACLK -// FSRCO -// HFRCOEM23 -// Selection of the Clock source for VDAC0CLK -// CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#ifndef SL_CLOCK_MANAGER_VDAC0CLK_SOURCE -#define SL_CLOCK_MANAGER_VDAC0CLK_SOURCE CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK -#endif - -// -// - -#endif /* SL_CLOCK_MANAGER_TREE_CONFIG_H */ - -// <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/clock_manager/inc/sl_clock_manager.h b/simplicity_sdk/platform/service/clock_manager/inc/sl_clock_manager.h index 14db5e041..f81db0a1e 100644 --- a/simplicity_sdk/platform/service/clock_manager/inc/sl_clock_manager.h +++ b/simplicity_sdk/platform/service/clock_manager/inc/sl_clock_manager.h @@ -36,6 +36,7 @@ #include "sl_status.h" #include "sl_enum.h" #include "sl_device_clock.h" +#include "sl_code_classification.h" #ifdef __cplusplus extern "C" { @@ -321,6 +322,7 @@ sl_status_t sl_clock_manager_runtime_init(void); * @return Status code. * SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sl_clock_manager_get_oscillator_frequency(sl_oscillator_t oscillator, uint32_t *frequency); @@ -347,6 +349,7 @@ sl_status_t sl_clock_manager_get_oscillator_precision(sl_oscillator_t oscillator * @return Status code. * SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sl_clock_manager_get_clock_branch_frequency(sl_clock_branch_t clock_branch, uint32_t *frequency); diff --git a/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c b/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c index 223556e95..3d7aa35bb 100644 --- a/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c +++ b/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_hal_s2.c @@ -295,6 +295,11 @@ sl_status_t sli_clock_manager_hal_get_clock_branch_frequency(sl_clock_branch_t c *frequency = CMU_ClockFreqGet(cmuClock_USB); break; #endif +#if defined(_CMU_DPLLREFCLKCTRL_MASK) + case SL_CLOCK_BRANCH_DPLLREFCLK: + *frequency = CMU_ClockFreqGet(cmuClock_DPLLREFCLK); + break; +#endif default: *frequency = 0U; @@ -477,6 +482,13 @@ sl_status_t sli_clock_manager_hal_get_clock_branch_precision(sl_clock_branch_t c break; #endif +#if defined(_CMU_DPLLREFCLKCTRL_MASK) + case SL_CLOCK_BRANCH_DPLLREFCLK: + *precision = 0U; + return_status = SL_STATUS_NOT_SUPPORTED; + break; +#endif + default: *precision = 0U; return_status = SL_STATUS_INVALID_PARAMETER; @@ -1004,3 +1016,25 @@ sl_status_t sli_clock_manager_hal_wait_usbpll(void) return SL_STATUS_NOT_AVAILABLE; #endif } + +/***************************************************************************//** + * Updates QSPI clock and reference clock. + ******************************************************************************/ +sl_status_t sli_clock_manager_hal_update_qspi_clk(sl_oscillator_t oscillator) +{ + (void)oscillator; + return SL_STATUS_NOT_AVAILABLE; +} + +/***************************************************************************//** + * Gets QSPI clock source. + ******************************************************************************/ +sl_status_t sli_clock_manager_get_current_qspi_clk(sl_oscillator_t *oscillator) +{ + if (oscillator == NULL) { + return SL_STATUS_NULL_POINTER; + } + + (void)oscillator; + return SL_STATUS_NOT_AVAILABLE; +} diff --git a/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c b/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c index 84349441f..7173f92b7 100644 --- a/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c +++ b/simplicity_sdk/platform/service/clock_manager/src/sl_clock_manager_init_hal_s2.c @@ -36,6 +36,11 @@ #include "sl_assert.h" #include "em_device.h" #include "em_cmu.h" +#include "sl_gpio.h" + +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +#include "sli_clock_manager_runtime_configuration.h" +#endif #if defined(RFFPLL_PRESENT) #if defined(SL_CLOCK_MANAGER_RFFPLL_BAND) && (SL_CLOCK_MANAGER_RFFPLL_BAND == 7) @@ -76,6 +81,12 @@ #define HFXO_CRYSTSAL_SHARING_PRS_CHANNEL 0 #endif +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +#define FUNCTION_SCOPE +#else +#define FUNCTION_SCOPE static +#endif + /******************************************************************************* ****************************** TYPEDEFS *********************************** ******************************************************************************/ @@ -93,8 +104,10 @@ typedef struct { ************************** LOCAL VARIABLES ******************************** ******************************************************************************/ -#if defined(RFFPLL_PRESENT) \ - && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) +#if defined(RFFPLL_PRESENT) \ + && defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1) \ + && (SL_CLOCK_MANAGER_RFFPLL_CUSTOM_BAND == 0) \ + && !((SL_CLOCK_MANAGER_RFFPLL_BAND == 7) && defined(RADIO_CONFIG_RFFPLL_CONFIG_PRESENT)) // Table of possible radio frequency bands and their associated settings. static clock_manager_rffpll_config_t rffpll_band_config_39MHz[] = { { 97500000, 23, 7, 115 }, // Band 450 MHz @@ -107,6 +120,16 @@ static clock_manager_rffpll_config_t rffpll_band_config_39MHz[] = { }; #endif +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +uint32_t SLI_CLOCK_MANAGER_HFXO_MODE = SL_CLOCK_MANAGER_HFXO_MODE; +uint32_t SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY = SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY_DEFAULT; +uint32_t SLI_CLOCK_MANAGER_HFRCO_BAND = SL_CLOCK_MANAGER_HFRCO_BAND; +#endif + /******************************************************************************* *************************** LOCAL FUNCTIONS ******************************* ******************************************************************************/ @@ -116,26 +139,33 @@ static clock_manager_rffpll_config_t rffpll_band_config_39MHz[] = { /***************************************************************************//** * Initializes HFXO Oscillator. ******************************************************************************/ -static sl_status_t init_hfxo(void) +FUNCTION_SCOPE sl_status_t init_hfxo(void) { CMU_HFXOInit_TypeDef clock_manager_hfxo_init = CMU_HFXOINIT_DEFAULT; - clock_manager_hfxo_init.mode = SL_CLOCK_MANAGER_HFXO_MODE >> _HFXO_CFG_MODE_SHIFT; + clock_manager_hfxo_init.mode = SLI_CLOCK_MANAGER_HFXO_MODE >> _HFXO_CFG_MODE_SHIFT; - if (SL_CLOCK_MANAGER_HFXO_MODE == cmuHfxoOscMode_ExternalSine) { + if (SLI_CLOCK_MANAGER_HFXO_MODE == cmuHfxoOscMode_ExternalSine) { clock_manager_hfxo_init = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINE; +#if defined(_HFXO_CFG_MODE_EXTCLKPKDET) + } else if (SLI_CLOCK_MANAGER_HFXO_MODE == cmuHfxoOscMode_ExternalSinePkDet) { + clock_manager_hfxo_init = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINEPKDET; +#endif } int ctune = -1; +#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 #if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) // Use HFXO tuning value from DEVINFO if available (PCB modules) if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; } +#endif #endif // Use HFXO tuning value from MFG token in UD page if not already set - if ((ctune == -1) && (MFG_CTUNE_HFXO_VAL != 0xFFFF)) { + if ((ctune == -1) + && (MFG_CTUNE_HFXO_VAL <= (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT))) { ctune = MFG_CTUNE_HFXO_VAL; } @@ -159,6 +189,12 @@ static sl_status_t init_hfxo(void) clock_manager_hfxo_init.ctuneXoAna = ctune; } +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) + if (SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY != SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY_DEFAULT) { + clock_manager_hfxo_init.ctuneFixAna = SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY; + } +#endif + #if defined(SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN) && (SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_EN == 1) // Set port and pin. GPIO_Port_TypeDef port = SL_CLOCK_MANAGER_HFXO_CRYSTAL_SHARING_GPIO_PORT; @@ -238,6 +274,12 @@ static sl_status_t init_hfxo(void) CMU_HFXOInit(&clock_manager_hfxo_init); CMU_HFXOPrecisionSet(SL_CLOCK_MANAGER_HFXO_PRECISION); +#if defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) + if (SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY == SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY_DEFAULT) { + SLI_CLOCK_MANAGER_HFXO_CTUNE_FIXED_STEADY = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEFIXANA_MASK) >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT; + } +#endif + return SL_STATUS_OK; } #endif @@ -247,16 +289,29 @@ static sl_status_t init_hfxo(void) /***************************************************************************//** * Initializes LFXO Oscillator. ******************************************************************************/ -static sl_status_t init_lfxo(void) +FUNCTION_SCOPE sl_status_t init_lfxo(void) { CMU_LFXOInit_TypeDef clock_manager_lfxo_init = CMU_LFXOINIT_DEFAULT; clock_manager_lfxo_init.mode = SL_CLOCK_MANAGER_LFXO_MODE >> _LFXO_CFG_MODE_SHIFT; clock_manager_lfxo_init.timeout = SL_CLOCK_MANAGER_LFXO_TIMEOUT >> _LFXO_CFG_TIMEOUT_SHIFT; + clock_manager_lfxo_init.capTune = 0xFF; - if (MFG_CTUNE_LFXO_VAL != 0xFF) { +#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 +#if defined(_DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) + // Use LFXO tuning value from DEVINFO if available (PCB modules) + if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_LFXOCALVAL_MASK) == _DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { + clock_manager_lfxo_init.capTune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK; + } +#endif +#endif + + if ((clock_manager_lfxo_init.capTune == 0xFF) + && (MFG_CTUNE_LFXO_VAL <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT))) { clock_manager_lfxo_init.capTune = MFG_CTUNE_LFXO_VAL; - } else { + } + + if (clock_manager_lfxo_init.capTune == 0xFF) { clock_manager_lfxo_init.capTune = SL_CLOCK_MANAGER_LFXO_CTUNE; } @@ -267,11 +322,42 @@ static sl_status_t init_lfxo(void) } #endif +/***************************************************************************//** + * Initializes Clock Input CLKIN0. + ******************************************************************************/ +static sl_status_t init_clkin0(void) +{ + sl_status_t status = SL_STATUS_OK; + +#if (defined(SL_CLOCK_MANAGER_SYSCLK_SOURCE) && (SL_CLOCK_MANAGER_SYSCLK_SOURCE == CMU_SYSCLKCTRL_CLKSEL_CLKIN0)) \ + || (defined(SL_CLOCK_MANAGER_DPLL_REFCLK) && (SL_CLOCK_MANAGER_DPLL_REFCLK == CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0)) \ + || (defined(SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE) && (SL_CLOCK_MANAGER_EM01GRPBCLK_SOURCE == CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0)) + +#if !defined(SL_CLOCK_MANAGER_CLKIN0_PORT) || !defined(SL_CLOCK_MANAGER_CLKIN0_PIN) +#error "Invalid configuration: CLKIN0 reference can't be use without configuring SL_CLOCK_MANAGER_CLKIN0 with a valid port and pin." +#endif + + sl_gpio_t clkin0_gpio = { SL_CLOCK_MANAGER_CLKIN0_PORT, SL_CLOCK_MANAGER_CLKIN0_PIN }; + + status = sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO); + if (status != SL_STATUS_OK) { + return status; + } + + status = sl_gpio_set_pin_mode(&clkin0_gpio, SL_GPIO_MODE_INPUT, false); + if (status == SL_STATUS_OK) { + GPIO->CMUROUTE.CLKIN0ROUTE = (clkin0_gpio.port << _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT) + | (clkin0_gpio.pin << _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT); + } +#endif + return status; +} + #if defined(HFRCO_PRESENT) /***************************************************************************//** * Initializes HFRCODPLL Oscillator. ******************************************************************************/ -static sl_status_t init_hfrcodpll(void) +FUNCTION_SCOPE sl_status_t init_hfrcodpll(void) { #if defined(SL_CLOCK_MANAGER_HFRCO_DPLL_EN) && (SL_CLOCK_MANAGER_HFRCO_DPLL_EN == 1) CMU_DPLLInit_TypeDef clock_manager_dpll_init = { @@ -328,7 +414,7 @@ static sl_status_t init_hfrcodpll(void) return SL_STATUS_FAIL; } #else - CMU_HFRCODPLLBandSet(SL_CLOCK_MANAGER_HFRCO_BAND); + CMU_HFRCODPLLBandSet(SLI_CLOCK_MANAGER_HFRCO_BAND); #endif return SL_STATUS_OK; } @@ -338,7 +424,7 @@ static sl_status_t init_hfrcodpll(void) /***************************************************************************//** * Initializes HFRCOEM23 Oscillator. ******************************************************************************/ -static sl_status_t init_hfrcoem23(void) +FUNCTION_SCOPE sl_status_t init_hfrcoem23(void) { CMU_HFRCOEM23BandSet(SL_CLOCK_MANAGER_HFRCOEM23_BAND); @@ -350,13 +436,16 @@ static sl_status_t init_hfrcoem23(void) /***************************************************************************//** * Initializes LFRCO Oscillator. ******************************************************************************/ -static sl_status_t init_lfrco(void) +FUNCTION_SCOPE sl_status_t init_lfrco(void) { #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) CMU_ClockEnable(cmuClock_LFRCO, true); #endif #if defined(PLFRCO_PRESENT) +#if !(defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1)) + EFM_ASSERT(SL_CLOCK_MANAGER_LFRCO_PRECISION != cmuPrecisionHigh); +#endif CMU_LFRCOSetPrecision(SL_CLOCK_MANAGER_LFRCO_PRECISION); #endif @@ -369,7 +458,7 @@ static sl_status_t init_lfrco(void) /***************************************************************************//** * Initializes RFFPLL Oscillator. ******************************************************************************/ -static sl_status_t init_rffpll(void) +FUNCTION_SCOPE sl_status_t init_rffpll(void) { CMU_RFFPLL_Init_TypeDef rffpll_init = CMU_RFFPLL_DEFAULT; @@ -413,7 +502,7 @@ static sl_status_t init_rffpll(void) /***************************************************************************//** * Initializes USBPLL Oscillator. ******************************************************************************/ -static sl_status_t init_usbpll(void) +FUNCTION_SCOPE sl_status_t init_usbpll(void) { CMU_USBPLL_Init_TypeDef usbpll_config; uint32_t hfxo_freq = SystemHFXOClockGet(); @@ -464,7 +553,7 @@ static sl_status_t init_usbpll(void) /***************************************************************************//** * Initializes Clock branches. ******************************************************************************/ -static sl_status_t init_clock_branches(void) +FUNCTION_SCOPE sl_status_t init_clock_branches(void) { // Initialize SYSCLK clock branch. #if defined(SL_CLOCK_MANAGER_SYSCLK_SOURCE) @@ -474,10 +563,10 @@ static sl_status_t init_clock_branches(void) #else CLOCK_MANAGER_CLOCK_SELECT_SET(SYSCLK, SL_CLOCK_MANAGER_SYSCLK_SOURCE); #endif + sli_em_cmu_SYSCLKInitPostClockSelect(false); CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~(_CMU_SYSCLKCTRL_HCLKPRESC_MASK | _CMU_SYSCLKCTRL_PCLKPRESC_MASK)) | SL_CLOCK_MANAGER_HCLK_DIVIDER | SL_CLOCK_MANAGER_PCLK_DIVIDER; - sli_em_cmu_SYSCLKInitPostClockSelect(false); #else EFM_ASSERT(false); #endif @@ -691,6 +780,15 @@ static sl_status_t init_clock_branches(void) CLOCK_MANAGER_CLOCK_SELECT_SET(VDAC0CLK, SL_CLOCK_MANAGER_VDAC0CLK_SOURCE); #else EFM_ASSERT(false); +#endif + + // Initialize VDAC1 clock branch. +#if VDAC_COUNT > 1 +#if defined(SL_CLOCK_MANAGER_VDAC1CLK_SOURCE) + CLOCK_MANAGER_CLOCK_SELECT_SET(VDAC1CLK, SL_CLOCK_MANAGER_VDAC1CLK_SOURCE); +#else + EFM_ASSERT(false); +#endif #endif #endif @@ -708,6 +806,13 @@ sl_status_t sli_clock_manager_hal_init(void) { sl_status_t status; +#if defined(SYSRTC_PRESENT) + status = sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_SYSRTC0); + if (status != SL_STATUS_OK) { + return status; + } +#endif + // Initialize Oscillators #if defined(LFXO_PRESENT) \ && defined(SL_CLOCK_MANAGER_LFXO_EN) && (SL_CLOCK_MANAGER_LFXO_EN == 1) @@ -725,6 +830,11 @@ sl_status_t sli_clock_manager_hal_init(void) } #endif + status = init_clkin0(); + if (status != SL_STATUS_OK) { + return status; + } + #if defined(HFRCO_PRESENT) status = init_hfrcodpll(); if (status != SL_STATUS_OK) { diff --git a/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_hal.h b/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_hal.h index 9736d187a..695ab8772 100644 --- a/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_hal.h +++ b/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_hal.h @@ -45,6 +45,7 @@ sl_status_t sli_clock_manager_hal_runtime_init(void); /***************************************************************************//** * Gets frequency of given oscillator. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_clock_manager_hal_get_oscillator_frequency(sl_oscillator_t oscillator, uint32_t *frequency); @@ -57,6 +58,7 @@ sl_status_t sli_clock_manager_hal_get_oscillator_precision(sl_oscillator_t oscil /***************************************************************************//** * Gets frequency of given clock branch. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sli_clock_manager_hal_get_clock_branch_frequency(sl_clock_branch_t clock_branch, uint32_t *frequency); @@ -172,6 +174,21 @@ sl_status_t sli_clock_manager_hal_get_sysclk_source(sl_oscillator_t *source); ******************************************************************************/ sl_status_t sli_clock_manager_hal_wait_usbpll(void); +/***************************************************************************//** + * Updates QSPI clock and reference clock. + * + * @note This API is not thread-safe and should therefore not be called + across multiple tasks. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_hal_update_qspi_clk(sl_oscillator_t oscillator); + +/***************************************************************************//** + * Gets QSPI clock source. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_CLOCK_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +sl_status_t sli_clock_manager_get_current_qspi_clk(sl_oscillator_t *oscillator); + #ifdef __cplusplus } #endif diff --git a/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_init_hal.h b/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_init_hal.h index b03796e8a..04562b245 100644 --- a/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_init_hal.h +++ b/simplicity_sdk/platform/service/clock_manager/src/sli_clock_manager_init_hal.h @@ -33,6 +33,8 @@ #include "sl_status.h" #include "sl_clock_manager_tree_config.h" +#include "sl_clock_manager_oscillator_config.h" +#include "em_device.h" #ifdef __cplusplus extern "C" { @@ -71,6 +73,28 @@ extern "C" { #define CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE_NX(clock_branch, clock_source) CMU_##clock_branch##CTRL_CLKSEL##clock_source #define CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE(clock_branch, clock_source) CLOCK_MANAGER_GET_DEFAULT_CLOCK_SOURCE_NX(clock_branch, clock_source) +#if !defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) +#define SLI_CLOCK_MANAGER_HFXO_MODE SL_CLOCK_MANAGER_HFXO_MODE +#define SLI_CLOCK_MANAGER_HFRCO_BAND SL_CLOCK_MANAGER_HFRCO_BAND +#endif // #if !defined(SLI_CLOCK_MANAGER_RUNTIME_CONFIGURATION) + +#if defined(SL_CLOCK_MANAGER_SOCPLL_EN) && (SL_CLOCK_MANAGER_SOCPLL_EN == 1) +#if defined(SL_CLOCK_MANAGER_SOCPLL_ADVANCED_SETTINGS) && (SL_CLOCK_MANAGER_SOCPLL_ADVANCED_SETTINGS == 0) +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) || (defined(SL_CLOCK_MANAGER_HFXO_EN) && (SL_CLOCK_MANAGER_HFXO_EN == 1)) +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK SOCPLL_CTRL_REFCLKSEL_REF_HFXO +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ SL_CLOCK_MANAGER_HFXO_FREQ +#else +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK SOCPLL_CTRL_REFCLKSEL_REF_HFRCO +#define SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ SL_CLOCK_MANAGER_HFRCO_BAND +#endif +#define SL_CLOCK_MANAGER_SOCPLL_FRACTIONAL_EN 1 +// SOCPLL Formula: SOCPLL_FREQ = REFCLK_FREQ * (DIVN+2 + DIVF/1024) / 6 +// SL_CLOCK_MANAGER_SOCPLL_DIVN is rounded down and SL_CLOCK_MANAGER_SOCPLL_DIVF is rounded to the closest integer. +#define SL_CLOCK_MANAGER_SOCPLL_DIVN (6ULL * SL_CLOCK_MANAGER_SOCPLL_FREQ / SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ - 2ULL) +#define SL_CLOCK_MANAGER_SOCPLL_DIVF ((6ULL * 1024ULL * SL_CLOCK_MANAGER_SOCPLL_FREQ + SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ / 2ULL) / SL_CLOCK_MANAGER_SOCPLL_REFCLK_FREQ - 1024ULL * (SL_CLOCK_MANAGER_SOCPLL_DIVN + 2ULL)) +#endif +#endif + /******************************************************************************* ****************************** PROTOTYPES ********************************** ******************************************************************************/ diff --git a/simplicity_sdk/platform/service/device_init/config/s2/sdid235/20dbm/sl_device_init_dcdc_config.h b/simplicity_sdk/platform/service/device_init/config/s2/sdid235/20dbm/sl_device_init_dcdc_config.h index 059d2d670..e6cb4eeba 100644 --- a/simplicity_sdk/platform/service/device_init/config/s2/sdid235/20dbm/sl_device_init_dcdc_config.h +++ b/simplicity_sdk/platform/service/device_init/config/s2/sdid235/20dbm/sl_device_init_dcdc_config.h @@ -50,8 +50,8 @@ // DCDC PFMX Mode Peak Current Setting <0-15> // -// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT -#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 6 +// Default: DCDC_PFMXCTRL_IPKVAL_LOAD100MA +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 9 // <<< end of configuration section >>> diff --git a/simplicity_sdk/platform/service/device_init/config/s2/sdid240/boost/sl_device_init_dcdc_config.h b/simplicity_sdk/platform/service/device_init/config/s2/sdid240/boost/sl_device_init_dcdc_config.h new file mode 100644 index 000000000..3c5b88aa0 --- /dev/null +++ b/simplicity_sdk/platform/service/device_init/config/s2/sdid240/boost/sl_device_init_dcdc_config.h @@ -0,0 +1,64 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +#include "sl_device_init_dcdc.h" +#include "em_device.h" + +// DC/DC Type +#define SL_DEVICE_INIT_DCDC_TYPE SL_DEVICE_INIT_DCDC_TYPE_BOOST + +// <<< Use Configuration Wizard in Context Menu >>> + +// DC/DC Boost Settings + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// DC/DC Boost Output Voltage Settings +// 1.8 V +// 1.9 V +// 2.0 V +// 2.1 V +// 2.2 V +// 2.3 V +// 2.4 V +// Default: emuDcdcBoostOutputVoltage_1v8 +#define SL_DEVICE_INIT_DCDC_BOOST_OUTPUT emuDcdcBoostOutputVoltage_1v8 + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/simplicity_sdk/platform/service/device_init/config/s2/sdid240/buck/sl_device_init_dcdc_config.h b/simplicity_sdk/platform/service/device_init/config/s2/sdid240/buck/sl_device_init_dcdc_config.h new file mode 100644 index 000000000..0098f76eb --- /dev/null +++ b/simplicity_sdk/platform/service/device_init/config/s2/sdid240/buck/sl_device_init_dcdc_config.h @@ -0,0 +1,58 @@ +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +#include "sl_device_init_dcdc.h" +#include "em_device.h" + +// DC/DC Type +#define SL_DEVICE_INIT_DCDC_TYPE SL_DEVICE_INIT_DCDC_TYPE_BUCK + +// <<< Use Configuration Wizard in Context Menu >>> + +// DC/DC Buck Settings + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/simplicity_sdk/platform/service/device_init/config/s2/sdid240/sl_device_init_hfxo_config.h b/simplicity_sdk/platform/service/device_init/config/s2/sdid240/sl_device_init_hfxo_config.h index 78b14ee25..e144a3140 100644 --- a/simplicity_sdk/platform/service/device_init/config/s2/sdid240/sl_device_init_hfxo_config.h +++ b/simplicity_sdk/platform/service/device_init/config/s2/sdid240/sl_device_init_hfxo_config.h @@ -41,8 +41,8 @@ #define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal // Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 // HFXO precision in PPM <0-65535> // Default: 50 diff --git a/simplicity_sdk/platform/service/device_init/src/sl_device_init_dcdc_s2.c b/simplicity_sdk/platform/service/device_init/src/sl_device_init_dcdc_s2.c index 5227eb41b..d00ada8c5 100644 --- a/simplicity_sdk/platform/service/device_init/src/sl_device_init_dcdc_s2.c +++ b/simplicity_sdk/platform/service/device_init/src/sl_device_init_dcdc_s2.c @@ -50,6 +50,9 @@ sl_status_t sl_device_init_dcdc(void) #else // SL_DEVICE_INIT_DCDC_TYPE #if SL_DEVICE_INIT_DCDC_ENABLE EMU_DCDCBoostInit_TypeDef dcdcBoostInit = EMU_DCDCBOOSTINIT_DEFAULT; +#if defined(_DCDC_CTRL_DVDDBSTPRG_MASK) + dcdcBoostInit.outputVoltage = SL_DEVICE_INIT_DCDC_BOOST_OUTPUT; +#endif EMU_DCDCBoostInit(&dcdcBoostInit); #endif #endif //SL_DEVICE_INIT_DCDC_TYPE diff --git a/simplicity_sdk/platform/service/device_init/src/sl_device_init_hfxo_s2.c b/simplicity_sdk/platform/service/device_init/src/sl_device_init_hfxo_s2.c index a65242be7..1f9c32ace 100644 --- a/simplicity_sdk/platform/service/device_init/src/sl_device_init_hfxo_s2.c +++ b/simplicity_sdk/platform/service/device_init/src/sl_device_init_hfxo_s2.c @@ -47,11 +47,13 @@ sl_status_t sl_device_init_hfxo(void) int ctune = -1; +#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 #if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) // Use HFXO tuning value from DEVINFO if available (PCB modules) if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; } +#endif #endif // Use HFXO tuning value from MFG token in UD page if not already set diff --git a/simplicity_sdk/platform/service/device_init/src/sl_device_init_lfxo_s2.c b/simplicity_sdk/platform/service/device_init/src/sl_device_init_lfxo_s2.c index 8096521e0..ed3264516 100644 --- a/simplicity_sdk/platform/service/device_init/src/sl_device_init_lfxo_s2.c +++ b/simplicity_sdk/platform/service/device_init/src/sl_device_init_lfxo_s2.c @@ -45,11 +45,13 @@ sl_status_t sl_device_init_lfxo(void) int ctune = -1; +#ifndef _SILICON_LABS_32B_SERIES_2_CONFIG_9 #if defined(_DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) // Use LFXO tuning value from DEVINFO if available (PCB modules) if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_LFXOCALVAL_MASK) == _DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK; } +#endif #endif // Use LFXO tuning value from MFG token in UD page if not already set diff --git a/simplicity_sdk/platform/service/device_init/src/sl_device_init_rffpll_s2.c b/simplicity_sdk/platform/service/device_init/src/sl_device_init_rffpll_s2.c index 5a38e452f..454c64bcc 100644 --- a/simplicity_sdk/platform/service/device_init/src/sl_device_init_rffpll_s2.c +++ b/simplicity_sdk/platform/service/device_init/src/sl_device_init_rffpll_s2.c @@ -55,6 +55,8 @@ typedef struct { uint8_t divider_n; // Feedback divider N. } sl_device_init_rffpll_config_t; +#if (SL_DEVICE_INIT_RFFPLL_CUSTOM_BAND == 0) \ + && !((SL_DEVICE_INIT_RFFPLL_BAND == 7) && defined(RADIO_CONFIG_RFFPLL_CONFIG_PRESENT)) // Table of possible radio frequency bands and their associated settings. sl_device_init_rffpll_config_t rffpll_band_config_39MHz[] = { { 97500000, 23, 7, 115 }, // Band 450 MHz @@ -65,6 +67,7 @@ sl_device_init_rffpll_config_t rffpll_band_config_39MHz[] = { { 97500000, 23, 7, 115 }, // Band 928 MHz { 97500000, 20, 6, 100 } // Band 9xx MHz (covers from 901 to 928 MHz) }; +#endif sl_status_t sl_device_init_rffpll(void) { diff --git a/simplicity_sdk/platform/service/device_manager/clocks/sl_device_clock_efr32xg29.c b/simplicity_sdk/platform/service/device_manager/clocks/sl_device_clock_efr32xg29.c new file mode 100644 index 000000000..978304ac9 --- /dev/null +++ b/simplicity_sdk/platform/service/device_manager/clocks/sl_device_clock_efr32xg29.c @@ -0,0 +1,319 @@ +/**************************************************************************//** + * @file + * @brief Device Manager Clock Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include "em_device.h" +#include "sl_device_clock.h" + +/***************************************************************************//** + * @addtogroup device_clock Device Manager Clock + * @{ + ******************************************************************************/ + +#if defined(_CMU_CLKEN1_ACMP0_SHIFT) +/// Define ACMP0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ACMP0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ACMP0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_AGC_SHIFT) +/// Define AGC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_AGC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_AGC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_AMUXCP0_SHIFT) +/// Define AMUXCP0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_AMUXCP0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_AMUXCP0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_BUFC_SHIFT) +/// Define BUFC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_BUFC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_BUFC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_BURAM_SHIFT) +/// Define BURAM peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_BURAM_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_BURAM_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_BURTC_SHIFT) +/// Define BURTC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_BURTC_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_BURTC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_CRYPTOACC_SHIFT) +/// Define CRYPTOACC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_CRYPTOACC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_CRYPTOACC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_SEMAILBOXHOST_SHIFT) +/// Define SEMAILBOX peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SEMAILBOX_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SEMAILBOXHOST_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_DMEM_SHIFT) +/// Define DMEM peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_DMEM_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_DMEM_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_DCDC_SHIFT) +/// Define DCDC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_DCDC_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_DCDC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_DPLL0_SHIFT) +/// Define DPLL0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_DPLL0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_DPLL0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_ETAMPDET_SHIFT) +/// Define ETAMPDET peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ETAMPDET_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ETAMPDET_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_EUSART0_SHIFT) +/// Define EUSART0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_EUSART0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_EUSART0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_EUSART1_SHIFT) +/// Define EUSART1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_EUSART1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_EUSART1_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_FRC_SHIFT) +/// Define FRC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_FRC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_FRC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_FSRCO_SHIFT) +/// Define FSRCO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_FSRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_FSRCO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_GPCRC_SHIFT) +/// Define GPCRC0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_GPCRC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_GPCRC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_GPIO_SHIFT) +/// Define GPIO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_GPIO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_GPIO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_HFRCO0_SHIFT) +/// Define HFRCO0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_HFRCO0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFRCO0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_HFXO0_SHIFT) +/// Define HFXO0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_HFXO0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_HFXO0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_I2C0_SHIFT) +/// Define I2C0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_I2C0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_I2C0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_I2C1_SHIFT) +/// Define I2C1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_I2C1_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_I2C1_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_IADC0_SHIFT) +/// Define IADC0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_IADC0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_IADC0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_ICACHE0_SHIFT) +/// Define ICACHE0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ICACHE0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_ICACHE0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_IFADCDEBUG_SHIFT) +/// Define IFADCDEBUG peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_IFADCDEBUG_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_IFADCDEBUG_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LDMA_SHIFT) +/// Define LDMA0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LDMA0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LDMA_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LDMAXBAR_SHIFT) +/// Define LDMAXBAR0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LDMAXBAR0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LDMAXBAR_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LETIMER0_SHIFT) +/// Define LETIMER0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LETIMER0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LETIMER0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LFRCO_SHIFT) +/// Define LFRCO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LFRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LFRCO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_LFXO_SHIFT) +/// Define LFXO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_LFXO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_LFXO_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_MODEM_SHIFT) +/// Define MODEM peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_MODEM_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MODEM_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_MSC_SHIFT) +/// Define MSC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_MSC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_MSC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_PDM_SHIFT) +/// Define PDM peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_PDM_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_PDM_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_PRORTC_SHIFT) +/// Define PRORTC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_PRORTC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_PRORTC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_PROTIMER_SHIFT) +/// Define PROTIMER peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_PROTIMER_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_PROTIMER_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_PRS_SHIFT) +/// Define PRS peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_PRS_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_PRS_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RAC_SHIFT) +/// Define RAC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RAC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RAC_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_RADIOAES_SHIFT) +/// Define RADIOAES peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RADIOAES_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_RADIOAES_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RDMAILBOX0_SHIFT) +/// Define RDMAILBOX0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RDMAILBOX0_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RDMAILBOX0_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RDMAILBOX1_SHIFT) +/// Define RDMAILBOX1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RDMAILBOX1_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RDMAILBOX1_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RDSCRATCHPAD_SHIFT) +/// Define RDSCRATCHPAD peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RDSCRATCHPAD_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RDSCRATCHPAD_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RFCRC_SHIFT) +/// Define RFCRC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RFCRC_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFCRC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_RFSENSE_SHIFT) +/// Define RFSENSE peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RFSENSE_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_RFSENSE_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_RTCC_SHIFT) +/// Define RTCC peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_RTCC_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_RTCC_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_SMU_SHIFT) +/// Define SMU peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SMU_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SMU_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_SYNTH_SHIFT) +/// Define SYNTH peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SYNTH_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_SYNTH_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_SYSCFG_SHIFT) +/// Define SYSCFG peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_SYSCFG_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_SYSCFG_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER0_SHIFT) +/// Define TIMER0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER1_SHIFT) +/// Define TIMER1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER1_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER1_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER2_SHIFT) +/// Define TIMER2 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER2_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER2_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_TIMER3_SHIFT) +/// Define TIMER3 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER3_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_TIMER3_SHIFT; +#endif + +#if defined(_CMU_CLKEN1_TIMER4_SHIFT) +/// Define TIMER4 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_TIMER4_VALUE = (BUS_CLOCK_CLKEN1 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN1_TIMER4_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_ULFRCO_SHIFT) +/// Define ULFRCO peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_ULFRCO_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_ULFRCO_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_USART0_SHIFT) +/// Define USART0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_USART0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_USART0_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_USART1_SHIFT) +/// Define USART1 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_USART1_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_USART1_SHIFT; +#endif + +#if defined(_CMU_CLKEN0_WDOG0_SHIFT) +/// Define WDOG0 peripheral bus clock value. +const uint32_t SL_BUS_CLOCK_WDOG0_VALUE = (BUS_CLOCK_CLKEN0 << _BUS_CLOCK_CLKENX_SHIFT) | _CMU_CLKEN0_WDOG0_SHIFT; +#endif + +/** @} (end addtogroup device_clock) */ diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg21.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg21.c index 686886ff5..beceaf784 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg21.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg21.c @@ -247,6 +247,13 @@ const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST .bus_clock = SL_BUS_CLOCK_INVALID }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg22.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg22.c index a32bf2a66..db1440bcc 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg22.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg22.c @@ -233,6 +233,13 @@ const sl_peripheral_val_t sl_peripheral_val_rtcc = { .base = RTCC_BASE, .bus_clock = SL_BUS_CLOCK_RTCC }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg23.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg23.c index 05b140f0a..ce4e5ca16 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg23.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg23.c @@ -310,6 +310,13 @@ const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST .bus_clock = SL_BUS_CLOCK_SEMAILBOX }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c index 286122e03..c053f3dda 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg24.c @@ -282,6 +282,13 @@ const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST .bus_clock = SL_BUS_CLOCK_SEMAILBOX }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg25.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg25.c index 90d4dcb9f..ca2432c7f 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg25.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg25.c @@ -331,6 +331,13 @@ const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST .bus_clock = SL_BUS_CLOCK_SEMAILBOX }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg26.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg26.c index 27aaff27c..891e0d01b 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg26.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg26.c @@ -331,6 +331,13 @@ const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST .bus_clock = SL_BUS_CLOCK_SEMAILBOX }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg27.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg27.c index a18a78456..7ca98e261 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg27.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg27.c @@ -254,6 +254,13 @@ const sl_peripheral_val_t sl_peripheral_val_sepuf = { .base = SEPUF_APBCFG_BASE, .bus_clock = SL_BUS_CLOCK_INVALID }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg28.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg28.c index 0399fa38f..ea2d7a050 100644 --- a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg28.c +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg28.c @@ -317,6 +317,13 @@ const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST .bus_clock = SL_BUS_CLOCK_SEMAILBOX }; #endif +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + #if defined(SYSCFG_BASE) // Define peripheral SYSCFG. const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, diff --git a/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg29.c b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg29.c new file mode 100644 index 000000000..891219517 --- /dev/null +++ b/simplicity_sdk/platform/service/device_manager/devices/sl_device_peripheral_hal_efr32xg29.c @@ -0,0 +1,341 @@ +/**************************************************************************//** + * @file + * @brief Device Manager Peripheral Definition + ****************************************************************************** + * # License + * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include "em_device.h" +#include "sl_device_peripheral.h" +#include "sl_device_clock.h" + +/***************************************************************************//** + * @addtogroup device_peripheral Device Abstraction Peripheral + * @{ + ******************************************************************************/ + +#if defined(ACMP0_BASE) +/// Define peripheral ACMP0. +const sl_peripheral_val_t sl_peripheral_val_acmp0 = { .base = ACMP0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_ACMP0 }; +#endif + +#if defined(BURAM_BASE) +/// Define peripheral BURAM. +const sl_peripheral_val_t sl_peripheral_val_buram = { .base = BURAM_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_BURAM }; +#endif + +#if defined(BURTC_BASE) +/// Define peripheral BURTC. +const sl_peripheral_val_t sl_peripheral_val_burtc = { .base = BURTC_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM4GRPACLK, + .bus_clock = SL_BUS_CLOCK_BURTC }; +#endif + +#if defined(CMU_BASE) +/// Define peripheral CMU. +const sl_peripheral_val_t sl_peripheral_val_cmu = { .base = CMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; +#endif + +#if defined(SEMAILBOX_HOST_BASE) +/// Define peripheral SEMAILBOX. +const sl_peripheral_val_t sl_peripheral_val_semailbox = { .base = SEMAILBOX_HOST_BASE, + .clk_branch = SL_CLOCK_BRANCH_HCLK, + .bus_clock = SL_BUS_CLOCK_SEMAILBOX }; +#endif + +#if defined(DCDC_BASE) +/// Define peripheral DCDC. +const sl_peripheral_val_t sl_peripheral_val_dcdc = { .base = DCDC_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_DCDC }; +#endif + +#if defined(DPLL0_BASE) +/// Define peripheral DPLL0. +const sl_peripheral_val_t sl_peripheral_val_dpll0 = { .base = DPLL0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_DPLL0 }; +#endif + +#if defined(EMU_BASE) +/// Define peripheral EMU. +const sl_peripheral_val_t sl_peripheral_val_emu = { .base = EMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; +#endif + +#if defined(ETAMPDET_BASE) +/// Define peripheral ETAMPDET. +const sl_peripheral_val_t sl_peripheral_val_etampdet = { .base = ETAMPDET_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM4GRPACLK, + .bus_clock = SL_BUS_CLOCK_ETAMPDET }; +#endif + +#if defined(EUSART0_BASE) +/// Define peripheral EUSART0. +const sl_peripheral_val_t sl_peripheral_val_eusart0 = { .base = EUSART0_BASE, + .clk_branch = SL_CLOCK_BRANCH_EUSART0CLK, + .bus_clock = SL_BUS_CLOCK_EUSART0 }; +#endif + +#if defined(EUSART1_BASE) +/// Define peripheral EUSART1. +const sl_peripheral_val_t sl_peripheral_val_eusart1 = { .base = EUSART1_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPCCLK, + .bus_clock = SL_BUS_CLOCK_EUSART1 }; +#endif + +#if defined(FSRCO_BASE) +/// Define peripheral FSRCO. +const sl_peripheral_val_t sl_peripheral_val_fsrco = { .base = FSRCO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_FSRCO }; +#endif + +#if defined(GPCRC_BASE) +/// Define peripheral GPCRC0. +const sl_peripheral_val_t sl_peripheral_val_gpcrc0 = { .base = GPCRC_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_GPCRC0 }; +#endif + +#if defined(GPIO_BASE) +/// Define peripheral GPIO. +const sl_peripheral_val_t sl_peripheral_val_gpio = { .base = GPIO_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_GPIO }; +#endif + +#if defined(HFRCO0_BASE) +/// Define peripheral HFRCO0. +const sl_peripheral_val_t sl_peripheral_val_hfrco0 = { .base = HFRCO0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_HFRCO0 }; +#endif + +#if defined(HFXO0_BASE) +/// Define peripheral HFXO0. +const sl_peripheral_val_t sl_peripheral_val_hfxo0 = { .base = HFXO0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_HFXO0 }; +#endif + +#if defined(I2C0_BASE) +/// Define peripheral I2C0. +const sl_peripheral_val_t sl_peripheral_val_i2c0 = { .base = I2C0_BASE, + .clk_branch = SL_CLOCK_BRANCH_LSPCLK, + .bus_clock = SL_BUS_CLOCK_I2C0 }; +#endif + +#if defined(I2C1_BASE) +/// Define peripheral I2C1. +const sl_peripheral_val_t sl_peripheral_val_i2c1 = { .base = I2C1_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_I2C1 }; +#endif + +#if defined(IADC0_BASE) +/// Define peripheral IADC0. +const sl_peripheral_val_t sl_peripheral_val_iadc0 = { .base = IADC0_BASE, + .clk_branch = SL_CLOCK_BRANCH_IADCCLK, + .bus_clock = SL_BUS_CLOCK_IADC0 }; +#endif + +#if defined(ICACHE0_BASE) +/// Define peripheral ICACHE0. +const sl_peripheral_val_t sl_peripheral_val_icache0 = { .base = ICACHE0_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_ICACHE0 }; +#endif + +#if defined(LDMA_BASE) +/// Define peripheral LDMA0. +const sl_peripheral_val_t sl_peripheral_val_ldma0 = { .base = LDMA_BASE, + .clk_branch = SL_CLOCK_BRANCH_HCLK, + .bus_clock = SL_BUS_CLOCK_LDMA0 }; +#endif + +#if defined(LDMAXBAR_BASE) +/// Define peripheral LDMAXBAR0. +const sl_peripheral_val_t sl_peripheral_val_ldmaxbar0 = { .base = LDMAXBAR_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_LDMAXBAR0 }; +#endif + +#if defined(LETIMER0_BASE) +/// Define peripheral LETIMER0. +const sl_peripheral_val_t sl_peripheral_val_letimer0 = { .base = LETIMER0_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM23GRPACLK, + .bus_clock = SL_BUS_CLOCK_LETIMER0 }; +#endif + +#if defined(LFRCO_BASE) +/// Define peripheral LFRCO. +const sl_peripheral_val_t sl_peripheral_val_lfrco = { .base = LFRCO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_LFRCO }; +#endif + +#if defined(LFXO_BASE) +/// Define peripheral LFXO. +const sl_peripheral_val_t sl_peripheral_val_lfxo = { .base = LFXO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_LFXO }; +#endif + +#if defined(MSC_BASE) +/// Define peripheral MSC. +const sl_peripheral_val_t sl_peripheral_val_msc = { .base = MSC_BASE, + .clk_branch = SL_CLOCK_BRANCH_HCLK, + .bus_clock = SL_BUS_CLOCK_MSC }; +#endif + +#if defined(PDM_BASE) +/// Define peripheral PDM. +const sl_peripheral_val_t sl_peripheral_val_pdm = { .base = PDM_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPBCLK, + .bus_clock = SL_BUS_CLOCK_PDM }; +#endif + +#if defined(PRORTC_BASE) +/// Define peripheral PRORTC. +const sl_peripheral_val_t sl_peripheral_val_prortc = { .base = PRORTC_BASE, + .clk_branch = SL_CLOCK_BRANCH_PRORTCCLK, + .bus_clock = SL_BUS_CLOCK_PRORTC }; +#endif + +#if defined(PRS_BASE) +/// Define peripheral PRS. +const sl_peripheral_val_t sl_peripheral_val_prs = { .base = PRS_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_PRS }; +#endif + +#if defined(RADIOAES_BASE) +/// Define peripheral RADIOAES. +const sl_peripheral_val_t sl_peripheral_val_radioaes = { .base = RADIOAES_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_RADIOAES }; +#endif + +#if defined(RTCC_BASE) +/// Define peripheral RTCC. +const sl_peripheral_val_t sl_peripheral_val_rtcc = { .base = RTCC_BASE, + .clk_branch = SL_CLOCK_BRANCH_RTCCCLK, + .bus_clock = SL_BUS_CLOCK_RTCC }; +#endif + +#if defined(DMEM_BASE) +/// Define peripheral DMEM. +const sl_peripheral_val_t sl_peripheral_val_dmem = { .base = DMEM_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_DMEM }; +#endif + +#if defined(SMU_BASE) +// Define peripheral SMU. +const sl_peripheral_val_t sl_peripheral_val_smu = { .base = SMU_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SMU }; +#endif + +#if defined(SYSCFG_BASE) +/// Define peripheral SYSCFG. +const sl_peripheral_val_t sl_peripheral_val_syscfg = { .base = SYSCFG_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_SYSCFG }; +#endif + +#if defined(TIMER0_BASE) +/// Define peripheral TIMER0. +const sl_peripheral_val_t sl_peripheral_val_timer0 = { .base = TIMER0_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER0 }; +#endif + +#if defined(TIMER1_BASE) +/// Define peripheral TIMER1. +const sl_peripheral_val_t sl_peripheral_val_timer1 = { .base = TIMER1_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER1 }; +#endif + +#if defined(TIMER2_BASE) +/// Define peripheral TIMER2. +const sl_peripheral_val_t sl_peripheral_val_timer2 = { .base = TIMER2_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER2 }; +#endif + +#if defined(TIMER3_BASE) +/// Define peripheral TIMER3. +const sl_peripheral_val_t sl_peripheral_val_timer3 = { .base = TIMER3_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER3 }; +#endif + +#if defined(TIMER4_BASE) +/// Define peripheral TIMER4. +const sl_peripheral_val_t sl_peripheral_val_timer4 = { .base = TIMER4_BASE, + .clk_branch = SL_CLOCK_BRANCH_EM01GRPACLK, + .bus_clock = SL_BUS_CLOCK_TIMER4 }; +#endif + +#if defined(ULFRCO_BASE) +/// Define peripheral ULFRCO. +const sl_peripheral_val_t sl_peripheral_val_ulfrco = { .base = ULFRCO_BASE, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_ULFRCO }; +#endif + +#if defined(USART0_BASE) +/// Define peripheral USART0. +const sl_peripheral_val_t sl_peripheral_val_usart0 = { .base = USART0_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_USART0 }; +#endif + +#if defined(USART1_BASE) +/// Define peripheral USART1. +const sl_peripheral_val_t sl_peripheral_val_usart1 = { .base = USART1_BASE, + .clk_branch = SL_CLOCK_BRANCH_PCLK, + .bus_clock = SL_BUS_CLOCK_USART1 }; +#endif + +#if defined(WDOG0_BASE) +/// Define peripheral WDOG0. +const sl_peripheral_val_t sl_peripheral_val_wdog0 = { .base = WDOG0_BASE, + .clk_branch = SL_CLOCK_BRANCH_WDOG0CLK, + .bus_clock = SL_BUS_CLOCK_WDOG0 }; +#endif + +/** @} (end addtogroup device_peripheral) */ diff --git a/simplicity_sdk/platform/service/device_manager/inc/sl_device_clock.h b/simplicity_sdk/platform/service/device_manager/inc/sl_device_clock.h index ef4bb5606..e35bb2688 100644 --- a/simplicity_sdk/platform/service/device_manager/inc/sl_device_clock.h +++ b/simplicity_sdk/platform/service/device_manager/inc/sl_device_clock.h @@ -34,6 +34,10 @@ #include "sl_enum.h" #include +#if defined(DEVICE_CLOCK_INTERNAL_PRESENT) +#include "sli_device_clock_internal.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -65,7 +69,8 @@ SL_ENUM(sl_oscillator_t) { SL_OSCILLATOR_LFXO, ///< LFXO Oscillator SL_OSCILLATOR_LFRCO, ///< LFRCO Oscillator SL_OSCILLATOR_ULFRCO, ///< ULFRCO Oscillator - SL_OSCILLATOR_CLKIN0 ///< CLKIN0 Oscillator + SL_OSCILLATOR_CLKIN0, ///< CLKIN0 Oscillator + SL_OSCILLATOR_FLPLL ///< FLPLL Oscillator }; /// Clock Branches @@ -92,7 +97,7 @@ SL_ENUM(sl_clock_branch_t) { SL_CLOCK_BRANCH_SYSRTCCLK, ///< SYSRTCCLK Clock Branch SL_CLOCK_BRANCH_EUART0CLK, ///< EUART0CLK Clock Branch SL_CLOCK_BRANCH_EUSART0CLK, ///< EUSART0CLK Clock Branch - SL_CLOCK_BRANCH_DPLLREFCLK, ///< EUSART0CLK Clock Branch + SL_CLOCK_BRANCH_DPLLREFCLK, ///< DPLLREFCLK Clock Branch SL_CLOCK_BRANCH_I2C0CLK, ///< I2C0CLK Clock Branch SL_CLOCK_BRANCH_LCDCLK, ///< LCDCLK Clock Branch SL_CLOCK_BRANCH_PIXELRZCLK, ///< PIXELRZCLK Clock Branch @@ -103,6 +108,7 @@ SL_ENUM(sl_clock_branch_t) { SL_CLOCK_BRANCH_VDAC0CLK, ///< VDAC0CLK Clock Branch SL_CLOCK_BRANCH_VDAC1CLK, ///< VDAC1CLK Clock Branch SL_CLOCK_BRANCH_USB0CLK, ///< USB0CLK Clock Branch + SL_CLOCK_BRANCH_FLPLLREFCLK, ///< FLPLLREFCLK Clock Branch SL_CLOCK_BRANCH_INVALID ///< INVALID Clock Branch }; @@ -293,6 +299,9 @@ SL_ENUM(sl_clock_branch_t) { /// Define for LFXO peripheral bus clock pointer. #define SL_BUS_CLOCK_LFXO (&SL_BUS_CLOCK_LFXO_VALUE) +/// Define for LPWAES peripheral bus clock pointer. +#define SL_BUS_CLOCK_LPWAES (&SL_BUS_CLOCK_LPWAES_VALUE) + /// Define for LPW0PORTAL peripheral bus clock pointer. #define SL_BUS_CLOCK_LPW0PORTAL (&SL_BUS_CLOCK_LPW0PORTAL_VALUE) @@ -618,6 +627,9 @@ extern const uint32_t SL_BUS_CLOCK_LFRCO_VALUE; // External declaration for LFXO peripheral bus clock value. extern const uint32_t SL_BUS_CLOCK_LFXO_VALUE; +// External declaration for LPWAES peripheral bus clock value. +extern const uint32_t SL_BUS_CLOCK_LPWAES_VALUE; + // External declaration for LPW0PORTAL peripheral bus clock value. extern const uint32_t SL_BUS_CLOCK_LPW0PORTAL_VALUE; diff --git a/simplicity_sdk/platform/service/device_manager/inc/sl_device_gpio.h b/simplicity_sdk/platform/service/device_manager/inc/sl_device_gpio.h index 3a70c5e18..e97615160 100644 --- a/simplicity_sdk/platform/service/device_manager/inc/sl_device_gpio.h +++ b/simplicity_sdk/platform/service/device_manager/inc/sl_device_gpio.h @@ -69,6 +69,57 @@ SL_ENUM(sl_gpio_port_t) { SL_GPIO_PORT_K = 10, }; +/// GPIO Pin Modes. +SL_ENUM(sl_gpio_mode_t) { + /// Input disabled. Pull-up if DOUT is set. + SL_GPIO_MODE_DISABLED, + + /// Input enabled. Filter if DOUT is set. + SL_GPIO_MODE_INPUT, + + /// Input enabled. DOUT determines pull direction. + SL_GPIO_MODE_INPUT_PULL, + + /// Input enabled with filter. DOUT determines pull direction. + SL_GPIO_MODE_INPUT_PULL_FILTER, + + /// Push-pull output. + SL_GPIO_MODE_PUSH_PULL, + + /// Push-pull using alternate control. + SL_GPIO_MODE_PUSH_PULL_ALTERNATE, + + /// Wired-or output. + SL_GPIO_MODE_WIRED_OR, + + /// Wired-or output with pull-down. + SL_GPIO_MODE_WIRED_OR_PULL_DOWN, + + /// Open-drain output. + SL_GPIO_MODE_WIRED_AND, + + /// Open-drain output with filter. + SL_GPIO_MODE_WIRED_AND_FILTER, + + /// Open-drain output with pull-up. + SL_GPIO_MODE_WIRED_AND_PULLUP, + + /// Open-drain output with filter and pull-up. + SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER, + + /// Open-drain output using alternate control. + SL_GPIO_MODE_WIRED_AND_ALTERNATE, + + /// Open-drain output using alternate control with filter. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER, + + /// Open-drain output using alternate control with pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP, + + /// Open-drain output using alternate control with filter and pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER, +}; + /// GPIO Interrupt Configuration flags. SL_ENUM(sl_gpio_interrupt_flag_t) { /// No edge configured. @@ -90,40 +141,6 @@ SL_ENUM(sl_gpio_interrupt_flag_t) { #define SL_GPIO_INTERRUPT_UNAVAILABLE (-1) -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? GPIO_PORT_A_PIN_COUNT \ - : (port) == 1 ? GPIO_PORT_B_PIN_COUNT \ - : (port) == 2 ? GPIO_PORT_C_PIN_COUNT \ - : (port) == 3 ? GPIO_PORT_D_PIN_COUNT \ - : (port) == 4 ? GPIO_PORT_E_PIN_COUNT \ - : (port) == 5 ? GPIO_PORT_F_PIN_COUNT \ - : (port) == 6 ? GPIO_PORT_G_PIN_COUNT \ - : (port) == 7 ? GPIO_PORT_H_PIN_COUNT \ - : (port) == 8 ? GPIO_PORT_I_PIN_COUNT \ - : (port) == 9 ? GPIO_PORT_J_PIN_COUNT \ - : (port) == 10 ? GPIO_PORT_K_PIN_COUNT \ - : 0) - -#define _GPIO_PORT_MASK(port) ( \ - ((int)port) == 0 ? GPIO_PORT_A_PIN_MASK \ - : ((int)port) == 1 ? GPIO_PORT_B_PIN_MASK \ - : ((int)port) == 2 ? GPIO_PORT_C_PIN_MASK \ - : ((int)port) == 3 ? GPIO_PORT_D_PIN_MASK \ - : ((int)port) == 4 ? GPIO_PORT_E_PIN_MASK \ - : ((int)port) == 5 ? GPIO_PORT_F_PIN_MASK \ - : ((int)port) == 6 ? GPIO_PORT_G_PIN_MASK \ - : ((int)port) == 7 ? GPIO_PORT_H_PIN_MASK \ - : ((int)port) == 8 ? GPIO_PORT_I_PIN_MASK \ - : ((int)port) == 9 ? GPIO_PORT_J_PIN_MASK \ - : ((int)port) == 10 ? GPIO_PORT_K_PIN_MASK \ - : 0UL) - -/// Validation of port. -#define SL_GPIO_PORT_IS_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) - -/// Validation of port and pin. -#define SL_GPIO_PORT_PIN_IS_VALID(port, pin) ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) - /// Validation of flag. #define SL_GPIO_FLAG_IS_VALID(flag) ((flag == SL_GPIO_INTERRUPT_NO_EDGE) || (flag == SL_GPIO_INTERRUPT_RISING_EDGE) || (flag == SL_GPIO_INTERRUPT_FALLING_EDGE) || (flag == SL_GPIO_INTERRUPT_RISING_FALLING_EDGE)) @@ -491,42 +508,6 @@ SL_ENUM(sl_gpio_interrupt_flag_t) { #define PK30 (&pk30) #define PK31 (&pk31) -/// Define for port specific pin mask -#define GPIO_PORT_A_PIN_MASK (gpio_port_a_pin_mask) -#define GPIO_PORT_B_PIN_MASK (gpio_port_b_pin_mask) -#define GPIO_PORT_C_PIN_MASK (gpio_port_c_pin_mask) -#define GPIO_PORT_D_PIN_MASK (gpio_port_d_pin_mask) -#define GPIO_PORT_E_PIN_MASK (gpio_port_e_pin_mask) -#define GPIO_PORT_F_PIN_MASK (gpio_port_f_pin_mask) -#define GPIO_PORT_G_PIN_MASK (gpio_port_g_pin_mask) -#define GPIO_PORT_H_PIN_MASK (gpio_port_h_pin_mask) -#define GPIO_PORT_I_PIN_MASK (gpio_port_i_pin_mask) -#define GPIO_PORT_J_PIN_MASK (gpio_port_j_pin_mask) -#define GPIO_PORT_K_PIN_MASK (gpio_port_k_pin_mask) - -/// Define for port specific pin count -#define GPIO_PORT_A_PIN_COUNT (gpio_port_a_pin_count) -#define GPIO_PORT_B_PIN_COUNT (gpio_port_b_pin_count) -#define GPIO_PORT_C_PIN_COUNT (gpio_port_c_pin_count) -#define GPIO_PORT_D_PIN_COUNT (gpio_port_d_pin_count) -#define GPIO_PORT_E_PIN_COUNT (gpio_port_e_pin_count) -#define GPIO_PORT_F_PIN_COUNT (gpio_port_f_pin_count) -#define GPIO_PORT_G_PIN_COUNT (gpio_port_g_pin_count) -#define GPIO_PORT_H_PIN_COUNT (gpio_port_h_pin_count) -#define GPIO_PORT_I_PIN_COUNT (gpio_port_i_pin_count) -#define GPIO_PORT_J_PIN_COUNT (gpio_port_j_pin_count) -#define GPIO_PORT_K_PIN_COUNT (gpio_port_k_pin_count) - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -/// Highest GPIO port number. -#define GPIO_PORT_MAX 3 - -/// Highest GPIO pin number. -#define GPIO_PIN_MAX 15 - -/// @endcond - /******************************************************************************* ******************************* STRUCTS *********************************** ******************************************************************************/ @@ -678,30 +659,6 @@ extern const sl_gpio_t pd30; extern const sl_gpio_t pd31; extern const sl_gpio_t pd32; -extern const uint32_t gpio_port_a_pin_mask; -extern const uint32_t gpio_port_b_pin_mask; -extern const uint32_t gpio_port_c_pin_mask; -extern const uint32_t gpio_port_d_pin_mask; -extern const uint32_t gpio_port_e_pin_mask; -extern const uint32_t gpio_port_f_pin_mask; -extern const uint32_t gpio_port_g_pin_mask; -extern const uint32_t gpio_port_h_pin_mask; -extern const uint32_t gpio_port_i_pin_mask; -extern const uint32_t gpio_port_j_pin_mask; -extern const uint32_t gpio_port_k_pin_mask; - -extern const uint32_t gpio_port_a_pin_count; -extern const uint32_t gpio_port_b_pin_count; -extern const uint32_t gpio_port_c_pin_count; -extern const uint32_t gpio_port_d_pin_count; -extern const uint32_t gpio_port_e_pin_count; -extern const uint32_t gpio_port_f_pin_count; -extern const uint32_t gpio_port_g_pin_count; -extern const uint32_t gpio_port_h_pin_count; -extern const uint32_t gpio_port_i_pin_count; -extern const uint32_t gpio_port_j_pin_count; -extern const uint32_t gpio_port_k_pin_count; - /// @endcond /** @} (end addtogroup device_gpio) */ diff --git a/simplicity_sdk/platform/service/device_manager/inc/sl_device_peripheral.h b/simplicity_sdk/platform/service/device_manager/inc/sl_device_peripheral.h index 873d65ff5..d9f4eb822 100644 --- a/simplicity_sdk/platform/service/device_manager/inc/sl_device_peripheral.h +++ b/simplicity_sdk/platform/service/device_manager/inc/sl_device_peripheral.h @@ -30,7 +30,12 @@ #ifndef SL_DEVICE_PERIPHERAL_H #define SL_DEVICE_PERIPHERAL_H -#include "sl_device_clock.h" +#include "sl_device_peripheral_types.h" +#include "sl_code_classification.h" + +#if defined(DEVICE_PERIPHERAL_INTERNAL_PRESENT) +#include "sli_device_peripheral_internal.h" +#endif #ifdef __cplusplus extern "C" { @@ -207,6 +212,9 @@ extern "C" { /// Define pointer to LFXO peripheral structure. #define SL_PERIPHERAL_LFXO (&sl_peripheral_val_lfxo) +/// Define pointer to LPWAES peripheral structure. +#define SL_PERIPHERAL_LPWAES (&sl_peripheral_val_lpwaes) + /// Define pointer to LPW0PORTAL peripheral structure. #define SL_PERIPHERAL_LPW0PORTAL (&sl_peripheral_val_lpw0portal) @@ -273,6 +281,9 @@ extern "C" { /// Define pointer to SEPUF peripheral structure. #define SL_PERIPHERAL_SEPUF (&sl_peripheral_val_sepuf) +/// Define pointer to SMU peripheral structure. +#define SL_PERIPHERAL_SMU (&sl_peripheral_val_smu) + /// Define pointer to SOCPLL0 peripheral structure. #define SL_PERIPHERAL_SOCPLL0 (&sl_peripheral_val_socpll0) @@ -353,16 +364,6 @@ extern "C" { // ---------------------------------------------------------------------------- // TYPEDEFS -/// Define peripheral structure. -typedef struct sl_peripheral { - uint32_t base; ///< Peripheral base address. - sl_clock_branch_t clk_branch; ///< Peripheral clock branch. - sl_bus_clock_t bus_clock; ///< Peripheral bus clock. -} sl_peripheral_val_t; - -/// Define peripheral typedef. -typedef const sl_peripheral_val_t* sl_peripheral_t; - /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN #if defined(__ICCARM__) @@ -487,6 +488,9 @@ typedef struct lfrco_typedef LFRCO_TypeDef; // Declare peripheral structure for LFXO. typedef struct lfxo_typedef LFXO_TypeDef; +// Declare peripheral structure for LPWAES. +typedef struct lpwaes_typedef LPWAES_TypeDef; + // Declare peripheral structure for LPW0PORTAL. typedef struct lpw0portal_typedef LPW0PORTAL_TypeDef; @@ -547,6 +551,9 @@ typedef struct seportal_typedef SEPORTAL_TypeDef; // Declare peripheral structure for SEPUF_APBCFG. typedef struct sepuf_apbcfg_typedef SEPUF_APBCFG_TypeDef; +// Declare peripheral structure for SMU. +typedef struct smu_typedef SMU_TypeDef; + // Declare peripheral structure for SOCPLL. typedef struct socpll_typedef SOCPLL_TypeDef; @@ -748,6 +755,9 @@ extern const sl_peripheral_val_t sl_peripheral_val_lfrco; // External declaration for LFXO peripheral structure. extern const sl_peripheral_val_t sl_peripheral_val_lfxo; +// External declaration for LPWAES peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_lpwaes; + // External declaration for LPW0PORTAL peripheral structure. extern const sl_peripheral_val_t sl_peripheral_val_lpw0portal; @@ -814,6 +824,9 @@ extern const sl_peripheral_val_t sl_peripheral_val_seportal; // External declaration for SEPUF peripheral structure. extern const sl_peripheral_val_t sl_peripheral_val_sepuf; +// External declaration for SMU peripheral structure. +extern const sl_peripheral_val_t sl_peripheral_val_smu; + // External declaration for SOCPLL0 peripheral structure. extern const sl_peripheral_val_t sl_peripheral_val_socpll0; @@ -1362,6 +1375,18 @@ inline LFXO_TypeDef *sl_device_peripheral_lfxo_get_base_addr(const sl_peripheral return (LFXO_TypeDef *)peripheral->base; } +/***************************************************************************//** + * The base address getter for LPWAES. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline LPWAES_TypeDef *sl_device_peripheral_lpwaes_get_base_addr(const sl_peripheral_t peripheral) +{ + return (LPWAES_TypeDef *)peripheral->base; +} + /***************************************************************************//** * The base address getter for LPW0PORTAL. * @@ -1602,6 +1627,18 @@ inline SEPUF_APBCFG_TypeDef *sl_device_peripheral_sepuf_apbcfg_get_base_addr(con return (SEPUF_APBCFG_TypeDef *)peripheral->base; } +/***************************************************************************//** + * The base address getter for SMU. + * + * @param peripheral A pointer to peripheral. + * + * @return The base address of the peripheral. + ******************************************************************************/ +inline SMU_TypeDef *sl_device_peripheral_smu_get_base_addr(const sl_peripheral_t peripheral) +{ + return (SMU_TypeDef *)peripheral->base; +} + /***************************************************************************//** * The base address getter for SOCPLL. * @@ -1765,6 +1802,7 @@ inline WDOG_TypeDef *sl_device_peripheral_wdog_get_base_addr(const sl_peripheral * * @return The clock branch of the peripheral. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_DEVICE_PERIPHERAL, SL_CODE_CLASS_TIME_CRITICAL) inline sl_clock_branch_t sl_device_peripheral_get_clock_branch(const sl_peripheral_t peripheral) { return peripheral->clk_branch; diff --git a/simplicity_sdk/platform/service/device_manager/gpios/sl_device_gpio_common.c b/simplicity_sdk/platform/service/device_manager/inc/sl_device_peripheral_types.h similarity index 65% rename from simplicity_sdk/platform/service/device_manager/gpios/sl_device_gpio_common.c rename to simplicity_sdk/platform/service/device_manager/inc/sl_device_peripheral_types.h index 0b9ead28c..eea9d62ea 100644 --- a/simplicity_sdk/platform/service/device_manager/gpios/sl_device_gpio_common.c +++ b/simplicity_sdk/platform/service/device_manager/inc/sl_device_peripheral_types.h @@ -1,6 +1,6 @@ /**************************************************************************//** * @file - * @brief Device Manager Clock Definition + * @brief Device Manager API Definition ****************************************************************************** * # License * Copyright 2024 Silicon Laboratories, Inc. www.silabs.com @@ -27,23 +27,39 @@ * 3. This notice may not be removed or altered from any source distribution. * *****************************************************************************/ +#ifndef SL_DEVICE_PERIPHERAL_TYPES_H +#define SL_DEVICE_PERIPHERAL_TYPES_H -#include "em_device.h" -#include "sl_device_gpio.h" +#include "sl_device_clock.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif /***************************************************************************//** - * @addtogroup device_gpio Device Manager GPIO + * @addtogroup device_peripheral Device Abstraction Peripheral + * * @{ ******************************************************************************/ -const uint32_t gpio_port_a_pin_mask = GPIO_PA_MASK; -const uint32_t gpio_port_b_pin_mask = GPIO_PB_MASK; -const uint32_t gpio_port_c_pin_mask = GPIO_PC_MASK; -const uint32_t gpio_port_d_pin_mask = GPIO_PD_MASK; +// ---------------------------------------------------------------------------- +// TYPEDEFS + +/// Define peripheral structure. +typedef struct sl_peripheral { + uint32_t base; ///< Peripheral base address. + sl_clock_branch_t clk_branch; ///< Peripheral clock branch. + sl_bus_clock_t bus_clock; ///< Peripheral bus clock. +} sl_peripheral_val_t; + +/// Define peripheral typedef. +typedef const sl_peripheral_val_t* sl_peripheral_t; + +/** @} (end addtogroup device_peripheral) */ -const uint32_t gpio_port_a_pin_count = GPIO_PA_COUNT; -const uint32_t gpio_port_b_pin_count = GPIO_PB_COUNT; -const uint32_t gpio_port_c_pin_count = GPIO_PC_COUNT; -const uint32_t gpio_port_d_pin_count = GPIO_PD_COUNT; +#ifdef __cplusplus +} +#endif -/** @} (end addtogroup device_gpio) */ +#endif // SL_DEVICE_PERIPHERAL_TYPES_H diff --git a/simplicity_sdk/platform/service/device_manager/src/sl_device_clock.c b/simplicity_sdk/platform/service/device_manager/src/sl_device_clock.c index 7b15d2a55..f24c3af31 100644 --- a/simplicity_sdk/platform/service/device_manager/src/sl_device_clock.c +++ b/simplicity_sdk/platform/service/device_manager/src/sl_device_clock.c @@ -180,6 +180,9 @@ __WEAK const uint32_t SL_BUS_CLOCK_LFRCO_VALUE = 0xFFFFFFFF; // External declaration for LFXO peripheral bus clock value. __WEAK const uint32_t SL_BUS_CLOCK_LFXO_VALUE = 0xFFFFFFFF; +// External declaration for LPWAES peripheral bus clock value. +__WEAK const uint32_t SL_BUS_CLOCK_LPWAES_VALUE = 0xFFFFFFFF; + // External declaration for LPW0PORTAL peripheral bus clock value. __WEAK const uint32_t SL_BUS_CLOCK_LPW0PORTAL_VALUE = 0xFFFFFFFF; diff --git a/simplicity_sdk/platform/service/device_manager/src/sl_device_gpio.c b/simplicity_sdk/platform/service/device_manager/src/sl_device_gpio.c index e4db507b7..0910971e3 100644 --- a/simplicity_sdk/platform/service/device_manager/src/sl_device_gpio.c +++ b/simplicity_sdk/platform/service/device_manager/src/sl_device_gpio.c @@ -400,30 +400,4 @@ const sl_gpio_t pk29 = { .port = SL_GPIO_PORT_K, .pin = 29 }; const sl_gpio_t pk30 = { .port = SL_GPIO_PORT_K, .pin = 30 }; const sl_gpio_t pk31 = { .port = SL_GPIO_PORT_K, .pin = 31 }; -/// Declarations for port specific pin mask -__WEAK const uint32_t gpio_port_a_pin_mask = 0; -__WEAK const uint32_t gpio_port_b_pin_mask = 0; -__WEAK const uint32_t gpio_port_c_pin_mask = 0; -__WEAK const uint32_t gpio_port_d_pin_mask = 0; -__WEAK const uint32_t gpio_port_e_pin_mask = 0; -__WEAK const uint32_t gpio_port_f_pin_mask = 0; -__WEAK const uint32_t gpio_port_g_pin_mask = 0; -__WEAK const uint32_t gpio_port_h_pin_mask = 0; -__WEAK const uint32_t gpio_port_i_pin_mask = 0; -__WEAK const uint32_t gpio_port_j_pin_mask = 0; -__WEAK const uint32_t gpio_port_k_pin_mask = 0; - -/// Declarations for port specific pin count -__WEAK const uint32_t gpio_port_a_pin_count = 0; -__WEAK const uint32_t gpio_port_b_pin_count = 0; -__WEAK const uint32_t gpio_port_c_pin_count = 0; -__WEAK const uint32_t gpio_port_d_pin_count = 0; -__WEAK const uint32_t gpio_port_e_pin_count = 0; -__WEAK const uint32_t gpio_port_f_pin_count = 0; -__WEAK const uint32_t gpio_port_g_pin_count = 0; -__WEAK const uint32_t gpio_port_h_pin_count = 0; -__WEAK const uint32_t gpio_port_i_pin_count = 0; -__WEAK const uint32_t gpio_port_j_pin_count = 0; -__WEAK const uint32_t gpio_port_k_pin_count = 0; - /** @} (end addtogroup device_gpio) */ diff --git a/simplicity_sdk/platform/service/device_manager/src/sl_device_peripheral.c b/simplicity_sdk/platform/service/device_manager/src/sl_device_peripheral.c index 28cfe2c04..df29a974a 100644 --- a/simplicity_sdk/platform/service/device_manager/src/sl_device_peripheral.c +++ b/simplicity_sdk/platform/service/device_manager/src/sl_device_peripheral.c @@ -285,6 +285,11 @@ __WEAK const sl_peripheral_val_t sl_peripheral_val_lfxo = { .base = 0xFFFFFFFF, .clk_branch = SL_CLOCK_BRANCH_INVALID, .bus_clock = SL_BUS_CLOCK_INVALID }; +// Weak definition of peripheral LPWAES. +__WEAK const sl_peripheral_val_t sl_peripheral_val_lpwaes = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + // Weak definition of peripheral LPW0PORTAL. __WEAK const sl_peripheral_val_t sl_peripheral_val_lpw0portal = { .base = 0xFFFFFFFF, .clk_branch = SL_CLOCK_BRANCH_INVALID, @@ -395,6 +400,11 @@ __WEAK const sl_peripheral_val_t sl_peripheral_val_sepuf = { .base = 0xFFFFFFFF, .clk_branch = SL_CLOCK_BRANCH_INVALID, .bus_clock = SL_BUS_CLOCK_INVALID }; +// Weak definition of peripheral SMU. +__WEAK const sl_peripheral_val_t sl_peripheral_val_smu = { .base = 0xFFFFFFFF, + .clk_branch = SL_CLOCK_BRANCH_INVALID, + .bus_clock = SL_BUS_CLOCK_INVALID }; + // Weak definition of peripheral SOCPLL0. __WEAK const sl_peripheral_val_t sl_peripheral_val_socpll0 = { .base = 0xFFFFFFFF, .clk_branch = SL_CLOCK_BRANCH_INVALID, @@ -642,6 +652,9 @@ extern LFRCO_TypeDef *sl_device_peripheral_lfrco_get_base_addr(const sl_peripher // External base address getter declaration for LFXO. extern LFXO_TypeDef *sl_device_peripheral_lfxo_get_base_addr(const sl_peripheral_t peripheral); +// External base address getter declaration for LPWAES. +extern LPWAES_TypeDef *sl_device_peripheral_lpwaes_get_base_addr(const sl_peripheral_t peripheral); + // External base address getter declaration for LPW0PORTAL. extern LPW0PORTAL_TypeDef *sl_device_peripheral_lpw0portal_get_base_addr(const sl_peripheral_t peripheral); @@ -702,6 +715,9 @@ extern SEPORTAL_TypeDef *sl_device_peripheral_seportal_get_base_addr(const sl_pe // External base address getter declaration for SEPUF_APBCFG. extern SEPUF_APBCFG_TypeDef *sl_device_peripheral_sepuf_apbcfg_get_base_addr(const sl_peripheral_t peripheral); +// External base address getter declaration for SMU. +extern SMU_TypeDef *sl_device_peripheral_smu_get_base_addr(const sl_peripheral_t peripheral); + // External base address getter declaration for SOCPLL. extern SOCPLL_TypeDef *sl_device_peripheral_socpll_get_base_addr(const sl_peripheral_t peripheral); diff --git a/simplicity_sdk/platform/service/hfxo_manager/inc/sl_hfxo_manager.h b/simplicity_sdk/platform/service/hfxo_manager/inc/sl_hfxo_manager.h index b92b86184..b011f7652 100644 --- a/simplicity_sdk/platform/service/hfxo_manager/inc/sl_hfxo_manager.h +++ b/simplicity_sdk/platform/service/hfxo_manager/inc/sl_hfxo_manager.h @@ -114,7 +114,7 @@ sl_status_t sl_hfxo_manager_init(void); * Default values should be enough to wake-up sleepy crystals. Otherwise, * this function can be used. ******************************************************************************/ -sl_status_t sl_hfxo_manager_update_sleepy_xtal_settings(sl_hfxo_manager_sleepy_xtal_settings_t *settings); +sl_status_t sl_hfxo_manager_update_sleepy_xtal_settings(const sl_hfxo_manager_sleepy_xtal_settings_t *settings); /***************************************************************************//** * When this callback function is called, it means that HFXO failed twice in diff --git a/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager.c b/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager.c index 060fac99d..f7fa0434b 100644 --- a/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager.c +++ b/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager.c @@ -120,7 +120,7 @@ sl_status_t sl_hfxo_manager_init(void) * Default values should be enough to wake-up sleepy crystals. Otherwise, * this function can be used. ******************************************************************************/ -sl_status_t sl_hfxo_manager_update_sleepy_xtal_settings(sl_hfxo_manager_sleepy_xtal_settings_t *settings) +sl_status_t sl_hfxo_manager_update_sleepy_xtal_settings(const sl_hfxo_manager_sleepy_xtal_settings_t *settings) { return sli_hfxo_manager_update_sleepy_xtal_settings_hardware(settings); } diff --git a/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c b/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c index f660722a2..a97d01d57 100644 --- a/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c +++ b/simplicity_sdk/platform/service/hfxo_manager/src/sl_hfxo_manager_hal_s2.c @@ -165,10 +165,8 @@ void sli_hfxo_manager_init_hardware(void) /***************************************************************************//** * Updates sleepy crystal settings in specific hardware registers. ******************************************************************************/ -sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(sl_hfxo_manager_sleepy_xtal_settings_t *settings) +sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(const sl_hfxo_manager_sleepy_xtal_settings_t *settings) { - (void)settings; - #if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1) EFM_ASSERT(settings->ana_ctune <= (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)); EFM_ASSERT(settings->core_bias_current <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT)); @@ -178,6 +176,7 @@ sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(sl_hfxo_manage return SL_STATUS_OK; #else + (void)settings; return SL_STATUS_NOT_AVAILABLE; #endif } diff --git a/simplicity_sdk/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h b/simplicity_sdk/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h index 7628703ef..398946262 100644 --- a/simplicity_sdk/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h +++ b/simplicity_sdk/platform/service/hfxo_manager/src/sli_hfxo_manager_internal.h @@ -41,7 +41,7 @@ extern "C" { /***************************************************************************//** * Updates sleepy crystal settings in specific hardware registers. ******************************************************************************/ -sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(sl_hfxo_manager_sleepy_xtal_settings_t *settings); +sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(const sl_hfxo_manager_sleepy_xtal_settings_t *settings); #ifdef __cplusplus } diff --git a/simplicity_sdk/platform/service/interrupt_manager/inc/sl_interrupt_manager.h b/simplicity_sdk/platform/service/interrupt_manager/inc/sl_interrupt_manager.h new file mode 100644 index 000000000..d2979236d --- /dev/null +++ b/simplicity_sdk/platform/service/interrupt_manager/inc/sl_interrupt_manager.h @@ -0,0 +1,404 @@ +/***************************************************************************//** + * @file + * @brief Interrupt Management API to enable and configure interrupts. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_INTERRUPT_MANAGER_H +#define SL_INTERRUPT_MANAGER_H + +#include +#include +#include "sl_core.h" +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup interrupt_manager Interrupt Manager + * @brief Interrupt management service can be used for general interrupt management. + * The source files for Interrupt Manager platform software module are present under + * platform/services/interrupt_manager. + * @details + * ## Overview + * The Interrupt Manager is a service that offers interupt management functions and configurations + * for setting the interrupt vector in RAM, managing the core reset initiation function and + * doing general interrupt management operations. + * + * ## Configuration Options + * + * Some properties of the Interrupt Manager are compile-time configurable. These + * properties are set in the sl_interrupt_manager_s2_config.h file. + * These are the available configuration parameters with default values defined. + * @code + * + * // Put the interrupt vector table in RAM. + * // Set to 1 to put the vector table in RAM. + * // Default: 0 + * #define SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM 0 + * @endcode + * + * @note The SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM configuration is only available + * on series 2. Enabling the S2_INTERRUPTS_IN_RAM configuration will tell the Interrupt Manager + * to copy the interrupt vector table from ROM to RAM and select it as the interrupt table. + * On newer series this feature is always enabled. + * + * ## The API + * + * This section contains brief descriptions of the functions in the API. For more + * information on input and output parameters and return values, + * click on the hyperlinked function names. + * + * @ref sl_interrupt_manager_disable_interrupts and @ref sl_interrupt_manager_enable_interrupts() + * are used to prevent interrupts from executing during a certain timelapse. + * + * @ref sl_interrupt_manager_is_irq_disabled, @ref sl_interrupt_manager_is_irq_blocked + * are used to know the status of an interrupt, either if it's disabled or blocked by one of the + * following reasons: priority masking, disabling or an active interrupt of higher priority + * is executing. + * + * @ref sl_interrupt_manager_is_irq_pending, @ref sl_interrupt_manager_set_irq_pending and + * @ref sl_interrupt_manager_clear_irq_pending + * are used for control and query of external interrupt source pending status. + * + * @ref sl_interrupt_manager_get_irq_priority and @ref sl_interrupt_manager_set_irq_priority + * are used to get or set the priority for a specific interrupt. + * + * ## Priority Stratification + * With the Interrupt Manager service and more generally in the Simplicity SDK, there are multiple distinct + * levels of priority stratification. + * + * Each of these has their own characteristics and purposes. + * For example, the higher priority group is considered to not be able to call kernel, power manager + * or protocol stacks functions. They will only be impacted by critical sections (general interrupt + * disable) but will be above atomic base interrupt priority level for execution. The higher level + * is considered to be between 0 and 2 and the base interrupt priority level is 3. + * + * In the normal priority group you will find most application interrupts and such interrupts will be + * the ones that will make calls to more features such as kernel, power manager and protocol stacks API. + * It is this way because they are less deterministic than the "higher priority interrupts". + * + * + * + *
Priority stratification inside SDK
PriorityPurpose + *
0 - 2 (Highest) + *
    + *
  • No Kernel calls + *
  • No Power Manager calls + *
  • Not maskable by atomic sections + *
+ *
3 - 7 (Normal) + *
    + *
  • kernel calls + *
  • power manager + *
  • protocol stacks API + *
+ *
7 (Lowest) + *
    + *
  • PendSV level of priority + *
+ *
+ * @{ + ******************************************************************************/ + +/// @brief sl_interrupt_manager interrupt handler function. +typedef void(*sl_interrupt_manager_irq_handler_t)(void); + +/***************************************************************************//** + * @brief + * Initialize interrupt controller hardware and initialise vector table + * in RAM. + * + * @note + * The interrupt manager init function will perform the initialization only + * once even if it's called multiple times. + ******************************************************************************/ +void sl_interrupt_manager_init(void); + +/***************************************************************************//** + * @brief + * Reset the cpu core. + ******************************************************************************/ +void sl_interrupt_manager_reset_system(void); + +/***************************************************************************//** + * @brief + * Disable interrupts. + ******************************************************************************/ +void sl_interrupt_manager_disable_interrupts(void); + +/***************************************************************************//** + * @brief + * Enable interrupts. + ******************************************************************************/ +void sl_interrupt_manager_enable_interrupts(void); + +/***************************************************************************//** + * @brief + * Disable interrupt for an interrupt source. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_disable_irq(int32_t irqn); + +/***************************************************************************//** + * @brief + * Enable interrupt for an interrupt source. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_enable_irq(int32_t irqn); + +/***************************************************************************//** + * @brief + * Check if an interrupt is disabled. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * True if the interrupt is disabled. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_disabled(int32_t irqn); + +/***************************************************************************//** + * @brief + * Check if a specific interrupt is blocked. + * + * @note + * The function return true if the IRQ is disabled. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * True if the interrupt is disabled or blocked. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_blocked(int32_t irqn); + +/***************************************************************************//** + * @brief + * Get Pending Interrupt + * + * @note + * Read the pending status of a specified interrupt and returns it status. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * false Interrupt status is not pending. + * true Interrupt status is pending. + ******************************************************************************/ +bool sl_interrupt_manager_is_irq_pending(int32_t irqn); + +/***************************************************************************//** + * @brief + * Set interrupt status to pending. + * + * @note + * Sets an interrupt pending status to true. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + ******************************************************************************/ +void sl_interrupt_manager_set_irq_pending(int32_t irqn); + +/***************************************************************************//** +* @brief +* Clear Pending Interrupt +* +* @details +* Clear an interrupt pending status +* +* @param[in] irqn +* The interrupt number of the interrupt source. +* +* @note +* irqn must not be negative. +*******************************************************************************/ +void sl_interrupt_manager_clear_irq_pending(int32_t irqn); + +/***************************************************************************//** + * @brief + * Set the interrupt handler of an interrupt source. + * + * @note + * This function depends on a RAM based interrupt vector table, i.e. + * SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM must be true. Or the device + * must be Series 3. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @param[in] handler + * The new interrupt handler for the interrupt source. + * + * @return + * The prior interrupt handler for the interrupt source. + ******************************************************************************/ +sl_status_t sl_interrupt_manager_set_irq_handler(int32_t irqn, + sl_interrupt_manager_irq_handler_t handler); + +/***************************************************************************//** + * @brief + * Get the interrupt preemption priority of an interrupt source. + * + * @note + * The number of priority levels is platform dependent. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * The interrupt priority for the interrupt source. + * Value 0 denotes the highest priority. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_irq_priority(int32_t irqn); + +/***************************************************************************//** + * @brief + * Set the interrupt preemption priority of an interrupt source. + * + * @note + * The number of priority levels is platform dependent. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @param[in] priority + * The new interrupt priority for the interrupt source. + * Value 0 denotes the highest priority. + ******************************************************************************/ +void sl_interrupt_manager_set_irq_priority(int32_t irqn, uint32_t priority); + +/***************************************************************************//** + * @brief + * Increase the interrupt preemption priority of an interrupt source. + * relative to the default priority. + * + * @details + * This function is useful to be architecture agnostic with priority values. + * + * Usage: + * new_prio = sl_interrupt_manager_increase_irq_priority_from_default(IRQn, 1); + * + * This will increase the priority of IRQn by 1. + * + * @param[in] irqn + * The irq to change the priority. + * + * @param[in] diff + * The relative difference. + ******************************************************************************/ +void sl_interrupt_manager_increase_irq_priority_from_default(int32_t irqn, uint32_t diff); + +/***************************************************************************//** + * @brief + * Decrease the interrupt preemption priority of an interrupt source + * relative to the default priority. + * + * @details + * This function is useful to be architecture agnostic with priority values. + * + * Usage: + * new_prio = sl_interrupt_manager_decrease_irq_priority_from_default(IRQn, 1); + * + * This will decrease the priority of IRQn by 1. + * + * @param[in] irqn + * The irq to change the priority. + * + * @param[in] diff + * The relative difference. + ******************************************************************************/ +void sl_interrupt_manager_decrease_irq_priority_from_default(int32_t irqn, uint32_t diff); + +/***************************************************************************//** + * @brief + * Get the default interrupt preemption priority value. + * + * @return + * The default priority. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_default_priority(void); + +/***************************************************************************//** + * @brief + * Get the highest interrupt preemption priority value. + * + * @return + * The highest priority value. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_highest_priority(void); + +/***************************************************************************//** + * @brief + * Get the lowest interrupt preemption priority value. + * + * @return + * The lowest priority value. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_lowest_priority(void); + +/***************************************************************************//** + * @brief + * Get the interrupt active status. + * + * @param[in] irqn + * The interrupt number of the interrupt source. + * + * @return + * The interrupt active status. + ******************************************************************************/ +uint32_t sl_interrupt_manager_get_active_irq(int32_t irqn); + +/***************************************************************************//** + * @brief + * Get the current ISR table. + * + * @details + * Depending on the configuration of the Interrupt Manager, this table of + * ISRs may be in RAM or in FLASH, and each ISR may or may not be wrapped by + * enter/exit hooks. + * + * @return + * The current ISR table. + ******************************************************************************/ +sl_interrupt_manager_irq_handler_t* sl_interrupt_manager_get_isr_table(void); + +/** @} (end addtogroup interrupt_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_INTERRUPT_MANAGER_H */ diff --git a/simplicity_sdk/platform/service/memory_manager/inc/sl_memory_manager.h b/simplicity_sdk/platform/service/memory_manager/inc/sl_memory_manager.h index 89d4af3c9..21767abde 100644 --- a/simplicity_sdk/platform/service/memory_manager/inc/sl_memory_manager.h +++ b/simplicity_sdk/platform/service/memory_manager/inc/sl_memory_manager.h @@ -551,12 +551,12 @@ typedef struct { /// @brief Memory block reservation handle. typedef struct { void *block_address; ///< Reserved block base address. - uint32_t block_size; ///< Reserved block size (in bytes). + size_t block_size; ///< Reserved block size (in bytes). } sl_memory_reservation_t; /// @brief Memory pool handle. typedef struct { -#if !defined(SL_MEMORY_POOL_LIGHT) +#if defined(SL_MEMORY_POOL_POWER_AWARE) sl_memory_reservation_t *reservation; ///< Pointer to reservation handle. #else void *block_address; ///< Reserved block base address. @@ -891,6 +891,33 @@ sl_status_t sl_memory_pool_handle_free(sl_memory_pool_t *pool_handle); ******************************************************************************/ uint32_t sl_memory_pool_handle_get_size(void); +/***************************************************************************//** + * Gets the total count of blocks in a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return Total number of blocks. + ******************************************************************************/ +uint32_t sl_memory_pool_get_total_block_count(const sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Gets the count of free blocks in a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return Number of free blocks. + ******************************************************************************/ +uint32_t sl_memory_pool_get_free_block_count(const sl_memory_pool_t *pool_handle); + +/***************************************************************************//** + * Gets the count of used blocks in a memory pool. + * + * @param[in] pool_handle Handle to the memory pool. + * + * @return Number of used blocks. + ******************************************************************************/ +uint32_t sl_memory_pool_get_used_block_count(const sl_memory_pool_t *pool_handle); + /***************************************************************************//** * Populates an sl_memory_heap_info_t{} structure with the current status of * the heap. diff --git a/simplicity_sdk/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h b/simplicity_sdk/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h index 658879102..6e1d06c2e 100644 --- a/simplicity_sdk/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h +++ b/simplicity_sdk/platform/service/memory_manager/profiler/inc/sli_memory_profiler.h @@ -446,7 +446,10 @@ void sli_memory_profiler_track_free(sli_memory_tracker_handle_t tracker_handle, * that have their own (more detailed) owners. If set to * `SLI_INVALID_MEMORY_TRACKER_HANDLE`, the ownership of the innermost * allocation is taken. - * @param[in] ptr Pointer to the allocated memory for which ownership is taken + * @param[in] ptr Pointer to the allocated memory for which ownership is taken. + * The caller may pass a NULL pointer to indicate that the location pointer to + * be @p pc has failed to obtain a valid pointer, for example because a memory + * allocation that was meant to provide the pointer has failed. * @param[in] pc The program counter at the location that took ownership */ void sli_memory_profiler_track_ownership(sli_memory_tracker_handle_t tracker_handle, diff --git a/simplicity_sdk/platform/service/memory_manager/profiler/src/sli_memory_profiler.c b/simplicity_sdk/platform/service/memory_manager/profiler/src/sli_memory_profiler.c index 9d91b1a50..34716c663 100644 --- a/simplicity_sdk/platform/service/memory_manager/profiler/src/sli_memory_profiler.c +++ b/simplicity_sdk/platform/service/memory_manager/profiler/src/sli_memory_profiler.c @@ -39,10 +39,6 @@ #include "SEGGER_RTT.h" #include "sl_rtt_buffer_index.h" -#define SLI_MEMPROF_HEADER_LEN 3 -#define SLI_MEMPROF_OPTIONAL_CHECKSUM_LEN 2 -#define SLI_MEMPROF_OTHER_FIELD_LEN 11 - // The type byte is composed of flag bits and a field for the event ID #define SLI_MEMPROF_EVENT_FLAG_HAS_CHECKSUM ((uint8_t) 0x80) #define SLI_MEMPROF_EVENT_ID_MASK ((uint8_t) 0x0F) @@ -61,29 +57,17 @@ #define SLI_MEMPROF_EVENT_LOG_ID 11 // Version of the binary format for the events we send over RTT -#define SLI_MEMPROF_EVENT_FORMAT_VERSION 8 +#define SLI_MEMPROF_EVENT_FORMAT_VERSION 9 /** * @brief Maximum length of a tracker description string - * - * The maximum length of any event must never exceed the size of the RTT buffer, - * as otherwise we wouldn't be able to write a full event to the buffer - * atomically (we use mode that blocks if there's no space in the RTT buffer). - * The worst case for the description length occurs with - * sli_memprof_evt_create_pool_tracker_t, which has 11 bytes of other fields - * plus 3 bytes of header plus optionally 2 bytes of checksum. Our config allows - * a minimum RTT buffer of 36 bytes, so calculate the description length limit - * from that. */ -#define MAX_TRACKER_DESCRIPTION_LEN (SLI_MEMORY_PROFILER_RTT_BUFFER_SIZE - SLI_MEMPROF_HEADER_LEN - SLI_MEMPROF_OPTIONAL_CHECKSUM_LEN - SLI_MEMPROF_OTHER_FIELD_LEN) +#define MAX_TRACKER_DESCRIPTION_LEN 32 /** * @brief Maximum length of snapshot name - * - * Maximum length is the minimum acceptable buffer length 36 bytes minus the - * 3-byte header and the 2-byte optional checksum. */ -#define MAX_SNAPSHOT_NAME_LEN (SLI_MEMORY_PROFILER_RTT_BUFFER_SIZE - SLI_MEMPROF_HEADER_LEN - SLI_MEMPROF_OPTIONAL_CHECKSUM_LEN) +#define MAX_SNAPSHOT_NAME_LEN 32 /** * @brief Event header structure @@ -98,13 +82,15 @@ typedef __PACKED_STRUCT { * @brief Event structure for the "init" event */ typedef __PACKED_STRUCT { - uint8_t format_version; ///< Version of the event format to verify binary compatibility + sli_memprof_evt_hdr_t header; ///< The common event header + uint8_t format_version; ///< Version of the event format to verify binary compatibility } sli_memprof_evt_init_t; /** * @brief Event structure for the "create_pool_tracker" event */ typedef __PACKED_STRUCT { + sli_memprof_evt_hdr_t header; ///< The common event header uint32_t tracker_handle; ///< Handle of the pool tracker that was created uint32_t ptr; ///< Pointer to the pool block allocated from the parent memory uint32_t size; ///< Size of the pool block allocated from the parent memory @@ -116,6 +102,7 @@ typedef __PACKED_STRUCT { * @brief Event structure for the "create_tracker" event */ typedef __PACKED_STRUCT { + sli_memprof_evt_hdr_t header; ///< The common event header uint32_t tracker_handle; ///< Handle of the tracker that was created uint8_t flags; ///< Reserved for future flag bits. Set to 0 for now. uint8_t description[MAX_TRACKER_DESCRIPTION_LEN]; ///< Short human-readable description @@ -125,6 +112,7 @@ typedef __PACKED_STRUCT { * @brief Event structure for the "describe_tracker" event */ typedef __PACKED_STRUCT { + sli_memprof_evt_hdr_t header; ///< The common event header uint32_t tracker_handle; ///< Handle of the tracker uint8_t description[MAX_TRACKER_DESCRIPTION_LEN]; ///< Short human-readable description } sli_memprof_evt_describe_tracker_t; @@ -133,41 +121,47 @@ typedef __PACKED_STRUCT { * @brief Event structure for the "delete_tracker" event */ typedef __PACKED_STRUCT { - uint32_t tracker_handle; ///< Handle of the pool tracker that was deleted + sli_memprof_evt_hdr_t header; ///< The common event header + uint32_t tracker_handle; ///< Handle of the pool tracker that was deleted } sli_memprof_evt_delete_tracker_t; /** * @brief Event structure for the "track_alloc" event */ typedef __PACKED_STRUCT { - uint32_t tracker_handle; ///< Handle of the tracker - uint32_t ptr; ///< Pointer to the allocated memory or NULL if allocation failed - uint32_t size; ///< The number of bytes allocated, or attempted to allocate - uint32_t pc; ///< The program counter at the location of the owner + sli_memprof_evt_hdr_t header; ///< The common event header + uint32_t tracker_handle; ///< Handle of the tracker + uint32_t ptr; ///< Pointer to the allocated memory or NULL if allocation failed + uint32_t size; ///< The number of bytes allocated, or attempted to allocate + uint32_t pc; ///< The program counter at the location of the owner } sli_memprof_evt_track_alloc_t; /** * @brief Event structure for the "track_realloc" event */ typedef __PACKED_STRUCT { - uint32_t tracker_handle; ///< Handle of the tracker - uint32_t ptr; ///< Pointer to the original memory block - uint32_t realloced_ptr; ///< Pointer to the resized or allocated memory - uint32_t size; ///< The size that the block was reallocated to + sli_memprof_evt_hdr_t header; ///< The common event header + uint32_t tracker_handle; ///< Handle of the tracker + uint32_t ptr; ///< Pointer to the original memory block + uint32_t realloced_ptr; ///< Pointer to the resized or allocated memory + uint32_t size; ///< The size that the block was reallocated to } sli_memprof_evt_track_realloc_t; /** * @brief Event structure for the "track_free" event */ typedef __PACKED_STRUCT { - uint32_t tracker_handle; ///< Handle of the tracker - uint32_t ptr; ///< Pointer to the free'd memory + sli_memprof_evt_hdr_t header; ///< The common event header + uint32_t tracker_handle; ///< Handle of the tracker + uint32_t ptr; ///< Pointer to the free'd memory } sli_memprof_evt_track_free_t; /** * @brief Event structure for the "track_ownership" event */ typedef __PACKED_STRUCT { + sli_memprof_evt_hdr_t header; ///< The common event header + /// Handle of the tracker level at which the ownership is taken. This is used /// to disambiguate in cases where nested allocations start at the same memory /// location, and the caller is specifically taking ownership of one of the @@ -183,6 +177,7 @@ typedef __PACKED_STRUCT { * @brief Event structure for the "take_snapshot" event */ typedef __PACKED_STRUCT { + sli_memprof_evt_hdr_t header; ///< The common event header uint8_t name[MAX_SNAPSHOT_NAME_LEN]; ///< Short human-readable name for the snapshot } sli_memprof_evt_take_snapshot_t; @@ -190,35 +185,14 @@ typedef __PACKED_STRUCT { * @brief Event structure for the "log" event */ typedef __PACKED_STRUCT { - uint32_t log_id; ///< The unique ID of the log - uint32_t arg1; ///< ID-specific argument 1 - uint32_t arg2; ///< ID-specific argument 2 - uint32_t arg3; ///< ID-specific argument 3 - uint32_t pc; ///< The program counter at the location of the log call + sli_memprof_evt_hdr_t header; ///< The common event header + uint32_t log_id; ///< The unique ID of the log + uint32_t arg1; ///< ID-specific argument 1 + uint32_t arg2; ///< ID-specific argument 2 + uint32_t arg3; ///< ID-specific argument 3 + uint32_t pc; ///< The program counter at the location of the log call } sli_memprof_evt_log_t; -/** - * @brief Data structure of memory profiler events - */ -typedef __PACKED_STRUCT { - sli_memprof_evt_hdr_t hdr; ///< Event header - - /** Union of Memory Profiler event types */ - union { - sli_memprof_evt_init_t init; - sli_memprof_evt_create_pool_tracker_t create_pool_tracker; - sli_memprof_evt_create_tracker_t create_tracker; - sli_memprof_evt_describe_tracker_t describe_tracker; - sli_memprof_evt_delete_tracker_t delete_tracker; - sli_memprof_evt_track_alloc_t track_alloc; - sli_memprof_evt_track_realloc_t track_realloc; - sli_memprof_evt_track_free_t track_free; - sli_memprof_evt_track_ownership_t track_ownership; - sli_memprof_evt_take_snapshot_t take_snapshot; - sli_memprof_evt_log_t log; - } data; -} sli_memprof_evt_t; - /** brief Set to true when the Memory Profiler has initialized */ static bool memory_profiler_initialized = false; @@ -230,61 +204,29 @@ static uint8_t next_sequence_number = 0; */ static uint8_t rtt_buffer[SLI_MEMORY_PROFILER_RTT_BUFFER_SIZE]; -/** - * @brief Append Fletcher's checksum - * - * Calculate Fletcher's checksum. Memory Profiler events are short and the - * checksum calculation is guaranteed not to overflow. Hence we can - * efficiently sum and calculate the modulos just once after the loop. - */ -#if SLI_MEMORY_PROFILER_INCLUDE_CHECKSUM -static inline void append_checksum(uint8_t *data, uint32_t data_len) -{ - uint32_t c0 = 0; - uint32_t c1 = 0; - for (uint32_t i = 0; i < data_len; i++) { - c0 = c0 + data[i]; - c1 = c1 + c0; - } - c0 = c0 % 255; - c1 = c1 % 255; - - // Append the checksum - data[data_len++] = (uint8_t) c0; - data[data_len++] = (uint8_t) c1; -} -#endif - /** * @brief Send a memory profiler event over RTT * * This function fills the event header of the specified event structure and * sends the event over the RTT. * - * @param[in] event Pointer to the event structure to fill and send + * @param[in] header Pointer to the header structure. The payload must follow + * right after the header in contiguous memory addresses * @param[in] id ID of the event - * @param[in] payload_len Length of the payload part of the event + * @param[in] event_len Total length of the event header and payload */ -static void send_memory_profiler_event(sli_memprof_evt_t *event, +static void send_memory_profiler_event(sli_memprof_evt_hdr_t *header, uint8_t id, - uint8_t payload_len) + size_t event_len) { // Initialize the header - event->hdr.type = id; - event->hdr.len = payload_len; - event->hdr.seq_num = next_sequence_number++; - uint8_t *data = (uint8_t *) event; - uint32_t data_len = sizeof(event->hdr) + payload_len; - -#if SLI_MEMORY_PROFILER_INCLUDE_CHECKSUM - - append_checksum(data, data_len); - event->hdr.type |= SLI_MEMPROF_EVENT_FLAG_HAS_CHECKSUM; - -#endif // SLI_MEMORY_PROFILER_INCLUDE_CHECKSUM + EFM_ASSERT(event_len >= sizeof(*header)); + header->type = id; + header->len = event_len - sizeof(*header); + header->seq_num = next_sequence_number++; // Send the event - SEGGER_RTT_Write(SL_MEMORY_PROFILER_RTT_BUFFER_INDEX, data, data_len); + SEGGER_RTT_Write(SL_MEMORY_PROFILER_RTT_BUFFER_INDEX, header, event_len); } /** @@ -304,9 +246,9 @@ static void init_memory_profiler() // Send the init event next_sequence_number = 0; - sli_memprof_evt_t init_event; - init_event.data.init.format_version = SLI_MEMPROF_EVENT_FORMAT_VERSION; - send_memory_profiler_event(&init_event, SLI_MEMPROF_EVENT_INIT_ID, sizeof(init_event.data.init)); + sli_memprof_evt_init_t event; + event.format_version = SLI_MEMPROF_EVENT_FORMAT_VERSION; + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_INIT_ID, sizeof(event)); memory_profiler_initialized = true; } @@ -333,23 +275,20 @@ sl_status_t sli_memory_profiler_create_pool_tracker(sli_memory_tracker_handle_t CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.create_pool_tracker.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; - event.data.create_pool_tracker.ptr = (uint32_t) (uintptr_t) ptr; - event.data.create_pool_tracker.size = (uint32_t) size; - event.data.create_pool_tracker.flags = 0; + sli_memprof_evt_create_pool_tracker_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + event.ptr = (uint32_t) (uintptr_t) ptr; + event.size = (uint32_t) size; + event.flags = 0; size_t description_len = 0; if (description != NULL) { description_len = strlen(description); - if (description_len > sizeof(event.data.create_pool_tracker.description)) { - description_len = sizeof(event.data.create_pool_tracker.description); + if (description_len > sizeof(event.description)) { + description_len = sizeof(event.description); } - memcpy(event.data.create_pool_tracker.description, description, description_len); + memcpy(event.description, description, description_len); } - size_t event_len = - sizeof(event.data.create_pool_tracker) - - sizeof(event.data.create_pool_tracker.description) - + description_len; + size_t event_len = sizeof(event) - sizeof(event.description) + description_len; CORE_ENTER_ATOMIC(); @@ -359,7 +298,7 @@ sl_status_t sli_memory_profiler_create_pool_tracker(sli_memory_tracker_handle_t } // Send the event - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_CREATE_POOL_TRACKER_ID, (uint8_t) event_len); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_CREATE_POOL_TRACKER_ID, event_len); CORE_EXIT_ATOMIC(); @@ -373,21 +312,18 @@ sl_status_t sli_memory_profiler_create_tracker(sli_memory_tracker_handle_t track CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.create_tracker.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; - event.data.create_tracker.flags = 0; + sli_memprof_evt_create_tracker_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + event.flags = 0; size_t description_len = 0; if (description != NULL) { description_len = strlen(description); - if (description_len > sizeof(event.data.create_tracker.description)) { - description_len = sizeof(event.data.create_tracker.description); + if (description_len > sizeof(event.description)) { + description_len = sizeof(event.description); } - memcpy(event.data.create_tracker.description, description, description_len); + memcpy(event.description, description, description_len); } - size_t event_len = - sizeof(event.data.create_tracker) - - sizeof(event.data.create_tracker.description) - + description_len; + size_t event_len = sizeof(event) - sizeof(event.description) + description_len; CORE_ENTER_ATOMIC(); @@ -397,7 +333,7 @@ sl_status_t sli_memory_profiler_create_tracker(sli_memory_tracker_handle_t track } // Send the event - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_CREATE_TRACKER_ID, (uint8_t) event_len); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_CREATE_TRACKER_ID, event_len); CORE_EXIT_ATOMIC(); @@ -411,24 +347,21 @@ void sli_memory_profiler_describe_tracker(sli_memory_tracker_handle_t tracker_ha CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.describe_tracker.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + sli_memprof_evt_describe_tracker_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; size_t description_len = 0; if (description != NULL) { description_len = strlen(description); - if (description_len > sizeof(event.data.describe_tracker.description)) { - description_len = sizeof(event.data.describe_tracker.description); + if (description_len > sizeof(event.description)) { + description_len = sizeof(event.description); } - memcpy(event.data.describe_tracker.description, description, description_len); + memcpy(event.description, description, description_len); } - size_t event_len = - sizeof(event.data.describe_tracker) - - sizeof(event.data.describe_tracker.description) - + description_len; + size_t event_len = sizeof(event) - sizeof(event.description) + description_len; // Send the event atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_DESCRIBE_TRACKER_ID, (uint8_t) event_len); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_DESCRIBE_TRACKER_ID, event_len); CORE_EXIT_ATOMIC(); } @@ -438,12 +371,12 @@ void sli_memory_profiler_delete_tracker(sli_memory_tracker_handle_t tracker_hand CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.delete_tracker.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + sli_memprof_evt_delete_tracker_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; // Send the event atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_DELETE_TRACKER_ID, sizeof(event.data.delete_tracker)); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_DELETE_TRACKER_ID, sizeof(event)); CORE_EXIT_ATOMIC(); } @@ -466,15 +399,15 @@ void sli_memory_profiler_track_alloc_with_ownership(sli_memory_tracker_handle_t CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.track_alloc.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; - event.data.track_alloc.ptr = (uint32_t) (uintptr_t) ptr; - event.data.track_alloc.size = (uint32_t) size; - event.data.track_alloc.pc = (uint32_t) (uintptr_t) pc; + sli_memprof_evt_track_alloc_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + event.ptr = (uint32_t) (uintptr_t) ptr; + event.size = (uint32_t) size; + event.pc = (uint32_t) (uintptr_t) pc; // Send atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_TRACK_ALLOC_ID, sizeof(event.data.track_alloc)); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_TRACK_ALLOC_ID, sizeof(event)); CORE_EXIT_ATOMIC(); } @@ -487,15 +420,15 @@ void sli_memory_profiler_track_realloc(sli_memory_tracker_handle_t tracker_handl CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.track_realloc.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; - event.data.track_realloc.ptr = (uint32_t) (uintptr_t) ptr; - event.data.track_realloc.realloced_ptr = (uint32_t) (uintptr_t) realloced_ptr; - event.data.track_realloc.size = (uint32_t) size; + sli_memprof_evt_track_realloc_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + event.ptr = (uint32_t) (uintptr_t) ptr; + event.realloced_ptr = (uint32_t) (uintptr_t) realloced_ptr; + event.size = (uint32_t) size; // Send atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_TRACK_REALLOC_ID, sizeof(event.data.track_realloc)); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_TRACK_REALLOC_ID, sizeof(event)); CORE_EXIT_ATOMIC(); } @@ -506,13 +439,13 @@ void sli_memory_profiler_track_free(sli_memory_tracker_handle_t tracker_handle, CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.track_free.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; - event.data.track_free.ptr = (uint32_t) (uintptr_t) ptr; + sli_memprof_evt_track_free_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + event.ptr = (uint32_t) (uintptr_t) ptr; // Send atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_TRACK_FREE_ID, sizeof(event.data.track_free)); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_TRACK_FREE_ID, sizeof(event)); CORE_EXIT_ATOMIC(); } @@ -524,15 +457,14 @@ void sli_memory_profiler_track_ownership(sli_memory_tracker_handle_t tracker_han CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.track_ownership.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; - event.data.track_ownership.ptr = (uint32_t) (uintptr_t) ptr; - event.data.track_ownership.pc = (uint32_t) (uintptr_t) pc; + sli_memprof_evt_track_ownership_t event; + event.tracker_handle = (uint32_t) (uintptr_t) tracker_handle; + event.ptr = (uint32_t) (uintptr_t) ptr; + event.pc = (uint32_t) (uintptr_t) pc; // Send atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_TRACK_OWNERSHIP_ID, - sizeof(event.data.track_ownership)); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_TRACK_OWNERSHIP_ID, sizeof(event)); CORE_EXIT_ATOMIC(); } @@ -542,21 +474,17 @@ void sli_memory_profiler_take_snapshot(const char *name) CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; + sli_memprof_evt_take_snapshot_t event; size_t name_len = strlen(name); - if (name_len > sizeof(event.data.take_snapshot.name)) { - name_len = sizeof(event.data.take_snapshot.name); + if (name_len > sizeof(event.name)) { + name_len = sizeof(event.name); } - memcpy(event.data.take_snapshot.name, name, name_len); - size_t event_len = - sizeof(event.data.take_snapshot) - - sizeof(event.data.take_snapshot.name) - + name_len; + memcpy(event.name, name, name_len); + size_t event_len = sizeof(event) - sizeof(event.name) + name_len; // Send atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_TAKE_SNAPSHOT_ID, - (uint8_t) event_len); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_TAKE_SNAPSHOT_ID, event_len); CORE_EXIT_ATOMIC(); } @@ -566,16 +494,15 @@ void sli_memory_profiler_log(uint32_t log_id, uint32_t arg1, uint32_t arg2, uint CORE_DECLARE_IRQ_STATE; // Fill the event structure - sli_memprof_evt_t event; - event.data.log.log_id = log_id; - event.data.log.arg1 = arg1; - event.data.log.arg2 = arg2; - event.data.log.arg3 = arg3; - event.data.log.pc = (uint32_t) (uintptr_t) pc; + sli_memprof_evt_log_t event; + event.log_id = log_id; + event.arg1 = arg1; + event.arg2 = arg2; + event.arg3 = arg3; + event.pc = (uint32_t) (uintptr_t) pc; // Send atomically CORE_ENTER_ATOMIC(); - send_memory_profiler_event(&event, SLI_MEMPROF_EVENT_LOG_ID, - sizeof(event.data.log)); + send_memory_profiler_event(&event.header, SLI_MEMPROF_EVENT_LOG_ID, sizeof(event)); CORE_EXIT_ATOMIC(); } diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager.c index 3b71af65d..9a09ff361 100644 --- a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager.c +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager.c @@ -81,7 +81,7 @@ extern char __HeapLimit[]; extern sli_block_metadata_t *sli_free_lt_list_head; extern sli_block_metadata_t *sli_free_st_list_head; extern uint32_t sli_free_blocks_number; -static size_t heap_size; +static size_t heap_used_size; static size_t heap_high_watermark; #if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) bool reserve_no_retention_first = true; @@ -94,8 +94,6 @@ bool reserve_no_retention_first = true; static sli_block_metadata_t *memory_manage_data_alignment(sli_block_metadata_t *current_block_metadata, size_t block_align); -void memory_get_heap_info(sl_memory_heap_info_t *heap_info); - /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ @@ -110,7 +108,7 @@ sl_status_t sl_memory_init(void) { sl_memory_region_t heap_region = sl_memory_get_heap_region(); sli_free_blocks_number = 0u; - heap_size = 0u; + heap_used_size = 0u; heap_high_watermark = 0u; // At first, all general purpose heap available to long-term/short-term blocks. @@ -192,7 +190,6 @@ sl_status_t sl_memory_reserve_no_retention(size_t size, || (SL_MATH_IS_PWR2(align) && (align <= SL_MEMORY_BLOCK_ALIGN_512_BYTES))); - EFM_ASSERT(size != 0u); // Assert block reservation with retention is done prior to any other allocations types. #if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) EFM_ASSERT(reserve_no_retention_first == true); @@ -203,9 +200,19 @@ sl_status_t sl_memory_reserve_no_retention(size_t size, size_t block_size_remaining; size_t size_real; sl_status_t status; + sl_memory_region_t heap_region = sl_memory_get_heap_region(); + + // Verify that the block pointer isn't NULL. + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } *block = NULL; // No block reserved yet. + if ((size == 0) || (size >= heap_region.size)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Adjust size to match the minimum alignment to maximize CPU access performance. size_real = SLI_ALIGN_ROUND_UP(size, SLI_BLOCK_ALLOC_MIN_ALIGN); @@ -239,9 +246,9 @@ sl_status_t sl_memory_reserve_no_retention(size_t size, status = SL_STATUS_ALLOCATION_FAILED; } - heap_size += size_real; - if (heap_size > heap_high_watermark) { - heap_high_watermark = heap_size; + heap_used_size += size_real; + if (heap_used_size > heap_high_watermark) { + heap_high_watermark = heap_used_size; } CORE_EXIT_ATOMIC(); @@ -259,10 +266,17 @@ sl_status_t sl_memory_reserve_no_retention(size_t size, ******************************************************************************/ void *sl_malloc(size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *block_avail = NULL; (void)sl_memory_alloc_advanced(size, SL_MEMORY_BLOCK_ALIGN_DEFAULT, BLOCK_TYPE_LONG_TERM, &block_avail); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block_avail, return_address); +#endif + return block_avail; } @@ -273,10 +287,17 @@ sl_status_t sl_memory_alloc(size_t size, sl_memory_block_type_t type, void **block) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif sl_status_t status; status = sl_memory_alloc_advanced(size, SL_MEMORY_BLOCK_ALIGN_DEFAULT, type, block); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif + return status; } @@ -295,6 +316,10 @@ sl_status_t sl_memory_alloc_advanced(size_t size, sl_memory_block_type_t type, void **block) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + // Check proper alignment characteristics. EFM_ASSERT((align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) || (SL_MATH_IS_PWR2(align) @@ -302,6 +327,7 @@ sl_status_t sl_memory_alloc_advanced(size_t size, sli_block_metadata_t *current_block_metadata = NULL; sli_block_metadata_t *allocated_blk = NULL; + sl_memory_region_t heap_region = sl_memory_get_heap_region(); const sli_block_metadata_t *old_block_metadata = NULL; size_t current_block_len; size_t size_real; @@ -321,7 +347,7 @@ sl_status_t sl_memory_alloc_advanced(size_t size, *block = NULL; // No block allocated yet. - if (size == 0) { + if ((size == 0) || (size >= heap_region.size)) { return SL_STATUS_INVALID_PARAMETER; } @@ -335,7 +361,7 @@ sl_status_t sl_memory_alloc_advanced(size_t size, if ((current_block_metadata == NULL) || (size_adjusted == 0)) { CORE_EXIT_ATOMIC(); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(sli_mm_heap_name, NULL, size); + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_name, NULL, size, return_address); #endif return SL_STATUS_ALLOCATION_FAILED; } @@ -447,9 +473,9 @@ sl_status_t sl_memory_alloc_advanced(size_t size, sli_update_free_list_heads(allocated_blk, old_block_metadata, true); } - heap_size += size_adjusted; - if (heap_size > heap_high_watermark) { - heap_high_watermark = heap_size; + heap_used_size += size_adjusted; + if (heap_used_size > heap_high_watermark) { + heap_high_watermark = heap_used_size; } CORE_EXIT_ATOMIC(); @@ -457,11 +483,11 @@ sl_status_t sl_memory_alloc_advanced(size_t size, *block = (void *)((uint8_t *)allocated_blk + SLI_BLOCK_METADATA_SIZE_BYTE); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(sli_mm_heap_name, allocated_blk, size_real + SLI_BLOCK_METADATA_SIZE_BYTE); + sli_memory_profiler_track_alloc(sli_mm_heap_name, allocated_blk, size_real + SLI_BLOCK_METADATA_SIZE_BYTE); if (type == BLOCK_TYPE_LONG_TERM) { - SLI_MEMORY_PROFILER_TRACK_ALLOC(sli_mm_heap_malloc_lt_name, *block, size); + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_malloc_lt_name, *block, size, return_address); } else if (type == BLOCK_TYPE_SHORT_TERM) { - SLI_MEMORY_PROFILER_TRACK_ALLOC(sli_mm_heap_malloc_st_name, *block, size); + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_malloc_st_name, *block, size, return_address); } #endif @@ -510,7 +536,7 @@ sl_status_t sl_memory_free(void *block) } #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_FREE(sli_mm_heap_name, ((uint8_t *)block - SLI_BLOCK_METADATA_SIZE_BYTE)); + sli_memory_profiler_track_free(sli_mm_heap_name, ((uint8_t *)block - SLI_BLOCK_METADATA_SIZE_BYTE)); #endif CORE_DECLARE_IRQ_STATE; @@ -527,6 +553,8 @@ sl_status_t sl_memory_free(void *block) sli_block_metadata_t *free_block = current_metadata; sli_block_metadata_t *next_block = NULL; + heap_used_size -= SLI_BLOCK_LEN_DWORD_TO_BYTE(current_metadata->length); + // Update counter with block being freed. sli_free_blocks_number++; @@ -605,8 +633,6 @@ sl_status_t sl_memory_free(void *block) sli_free_st_list_head = free_block; } - heap_size -= total_size_free_block; - CORE_EXIT_ATOMIC(); #if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) @@ -626,10 +652,17 @@ sl_status_t sl_memory_free(void *block) void *sl_calloc(size_t item_count, size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *block_avail = NULL; (void)sl_memory_calloc(item_count, size, BLOCK_TYPE_LONG_TERM, &block_avail); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block_avail, return_address); +#endif + return block_avail; } @@ -641,6 +674,9 @@ sl_status_t sl_memory_calloc(size_t item_count, sl_memory_block_type_t type, void **block) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif size_t block_size; sl_status_t status = SL_STATUS_OK; @@ -666,6 +702,10 @@ sl_status_t sl_memory_calloc(size_t item_count, memset(*block, 0, block_size); } +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif + return status; } @@ -675,10 +715,21 @@ sl_status_t sl_memory_calloc(size_t item_count, void *sl_realloc(void *ptr, size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *block_avail = NULL; (void)sl_memory_realloc(ptr, size, &block_avail); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + // Realloc to 0 bytes is equivalent to free, so only track ownership when size + // is other than 0 + if (size != 0) { + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block_avail, return_address); + } +#endif + return block_avail; } @@ -700,6 +751,10 @@ sl_status_t sl_memory_realloc(void *ptr, size_t size, void **block) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + sl_memory_region_t heap_region = sl_memory_get_heap_region(); sl_status_t status = SL_STATUS_OK; sli_block_metadata_t *current_block = NULL; sli_block_metadata_t *next_block = NULL; @@ -714,6 +769,10 @@ sl_status_t sl_memory_realloc(void *ptr, *block = NULL; // No block allocated yet. + if (size >= heap_region.size) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((ptr == NULL) && (size == 0)) { return SL_STATUS_INVALID_PARAMETER; } @@ -721,6 +780,9 @@ sl_status_t sl_memory_realloc(void *ptr, // Manage special parameters values (see Note #1). if (ptr == NULL) { status = sl_memory_alloc(size, BLOCK_TYPE_LONG_TERM, block); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif return status; } else if (size == 0) { status = sl_memory_free(ptr); @@ -800,7 +862,7 @@ sl_status_t sl_memory_realloc(void *ptr, // Current block has been extended. Its payload must be returned to the caller. *block = ptr; #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_REALLOC(sli_mm_heap_name, + sli_memory_profiler_track_realloc(sli_mm_heap_name, (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, size_real + SLI_BLOCK_METADATA_SIZE_BYTE); @@ -827,7 +889,7 @@ sl_status_t sl_memory_realloc(void *ptr, memcpy(*block, ptr, current_block_len); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_REALLOC(sli_mm_heap_name, + sli_memory_profiler_track_realloc(sli_mm_heap_name, (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, (uint8_t *)*block - SLI_BLOCK_METADATA_SIZE_BYTE, size_real + SLI_BLOCK_METADATA_SIZE_BYTE); @@ -841,9 +903,11 @@ sl_status_t sl_memory_realloc(void *ptr, } } - heap_size += size_real - current_block_len; - if (heap_size > heap_high_watermark) { - heap_high_watermark = heap_size; + if (find_new_block == false) { + heap_used_size += size_real - current_block_len; + if (heap_used_size > heap_high_watermark) { + heap_high_watermark = heap_used_size; + } } // BLOCK REDUCTION. @@ -898,20 +962,18 @@ sl_status_t sl_memory_realloc(void *ptr, current_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(size_real); current_block->offset_neighbour_next = current_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; sli_memory_metadata_init(adjusted_next_block); - adjusted_next_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(current_block_remaining_len); + adjusted_next_block->length = (uint16_t)SLI_BLOCK_LEN_BYTE_TO_DWORD(current_block_remaining_len - SLI_BLOCK_METADATA_SIZE_BYTE); adjusted_next_block->offset_neighbour_prev = current_block->offset_neighbour_next; - if ((next_block != NULL) && (next_block->offset_neighbour_next != 0)) { - sli_block_metadata_t *next_next_block = (sli_block_metadata_t *)((uint64_t *)next_block + next_block->offset_neighbour_next); - + if (next_block != NULL) { adjusted_next_block->offset_neighbour_next = adjusted_next_block->length + SLI_BLOCK_METADATA_SIZE_DWORD; - next_next_block->offset_neighbour_prev = adjusted_next_block->offset_neighbour_next; + next_block->offset_neighbour_prev = adjusted_next_block->offset_neighbour_next; } else { adjusted_next_block->offset_neighbour_next = 0; // End of heap } sli_free_blocks_number++; // Update head pointers accordingly. - sli_update_free_list_heads(adjusted_next_block, NULL, true); + sli_update_free_list_heads(adjusted_next_block, NULL, false); } else { // Not enough space in current block remaining area to create a new free block. // consider the current block unallocated portion as lost for now until the current block is freed. @@ -922,19 +984,19 @@ sl_status_t sl_memory_realloc(void *ptr, // Current block has been reduced. Its payload must be returned to the caller. *block = ptr; #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_REALLOC(sli_mm_heap_name, + sli_memory_profiler_track_realloc(sli_mm_heap_name, (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, size_real + SLI_BLOCK_METADATA_SIZE_BYTE); #endif - heap_size -= current_block_len - size_real; + heap_used_size -= current_block_len - size_real; } else { // If the size requested does not provoke a block extension or reduction, consider no error. // And return the same given address. We still track it to show that resize was requested. *block = ptr; #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_REALLOC(sli_mm_heap_name, + sli_memory_profiler_track_realloc(sli_mm_heap_name, (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, (uint8_t *)ptr - SLI_BLOCK_METADATA_SIZE_BYTE, size_real + SLI_BLOCK_METADATA_SIZE_BYTE); @@ -943,6 +1005,10 @@ sl_status_t sl_memory_realloc(void *ptr, CORE_EXIT_ATOMIC(); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *block, return_address); +#endif + return status; } diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c index b79642266..b1d7fcaea 100644 --- a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_dynamic_reservation.c @@ -64,6 +64,10 @@ sl_status_t sl_memory_reserve_block(size_t size, sl_memory_reservation_t *handle, void **block) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + // Check proper alignment characteristics. EFM_ASSERT((align == SL_MEMORY_BLOCK_ALIGN_DEFAULT) || (SL_MATH_IS_PWR2(align) @@ -76,6 +80,7 @@ sl_status_t sl_memory_reserve_block(size_t size, size_t size_real; size_t size_adjusted; size_t block_size_remaining; + sl_memory_region_t heap_region = sl_memory_get_heap_region(); #if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) reserve_no_retention_first = false; #endif @@ -92,7 +97,7 @@ sl_status_t sl_memory_reserve_block(size_t size, *block = NULL; // No block reserved yet. - if (size == 0) { + if ((size == 0) || (size >= heap_region.size)) { return SL_STATUS_INVALID_PARAMETER; } @@ -107,7 +112,7 @@ sl_status_t sl_memory_reserve_block(size_t size, if ((free_block_metadata == NULL) || (size_adjusted == 0)) { CORE_EXIT_ATOMIC(); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(sli_mm_heap_name, NULL, size); + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_name, NULL, size, return_address); #endif return SL_STATUS_ALLOCATION_FAILED; } @@ -171,8 +176,11 @@ sl_status_t sl_memory_reserve_block(size_t size, #endif #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(sli_mm_heap_name, handle->block_address, size_real); - SLI_MEMORY_PROFILER_TRACK_ALLOC(sli_mm_heap_reservation_name, handle->block_address, handle->block_size); + sli_memory_profiler_track_alloc(sli_mm_heap_name, handle->block_address, size_real); + sli_memory_profiler_track_alloc_with_ownership(sli_mm_heap_reservation_name, + handle->block_address, + handle->block_size, + return_address); #endif return SL_STATUS_OK; @@ -209,7 +217,7 @@ sl_status_t sl_memory_release_block(sl_memory_reservation_t *handle) } #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_FREE(sli_mm_heap_name, handle->block_address); + sli_memory_profiler_track_free(sli_mm_heap_name, handle->block_address); #endif CORE_DECLARE_IRQ_STATE; @@ -327,10 +335,15 @@ sl_status_t sl_memory_release_block(sl_memory_reservation_t *handle) ******************************************************************************/ sl_status_t sl_memory_reservation_handle_alloc(sl_memory_reservation_t **handle) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif sl_status_t status; status = sl_memory_alloc(sizeof(sl_memory_reservation_t), BLOCK_TYPE_LONG_TERM, (void**)handle); - +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *handle, return_address); +#endif if (status != SL_STATUS_OK) { return status; } diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool.c index 83d17edf1..028275fed 100644 --- a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool.c +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool.c @@ -52,6 +52,9 @@ sl_status_t sl_memory_create_pool(size_t block_size, uint32_t block_count, sl_memory_pool_t *pool_handle) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif sl_status_t status = SL_STATUS_OK; uint8_t *block = NULL; size_t block_addr; @@ -73,6 +76,10 @@ sl_status_t sl_memory_create_pool(size_t block_size, pool_size = pool_handle->block_size * pool_handle->block_count; status = sl_memory_alloc(pool_size, BLOCK_TYPE_LONG_TERM, (void **)&block); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block, return_address); +#endif + if (status != SL_STATUS_OK) { return status; } @@ -136,6 +143,9 @@ sl_status_t sl_memory_delete_pool(sl_memory_pool_t *pool_handle) sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, void **block) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif CORE_DECLARE_IRQ_STATE; if ((pool_handle == NULL) || (block == NULL)) { @@ -150,7 +160,7 @@ sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, if ((size_t)pool_handle->block_free == SLI_MEM_POOL_OUT_OF_MEMORY) { CORE_EXIT_ATOMIC(); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(pool_handle, NULL, pool_handle->block_size); + sli_memory_profiler_track_alloc_with_ownership(pool_handle, NULL, pool_handle->block_size, return_address); #endif return SL_STATUS_EMPTY; } @@ -164,7 +174,7 @@ sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, CORE_EXIT_ATOMIC(); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(pool_handle, block_addr, pool_handle->block_size); + sli_memory_profiler_track_alloc_with_ownership(pool_handle, block_addr, pool_handle->block_size, return_address); #endif *block = block_addr; @@ -189,7 +199,7 @@ sl_status_t sl_memory_pool_free(sl_memory_pool_t *pool_handle, && ((size_t)block <= ((size_t)pool_handle->block_address + (pool_handle->block_size * pool_handle->block_count)))); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_FREE(pool_handle, block); + sli_memory_profiler_track_free(pool_handle, block); #endif CORE_ENTER_ATOMIC(); @@ -204,35 +214,29 @@ sl_status_t sl_memory_pool_free(sl_memory_pool_t *pool_handle, } /***************************************************************************//** - * Dynamically allocates a memory pool handle. + * Gets the count of free blocks in a memory pool. ******************************************************************************/ -sl_status_t sl_memory_pool_handle_alloc(sl_memory_pool_t **pool_handle) +uint32_t sl_memory_pool_get_free_block_count(const sl_memory_pool_t *pool_handle) { - sl_status_t status; + uint32_t free_block_count = 0; + uint32_t *free_block; - // Allocate pool_handle as a long-term block. - status = sl_memory_alloc(sizeof(sl_memory_pool_t), BLOCK_TYPE_LONG_TERM, (void **)pool_handle); + if (pool_handle == NULL) { + return 0; + } - return status; -} + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); -/***************************************************************************//** - * Frees a dynamically allocated memory pool handle. - ******************************************************************************/ -sl_status_t sl_memory_pool_handle_free(sl_memory_pool_t *pool_handle) -{ - sl_status_t status; + free_block = pool_handle->block_free; - // Free memory pool_handle. - status = sl_memory_free((void *)pool_handle); + // Go through the free block list and count the number of free blocks remaining. + while ((size_t)free_block != SLI_MEM_POOL_OUT_OF_MEMORY) { + free_block = *(uint32_t **)free_block; + free_block_count++; + } - return status; -} + CORE_EXIT_ATOMIC(); -/***************************************************************************//** - * Gets the size of the memory pool handle structure. - ******************************************************************************/ -uint32_t sl_memory_pool_handle_get_size(void) -{ - return sizeof(sl_memory_pool_t); + return free_block_count; } diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool_common.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool_common.c new file mode 100644 index 000000000..3050a3475 --- /dev/null +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool_common.c @@ -0,0 +1,112 @@ +/***************************************************************************//** + * @file + * @brief Memory Manager Driver's Memory Pool Common Implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_memory_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +#include "sli_memory_profiler.h" +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Dynamically allocates a memory pool handle. + ******************************************************************************/ +sl_status_t sl_memory_pool_handle_alloc(sl_memory_pool_t **pool_handle) +{ +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif + sl_status_t status; + + // Allocate pool_handle as a long-term block. + status = sl_memory_alloc(sizeof(sl_memory_pool_t), BLOCK_TYPE_LONG_TERM, (void **)pool_handle); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, *pool_handle, return_address); +#endif + + return status; +} + +/***************************************************************************//** + * Frees a dynamically allocated memory pool handle. + ******************************************************************************/ +sl_status_t sl_memory_pool_handle_free(sl_memory_pool_t *pool_handle) +{ + sl_status_t status; + + // Free memory pool_handle. + status = sl_memory_free((void *)pool_handle); + + return status; +} + +/***************************************************************************//** + * Gets the size of the memory pool handle structure. + ******************************************************************************/ +uint32_t sl_memory_pool_handle_get_size(void) +{ + return sizeof(sl_memory_pool_t); +} + +/***************************************************************************//** + * Gets the total count of blocks in a memory pool. + ******************************************************************************/ +uint32_t sl_memory_pool_get_total_block_count(const sl_memory_pool_t *pool_handle) +{ + if (pool_handle == NULL) { + return 0; + } + + return pool_handle->block_count; +} + +/***************************************************************************//** + * Gets the count of used blocks in a memory pool. + ******************************************************************************/ +uint32_t sl_memory_pool_get_used_block_count(const sl_memory_pool_t *pool_handle) +{ + uint32_t used_block_count = 0; + + if (pool_handle == NULL) { + return 0; + } + + used_block_count = pool_handle->block_count - sl_memory_pool_get_free_block_count(pool_handle); + + return used_block_count; +} diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool_power_aware.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool_power_aware.c index 6320ef52f..01449d9a2 100644 --- a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool_power_aware.c +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_pool_power_aware.c @@ -36,6 +36,7 @@ #include "sl_bit.h" #include "em_device.h" #include "sl_core.h" +#include "sl_common.h" #if defined(SL_COMPONENT_CATALOG_PRESENT) #include "sl_component_catalog.h" @@ -67,6 +68,9 @@ sl_status_t sl_memory_create_pool(size_t block_size, uint32_t block_count, sl_memory_pool_t *pool_handle) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif sl_status_t status; uint8_t *block = NULL; size_t size_free_list_bytes = 0u; @@ -77,16 +81,31 @@ sl_status_t sl_memory_create_pool(size_t block_size, EFM_ASSERT(block_count > 0u); // Verify that the handle pointer isn't NULL. - if ((pool_handle == NULL) || (pool_handle->reservation == NULL)) { + if (pool_handle == NULL) { return SL_STATUS_NULL_POINTER; } + // Allocate reservation handle as a long-term block. + status = sl_memory_reservation_handle_alloc(&pool_handle->reservation); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + pool_handle->reservation, + return_address); +#endif + if (status != SL_STATUS_OK) { + return status; + } + // Reserve a block in which the entire pool will reside. status = sl_memory_reserve_block((block_size * block_count), SL_MEMORY_BLOCK_ALIGN_DEFAULT, pool_handle->reservation, (void **)&block); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, block, return_address); +#endif if (status != SL_STATUS_OK) { + sl_memory_reservation_handle_free(pool_handle->reservation); return status; } // Returned block pointer not used because its reference is already stored in reservation handle. @@ -96,6 +115,11 @@ sl_status_t sl_memory_create_pool(size_t block_size, size_free_list_bytes = SLI_POOL_BITS_TO_BYTE(block_count); size_free_list_bytes = SLI_ALIGN_ROUND_UP(size_free_list_bytes, SLI_WORD_SIZE_32); status = sl_memory_alloc(size_free_list_bytes, BLOCK_TYPE_LONG_TERM, (void **)&pool_handle->block_free); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + pool_handle->block_free, + return_address); +#endif if (status != SL_STATUS_OK) { (void)sl_memory_release_block(pool_handle->reservation); return status; @@ -189,6 +213,12 @@ sl_status_t sl_memory_delete_pool(sl_memory_pool_t *pool_handle) // Release free list. status = sl_memory_free((void *)pool_handle->block_free); + if (status != SL_STATUS_OK) { + return status; + } + + // Free reservation pool_handle. + status = sl_memory_reservation_handle_free(pool_handle->reservation); #if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) SEGGER_SYSVIEW_HeapFree(pool_handle, pool_handle->reservation); @@ -212,6 +242,9 @@ sl_status_t sl_memory_delete_pool(sl_memory_pool_t *pool_handle) sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, void **block) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif uint32_t free_list_size_byte = 0u; uint32_t free_list_size_word = 0u; uint32_t bitmap_ix = 0u; @@ -245,9 +278,12 @@ sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, block_ix += bit_position; } else { // No more free blocks. See Note #1. + CORE_EXIT_ATOMIC(); + #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(pool_handle, NULL, pool_handle->block_size); + sli_memory_profiler_track_alloc_with_ownership(pool_handle, NULL, pool_handle->block_size, return_address); #endif + return SL_STATUS_EMPTY; } @@ -257,7 +293,7 @@ sl_status_t sl_memory_pool_alloc(sl_memory_pool_t *pool_handle, CORE_EXIT_ATOMIC(); #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_ALLOC(pool_handle, *block, pool_handle->block_size); + sli_memory_profiler_track_alloc_with_ownership(pool_handle, *block, pool_handle->block_size, return_address); #endif #if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) uint32_t tag = (uint32_t)__builtin_extract_return_addr(__builtin_return_address(0)); @@ -282,7 +318,7 @@ sl_status_t sl_memory_pool_free(sl_memory_pool_t *pool_handle, } #if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) - SLI_MEMORY_PROFILER_TRACK_FREE(pool_handle, block); + sli_memory_profiler_track_free(pool_handle, block); #endif #if defined(SLI_MEMORY_MANAGER_ENABLE_SYSTEMVIEW) SEGGER_SYSVIEW_HeapFree(pool_handle, block); @@ -308,51 +344,29 @@ sl_status_t sl_memory_pool_free(sl_memory_pool_t *pool_handle, } /***************************************************************************//** - * Dynamically allocates a memory pool handle. + * Gets the count of free blocks in a memory pool. ******************************************************************************/ -sl_status_t sl_memory_pool_handle_alloc(sl_memory_pool_t **pool_handle) +uint32_t sl_memory_pool_get_free_block_count(const sl_memory_pool_t *pool_handle) { - sl_status_t status; + uint32_t free_block_count = 0u; + size_t free_list_size; - // Allocate pool_handle as a long-term block. See Note #1. - status = sl_memory_alloc(sizeof(sl_memory_pool_t), BLOCK_TYPE_LONG_TERM, (void**)pool_handle); - if (status != SL_STATUS_OK) { - return status; + if (pool_handle == NULL) { + return 0; } - // Allocate reservation handle as a long-term block. - status = sl_memory_reservation_handle_alloc(&(*pool_handle)->reservation); - if (status != SL_STATUS_OK) { - // Free previous successful memory pool handle allocation. - sl_memory_free((void*)pool_handle); - } + // Get the size of the free block list. + free_list_size = (pool_handle->block_count + SLI_DEF_INT_32_NBR_BITS - 1) / SLI_DEF_INT_32_NBR_BITS; - return status; -} - -/***************************************************************************//** - * Frees a dynamically allocated memory pool handle. - ******************************************************************************/ -sl_status_t sl_memory_pool_handle_free(sl_memory_pool_t *pool_handle) -{ - sl_status_t status; + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); - // Free reservation pool_handle. - status = sl_memory_reservation_handle_free(pool_handle->reservation); - if (status != SL_STATUS_OK) { - return status; + // Count the number of free blocks remaining. + for (size_t i = 0u; i < free_list_size; i++) { + free_block_count += SL_POPCOUNT32(pool_handle->block_free[i]); } - // Free memory pool handle. - status = sl_memory_free((void *)pool_handle); - - return status; -} + CORE_EXIT_ATOMIC(); -/***************************************************************************//** - * Gets the size of the memory pool handle structure. - ******************************************************************************/ -uint32_t sl_memory_pool_handle_get_size(void) -{ - return sizeof(sl_memory_pool_t); + return free_block_count; } diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_redirect.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_redirect.c new file mode 100644 index 000000000..1b6d1cb1d --- /dev/null +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_redirect.c @@ -0,0 +1,258 @@ +/***************************************************************************//** + * @file + * @brief This is a simple wrapper for the stdlib memory management functions + * like malloc, calloc, realloc and free in order to redirect memory_manager API + * to stdlib implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_memory_manager.h" +#include "sl_status.h" +#include "sl_core.h" + +#include + +/***************************************************************************//** + * Initializes the memory manager. + ******************************************************************************/ +sl_status_t sl_memory_init(void) +{ + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Allocates a memory block of at least requested size from the heap. Simple + * version. + * + * This function will be redirected to the 'malloc()' function. + ******************************************************************************/ +void *sl_malloc(size_t size) +{ + void *block_avail; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + + block_avail = malloc(size); + + CORE_EXIT_ATOMIC(); + + return block_avail; +} + +/***************************************************************************//** + * Dynamically allocates a block of memory. Advanced version that allows to + * specify alignment. + * + * This function will be redirected to the standard 'malloc()' function. + ******************************************************************************/ +sl_status_t sl_memory_alloc_advanced(size_t size, + size_t align, + sl_memory_block_type_t type, + void **block) +{ + (void)type; + + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // No block allocated yet. + *block = NULL; + + if ((size == 0) || (align == 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + *block = malloc(size); + + CORE_EXIT_ATOMIC(); + + if (*block == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + + if ((align != SL_MEMORY_BLOCK_ALIGN_DEFAULT) && (((uintptr_t)*block % (uintptr_t)align) != 0)) { + // Deallocate *block. + sl_free(*block); + *block = NULL; + + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Dynamically allocates a block of memory. + * + * This function simplifies memory allocation by calling 'sl_memory_alloc_advanced()' + * with alignment set to 8 bytes. + ******************************************************************************/ +sl_status_t sl_memory_alloc(size_t size, + sl_memory_block_type_t type, + void **block) +{ + return sl_memory_alloc_advanced(size, SL_MEMORY_BLOCK_ALIGN_DEFAULT, type, block); +} + +/***************************************************************************//** + * Dynamically allocates a block of memory cleared to 0. Simple version. + * + * This function will be redirected to the standard 'calloc()' function. + ******************************************************************************/ +void *sl_calloc(size_t item_count, + size_t size) +{ + void *block_avail = NULL; + + (void)sl_memory_calloc(item_count, size, BLOCK_TYPE_LONG_TERM, &block_avail); + + return block_avail; +} + +/***************************************************************************//** + * Dynamically allocates a block of memory cleared to 0. + * + * This function will be redirected to the standard 'calloc()' function. + ******************************************************************************/ +sl_status_t sl_memory_calloc(size_t item_count, + size_t size, + sl_memory_block_type_t type, + void **block) +{ + (void)type; + CORE_DECLARE_IRQ_STATE; + + // Verify that the block pointer isn't NULL. + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } + + *block = NULL; // No block allocated yet. + + if ((size == 0) || (item_count == 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + *block = calloc(item_count, size); + + CORE_EXIT_ATOMIC(); + + if (*block == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Resizes a previously allocated memory block. Simple version. + * + * This function will be redirected to the standard 'realloc()' function. + ******************************************************************************/ +void *sl_realloc(void *ptr, size_t size) +{ + void *block_avail = NULL; + + (void)sl_memory_realloc(ptr, size, &block_avail); + + return block_avail; +} + +/***************************************************************************//** + * Resizes a previously allocated memory block. + * + * This function will be redirected to the standard 'realloc()' function. + ******************************************************************************/ +sl_status_t sl_memory_realloc(void *ptr, + size_t size, + void **block) +{ + (void)block; + CORE_DECLARE_IRQ_STATE; + + // Verify that the block pointer isn't NULL. + if (block == NULL) { + return SL_STATUS_NULL_POINTER; + } + + *block = NULL; // No block allocated yet. + + if ((ptr == NULL) && (size == 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_ENTER_ATOMIC(); + + *block = realloc(ptr, size); + + CORE_EXIT_ATOMIC(); + + if (*block == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Frees a dynamically allocated block of memory. + * + * This function will be redirected to the standard 'free()' function. + ******************************************************************************/ +sl_status_t sl_memory_free(void *ptr) +{ + CORE_DECLARE_IRQ_STATE; + + if (ptr == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + free(ptr); + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Frees a previously allocated block back into the heap. Simple version. + * + * This function will be redirected to the 'free()' function. + ******************************************************************************/ +void sl_free(void *ptr) +{ + (void)sl_memory_free(ptr); +} diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_region_host.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_region_host.c index 21fa0d4c9..e58507176 100644 --- a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_region_host.c +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_region_host.c @@ -37,7 +37,9 @@ #endif // Simulated C heap size. +#ifndef SL_MM_HEAP_SIZE #define SL_MM_HEAP_SIZE (4 * 1024) +#endif /******************************************************************************* *************************** GLOBAL VARIABLES ******************************* diff --git a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_retarget.c b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_retarget.c index f111c6d95..29581f072 100644 --- a/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_retarget.c +++ b/simplicity_sdk/platform/service/memory_manager/src/sl_memory_manager_retarget.c @@ -30,6 +30,14 @@ #include "sl_memory_manager.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) +#include "sli_memory_profiler.h" +#endif + #if defined(__GNUC__) // Wrapping a system function with GCC works by using the linker option '--wrap=symbol'. // Any undefined reference to "symbol" will be resolved to "__wrap_symbol". @@ -145,6 +153,9 @@ volatile uint32_t retarget_realloc_counter = 0; ATTR_EXT_VIS void *STD_LIB_WRAPPER_MALLOC(RARG size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif VOID_RARG; void *ptr; @@ -153,23 +164,49 @@ ATTR_EXT_VIS void *STD_LIB_WRAPPER_MALLOC(RARG retarget_malloc_counter++; #endif +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + return ptr; } #if defined(__IAR_SYSTEMS_ICC__) && (__VER__ == 9040001) void *STD_LIB_WRAPPER_MALLOC_ADVANCED(size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *ptr; ptr = sl_malloc(size); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + return ptr; } void *STD_LIB_WRAPPER_MALLOC_NO_FREE(size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *ptr; ptr = sl_malloc(size); + +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + return ptr; } #endif @@ -214,6 +251,9 @@ ATTR_EXT_VIS void *STD_LIB_WRAPPER_CALLOC(RARG size_t item_count, size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif VOID_RARG; void *ptr; @@ -222,6 +262,12 @@ ATTR_EXT_VIS void *STD_LIB_WRAPPER_CALLOC(RARG retarget_calloc_counter++; #endif +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + return ptr; } @@ -229,20 +275,38 @@ ATTR_EXT_VIS void *STD_LIB_WRAPPER_CALLOC(RARG void *STD_LIB_WRAPPER_CALLOC_ADVANCED(size_t item_count, size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *ptr; ptr = sl_calloc(item_count, size); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + return ptr; } void *STD_LIB_WRAPPER_CALLOC_NO_FREE(size_t item_count, size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *ptr; ptr = sl_calloc(item_count, size); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + ptr, + return_address); +#endif + return ptr; } #endif @@ -272,6 +336,9 @@ ATTR_EXT_VIS void *STD_LIB_WRAPPER_REALLOC(RARG void *ptr, size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif VOID_RARG; void *r_ptr; @@ -280,6 +347,12 @@ ATTR_EXT_VIS void *STD_LIB_WRAPPER_REALLOC(RARG retarget_realloc_counter++; #endif +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + r_ptr, + return_address); +#endif + return r_ptr; } @@ -287,10 +360,19 @@ ATTR_EXT_VIS void *STD_LIB_WRAPPER_REALLOC(RARG void *STD_LIB_WRAPPER_REALLOC_ADVANCED(void *ptr, size_t size) { +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + void * volatile return_address = sli_memory_profiler_get_return_address(); +#endif void *r_ptr; r_ptr = sl_realloc(ptr, size); +#if defined(SL_CATALOG_MEMORY_PROFILER_PRESENT) + sli_memory_profiler_track_ownership(SLI_INVALID_MEMORY_TRACKER_HANDLE, + r_ptr, + return_address); +#endif + return r_ptr; } #endif diff --git a/simplicity_sdk/platform/service/memory_manager/src/sli_memory_manager_common.c b/simplicity_sdk/platform/service/memory_manager/src/sli_memory_manager_common.c index 700a83f1d..5faa47c63 100644 --- a/simplicity_sdk/platform/service/memory_manager/src/sli_memory_manager_common.c +++ b/simplicity_sdk/platform/service/memory_manager/src/sli_memory_manager_common.c @@ -360,7 +360,9 @@ void *sli_memory_get_shortterm_head_ptr(void) /***************************************************************************//** * Update free lists heads (short and long terms). ******************************************************************************/ -void sli_update_free_list_heads(sli_block_metadata_t *free_head, const sli_block_metadata_t *condition_block, bool search) +void sli_update_free_list_heads(sli_block_metadata_t *free_head, + const sli_block_metadata_t *condition_block, + bool search) { if (search) { if ((sli_free_lt_list_head == condition_block) || (condition_block == NULL)) { @@ -372,9 +374,13 @@ void sli_update_free_list_heads(sli_block_metadata_t *free_head, const sli_block } else { if (sli_free_lt_list_head == condition_block) { sli_free_lt_list_head = free_head; + } else if (free_head < sli_free_lt_list_head) { + sli_free_lt_list_head = free_head; } if (sli_free_st_list_head == condition_block) { sli_free_st_list_head = free_head; + } else if (free_head > sli_free_st_list_head) { + sli_free_st_list_head = free_head; } } } diff --git a/simplicity_sdk/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h b/simplicity_sdk/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h index 12e611cf5..085b27aaa 100644 --- a/simplicity_sdk/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h +++ b/simplicity_sdk/platform/service/power_manager/config/SIXG301/sl_power_manager_config.h @@ -71,6 +71,13 @@ // Default: 0 #define SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN 0 // + +// Enable QSPI clock switch for sleep +// Enable/Disable the QSPI clock switching when entering sleep. +// By default the QSPI clock uses a PLL. To further reduce the power consumption in sleep, the QSPI can be switched to a RCO oscillator during the sleep period. +// Default: 1 +#define SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN 1 +// // #endif /* SL_POWER_MANAGER_CONFIG_H */ diff --git a/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager.h b/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager.h index fc134e70a..9e9336c10 100644 --- a/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager.h +++ b/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager.h @@ -96,6 +96,8 @@ extern "C" { * clock will be active once sl_power_manager_add_requirement() returns. The EM * requirement can be also be removed from an ISR. * + * Requirements should not be removed if it was not previously added. + * * ## Subscribe to events * * It possible to get notified when the system transition from a power level to @@ -267,8 +269,8 @@ typedef struct { /// @brief Struct representing energy mode transition event handle typedef struct { - sl_slist_node_t node; ///< List node. - sl_power_manager_em_transition_event_info_t *info; ///< Handle event info. + sl_slist_node_t node; ///< List node. + const sl_power_manager_em_transition_event_info_t *info; ///< Handle event info. } sl_power_manager_em_transition_event_handle_t; /// On ISR Exit Hook answer @@ -541,6 +543,7 @@ void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); * is added on SL_POWER_MANAGER_EM1, since we will * never sleep at a lower level than EM1. *****************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) bool sl_power_manager_is_latest_wakeup_internal(void); /***************************************************************************//** diff --git a/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager_execution_modes.h b/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager_execution_modes.h index d167b165a..c79836a4f 100644 --- a/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager_execution_modes.h +++ b/simplicity_sdk/platform/service/power_manager/inc/sl_power_manager_execution_modes.h @@ -73,6 +73,21 @@ __INLINE void sl_power_manager_remove_performance_mode_requirement(void) sli_power_manager_update_execution_mode_requirement(false); } +/***************************************************************************//** + * Initializes execution mode feature. + * + * @note FOR INTERNAL USE ONLY. + ******************************************************************************/ +void sli_power_manager_executions_modes_init(void); + +/***************************************************************************//** + * Implement execution mode if not already implemented during a wakeup event. + * + * @note FOR INTERNAL USE ONLY. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_implement_execution_mode_on_wakeup(void); + #ifdef __cplusplus } #endif diff --git a/simplicity_sdk/platform/service/power_manager/inc/sli_power_manager.h b/simplicity_sdk/platform/service/power_manager/inc/sli_power_manager.h index ebd71d563..1e2b9d434 100644 --- a/simplicity_sdk/platform/service/power_manager/inc/sli_power_manager.h +++ b/simplicity_sdk/platform/service/power_manager/inc/sli_power_manager.h @@ -40,6 +40,38 @@ extern "C" { #endif +/******************************************************************************* + ****************************** HOOK REFERENCES **************************** + ******************************************************************************/ + +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +bool sl_power_manager_sleep_on_isr_exit(void); + +// Callback to application after wakeup but before restoring interrupts. +// For internal Silicon Labs use only +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_on_wakeup(void); + +// Hook that can be used by the log outputer to suspend transmission of logs +// in case it would require energy mode changes while in the sleep loop. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_suspend_log_transmission(void); + +// Hook that can be used by the log outputer to resume transmission of logs. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_resume_log_transmission(void); + +// Callback to notify possible transition from EM1P to EM2. +// For internal Silicon Labs use only +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +__WEAK void sli_power_manager_em1p_to_em2_notification(void); + +/***************************************************************************//** + * Mandatory callback that allows to cancel sleeping action. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +bool sl_power_manager_is_ok_to_sleep(void); + /******************************************************************************* ***************************** PROTOTYPES ********************************** ******************************************************************************/ @@ -83,6 +115,7 @@ __WEAK void sli_power_manager_set_high_accuracy_hf_clock_as_used(void); * * @return Wake-up restore process time. ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) uint32_t sli_power_manager_get_restore_delay(void); /***************************************************************************//** @@ -90,6 +123,48 @@ uint32_t sli_power_manager_get_restore_delay(void); ******************************************************************************/ void sli_power_manager_initiate_restore(void); +/***************************************************************************//** + * Performs pre sleep operations. + * + * @note Must only be called by the RTOS integration code. + ******************************************************************************/ +void sli_power_manager_pre_sleep(void); + +/***************************************************************************//** + * Fetches current energy mode + * + * @return Returns current energy mode + ******************************************************************************/ +sl_power_manager_em_t sli_power_manager_get_current_em(void); + +/***************************************************************************//** + * Update Energy Mode 4 configurations. + ******************************************************************************/ +void sli_power_manager_init_em4(void); + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @note Will also update the wake up time from EM2 to EM0. + ******************************************************************************/ +void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); + +/***************************************************************************//** + * Initializes energy mode transition list. + ******************************************************************************/ +void sli_power_manager_em_transition_event_list_init(void); + +/***************************************************************************//** + * Notify subscribers about energy mode transition. + * + * @param from Energy mode from which CPU comes from. + * + * @param to Energy mode to which CPU is going to. + ******************************************************************************/ +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_notify_em_transition(sl_power_manager_em_t from, + sl_power_manager_em_t to); + #ifdef __cplusplus } #endif diff --git a/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_common.c b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_common.c new file mode 100644 index 000000000..ffff08e57 --- /dev/null +++ b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_common.c @@ -0,0 +1,213 @@ +/***************************************************************************//** + * @file + * @brief Power Manager common API implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sli_power_manager.h" +#include "sli_clock_manager.h" +#include "sl_assert.h" +#include "sl_atomic.h" +#include "sl_clock_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include "em_device.h" +#if !defined(_SILICON_LABS_32B_SERIES_3) +#include "em_emu.h" +#else +#include "sli_power_manager_execution_modes_private.h" +#endif + +#include +#include +#include + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Events subscribers lists +static sl_slist_node_t *power_manager_em_transition_event_list = NULL; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Last-chance check before sleep. + * + * @return True, if the system should actually sleep. + * False, if not. + * + * @note This is the fallback implementation of the callback, it can be + * overridden by the application or other components. + ******************************************************************************/ +__WEAK bool sl_power_manager_is_ok_to_sleep(void) +{ + return true; +} + +/***************************************************************************//** + * Check if the MCU can sleep after an interrupt. + * + * @return True, if the system can sleep after the interrupt. + * False, otherwise. + * + * @note This is the fallback implementation of the callback, it can be + * overridden by the application or other components. + ******************************************************************************/ +__WEAK bool sl_power_manager_sleep_on_isr_exit(void) +{ + return false; +} + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @note Will also update the wake up time from EM2 to EM0. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) +{ +#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(enable); + + CORE_EXIT_CRITICAL(); +#else + (void)enable; +#endif +} + +/***************************************************************************//** + * Registers a callback to be called on given Energy Mode transition(s). + * + * @note Adding/Removing requirement(s) from the callback is not supported. + ******************************************************************************/ +void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, + const sl_power_manager_em_transition_event_info_t *event_info) +{ + CORE_DECLARE_IRQ_STATE; + + event_handle->info = event_info; + CORE_ENTER_CRITICAL(); + sl_slist_push(&power_manager_em_transition_event_list, &event_handle->node); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Unregisters an event callback handle on Energy mode transition. + ******************************************************************************/ +void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sl_slist_remove(&power_manager_em_transition_event_list, &event_handle->node); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Initializes energy mode transition list. + ******************************************************************************/ +void sli_power_manager_em_transition_event_list_init(void) +{ + sl_slist_init(&power_manager_em_transition_event_list); +} + +/***************************************************************************//** + * Notify subscribers about energy mode transition. + ******************************************************************************/ +void sli_power_manager_notify_em_transition(sl_power_manager_em_t from, + sl_power_manager_em_t to) +{ + sl_power_manager_em_transition_event_handle_t *handle; + sl_power_manager_em_transition_event_t transition = 0; + + switch (to) { + case SL_POWER_MANAGER_EM0: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0; + break; + + case SL_POWER_MANAGER_EM1: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1; + break; + + case SL_POWER_MANAGER_EM2: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2; + break; + +#if !defined(SL_CATALOG_POWER_MANAGER_ARM_SLEEP_ON_EXIT) + case SL_POWER_MANAGER_EM3: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3; + break; +#endif + + default: + EFM_ASSERT(0); + } + + switch (from) { + case SL_POWER_MANAGER_EM0: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0; + break; + + case SL_POWER_MANAGER_EM1: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1; + break; + + case SL_POWER_MANAGER_EM2: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2; + break; + +#if !defined(SL_CATALOG_POWER_MANAGER_ARM_SLEEP_ON_EXIT) + case SL_POWER_MANAGER_EM3: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3; + break; +#endif + + default: + EFM_ASSERT(0); + } + + SL_SLIST_FOR_EACH_ENTRY(power_manager_em_transition_event_list, handle, sl_power_manager_em_transition_event_handle_t, node) { + if ((handle->info->event_mask & transition) > 0) { + handle->info->on_event(from, to); + } + } +} diff --git a/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_em4.c b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_em4.c new file mode 100644 index 000000000..e553c9916 --- /dev/null +++ b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_em4.c @@ -0,0 +1,330 @@ +/***************************************************************************//** + * @file + * @brief Power Manager EM4 API implementation. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sli_power_manager.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_emu.h" +#include "em_cmu.h" +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#include "em_iadc.h" +#endif +#endif + +#include +#include + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#if defined(WDOG_PRESENT) +// Macros to determine if WDOG instances are clocked or not + +#if defined(CMU_CLKEN0_WDOG0) +#define WDOG0_CLOCK_ENABLED_BIT (CMU->CLKEN0 & CMU_CLKEN0_WDOG0) +#else +// There's no CMU->CLKEN1 so assume the WDOG0 is clocked +#define WDOG0_CLOCK_ENABLED_BIT 1 +#endif + +#if defined(CMU_CLKEN1_WDOG1) +#define WDOG1_CLOCK_ENABLED_BIT (CMU->CLKEN1 & CMU_CLKEN1_WDOG1) +#else +// There's no CMU->CLKEN1 so assume the WDOG1 is clocked +#define WDOG1_CLOCK_ENABLED_BIT 1 +#endif + +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +static bool is_em4_blocked(void); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) +static void ramp_dvdd_and_switch_to_dcdc_bypass_mode(void); +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * update energy mode 4 configurations. + ******************************************************************************/ +void sli_power_manager_init_em4(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2) + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | (uint32_t)SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE; +#else + EMU_EM4Init_TypeDef em4_init = EMU_EM4INIT_DEFAULT; + em4_init.pinRetentionMode = (EMU_EM4PinRetention_TypeDef)SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE; + EMU_EM4Init(&em4_init); +#endif +} + +/****************************************************************************** + * Event called before entering EM4 sleep. + *****************************************************************************/ +SL_WEAK void sl_power_manager_em4_presleep_hook(void) +{ + // This implementation is empty, but this function can be redefined as it's a weak implementation. +} + +/***************************************************************************//** + * Enter energy mode 4 (EM4). + * + * @note You should not expect to return from this function. Once the device + * enters EM4, only a power on reset or external reset pin can wake the + * device. + * + * @note On xG22 devices, this function re-configures the IADC if EM4 entry + * is possible. + ******************************************************************************/ +__NO_RETURN void sl_power_manager_enter_em4(void) +{ + /* Device with Boost DC-DC cannot enter EM4 because Boost DC-DC module does not + * have BYPASS switch so DC-DC converter can not be set to bypass mode. */ +#if (defined(_SILICON_LABS_DCDC_FEATURE) \ + && (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST)) + EFM_ASSERT(false); +#endif + + // Make sure that we are not interrupted while we are entering em4 + CORE_CRITICAL_IRQ_DISABLE(); + + EFM_ASSERT(is_em4_blocked() == false); + +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) + sli_metric_em4_wake_init(); +#endif + + uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); + uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); + + // Make sure that the register write lock is disabled. + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; + +#if defined(_DCDC_IF_EM4ERR_MASK) + // Workaround for bug that may cause a Hard Fault on EM4 entry + CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); + // The buck DC-DC is available in all energy modes except for EM4. + // The DC-DC converter must first be turned off and switched over to bypass mode. +#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) + ramp_dvdd_and_switch_to_dcdc_bypass_mode(); + #else + EMU_DCDCModeSet(emuDcdcMode_Bypass); + #endif +#endif +#endif + + sl_power_manager_em4_presleep_hook(); + + for (uint8_t i = 0; i < 4; i++) { + EMU->EM4CTRL = em4seq2; + EMU->EM4CTRL = em4seq3; + } + EMU->EM4CTRL = em4seq2; + __WFI(); + + for (;; ) { + // __NO_RETURN + } +} + +/***************************************************************************//** + * When EM4 pin retention is set to power_manager_pin_retention_latch, + * then pins are retained through EM4 entry and wakeup. The pin state is + * released by calling this function. The feature allows peripherals or + * GPIO to be re-initialized after EM4 exit (reset), and when + * initialization is done, this function can release pins and return + * control to the peripherals or GPIO. + ******************************************************************************/ +void sl_power_manager_em4_unlatch_pin_retention(void) +{ +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) + EMU->CMD = EMU_CMD_EM4UNLATCH; +#endif +} + +/***************************************************************************//** + * Returns true if em4 entry is blocked by a watchdog peripheral. + ******************************************************************************/ +static bool is_em4_blocked(void) +{ +#if defined(WDOG_PRESENT) +#if WDOG_COUNT > 0 + if ( WDOG0_CLOCK_ENABLED_BIT && (WDOG0->CFG & WDOG_CFG_EM4BLOCK) && (WDOG0->EN & WDOG_EN_EN) ) { + return true; + } +#endif +#if WDOG_COUNT > 1 + if ( WDOG1_CLOCK_ENABLED_BIT && (WDOG1->CFG & WDOG_CFG_EM4BLOCK) && (WDOG1->EN & WDOG_EN_EN) ) { + return true; + } +#endif +#endif + return false; +} + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) + +/* The following section provides an optimization to improve peak current + * consumption on xG22 devices. + */ + +// ADC clock frequency (source and after prescale) +#define CLK_SRC_ADC_FREQ 9600000 // CLK_SRC_ADC +#define CLK_ADC_FREQ 1000000 // CLK_ADC + +extern void sli_delay_loop(uint32_t cycles); + +uint32_t * dcdc_test_addr = (uint32_t *)(DCDC_NS_BASE + 0x80); +uint32_t ipkval = 7; +uint32_t ipktimeout = 1; + +/* Pulse generation sequence TOCTRIG (bit 3) TOCMODE (bit 2)*/ +uint32_t cmd[2] = { (1 << 2) | (1 << 3), (1 << 2) }; + +/***************************************************************************//** + * The voltage of Dvdd is ramped up to VMCU by sending pulses to a DCDC test + * register. These pulses are delayed, and ipkval and ipktimeout are tuned + * such that the voltage at Dvdd increases gradually to the voltage level of + * VMCU. Using the IADC, once Dvdd has gotten sufficiently close to VMCU, + * the DCDC peripheral is then switched into bypass mode. The IADC is used to + * detect this by sampling the voltage of Dvdd periodically, and calculating the + * difference between samples, when the difference is within some margin of zero + * then we know that the ramp sequence has reached a plateau. + ******************************************************************************/ +static void ramp_dvdd_and_switch_to_dcdc_bypass_mode(void) +{ + // Initialize the IADC for the purposes of detecting when the Dvdd ramp + // reaches a plateau. + IADC_Init_t init = IADC_INIT_DEFAULT; + IADC_AllConfigs_t initAllConfigs = IADC_ALLCONFIGS_DEFAULT; + IADC_InitSingle_t initSingle = IADC_INITSINGLE_DEFAULT; + IADC_SingleInput_t initSingleInput = IADC_SINGLEINPUT_DEFAULT; + CMU_ClockEnable(cmuClock_IADC0, true); + + init.srcClkPrescale = IADC_calcSrcClkPrescale(IADC0, CLK_SRC_ADC_FREQ, 0); + initAllConfigs.configs[0].reference = iadcCfgReferenceInt1V2; + initAllConfigs.configs[0].vRef = 1210; + initAllConfigs.configs[0].analogGain = iadcCfgAnalogGain1x; + initAllConfigs.configs[0].digAvg = iadcDigitalAverage1; + initAllConfigs.configs[0].adcClkPrescale = + IADC_calcAdcClkPrescale(IADC0, + CLK_ADC_FREQ, + 0, + iadcCfgModeNormal, + init.srcClkPrescale); + init.warmup = iadcWarmupKeepWarm; + + IADC_reset(IADC0); + CMU_ClockSelectSet(cmuClock_IADCCLK, cmuSelect_EM01GRPACLK); + initSingle.triggerAction = iadcTriggerActionContinuous; + initSingle.alignment = iadcAlignRight12; + initSingleInput.compare = false; // Disable Window CMP + initSingleInput.posInput = iadcPosInputDvdd; + IADC_init(IADC0, &init, &initAllConfigs); + IADC_initSingle(IADC0, &initSingle, &initSingleInput); + + // Start capturing + IADC_command(IADC0, iadcCmdStartSingle); + + // Initialize DCDC peak current value and timeout to reach peak current value + DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); + DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); + + /* Generate pulses */ + uint32_t iter = 1U; + IADC_Result_t prev_result; + volatile IADC_Result_t current_result = IADC_readSingleResult(IADC0); + while (true) { + // If the algorithm doesn't converge after 500 pulses, switch to dcdc + // bypass anyways. + if (iter >= 500) { + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + EFM_ASSERT(false); + return; + } + + /* Pulse generation sequence TOCTRIG (bit 3) TOCMODE (bit 2)*/ + *dcdc_test_addr = cmd[0]; + *dcdc_test_addr = cmd[1]; + + // In DCDC mode, MCU input voltage VREGVDD cannot be directly measured, so + // we can't know what the target DVDD voltage is. Instead, since DVDD + // ramp-up should follow a RC charge curve, measure DVDD and keep charging + // until the delta between measures is smaller than the set tolerance. + if (iter % 20U == 0U) { + prev_result = current_result; + current_result = IADC_readSingleResult(IADC0); + if ( abs((int32_t)(current_result.data - prev_result.data)) < SL_POWER_MANAGER_RAMP_DVDD_TOLERANCE ) { + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + return; + } + } + + if (DCDC->IF & DCDC_IF_TMAX) { + if (ipkval) { + ipkval--; // DCDC peak current value + } + + if (ipktimeout < 7) { + ipktimeout++; // Timeout to reach peak current value + } + + DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); + DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); + + DCDC->IF_CLR = DCDC_IF_TMAX; + } + + /* delay for 8 clock cycles */ + sli_delay_loop(8); + iter++; + } +} + +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) diff --git a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_execution_modes.c b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_execution_modes.c similarity index 99% rename from simplicity_sdk/platform/service/power_manager/src/sl_power_manager_execution_modes.c rename to simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_execution_modes.c index 3be33d6a6..76b4eab2a 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_execution_modes.c +++ b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_execution_modes.c @@ -31,9 +31,9 @@ #include "em_device.h" #include "sl_power_manager_config.h" #include "sl_power_manager.h" +#include "sli_power_manager.h" #include "sl_power_manager_execution_modes.h" #include "sli_power_manager_execution_modes_private.h" -#include "sli_power_manager_private.h" #include "sli_clock_manager.h" #include "sl_assert.h" #include "sl_core.h" diff --git a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_execution_modes_hal_sixg301.c b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_execution_modes_hal_sixg301.c similarity index 97% rename from simplicity_sdk/platform/service/power_manager/src/sl_power_manager_execution_modes_hal_sixg301.c rename to simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_execution_modes_hal_sixg301.c index 36e79fb85..2d1bf1c40 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_execution_modes_hal_sixg301.c +++ b/simplicity_sdk/platform/service/power_manager/src/common/sl_power_manager_execution_modes_hal_sixg301.c @@ -50,10 +50,11 @@ ******************************************************************************/ /***************************************************************************//** - * Saves the SYSCLK clock source that was used during standard mode execution. + * Initialize execution modes with original mode as standard mode. ******************************************************************************/ void sli_power_manager_executions_modes_hal_init(void) { + sli_power_manager_hal_apply_standard_mode(); } /***************************************************************************//** diff --git a/simplicity_sdk/platform/service/power_manager/src/sli_power_manager_execution_modes_private.h b/simplicity_sdk/platform/service/power_manager/src/common/sli_power_manager_execution_modes_private.h similarity index 82% rename from simplicity_sdk/platform/service/power_manager/src/sli_power_manager_execution_modes_private.h rename to simplicity_sdk/platform/service/power_manager/src/common/sli_power_manager_execution_modes_private.h index e1546991c..43385d01d 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sli_power_manager_execution_modes_private.h +++ b/simplicity_sdk/platform/service/power_manager/src/common/sli_power_manager_execution_modes_private.h @@ -41,21 +41,6 @@ extern "C" { #if defined(SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN) && (SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN == 1) -/***************************************************************************//** - * Initializes execution mode feature. - * - * @note FOR INTERNAL USE ONLY. - ******************************************************************************/ -void sli_power_manager_executions_modes_init(void); - -/***************************************************************************//** - * Implement execution mode if not already implemented during a wakeup event. - * - * @note FOR INTERNAL USE ONLY. - ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -void sli_power_manager_implement_execution_mode_on_wakeup(void); - /******************************************************************************* ***************************** HAL PROTOTYPES ****************************** ******************************************************************************/ diff --git a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager.c b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager.c similarity index 81% rename from simplicity_sdk/platform/service/power_manager/src/sl_power_manager.c rename to simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager.c index 82cdd4faa..9e4621faf 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager.c +++ b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager.c @@ -38,11 +38,13 @@ #include "sl_atomic.h" #include "sl_clock_manager.h" +#if defined(SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN) && (SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN == 1) +#include "sl_power_manager_execution_modes.h" +#endif + #include "em_device.h" #if !defined(_SILICON_LABS_32B_SERIES_3) #include "em_emu.h" -#else -#include "sli_power_manager_execution_modes_private.h" #endif #include @@ -58,7 +60,7 @@ #define SCHEDULE_WAKEUP_DEFAULT_RESTORE_TIME_OVERHEAD_TICK 0 // Determine if the device supports EM1P -#if !defined(SLI_DEVICE_SUPPORTS_EM1P) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && _SILICON_LABS_32B_SERIES_2_CONFIG >= 2 +#if !defined(SLI_DEVICE_SUPPORTS_EM1P) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) #define SLI_DEVICE_SUPPORTS_EM1P #endif @@ -72,9 +74,6 @@ static bool is_initialized = false; // Current active energy mode. static sl_power_manager_em_t current_em = SL_POWER_MANAGER_EM0; -// Events subscribers lists -static sl_slist_node_t *power_manager_em_transition_event_list = NULL; - // Table of energy modes counters. Each counter indicates the presence (not zero) // or absence (zero) of requirements on a given energy mode. The table doesn't // contain requirement on EM0. @@ -130,42 +129,6 @@ static volatile bool is_restored_from_hfxo_isr = false; static volatile bool is_restored_from_hfxo_isr_internal = false; #endif -/* - ********************************************************************************************************* - * HOOK REFERENCES - ********************************************************************************************************* - */ - -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -bool sl_power_manager_sleep_on_isr_exit(void); - -// Callback to application after wakeup but before restoring interrupts. -// For internal Silicon Labs use only -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -__WEAK void sli_power_manager_on_wakeup(void); - -// Hook that can be used by the log outputer to suspend transmission of logs -// in case it would require energy mode changes while in the sleep loop. -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -__WEAK void sli_power_manager_suspend_log_transmission(void); - -// Hook that can be used by the log outputer to resume transmission of logs. -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -__WEAK void sli_power_manager_resume_log_transmission(void); - -// Callback to notify possible transition from EM1P to EM2. -// For internal Silicon Labs use only -#ifdef SLI_DEVICE_SUPPORTS_EM1P -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -__WEAK void sli_power_manager_em1p_to_em2_notification(void); -#endif - -/***************************************************************************//** - * Mandatory callback that allows to cancel sleeping action. - ******************************************************************************/ -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -bool sl_power_manager_is_ok_to_sleep(void); - /******************************************************************************* ************************** LOCAL FUNCTIONS ******************************** ******************************************************************************/ @@ -191,10 +154,6 @@ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) static void clock_restore(void); #endif -SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) -static void power_manager_notify_em_transition(sl_power_manager_em_t from, - sl_power_manager_em_t to); - // Use PriMask to enter critical section by disabling interrupts. SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) static CORE_irqState_t enter_critical_with_primask(); @@ -203,6 +162,10 @@ static CORE_irqState_t enter_critical_with_primask(); SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) static void exit_critical_with_primask(CORE_irqState_t primask_state); +// Exit critical section and re-enter by using two funtion above. +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +static CORE_irqState_t yield_critical_with_primask(CORE_irqState_t primask_state); + /******************************************************************************* ************************** GLOBAL FUNCTIONS ******************************* ******************************************************************************/ @@ -237,7 +200,7 @@ sl_status_t sl_power_manager_init(void) #if (SL_POWER_MANAGER_DEBUG == 1) sli_power_manager_debug_init(); #endif - sl_slist_init(&power_manager_em_transition_event_list); + sli_power_manager_em_transition_event_list_init(); #if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) // If lowest energy mode is not restricted to EM1, determine and set lowest energy mode @@ -321,7 +284,7 @@ void sl_power_manager_sleep(void) #endif if (is_sleeping_waiting_for_clock_restore == false) { // But only notify if we are not in the process of waiting for the HF oscillators restore. - power_manager_notify_em_transition(current_em, lowest_em); + sli_power_manager_notify_em_transition(current_em, lowest_em); } current_em = lowest_em; // Keep new active energy mode } @@ -361,8 +324,7 @@ void sl_power_manager_sleep(void) // For internal Silicon Labs use only sli_power_manager_on_wakeup(); - exit_critical_with_primask(primask_state); - primask_state = enter_critical_with_primask(); + primask_state = yield_critical_with_primask(primask_state); // In case the HF restore was completed from the HFXO ISR, // and notification not done elsewhere, do it here @@ -370,7 +332,7 @@ void sl_power_manager_sleep(void) is_restored_from_hfxo_isr_internal = false; if (current_em == waiting_clock_restore_from_em) { current_em = SL_POWER_MANAGER_EM1; - power_manager_notify_em_transition(waiting_clock_restore_from_em, SL_POWER_MANAGER_EM1); + sli_power_manager_notify_em_transition(waiting_clock_restore_from_em, SL_POWER_MANAGER_EM1); } } @@ -392,8 +354,7 @@ void sl_power_manager_sleep(void) // If possible, go back to sleep in EM1 while waiting for HF accuracy restore while (!sli_power_manager_is_high_freq_accuracy_clk_ready(false)) { sli_power_manager_apply_em(SL_POWER_MANAGER_EM1); - exit_critical_with_primask(primask_state); - primask_state = enter_critical_with_primask(); + primask_state = yield_critical_with_primask(primask_state); } sli_power_manager_restore_states(); is_states_saved = false; @@ -401,22 +362,36 @@ void sl_power_manager_sleep(void) evaluate_wakeup(SL_POWER_MANAGER_EM0); #else + bool first_iteration = true; current_em = SL_POWER_MANAGER_EM1; // Notify listeners of transition to EM1 - power_manager_notify_em_transition(SL_POWER_MANAGER_EM0, SL_POWER_MANAGER_EM1); + sli_power_manager_notify_em_transition(SL_POWER_MANAGER_EM0, SL_POWER_MANAGER_EM1); + do { // Get lowest EM lowest_em = get_lowest_em(); + if (first_iteration == true + && lowest_em > SL_POWER_MANAGER_EM1) { + // Hook function for specific operations when we enter sleep with no EM1 requirement. + // Even though deepsleep is not entered, additional operations to reduce power can be perfomed. + sli_power_manager_em1hclkdiv_presleep_operations(); + first_iteration = false; + } + // Apply EM1 energy mode // Lowest EM is passed so that further actions can be taking by the HAL based on the EM requirements // but only EM1 sleep will be entered. sli_power_manager_apply_em(lowest_em); - exit_critical_with_primask(primask_state); - primask_state = enter_critical_with_primask(); + primask_state = yield_critical_with_primask(primask_state); } while (sl_power_manager_sleep_on_isr_exit() == true); + + if (first_iteration == false) { + // Since the lowest_em can change inside ISR, we don't use it for the condition check. + sli_power_manager_em1hclkdiv_postsleep_operations(); + } #endif #if defined(SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN) && (SL_POWER_MANAGER_EXECUTION_MODES_FEATURE_EN == 1) @@ -424,7 +399,7 @@ void sl_power_manager_sleep(void) #endif // Indicate back to EM0 - power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM0); + sli_power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM0); current_em = SL_POWER_MANAGER_EM0; sli_power_manager_resume_log_transmission(); @@ -456,11 +431,16 @@ void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, // Cannot increment above 255 (wraparound not allowed) EFM_ASSERT(!((requirement_em_table[em - 1] == UINT8_MAX) && (add == true))); + if ((requirement_em_table[em - 1] == UINT8_MAX) && (add == true)) { + return; + } // Cannot decrement below 0 (wraparound not allowed) EFM_ASSERT(!((requirement_em_table[em - 1] == 0) && (add == false))); - + if ((requirement_em_table[em - 1] == 0) && (add == false)) { + return; + } // Increment (add) or decrement (remove) energy mode counter. - requirement_em_table[em - 1] += (add) ? 1 : -1; + requirement_em_table[em - 1] += add ? 1 : -1; #if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) if (add == true @@ -482,7 +462,7 @@ void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, } if (current_em != lowest_em) { - power_manager_notify_em_transition(current_em, lowest_em); + sli_power_manager_notify_em_transition(current_em, lowest_em); current_em = lowest_em; // Keep new active energy mode } } @@ -506,14 +486,21 @@ void sli_power_manager_update_hf_clock_settings_preservation_requirement(bool ad CORE_ENTER_CRITICAL(); // Cannot increment above 255 (wraparound not allowed) EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == UINT8_MAX) && (add == true))); + if ((requirement_high_accuracy_hf_clock_counter == UINT8_MAX) && (add == true)) { + CORE_EXIT_CRITICAL(); + return; + } // Cannot decrement below 0 (wraparound not allowed) EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == 0) && (add == false))); - + if ((requirement_high_accuracy_hf_clock_counter == 0) && (add == false)) { + CORE_EXIT_CRITICAL(); + return; + } // Cannot add requirement if the "normal" clock settings are not currently applied EFM_ASSERT(!((current_em > SL_POWER_MANAGER_EM2) && (add == true))); // Increment (add) or decrement (remove) energy mode counter. - requirement_high_accuracy_hf_clock_counter += (add) ? 1 : -1; + requirement_high_accuracy_hf_clock_counter += add ? 1 : -1; // Save if the requirement is back to zero. requirement_high_accuracy_hf_clock_back_to_zero = (requirement_high_accuracy_hf_clock_counter == 0) ? true : false; @@ -616,34 +603,6 @@ bool sli_power_manager_get_clock_restore_status(void) } #endif -/***************************************************************************//** - * Registers a callback to be called on given Energy Mode transition(s). - * - * @note Adding/Removing requirement(s) from the callback is not supported. - ******************************************************************************/ -void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, - const sl_power_manager_em_transition_event_info_t *event_info) -{ - CORE_DECLARE_IRQ_STATE; - - event_handle->info = (sl_power_manager_em_transition_event_info_t *)event_info; - CORE_ENTER_CRITICAL(); - sl_slist_push(&power_manager_em_transition_event_list, &event_handle->node); - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * Unregisters an event callback handle on Energy mode transition. - ******************************************************************************/ -void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - sl_slist_remove(&power_manager_em_transition_event_list, &event_handle->node); - CORE_EXIT_CRITICAL(); -} - /***************************************************************************//** * Get configurable overhead value for early restore time in Sleeptimer ticks * when a schedule wake-up is set. @@ -759,34 +718,6 @@ uint32_t sli_power_manager_convert_delay_us_to_tick(uint32_t time_us) } #endif -/***************************************************************************//** - * Last-chance check before sleep. - * - * @return True, if the system should actually sleep. - * False, if not. - * - * @note This is the fallback implementation of the callback, it can be - * overridden by the application or other components. - ******************************************************************************/ -__WEAK bool sl_power_manager_is_ok_to_sleep(void) -{ - return true; -} - -/***************************************************************************//** - * Check if the MCU can sleep after an interrupt. - * - * @return True, if the system can sleep after the interrupt. - * False, otherwise. - * - * @note This is the fallback implementation of the callback, it can be - * overridden by the application or other components. - ******************************************************************************/ -__WEAK bool sl_power_manager_sleep_on_isr_exit(void) -{ - return false; -} - /**************************************************************************//** * Determines if the HFXO interrupt was part of the last wake-up and/or if * the HFXO early wakeup expired during the last ISR @@ -836,8 +767,9 @@ static sl_power_manager_em_t get_lowest_em(void) sl_power_manager_em_t em; // Retrieve lowest Energy mode allowed given the requirements - for (em_ix = 1; (em_ix < 3) && (requirement_em_table[em_ix - 1] == 0); em_ix++) { - ; + em_ix = 1; + while ((em_ix < 3) && (requirement_em_table[em_ix - 1] == 0)) { + em_ix++; } em = (sl_power_manager_em_t)em_ix; @@ -845,68 +777,6 @@ static sl_power_manager_em_t get_lowest_em(void) return em; } -/***************************************************************************//** - * Notify subscribers about energy mode transition. - * - * @param from Energy mode from which CPU comes from. - * - * @param to Energy mode to which CPU is going to. - ******************************************************************************/ -static void power_manager_notify_em_transition(sl_power_manager_em_t from, - sl_power_manager_em_t to) -{ - sl_power_manager_em_transition_event_handle_t *handle; - sl_power_manager_em_transition_event_t transition = 0; - - switch (to) { - case SL_POWER_MANAGER_EM0: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0; - break; - - case SL_POWER_MANAGER_EM1: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1; - break; - - case SL_POWER_MANAGER_EM2: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2; - break; - - case SL_POWER_MANAGER_EM3: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3; - break; - - default: - EFM_ASSERT(0); - } - - switch (from) { - case SL_POWER_MANAGER_EM0: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0; - break; - - case SL_POWER_MANAGER_EM1: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1; - break; - - case SL_POWER_MANAGER_EM2: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2; - break; - - case SL_POWER_MANAGER_EM3: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3; - break; - - default: - EFM_ASSERT(0); - } - - SL_SLIST_FOR_EACH_ENTRY(power_manager_em_transition_event_list, handle, sl_power_manager_em_transition_event_handle_t, node) { - if ((handle->info->event_mask & transition) > 0) { - handle->info->on_event(from, to); - } - } -} - /***************************************************************************//** * Enter critical section by disabling interrupts using PriMask. * @@ -932,8 +802,24 @@ static void exit_critical_with_primask(CORE_irqState_t primask_state) { if (primask_state == 0U) { __enable_irq(); + __ISB(); } } + +/***************************************************************************//** + * Exit critical section and re-enter by using PriMask. + * + * @param[in] primask_state Initial primask state. + * + * @return Initial primask state. + ******************************************************************************/ +static CORE_irqState_t yield_critical_with_primask(CORE_irqState_t primask_state) +{ + exit_critical_with_primask(primask_state); + return enter_critical_with_primask(); +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) /***************************************************************************//** * Evaluates scheduled wakeup and restart timer based on the wakeup time. * If the remaining time is shorter than the wakeup time then add a requirement @@ -941,7 +827,6 @@ static void exit_critical_with_primask(CORE_irqState_t primask_state) * * @note Must be called in a critical section. ******************************************************************************/ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) static void evaluate_wakeup(sl_power_manager_em_t to) { sl_status_t status; @@ -1025,15 +910,20 @@ static void update_em1_requirement(bool add) { // Cannot increment above 255 (wraparound not allowed) EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == UINT8_MAX) && (add == true))); + if ((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == UINT8_MAX) && (add == true)) { + return; + } // Cannot decrement below 0 (wraparound not allowed) EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == 0) && (add == false))); - + if ((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == 0) && (add == false)) { + return; + } #if (SL_POWER_MANAGER_DEBUG == 1) sli_power_manager_debug_log_em_requirement(SL_POWER_MANAGER_EM1, add, "PM_INTERNAL_EM1_REQUIREMENT"); #endif // Increment (add) or decrement (remove) energy mode counter. - requirement_em_table[SL_POWER_MANAGER_EM1 - 1] += (add) ? 1 : -1; + requirement_em_table[SL_POWER_MANAGER_EM1 - 1] += add ? 1 : -1; // In rare occasions a clock restore must be started here: // - An asynchronous event wake-up the system from deepsleep very near the early wake-up event, @@ -1110,7 +1000,7 @@ static void clock_restore(void) is_states_saved = false; // We do the notification only when the restore is completed. - power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM1); + sli_power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM1); current_em = SL_POWER_MANAGER_EM1; // Keep new active energy mode } else { // If the HF oscillator is not yet ready, we will go back to sleep while waiting @@ -1198,68 +1088,6 @@ void sli_hfxo_notify_ready_for_power_manager_from_prs(void) #endif } -/***************************************************************************//** - * Enable or disable fast wake-up in EM2 and EM3 - * - * @note Will also update the wake up time from EM2 to EM0. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) -{ -#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - - sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(enable); - - CORE_EXIT_CRITICAL(); -#else - (void)enable; -#endif -} - -/****************************************************************************** - * Event called before entering EM4 sleep. - *****************************************************************************/ -SL_WEAK void sl_power_manager_em4_presleep_hook(void) -{ -} - -/***************************************************************************//** - * Enter energy mode 4 (EM4). - * - * @note You should not expect to return from this function. Once the device - * enters EM4, only a power on reset or external reset pin can wake the - * device. - * - * @note On xG22 devices, this function re-configures the IADC if EM4 entry - * is possible. - ******************************************************************************/ -__NO_RETURN void sl_power_manager_enter_em4(void) -{ - sli_power_manager_enter_em4(); - for (;; ) { - // __NO_RETURN - } -} - -/***************************************************************************//** - * When EM4 pin retention is set to power_manager_pin_retention_latch, - * then pins are retained through EM4 entry and wakeup. The pin state is - * released by calling this function. The feature allows peripherals or - * GPIO to be re-initialized after EM4 exit (reset), and when - * initialization is done, this function can release pins and return - * control to the peripherals or GPIO. - ******************************************************************************/ -void sl_power_manager_em4_unlatch_pin_retention(void) -{ - sli_power_manager_em4_unlatch_pin_retention(); -} - /***************************************************************************//** * Returns current energy mode. ******************************************************************************/ diff --git a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_debug.c b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_debug.c similarity index 95% rename from simplicity_sdk/platform/service/power_manager/src/sl_power_manager_debug.c rename to simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_debug.c index 10405f935..e0f87fff6 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_debug.c +++ b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_debug.c @@ -44,11 +44,9 @@ static sli_power_debug_requirement_entry_t power_debug_entry_table[SL_POWER_MAN static sl_slist_node_t *power_debug_free_entry_list = NULL; static bool power_debug_ran_out_of_entry = false; -#if (!defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) static void power_manager_log_add_requirement(sl_slist_node_t **p_list, bool add, const char *name); -#endif // !(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) /***************************************************************************//** * Print a fancy table that describes the current requirements on each energy @@ -91,7 +89,6 @@ void sli_power_manager_debug_init(void) } } -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) /***************************************************************************//** * Log requirement to a list * @@ -140,7 +137,6 @@ static void power_manager_log_add_requirement(sl_slist_node_t **p_list, sl_slist_push(&power_debug_free_entry_list, &entry_remove->node); } } -#endif // !(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) #endif // SL_POWER_MANAGER_DEBUG #undef sli_power_manager_debug_log_em_requirement @@ -157,7 +153,7 @@ void sli_power_manager_debug_log_em_requirement(sl_power_manager_em_t em, bool add, const char *name) { -#if (!defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) && (SL_POWER_MANAGER_DEBUG == 1)) +#if (SL_POWER_MANAGER_DEBUG == 1) if (em != SL_POWER_MANAGER_EM0) { power_manager_log_add_requirement(&power_manager_debug_requirement_em_table[em - 1], add, name); } diff --git a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_hal_s2.c b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c similarity index 73% rename from simplicity_sdk/platform/service/power_manager/src/sl_power_manager_hal_s2.c rename to simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c index d8cdfcfd9..9909d78d5 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_hal_s2.c +++ b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c @@ -35,6 +35,7 @@ #include "em_cmu.h" #include "sl_assert.h" #include "sl_power_manager.h" +#include "sli_power_manager.h" #include "sli_power_manager_private.h" #include "sl_sleeptimer.h" #include "sli_sleeptimer.h" @@ -99,25 +100,6 @@ #define _HFXO_DBGSTATUS_STARTUPDONE_SHIFT 1 /**< Shift value for HFXO_STARTUPDONE */ #define _HFXO_DBGSTATUS_STARTUPDONE_MASK 0x2UL /**< Bit mask for HFXO_STARTUPDONE */ -#if defined(WDOG_PRESENT) -// Macros to determine if WDOG instances are clocked or not - -#if defined(CMU_CLKEN0_WDOG0) -#define WDOG0_CLOCK_ENABLED_BIT (CMU->CLKEN0 & CMU_CLKEN0_WDOG0) -#else -// There's no CMU->CLKEN1 so assume the WDOG0 is clocked -#define WDOG0_CLOCK_ENABLED_BIT 1 -#endif - -#if defined(CMU_CLKEN1_WDOG1) -#define WDOG1_CLOCK_ENABLED_BIT (CMU->CLKEN1 & CMU_CLKEN1_WDOG1) -#else -// There's no CMU->CLKEN1 so assume the WDOG1 is clocked -#define WDOG1_CLOCK_ENABLED_BIT 1 -#endif - -#endif - /******************************************************************************* ******************************* MACROS ************************************* ******************************************************************************/ @@ -132,7 +114,7 @@ * - Tref is the reference clock period. *******************************************************************************/ #define DPLL_LOCKING_DELAY_US_FUNCTION(M, freq_ref) \ - ((uint64_t)(DPLL_COARSECOUNT_VALUE * ((M) +1)) * 1000000 + ((freq_ref) - 1)) / (freq_ref) + (uint32_t)(((uint64_t)(DPLL_COARSECOUNT_VALUE * ((M) +1)) * 1000000 + ((freq_ref) - 1)) / (freq_ref)) /******************************************************************************* *************************** LOCAL VARIABLES ******************************** @@ -178,11 +160,6 @@ static uint32_t hfxo_wakeup_time_tick = 0; #endif #endif -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ -static bool is_em4_blocked(void); - /***************************************************************************//** * Do some hardware initialization if necessary. ******************************************************************************/ @@ -226,15 +203,15 @@ void sli_power_manager_init_hardware(void) || ((CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) == CMU_EM01GRPACLKCTRL_CLKSEL_HFXO)); #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - is_hf_x_oscillator_used |= (CMU->RADIOCLKCTRL & _CMU_RADIOCLKCTRL_EN_MASK) != 0; + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->RADIOCLKCTRL & _CMU_RADIOCLKCTRL_EN_MASK) != 0); #endif #if defined(CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO) - is_hf_x_oscillator_used |= ((CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO); + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO); #endif #if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO) - is_hf_x_oscillator_used |= ((CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO); + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO); #endif #if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) @@ -247,7 +224,7 @@ void sli_power_manager_init_hardware(void) #endif if (is_dpll_used && !is_hf_x_oscillator_used) { - is_hf_x_oscillator_used |= (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) == _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; + is_hf_x_oscillator_used = is_hf_x_oscillator_used || ((CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) == _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO); } // Calculate DPLL locking delay from its configuration @@ -282,127 +259,6 @@ void sli_power_manager_init_hardware(void) #endif } -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) - -/* The following section provides an optimization to improve peak current - * consumption on xG22 devices. - */ - -// ADC clock frequency (source and after prescale) -#define CLK_SRC_ADC_FREQ 9600000 // CLK_SRC_ADC -#define CLK_ADC_FREQ 1000000 // CLK_ADC - -extern void sli_delay_loop(uint32_t cycles); - -uint32_t * dcdc_test_addr = (uint32_t *)(DCDC_NS_BASE + 0x80); -uint32_t ipkval = 7; -uint32_t ipktimeout = 1; - -/* Pulse generation sequence TOCTRIG (bit 3) TOCMODE (bit 2)*/ -uint32_t cmd[2] = { (1 << 2) | (1 << 3), (1 << 2) }; - -/***************************************************************************//** - * The voltage of Dvdd is ramped up to VMCU by sending pulses to a DCDC test - * register. These pulses are delayed, and ipkval and ipktimeout are tuned - * such that the voltage at Dvdd increases gradually to the voltage level of - * VMCU. Using the IADC, once Dvdd has gotten sufficiently close to VMCU, - * the DCDC peripheral is then switched into bypass mode. The IADC is used to - * detect this by sampling the voltage of Dvdd periodically, and calculating the - * difference between samples, when the difference is within some margin of zero - * then we know that the ramp sequence has reached a plateau. - ******************************************************************************/ -static void ramp_dvdd_and_switch_to_dcdc_bypass_mode(void) -{ - // Initialize the IADC for the purposes of detecting when the Dvdd ramp - // reaches a plateau. - IADC_Init_t init = IADC_INIT_DEFAULT; - IADC_AllConfigs_t initAllConfigs = IADC_ALLCONFIGS_DEFAULT; - IADC_InitSingle_t initSingle = IADC_INITSINGLE_DEFAULT; - IADC_SingleInput_t initSingleInput = IADC_SINGLEINPUT_DEFAULT; - CMU_ClockEnable(cmuClock_IADC0, true); - - init.srcClkPrescale = IADC_calcSrcClkPrescale(IADC0, CLK_SRC_ADC_FREQ, 0); - initAllConfigs.configs[0].reference = iadcCfgReferenceInt1V2; - initAllConfigs.configs[0].vRef = 1210; - initAllConfigs.configs[0].analogGain = iadcCfgAnalogGain1x; - initAllConfigs.configs[0].digAvg = iadcDigitalAverage1; - initAllConfigs.configs[0].adcClkPrescale = - IADC_calcAdcClkPrescale(IADC0, - CLK_ADC_FREQ, - 0, - iadcCfgModeNormal, - init.srcClkPrescale); - init.warmup = iadcWarmupKeepWarm; - - IADC_reset(IADC0); - CMU_ClockSelectSet(cmuClock_IADCCLK, cmuSelect_EM01GRPACLK); - initSingle.triggerAction = iadcTriggerActionContinuous; - initSingle.alignment = iadcAlignRight12; - initSingleInput.compare = false; // Disable Window CMP - initSingleInput.posInput = iadcPosInputDvdd; - IADC_init(IADC0, &init, &initAllConfigs); - IADC_initSingle(IADC0, &initSingle, &initSingleInput); - - // Start capturing - IADC_command(IADC0, iadcCmdStartSingle); - - // Initialize DCDC peak current value and timeout to reach peak current value - DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); - DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); - - /* Generate pulses */ - uint32_t iter = 1U; - IADC_Result_t prev_result; - volatile IADC_Result_t current_result = IADC_readSingleResult(IADC0); - while (true) { - // If the algorithm doesn't converge after 500 pulses, switch to dcdc - // bypass anyways. - if (iter >= 500) { - DCDC->CTRL_CLR = DCDC_CTRL_MODE; - EFM_ASSERT(false); - return; - } - - /* Pulse generation sequence TOCTRIG (bit 3) TOCMODE (bit 2)*/ - *dcdc_test_addr = cmd[0]; - *dcdc_test_addr = cmd[1]; - - // In DCDC mode, MCU input voltage VREGVDD cannot be directly measured, so - // we can't know what the target DVDD voltage is. Instead, since DVDD - // ramp-up should follow a RC charge curve, measure DVDD and keep charging - // until the delta between measures is smaller than the set tolerance. - if (iter % 20U == 0U) { - prev_result = current_result; - current_result = IADC_readSingleResult(IADC0); - if ( abs((int32_t)(current_result.data - prev_result.data)) < SL_POWER_MANAGER_RAMP_DVDD_TOLERANCE ) { - DCDC->CTRL_CLR = DCDC_CTRL_MODE; - return; - } - } - - if (DCDC->IF & DCDC_IF_TMAX) { - if (ipkval) { - ipkval--; // DCDC peak current value - } - - if (ipktimeout < 7) { - ipktimeout++; // Timeout to reach peak current value - } - - DCDC->EM01CTRL0 = (DCDC->EM01CTRL0 & ~_DCDC_EM01CTRL0_IPKVAL_MASK) | (ipkval << 0); - DCDC->CTRL = (DCDC->CTRL & ~_DCDC_CTRL_IPKTMAXCTRL_MASK) | (ipktimeout << 4); - - DCDC->IF_CLR = DCDC_IF_TMAX; - } - - /* delay for 8 clock cycles */ - sli_delay_loop(8); - iter++; - } -} - -#endif - /***************************************************************************//** * Enable or disable fast wake-up in EM2 and EM3. ******************************************************************************/ @@ -486,6 +342,7 @@ void EMU_EM23PresleepHook(void) if (is_dpll_used) { DPLL0->EN_CLR = DPLL_EN_EN; while ((DPLL0->EN & _DPLL_EN_DISABLING_MASK) != 0) { + // Wait for DPLL to be disabled. } } #endif @@ -661,6 +518,7 @@ void sli_power_manager_restore_states(void) if (is_dpll_used) { DPLL0->EN_SET = DPLL_EN_EN; while ((DPLL0->STATUS & _DPLL_STATUS_RDY_MASK) == 0U) { + // Wait for DPLL to be ready. } } #endif @@ -813,6 +671,7 @@ void sli_power_manager_set_high_accuracy_hf_clock_as_used(void) ******************************************************************************/ void sli_power_manager_low_frequency_restore(void) { + // Nothing to do as on-demand feature will enable the LF oscillators automatically. } /***************************************************************************//** @@ -827,106 +686,21 @@ bool sli_power_manager_is_high_freq_accuracy_clk_used(void) } #endif -/***************************************************************************//** - * update energy mode 4 configurations. +#if defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * HAL hook function for pre EM1HCLKDIV sleep. ******************************************************************************/ -void sli_power_manager_init_em4(void) +void sli_power_manager_em1hclkdiv_presleep_operations(void) { - EMU_EM4Init_TypeDef em4_init = EMU_EM4INIT_DEFAULT; - em4_init.pinRetentionMode = (EMU_EM4PinRetention_TypeDef)SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE; - EMU_EM4Init(&em4_init); + // No operations to do before EM1HCLKDIV sleep on series 2 devices } -/***************************************************************************//** - * Returns true if em4 entry is blocked by a watchdog peripheral. +/******************************************************************************* + * HAL hook function for post EM1HCLKDIV sleep. ******************************************************************************/ -static bool is_em4_blocked(void) +void sli_power_manager_em1hclkdiv_postsleep_operations(void) { -#if defined(WDOG_PRESENT) -#if WDOG_COUNT > 0 - if ( WDOG0_CLOCK_ENABLED_BIT && (WDOG0->CFG & WDOG_CFG_EM4BLOCK) && (WDOG0->EN & WDOG_EN_EN) ) { - return true; - } -#endif -#if WDOG_COUNT > 1 - if ( WDOG1_CLOCK_ENABLED_BIT && (WDOG1->CFG & WDOG_CFG_EM4BLOCK) && (WDOG1->EN & WDOG_EN_EN) ) { - return true; - } -#endif -#endif - return false; + // No operations to do before EM1HCLKDIV sleep on series 2 devices } - -/***************************************************************************//** - * Enter energy mode 4 (EM4). - * - * @note You should not expect to return from this function. Once the device - * enters EM4, only a power on reset or external reset pin can wake the - * device. - * - * @note On xG22 devices, this function re-configures the IADC if EM4 entry - * is possible. - ******************************************************************************/ -__NO_RETURN void sli_power_manager_enter_em4(void) -{ - // Make sure that we are not interrupted while we are entering em4 - CORE_CRITICAL_IRQ_DISABLE(); - - EFM_ASSERT(is_em4_blocked() == false); - -#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) - sli_metric_em4_wake_init(); -#endif - - uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); - uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); - - // Make sure that the register write lock is disabled. - EMU_Unlock(); - -#if defined(_DCDC_IF_EM4ERR_MASK) - // Workaround for bug that may cause a Hard Fault on EM4 entry - CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); - // The buck DC-DC is available in all energy modes except for EM4. - // The DC-DC converter must first be turned off and switched over to bypass mode. -#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) - #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) && (SL_POWER_MANAGER_RAMP_DVDD_EN == 1) - ramp_dvdd_and_switch_to_dcdc_bypass_mode(); - #else - EMU_DCDCModeSet(emuDcdcMode_Bypass); - #endif #endif -#endif - - sl_power_manager_em4_presleep_hook(); - - for (uint8_t i = 0; i < 4; i++) { - EMU->EM4CTRL = em4seq2; - EMU->EM4CTRL = em4seq3; - } - EMU->EM4CTRL = em4seq2; - - for (;; ) { - // __NO_RETURN - } -} - -/***************************************************************************//** - * When EM4 pin retention is set to power_manager_pin_retention_latch, - * then pins are retained through EM4 entry and wakeup. The pin state is - * released by calling this function. The feature allows peripherals or - * GPIO to be re-initialized after EM4 exit (reset), and when - * initialization is done, this function can release pins and return - * control to the peripherals or GPIO. - ******************************************************************************/ -void sli_power_manager_em4_unlatch_pin_retention(void) -{ -#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) - EMU->CMD = EMU_CMD_EM4UNLATCH; -#endif -} - #endif diff --git a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_hal_sixg301.c b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_sixg301.c similarity index 63% rename from simplicity_sdk/platform/service/power_manager/src/sl_power_manager_hal_sixg301.c rename to simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_sixg301.c index 5fa4d5e0d..dea193639 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sl_power_manager_hal_sixg301.c +++ b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sl_power_manager_hal_sixg301.c @@ -38,45 +38,19 @@ #include "sl_component_catalog.h" #endif #include "sl_clock_manager.h" +#include "sli_clock_manager_hal.h" #include #if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) #warning "SIXG301 devices only support the power_manager_no_deepsleep sub-component of Power Manager." #endif -/******************************************************************************* - ******************************* DEFINES ************************************ - ******************************************************************************/ - -#if defined(WDOG_PRESENT) -// Macros to determine if WDOG instances are clocked or not - -#if defined(CMU_CLKEN0_WDOG0) -#define WDOG0_CLOCK_ENABLED_BIT (CMU->CLKEN0 & CMU_CLKEN0_WDOG0) -#else -// There's no CMU->CLKEN1 so assume the WDOG0 is clocked -#define WDOG0_CLOCK_ENABLED_BIT 1 -#endif - -#if defined(CMU_CLKEN1_WDOG1) -#define WDOG1_CLOCK_ENABLED_BIT (CMU->CLKEN1 & CMU_CLKEN1_WDOG1) -#else -// There's no CMU->CLKEN1 so assume the WDOG1 is clocked -#define WDOG1_CLOCK_ENABLED_BIT 1 -#endif - -#endif - /******************************************************************************* *************************** LOCAL VARIABLES ******************************** ******************************************************************************/ static uint32_t sysclk_prescalers_value; - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ -static bool is_em4_blocked(void); +sl_oscillator_t qspi_reference_clock; /***************************************************************************//** * Do some hardware initialization if necessary. @@ -131,7 +105,7 @@ void sli_power_manager_apply_em(sl_power_manager_em_t em) // Case where SYSCLK frequency can allow to have HCLK = SYSCLK/16 + PCLK/2 clk_division_value |= CMU_SYSCLKCTRL_PCLKPRESC_DIV2; } else { - // PCLK divider must be set to 1 to not go bollow 1MHz for LSPCLK branch + // PCLK divider must be set to 1 to not go below 1MHz for LSPCLK branch. clk_division_value |= CMU_SYSCLKCTRL_PCLKPRESC_DIV1; } } else if (sysclk_freq >= 16000000) { @@ -148,12 +122,12 @@ void sli_power_manager_apply_em(sl_power_manager_em_t em) clk_division_value = CMU_SYSCLKCTRL_HCLKPRESC_DIV1 | CMU_SYSCLKCTRL_PCLKPRESC_DIV1; } // Apply HCLK and PCLK divisions - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~(_CMU_SYSCLKCTRL_HCLKPRESC_MASK & _CMU_SYSCLKCTRL_PCLKPRESC_MASK)) | clk_division_value; + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~(_CMU_SYSCLKCTRL_HCLKPRESC_MASK | _CMU_SYSCLKCTRL_PCLKPRESC_MASK)) | clk_division_value; // Enter sleep mode SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; __WFI(); // Restore HCLK and PCLK prescaler - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~(_CMU_SYSCLKCTRL_HCLKPRESC_MASK & _CMU_SYSCLKCTRL_PCLKPRESC_MASK)) | sysclk_prescalers_value; + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~(_CMU_SYSCLKCTRL_HCLKPRESC_MASK | _CMU_SYSCLKCTRL_PCLKPRESC_MASK)) | sysclk_prescalers_value; break; #endif @@ -173,85 +147,32 @@ uint32_t sli_power_manager_get_wakeup_process_time_overhead(void) return 0; } -/***************************************************************************//** - * Update Energy Mode 4 configurations. - ******************************************************************************/ -void sli_power_manager_init_em4(void) -{ - EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) - | (uint32_t)SL_POWER_MANAGER_INIT_EMU_EM4_PIN_RETENTION_MODE; -} - -/***************************************************************************//** - * Returns true if em4 entry is blocked by a watchdog peripheral. - ******************************************************************************/ -static bool is_em4_blocked(void) -{ -#if defined(WDOG_PRESENT) -#if WDOG_COUNT > 0 - if ( WDOG0_CLOCK_ENABLED_BIT && (WDOG0->CFG & WDOG_CFG_EM4BLOCK) && (WDOG0->EN & WDOG_EN_EN) ) { - return true; - } -#endif -#if WDOG_COUNT > 1 - if ( WDOG1_CLOCK_ENABLED_BIT && (WDOG1->CFG & WDOG_CFG_EM4BLOCK) && (WDOG1->EN & WDOG_EN_EN) ) { - return true; - } -#endif -#endif - return false; -} - -/***************************************************************************//** - * Enter energy mode 4 (EM4). - * - * @note You should not expect to return from this function. Once the device - * enters EM4, only a power on reset or external reset pin can wake the - * device. +/******************************************************************************* + * HAL hook function for pre EM1HCLKDIV sleep. ******************************************************************************/ -__NO_RETURN void sli_power_manager_enter_em4(void) +void sli_power_manager_em1hclkdiv_presleep_operations(void) { - // Make sure that we are not interrupted while we are entering em4 - CORE_CRITICAL_IRQ_DISABLE(); - - EFM_ASSERT(is_em4_blocked() == false); - -#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) - sli_metric_em4_wake_init(); +#if defined(SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN) && (SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN == 1) + sl_status_t status; + // Save current QSPI reference clock. + status = sli_clock_manager_get_current_qspi_clk(&qspi_reference_clock); + EFM_ASSERT(status == SL_STATUS_OK); + // Update QSPI clock source. + status = sli_clock_manager_hal_update_qspi_clk(SL_OSCILLATOR_FSRCO); + EFM_ASSERT(status == SL_STATUS_OK); #endif - uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); - uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); - - // Make sure that the register write lock is disabled. - EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; - - sl_power_manager_em4_presleep_hook(); - - for (uint8_t i = 0; i < 4; i++) { - EMU->EM4CTRL = em4seq2; - EMU->EM4CTRL = em4seq3; - } - EMU->EM4CTRL = em4seq2; - - for (;; ) { - // __NO_RETURN - } } -/***************************************************************************//** - * When EM4 pin retention is set to power_manager_pin_retention_latch, - * then pins are retained through EM4 entry and wakeup. The pin state is - * released by calling this function. The feature allows peripherals or - * GPIO to be re-initialized after EM4 exit (reset), and when - * initialization is done, this function can release pins and return - * control to the peripherals or GPIO. +/******************************************************************************* + * HAL hook function for post EM1HCLKDIV sleep. ******************************************************************************/ -void sli_power_manager_em4_unlatch_pin_retention(void) +void sli_power_manager_em1hclkdiv_postsleep_operations(void) { -#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) - EMU->CMD = EMU_CMD_EM4UNLATCH; +#if defined(SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN) && (SL_POWER_MANAGER_QSPI_CLOCK_SWITCH_IN_SLEEP_EN == 1) + sl_status_t status; + // Restore original QSPI clock source. + status = sli_clock_manager_hal_update_qspi_clk(qspi_reference_clock); + EFM_ASSERT(status == SL_STATUS_OK); #endif } -#endif +#endif // _SILICON_LABS_32B_SERIES_3 diff --git a/simplicity_sdk/platform/service/power_manager/src/sli_power_manager_private.h b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sli_power_manager_private.h similarity index 79% rename from simplicity_sdk/platform/service/power_manager/src/sli_power_manager_private.h rename to simplicity_sdk/platform/service/power_manager/src/sleep_loop/sli_power_manager_private.h index 0331ed73b..249313f87 100644 --- a/simplicity_sdk/platform/service/power_manager/src/sli_power_manager_private.h +++ b/simplicity_sdk/platform/service/power_manager/src/sleep_loop/sli_power_manager_private.h @@ -122,13 +122,6 @@ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) bool sli_power_manager_is_high_freq_accuracy_clk_used(void); #endif -/***************************************************************************//** - * Enable or disable fast wake-up in EM2 and EM3 - * - * @note Will also update the wake up time from EM2 to EM0. - ******************************************************************************/ -void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); - /******************************************************************************* * Gets the delay associated the wake-up process from EM23. * @@ -148,39 +141,23 @@ uint32_t sli_power_manager_get_wakeup_process_time_overhead(void); bool sli_power_manager_get_clock_restore_status(void); #endif -/***************************************************************************//** - * Update Energy Mode 4 configurations. - ******************************************************************************/ -void sli_power_manager_init_em4(void); - -/***************************************************************************//** - * Enter energy mode 4 (EM4). - * - * @note You should not expect to return from this function. Once the device - * enters EM4, only a power on reset or external reset pin can wake the - * device. +#if defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * HAL hook function for pre EM1HCLKDIV sleep. * - * @note On xG22 devices, this function re-configures the IADC if EM4 entry - * is possible. - ******************************************************************************/ -void sli_power_manager_enter_em4(void); - -/***************************************************************************//** - * When EM4 pin retention is set to power_manager_pin_retention_latch, - * then pins are retained through EM4 entry and wakeup. The pin state is - * released by calling this function. The feature allows peripherals or - * GPIO to be re-initialized after EM4 exit (reset), and when - * initialization is done, this function can release pins and return - * control to the peripherals or GPIO. + * @note FOR INTERNAL USE ONLY. ******************************************************************************/ -void sli_power_manager_em4_unlatch_pin_retention(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_em1hclkdiv_presleep_operations(void); -/***************************************************************************//** - * Fetches current energy mode +/******************************************************************************* + * HAL hook function for post EM1HCLKDIV sleep. * - * @return Returns current energy mode + * @note FOR INTERNAL USE ONLY. ******************************************************************************/ -sl_power_manager_em_t sli_power_manager_get_current_em(void); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_POWER_MANAGER, SL_CODE_CLASS_TIME_CRITICAL) +void sli_power_manager_em1hclkdiv_postsleep_operations(void); +#endif #ifdef __cplusplus } diff --git a/simplicity_sdk/platform/service/sleeptimer/inc/sl_sleeptimer.h b/simplicity_sdk/platform/service/sleeptimer/inc/sl_sleeptimer.h index 3fdf6f4ce..5ec91e718 100644 --- a/simplicity_sdk/platform/service/sleeptimer/inc/sl_sleeptimer.h +++ b/simplicity_sdk/platform/service/sleeptimer/inc/sl_sleeptimer.h @@ -153,6 +153,9 @@ sl_status_t sl_sleeptimer_init(void); * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG * or 0 for not flags. * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * * @return SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) @@ -178,6 +181,9 @@ sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG * or 0 for not flags. * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * * @return SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) @@ -203,6 +209,9 @@ sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG * or 0 for not flags. * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * * @return SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) @@ -228,6 +237,9 @@ sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *han * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG * or 0 for not flags. * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * * @return SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) @@ -243,6 +255,9 @@ sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *h * * @param handle Pointer to handle to timer. * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. + * * @return SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) @@ -259,7 +274,7 @@ sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle); * @return SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) -sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, +sl_status_t sl_sleeptimer_is_timer_running(const sl_sleeptimer_timer_handle_t *handle, bool *running); /***************************************************************************//** @@ -271,7 +286,7 @@ sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, * @return SL_STATUS_OK if successful. Error code otherwise. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) -sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, +sl_status_t sl_sleeptimer_get_timer_time_remaining(const sl_sleeptimer_timer_handle_t *handle, uint32_t *time); /**************************************************************************//** @@ -758,6 +773,9 @@ bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void); * by calling sl_sleeptimer_get_max_ms32_conversion(). * If the value passed to 'timeout_ms' is too large, * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. *****************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) __STATIC_INLINE sl_status_t sl_sleeptimer_start_timer_ms(sl_sleeptimer_timer_handle_t *handle, @@ -802,6 +820,9 @@ __STATIC_INLINE sl_status_t sl_sleeptimer_start_timer_ms(sl_sleeptimer_timer_han * by calling sl_sleeptimer_get_max_ms32_conversion(). * If the value passed to 'timeout_ms' is too large, * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. *****************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) __STATIC_INLINE sl_status_t sl_sleeptimer_restart_timer_ms(sl_sleeptimer_timer_handle_t *handle, @@ -846,6 +867,9 @@ __STATIC_INLINE sl_status_t sl_sleeptimer_restart_timer_ms(sl_sleeptimer_timer_h * by calling sl_sleeptimer_get_max_ms32_conversion(). * If the value passed to 'timeout_ms' is too large, * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, @@ -879,6 +903,9 @@ sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t * * by calling sl_sleeptimer_get_max_ms32_conversion(). * If the value passed to 'timeout_ms' is too large, * SL_STATUS_INVALID_PARAMETER will be returned. + * + * @note This function cannot be called from an interrupt with a higher + * priority than BASEPRI. ******************************************************************************/ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, @@ -933,6 +960,9 @@ uint16_t sl_sleeptimer_get_clock_accuracy(void); /// /// Timer structures must be allocated by the user. The function is called from within an interrupt handler with interrupts enabled. /// +/// As sleeptimer callback functions are executed in ISR, they should be kept simple and short. +/// For periodic timers, the sleeptimer's callbacks need to be shorter than the timer's period to allow the application to exit the interrupt context. +/// /// @n @subsection timekeeping Timekeeping /// /// A 64-bits tick counter is accessible through the @li uint64_t sl_sleeptimer_get_tick_count64(void) API. It keeps the tick count since the initialization of the driver @@ -1073,25 +1103,25 @@ uint16_t sl_sleeptimer_get_clock_accuracy(void); /// @ref sl_sleeptimer_start_timer() @n /// Start a one shot 32 bits timer. When a timer expires, a user-supplied callback function /// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for /// details of the callback prototype. /// /// @ref sl_sleeptimer_restart_timer() @n /// Restart a one shot 32 bits timer. When a timer expires, a user-supplied callback function /// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for /// details of the callback prototype. /// /// @ref sl_sleeptimer_start_periodic_timer() @n /// Start a periodic 32 bits timer. When a timer expires, a user-supplied callback function /// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for /// details of the callback prototype. /// /// @ref sl_sleeptimer_restart_periodic_timer() @n /// Restart a periodic 32 bits timer. When a timer expires, a user-supplied callback function /// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for +/// sl_sleeptimer_start_timer(). See @ref sl_sleeptimer_timer_callback_t for /// details of the callback prototype. /// /// @ref sl_sleeptimer_stop_timer() @n diff --git a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer.c b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer.c index 224f328fe..d271b66c4 100644 --- a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer.c +++ b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer.c @@ -82,7 +82,7 @@ SLEEPTIMER_ENUM(sl_sleeptimer_time_format_t) { typedef uint32_t sl_sleeptimer_tick_count_t; // Overflow counter used to provide 64-bits tick count. -static volatile uint16_t overflow_counter; +static volatile uint32_t overflow_counter; #if SL_SLEEPTIMER_WALLCLOCK_CONFIG // Current time count. @@ -126,7 +126,7 @@ SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle); SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) -static void set_comparator_for_next_timer(void); +static sl_status_t set_comparator_for_next_timer(void); SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) static void update_delta_list(void); @@ -146,6 +146,9 @@ static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, uint8_t priority, uint16_t option_flags); +SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) +static void process_expired_timer(sl_sleeptimer_timer_handle_t *timer); + SL_CODE_CLASSIFY(SL_CODE_COMPONENT_SLEEPTIMER, SL_CODE_CLASS_TIME_CRITICAL) static void update_next_timer_to_expire_is_power_manager(void); @@ -473,12 +476,12 @@ sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle) return error; } - if (set_comparator && timer_head) { - set_comparator_for_next_timer(); - } else if (!timer_head) { - sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + if (set_comparator) { + error = set_comparator_for_next_timer(); + if (error == SL_STATUS_NULL_POINTER) { + sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + } } - CORE_EXIT_CRITICAL(); return SL_STATUS_OK; @@ -487,7 +490,7 @@ sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle) /**************************************************************************//** * Gets the status of a timer. *****************************************************************************/ -sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, +sl_status_t sl_sleeptimer_is_timer_running(const sl_sleeptimer_timer_handle_t *handle, bool *running) { CORE_DECLARE_IRQ_STATE; @@ -514,7 +517,7 @@ sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, /**************************************************************************//** * Gets a 32 bits timer's time remaining. *****************************************************************************/ -sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, +sl_status_t sl_sleeptimer_get_timer_time_remaining(const sl_sleeptimer_timer_handle_t *handle, uint32_t *time) { CORE_DECLARE_IRQ_STATE; @@ -614,7 +617,7 @@ bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void) // Make sure that the Power Manager Sleeptimer is actually expired in addition // to being the next timer. - if ((next_timer_is_power_manager) + if (next_timer_is_power_manager && ((sl_sleeptimer_get_tick_count() - timer_head->timeout_expected_tc) > MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION)) { next_timer_is_power_manager = false; } @@ -1238,10 +1241,10 @@ sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, if ((tick <= UINT64_MAX / 1000) && (timer_frequency != 0u)) { if (is_power_of_2(timer_frequency)) { - *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); + *ms = (tick * (uint64_t)1000u) >> div_to_log2(timer_frequency); return SL_STATUS_OK; } else { - *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); + *ms = (tick * (uint64_t)1000u) / timer_frequency; return SL_STATUS_OK; } } else { @@ -1272,9 +1275,7 @@ void process_timer_irq(uint8_t local_flag) update_delta_list(); - if (timer_head) { - set_comparator_for_next_timer(); - } + set_comparator_for_next_timer(); } if (local_flag & SLEEPTIMER_EVENT_COMP) { @@ -1288,12 +1289,9 @@ void process_timer_irq(uint8_t local_flag) update_delta_list(); // Process all timers that have expired. - while ((timer_head) && (timer_head->delta == 0)) { + while (timer_head && (timer_head->delta == 0)) { sl_sleeptimer_timer_handle_t *temp = timer_head; current = timer_head; - int32_t periodic_correction = 0u; - int64_t timeout_temp = 0; - bool skip_remove = false; // Process timers with higher priority first while ((temp != NULL) && (temp->delta == 0)) { @@ -1304,59 +1302,12 @@ void process_timer_irq(uint8_t local_flag) } CORE_EXIT_ATOMIC(); - // Check if current periodic timer was delayed more than its actual timeout value - // and keep it at the head of the timers list if it's the case so that the - // callback function can be called the number of required time. - if (current->timeout_periodic != 0u) { - timeout_temp = current->timeout_periodic; - - periodic_correction = sleeptimer_hal_get_counter() - current->timeout_expected_tc; - if (periodic_correction > timeout_temp) { - skip_remove = true; - current->timeout_expected_tc += current->timeout_periodic; - } - } - - // Remove current timer from timer list except if the current timer is a periodic timer - // that was intentionally kept at the head of the timers list. - if (skip_remove != true) { - CORE_ENTER_ATOMIC(); - delta_list_remove_timer(current); - CORE_EXIT_ATOMIC(); - } - - // Re-insert periodic timer that was previsouly removed from the list - // and compensate for any deviation from the periodic timer frequency. - if (current->timeout_periodic != 0u && skip_remove != true) { - timeout_temp -= periodic_correction; - EFM_ASSERT(timeout_temp >= 0); - // Compensate for drift caused by ms to ticks conversion - if (current->conversion_error > 0) { - // Increment accumulated error by the ms to ticks conversion error - current->accumulated_error += current->conversion_error; - // If the accumulated error exceeds a tick, subtract that tick from the next - // periodic timer's timeout value. - if (current->accumulated_error >= 1000) { - current->accumulated_error -= 1000; - timeout_temp -= 1; - current->timeout_expected_tc -= 1; - } - } - CORE_ENTER_ATOMIC(); - delta_list_insert_timer(current, (sl_sleeptimer_tick_count_t)timeout_temp); - current->timeout_expected_tc += current->timeout_periodic; - CORE_EXIT_ATOMIC(); - } + process_expired_timer(current); // Save current option flag and the number of timers that expired. option_flags = current->option_flags; nb_timer_expire++; - // Call current timer callback function if any. - if (current->callback != NULL) { - current->callback(current, current->callback_data); - } - CORE_ENTER_ATOMIC(); // Re-update the list to account for delays during timer's callback. @@ -1366,15 +1317,12 @@ void process_timer_irq(uint8_t local_flag) // If the only timer expired is the internal Power Manager one, // from the Sleeptimer perspective, the system can go back to sleep after the ISR handling. sleep_on_isr_exit = false; - if (nb_timer_expire == 1u) { - if (option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { - sleep_on_isr_exit = true; - } + if ((nb_timer_expire == 1u) && (option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG)) { + sleep_on_isr_exit = true; } - if (timer_head) { - set_comparator_for_next_timer(); - } else { + sl_status_t error = set_comparator_for_next_timer(); + if (error == SL_STATUS_NULL_POINTER) { sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); } CORE_EXIT_ATOMIC(); @@ -1467,6 +1415,10 @@ static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle) sl_sleeptimer_timer_handle_t *prev = NULL; sl_sleeptimer_timer_handle_t *current = timer_head; + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + // Retrieve timer in delta list. while (current != NULL && current != handle) { prev = current; @@ -1494,23 +1446,27 @@ static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle) /******************************************************************************* * Sets comparator for next timer. ******************************************************************************/ -static void set_comparator_for_next_timer(void) +static sl_status_t set_comparator_for_next_timer(void) { - if (timer_head->delta > 0) { - sl_sleeptimer_tick_count_t compare_value; + if (timer_head) { + if (timer_head->delta > 0) { + sl_sleeptimer_tick_count_t compare_value; - compare_value = last_delta_update_count + timer_head->delta; + compare_value = last_delta_update_count + timer_head->delta; - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - sleeptimer_hal_set_compare(compare_value); - } else { - // In case timer has already expire, don't attempt to set comparator. Just - // trigger compare match interrupt. - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - sleeptimer_hal_set_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_compare(compare_value); + } else { + // In case timer has already expire, don't attempt to set comparator. Just + // trigger compare match interrupt. + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_int(SLEEPTIMER_EVENT_COMP); + } + update_next_timer_to_expire_is_power_manager(); + return SL_STATUS_OK; } - update_next_timer_to_expire_is_power_manager(); + return SL_STATUS_NULL_POINTER; } /******************************************************************************* @@ -1612,6 +1568,68 @@ static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, return SL_STATUS_OK; } +/***************************************************************************//** + * Processes an expired timer. + * + * @param timer Expired timer to process. + ******************************************************************************/ +static void process_expired_timer(sl_sleeptimer_timer_handle_t *timer) +{ + CORE_DECLARE_IRQ_STATE; + int32_t periodic_correction = 0u; + int64_t timeout_temp = 0; + bool skip_remove = false; + + // Check if periodic timer was delayed more than its actual timeout value + // and keep it at the head of the timers list if it's the case so that the + // callback function can be called the number of required time. + if (timer->timeout_periodic != 0u) { + timeout_temp = timer->timeout_periodic; + + periodic_correction = sleeptimer_hal_get_counter() - timer->timeout_expected_tc; + if (periodic_correction >= timeout_temp) { + skip_remove = true; + timer->timeout_expected_tc += timer->timeout_periodic; + } + } + + // Remove timer from list except if the timer is a periodic timer that was + // intentionally kept at the head of the timers list. + if (skip_remove != true) { + CORE_ENTER_ATOMIC(); + delta_list_remove_timer(timer); + CORE_EXIT_ATOMIC(); + } + + // Re-insert periodic timer that was previsouly removed from the list + // and compensate for any deviation from the periodic timer frequency. + if (timer->timeout_periodic != 0u && skip_remove != true) { + timeout_temp -= periodic_correction; + EFM_ASSERT(timeout_temp > 0); + // Compensate for drift caused by ms to ticks conversion + if (timer->conversion_error > 0) { + // Increment accumulated error by the ms to ticks conversion error + timer->accumulated_error += timer->conversion_error; + // If the accumulated error exceeds a tick, subtract that tick from the next + // periodic timer's timeout value. + if (timer->accumulated_error >= 1000) { + timer->accumulated_error -= 1000; + timeout_temp -= 1; + timer->timeout_expected_tc -= 1; + } + } + CORE_ENTER_ATOMIC(); + delta_list_insert_timer(timer, (sl_sleeptimer_tick_count_t)timeout_temp); + timer->timeout_expected_tc += timer->timeout_periodic; + CORE_EXIT_ATOMIC(); + } + + // Call timer callback function if any. + if (timer->callback != NULL) { + timer->callback(timer, timer->callback_data); + } +} + /******************************************************************************* * Updates internal flag that indicates if next timer to expire is the power * manager's one. @@ -1623,18 +1641,16 @@ static void update_next_timer_to_expire_is_power_manager(void) next_timer_to_expire_is_power_manager = false; - while (delta_diff_with_first <= 1) { + while ((delta_diff_with_first <= 1) && (current != NULL)) { if (current->option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { next_timer_to_expire_is_power_manager = true; break; } current = current->next; - if (current == NULL) { - break; + if (current != NULL) { + delta_diff_with_first += current->delta; } - - delta_diff_with_first += current->delta; } } @@ -1679,7 +1695,7 @@ __STATIC_INLINE uint32_t div_to_log2(uint32_t div) ******************************************************************************/ __STATIC_INLINE bool is_power_of_2(uint32_t nbr) { - if ((((nbr) != 0u) && (((nbr) & ((nbr) - 1u)) == 0u))) { + if ((nbr != 0u) && ((nbr & (nbr - 1u)) == 0u)) { return true; } else { return false; diff --git a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c index 67048b6ab..176999253 100644 --- a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c +++ b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c @@ -57,7 +57,7 @@ #define sleeptimer_hal_burtc_get_counter() sl_hal_burtc_get_counter() #define sleeptimer_hal_burtc_get_compare() sl_hal_burtc_get_compare() #define sleeptimer_hal_burtc_set_compare(compare) sl_hal_burtc_set_compare(compare) -#define sleeptimer_hal_burtc_get_interrupts() sl_hal_burtc_get_interrupts() +#define sleeptimer_hal_burtc_get_interrupts() sl_hal_burtc_get_pending_interrupts() #define sleeptimer_hal_burtc_set_interrupts(flags) sl_hal_burtc_set_interrupts(flags) #define sleeptimer_hal_burtc_enable_interrupts(interrupts) sl_hal_burtc_enable_interrupts(interrupts) #define sleeptimer_hal_burtc_disable_interrupts(interrupts) sl_hal_burtc_disable_interrupts(interrupts) @@ -67,6 +67,7 @@ #include "sl_clock_manager.h" #include "sl_device_peripheral.h" +#include "sl_interrupt_manager.h" #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) #include "sl_power_manager.h" @@ -168,8 +169,8 @@ void sleeptimer_hal_init_timer() #endif // Setup BURTC interrupt - NVIC_ClearPendingIRQ(BURTC_IRQn); - NVIC_EnableIRQ(BURTC_IRQn); + sl_interrupt_manager_clear_irq_pending(BURTC_IRQn); + sl_interrupt_manager_enable_irq(BURTC_IRQn); } /****************************************************************************** diff --git a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c index 8979e8963..893e4d38e 100644 --- a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c +++ b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c @@ -35,6 +35,7 @@ #include "sli_sleeptimer_hal.h" #include "sl_core.h" #include "sl_clock_manager.h" +#include "sl_interrupt_manager.h" #include "em_bus.h" #if defined(SL_COMPONENT_CATALOG_PRESENT) @@ -174,8 +175,8 @@ void sleeptimer_hal_init_timer(void) #endif #endif - NVIC_ClearPendingIRQ(PRORTC_IRQn); - NVIC_EnableIRQ(PRORTC_IRQn); + sl_interrupt_manager_clear_irq_pending(PRORTC_IRQn); + sl_interrupt_manager_enable_irq(PRORTC_IRQn); } /****************************************************************************** diff --git a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c index 5fdf96ff0..4619545f3 100644 --- a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c +++ b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c @@ -36,6 +36,7 @@ #include "sli_sleeptimer_hal.h" #include "sl_core.h" #include "sl_clock_manager.h" +#include "sl_interrupt_manager.h" #include "sl_device_peripheral.h" #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) @@ -84,8 +85,8 @@ void sleeptimer_hal_init_timer(void) RTCC_Enable(true); - NVIC_ClearPendingIRQ(RTCC_IRQn); - NVIC_EnableIRQ(RTCC_IRQn); + sl_interrupt_manager_clear_irq_pending(RTCC_IRQn); + sl_interrupt_manager_enable_irq(RTCC_IRQn); } /****************************************************************************** diff --git a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c index 158347129..655fae8fb 100644 --- a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c +++ b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c @@ -40,6 +40,7 @@ #include "sl_code_classification.h" #include "sl_core.h" #include "sl_clock_manager.h" +#include "sl_interrupt_manager.h" #include "sl_device_peripheral.h" #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) @@ -81,6 +82,9 @@ void sleeptimer_hal_init_timer(void) sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_SYSRTC0); + // Make sure the bus clock enabling is done. + __DSB(); + #if (SL_SLEEPTIMER_DEBUGRUN == 1) sysrtc_config.enable_debug_run = true; #endif @@ -96,8 +100,8 @@ void sleeptimer_hal_init_timer(void) sl_hal_sysrtc_enable(); sl_hal_sysrtc_set_counter(0u); - NVIC_ClearPendingIRQ(SYSRTC_APP_IRQn); - NVIC_EnableIRQ(SYSRTC_APP_IRQn); + sl_interrupt_manager_clear_irq_pending(SYSRTC_APP_IRQn); + sl_interrupt_manager_enable_irq(SYSRTC_APP_IRQn); } /******************************************************************************* diff --git a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c index 38df5195d..132c73c0b 100644 --- a/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c +++ b/simplicity_sdk/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c @@ -41,6 +41,7 @@ #include "sli_sleeptimer_hal.h" #include "sl_core.h" #include "sl_clock_manager.h" +#include "sl_interrupt_manager.h" #include "sl_device_peripheral.h" #if defined(SL_CATALOG_POWER_MANAGER_PRESENT) @@ -93,7 +94,7 @@ #define sleeptimer_hal_timer_get_counter(timer_instance) sl_hal_timer_get_counter(timer_instance) #define sleeptimer_hal_timer_get_compare(timer_instance, channel) sl_hal_timer_channel_get_compare(timer_instance, channel) #define sleeptimer_hal_timer_set_compare(timer_instance, channel, compare) sl_hal_timer_channel_set_compare(timer_instance, channel, compare) -#define sleeptimer_hal_timer_get_interrupt(timer_instance) sl_hal_timer_get_interrupts(timer_instance) +#define sleeptimer_hal_timer_get_interrupt(timer_instance) sl_hal_timer_get_pending_interrupts(timer_instance) #define sleeptimer_hal_timer_set_interrupt(timer_instance, flags) sl_hal_timer_set_interrupts(timer_instance, flags) #define sleeptimer_hal_timer_enable_interrupt(timer_instance, flags) sl_hal_timer_enable_interrupts(timer_instance, flags) #define sleeptimer_hal_timer_disable_interrupt(timer_instance, flags) sl_hal_timer_disable_interrupts(timer_instance, flags) @@ -151,10 +152,11 @@ void sleeptimer_hal_init_timer(void) sl_hal_timer_wait_sync(SLEEPTIMER_TIMER_INSTANCE); sl_hal_timer_set_top(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_TOP_MAX); sl_hal_timer_channel_set_compare(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, 0UL); + sl_hal_timer_start(SLEEPTIMER_TIMER_INSTANCE); #endif - NVIC_ClearPendingIRQ(SLEEPTIMER_TIMER_IRQ); - NVIC_EnableIRQ(SLEEPTIMER_TIMER_IRQ); + sl_interrupt_manager_clear_irq_pending(SLEEPTIMER_TIMER_IRQ); + sl_interrupt_manager_enable_irq(SLEEPTIMER_TIMER_IRQ); } /****************************************************************************** diff --git a/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_hci.h b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_hci.h index 9a4459193..144d67d87 100644 --- a/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_hci.h +++ b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_hci.h @@ -105,6 +105,8 @@ void sl_btctrl_request_hard_reset(void); void sl_btctrl_hci_parser_init_conn(void); +void sl_btctrl_hci_parser_init_subrate(void); + void sl_btctrl_hci_parser_init_adv(void); void sl_btctrl_hci_parser_init_phy(void); diff --git a/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_hci_event.h b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_hci_event.h new file mode 100644 index 000000000..3b37dbc63 --- /dev/null +++ b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_hci_event.h @@ -0,0 +1,113 @@ +/***************************************************************************//** + * @brief Provides API to create HCI event handler hooks to filter out events + * that are passed to host stack + * + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_BTCTRL_HCI_EVENT_H +#define SLI_BTCTRL_HCI_EVENT_H + +#include +#include +#include + +enum sl_btctrl_hci_event_filter_status { + SL_BTCTRL_HCI_EVENT_FILTER_STATUS_EVENT_ACCEPT = 0x00, + SL_BTCTRL_HCI_EVENT_FILTER_STATUS_EVENT_DISCARD = 0x01 +}; + +/** + * @brief Struct declaration for opaque pointer + * It is intentionally undefined to prevent direct manipulation. + */ +struct sl_btctrl_hci_event; + +/** + * @brief HCI event filter callback function + * @important Filtering function should only return false for advertising events or other discardable events + * @important Host stack might end up in deadlock if command complete or other state affecting events are discarded + * @param event Opaque handle to the HCI event + * @return sl_btctrl_hci_event_filter_status SL_BTCTRL_HCI_FILTER_STATUS_EVENT_ACCEPT continue processing event, + * SL_BTCTRL_HCI_FILTER_STATUS_EVENT_DISCARD discard event + */ +typedef enum sl_btctrl_hci_event_filter_status (*sl_btctrl_hci_event_callback)(struct sl_btctrl_hci_event *event); + +/** + * @brief Event handler structure + * Event handler structure must be allocated from the heap + * Controller will fill and use the structure members, do not modify directly + */ +typedef struct sl_btctrl_hci_event_handler { + struct sl_btctrl_hci_event_handler *next; + sl_btctrl_hci_event_callback handler; +} sl_btctrl_hci_event_handler_t; + +/** + * @brief Register HCI Event handler callback function + * + * @param handler_ptr Pointer to sl_btctrl_hci_event_handler_t structure, this is fully initialized by the function + * @param callback function pointer to the filter callback function + * @return sl_status_t SL_STATUS_OK if success + */ +sl_status_t sl_btctrl_hci_register_event_handler(sl_btctrl_hci_event_handler_t *handler_ptr, sl_btctrl_hci_event_callback callback); + +/** + * @brief Clear all registered event handler callbacks + * @return sl_status_t SL_STATUS_OK if success + */ +sl_status_t sl_btctrl_hci_clear_event_handlers(void); + +/** + * @brief Get opcode of HCI event + * @param event Event handler passed to the callback function + * @param event_code pointer to where to place the opcode of event + * @param subevent_code pointer to where to place the subevent of event, only used if event code is 0x3e (LE Meta event) + * @return sl_status_t SL_STATUS_OK if success + */ +sl_status_t sl_btctrl_hci_event_get_opcode(struct sl_btctrl_hci_event *event, uint8_t *event_code, uint8_t *subevent_code); + +/** + * @brief Get length of event payload + * @param event Event handler passed to the callback function + * @param length pointer to size_t where to store the length + * @return sl_status_t SL_STATUS_OK if success + */ +sl_status_t sl_btctrl_hci_event_get_length(struct sl_btctrl_hci_event *event, size_t *length); + +/** + * @brief Get event parameters + * @param event Event handler passed to the callback function + * @param destination pointer to destination buffer + * @param destination_length length of the destination buffer + * @param offset offset of where to read the event payload + * @param length pointer to size_t where to store how many bytes have been copied to the buffer + * @return sl_status_t SL_STATUS_OK if success + */ +sl_status_t sl_btctrl_hci_event_get_parameters(struct sl_btctrl_hci_event *event, uint8_t *destination, size_t destination_length, size_t offset, size_t *length); + +#endif // SLI_BTCTRL_HCI_EVENT_H diff --git a/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_iso.h b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_iso.h new file mode 100644 index 000000000..320119a34 --- /dev/null +++ b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_iso.h @@ -0,0 +1,40 @@ +/***************************************************************************//** + * @brief Bluetooth ISO API. + * + * This interface is for external use. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_BTCTRL_ISO_H_ +#define _SL_BTCTRL_ISO_H_ + +/** + * Initialize CIS component + */ +void sl_btctrl_init_cis(void); + +#endif // _SL_BTCTRL_ISO_H_ diff --git a/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h index b24584200..bbdb07cd1 100644 --- a/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h +++ b/simplicity_sdk/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h @@ -255,6 +255,10 @@ void sl_btctrl_init_adv(void); void sl_btctrl_init_conn(void); +void sl_btctrl_init_subrate(void); + +sl_status_t sl_btctrl_allocate_conn_subrate_memory(uint8_t connectionsCount); + void sl_btctrl_init_phy(void); void sl_btctrl_init_adv_ext(void); diff --git a/wiseconnect/components/common/inc/sl_additional_status.h b/wiseconnect/components/common/inc/sl_additional_status.h new file mode 100644 index 000000000..f9642d51d --- /dev/null +++ b/wiseconnect/components/common/inc/sl_additional_status.h @@ -0,0 +1,753 @@ +/******************************************************************************** + * @file sl_additional_status.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#define SL_STATUS_SI91X_SUBSPACE ((sl_status_t)0x00010000) + +/** + * @addtogroup WISECONNECT_STATUS_CODES + * @{ + */ + +// Additional generic errors +#define SL_STATUS_OS_OPERATION_FAILURE ((sl_status_t)0x0051) ///< OS operation failed. +#define SL_STATUS_BOOTUP_OPTIONS_NOT_SAVED ((sl_status_t)0x0052) ///< Bootup options were not saved. +#define SL_STATUS_BOOTUP_OPTIONS_CHECKSUM_FAILURE ((sl_status_t)0x0053) ///< Bootup options checksum validation failed. +#define SL_STATUS_BOOTLOADER_VERSION_MISMATCH \ + ((sl_status_t)0x0054) ///< Bootloader version does not match expected version. +#define SL_STATUS_WAITING_FOR_BOARD_READY ((sl_status_t)0x0055) ///< Waiting for the board to be ready. +#define SL_STATUS_VALID_FIRMWARE_NOT_PRESENT ((sl_status_t)0x0056) ///< No valid firmware present. +#define SL_STATUS_INVALID_OPTION ((sl_status_t)0x0057) ///< Provided option is invalid. +#define SL_STATUS_SPI_BUSY ((sl_status_t)0x0058) ///< SPI is currently busy. +#define SL_STATUS_CARD_READY_TIMEOUT ((sl_status_t)0x0059) ///< Timeout waiting for card to be ready. +#define SL_STATUS_FW_LOAD_OR_UPGRADE_TIMEOUT ((sl_status_t)0x005A) ///< Firmware load or upgrade operation timed out. + +// Additional Wi-Fi errors +#define SL_STATUS_WIFI_DOES_NOT_EXIST ((sl_status_t)0x0B21) ///< WiFi network does not exist. +#define SL_STATUS_WIFI_NOT_AUTHENTICATED ((sl_status_t)0x0B22) ///< WiFi network not authenticated. +#define SL_STATUS_WIFI_NOT_KEYED \ + ((sl_status_t)0x0B23) ///< Device attempts to connect to a secured WiFi network without providing the correct security key or credentials. +#define SL_STATUS_WIFI_IOCTL_FAIL ((sl_status_t)0x0B24) ///< Input/Output Control operation failed. +#define SL_STATUS_WIFI_BUFFER_UNAVAILABLE_TEMPORARY ((sl_status_t)0x0B25) ///< WiFi buffer temporarily unavailable. +#define SL_STATUS_WIFI_BUFFER_UNAVAILABLE_PERMANENT ((sl_status_t)0x0B26) ///< WiFi buffer permanently unavailable. +#define SL_STATUS_WIFI_WPS_PBC_OVERLAP ((sl_status_t)0x0B27) ///< WPS PBC overlap detected. +#define SL_STATUS_WIFI_CONNECTION_LOST ((sl_status_t)0x0B28) ///< WiFi connection lost. +#define SL_STATUS_WIFI_OUT_OF_EVENT_HANDLER_SPACE ((sl_status_t)0x0B29) ///< No space for additional event handlers. +#define SL_STATUS_WIFI_SEMAPHORE_ERROR ((sl_status_t)0x0B2A) ///< Semaphore manipulation error. +#define SL_STATUS_WIFI_FLOW_CONTROLLED ((sl_status_t)0x0B2B) ///< Packet retrieval cancelled due to flow control. +#define SL_STATUS_WIFI_NO_CREDITS ((sl_status_t)0x0B2C) ///< Packet retrieval cancelled due to lack of bus credits. +#define SL_STATUS_WIFI_NO_PACKET_TO_SEND \ + ((sl_status_t)0x0B2D) ///< Packet retrieval cancelled due to no pending packets. +#define SL_STATUS_WIFI_CORE_CLOCK_NOT_ENABLED ((sl_status_t)0x0B2E) ///< WiFi core disabled due to no clock. +#define SL_STATUS_WIFI_CORE_IN_RESET ((sl_status_t)0x0B2F) ///< WiFi core disabled because it is in reset state. +#define SL_STATUS_WIFI_UNSUPPORTED ((sl_status_t)0x0B30) ///< Unsupported WiFi function. +#define SL_STATUS_WIFI_BUS_WRITE_REGISTER_ERROR \ + ((sl_status_t)0x0B31) ///< Error occurred while writing to the WLAN register. +#define SL_STATUS_WIFI_SDIO_BUS_UP_FAIL ((sl_status_t)0x0B32) ///< SDIO bus failed to initialize. +#define SL_STATUS_WIFI_JOIN_IN_PROGRESS ((sl_status_t)0x0B33) ///< WiFi join operation is still in progress. +#define SL_STATUS_WIFI_NETWORK_NOT_FOUND ((sl_status_t)0x0B34) ///< Specified WiFi network was not found. +#define SL_STATUS_WIFI_INVALID_JOIN_STATUS ((sl_status_t)0x0B35) ///< Invalid status encountered during WiFi join. +#define SL_STATUS_WIFI_UNKNOWN_INTERFACE ((sl_status_t)0x0B36) ///< Unknown WiFi interface specified. +#define SL_STATUS_WIFI_SDIO_RX_FAIL ((sl_status_t)0x0B37) ///< Error occurred during SDIO receive operation. +#define SL_STATUS_WIFI_HWTAG_MISMATCH ((sl_status_t)0x0B38) ///< Hardware tag header is corrupt. +#define SL_STATUS_WIFI_RX_BUFFER_ALLOC_FAIL \ + ((sl_status_t)0x0B39) ///< Failed to allocate a buffer for WiFi receive operation. +#define SL_STATUS_WIFI_BUS_READ_REGISTER_ERROR \ + ((sl_status_t)0x0B3A) ///< Error occurred while reading a bus hardware register. +#define SL_STATUS_WIFI_THREAD_CREATE_FAILED ((sl_status_t)0x0B3B) ///< Failed to create a new WiFi thread. +#define SL_STATUS_WIFI_QUEUE_ERROR ((sl_status_t)0x0B3C) ///< Error occurred while manipulating a WiFi queue. +#define SL_STATUS_WIFI_BUFFER_POINTER_MOVE_ERROR \ + ((sl_status_t)0x0B3D) ///< Error occurred while moving the current pointer of a buffer. + +#define SL_STATUS_WIFI_BUFFER_SIZE_SET_ERROR \ + ((sl_status_t)0x0B3E) ///< Error occurred while setting the size of the packet buffer. + +#define SL_STATUS_WIFI_THREAD_STACK_NULL \ + ((sl_status_t)0x0B3F) ///< Null stack pointer passed when a non-null pointer was required. +#define SL_STATUS_WIFI_THREAD_DELETE_FAIL ((sl_status_t)0x0B40) ///< Error occurred while deleting a WiFi thread. +#define SL_STATUS_WIFI_SLEEP_ERROR ((sl_status_t)0x0B41) ///< Failed to put a WiFi thread to sleep. +#define SL_STATUS_WIFI_BUFFER_ALLOC_FAIL ((sl_status_t)0x0B42) ///< Failed to allocate a WiFi packet buffer. +#define SL_STATUS_WIFI_INTERFACE_NOT_UP ((sl_status_t)0x0B44) ///< The requested WiFi interface is not active. +#define SL_STATUS_WIFI_DELAY_TOO_LONG ((sl_status_t)0x0B45) ///< The requested delay for WiFi operation is too long. +#define SL_STATUS_WIFI_INVALID_DUTY_CYCLE \ + ((sl_status_t)0x0B46) ///< The specified WiFi duty cycle is outside the valid range. +#define SL_STATUS_WIFI_PMK_WRONG_LENGTH \ + ((sl_status_t)0x0B47) ///< The returned Pairwise Master Key (PMK) length is incorrect. +#define SL_STATUS_WIFI_UNKNOWN_SECURITY_TYPE \ + ((sl_status_t)0x0B48) ///< The security type of the WiFi Access Point is unknown. +#define SL_STATUS_WIFI_WEP_NOT_ALLOWED \ + ((sl_status_t)0x0B49) ///< WEP security is not allowed; use Open security instead. +#define SL_STATUS_WIFI_WPA_KEYLEN_BAD ((sl_status_t)0x0B4A) ///< WPA/WPA2 key length must be between 8 and 64 bytes. +#define SL_STATUS_WIFI_FILTER_NOT_FOUND ((sl_status_t)0x0B4B) ///< The specified WiFi filter ID was not found. +#define SL_STATUS_WIFI_SPI_ID_READ_FAIL ((sl_status_t)0x0B4C) ///< Failed to read the SPI ID (0xfeedbead) from the chip. +#define SL_STATUS_WIFI_SPI_SIZE_MISMATCH ((sl_status_t)0x0B4D) ///< Size mismatch between SPI and SDPCM header. +#define SL_STATUS_WIFI_ADDRESS_ALREADY_REGISTERED \ + ((sl_status_t)0x0B4E) ///< Attempted to register a multicast address that is already registered. +#define SL_STATUS_WIFI_SDIO_RETRIES_EXCEEDED \ + ((sl_status_t)0x0B4F) ///< SDIO transfer failed after exceeding the maximum number of retries. +#define SL_STATUS_WIFI_NULL_PTR_ARG ((sl_status_t)0x0B50) ///< Null pointer argument passed to a function. +#define SL_STATUS_WIFI_THREAD_FINISH_FAIL ((sl_status_t)0x0B51) ///< Error occurred while attempting to delete a thread. +#define SL_STATUS_WIFI_WAIT_ABORTED ((sl_status_t)0x0B52) ///< Semaphore or mutex wait operation was aborted. +#define SL_STATUS_WIFI_QUEUE_MESSAGE_UNALIGNED ((sl_status_t)0x0B53) ///< Unaligned message found in the queue. +#define SL_STATUS_WIFI_MUTEX_ERROR ((sl_status_t)0x0B54) ///< Error occurred during a mutex operation. +#define SL_STATUS_WIFI_SECURE_LINK_DECRYPT_ERROR \ + ((sl_status_t)0x0B57) ///< Error occurred during decryption over a secure link. +#define SL_STATUS_WIFI_SECURE_LINK_KEY_RENEGOTIATION_ERROR \ + ((sl_status_t)0x0B59) ///< Error occurred during key renegotiation over a secure link. +#define SL_STATUS_WIFI_INVALID_OPERMODE ((sl_status_t)0x0B60) ///< Invalid operation mode provided. +#define SL_STATUS_WIFI_INVALID_ENCRYPTION_METHOD ((sl_status_t)0x0B61) ///< Invalid encryption method provided. + +// Si91X Crypto errors +#define SL_STATUS_TRNG_DUPLICATE_ENTROPY ((sl_status_t)0x0B62) ///< Error due to duplicate entropy elements in TRNG. + +// Si91X Wi-Fi transceiver error codes +#define SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS ((sl_status_t)0x0B63) ///< Provided MAC address is invalid. +#define SL_STATUS_TRANSCEIVER_INVALID_QOS_PRIORITY ((sl_status_t)0x0B64) ///< Provided QoS priority is invalid. +#define SL_STATUS_TRANSCEIVER_INVALID_CHANNEL ((sl_status_t)0x0B65) ///< Provided channel is invalid. +#define SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE ((sl_status_t)0x0B66) ///< Provided data rate is invalid. +#define SL_STATUS_TRANSCEIVER_INVALID_CONFIG \ + ((sl_status_t)0x0B67) ///< Provided transceiver configuration parameters are invalid. + +// Si91X Crypto Firmware Errors +#define SL_STATUS_CRYPTO_INVALID_PARAMETER \ + ((sl_status_t)0x1CCFE) ///< Return when parameter passed to Crypto SAPI is invalid. +#define SL_STATUS_CRYPTO_INVALID_SIGNATURE \ + ((sl_status_t)0x1CC9A) ///< Return in AEAD (CCM, GCM, Chachapoly) decryption function, when MAC generated during decryption does not match the MAC passed. + +// Si91X Wi-Fi Firmware errors +#define SL_STATUS_SI91X_SCAN_ISSUED_IN_ASSOCIATED_STATE \ + ((sl_status_t)0x10002) ///< Scan command issued while device is already associated with an access point. +#define SL_STATUS_SI91X_NO_AP_FOUND ((sl_status_t)0x10003) ///< No access point found. +#define SL_STATUS_SI91X_INVALID_PSK_IN_WEP_SECURITY \ + ((sl_status_t)0x10004) ///< Incorrect PSK provided while trying to join an access point with WEP security enabled. +#define SL_STATUS_SI91X_INVALID_BAND ((sl_status_t)0x10005) ///< Invalid band specified. +#define SL_STATUS_SI91X_UNASSOCIATED \ + ((sl_status_t)0x10006) ///< Device is not associated or is in an unassociated state. +#define SL_STATUS_SI91X_DEAUTHENTICATION_RECEIVED_FROM_AP \ + ((sl_status_t)0x10008) ///< De-authentication received from access point. +#define SL_STATUS_SI91X_ASSOCIATION_FAILED \ + ((sl_status_t)0x10009) ///< Failed to associate with the access point during "Join". +#define SL_STATUS_SI91X_INVALID_CHANNEL ((sl_status_t)0x1000A) ///< Invalid channel specified. +#define SL_STATUS_SI91X_JOIN_AUTHENTICATION_FAILED \ + ((sl_status_t)0x1000E) ///< Authentication failure during "Join". Unable to find access point during join which was found during scan. +#define SL_STATUS_SI91X_BEACON_MISSED_FROM_AP_DURING_JOIN \ + ((sl_status_t)0x1000F) ///< Missed beacon from access point during join. +#define SL_STATUS_SI91X_INVALID_MAC_SUPPLIED \ + ((sl_status_t)0x10013) ///< Non-existent MAC address supplied in "Disassociate" command. +#define SL_STATUS_SI91X_EAP_CONFIG_NOT_DONE ((sl_status_t)0x10014) ///< EAP configuration is not completed. +#define SL_STATUS_SI91X_MEMORY_FAILED_FROM_MODULE \ + ((sl_status_t)0x10015) ///< Memory allocation failed or store configuration checksum failed. +#define SL_STATUS_SI91X_INSUFFICIENT_INFO \ + ((sl_status_t)0x10016) ///< Insufficient or incorrect information provided in join command. +#define SL_STATUS_SI91X_NOT_AP_INTERFACE ((sl_status_t)0x10017) ///< Not an access point interface. +#define SL_STATUS_SI91X_INVALID_PUSH_BUTTON_SEQUENCE \ + ((sl_status_t)0x10018) ///< Push button command issued before the expiry of the previous push button command. +#define SL_STATUS_SI91X_REJOIN_FAILURE ((sl_status_t)0x10019) ///< Rejoin failure: Access point not found. +#define SL_STATUS_SI91X_FREQUENCY_NOT_SUPPORTED ((sl_status_t)0x1001A) ///< Operation failed: Frequency not supported. +#define SL_STATUS_SI91X_INVALID_OPERMODE ((sl_status_t)0x1001B) ///< Operation failed: Invalid operation mode. +#define SL_STATUS_SI91X_EAP_CONFIG_FAILED ((sl_status_t)0x1001C) ///< EAP configuration failed. +#define SL_STATUS_SI91X_P2P_CONFIG_FAILED ((sl_status_t)0x1001D) ///< P2P configuration failed. +#define SL_STATUS_SI91X_GROUP_OWNER_NEGOTIATION_FAILED \ + ((sl_status_t)0x1001E) ///< Failed to start Group Owner negotiation. +#define SL_STATUS_SI91X_JOIN_TIMEOUT ((sl_status_t)0x10020) ///< Join operation timed out. +#define SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE ((sl_status_t)0x10021) ///< Command issued in an invalid state. +#define SL_STATUS_SI91X_INVALID_QUERY_GO_PARAMS \ + ((sl_status_t)0x10022) ///< Invalid parameters for Query GO in the current operating mode. +#define SL_STATUS_SI91X_ACCESS_POINT_FAILED ((sl_status_t)0x10023) ///< Failed to form access point. +#define SL_STATUS_SI91X_INVALID_SCAN_INFO ((sl_status_t)0x10024) ///< Invalid scan input parameters. +#define SL_STATUS_SI91X_COMMAND_ISSUED_IN_REJOIN_STATE \ + ((sl_status_t)0x10025) ///< Command issued during re-join operation. +#define SL_STATUS_SI91X_WRONG_PARAMETERS ((sl_status_t)0x10026) ///< Incorrect parameters provided for the command. +#define SL_STATUS_SI91X_PROVISION_DISCOVERY_FAILED_IN_P2P \ + ((sl_status_t)0x10027) ///< Provision discovery failed in P2P mode. +#define SL_STATUS_SI91X_INVALID_PSK_LENGTH \ + ((sl_status_t)0x10028) ///< PSK length less than 8 bytes or more than 63 bytes. +#define SL_STATUS_SI91X_FAILED_TO_CLEAR_OR_SET_EAP_CERTIFICATE \ + ((sl_status_t)0x10029) ///< Failed to clear or to set the Enterprise Certificate (Set Certificate). +#define SL_STATUS_SI91X_P2P_GO_NEGOTIATED_FAILED ((sl_status_t)0x1002A) ///< P2P Group Owner negotiation failed. +#define SL_STATUS_SI91X_ASSOCIATION_TIMEOUT_IN_P2P_WPS_MODE \ + ((sl_status_t)0x1002B) ///< Association between nodes failed in P2P WPS mode due to timeout. +#define SL_STATUS_SI91X_COMMAND_ISSUED_WHILE_INTERNAL_OPERATION \ + ((sl_status_t)0x1002C) ///< Command issued by the Host while the device is executing an internal operation (e.g., auto-join or auto-create). +#define SL_STATUS_SI91X_INVALID_WEP_KEY_LEN ((sl_status_t)0x1002D) ///< Invalid WEP key length. +#define SL_STATUS_SI91X_ICMP_REQUEST_TIMEOUT_ERROR ((sl_status_t)0x1002E) ///< ICMP request timed out. +#define SL_STATUS_SI91X_ICMP_DATA_SIZE_EXCEED_MAX_LIMIT \ + ((sl_status_t)0x1002F) ///< ICMP data size exceeds the maximum limit. +#define SL_STATUS_SI91X_SEND_DATA_PACKET_EXCEED_LIMIT \ + ((sl_status_t)0x10030) ///< Data packet size exceeded the limit, MQTT published the data and length mismatched, or MQTT send data packet exceeded the limit. +#define SL_STATUS_SI91X_ARP_CACHE_NOT_FOUND ((sl_status_t)0x10031) ///< ARP cache entry not found. +#define SL_STATUS_SI91X_UART_COMMAND_TIMEOUT ((sl_status_t)0x10032) ///< UART command timed out. +#define SL_STATUS_SI91X_FIXED_DATA_RATE_NOT_SUPPORTED_BY_AP \ + ((sl_status_t)0x10033) ///< Fixed data rate not supported by the connected AP. +#define SL_STATUS_SI91X_USERNAME_PASSWORD_CLIENTID_TOPIC_MAX_LEN \ + ((sl_status_t)0x10036) ///< Maximum length exceeded for username, password, client ID, or topic in MQTT. +#define SL_STATUS_SI91X_INVALID_WPS_PIN ((sl_status_t)0x10037) ///< Invalid WPS PIN. +#define SL_STATUS_SI91X_INVALID_WPS_PIN_LEN ((sl_status_t)0x10038) ///< Invalid WPS PIN length. +#define SL_STATUS_SI91X_INVALID_PMK_LEN ((sl_status_t)0x10039) ///< Invalid PMK length. +#define SL_STATUS_SI91X_SSID_NOT_PRESENT_FOR_PMK_GENERATION \ + ((sl_status_t)0x1003A) ///< SSID not present for PMK generation. +#define SL_STATUS_SI91X_SSID_INCORRECT_PMK_GENERATION \ + ((sl_status_t)0x1003B) ///< SSID incorrect for PMK generation(more than 32 bytes). +#define SL_STATUS_SI91X_BAND_NOT_SUPPORTED ((sl_status_t)0x1003C) ///< Band not supported. +#define SL_STATUS_SI91X_INVALID_USR_STORE_CONFIGURATION_LEN \ + ((sl_status_t)0x1003D) ///< Invalid user store configuration length. +#define SL_STATUS_SI91X_INVALID_COMMAND_LEN \ + ((sl_status_t)0x1003E) ///< Invalid command length (exceeds the number of characters specified in the PRM). +#define SL_STATUS_SI91X_DATA_PACKET_DROPPED ((sl_status_t)0x1003F) ///< Data packet dropped. +#define SL_STATUS_SI91X_WEP_KEY_NOT_GIVEN ((sl_status_t)0x10040) ///< WEP key not provided. +#define SL_STATUS_SI91X_INVALID_STORE_CONFIG_PROFILE ((sl_status_t)0x10041) ///< Store config profile length error. +#define SL_STATUS_SI91X_MISSING_PSK_OR_PMK ((sl_status_t)0x10042) ///< PSK or PMK not provided. +#define SL_STATUS_SI91X_INVALID_SECURITY_MODE_IN_JOIN_COMMAND \ + ((sl_status_t)0x10043) ///< Invalid security mode in join command. +#define SL_STATUS_SI91X_MAX_BEACON_MISCOUNT \ + ((sl_status_t)0x10044) ///< Maximum beacon miscount reached: De-authentication due to beacon miss. +#define SL_STATUS_SI91X_DEAUTH_REQUEST_FROM_SUPPLICANT \ + ((sl_status_t)0x10045) ///< De-authentication request received from supplicant. +#define SL_STATUS_SI91X_DEAUTH_REQUEST_FROM_FROM_AP \ + ((sl_status_t)0x10046) ///< De-authentication request received from AP after channel switching. +#define SL_STATUS_SI91X_MISSED_SYNCHRONIZATION ((sl_status_t)0x10047) ///< Synchronization missed. +#define SL_STATUS_SI91X_AUTHENTICATION_TIMEOUT ((sl_status_t)0x10048) ///< Authentication timeout occurred. +#define SL_STATUS_SI91X_ASSOCIATION_TIMEOUT ((sl_status_t)0x10049) ///< Association timeout. +#define SL_STATUS_SI91X_BG_SCAN_NOT_ALLOWED ((sl_status_t)0x1004A) ///< BG scan in given channels is not allowed. +#define SL_STATUS_SI91X_SSID_MISMATCH ((sl_status_t)0x1004B) ///< Scanned SSID and SSID given in join are not matching. +#define SL_STATUS_SI91X_CLIENT_MAX_SUPPORTED_EXCEEDED \ + ((sl_status_t)0x1004C) ///< The number of clients exceeds the maximum number of supported stations. +#define SL_STATUS_SI91X_HT_CAPABILITIES_NOT_SUPPORTED \ + ((sl_status_t)0x1004D) ///< The specified HT capabilities are not supported. +#define SL_STATUS_SI91X_UART_FLOW_NOT_SUPPORTED ((sl_status_t)0x1004E) ///< UART flow control is not supported. +#define SL_STATUS_SI91X_ZB_BT_BLE_PKT_RECEIVED \ + ((sl_status_t)0x1004F) ///< ZB/BT/BLE packet received, but the protocol is not enabled. +#define SL_STATUS_SI91X_MGMT_PKT_DROPPED ((sl_status_t)0x10050) ///< Management packet dropped. +#define SL_STATUS_SI91X_INVALID_RF_CURRENT_MODE ((sl_status_t)0x10051) ///< The current RF mode is invalid. +#define SL_STATUS_SI91X_POWER_SAVE_NOT_SUPPORTED \ + ((sl_status_t)0x10052) ///< Power save is not supported for the specified interface. +#define SL_STATUS_SI91X_CONCURRENT_AP_IN_CONNECTED_STATE \ + ((sl_status_t)0x10053) ///< Concurrent AP is in a connected state. +#define SL_STATUS_SI91X_CONNECTED_AP_OR_STATION_CHANNEL_MISMATCH \ + ((sl_status_t)0x10054) ///< Channel mismatch between connected AP and station. +#define SL_STATUS_SI91X_IAP_COPROCESSOR_ERROR ((sl_status_t)0x10055) ///< IAP coprocessor error occurred. +#define SL_STATUS_SI91X_WPS_NOT_SUPPORTED \ + ((sl_status_t)0x10056) ///< WPS is not supported in the current operating mode. +#define SL_STATUS_SI91X_CONCURRENT_AP_CHANNEL_MISMATCH \ + ((sl_status_t)0x10057) ///< Concurrent AP channel does not match the connected station channel. +#define SL_STATUS_SI91X_PBC_SESSION_OVERLAP ((sl_status_t)0x10058) ///< PBC session overlap error. +#define SL_STATUS_SI91X_BT_FEATURE_BITMAP_INVALID ((sl_status_t)0x10059) ///< The Bluetooth feature bitmap is invalid. +#define SL_STATUS_SI91X_FOUR_WAY_HANDSHAKE_FAILED \ + ((sl_status_t)0x1005A) ///< The 4/4 confirmation of the four-way handshake failed. +#define SL_STATUS_SI91X_MAC_ADDRESS_NOT_PRESENT_IN_MAC_JOIN \ + ((sl_status_t)0x1005B) ///< MAC address is not present in the MAC-based join. +#define SL_STATUS_SI91X_CONCURRENT_MODE_DOWN \ + ((sl_status_t)0x1005C) ///< Concurrent mode requires both AP and client to be up for configuration. +#define SL_STATUS_SI91X_CERTIFICATE_LOAD_NOT_ALLOWED_IN_FLASH \ + ((sl_status_t)0x1005D) ///< Certificate load operation is not allowed in flash memory. +#define SL_STATUS_SI91X_CERTIFICATE_LOAD_NOT_ALLOWED_IN_RAM \ + ((sl_status_t)0x1005E) ///< Certificate load operation is not allowed in RAM. +#define SL_STATUS_SI91X_WRONG_CERTIFICATE_LOAD_INDEX \ + ((sl_status_t)0x1005F) ///< Certificate load failed due to an incorrect index. +#define SL_STATUS_SI91X_AP_HT_CAPS_NOT_ENABLED ((sl_status_t)0x10060) ///< Access Point HT capabilities are not enabled. +#define SL_STATUS_SI91X_ADDRESS_FAMILY_NOT_SUPPORTED \ + ((sl_status_t)0x10061) ///< The specified address family is not supported by the protocol. +#define SL_STATUS_SI91X_INVALID_BEACON_INTERVAL_OR_DTM_PERIOD \ + ((sl_status_t)0x10062) ///< The provided beacon interval or DTIM period is invalid. +#define SL_STATUS_SI91X_INVALID_CONFIG_RANGE_PROVIDED \ + ((sl_status_t)0x10063) ///< The provided configuration range is invalid. +#define SL_STATUS_SI91X_INVALID_CONFIG_TYPE \ + ((sl_status_t)0x10064) ///< The provided configuration type (e.g., RTS threshold) is invalid. +#define SL_STATUS_SI91X_ERROR_WITH_MQTT_COMMAND ((sl_status_t)0x10065) ///< An error occurred with the MQTT command. +#define SL_STATUS_SI91X_HIGHER_LISTEN_INTERVAL \ + ((sl_status_t)0x10066) ///< The listen interval in power save mode is greater than that specified in the join command. +#define SL_STATUS_SI91X_WLAN_RADIO_DEREGISTERED ((sl_status_t)0x10067) ///< The WLAN radio has been deregistered. +#define SL_STATUS_SI91X_SAE_FAILURE_DUE_TO_MULTIPLE_CONFIRM_FRAMES_FROM_AP \ + ((sl_status_t)0x10069) ///< SAE authentication failed due to multiple confirm frames received from the Access Point. +#define SL_STATUS_SI91X_EC_GROUP_STATION_UNSUPPORTED_BY_AP \ + ((sl_status_t)0x1006A) ///< The Access Point does not support the EC-group set by the station. +#define SL_STATUS_SI91X_NO_11AX_SUPPORT_IN_AP \ + ((sl_status_t)0x1006C) ///< 802.11ax (Wi-Fi 6) is not supported in Access Point mode. +#define SL_STATUS_SI91X_NON_PREF_CHAN_CONFIG_FAILED \ + ((sl_status_t)0x1006D) ///< Non-preferred channel configuration failed. +#define SL_STATUS_TWT_SUPPORT_NOT_ENABLED_ERR \ + ((sl_status_t)0x10070) ///< Error occurs when HE_PARAMS_SUPPORT and SLI_SI91X_ENABLE_TWT_FEATURE macros are not enabled. +#define SL_STATUS_TWT_SETUP_ERR_SESSION_ACTIVE \ + ((sl_status_t)0x10071) ///< Error occurs when a TWT config command is issued while there is already an active TWT session. +#define SL_STATUS_TWT_TEARDOWN_ERR_FLOWID_NOT_MATCHED \ + ((sl_status_t)0x10072) ///< Error occurs when a TWT teardown command is issued with a flow ID that does not match the existing session flow ID. +#define SL_STATUS_TWT_TEARDOWN_ERR_NOACTIVE_SESS \ + ((sl_status_t)0x10073) ///< Error occurs when a teardown command is issued while there is no active TWT session. +#define SL_STATUS_TWT_SESSION_NOT_FEASIBLE \ + ((sl_status_t)0x10074) ///< Indicates that a TWT session is not feasible. This error is thrown only when the TWT Auto Selection API is used. +#define SL_STATUS_SI91X_RESCHEDULE_TWT_NOT_SUPPORTED \ + ((sl_status_t)0x10075) ///< Error occurs when the AP does not support TWT information frame reception. +#define SL_STATUS_SI91X_RESCHEDULE_TWT_ERR_NOACTIVE_SESS \ + ((sl_status_t)0x10076) ///< Error occurs when there is no active TWT agreement corresponding to the given flow ID. +#define SL_STATUS_SI91X_TWT_RESCHEDULING_IN_PROGRESS \ + ((sl_status_t)0x10077) ///< Indicates that a suspend or resume TWT action is currently in progress. +#define SL_STATUS_SI91X_RESCHEDULE_TWT_PACKET_CREATION_FAILED \ + ((sl_status_t)0x10078) ///< Error occurs when TWT information frame packet creation fails in firmware. +#define SL_STATUS_SI91X_INVALID_STATION_TSF \ + ((sl_status_t)0x10079) ///< Error occurs when the station TSF is invalid, typically when the station is not connected or has not received at least one beacon. +#define SL_STATUS_SI91X_MQTT_ERROR_UNACCEPTABLE_PROTOCOL \ + ((sl_status_t)0x10081) ///< Error occurs when the server does not support the level of the MQTT protocol requested by the client. +#define SL_STATUS_SI91X_MQTT_ERROR_IDENTIFIER_REJECTED \ + ((sl_status_t)0x10082) ///< Error occurs when the client identifier is correct UTF-8 but is not allowed by the server. +#define SL_STATUS_SI91X_MQTT_ERROR_SERVER_UNAVAILABLE \ + ((sl_status_t)0x10083) ///< Error occurs when the network connection has been made but the MQTT service is unavailable. +#define SL_STATUS_SI91X_MQTT_ERROR_BAD_USERNAME_PASSWORD \ + ((sl_status_t)0x10084) ///< The data in the username or password is malformed. +#define SL_STATUS_SI91X_MQTT_ERROR_NOT_AUTHORIZED ((sl_status_t)0x10085) ///< The client is not authorized to connect. +#define SL_STATUS_SI91X_SA_QUERY_TIMEOUT ((sl_status_t)0x10086) ///< Disconnection due to SA Query Timeout. +#define SL_STATUS_SI91X_TRANSCEIVER_PEER_DS_FEAT_DISABLED \ + ((sl_status_t)0x10096) ///< Feature to add peers in MAC layer is disabled. +#define SL_STATUS_SI91X_TRANSCEIVER_PEER_ALREADY_EXISTS ((sl_status_t)0x10097) ///< Peer already exists in MAC layer. +#define SL_STATUS_SI91X_TRANSCEIVER_MAX_PEER_LIMIT_REACHED \ + ((sl_status_t)0x10098) ///< Max peer limit reached in MAC layer. +#define SL_STATUS_SI91X_TRANSCEIVER_PEER_NOT_FOUND ((sl_status_t)0x10099) ///< Peer not found in MAC layer. +#define SL_STATUS_SI91X_DUPLICATE_ENTRY_EXISTS_IN_DNS_SERVER_TABLE \ + ((sl_status_t)0x100AF) ///< Duplicate entry exists in DNS server table. +#define SL_STATUS_SI91X_NO_MEM_AVAILABLE ((sl_status_t)0x100B1) ///< Memory error: No memory available. +#define SL_STATUS_SI91X_INVALID_CHARACTERS_IN_JSON_OBJECT ((sl_status_t)0x100B2) ///< Invalid characters in JSON object. +#define SL_STATUS_SI91X_NO_KEY_FOUND ((sl_status_t)0x100B3) ///< Update commands: No such key found. +#define SL_STATUS_SI91X_NO_FILE_FOUND ((sl_status_t)0x100B4) ///< No such file found: Re-check filename. +#define SL_STATUS_SI91X_NO_WEB_PAGE_EXISTS_WITH_SAME_FILENAME \ + ((sl_status_t)0x100B5) ///< No corresponding web page exists with the same filename. +#define SL_STATUS_SI91X_SPACE_UNAVAILABLE_FOR_NEW_FILE ((sl_status_t)0x100B6) ///< Space unavailable for new file. +#define SL_STATUS_SI91X_INVALID_INPUT_DATA \ + ((sl_status_t)0x100C1) ///< Invalid input data, re-check filename, lengths, etc. +#define SL_STATUS_SI91X_NO_SPACE_AVAILABLE_FOR_NEW_FILE ((sl_status_t)0x100C2) ///< Space unavailable for new file. +#define SL_STATUS_SI91X_EXISTING_FILE_OVERWRITE \ + ((sl_status_t)0x100C3) ///< Existing file overwrite: Exceeds size of previous file. Use erase and try again. +#define SL_STATUS_SI91X_NO_SUCH_FILE_FOUND ((sl_status_t)0x100C4) ///< No such file found. Re-check filename. +#define SL_STATUS_SI91X_MEMORY_ERROR ((sl_status_t)0x100C5) ///< Memory Error: No memory available. +#define SL_STATUS_SI91X_RECEIVED_MORE_WEB_PAGE_DATA \ + ((sl_status_t)0x100C6) ///< Received more web page data than the total length initially specified. +#define SL_STATUS_SI91X_SET_REGION_ERROR ((sl_status_t)0x100C7) ///< Error in set region command. +#define SL_STATUS_SI91X_INVALID_WEBPAGE_CURRENT_CHUNK_LEN \ + ((sl_status_t)0x100C8) ///< Web page current chunk length is incorrect. +#define SL_STATUS_SI91X_AP_SET_REGION_COMMAND_ERROR ((sl_status_t)0x100CA) ///< Error in AP set region command. +#define SL_STATUS_SI91X_AP_SET_REGION_COMMAND_PARAMETERS_ERROR \ + ((sl_status_t)0x100CB) ///< Error in AP set region command parameters. +#define SL_STATUS_SI91X_REGION_CODE_NOT_SUPPORTED ((sl_status_t)0x100CC) ///< Region code not supported. +#define SL_STATUS_SI91X_EXTRACTING_COUNTRY_REGION_FROM_BEACON_FAILED \ + ((sl_status_t)0x100CD) ///< Error in extracting country region from beacon. +#define SL_STATUS_SI91X_SELECTED_REGION_NOT_SUPPORTED \ + ((sl_status_t)0x100CE) ///< Device does not have selected region support. +#define SL_STATUS_SI91X_SSL_TLS_CONTEXT_CREATION_FAILED ((sl_status_t)0x100D1) ///< SSL/TLS context create failed. +#define SL_STATUS_SI91X_SSL_TLS_HANDSHAKE_FAIL \ + ((sl_status_t)0x100D2) ///< SSL/TLS handshake failed. Socket will be closed. +#define SL_STATUS_SI91X_SSL_TLS_MAX_SOCKETS_REACHED ((sl_status_t)0x100D3) ///< SSL/TLS max sockets reached. +#define SL_STATUS_SI91X_FTP_CLIENT_NOT_CONNECTED ((sl_status_t)0x100D3) ///< FTP client is not connected. +#define SL_STATUS_SI91X_CIPHER_SET_FAILED ((sl_status_t)0x100D4) ///< Cipher set failure. +#define SL_STATUS_SI91X_HTTP_CREDENTIALS_MAX_LEN_EXCEEDED \ + ((sl_status_t)0x100F1) ///< HTTP credentials maximum length exceeded. +#define SL_STATUS_SI91X_FEATURE_NOT_SUPPORTED ((sl_status_t)0x100F7) ///< Feature not supported. +#define SL_STATUS_SI91X_FLASH_WRITE_OR_FLASH_DATA_VERIFICATION_FAILED \ + ((sl_status_t)0x100F8) ///< Unable to write to flash OR flash data verification failed. +#define SL_STATUS_SI91X_CALIBRATION_DATA_VERIFICATION_FAILED \ + ((sl_status_t)0x100F9) ///< Calibration data verification failed. +#define SL_STATUS_SI91X_SNMP_INTERNAL_ERROR ((sl_status_t)0x10100) ///< SNMP internal error. +#define SL_STATUS_SI91X_SNMP_INVALID_IP_PROTOCOL ((sl_status_t)0x10104) ///< SNMP invalid IP protocol error. +#define SL_STATUS_SI91X_UNSUPPORTED_PWR_IDX_915 ((sl_status_t)0x10105) ///< Unsupported power index for 915 +#define SL_STATUS_SI91x_EFUSE_DATA_INVALID ((sl_status_t)0x10106) ///< Efuse data is invalid. +#define SL_STATUS_SI91X_NO_DATA_RECEIVED_OR_RECEIVE_TIMEOUT \ + ((sl_status_t)0x1BB01) ///< No data received or receive timeout. +#define SL_STATUS_SI91X_INSUFFICIENT_DATA_FOR_TIME_CONVERSION \ + ((sl_status_t)0x1BB08) ///< Insufficient data for converting NTP time to mm-dd-yy time format. +#define SL_STATUS_SI91X_INVALID_SNTP_SERVER_ADDRESS ((sl_status_t)0x1BB0A) ///< Invalid SNTP server address. +#define SL_STATUS_SI91X_SNTP_CLIENT_NOT_STARTED ((sl_status_t)0x1BB0B) ///< SNTP client not started. +#define SL_STATUS_SI91X_SNTP_SERVER_UNAVAILABLE \ + ((sl_status_t)0x1BB10) ///< SNTP server not available. Client will not get any time update service from current server. +#define SL_STATUS_SI91X_SNTP_SERVER_AUTHENTICATION_FAILED ((sl_status_t)0x1BB15) ///< SNTP server authentication failed. +#define SL_STATUS_SI91X_INTERNAL_ERROR ((sl_status_t)0x1BB0E) ///< Internal error. +#define SL_STATUS_SI91X_MULTICAST_IP_ADDRESS_ENTRY_NOT_FOUND \ + ((sl_status_t)0x1BB16) ///< Entry not found for multicast IP address. +#define SL_STATUS_SI91X_MULTICAST_NO_ENTRIES_FOUND ((sl_status_t)0x1BB17) ///< No more entries found for multicast. +#define SL_STATUS_SI91X_IP_ADDRESS_ERROR ((sl_status_t)0x1BB21) ///< IP address error. +#define SL_STATUS_SI91X_SOCKET_ALREADY_BOUND ((sl_status_t)0x1BB22) ///< Socket already bound. +#define SL_STATUS_SI91X_PORT_UNAVAILABLE ((sl_status_t)0x1BB23) ///< Port not available. +#define SL_STATUS_SI91X_SOCKET_NOT_CREATED ((sl_status_t)0x1BB27) ///< Socket is not created. +#define SL_STATUS_SI91X_ICMP_REQUEST_FAILED ((sl_status_t)0x1BB29) ///< ICMP request failed. +#define SL_STATUS_SI91X_MAX_LISTEN_SOCKETS_REACHED ((sl_status_t)0x1BB33) ///< Maximum listen sockets reached. +#define SL_STATUS_SI91X_DHCP_DUPLICATE_LISTEN ((sl_status_t)0x1BB34) ///< DHCP duplicate listen. +#define SL_STATUS_SI91X_PORT_NOT_IN_CLOSE_STATE ((sl_status_t)0x1BB35) ///< Port not in closed state. +#define SL_STATUS_SI91X_SOCKET_CLOSED ((sl_status_t)0x1BB36) ///< Socket is closed or in process of closing. +#define SL_STATUS_SI91X_PROCESS_IN_PROGRESS ((sl_status_t)0x1BB37) ///< Process in progress. +#define SL_STATUS_SI91X_CONNECT_TO_NON_EXISTING_TCP_SERVER_SOCKET \ + ((sl_status_t)0x1BB38) ///< Trying to connect to a non-existing TCP server socket. +#define SL_STATUS_SI91X_ERROR_IN_LEN_OF_THE_COMMAND \ + ((sl_status_t)0x1BB3E) ///< Error in the length of the command (exceeds the number of characters mentioned in the PRM). +#define SL_STATUS_SI91X_WRONG_PACKET_INFO ((sl_status_t)0x1BB40) ///< Wrong packet information. +#define SL_STATUS_SI91X_SOCKET_STILL_BOUND ((sl_status_t)0x1BB42) ///< Socket is still bound. +#define SL_STATUS_SI91X_NO_FREE_PORT ((sl_status_t)0x1BB45) ///< No free port available. +#define SL_STATUS_SI91X_INVALID_PORT ((sl_status_t)0x1BB46) ///< Invalid port specified. +#define SL_STATUS_SI91X_CORRUPTED_RPS_HEADER \ + ((sl_status_t)0x1BB49) ///< Corrupted RPS header encountered or Received empty RPS file(no data) during firmware update. +#define SL_STATUS_SI91X_FEATURE_UNSUPPORTED ((sl_status_t)0x1BB4B) ///< Feature not supported. +#define SL_STATUS_SI91X_SOCKET_IN_UNCONNECTED_STATE \ + ((sl_status_t)0x1BB50) ///< Socket is not in a connected state. Disconnected from the server. In the case of FTP, the user needs to issue a destroy command after receiving this error. +#define SL_STATUS_SI91X_POP3_SESSION_CREATION_FAILED \ + ((sl_status_t)0x1BB87) ///< POP3 session creation failed or POP3 session got terminated. +#define SL_STATUS_SI91X_DHCPV6_HANDSHAKE_FAIL ((sl_status_t)0x1BB9C) ///< DHCPv6 handshake failure. +#define SL_STATUS_SI91X_DHCP_INVALID_IP_RESPONSE ((sl_status_t)0x1BB9D) ///< DHCP invalid IP response. +#define SL_STATUS_SI91X_SMTP_AUTHENTICATION_ERROR ((sl_status_t)0x1BBA0) ///< SMTP authentication error. +#define SL_STATUS_SI91X_SMTP_OVER_SIZE_MAIL_DATA \ + ((sl_status_t)0x1BBA1) ///< No DNS server was specified, SMTP over size mail data. +#define SL_STATUS_SI91X_SMTP_INVALID_SERVER_REPLY ((sl_status_t)0x1BBA2) ///< SMTP invalid server reply. +#define SL_STATUS_SI91X_SMTP_DNS_QUERY_FAILED ((sl_status_t)0x1BBA3) ///< DNS query failed, SMTP internal error. +#define SL_STATUS_SI91X_SMTP_BAD_DNS_ADDRESS \ + ((sl_status_t)0x1BBA4) ///< Bad DNS address, SMTP server error code received. +#define SL_STATUS_SI91X_SMTP_INVALID_PARAMETERS ((sl_status_t)0x1BBA5) ///< SMTP invalid parameters. +#define SL_STATUS_SI91X_SMTP_PACKET_ALLOCATION_FAILED ((sl_status_t)0x1BBA6) ///< SMTP packet allocation failed. +#define SL_STATUS_SI91X_SMTP_GREET_REPLY_FAILED ((sl_status_t)0x1BBA7) ///< SMTP Greet reply failed. +#define SL_STATUS_SI91X_SMTP_PARAMETER_ERROR ((sl_status_t)0x1BBA8) ///< Parameter error, SMTP hello reply error. +#define SL_STATUS_SI91X_SMTP_MAIL_REPLY_ERROR ((sl_status_t)0x1BBA9) ///< SMTP mail reply error. +#define SL_STATUS_SI91X_SMTP_RCPT_REPLY_ERROR ((sl_status_t)0x1BBAA) ///< SMTP RCPT reply error. +#define SL_STATUS_SI91X_SMTP_MESSAGE_REPLY_ERROR ((sl_status_t)0x1BBAB) ///< SMTP message reply error. +#define SL_STATUS_SI91X_SMTP_DATA_REPLY_ERROR ((sl_status_t)0x1BBAC) ///< SMTP data reply error. +#define SL_STATUS_SI91X_SMTP_AUTH_REPLY_ERROR ((sl_status_t)0x1BBAD) ///< SMTP authentication reply error. +#define SL_STATUS_SI91X_SMTP_SERVER_REPLY_ERROR ((sl_status_t)0x1BBAE) ///< SMTP server error reply. +#define SL_STATUS_SI91X_DNS_DUPLICATE_ENTRY ((sl_status_t)0x1BBAF) ///< DNS duplicate entry. +#define SL_STATUS_SI91X_SMTP_OVERSIZE_SERVER_REPLY ((sl_status_t)0x1BBB1) ///< SMTP oversize server reply. +#define SL_STATUS_SI91X_SMTP_CLIENT_NOT_INITIALIZED ((sl_status_t)0x1BBB2) ///< SMTP client not initialized. +#define SL_STATUS_SI91X_DNS_IPV6_NOT_SUPPORTED ((sl_status_t)0x1BBB3) ///< DNS IPv6 not supported. +#define SL_STATUS_SI91X_INVALID_MAIL_INDEX_FOR_POP3_MAIL_RETRIEVE_COMMAND \ + ((sl_status_t)0x1BBC5) ///< Invalid mail index specified for the POP3 mail retrieve command. +#define SL_STATUS_SI91X_SSL_TLS_HANDSHAKE_FAILED ((sl_status_t)0x1BBD2) ///< SSL/TLS handshake process failed. +#define SL_STATUS_SI91X_FTP_CLIENT_DISCONNECTED \ + ((sl_status_t)0x1BBD3) ///< FTP client is either not connected or has been disconnected from the FTP server. +#define SL_STATUS_SI91X_FTP_CLIENT_NOT_DISCONNECTED \ + ((sl_status_t)0x1BBD4) ///< FTP client is still connected and has not been disconnected. +#define SL_STATUS_SI91X_FTP_FILE_NOT_OPENED ((sl_status_t)0x1BBD5) ///< FTP file could not be opened. +#define SL_STATUS_SI91X_SSL_TLS_HANDSHAKE_TIMEOUT_OR_FTP_FILE_NOT_CLOSED \ + ((sl_status_t)0x1BBD6) ///< SSL/TLS handshake timed out or the FTP file was not closed properly. +#define SL_STATUS_SI91X_FTP_EXPECTED_1XX_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBD9) ///< Expected 1XX response from the FTP server was not received. +#define SL_STATUS_SI91X_FTP_EXPECTED_2XX_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDA) ///< Expected 2XX response from the FTP server was not received. +#define SL_STATUS_SI91X_FTP_EXPECTED_22X_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDB) ///< Expected 22X response from the FTP server was not received. +#define SL_STATUS_SI91X_FTP_EXPECTED_23X_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDC) ///< Expected 23X response from the FTP server was not received. +#define SL_STATUS_SI91X_FTP_EXPECTED_3XX_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDD) ///< Expected 3XX response from the FTP server was not received. +#define SL_STATUS_SI91X_FTP_EXPECTED_33X_RESPONSE_NOT_RECEIVED \ + ((sl_status_t)0x1BBDE) ///< Expected 33X response from the FTP server was not received. +#define SL_STATUS_SI91X_HTTP_TIMEOUT ((sl_status_t)0x1BBE1) ///< HTTP request timed out. +#define SL_STATUS_SI91X_HTTP_FAILED ((sl_status_t)0x1BBE2) ///< HTTP request failed. +#define SL_STATUS_SI91X_HTTP_PUT_CLIENT_TIMEOUT ((sl_status_t)0x1BBE7) ///< HTTP PUT client request timed out. +#define SL_STATUS_SI91X_AUTHENTICATION_ERROR ((sl_status_t)0x1BBEB) ///< Authentication process failed. +#define SL_STATUS_SI91X_INVALID_PACKET_LENGTH \ + ((sl_status_t)0x1BBED) ///< Invalid packet length. Content length and received data length mismatch. +#define SL_STATUS_SI91X_SERVER_RESPONDS_BEFORE_REQUEST_COMPLETE \ + ((sl_status_t)0x1BBEF) ///< Server responds before HTTP client request is complete. +#define SL_STATUS_SI91X_HTTP_PASSWORD_TOO_LONG ((sl_status_t)0x1BBF0) ///< HTTP/HTTPS password is too long. +#define SL_STATUS_SI91X_MQTT_PING_TIMEOUT ((sl_status_t)0x1BBF1) ///< MQTT ping timeout error. +#define SL_STATUS_SI91X_MQTT_COMMAND_SENT_IN_INCORRECT_STATE \ + ((sl_status_t)0x1BBF2) ///< MQTT command sent in incorrect state. +#define SL_STATUS_SI91X_MQTT_ACK_TIMEOUT ((sl_status_t)0x1BBF3) ///< MQTT ACK timeout error. +#define SL_STATUS_SI91X_POP3_INVALID_MAIL_INDEX ((sl_status_t)0x1BBFF) ///< POP3 error for invalid mail index. +#define SL_STATUS_SI91X_FW_UPDATE_DONE ((sl_status_t)0x1DD03) ///< Firmware update successful. +#define SL_STATUS_SI91X_FW_UPDATE_FAILED ((sl_status_t)0x1DD04) ///< Firmware update failed. +#define SL_STATUS_SI91X_ALLOCATION_FAILED \ + ((sl_status_t)0x1DD3D) ///< Memory allocation failed in NWP during firmware upgradation. +#define SL_STATUS_SI91X_INSUFFICIENT_FLASH_MEMORY \ + ((sl_status_t)0x1DD3E) ///< Insufficient space in NWP flash memory during firmware upgradation. +#define SL_STATUS_SI91X_FW_UP_WRONG_PACKET_INFO ((sl_status_t)0x1DD40) ///< Wrong packet info. +#define SL_STATUS_SI91X_INVALID_LENGTH \ + ((sl_status_t)0x1DD41) ///< All payload chunks length together can't be greater than total image size in header, during firmware upgradation. +#define SL_STATUS_SI91X_SOCKET_NOT_CONNECTED \ + ((sl_status_t)0x1FFFF) ///< Listening TCP socket in device is not connected to the remote peer, or the LTCP socket is not yet opened in the device. +#define SL_STATUS_SI91X_SOCKET_LIMIT_EXCEEDED \ + ((sl_status_t)0x1FFFE) ///< Socket limit exceeded. More than 10 sockets opened. +#define SL_STATUS_SI91X_HTTP_OTAF_INVALID_PACKET ((sl_status_t)0x1FFFD) ///< HTTP OTAF invalid packet. +#define SL_STATUS_SI91X_TCP_IP_INIT_FAILED ((sl_status_t)0x1FFFC) ///< TCP/IP initialization failed. +#define SL_STATUS_SI91X_CONCURRENT_IP_CREATION_ERROR \ + ((sl_status_t)0x1FFFB) ///< Cannot create IP in same interface in concurrent mode. +#define SL_STATUS_SI91X_HTTP_OTAF_INCOMPLETE_PACKET ((sl_status_t)0x1FFF4) ///< HTTP OTAF incomplete packet. +#define SL_STATUS_SI91X_INVALID_STORE_CONFIGURATION_PROFILE \ + ((sl_status_t)0x1FFF5) ///< Invalid or mismatched store configuration profile type. +#define SL_STATUS_SI91X_MQTT_REMOTE_TERMINATE_ERROR ((sl_status_t)0x1FFF6) ///< MQTT remote terminate error. +#define SL_STATUS_SI91X_MQTT_KEEP_ALIVE_TERMINATE_ERROR \ + ((sl_status_t)0x1BBF1) ///< MQTT remote terminate error due to keep-alive response timeout. +#define SL_STATUS_SI91X_BYTE_STUFFING_ERROR_IN_AT_MODE ((sl_status_t)0x1FFF7) ///< Byte stuffing error in AT mode. +#define SL_STATUS_SI91X_INVALID_COMMAND_OR_OPERATION \ + ((sl_status_t)0x1FFF8) ///< Invalid command (e.g. parameters insufficient or invalid in the command). Invalid operation (e.g. power save command with the same mode given twice, accessing wrong socket, creating more than allowed sockets ). +#define SL_STATUS_SI91X_HTTP_OTAF_NO_PACKET ((sl_status_t)0x1FFF9) ///< HTTP OTAF no packet received. +#define SL_STATUS_SI91X_TCP_SOCKET_NOT_CONNECTED ((sl_status_t)0x1FFFA) ///< TCP socket is not connected. +#define SL_STATUS_SI91X_MAX_STATION_COUNT_EXCEEDED \ + ((sl_status_t)0x1FFC5) ///< Station count exceeded the maximum supported stations. +#define SL_STATUS_SI91X_UNABLE_TO_SEND_TCP_DATA ((sl_status_t)0x1FFC4) ///< Unable to send TCP data. +#define SL_STATUS_SI91X_SOCKET_BUFFER_TOO_SMALL ((sl_status_t)0x1FFBC) ///< Socket buffer too small. +#define SL_STATUS_SI91X_INVALID_CONTENT_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFBB) ///< Invalid content in the DNS response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_CLASS_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFBA) ///< DNS class error in response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_COUNT_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFB8) ///< DNS count error in response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_RETURN_CODE_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFB7) ///< DNS return code error in the response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_OPCODE_ERROR_IN_DNS_RESPONSE \ + ((sl_status_t)0x1FFB6) ///< DNS Opcode error in the response to the DNS resolution query. +#define SL_STATUS_SI91X_DNS_ID_MISMATCH \ + ((sl_status_t)0x1FFB5) ///< DNS id mismatch between the DNS resolution request and response. +#define SL_STATUS_SI91X_INVALID_INPUT_IN_DNS_QUERY \ + ((sl_status_t)0x1FFAB) ///< Invalid input provided in the DNS resolution query. +#define SL_STATUS_SI91X_DNS_RESPONSE_TIMEOUT ((sl_status_t)0x1FF42) ///< DNS response was timed out. +#define SL_STATUS_SI91X_ARP_REQUEST_FAILURE ((sl_status_t)0x1FFA1) ///< ARP request failure. +#define SL_STATUS_SI91X_UNABLE_TO_UPDATE_TCP_WINDOW ((sl_status_t)0x1FF91) ///< Failed to update TCP window. +#define SL_STATUS_SI91X_DHCP_LEASE_EXPIRED ((sl_status_t)0x1FF9D) ///< DHCP lease time expired. +#define SL_STATUS_SI91X_DHCP_HANDSHAKE_FAILURE ((sl_status_t)0x1FF9C) ///< DHCP handshake failure. +#define SL_STATUS_SI91X_WEBSOCKET_CREATION_FAILED ((sl_status_t)0x1FF88) ///< WebSocket creation failed. +#define SL_STATUS_SI91X_TRYING_TO_CONNECT_NON_EXISTENT_TCP_SERVER_SOCKET \ + ((sl_status_t)0x1FF87) ///< Attempted to connect to a non-existent TCP server socket on the remote side. +#define SL_STATUS_SI91X_TRYING_TO_CLOSE_NON_EXISTENT_SOCKET \ + ((sl_status_t)0x1FF86) ///< Attempted to close a non-existent or invalid socket descriptor. +#define SL_STATUS_SI91X_INVALID_SOCKET_PARAMETERS \ + ((sl_status_t)0x1FF85) ///< The provided socket parameters are invalid. +#define SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE ((sl_status_t)0x1FF82) ///< The requested feature is not supported. +#define SL_STATUS_SI91X_SOCKET_ALREADY_OPEN ((sl_status_t)0x1FF81) ///< The socket is already open. +#define SL_STATUS_SI91X_MAX_SOCKETS_EXCEEDED \ + ((sl_status_t)0x1FF80) ///< Attempted to open more than the maximum allowed number of sockets. +#define SL_STATUS_SI91X_DATA_LENGTH_EXCEEDS_MSS \ + ((sl_status_t)0x1FF7E) ///< Data length exceeds the Maximum Segment Size (MSS). +#define SL_STATUS_SI91X_IP_CONFLICT_ERROR \ + ((sl_status_t)0x1FF75) ///< Device unable to configure IP address due to an IP conflict. +#define SL_STATUS_SI91X_FEATURE_NOT_ENABLED ((sl_status_t)0x1FF74) ///< The requested feature is not enabled. +#define SL_STATUS_SI91X_DHCP_SERVER_NOT_SET ((sl_status_t)0x1FF73) ///< DHCP server is not configured in AP mode. +#define SL_STATUS_SI91X_AP_SET_REGION_PARAM_ERROR \ + ((sl_status_t)0x1FF71) ///< Invalid parameters provided for the AP set region command. +#define SL_STATUS_SI91X_SSL_TLS_NOT_SUPPORTED ((sl_status_t)0x1FF70) ///< SSL/TLS is not supported. +#define SL_STATUS_SI91X_JSON_NOT_SUPPORTED ((sl_status_t)0x1FF6F) ///< JSON format is not supported. +#define SL_STATUS_SI91X_INVALID_OPERATING_MODE ((sl_status_t)0x1FF6E) ///< The specified operating mode is invalid. +#define SL_STATUS_SI91X_INVALID_SOCKET_CONFIG_PARAMS \ + ((sl_status_t)0x1FF6D) ///< Invalid socket configuration parameters. +#define SL_STATUS_SI91X_WEBSOCKET_CREATION_TIMEOUT ((sl_status_t)0x1FF6C) ///< Web socket creation timeout. +#define SL_STATUS_SI91X_PARAM_MAX_VALUE_EXCEEDED \ + ((sl_status_t)0x1FF6B) ///< Parameter exceeds the maximum allowed value. +#define SL_STATUS_SI91X_SOCKET_READ_TIMEOUT ((sl_status_t)0x1FF6A) ///< The socket read operation timed out. +#define SL_STATUS_SI91X_INVALID_COMMAND_SEQUENCE ((sl_status_t)0x1FF69) ///< The command sequence is invalid. +#define SL_STATUS_SI91X_DNS_RESPONSE_TIMEOUT_ERROR ((sl_status_t)0x1FF42) ///< The DNS response timed out. +#define SL_STATUS_SI91X_HTTP_SOCKET_CREATION_FAILED ((sl_status_t)0x1FF41) ///< Failed to create an HTTP socket. +#define SL_STATUS_SI91X_HTTP_GET_CMD_IN_PROGRESS \ + ((sl_status_t)0x10005) ///< An HTTP GET command is currently in progress. +#define SL_STATUS_SI91X_TCP_CLOSE_BEFORE_RESPONSE_ERROR \ + ((sl_status_t)0x1FF40) ///< TCP socket close command issued before receiving the response of the previous close command. +#define SL_STATUS_SI91X_WAIT_ON_HOST_FEATURE_NOT_ENABLED \ + ((sl_status_t)0x1FF36) ///< 'Wait On Host' feature is not enabled. +#define SL_STATUS_SI91X_STORE_CONFIG_CHECKSUM_INVALID \ + ((sl_status_t)0x1FF35) ///< Store configuration checksum validation failed. +#define SL_STATUS_SI91X_TCP_KEEP_ALIVE_TIMEOUT ((sl_status_t)0x1FF33) ///< TCP keep-alive timed out. +#define SL_STATUS_SI91X_TCP_ACK_FAILED_FOR_SYN_ACK ((sl_status_t)0x1FF2D) ///< TCP ACK failed for TCP SYN-ACK. +#define SL_STATUS_SI91X_MEMORY_LIMIT_EXCEEDED \ + ((sl_status_t)0x1FF2C) ///< Memory limit exceeded in the given operating mode. +#define SL_STATUS_SI91X_MEMORY_LIMIT_EXCEEDED_DURING_AUTO_JOIN \ + ((sl_status_t)0x1FF2A) ///< Memory limit exceeded in the operating mode during auto join/create. +#define SL_STATUS_SI91X_MDNS_COMMAND_NOT_SUPPORTED ((sl_status_t)0x1FF2B) ///< The MDNS command type is invalid. +#define SL_STATUS_SI91X_PUF_OPERATION_BLOCKED ((sl_status_t)0x1CC2F) ///< The PUF operation is blocked. +#define SL_STATUS_SI91X_PUF_ACTIVATION_CODE_INVALID ((sl_status_t)0x1CC31) ///< The PUF activation code is invalid. +#define SL_STATUS_SI91X_PUF_INPUT_PARAMETERS_INVALID ((sl_status_t)0x1CC32) ///< The PUF input parameters are invalid. +#define SL_STATUS_SI91X_PUF_IN_ERROR_STATE ((sl_status_t)0x1CC33) ///< The PUF is in an error state. +#define SL_STATUS_SI91X_PUF_OPERATION_NOT_ALLOWED ((sl_status_t)0x1CC34) ///< The PUF operation is not allowed. +#define SL_STATUS_SI91X_PUF_OPERATION_FAILED ((sl_status_t)0x1CC35) ///< The PUF operation failed. +#define SL_STATUS_SI91X_CRYPTO_INPUT_MSG_LENGTH_EXCEEDED \ + ((sl_status_t)0x1CC9F) ///< Input message length exceed the expected length. +#define SL_STATUS_SI91X_AUTO_JOIN_IN_PROGRESS \ + ((sl_status_t)0x15A5A) ///< Auto join or user store configuration is in progress. +#define SL_STATUS_SI91X_RSNIE_FROM_AP_INVALID \ + ((sl_status_t)0x1FFE1) ///< Received an invalid RSNIE from the AP to the station. +#define SL_STATUS_SI91X_SNTP_MAX_ATTEMPTS_REACHED \ + ((sl_status_t)0x1FF5F) ///< Maximum number of invalid SNTP attempts reached. +#define SL_STATUS_SI91X_FREQUENCY_OFFSET_ZER0 ((sl_status_t)0x100FC) ///< The frequency offset sent is zero. +#define SL_STATUS_SI91X_FREQUENCY_OFFSET_OUT_OF_LIMITS \ + ((sl_status_t)0x100FB) ///< Frequency offset specified goes beyond upper or lower limits and indicates that frequency offset cannot be changed further. + +//Bluetooth Generic Error Codes +#define SL_STATUS_SI91X_UNKNOWN_HCI_COMMAND (0x4E01) ///< Unknown HCI command . +#define SL_STATUS_SI91X_UNKNOWN_CONNECTION_IDENTIFIER (0x4E02) ///< Unknown Connection Identifier . +#define SL_STATUS_SI91X_HARDWARE_FAILURE (0x4E03) ///< Hardware failure . +#define SL_STATUS_SI91X_PAGE_TIMEOUT (0x4E04) ///< Page timeout . +#define SL_STATUS_SI91X_AUTHENTICATION_FAILURE (0x4E05) ///< Authentication failure . +#define SL_STATUS_SI91X_PIN_MISSING (0x4E06) ///< Pin missing . +#define SL_STATUS_SI91X_MEMORY_CAPACITY_EXCEED (0x4E07) ///< Memory capacity exceeded . +#define SL_STATUS_SI91X_CONNECTION_TIMEOUT (0x4E08) ///< Connection timeout . +#define SL_STATUS_SI91X_CONNECTION_LIMIT_EXCEED (0x4E09) ///< Connection limit exceeded . +#define SL_STATUS_SI91X_SCO_LIMIT_EXCEED (0x4E0A) ///< SCO limit exceeded . +#define SL_STATUS_SI91X_ACL_CONNECTION_ALREADY_EXIST (0x4E0B) ///< ACL Connection already exists . +#define SL_STATUS_SI91X_COMMAND_DISALLOWED (0x4E0C) ///< Command disallowed . +#define SL_STATUS_SI91X_CONNECTION_REJECTED_LIMITED_RESOURCES \ + (0x4E0D) ///< Connection rejected due to limited resources . +#define SL_STATUS_SI91X_CONNECTION_REJECTED_SECURITY_REASONS (0x4E0E) ///< Connection rejected due to security reasons . +#define SL_STATUS_SI91X_CONNECTION_REJECTED_FOR_BD_ADDR (0x4E0F) ///< Connection rejected for BD address . +#define SL_STATUS_SI91X_CONNECTION_ACCEPT_TIMEOUT (0x4E10) ///< Connection accept timeout . +#define SL_STATUS_SI91X_UNSUPPORTED_FEATURE_OR_PARAMETER (0x4E11) ///< Unsupported feature or parameter . +#define SL_STATUS_SI91X_INVALID_HCI_COMMAND_PARAMETER (0x4E12) ///< Invalid HCI command parameter . +#define SL_STATUS_SI91X_REMOTE_USER_TERMINATED_CONNECTION (0x4E13) ///< Remote user terminated connection . +#define SL_STATUS_SI91X_REMOTE_DEVICE_TERMINATED_CONNECTION_LOW_RESOURCES \ + (0x4E14) ///< Remote device terminated connection due to low resources . +#define SL_STATUS_SI91X_REMOTE_DEVICE_TERMINATED_CONNECTION_POWER_OFF \ + (0x4E15) ///< Remote device terminated connection due to power off . +#define SL_STATUS_SI91X_LOCAL_DEVICE_TERMINATED_CONNECTION (0x4E16) ///< Local device terminated connection . +#define SL_STATUS_SI91X_REPEATED_ATTEMPTS (0x4E17) ///< Repeated attempts . +#define SL_STATUS_SI91X_PAIRING_NOT_ALLOWED (0x4E18) ///< Pairing not allowed . +#define SL_STATUS_SI91X_UNKNOWN_LMP_PDU (0x4E19) ///< Unknown LMP PDU . +#define SL_STATUS_SI91X_UNSUPPORTED_REMOTE_FEATURE (0x4E1A) ///< Unsupported remote feature . +#define SL_STATUS_SI91X_SCO_OFFSET_REJECTED (0x4E1B) ///< SCO offset rejected . +#define SL_STATUS_SI91X_SCO_INTERVAL_REJECTED (0x4E1C) ///< SCO interval rejected . +#define SL_STATUS_SI91X_SCO_AIR_MODE_REJECTED (0x4E1D) ///< SCO Air mode rejected . +#define SL_STATUS_SI91X_INVALID_LMP_PARAMETERS (0x4E1E) ///< Invalid LMP parameters . +#define SL_STATUS_SI91X_UNSPECIFIED (0x4E1F) ///< Unspecified . +#define SL_STATUS_SI91X_UNSUPPORTED_LMP_PARAMETER (0x4E20) ///< Unsupported LMP Parameter . +#define SL_STATUS_SI91X_ROLE_CHANGE_NOT_ALLOWED (0x4E21) ///< Role change not allowed . +#define SL_STATUS_SI91X_LMP_RESPONSE_TIMEOUT (0x4E22) ///< LMP response timeout . +#define SL_STATUS_SI91X_LMP_TRANSACTION_COLLISION (0x4E23) ///< LMP transaction collision . +#define SL_STATUS_SI91X_LMP_PDU_NOT_ALLOWED (0x4E24) ///< LMP PDU not allowed . +#define SL_STATUS_SI91X_ENCRYPTION_MODE_NOT_ACCEPTABLE (0x4E25) ///< Encryption mode not acceptable . +#define SL_STATUS_SI91X_LINK_KEY_CANNOT_CHANGE (0x4E26) ///< Link key cannot change . +#define SL_STATUS_SI91X_REQUESTED_QOS_NOT_SUPPORTED (0x4E27) ///< Requested QOS not supported . +#define SL_STATUS_SI91X_INSTANT_PASSED (0x4E28) ///< Instant passed . +#define SL_STATUS_SI91X_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED (0x4E29) ///< Pairing with unit key not supported . +#define SL_STATUS_SI91X_DIFFERENT_TRANSACTION_COLLISION (0x4E2A) ///< Different transaction collision . +#define SL_STATUS_SI91X_RESERVED_1 (0x4E2B) ///< Reserved 1 . +#define SL_STATUS_SI91X_QOS_PARAMETER_NOT_ACCEPTABLE (0x4E2C) ///< QOS parameter not acceptable . +#define SL_STATUS_SI91X_QOS_REJECTED (0x4E2D) ///< QOS rejected . +#define SL_STATUS_SI91X_CHANNEL_CLASSIFICATION_NOT_SUPPORTED (0x4E2E) ///< Channel classification not supported . +#define SL_STATUS_SI91X_INSUFFICIENT_SECURITY (0x4E2F) ///< Insufficient security . +#define SL_STATUS_SI91X_PARAMETER_OUT_OF_MANDATORY_RANGE (0x4E30) ///< Parameter out of mandatory range . +#define SL_STATUS_SI91X_RESERVED_2 (0x4E31) ///< Reserved 2 . +#define SL_STATUS_SI91X_ROLE_SWITCH_PENDING (0x4E32) ///< Role switch pending . +#define SL_STATUS_SI91X_RESERVED_3 (0x4E33) ///< Reserved 3 . +#define SL_STATUS_SI91X_RESERVED_SLOT_VIOLATION (0x4E34) ///< Reserved slot violation . +#define SL_STATUS_SI91X_ROLE_SWITCH_FAILED (0x4E35) ///< Role switch failed . +#define SL_STATUS_SI91X_EXTENDED_INQUIRY_RESPONSE_TOO_LARGE (0x4E36) ///< Extended Inquiry Response too large . +#define SL_STATUS_SI91X_EXTENDED_SECURE_SIMPLE_PAIRING_NOT_SUPPORTED (0x4E37) ///< Extended SSP not supported . +#define SL_STATUS_SI91X_HOST_BUSY_PAIRING (0X4E38) ///< Host busy pairing . +#define SL_STATUS_SI91X_PINCODE_REPLY_FOR_WRONG_BD_ADDRESS (0x4E39) ///< Wrong BD Address . +#define SL_STATUS_SI91X_CONNECTION_FAILED_ESTABLISHED (0x4E3E) ///< Connection Failed to be Established . +#define SL_STATUS_SI91X_INVALID_GAIN_TABLE_PAYLOAD_LENGTH (0x4F01) ///< Invalid Gain table payload length . +#define SL_STATUS_SI91X_INVALID_REGION (0x4F02) ///< Invalid Region . +#define SL_STATUS_SI91X_INVALID_GAIN_TABLE_OFFSET_REQUEST_TYPE (0x4F03) ///< Invalid Gain Table offset request type . +#define SL_STATUS_SI91X_INVALID_NODE_ID (0x4F04) ///< Invalid Node ID . +#define SL_STATUS_SI91X_BT_INVALID_COMMAND (0x4FF8) ///< BT Invalid Command . +#define SL_STATUS_SI91X_INVALID_ARGS (0x0101) ///< Invalid Args . +#define SL_STATUS_SI91X_UNKNOWN (0x0102) ///< Unknown . +#define SL_STATUS_SI91X_FIRMWARE_TIMEOUT (0x0103) ///< Firmware Timeout . +#define SL_STATUS_SI91X_MEMORY_ALLOC_FAIL (0x0104) ///< Memory alloc fail . +#define SL_STATUS_SI91X_IO_FAIL (0x0106) ///< I/O fail . +#define SL_STATUS_SI91X_UNSUPPORTED (0x0108) ///< Unsupported . +#define SL_STATUS_SI91X_SHORT_BUF (0x0109) ///< Short buf . +#define SL_STATUS_SI91X_BUF_OVERFLOW (0x010A) ///< Buf overflow . +#define SL_STATUS_SI91X_TOO_LARGE_BUF (0x010B) ///< Too large buf . +#define SL_STATUS_SI91X_I_O_ABORT (0x010C) ///< I/O abort . +#define SL_STATUS_SI91X_OPEN_FAIL (0x010D) ///< File open fail . +#define SL_STATUS_SI91X_OS_TASK_INVALID_PRIORITY (0x1010) ///< OS task invalid priority . +#define SL_STATUS_SI91X_OS_TASK_PRIO_EXISTS (0x1011) ///< OS task prio exists . +#define SL_STATUS_SI91X_OS_TASK_NOT_STOPPED (0x1012) ///< OS task not stopped . +#define SL_STATUS_SI91X_OS_SEM_MAX_VALUE (0x1020) ///< OS sem max value . +#define SL_STATUS_SI91X_OS_SEM_NOT_AVAILABLE (0x1021) ///< OS sem not available . +#define SL_STATUS_SI91X_OS_SEM_RESET (0x1022) ///< OS sem reset . +#define SL_STATUS_SI91X_OS_MUTEX_NOT_OWNER (0x1030) ///< OS mutex not owner . +#define SL_STATUS_SI91X_OS_MUTEX_NOT_LOCKED (0x1031) ///< OS mutex not locked . +#define SL_STATUS_SI91X_OS_MUTEX_LOCK_FAILED (0x1032) ///< OS mutex lock failed . +#define SL_STATUS_SI91X_OS_MUTEX_TRY_LOCK_FAILED (0x1033) ///< OS mutex try lock failed . +#define SL_STATUS_SI91X_OS_MSG_QUEUE_FULL (0x1040) ///< OS msg queue full . +#define SL_STATUS_SI91X_OS_MESSAGE_QUEUE_EMPTY (0x1041) ///< OS message queue empty . +#define SL_STATUS_SI91X_PIPE_EMPTY (0x1050) ///< Pipe empty . +#define SL_STATUS_SI91X_PIPE_FULL (0x1051) ///< Pipe full . +#define SL_STATUS_SI91X_INVALID_LEN (0x1052) ///< Invalid len . +#define SL_STATUS_SI91X_PIPE_READ_IN_USE (0x1053) ///< Pipe read in use . +#define SL_STATUS_SI91X_PIPE_WRITE_IN_USE (0x1054) ///< Pipe write in use . +#define SL_STATUS_SI91X_OS_TIMER_EXPIRED (0x1060) ///< OS timer expired . +#define SL_STATUS_SI91X_OS_TIMER_STATE_RUNNING (0x1061) ///< OS timer state running . +#define SL_STATUS_SI91X_OS_CANNOT_WAIT (0x1070) ///< OS cannot wait . +#define SL_STATUS_SI91X_OS_MEM_POOL_EMPTY (0x1080) ///< OS mem pool empty . +#define SL_STATUS_SI91X_OS_MEM_POOL_SIZE_SHORT (0x1081) ///< OS mem pool size short . + +//BLE Generic Error Codes +#define SL_STATUS_SI91X_DIRECTED_ADVERTISING_TIMEOUT (0x4E3C) ///< Directed Advertising Timeout . +#define SL_STATUS_SI91X_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE \ + (0x4E3D) ///< Connection terminated due to MIC failure . +#define SL_STATUS_SI91X_INVALID_HANDLE_RANGE (0x4E60) ///< Invalid Handle Range . +#define SL_STATUS_SI91X_MEMORY_IS_NOT_SUFFICIENT (0x4E61) ///< Memory is not sufficient . +#define SL_STATUS_SI91X_INVALID_PARAMETERS (0x4E62) ///< Invalid Parameters . +#define SL_STATUS_SI91X_BLE_BUFFER_COUNT_EXCEEDED (0x4E63) ///< BLE Buffer Count Exceeded . +#define SL_STATUS_SI91X_BLE_BUFFER_ALREADY_IN_USE (0x4E64) ///< BLE Buffer already in use . +#define SL_STATUS_SI91X_INVALID_ATTRIBUTE_LENGTH \ + (0x4E65) ///< Invalid Attribute Length When Small Buffer Mode is Configured . +#define SL_STATUS_SI91X_INVALID_NAME_LENGTH (0x4E66) ///< Invalid Name length when set to more than 16 bytes . + +//BLE Mode Error Codes +#define SL_STATUS_SI91X_INVALID_HANDLE (0x4A01) ///< Invalid Handle . +#define SL_STATUS_SI91X_READ_NOT_PERMITTED (0x4A02) ///< Read not permitted . +#define SL_STATUS_SI91X_WRITE_NOT_PERMITTED (0x4A03) ///< Write not permitted . +#define SL_STATUS_SI91X_INVALID_PDU (0x4A04) ///< Invalid PDU . +#define SL_STATUS_SI91X_INSUFFICIENT_AUTHENTICATION (0x4A05) ///< Insufficient authentication . +#define SL_STATUS_SI91X_REQUEST_NOT_SUPPORTED (0x4A06) ///< Request not supported . +#define SL_STATUS_SI91X_INVALID_OFFSET (0x4A07) ///< Invalid offset . +#define SL_STATUS_SI91X_INSUFFICIENTA_UTHORIZATION (0x4A08) ///< Insufficient authorization . +#define SL_STATUS_SI91X_PREPARE_QUEUE_FULL (0x4A09) ///< Prepare queue full . +#define SL_STATUS_SI91X_ATTRIBUTE_NOT_FOUND (0x4A0A) ///< Attribute not found . +#define SL_STATUS_SI91X_ATTRIBUTE_NOT_LONG (0x4A0B) ///< Attribute not Long . +#define SL_STATUS_SI91X_INSUFFICIENT_ENCRYPTION_KEY_SIZE (0x4A0C) ///< Insufficient encryption key size . +#define SL_STATUS_SI91X_INVALID_ATTRIBUTE_VALUE_LENGTH (0x4A0D) ///< Invalid attribute value length . +#define SL_STATUS_SI91X_UNLIKELY_ERROR (0x4A0E) ///< Unlikely error . +#define SL_STATUS_SI91X_INSUFFICIENT_ENCRYPTION (0x4A0F) ///< Insufficient encryption . +#define SL_STATUS_SI91X_UNSUPPORTED_GROUP_TYPE (0x4A10) ///< Unsupported group type . +#define SL_STATUS_SI91X_INSUFFICIENT_RESOURCES (0x4A11) ///< Insufficient resources . +#define SL_STATUS_SI91X_GATT_TIMEOUT (0x4A80) ///< GATT Timeout . +#define SL_STATUS_SI91X_DATA_MAINTAINED_IN_HOST (0x4AFF) ///< Data Maintained in Host . +#define SL_STATUS_SI91X_SMP_PASSKEY_ENTRY_FAILED (0x4B01) ///< SMP Passkey entry failed . +#define SL_STATUS_SI91X_SMP_OOB_NOT_AVAILABLE (0x4B02) ///< SMP OOB not available . +#define SL_STATUS_SI91X_SMP_AUTHENTICATION_REQUIREMENTS (0x4B03) ///< SMP Authentication Requirements . +#define SL_STATUS_SI91X_SMP_CONFIRM_VALUE_FAILED (0x4B04) ///< SMP confirm value failed . +#define SL_STATUS_SI91X_SMP_PAIRING_NOT_SUPPORTED (0x4B05) ///< SMP Pairing not supported . +#define SL_STATUS_SI91X_SMP_ENCRYPTION_KEY_SIZE_INSUFFICIENT (0x4B06) ///< SMP Encryption key size insufficient . +#define SL_STATUS_SI91X_SMP_COMMAND_NOT_SUPPORTED (0x4B07) ///< SMP command not supported . +#define SL_STATUS_SI91X_SMP_PAIRING_FAILED (0x4B08) ///< SMP pairing failed . +#define SL_STATUS_SI91X_SMP_REPEATED_ATTEMPTS (0x4B09) ///< SMP repeated attempts . +#define SL_STATUS_SI91X_SMP_INVALID_PARAMETERS (0x4B0A) ///< SMP Invalid parameters . +#define SL_STATUS_SI91X_SMP_DH_KEY_CHECK_FAILED (0x4B0B) ///< SMP DH Key check failed . +#define SL_STATUS_SI91X_SMP_NUMERIC_COMPARISON_FAILED (0x4B0C) ///< SMP Numeric Comparison Failed . +#define SL_STATUS_SI91X_SMP_INVALID_KEYS_GENERATED (0x4BFD) ///< SMP Invalid Keys Generated . +#define SL_STATUS_SI91X_SMP_IDENTICAL_PUBLIC_KEY (0x4BFE) ///< SMP Identical Public Key . +#define SL_STATUS_SI91X_PSM_CONN_FAILED (0x4C02) ///< PSM Conn Failed . +#define SL_STATUS_SI91X_BLE_REMOTE_DEVICE_FOUND (0x4D00) ///< BLE Remote device found . +#define SL_STATUS_SI91X_BLE_REMOTE_DEVICE_NOT_FOUND (0x4D01) ///< BLE Remote device not found . +#define SL_STATUS_SI91X_BLE_REMOTE_DEVICE_STRUCTURE_FULL (0x4D02) ///< BLE Remote device structure full . +#define SL_STATUS_SI91X_UNABLE_TO_CHANGE_STATE (0x4D03) ///< Unable to change state . +#define SL_STATUS_SI91X_BLE_NOT_CONNECTED (0x4D04) ///< BLE not Connected . +#define SL_STATUS_SI91X_BLE_SOCKET_NOT_AVAILABLE (0x4D05) ///< BLE socket not available. . +#define SL_STATUS_SI91X_ATTRIBUTE_RECORD_NOT_FOUND (0x4D06) ///< Attribute record not found . +#define SL_STATUS_SI91X_ATTRIBUTE_ENTRY_NOT_FOUND (0x4D07) ///< Attribute entry not found . +#define SL_STATUS_SI91X_PROFILE_RECORD_FULL (0x4D08) ///< Profile record full . +#define SL_STATUS_SI91X_ATTRIBUTE_RECORD_FULL (0x4D09) ///< Attribute record full . +#define SL_STATUS_SI91X_BLE_PROFILE_HANDLER_INVALID (0x4D0A) ///< BLE profile not found(profile handler invalid) . +#define SL_STATUS_SI91X_BLE_ATTRIBUTE_BUFFER_FULL (0x4D0B) ///< BLE Attribute Buffer Full . +#define SL_STATUS_SI91X_BLE_CONNECTION_SOCK_NOT_AVAILABLE (0x4D10) ///< BLE Connection Sock not Available . +#define SL_STATUS_SI91X_BLE_REMOTE_CREDITS_NOT_AVAILABLE (0x4D11) ///< BLE Remote Credits not Available . +#define SL_STATUS_SI91X_PARAMETER_OUTOFF_MANADATORY_RANGE (0x4D14) ///< Parameter is outoff the manadatory range . + +/** @} */ diff --git a/wiseconnect/components/common/inc/sl_constants.h b/wiseconnect/components/common/inc/sl_constants.h new file mode 100644 index 000000000..7c6ca5bfa --- /dev/null +++ b/wiseconnect/components/common/inc/sl_constants.h @@ -0,0 +1,204 @@ +/***************************************************************************/ /** + * @file sl_constants.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_additional_status.h" +#include +#include +#include +#include + +#define SL_STATUS_ENUM(prefix, name, value) prefix##_##name = (prefix##_ENUM_OFFSET + value) +#define SL_STATUS_SHARED_ENUM(prefix, name) prefix##_##name = (SL_##name) + +#ifdef __CC_ARM +#define BREAKPOINT() __asm__("bkpt #0") +#else +#define BREAKPOINT() __asm__("bkpt") +#endif + +#define SL_IPV4_ADDRESS_LENGTH 4 +#define SL_IPV6_ADDRESS_LENGTH 16 + +#ifndef UNUSED_VARIABLE +#define UNUSED_VARIABLE(x) (void)(x) +#endif // UNUSED_VARIABLE +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +#define ARRAY_COUNT(x) (sizeof(x) / sizeof *(x)) + +#ifndef FUZZING +#define SL_ASSERT(condition, ...) \ + do { \ + if (!(condition)) { \ + BREAKPOINT(); \ + } \ + } while (0) +#else +#define SL_ASSERT(condition, ...) \ + do { \ + if (!(condition)) { \ + } \ + } while (0) +#endif + +#define SL_WAIT_FOREVER 0xFFFFFFFF +#define SL_INVALID_POINTER ((void *)0xEFFFFFFF) // This can point to any location that will trigger an exception + +// Defines for log tags +#define ERROR_TAG "ERROR" +#define WARNING_TAG "WARNING" +#define DEBUG_TAG "DEBUG" +#define INFO_TAG "INFO" + +// Defines for error logging +#define PRINT_ERROR_LOGS 0 + +#define PRINT_STATUS(tag, status) printf("\r\n%s %s:%d: 0x%lu \r\n", tag, __FILE__, __LINE__, (unsigned long)status); + +#define SL_CHECK_STATUS(x) \ + do { \ + if (x != SL_SUCCESS) { \ + goto status_check_fail; \ + } \ + } while (0) + +#define SL_CHECK_STATUS_AND_LOG(x, log) \ + do { \ + if (x != SL_SUCCESS) { \ + SL_LOG(log); \ + goto status_check_fail; \ + } \ + } while (0) + +// Macros to help work with pointers / allocations +#define SL_VERIFY_POINTER_OR_EXIT(pointer) \ + do { \ + if ((pointer) == NULL) { \ + goto exit; \ + } \ + } while (0) + +#define SL_VERIFY_POINTER_OR_GOTO(pointer, label) \ + do { \ + if ((pointer) == NULL) { \ + goto label; \ + } \ + } while (0) + +#define SL_VERIFY_POINTER_OR_RETURN(pointer, status) \ + do { \ + if ((pointer) == NULL) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_STATUS(ERROR_TAG, status) \ + } \ + return (status); \ + } \ + } while (0) + +#define SL_VERIFY_SUCCESS_OR_CONTINUE(x) \ + do { \ + if (x != SL_STATUS_OK) { \ + continue; \ + } \ + } while (0) + +#define SL_VERIFY_SUCCESS_OR_EXIT(x) \ + do { \ + if (x != SL_STATUS_OK) { \ + goto exit; \ + } \ + } while (0) + +#define SL_VERIFY_SUCCESS_OR_RETURN(x) \ + do { \ + if ((x) != SL_STATUS_OK) { \ + return (x); \ + } \ + } while (0) + +#define SL_CLEANUP_MALLOC(pointer) \ + do { \ + if ((pointer) != NULL) { \ + free(pointer); \ + pointer = NULL; \ + } \ + } while (0) + +#define SL_VERIFY_PARAMETER(condition) \ + do { \ + if (!(condition)) { \ + return SL_BAD_ARG; \ + } \ + } while (0) + +#define VERIFY_STATUS_AND_RETURN(status) \ + do { \ + if (status != SL_STATUS_OK) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_STATUS(ERROR_TAG, status) \ + } \ + return status; \ + } \ + } while (0) + +#define VERIFY_STATUS_AND_GOTO(status, goto_label) \ + do { \ + if (status != SL_STATUS_OK) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_STATUS(ERROR_TAG, status) \ + } \ + goto goto_label; \ + } \ + } while (0) + +#define PRINT_ERROR_STATUS(tag, status) printf("\r\n%s %s:%d: 0x%x \r\n", tag, __FILE__, __LINE__, (unsigned int)status) + +#ifdef PRINT_DEBUG_LOG +extern void sl_debug_log(const char *format, ...); +#define SL_DEBUG_LOG(format, ...) \ + do { \ + sl_debug_log("%s:%s:%d:" format "\r\n", __FILE__, __func__, __LINE__, ##__VA_ARGS__); \ + } while (0) +#else +extern void sl_redirect_log(const char *format, ...); +#define SL_DEBUG_LOG(format, ...) \ + do { \ + sl_redirect_log("%s:%s:%d:" format "\r\n", __FILE__, __func__, __LINE__, ##__VA_ARGS__); \ + } while (0) +#endif + +#define SL_COMPILE_TIME_ASSERT(condition, comment) typedef char assertion_failed__##comment[2 * !!(condition)-1]; + +typedef uint32_t sl_duration_t; + +typedef void (*sl_event_handler_t)(void); diff --git a/wiseconnect/components/common/inc/sl_ieee802_types.h b/wiseconnect/components/common/inc/sl_ieee802_types.h new file mode 100644 index 000000000..72e89a711 --- /dev/null +++ b/wiseconnect/components/common/inc/sl_ieee802_types.h @@ -0,0 +1,53 @@ +/***************************************************************************/ /** + * @file + * @brief Common IEEE 802 types + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include + +/** \addtogroup SL_NET_TYPES */ +/** @{ */ + +/// The IEEE defined 48-bit extended unique identifier (EUI-48) +typedef struct { + uint8_t octet[6]; ///< Value of EUI-48 address +} sl_eui48_address_t; + +/// The IEEE defined 64-bit extended unique identifier (EUI-64) +typedef struct { + uint8_t octet[8]; ///< Value of EUI-64 address +} sl_eui64_address_t; + +/// Generic SL MAC address type +typedef sl_eui48_address_t sl_mac_address_t; + +/// Ethernet MAC address +typedef sl_eui48_address_t sl_ethernet_address_t; + +/** @} */ diff --git a/wiseconnect/components/common/inc/sl_ip_types.h b/wiseconnect/components/common/inc/sl_ip_types.h new file mode 100644 index 000000000..16035d78f --- /dev/null +++ b/wiseconnect/components/common/inc/sl_ip_types.h @@ -0,0 +1,97 @@ +/***************************************************************************/ /** + * @file + * @brief IP networking types + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once +#include "stdint.h" + +/** + * @addtogroup SL_NET_CONSTANTS + * @{ + */ + +/// Enumeration of IP version +typedef enum { + SL_IPV4_VERSION = 4, ///< IPv4 version + SL_IPV6_VERSION = 6 ///< IPv6 version +} sl_ip_version_t; + +/// Enumeration of IP address types/// Enumeration of IP address types. +typedef enum { + SL_IPV4 = (1 << 2), ///< IPv4 address + SL_IPV6 = (1 << 3), ///< IPv6, Unspecified sub-type + SL_IPV6_LINK_LOCAL = SL_IPV6 + 1, ///< IPv6, Link local address + SL_IPV6_SITE_LOCAL = SL_IPV6 + 2, ///< IPv6, Site local address + SL_IPV6_GLOBAL = SL_IPV6 + 3, ///< IPv6, Global address + SL_INVALID_IP = 0 ///< This enumeration value represents an invalid IP address. +} sl_ip_address_type_t; + +/// Enumeration of IP Management type +typedef enum { + SL_IP_MANAGEMENT_STATIC_IP = 1, ///< Assign STATIC IP address to an interface + SL_IP_MANAGEMENT_DHCP, ///< Assign IP address to an interface dynamically using DHCP + SL_IP_MANAGEMENT_LINK_LOCAL ///< Assign IP address using link-local addressing +} sl_ip_management_t; + +/** @} */ + +/** \addtogroup SL_NET_TYPES */ +/** @{ */ + +/// IPv4 address object +typedef union { + uint32_t value; ///< IPv4 address as a uint32_t + uint8_t bytes[4]; ///< IPv4 address as uint8_t[4] +} sl_ipv4_address_t; + +/// IPv6 address object +typedef union { + uint32_t value[4]; ///< IPv6 address as a uint32_t[4] + uint8_t bytes[16]; ///< IPv6 address as uint8_t[16] +} sl_ipv6_address_t; + +/// Generic IP Address Structure. Supports both IPv4 and IPv6 addresses +#pragma pack(1) +typedef struct { + /// IP address object + union { + sl_ipv4_address_t v4; ///< IPv4 address + sl_ipv6_address_t v6; ///< IPv6 address + } ip; + + sl_ip_address_type_t type; ///< IP address type +} sl_ip_address_t; +#pragma pack() + +/** @} */ + +/// Macro to assist initializing an IPv4 address +#define SL_IPV4_ADDRESS(a, b, c, d) \ + { \ + .ip.v4.bytes = { a, b, c, d }, .type = SL_IPV4 \ + } diff --git a/wiseconnect/components/common/inc/sl_utility.h b/wiseconnect/components/common/inc/sl_utility.h new file mode 100644 index 000000000..4e954b584 --- /dev/null +++ b/wiseconnect/components/common/inc/sl_utility.h @@ -0,0 +1,92 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_ip_types.h" +#include "sl_ieee802_types.h" +#include "sl_wifi_types.h" + +/***************************************************************************/ /** + * @brief + * Convert a character string into a sl_ipv4_address_t + * @param line + * Argument string that is expected to be like 192.168.0.1 + * @param ip + * Pointer to sl_ipv4_address_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t convert_string_to_sl_ipv4_address(char *line, sl_ipv4_address_t *ip); + +/***************************************************************************/ /** +* @brief +* Convert IPv6 binary address into presentation (printable) format +* @param[in] input +* A pointer to the buffer containing the binary IPV6 address +* @param[in] dst +* A pointer to the buffer where the resulting string will be stored +* @param[in] size +* The size of the destination buffer in bytes +* @return +* A pointer to a resulting string containing human readable representation of IPV6 address. +******************************************************************************/ +char *sl_inet_ntop6(const unsigned char *input, char *dst, uint32_t size); + +/***************************************************************************/ /** + * @brief + * Convert a character string into a [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t) + * @param line + * Argument string that is expected to be like 00:11:22:33:44:55 + * @param mac + * Pointer to [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t). + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t convert_string_to_mac_address(const char *line, sl_mac_address_t *mac); + +void print_sl_ip_address(const sl_ip_address_t *sl_ip_address); +void print_sl_ipv4_address(const sl_ipv4_address_t *ip_address); +void print_sl_ipv6_address(const sl_ipv6_address_t *ip_address); +void print_mac_address(const sl_mac_address_t *mac_address); +void convert_uint32_to_bytestream(uint16_t data, uint8_t *buffer); +void little_to_big_endian(const unsigned int *source, unsigned char *result, unsigned int length); +int sl_inet_pton6(const char *src, const char *src_endp, unsigned char *dst, unsigned int *ptr_result); +void reverse_digits(unsigned char *xx, int no_digits); +void print_firmware_version(const sl_wifi_firmware_version_t *firmware_version); + +/***************************************************************************/ /** + * @brief Print 802.11 packet + * + * @param[in] packet - pointer to start of MAC header + * @param[in] packet_length - total packet length (MAC header + payload) + * @param[in] max_payload_length - maximum number of payload bytes to print + ******************************************************************************/ +void print_80211_packet(const uint8_t *packet, uint32_t packet_length, uint16_t max_payload_length); diff --git a/wiseconnect/components/common/src/sl_utility.c b/wiseconnect/components/common/src/sl_utility.c new file mode 100644 index 000000000..c7ceed9a5 --- /dev/null +++ b/wiseconnect/components/common/src/sl_utility.c @@ -0,0 +1,361 @@ +/***************************************************************************/ /** + * @file sl_utility.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include "sl_utility.h" +#include "sl_constants.h" +#include "sl_string.h" +#include "cmsis_compiler.h" +#include +#include + +#ifdef SPRINTF_CHAR +#define SPRINTF(x) strlen(sprintf /**/ x) +#else +#define SPRINTF(x) ((size_t)sprintf x) +#endif + +#define DIGIT_VAL(c) \ + (((c >= '0') && (c <= '9')) ? (c - '0') \ + : ((c >= 'a') && (c <= 'z')) ? (c - 'a' + 10) \ + : ((c >= 'A') && (c <= 'Z')) ? (c - 'A' + 10) \ + : -1) +typedef struct { + int base; + int len; +} data_t; + +extern char *strtok_r(char *, const char *, char **); + +void convert_uint32_to_bytestream(uint16_t data, uint8_t *buffer) +{ + buffer[0] = (uint8_t)(data & 0xFF); + buffer[1] = (uint8_t)((data >> 8) & 0xFF); + buffer[2] = (uint8_t)((data >> 16) & 0xFF); + buffer[3] = (uint8_t)((data >> 24) & 0xFF); + return; +} + +sl_status_t convert_string_to_sl_ipv4_address(char *line, sl_ipv4_address_t *ip) +{ + char *lasts = NULL; + const char *token = strtok_r(line, ".", &lasts); + + for (uint8_t i = 0; i < 4; i++, token = strtok_r(NULL, ".", &lasts)) { + if (token == NULL) { + return SL_STATUS_COMMAND_IS_INVALID; + } + ip->bytes[i] = (uint8_t)strtoul(token, 0, 0); + } + return SL_STATUS_OK; +} + +void print_sl_ip_address(const sl_ip_address_t *sl_ip_address) +{ + if (sl_ip_address == NULL) { + return; + } + + if (sl_ip_address->type == SL_IPV4) { + print_sl_ipv4_address(&sl_ip_address->ip.v4); + } else if (sl_ip_address->type == SL_IPV6) { + print_sl_ipv6_address(&sl_ip_address->ip.v6); + } +} + +void print_sl_ipv4_address(const sl_ipv4_address_t *ip_address) +{ + printf("%d.%d.%d.%d", ip_address->bytes[0], ip_address->bytes[1], ip_address->bytes[2], ip_address->bytes[3]); +} + +void print_sl_ipv6_address(const sl_ipv6_address_t *ip_address) +{ + char temp_buffer[46] = { 0 }; + sl_inet_ntop6((const unsigned char *)(ip_address), (char *)temp_buffer, sizeof(temp_buffer)); + printf("%s\r\n", temp_buffer); +} + +void print_mac_address(const sl_mac_address_t *mac_address) +{ + if (mac_address == NULL) { + return; + } + printf("%2X:%2X:%2X:%2X:%2X:%2X", + mac_address->octet[0], + mac_address->octet[1], + mac_address->octet[2], + mac_address->octet[3], + mac_address->octet[4], + mac_address->octet[5]); +} + +char *sl_inet_ntop6(const unsigned char *input, char *dst, uint32_t size) +{ + char tmp[sizeof "ffff:ffff:ffff:ffff:ffff:ffff:255.255.255.255"]; + char *tp; + data_t best; + data_t cur; + unsigned int words[SL_IPV6_ADDRESS_LENGTH / 2]; + int i; + unsigned int ip_big_endian[4]; + const unsigned char *src; + src = (unsigned char *)&ip_big_endian; + + little_to_big_endian((const unsigned int *)input, (unsigned char *)ip_big_endian, SL_IPV6_ADDRESS_LENGTH); + + memset(words, '\0', sizeof words); + for (i = 0; i < SL_IPV6_ADDRESS_LENGTH; i += 2) { + int temp = src[i]; + words[i / 2] = (temp << 8) | src[i + 1]; + } + best.base = -1; + cur.base = -1; + best.len = 0; + cur.len = 0; + for (i = 0; i < (SL_IPV6_ADDRESS_LENGTH / 2); i++) { + if (words[i] == 0) { + if (cur.base == -1) { + cur.base = i; + cur.len = 1; + } else + cur.len++; + } else { + if (cur.base != -1) { + if (best.base == -1 || cur.len > best.len) + best = cur; + cur.base = -1; + } + } + } + if ((cur.base != -1) && (best.base == -1 || cur.len > best.len)) + best = cur; + if (best.base != -1 && best.len < 2) + best.base = -1; + /* + * Format the result. + */ + tp = tmp; + for (i = 0; i < (SL_IPV6_ADDRESS_LENGTH / 2); i++) { + /* Are we inside the best run of 0x00's? */ + if (best.base != -1 && i >= best.base && i < (best.base + best.len)) { + if (i == best.base) + *tp++ = ':'; + continue; + } + /* Are we following an initial run of 0x00s or any real hex? */ + if (i != 0) + *tp++ = ':'; + tp += SPRINTF((tp, "%x", words[i])); + } + /* Was it a trailing run of 0x00's? */ + if (best.base != -1 && (best.base + best.len) == (SL_IPV6_ADDRESS_LENGTH / 2)) + *tp++ = ':'; + *tp++ = '\0'; + /* + * Check for overflow, copy, and we're done. + */ + if ((uint32_t)(tp - tmp) > size) { + printf("\r\n Error \r\n"); + return NULL; + } + return memcpy(dst, tmp, size); +} + +static int hex_digit_value(char ch) +{ + if ('0' <= ch && ch <= '9') + return ch - '0'; + if ('a' <= ch && ch <= 'f') + return ch - 'a' + 10; + if ('A' <= ch && ch <= 'F') + return ch - 'A' + 10; + return -1; +} + +void little_to_big_endian(const unsigned int *source, unsigned char *result, unsigned int length) +{ + unsigned char *temp; + unsigned int curr = 0; + length /= 4; + + for (unsigned int i = 0; i < length; i++) { + curr = source[i]; + temp = &result[i * 4]; + temp[3] = (curr & 0xFF); + temp[2] = ((curr >> 8) & 0xFF); + temp[1] = ((curr >> 16) & 0xFF); + temp[0] = ((curr >> 24) & 0xFF); + } +} + +int sl_inet_pton6(const char *src, const char *src_endp, unsigned char *dst, unsigned int *ptr_result) +{ + unsigned char tmp[SL_IPV6_ADDRESS_LENGTH]; + unsigned char *tp; + unsigned char *endp; + unsigned char *colonp; + const char *curtok __attribute__((__unused__)); + int ch; + size_t xdigits_seen; /* Number of hex digits since colon. */ + unsigned int val; + tp = memset(tmp, '\0', SL_IPV6_ADDRESS_LENGTH); + endp = tp + SL_IPV6_ADDRESS_LENGTH; + colonp = NULL; + + /* Leading :: requires some special handling. */ + if (src == src_endp) + return 0; + if (*src == ':') { + ++src; + if (src == src_endp || *src != ':') + return 0; + } + + curtok = src; + xdigits_seen = 0; + val = 0; + + while (src < src_endp) { + ch = *src++; + int digit = hex_digit_value((char)ch); + //printf(" digit :%d ",digit); + if (digit >= 0) { + if (xdigits_seen == 4) + return 0; + val <<= 4; + val |= digit; + if (val > 0xffff) + return 0; + ++xdigits_seen; + continue; + } + if (ch == ':') { + curtok = src; + + if (xdigits_seen == 0) { + if (colonp) + return 0; + colonp = tp; + continue; + } else if (src == src_endp) + return 0; + if (tp + 2 > endp) + return 0; + + *tp++ = (unsigned char)(val >> 8) & 0xff; + *tp++ = (unsigned char)val & 0xff; + + xdigits_seen = 0; + val = 0; + continue; + } + } + + if (xdigits_seen > 0) { + if (tp + 2 > endp) + return 0; + *tp++ = (unsigned char)(val >> 8) & 0xff; + *tp++ = (unsigned char)val & 0xff; + } + if (colonp != NULL) { + /* Replace :: with zeros. */ + if (tp == endp) + /* :: would expand to a zero-width field. */ + return 0; + size_t n = tp - colonp; + memmove(endp - n, colonp, n); + memset(colonp, 0, endp - n - colonp); + tp = endp; + } + if (tp != endp) + return 0; + + memcpy(dst, tmp, SL_IPV6_ADDRESS_LENGTH); + little_to_big_endian((const unsigned int *)dst, (unsigned char *)ptr_result, SL_IPV6_ADDRESS_LENGTH); + + return 1; +} + +sl_status_t convert_string_to_mac_address(const char *line, sl_mac_address_t *mac) +{ + // Verify we have the exact number of characters. Basic argument verification + if (sl_strnlen((char *)line, 18) != 17) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint8_t index = 0; + while (index < 6) { + // Read all the data and verify validity + int char1 = DIGIT_VAL(line[0]); + int char2 = DIGIT_VAL(line[1]); + if (char1 == -1 || char2 == -1 || (line[2] != '\0' && line[2] != ':')) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Store value + mac->octet[index++] = (uint8_t)((uint8_t)char1 << 4) + (uint8_t)char2; + line += 3; + } + + return SL_STATUS_OK; +} + +void reverse_digits(unsigned char *xx, int no_digits) +{ + uint8_t temp; + for (int count = 0; count < (no_digits / 2); count++) { + temp = xx[count]; + xx[count] = xx[no_digits - count - 1]; + xx[no_digits - count - 1] = temp; + } +} + +void print_firmware_version(const sl_wifi_firmware_version_t *firmware_version) +{ + printf("\r\nFirmware version is: %x%x.%d.%d.%d.%d.%d.%d\r\n", + firmware_version->chip_id, + firmware_version->rom_id, + firmware_version->major, + firmware_version->minor, + firmware_version->security_version, + firmware_version->patch_num, + firmware_version->customer_id, + firmware_version->build_num); +} + +__WEAK void sl_debug_log(const char *format, ...) +{ + UNUSED_PARAMETER(format); +} + +void sl_redirect_log(const char *format, ...) +{ + UNUSED_PARAMETER(format); +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h new file mode 100644 index 000000000..24288ceaa --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/config/sl_board_configuration.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* @file sl_board_configuration.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#pragma once + +#include + +#define DEFAULT_UART NULL +#define DEFAULT_UART_PIN_CONFIG NULL diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h new file mode 100644 index 000000000..bac2e38cb --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/base_types.h @@ -0,0 +1,139 @@ +/****************************************************************************** +* @file base_types.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include "stdint.h" +#include +#include +/*****************************************************************************/ +/* Global pre-processor symbols/macros */ +/*****************************************************************************/ +#ifndef TRUE +/** Value is true (boolean_t type) */ +#define TRUE 1 +#endif + +#ifndef FALSE +/** Value is false (boolean_t type) */ +#define FALSE 0 +#endif + +#ifndef MIN +/** Returns the minimum value out of two values */ +#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) +#endif +#ifndef MAX +/** Returns the maximum value out of two values */ +#define MAX(X, Y) ((X) > (Y) ? (X) : (Y)) +#endif +/** Returns the dimension of an array */ +#define DIM(X) (sizeof(X) / sizeof(X[0])) + +#ifndef BIT +#define BIT(x) ((uint32_t)1U << (x)) +#endif +typedef enum en { Enable = 1, Disable = 0 } en_t; +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCCI character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t); + +#define RSI_DRIVER_VERSION_MAJOR_MINOR(major, minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version + */ +typedef struct _RSI_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} RSI_DRIVER_VERSION_M4; + +/* General return codes */ +#define RSI_DRIVER_OK 0 ///< Operation succeeded +#define RSI_DRIVER_ERROR -1 ///< Unspecified error +#define RSI_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define RSI_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define RSI_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define RSI_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define RSI_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +#define SET_BIT(n) BIT(n) //((uint32_t)1 << n) +#define CLR_BIT(n) ~BIT(n) //(~((uint32_t)1 << n)) + +#ifndef STATIC +#define STATIC static +#endif + +#ifndef INLINE +#ifdef __CC_ARM +#define INLINE __inline +#else +#define INLINE inline +#endif +#endif + +#define ENABLE 1 +#define DISABLE 0 + +#ifdef __cplusplus +} +#endif + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF */ +/******************************************************************************/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/data_types.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/data_types.h new file mode 100644 index 000000000..a686529b3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/data_types.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* @file data_types.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +/** @file data_types.h + * + * @brief This file contains data types defines + * + */ + +#ifndef DATA_TYPES_H +#define DATA_TYPES_H + +#include + +//! unsigned char is mapped to uint8 +typedef uint8_t uint8; +//! char is mapped to int8 +typedef int8_t int8; +//! unsigned short int is mapped as uint16 +typedef uint16_t uint16; +//! short int is mapped as int16 +typedef int16_t int16; +//! unsigned int is mapped as uint32 +typedef uint32_t uint32; +//! int is mapped as uint32 +typedef int32_t int32; + +#ifdef SINGLE_IMAGE + +typedef unsigned char UINT8; +typedef char INT8; +typedef unsigned short UINT16; + +typedef char STR; /* 8-bit character */ +typedef unsigned short WSTR; /* 16-bit character */ +typedef unsigned char BYTE; /* 8-bit unsigned integer */ +typedef unsigned char UINT08; /* 8-bit unsigned integer */ +typedef signed char INT08; /* 8-bit signed integer */ +typedef signed short INT16; /* 16-bit signed integer */ +typedef unsigned int UINT32; /* 32-bit unsigned integer */ +typedef signed int INT32; /* 32-bit signed integer */ +typedef unsigned long long UINT64; /* 64-bit unsigned integer */ +typedef signed long long INT64; /* 64-bit signed integer */ +typedef unsigned long ULONG; /* 32-bit long unsigned. */ +typedef long LONG; /* 32-bit long signed. */ +typedef int INTSTK; /* Defines CPU stack word size (in octets). */ +typedef int INTBOOL; +typedef unsigned long SIZE_T; +typedef float FLOAT32; /* 32-bit floating point */ +typedef double FLOAT64; /* 64-bit floating point */ +typedef int INTERR; + +typedef volatile BYTE REG_BYTE; /* 8-bit register */ +typedef volatile UINT16 REG_WORD16; /* 8-bit register */ +typedef volatile UINT32 REG_WORD32; + +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef short SHORT; +typedef unsigned short USHORT; +#endif /* SINGLE_IMAGE */ + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/em_device.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/em_device.h new file mode 100644 index 000000000..4822d3bbc --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/em_device.h @@ -0,0 +1,60 @@ +/**************************************************************************/ /** + * @file em_device.h + * @brief Device-specific header file inclusion based on the defined part number. + * + * This section of the code includes the appropriate device-specific header files + * based on the defined part number. If the part number is not defined, it generates + * a preprocessor error. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2022 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H + +#define EXT_IRQ_COUNT SI91X_EXT_IRQ_COUNT + +#if defined(SLI_SI917) || defined(SLI_SI915) +#include "si91x_device.h" + +#ifdef SLI_SI917 +#include "RTE_Device_917.h" +#else +#include "RTE_Device_915.h" +#endif + +#else +#error "em_device.h: PART NUMBER undefined" +#endif /* SLI_SI917 || SLI_SI915 */ + +#endif /* EM_DEVICE_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h new file mode 100644 index 000000000..2f5ca80c4 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ccp_common.h @@ -0,0 +1,30 @@ +/****************************************************************************** +* @file rsi_cpp_common.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#include "rsi_ccp_user_config.h" +#include "em_device.h" diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h new file mode 100644 index 000000000..b0f83061c --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_error.h @@ -0,0 +1,270 @@ +/******************************************************************************* +* @file rsi_error.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include + +#ifndef __RSI_ERROR_H__ +#define __RSI_ERROR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum errnoCode { + RSI_FAIL = -1, + RSI_OK = 0, + INVALID_PARAMETERS = 1, + + /*USART error codes*/ + ERROR_USART_BASE = 0x100, + ERROR_USART_CALLBACK_ERR = ERROR_USART_BASE + 1, + ERROR_USART_NOT_SUPPORTED = ERROR_USART_CALLBACK_ERR + 1, + + /* GPDMA error codes */ + ERROR_GPDMA_BASE = 0x200, + ERROR_GPDMA_INVALIDCHNLNUM = ERROR_GPDMA_BASE + 1, + ERROR_GPDMA_FLW_CTRL = ERROR_GPDMA_INVALIDCHNLNUM + 1, + ERROR_GPDMA_BURST = ERROR_GPDMA_FLW_CTRL + 1, + ERROR_GPDMA_SRC_ADDR = ERROR_GPDMA_BURST + 1, + ERROR_GPDMA_DST_ADDR = ERROR_GPDMA_SRC_ADDR + 1, + NOERR_GPDMA_FLAG_SET = ERROR_GPDMA_DST_ADDR + 1, + ERROR_GPDMA_INVALID_EVENT = NOERR_GPDMA_FLAG_SET + 1, + ERROR_GPDMA_INVALID_XFERMODE = ERROR_GPDMA_INVALID_EVENT + 1, + ERROR_GPDMA_INVALID_TRANS_LEN = ERROR_GPDMA_INVALID_XFERMODE + 1, + ERROR_GPDMA_INVALID_ARG = ERROR_GPDMA_INVALID_TRANS_LEN + 1, + ERROR_GPDMA_CHNL_BUSY = ERROR_GPDMA_INVALID_ARG + 1, + ERROR_GPDMA_NOT_ALIGNMENT = ERROR_GPDMA_CHNL_BUSY + 1, + ERROR_GPDMA_QUEUE_EMPTY = ERROR_GPDMA_NOT_ALIGNMENT + 1, + ERROR_GPDMA_GENERAL = ERROR_GPDMA_QUEUE_EMPTY + 1, + + /* UDMA error codes */ + ERROR_UDMA_BASE = 0x300, + ERROR_UDMA_INVALIDCHNLNUM = ERROR_UDMA_BASE + 1, + ERROR_UDMA_CTRL_BASE_INVALID = ERROR_UDMA_INVALIDCHNLNUM + 1, + ERROR_UDMA_INVALID_XFERMODE = ERROR_UDMA_CTRL_BASE_INVALID + 1, + ERROR_UDMA_INVALID_TRANS_LEN = ERROR_UDMA_INVALID_XFERMODE + 1, + ERROR_UDMA_INVALID_ARG = ERROR_UDMA_INVALID_TRANS_LEN + 1, + ERROR_UDMA_SRC_ADDR = ERROR_UDMA_INVALID_ARG + 1, + ERROR_UDMA_DST_ADDR = ERROR_UDMA_SRC_ADDR + 1, + ERROR_UDMA_CHNL_BUSY = ERROR_UDMA_DST_ADDR + 1, + + /* I2C error codes */ + ERROR_I2C_BASE = 0x400, + ERROR_I2C_INVALID_ARG = ERROR_I2C_BASE + 1, + ERROR_I2CS_UNKNOWN = ERROR_I2C_INVALID_ARG + 1, + ERROR_I2C_SPIKE_LOGIC = ERROR_I2CS_UNKNOWN + 1, + ERROR_I2C_IGNORE_GC_OR_START = ERROR_I2C_SPIKE_LOGIC + 1, + ERROR_I2C_STATUS_FLAG_NOT_SET = ERROR_I2C_IGNORE_GC_OR_START + 1, + ERROR_I2C_BUSY_FLAG = ERROR_I2C_STATUS_FLAG_NOT_SET + 1, + ERROR_I2C_MST_BUSY_FLAG = ERROR_I2C_BUSY_FLAG + 1, + ERROR_I2C_SLV_BUSY_FLAG = ERROR_I2C_MST_BUSY_FLAG + 1, + ERROR_I2C_SLV_DIS_WHILE_BUSY = ERROR_I2C_SLV_BUSY_FLAG + 1, + ERROR_I2C_MST_XFER_ABORT = ERROR_I2C_SLV_DIS_WHILE_BUSY + 1, + ERROR_I2C_MST_TX_CMD_BLOCK = ERROR_I2C_MST_XFER_ABORT + 1, + ERROR_I2C_SLV_RX_DATA_LOST = ERROR_I2C_MST_TX_CMD_BLOCK + 1, + ERROR_I2C_NO_TX_DATA = ERROR_I2C_SLV_RX_DATA_LOST + 1, + ERROR_I2C_NO_INTR_FLAG = ERROR_I2C_NO_TX_DATA + 1, + ERROR_I2C_ERROR_FLAG_NONE = ERROR_I2C_NO_INTR_FLAG + 1, + ERROR_I2C_INVALID_CB = ERROR_I2C_ERROR_FLAG_NONE + 1, + ERROR_I2C_INVALID_POINTER = ERROR_I2C_INVALID_CB + 1, + ERROR_I2C_GENERAL_FAILURE = ERROR_I2C_INVALID_POINTER + 1, + ERROR_I2C_TXABORT = ERROR_I2C_GENERAL_FAILURE + 1, + ERROR_I2C_SCL_STUCK_ATLOW = ERROR_I2C_TXABORT + 1, + ERROR_I2C_MST_ON_HOLD = ERROR_I2C_SCL_STUCK_ATLOW + 1, + ERROR_I2C_BUFFER_OVERFLOW = ERROR_I2C_MST_ON_HOLD + 1, + ERROR_I2C_BUFFER_UNDERFLOW = ERROR_I2C_BUFFER_OVERFLOW + 1, + + /* I2S error codes */ + ERROR_I2S_BASE = 0x500, + ERROR_I2S_INVALID_ARG = ERROR_I2S_BASE + 1, + ERROR_I2S_INVALID_RES = ERROR_I2S_INVALID_ARG + 1, + ERROR_I2S_INVALID_LENGTH = ERROR_I2S_INVALID_RES + 1, + ERROR_I2S_BUSY = ERROR_I2S_INVALID_LENGTH + 1, + ERROR_I2S_TXOVERRUN = ERROR_I2S_BUSY + 1, + ERROR_I2S_RXOVERRUN = ERROR_I2S_TXOVERRUN + 1, + ERROR_I2S_TXCOMPLETE = ERROR_I2S_RXOVERRUN + 1, + ERROR_I2S_RXCOMPLETE = ERROR_I2S_TXCOMPLETE + 1, + + /* UART error codes */ + ERROR_UART_BASE = 0x600, + ERROR_UART_INVALID_ARG = ERROR_UART_BASE + 1, + ERROR_UART_INVALID_RES = ERROR_UART_INVALID_ARG + 1, + + /* PWM error codes */ + ERROR_PWM_BASE = 0x700, + ERROR_PWM_INVALID_CHNLNUM = ERROR_PWM_BASE + 1, + ERROR_PWM_INVALID_PWMOUT = ERROR_PWM_INVALID_CHNLNUM + 1, + ERROR_PWM_NO_INTR = ERROR_PWM_INVALID_PWMOUT + 1, + ERROR_PWM_INVALID_ARG = ERROR_PWM_NO_INTR + 1, + + /* Timers error codes */ + ERROR_TIMER_BASE = 0x800, + ERROR_INVAL_TIMER_NUM = ERROR_TIMER_BASE + 1, + ERROR_INVAL_TIMER_MODE = ERROR_INVAL_TIMER_NUM + 1, + ERROR_INVAL_TIMERTYPE = ERROR_INVAL_TIMER_MODE + 1, + ERROR_INVAL_COUNTER_DIR = ERROR_INVAL_TIMERTYPE + 1, + + /* SCT error codes */ + ERROR_CT_BASE = 0x900, + ERROR_CT_INVALID_COUNTER_NUM = ERROR_CT_BASE + 1, + ERROR_CT_INVALID_ARG = ERROR_CT_INVALID_COUNTER_NUM + 1, + + /* EFUSE ERROR CODES */ + ERROR_EFUSE_BASE = 0xA00, + ERROR_EFUSE_INVALID_WRITE_ADDRESS = ERROR_EFUSE_BASE + 1, + ERROR_EFUSE_INVALID_WRITE_BIT_POSITION = ERROR_EFUSE_INVALID_WRITE_ADDRESS + 1, + ERROR_EFUSE_INVALID_PARAMETERS = ERROR_EFUSE_INVALID_WRITE_BIT_POSITION + 1, + + /* CCI ERROR CODES */ + ERROR_CCI_BASE_ADDRESS = 0xB00, + ERROR_CCI_INIT_FAIL = ERROR_CCI_BASE_ADDRESS + 1, + ERROR_CCI_ADDRESS_ERR = ERROR_CCI_INIT_FAIL + 1, + + /* QEI ERROR CODES */ + ERROR_QEI_BASE = 0xC00, + ERROR_INVALID_WRITE_ADDRESS = ERROR_QEI_BASE + 1, + ERROR_INVALID_WRITE_BIT_POSITION = ERROR_INVALID_WRITE_ADDRESS + 1, + ERROR_INVALID_PARAMETERS = ERROR_INVALID_WRITE_BIT_POSITION + 1, + + /* SDIO ERROR CODES */ + ERROR_SSDIO_BASE_ADDRESS = 0xD00, /*!< SDIO Error base address */ + ERROR_SSDIO_INIT_FAIL = ERROR_SSDIO_BASE_ADDRESS + 1, + ERROR_SSDIO_ADDRESS_ERR = ERROR_SSDIO_INIT_FAIL + 1, + ERROR_SSDIO_INVALID_FN = ERROR_SSDIO_ADDRESS_ERR + 1, + ERROR_SSDIO_INVALID_PARAM = ERROR_SSDIO_INVALID_FN + 1, + + /* SPI ERROR CODES*/ + ERROR_SSPI_BASE_ADDRESS = 0xE00, + ERROR_SSPI_INIT_FAIL = ERROR_SSPI_BASE_ADDRESS + 1, + ERROR_SSPI_ADDRESS_ERR = ERROR_SSPI_INIT_FAIL + 1, + ERROR_SSPI_CB_ERROR = ERROR_SSPI_ADDRESS_ERR + 1, + + /* ETHERNET ERROR CODES */ + ERROR_ETH_BASE_ADDRESS = 0xF00, + ERROR_ETH_INIT_FAIL = ERROR_ETH_BASE_ADDRESS + 1, + ERROR_ETH_PARAM = ERROR_ETH_INIT_FAIL + 1, + ERROR_ETH_NULL = ERROR_ETH_PARAM + 1, + ERR_DMA_NOT_ALIGNMENT = ERROR_ETH_NULL + 1, + ERROR_ETH_CALLBACK_ERR = ERR_DMA_NOT_ALIGNMENT + 1, + + /*CAN ERROR CODES*/ + ERROR_CAN_BASE = 0x1000, + ERROR_CAN_INVALID_PARAMETERS = ERROR_CAN_BASE + 1, + ERROR_CAN_INVALID_TIMING_PARAMETERS = ERROR_CAN_INVALID_PARAMETERS + 1, + ERROR_CAN_OPERATION_IN_PROGRESS = ERROR_CAN_INVALID_TIMING_PARAMETERS + 1, + + /*GSPI ERROR CODES*/ + ERROR_GSPI_BASE = 0x1100, + ERROR_GSPI_INVALID_ARG = ERROR_GSPI_BASE + 1, + ERROR_GSPI_INVALID_LENGTH = ERROR_GSPI_BASE + 2, + ERROR_GSPI_BUSY = ERROR_GSPI_BASE + 3, + ERROR_GSPI_READ_DONE = ERROR_GSPI_BASE + 4, + ERROR_GSPI_IDLE = ERROR_GSPI_BASE + 5, + ERROR_GSPI_TX_DONE = ERROR_GSPI_BASE + 6, + + /*SSI ERROR CODES*/ + ERROR_SSI_BASE = 0x1200, + ERROR_SSI_INVALID_ARG = ERROR_SSI_BASE + 1, + ERROR_SSI_BUSY = ERROR_SSI_BASE + 2, + ERROR_SSI_IDLE = ERROR_SSI_BASE + 3, + TRANSFER_COMPLETE = ERROR_SSI_BASE + 4, + READ_COMPLETED = ERROR_SSI_BASE + 5, + + /*SSI ERROR CODES*/ + ERROR_CRC_BASE = 0x1300, + ERROR_CRC_INVALID_ARG = ERROR_CRC_BASE + 1, + + /*SSI ERROR CODES*/ + ERROR_RNG_BASE = 0x1400, + ERROR_RNG_INVALID_ARG = ERROR_RNG_BASE + 1, + + /*NPSS ERROR CODES*/ + ERROR_BOD_BASE = 0x1500, + ERROR_PS_BASE = ERROR_BOD_BASE + 1, + ERROR_BOD_INVALID_PARAMETERS = ERROR_PS_BASE + 1, + ERROR_PS_INVALID_PARAMETERS = ERROR_BOD_INVALID_PARAMETERS + 1, + ERROR_PS_INVALID_STATE = ERROR_PS_INVALID_PARAMETERS + 1, + + /*TIME PERIOD*/ + ERROR_TIMEPERIOD_BASE = 0x1600, + ERROR_TIME_PERIOD_PARAMETERS = ERROR_TIMEPERIOD_BASE + 1, + ERROR_TIME_PERIOD_RC_CALIB_NOT_DONE = ERROR_TIME_PERIOD_PARAMETERS + 1, + ERROR_CAL_INVALID_PARAMETERS = ERROR_TIME_PERIOD_RC_CALIB_NOT_DONE + 1, + + /*M4SS CLOCKS */ + ERROR_M4SS_CLK_BASE = 0x1700, + ERROR_CLOCK_NOT_ENABLED = ERROR_M4SS_CLK_BASE + 1, + ERROR_INVALID_INPUT_FREQUENCY = ERROR_CLOCK_NOT_ENABLED + 1, + + /*ULPSS CLOCKS */ + ERROR_ULPCLK_BASE = 1800, + ERROR_ULPCLK_INVALID_PARAMETERS = ERROR_ULPCLK_BASE + 1, + + ERROR_SIO_BASE = 0x1900, + ERROR_SIO_I2C_NO_ACK = ERROR_SIO_BASE + 1, + + /* ULPSS FIM */ + ERROR_FIM_BASE = 0x2000, + ERROR_FIM_MATRIX_INVALID_ARG = ERROR_FIM_BASE + 1, + + /* AUX ADC */ + ERROR_NO_MULTI_CHNL_ENABLE = 0x2100, + NO_MODE_SET = ERROR_NO_MULTI_CHNL_ENABLE + 1, + ERROR_PING_PONG_ADDR_MATCH = ERROR_NO_MULTI_CHNL_ENABLE + 2, + ERROR_ADC_INVALID_ARG = ERROR_NO_MULTI_CHNL_ENABLE + 3, + INVALID_SAMPLING_RATE = ERROR_NO_MULTI_CHNL_ENABLE + 4, + INVALID_AUX_REF_VOLTAGE = ERROR_NO_MULTI_CHNL_ENABLE + 5, + INVALID_SAMPLE_LENGTH = ERROR_NO_MULTI_CHNL_ENABLE + 6, + INVALID_ADC_CHANNEL_ENABLE = ERROR_NO_MULTI_CHNL_ENABLE + 6, + + /* AUX DAC */ + ERROR_NO_PAD_SEL = 0x2200, + ERROR_FREQ_VAL = ERROR_NO_PAD_SEL + 1, + + /*SDMEM*/ + ERROR_ACCESS_RIGHTS = 0x2300, + ERROR_ADDR_ALIGHMENGT = ERROR_ACCESS_RIGHTS + 1, + ERROR_SMIH = ERROR_ADDR_ALIGHMENGT + 1, + ERROR_INAVLID_MODE = ERROR_SMIH + 1, + ERROR_OPERATION_INPROGRESS = ERROR_INAVLID_MODE + 1, + ERROR_NOT_READY = ERROR_OPERATION_INPROGRESS + 1, + ERROR_UNINITIALIZED = ERROR_NOT_READY + 1, + ERROR_BUFFER_FULL = ERROR_UNINITIALIZED + 1, + ERROR_TIMEOUT = ERROR_BUFFER_FULL + 1, + CARD_NOT_READY_OP = ERROR_TIMEOUT + 1, + CARD_TYPE_MEMCARD = CARD_NOT_READY_OP + 1, +} rsi_error_t; + +#ifdef __cplusplus +} +#endif + +#endif // __RSI_ERROR_H__ + +/*END OF FILE */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h new file mode 100644 index 000000000..5c98a682a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_ps_ram_func.h @@ -0,0 +1,38 @@ +/****************************************************************************** +* @file rsi_ps_ram_func.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/** + * Includes + */ + +/*This API will be called by the boot loader when it is from non retention wake up +when flash execution is enabled */ +void RSI_PS_Restore(void); +void Init_QspiStc(void); +void RSI_FLASH_Initialize(void); diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h new file mode 100644 index 000000000..f4c323e47 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/rsi_system_config.h @@ -0,0 +1,116 @@ +/****************************************************************************** +* @file rsi_system_config.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_SYSTEM_CONFIG_H__ +#define __RSI_SYSTEM_CONFIG_H__ +#include "rsi_ccp_common.h" + +#include "base_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t scdc_volt_sel1[]; +extern uint32_t lp_scdc_extcapmode[]; +extern uint32_t m32rc_osc_trim_efuse[]; +extern uint32_t m20rc_osc_trim_efuse[]; +extern uint32_t dblr_32m_trim_efuse[]; +extern uint32_t m20ro_osc_trim_efuse[]; +extern uint32_t ro_32khz_trim_efuse[]; +extern uint32_t rc_16khz_trim_efuse[]; +extern uint32_t rc_64khz_trim_efuse[]; +extern uint32_t rc_32khz_trim_efuse[]; +extern uint32_t vbatt_status_trim_efuse[]; +extern uint32_t ro_ts_efuse[]; +extern uint32_t ro_tempsense_config[]; +extern uint32_t vbg_tsbjt_efuse[]; +extern uint32_t auxadc_off_diff_efuse[]; +extern uint32_t auxadc_gain_diff_efuse[]; +extern uint32_t auxadc_off_se_efuse[]; +extern uint32_t auxadc_gain_se_efuse[]; +extern uint32_t bg_trim_efuse[]; +extern uint32_t blackout_trim_efuse[]; +extern uint32_t poc_bias_efuse[]; +extern uint32_t buck_trim_efuse[]; +extern uint32_t ldosoc_trim_efuse[]; +extern uint32_t dpwm_freq_trim_efuse[]; +extern uint32_t delvbe_tsbjt_efuse[]; +extern uint32_t xtal1_bias_efuse[]; +extern uint32_t xtal2_bias_efuse[]; +extern uint32_t bod_cmp_hyst[]; +extern uint32_t ipmu_bod_clks_common_config2[]; +extern uint32_t ipmu_bod_clks_common_config1[]; +extern uint32_t pmu_common_config[]; +extern uint32_t ipmu_common_config[]; +extern uint32_t xtal1_khz_fast_start_en[]; +extern uint32_t xtal1_khz_fast_start_disable[]; +extern uint32_t hp_ldo_voltsel[]; +extern uint32_t poc_bias_current_11[]; +extern uint32_t ro_32khz_trim00_efuse[]; +extern uint32_t retnLP_volt_trim_efuse[]; +extern uint32_t retnHP_volt_trim_efuse[]; +extern uint32_t hpldo_volt_trim_efuse[]; +extern uint32_t scdc_volt_trim_efuse[]; +extern uint32_t poc_bias_current[]; +extern uint32_t scdc_volt_sel2[]; +extern uint32_t scdc_volt_trim_efuse[]; +extern uint32_t ana_perif_ptat_common_config1[]; +extern uint32_t ana_perif_ptat_common_config2[]; +extern uint32_t retn_ldo_0p75[]; +extern uint32_t retn_ldo_lpmode[]; +extern uint32_t retn_ldo_hpmode[]; +extern uint32_t retn_ldo_voltsel[]; +extern uint32_t ipmu_scdc_enable[]; +extern uint32_t buck_fast_transient_duty_1p8[]; +extern uint32_t hpldo_tran[]; +extern uint32_t LDOFLASH_BYPASS[]; +#define POWER_TARN_DISABLE 0 +#define POWER_TARN_ALWAYS_USE 1 +#define POWER_TARN_CONDITIONAL_USE 2 + +#define XTAL_CAP_MODE POWER_TARN_CONDITIONAL_USE + +#define IPMU_DOTC_PROG +#define IPMU_CALIB_DATA +typedef uint32_t uint32; +typedef uint16_t uint16; +typedef int32_t int32; +typedef uint8_t uint8; +#define cmemcpy memcpy + +#ifdef __cplusplus +} +#endif + +#endif //__RSI_SYSTEM_CONFIG_H__ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h new file mode 100644 index 000000000..b6050aaad --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_device.h @@ -0,0 +1,16035 @@ +/****************************************************************************** +* @file si91x_device.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/** @addtogroup Silicon Lab Inc. + * @{ + */ + +/** @addtogroup RS1xxxx + * @{ + */ + +#ifndef __RS1XXXX_H__ +#define __RS1XXXX_H__ + +#include "base_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== + */ +/* ================ Interrupt Number Definition + * ================ */ +/* =========================================================================================================================== + */ + +typedef enum { + /* ======================================= ARM Cortex-M4 Specific Interrupt + Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, + including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, + other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal + State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* ========================================== RS1xxxx Specific Interrupt + Numbers =========================================== */ + TIMER0_IRQn = 2, /*!< 2 TIMER0 */ + TIMER1_IRQn = 3, /*!< 3 TIMER1 */ + TIMER2_IRQn = 4, /*!< 4 TIMER2 */ + TIMER3_IRQn = 5, /*!< 5 TIMER3 */ + CAP_SENSOR_IRQn = 6, /*!< 6 CAP_SENSOR */ + COMP2_IRQn = 7, /*!< 7 COMP2 */ + COMP1_IRQn = 8, /*!< 8 COMP1 */ + UDMA1_IRQn = 10, /*!< 10 UDMA1 */ + ADC_IRQn = 11, /*!< 11 ADC */ + ULPSS_UART_IRQn = 12, /*!< 12 ULPSS_UART */ + I2C2_IRQn = 13, /*!< 13 I2C2 */ + I2S1_IRQn = 14, /*!< 14 I2S1 */ + IR_DECODER_IRQn = 15, /*!< 15 IR_DECODER */ + SSI2_IRQn = 16, /*!< 16 SSI2 */ + FIM_IRQn = 17, /*!< 17 FIM */ + ULP_EGPIO_PIN_IRQn = 18, /*!< 18 ULP_EGPIO_PIN */ + ULP_EGPIO_GROUP_IRQn = 19, /*!< 19 ULP_EGPIO_GROUP */ + NPSS_TO_MCU_WDT_INTR_IRQn = 20, /*!< 20 NPSS_TO_MCU_WDT_INTR */ + NPSS_TO_MCU_GPIO_INTR_IRQn = 21, /*!< 21 NPSS_TO_MCU_GPIO_INTR */ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + NPSS_TO_MCU_SYRTC_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_SYSRTC_INTR */ +#else + NPSS_TO_MCU_CMP_RF_WKP_INTR_IRQn = 22, /*!< 22 NPSS_TO_MCU_CMP_RF_WKP_INTR */ +#endif + NPSS_TO_MCU_BOD_INTR_IRQn = 23, /*!< 23 NPSS_TO_MCU_BOD_INTR */ + NPSS_TO_MCU_BUTTON_INTR_IRQn = 24, /*!< 24 NPSS_TO_MCU_BUTTON_INTR */ + NPSS_TO_MCU_SDC_INTR_IRQn = 25, /*!< 25 NPSS_TO_MCU_SDC_INTR */ + NPSS_TO_MCU_WIRELESS_INTR_IRQn = 26, /*!< 26 NPSS_TO_MCU_WIRELESS_INTR */ + NPSS_MCU_INTR_IRQn = 27, /*!< 27 NPSS_MCU_INTR */ + MCU_CAL_ALARM_IRQn = 28, /*!< 28 MCU_CAL_ALARM */ + MCU_CAL_RTC_IRQn = 29, /*!< 29 MCU_CAL_RTC */ + GPDMA_IRQn = 31, /*!< 31 GPDMA */ + UDMA0_IRQn = 33, /*!< 33 UDMA0 */ + CT_IRQn = 34, /*!< 34 CT */ + HIF0_IRQn = 35, /*!< 35 HIF0 */ + HIF1_IRQn = 36, /*!< 36 HIF1 */ + SIO_IRQn = 37, /*!< 37 SIO */ + USART0_IRQn = 38, /*!< 38 USART0 */ + UART1_IRQn = 39, /*!< 39 UART1 */ + EGPIO_WAKEUP_IRQn = 41, /*!< 41 EGPIO_WAKEUP */ + I2C0_IRQn = 42, /*!< 42 I2C0 */ + SSISlave_IRQn = 44, /*!< 44 SSISlave */ + GSPI0_IRQn = 46, /*!< 46 GSPI0 */ + SSI0_IRQn = 47, /*!< 47 SSI0 */ + MCPWM_IRQn = 48, /*!< 48 MCPWM */ + QEI_IRQn = 49, /*!< 49 QEI */ + EGPIO_GROUP_0_IRQn = 50, /*!< 50 EGPIO_GROUP_0 */ + EGPIO_GROUP_1_IRQn = 51, /*!< 51 EGPIO_GROUP_1 */ + EGPIO_PIN_0_IRQn = 52, /*!< 52 EGPIO_PIN_0 */ + EGPIO_PIN_1_IRQn = 53, /*!< 53 EGPIO_PIN_1 */ + EGPIO_PIN_2_IRQn = 54, /*!< 54 EGPIO_PIN_2 */ + EGPIO_PIN_3_IRQn = 55, /*!< 55 EGPIO_PIN_3 */ + EGPIO_PIN_4_IRQn = 56, /*!< 56 EGPIO_PIN_4 */ + EGPIO_PIN_5_IRQn = 57, /*!< 57 EGPIO_PIN_5 */ + EGPIO_PIN_6_IRQn = 58, /*!< 58 EGPIO_PIN_6 */ + EGPIO_PIN_7_IRQn = 59, /*!< 59 EGPIO_PIN_7 */ + QSPI_IRQn = 60, /*!< 60 QSPI */ + I2C1_IRQn = 61, /*!< 61 I2C1 */ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + MVP_IRQn = 62, /*!< 62 MVP */ + MVP_WAKEUP_IRQn = 63, /*!< 63 MVP_WAKEUP */ +#endif + I2S0_IRQn = 64, /*!< 64 I2S0 */ + PLL_CLOCK_IRQn = 69, /*!< 69 PLL_CLOCK */ + TASS_P2P_IRQn = 74 /*!< 74 TASS_P2P */ +} IRQn_Type; + +/* =========================================================================================================================== + */ +/* ================ Processor and Core Peripheral + * Section ================ */ +/* =========================================================================================================================== + */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and + * Core Peripherals =========================== */ +#define __CM4_REV 0x0100U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_si91x.h" /*!< RS1xxxx System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ +#define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ +#define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ +#define __IOM __IO +#endif + +/* ======================================== Start of section using anonymous + * unions ======================================== */ +#if defined(__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined(__ICCARM__) +#pragma language = extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#pragma clang diagnostic ignored "-Wgnu-anonymous-struct" +#pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) +#pragma warning 586 +#elif defined(__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/* =========================================================================================================================== + */ +/* ================ Device Specific Cluster Section + * ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief MCPWM_PWM_DEADTIME [PWM_DEADTIME] ([0..3]) + */ +typedef struct { + union { + __IOM unsigned int PWM_DEADTIME_A; /*!< (@ 0x00000000) PWM deadtime for A and + channel varies from 0 to 3 */ + + struct { + __IOM unsigned int DEADTIME_A_CH : 6; /*!< [5..0] Dead time A value to load into dead + time counter A of channel0 to channel3 */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] reserved1 */ + } PWM_DEADTIME_A_b; + }; + + union { + __IOM unsigned int PWM_DEADTIME_B; /*!< (@ 0x00000004) PWM deadtime for B and + channel varies from 0 to 3 */ + + struct { + __IOM unsigned int DEADTIME_B_CH : 6; /*!< [5..0] Dead time B value to load into deadtime + counter B of channel0 to channel3 */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] reserved1 */ + } PWM_DEADTIME_B_b; + }; +} MCPWM_PWM_DEADTIME_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief GPDMA_G_GLOBAL [GLOBAL] (GLOBAL) + */ +typedef struct { + union { + __IOM unsigned int INTERRUPT_REG; /*!< (@ 0x00000000) Interrupt Register */ + + struct { + __IOM unsigned int GPDMAC_INT_STAT : 8; /*!< [7..0] Interrupt Status */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } INTERRUPT_REG_b; + }; + + union { + __IOM unsigned int INTERRUPT_MASK_REG; /*!< (@ 0x00000004) Interrupt Mask Register */ + + struct { + __IOM unsigned int RESERVED1 : 8; /*!< [7..0] reserved1 */ + __IOM unsigned int LINK_LIST_FETCH_MASK : 8; /*!< [15..8] Linked list fetch done + interrupt bit mask control. By default, + descriptor fetch done interrupt is + masked. */ + __IOM unsigned int TFR_DONE_MASK : 8; /*!< [23..16] Transfer done interrupt + bit mask control. */ + __IOM unsigned int RESERVED2 : 8; /*!< [31..24] reserved2 */ + } INTERRUPT_MASK_REG_b; + }; + + union { + __IOM unsigned int INTERRUPT_STAT_REG; /*!< (@ 0x00000008) Interrupt status register */ + + struct { + __IOM unsigned int HRESP_ERR0 : 1; /*!< [0..0] DMA error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE0 : 1; /*!< [1..1] This bit indicates the status + of linked list descriptor + fetch done for channel 0 */ + __IOM unsigned int TFR_DONE0 : 1; /*!< [2..2] This bit indicates the status of DMA + transfer done interrupt for channel 0 */ + __IOM unsigned int GPDMAC_ERR0 : 1; /*!< [3..3] transfer size or burst size or + h size mismatch error */ + __IOM unsigned int HRESP_ERR1 : 1; /*!< [4..4] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE1 : 1; /*!< [5..5] This bit indicates the status + of linked list descriptor + fetch done for channel 1 */ + __IOM unsigned int TFR_DONE1 : 1; /*!< [6..6] This bit indicates the status of DMA + transfer done interrupt for channel 1. */ + __IOM unsigned int GPDMAC_ERR1 : 1; /*!< [7..7] transfer size or burst size or + h size mismatch error */ + __IOM unsigned int HRESP_ERR2 : 1; /*!< [8..8] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE2 : 1; /*!< [9..9] This bit indicates the status + of linked list descriptor + fetch done for channel 2. */ + __IOM unsigned int TFR_DONE2 : 1; /*!< [10..10] This bit indicates the status of DMA + transfer done interrupt for channel 2. */ + __IOM unsigned int GPDMAC_ERR2 : 1; /*!< [11..11] transfer size or burst size + or h size mismatch error */ + __IOM unsigned int HRESP_ERR3 : 1; /*!< [12..12] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE3 : 1; /*!< [13..13] This bit indicates the status + of linked list descriptor + fetch done for channel 3. */ + __IOM unsigned int TFR_DONE3 : 1; /*!< [14..14] This bit indicates the status of DMA + transfer done interrupt for channel 3. */ + __IOM unsigned int GPDMAC_ERR3 : 1; /*!< [15..15] transfer size or burst size + or h size mismatch error */ + __IOM unsigned int HRESP_ERR4 : 1; /*!< [16..16] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE4 : 1; /*!< [17..17] This bit indicates the status + of linked list descriptor + fetch done for channel 4. */ + __IOM unsigned int TFR_DONE4 : 1; /*!< [18..18] This bit indicates the status of DMA + transfer done interrupt for channel 4. */ + __IOM unsigned int GPDMAC_ERR4 : 1; /*!< [19..19] transfer size or burst size + or h size mismatch error */ + __IOM unsigned int HRESP_ERR5 : 1; /*!< [20..20] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE5 : 1; /*!< [21..21] This bit indicates the status + of linked list descriptor + fetch done for channel 5. */ + __IOM unsigned int TFR_DONE5 : 1; /*!< [22..22] This bit indicates the status of DMA + transfer done interrupt for channel 5. */ + __IOM unsigned int GPDMAC_ERR5 : 1; /*!< [23..23] transfer size or burst size + or h size mismatch error */ + __IM unsigned int HRESP_ERR6 : 1; /*!< [24..24] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE6 : 1; /*!< [25..25] This bit indicates the status + of linked list descriptor + fetch done for channel 6. */ + __IOM unsigned int TFR_DONE6 : 1; /*!< [26..26] This bit indicates the status of DMA + transfer done interrupt for channel 6. */ + __IOM unsigned int GPDMAC_ERR6 : 1; /*!< [27..27] transfer size or burst size + or h size mismatch error */ + __IOM unsigned int HRESP_ERR7 : 1; /*!< [28..28] HRESP error bit */ + __IOM unsigned int LINK_LIST_FETCH_DONE7 : 1; /*!< [29..29] This bit indicates the status + of linked list descriptor + fetch done for channel 7. */ + __IOM unsigned int TFR_DONE7 : 1; /*!< [30..30] This bit indicates the status of DMA + transfer done interrupt for channel 7. */ + __IOM unsigned int GPDMAC_ERR7 : 1; /*!< [31..31] transfer size or burst size + or h size mismatch error */ + } INTERRUPT_STAT_REG_b; + }; + + union { + __IOM unsigned int DMA_CHNL_ENABLE_REG; /*!< (@ 0x0000000C) This register used + for enable DMA channel */ + + struct { + __IOM unsigned int CH_ENB : 8; /*!< [7..0] CWhen a bit is set to one, it indicates, + corresponding channel is enabled for dma operation */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_ENABLE_REG_b; + }; + + union { + __IOM unsigned int DMA_CHNL_SQUASH_REG; /*!< (@ 0x00000010) This register used + for enable DMA channel squash */ + + struct { + __IOM unsigned int CH_DIS : 8; /*!< [7..0] CPU Will be masked to write zeros, + CPU is allowed write 1 only */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_SQUASH_REG_b; + }; + + union { + __IOM unsigned int DMA_CHNL_LOCK_REG; /*!< (@ 0x00000014) This register used for + enable DMA channel squash */ + + struct { + __IOM unsigned int CHNL_LOCK : 8; /*!< [7..0] When set entire DMA block transfer is done, + before other DMA request is serviced */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } DMA_CHNL_LOCK_REG_b; + }; +} GPDMA_G_GLOBAL_Type; /*!< Size = 24 (0x18) */ + +/** + * @brief GPDMA_C_CHANNEL_CONFIG [CHANNEL_CONFIG] ([0..7]) + */ +typedef struct { + union { + __IOM unsigned int LINK_LIST_PTR_REGS; /*!< (@ 0x00000000) Link List Register + for channel 0 to 7 */ + + struct { + __IOM unsigned int LINK_LIST_PTR_REG_CHNL : 32; /*!< [31..0] This is the address of the + memory location from which + we get our next descriptor */ + } LINK_LIST_PTR_REGS_b; + }; + + union { + __IOM unsigned int SRC_ADDR_REG_CHNL; /*!< (@ 0x00000004) Source Address + Register for channel 0 to 7 */ + + struct { + __IOM unsigned int SRC_ADDR : 32; /*!< [31..0] This is the address of the memory location + from which we get our next descriptor */ + } SRC_ADDR_REG_CHNL_b; + }; + + union { + __IOM unsigned int DEST_ADDR_REG_CHNL; /*!< (@ 0x00000008) Source Address + Register for channel 0 to 7 */ + + struct { + __IOM unsigned int DEST_ADDR : 32; /*!< [31..0] This is the destination + address to whih the data is sent */ + } DEST_ADDR_REG_CHNL_b; + }; + + union { + __IOM unsigned int CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x0000000C) Channel Control + Register for channel 0 to 7 */ + + struct { + __IOM unsigned int DMA_BLK_SIZE : 12; /*!< [11..0] This is data to be transmitted. Loaded + at the beginning of the DMA transfer and + decremented at every dma transaction. */ + __IOM unsigned int TRNS_TYPE : 2; /*!< [13..12] DMA transfer type */ + __IOM unsigned int DMA_FLOW_CTRL : 2; /*!< [15..14] DMA flow control */ + __IOM unsigned int MSTR_IF_FETCH_SEL : 1; /*!< [16..16] This selects the MASTER IF from + which data to be fetched */ + __IOM unsigned int MSTR_IF_SEND_SEL : 1; /*!< [17..17] This selects the MASTER + IF from which data to be sent */ + __IOM unsigned int DEST_DATA_WIDTH : 2; /*!< [19..18] Data transfer to destination. */ + __IOM unsigned int SRC_DATA_WIDTH : 2; /*!< [21..20] Data transfer from source. */ + __IOM unsigned int SRC_ALIGN : 1; /*!< [22..22] Reserved.Value set to 0 We do not do any + singles. We just do burst, save first 3 bytes in to + residue buffer in one cycle, In the next cycle send + 4 bytes to fifo, save 3 bytes in to residue. This + continues on. */ + __IOM unsigned int LINK_LIST_ON : 1; /*!< [23..23] This mode is set, when we + do link listed operation */ + __IOM unsigned int LINK_LIST_MSTR_SEL : 1; /*!< [24..24] This mode is set, when we do + link listed operation */ + __IOM unsigned int SRC_ADDR_CONTIGUOUS : 1; /*!< [25..25] Indicates Address is + contiguous from previous */ + __IOM unsigned int DEST_ADDR_CONTIGUOUS : 1; /*!< [26..26] Indicates Address is + contiguous from previous */ + __IOM unsigned int RETRY_ON_ERROR : 1; /*!< [27..27] When this bit is set, if + we recieve HRESPERR, We will retry + the DMA for that channel. */ + __IOM unsigned int LINK_INTERRUPT : 1; /*!< [28..28] This bit is set in link list + descriptor.Hard ware will send an interrupt + when the DMA transfer is done for the + corresponding link list address */ + __IOM unsigned int SRC_FIFO_MODE : 1; /*!< [29..29] If set to 1; source address will not + be incremented(means fifo mode for source) */ + __IOM unsigned int DEST_FIFO_MODE : 1; /*!< [30..30] If set to 1; destination address + will not be incremented(means fifo mode for + destination) */ + __IM unsigned int RESERVED1 : 1; /*!< [31..31] Reserved1 */ + } CHANNEL_CTRL_REG_CHNL_b; + }; + + union { + __IOM unsigned int MISC_CHANNEL_CTRL_REG_CHNL; /*!< (@ 0x00000010) Misc Channel Control + Register for channel 0 */ + + struct { + __IOM unsigned int AHB_BURST_SIZE : 3; /*!< [2..0] Burst size */ + __IOM unsigned int DEST_DATA_BURST : 6; /*!< [8..3] Burst writes in beats to + destination.(000000-64 beats + .....111111-63 beats) */ + __IOM unsigned int SRC_DATA_BURST : 6; /*!< [14..9] Burst writes in beats from + source(000000-64 beats + .....111111-63 beats) */ + __IOM unsigned int DEST_CHNL_ID : 6; /*!< [20..15] This is the destination channel Id to + which the data is sent. Must be set up prior to + DMA_CHANNEL_ENABLE */ + __IOM + unsigned int SRC_CHNL_ID : 6; /*!< [26..21] This is the source channel Id, + from which the data is fetched. must be + set up prior to DMA_CHANNEL_ENABLE */ + __IOM unsigned int DMA_PROT : 3; /*!< [29..27] Protection level to go with the data. It + will be concatenated with 1 b1 as there will be no + opcode fetching and directly assign to hprot in AHB + interface */ + __IOM unsigned int MEM_FILL_ENABLE : 1; /*!< [30..30] Enable for memory + filling with either 1s or 0s. */ + __IOM unsigned int MEM_ONE_FILL : 1; /*!< [31..31] Select for memory filling + with either 1s or 0s. */ + } MISC_CHANNEL_CTRL_REG_CHNL_b; + }; + + union { + __IOM unsigned int FIFO_CONFIG_REGS; /*!< (@ 0x00000014) FIFO Configuration + Register for channel 1 */ + + struct { + __IOM unsigned int FIFO_STRT_ADDR : 6; /*!< [5..0] Starting row address of channel */ + __IOM unsigned int FIFO_SIZE : 6; /*!< [11..6] Channel size */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] Reserved1 */ + } FIFO_CONFIG_REGS_b; + }; + + union { + __IOM unsigned int PRIORITY_CHNL_REGS; /*!< (@ 0x00000018) Priority Register for + channel 0 to 7 */ + + struct { + __IOM unsigned int PRIORITY_CH : 2; /*!< [1..0] Set a value between 2 b00 to 2 b11. The + channel having highest number is the highest + priority channel. */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved1 */ + } PRIORITY_CHNL_REGS_b; + }; + __IM unsigned int RESERVED[57]; +} GPDMA_C_CHANNEL_CONFIG_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief TIMERS_MATCH_CTRL [MATCH_CTRL] ([0..3]) + */ +typedef struct { + union { + __IOM unsigned int MCUULP_TMR_MATCH; /*!< (@ 0x00000000) Timer Match Register */ + + struct { + __IOM unsigned int TMR_MATCH : 32; /*!< [31..0] This bits are used to program the lower + significant 16-bits of timer time out value in + millisecond or number of system clocks */ + } MCUULP_TMR_MATCH_b; + }; + + union { + __IOM unsigned int MCUULP_TMR_CNTRL; /*!< (@ 0x00000004) Timer Control Register */ + + struct { + __OM unsigned int TMR_START : 1; /*!< [0..0] This Bit are Used to start the timer timer + gets reset upon setting this bit */ + __OM unsigned int TMR_INTR_CLR : 1; /*!< [1..1] This Bit are Used to clear the + timer */ + __IOM unsigned int TMR_INTR_ENABLE : 1; /*!< [2..2] This Bit are Used to + enable the time out interrupt */ + __IOM unsigned int TMR_TYPE : 2; /*!< [4..3] This Bit are Used to select the + type of timer */ + __IOM unsigned int TMR_MODE : 1; /*!< [5..5] This Bit are Used to select the + mode working of timer */ + __OM unsigned int TMR_STOP : 1; /*!< [6..6] This Bit are Used to stop the timer */ + __IOM unsigned int COUNTER_UP : 1; /*!< [7..7] For reading/tracking counter in + up counting this bit has to be set */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MCUULP_TMR_CNTRL_b; + }; +} TIMERS_MATCH_CTRL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief I2S0_CHANNEL_CONFIG [CHANNEL_CONFIG] ([0..3]) + */ +typedef struct { + union { + union { + __IM unsigned int I2S_LRBR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + + struct { + __IM unsigned int LRBR : 24; /*!< [23..0] Data received serially from the + received channel input */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_LRBR_b; + }; + + union { + __OM unsigned int I2S_LTHR; /*!< (@ 0x00000000) Left Receive Buffer Register */ + + struct { + __OM unsigned int LTHR : 24; /*!< [23..0] The Left Stereo Data to be transmitted + serially from the Transmitted channel output */ + __OM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_LTHR_b; + }; + }; + + union { + union { + __IM unsigned int I2S_RRBR; /*!< (@ 0x00000004) Right Receive Buffer Register */ + + struct { + __IM unsigned int RRBR : 24; /*!< [23..0] The Right Stereo Data received serially from + the received channel input through this register */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_RRBR_b; + }; + + union { + __OM unsigned int I2S_RTHR; /*!< (@ 0x00000004) Right Transmit Holding Register */ + + struct { + __OM unsigned int RTHR : 24; /*!< [23..0] The Right Stereo Data to be transmitted + serially from the Transmit channel output written + through this register */ + __OM unsigned int RESERVED1 : 8; /*!< [31..24] Reserved for future use */ + } I2S_RTHR_b; + }; + }; + + union { + __IOM unsigned int I2S_RER; /*!< (@ 0x00000008) Receive Enable Register */ + + struct { + __IOM unsigned int RXCHEN : 1; /*!< [0..0] This Bit enables/disables a receive channel + independently of all other channels */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RER_b; + }; + + union { + __IOM unsigned int I2S_TER; /*!< (@ 0x0000000C) Transmit Enable Register */ + + struct { + __IOM unsigned int TXCHEN : 1; /*!< [0..0] This Bit enables/disables a transmit channel + independently of all other channels */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TER_b; + }; + + union { + __IOM unsigned int I2S_RCR; /*!< (@ 0x00000010) Receive Configuration Register */ + + struct { + __IOM unsigned int WLEN : 3; /*!< [2..0] This Bits are used to program the desired data + resolution of the receiver and enables LSB of the + incoming left or right word */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + } I2S_RCR_b; + }; + + union { + __IOM unsigned int I2S_TCR; /*!< (@ 0x00000014) Transmit Configuration Register */ + + struct { + __IOM unsigned int WLEN : 3; /*!< [2..0] This Bits are used to program the desired data + resolution of the transmitter and ensure that MSB of the + data is transmitted first. */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + } I2S_TCR_b; + }; + + union { + __IM unsigned int I2S_ISR; /*!< (@ 0x00000018) Interrupt Status Register */ + + struct { + __IM unsigned int RXDA : 1; /*!< [0..0] Receive Data Available */ + __IM unsigned int RXFO : 1; /*!< [1..1] Receive Data FIFO */ + __IM unsigned int RESERVED1 : 2; /*!< [3..2] Reserved for future use */ + __IM unsigned int TXFE : 1; /*!< [4..4] Transmit FIFO Empty */ + __IM unsigned int TXFO : 1; /*!< [5..5] Transmit FIFO */ + __IM unsigned int RESERVED2 : 26; /*!< [31..6] Reserved for future use */ + } I2S_ISR_b; + }; + + union { + __IOM unsigned int I2S_IMR; /*!< (@ 0x0000001C) Interrupt Mask Register */ + + struct { + __IOM unsigned int RXDAM : 1; /*!< [0..0] RX Data Available Mask Interrupt */ + __IOM unsigned int RXFOM : 1; /*!< [1..1] RX FIFO Overrun Mask Interrupt */ + __IOM unsigned int RESERVED1 : 2; /*!< [3..2] Reserved for future use */ + __IOM unsigned int TXFEM : 1; /*!< [4..4] TX FIFO Empty Interrupt */ + __IOM unsigned int TXFOM : 1; /*!< [5..5] TX FIFO Overrun Interrupt */ + __IOM unsigned int RESERVED2 : 26; /*!< [31..6] Reserved for future use */ + } I2S_IMR_b; + }; + + union { + __IM unsigned int I2S_ROR; /*!< (@ 0x00000020) Receive Overrun Register */ + + struct { + __IM unsigned int RXCHO : 1; /*!< [0..0] Read this bit to clear the RX FIFO + data overrun interrupt */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_ROR_b; + }; + + union { + __IM unsigned int I2S_TOR; /*!< (@ 0x00000024) Transmit Overrun Register */ + + struct { + __IM unsigned int TXCHO : 1; /*!< [0..0] Read this bit to clear the TX FIFO + data overrun interrupt */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TOR_b; + }; + + union { + __IOM unsigned int I2S_RFCR; /*!< (@ 0x00000028) Receive FIFO Configuration Register0 */ + + struct { + __IOM unsigned int RXCHDT : 4; /*!< [3..0] This bits program the trigger level in the RX + FIFO at which the data available interrupt is + generated */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } I2S_RFCR_b; + }; + + union { + __IOM unsigned int I2S_TXFCR; /*!< (@ 0x0000002C) Transmit FIFO Configuration Register */ + + struct { + __IOM + unsigned int TXCHET : 4; /*!< [3..0] This bits program the trigger level + in the TX FIFO at which the Empty Threshold + Reached interrupt is generated */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } I2S_TXFCR_b; + }; + + union { + __OM unsigned int I2S_RFF; /*!< (@ 0x00000030) Receive FIFO Flush */ + + struct { + __OM unsigned int RXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an + individual RX FIFO RX channel or block must be disable + prior to writing to this bit */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RFF_b; + }; + + union { + __OM unsigned int I2S_TFF; /*!< (@ 0x00000034) Transmit FIFO Flush */ + + struct { + __OM unsigned int TXCHFR : 1; /*!< [0..0] Writing a 1 to this register flushes an + individual TX FIFO TX channel or block must be disable + prior to writing to this bit */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TFF_b; + }; + __IM unsigned int RSVD0; /*!< (@ 0x00000038) none */ + __IM unsigned int RSVD1; /*!< (@ 0x0000003C) none */ +} I2S0_CHANNEL_CONFIG_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief EGPIO_PIN_CONFIG [PIN_CONFIG] ([0..79]) + */ +typedef struct { + union { + __IOM unsigned int GPIO_CONFIG_REG; /*!< (@ 0x00000000) GPIO Configuration Register */ + + struct { + __IOM unsigned int DIRECTION : 1; /*!< [0..0] Direction of the GPIO pin */ + __IOM unsigned int PORTMASK : 1; /*!< [1..1] Port mask value */ + __IOM unsigned int MODE : 4; /*!< [5..2] GPIO Pin Mode Used for GPIO Pin Muxing */ + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM unsigned int GROUP_INTERRUPT1_ENABLE : 1; /*!< [8..8] When set, the corresponding + GPIO is pin is selected for + group intr 1 generation */ + __IOM unsigned int GROUP_INTERRUPT1_POLARITY : 1; /*!< [9..9] Decides the active value of + the pin to be considered for group + interrupt 1 generation */ + __IOM unsigned int GROUP_INTERRUPT2_ENABLE : 1; /*!< [10..10] When set, the corresponding + GPIO is pin is selected + for group intr 2 generation */ + __IOM unsigned int GROUP_INTERRUPT2_POLARITY : 1; /*!< [11..11] Decides the active value + of the pin to be considered + for group interrupt 2 generation */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved3 */ + } GPIO_CONFIG_REG_b; + }; + + union { + __IOM unsigned int BIT_LOAD_REG; /*!< (@ 0x00000004) Bit Load */ + + struct { + __IOM unsigned int BIT_LOAD : 1; /*!< [0..0] Loads 0th bit on to the pin on write. And + reads the value on pin on read into 0th bit */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } BIT_LOAD_REG_b; + }; + + union { + __IOM unsigned int WORD_LOAD_REG; /*!< (@ 0x00000008) Word Load */ + + struct { + __IOM unsigned int WORD_LOAD : 16; /*!< [15..0] Loads 1 on the pin when any of the bit in + load value is 1. On read pass the bit status into + all bits. */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } WORD_LOAD_REG_b; + }; + __IM unsigned int RESERVED; +} EGPIO_PIN_CONFIG_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief EGPIO_PORT_CONFIG [PORT_CONFIG] ([0..5]) + */ +typedef struct { + union { + __IOM unsigned int PORT_LOAD_REG; /*!< (@ 0x00000000) Port Load */ + + struct { + __IOM unsigned int PORT_LOAD : 16; /*!< [15..0] Loads the value on to pin on write. And + reads the value of load register on read */ + __IM unsigned int RES : 16; /*!< [31..16] RES */ + } PORT_LOAD_REG_b; + }; + + union { + __OM unsigned int PORT_SET_REG; /*!< (@ 0x00000004) Port Set Register */ + + struct { + __OM unsigned int PORT_SET : 16; /*!< [15..0] Sets the pin when corresponding bit is + high. Writing zero has no effect. */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_SET_REG_b; + }; + + union { + __OM unsigned int PORT_CLEAR_REG; /*!< (@ 0x00000008) Port Clear Register */ + + struct { + __OM unsigned int PORT_CLEAR : 16; /*!< [15..0] Clears the pin when corresponding bit is + high. Writing zero has no effect. */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_CLEAR_REG_b; + }; + + union { + __OM unsigned int PORT_MASKED_LOAD_REG; /*!< (@ 0x0000000C) Port Masked Load Register */ + + struct { + __OM unsigned int PORT_MASKED_LOAD : 16; /*!< [15..0] Only loads into pins which are not + masked. On read, pass only status unmasked + pins */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_MASKED_LOAD_REG_b; + }; + + union { + __OM unsigned int PORT_TOGGLE_REG; /*!< (@ 0x00000010) Port Toggle Register */ + + struct { + __OM unsigned int PORT_TOGGLE : 16; /*!< [15..0] Toggles the pin when corresponding bit + is high. Writing zero has not effect. */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_TOGGLE_REG_b; + }; + + union { + __IM unsigned int PORT_READ_REG; /*!< (@ 0x00000014) Port Read Register */ + + struct { + __IM unsigned int PORT_READ : 16; /*!< [15..0] Reads the value on GPIO pins + irrespective of the pin mode. */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } PORT_READ_REG_b; + }; + __IM unsigned int RESERVED[2]; +} EGPIO_PORT_CONFIG_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief EGPIO_INTR [INTR] ([0..5]) + */ +typedef struct { + union { + __IOM unsigned int GPIO_INTR_CTRL; /*!< (@ 0x00000000) GPIO Interrupt Control Register */ + + struct { + __IOM unsigned int LEVEL_HIGH_ENABLE : 1; /*!< [0..0] enables interrupt generation when + pin level is 1 */ + __IOM unsigned int LEVEL_LOW_ENABLE : 1; /*!< [1..1] enables interrupt generation when + pin level is 0 */ + __IOM unsigned int RISE_EDGE_ENABLE : 1; /*!< [2..2] enables interrupt generation when + rising edge is detected on pin */ + __IOM unsigned int FALL_EDGE_ENABLE : 1; /*!< [3..3] enables interrupt generation when + Falling edge is detected on pin */ + __IOM unsigned int MASK : 1; /*!< [4..4] Masks the interrupt. Interrupt will still be + seen in status register when enabled */ + __IOM unsigned int RESERVED1 : 3; /*!< [7..5] Reserved1 */ + __IOM unsigned int PIN_NUMBER : 4; /*!< [11..8] GPIO Pin to be chosen for + interrupt generation */ + __IOM unsigned int PORT_NUMBER : 2; /*!< [13..12] GPIO Port to be chosen for + interrupt generation */ + __IOM unsigned int RESERVED2 : 18; /*!< [31..14] Reserved2 */ + } GPIO_INTR_CTRL_b; + }; + + union { + __IOM unsigned int GPIO_INTR_STATUS; /*!< (@ 0x00000004) GPIO Interrupt Status + Register */ + + struct { + __IOM unsigned int INTERRUPT_STATUS : 1; /*!< [0..0] Gets set when interrupt + is enabled and occurs. */ + __IOM unsigned int RISE_EDGE_STATUS : 1; /*!< [1..1] Gets set when rise edge + is enabled and occurs. */ + __IOM unsigned int FALL_EDGE_STATUS : 1; /*!< [2..2] Gets set when Fall edge + is enabled and occurs. */ + __OM unsigned int MASK_SET : 1; /*!< [3..3] Mask set */ + __OM unsigned int MASK_CLEAR : 1; /*!< [4..4] Mask Clear */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } GPIO_INTR_STATUS_b; + }; +} EGPIO_INTR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief EGPIO_GPIO_GRP_INTR [GPIO_GRP_INTR] ([0..3]) + */ +typedef struct { + union { + __IOM unsigned int GPIO_GRP_INTR_CTRL_REG; /*!< (@ 0x00000000) GPIO Interrupt 0 + Control Register */ + + struct { + __IOM unsigned int AND_OR : 1; /*!< [0..0] AND/OR */ + __IOM unsigned int LEVEL_EDGE : 1; /*!< [1..1] Level/Edge */ + __IOM unsigned int ENABLE_WAKEUP : 1; /*!< [2..2] For wakeup generation, actual pin + status has to be seen(before double ranking + point) */ + __IOM unsigned int ENABLE_INTERRUPT : 1; /*!< [3..3] Enable Interrupt */ + __IOM unsigned int MASK : 1; /*!< [4..4] Mask */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } GPIO_GRP_INTR_CTRL_REG_b; + }; + + union { + __IOM unsigned int GPIO_GRP_INTR_STS; /*!< (@ 0x00000004) GPIO Interrupt 0 + Status Register */ + + struct { + __IOM unsigned int INTERRUPT_STATUS : 1; /*!< [0..0] Interrupt status is available in + this bit when interrupt is enabled and + generated. When 1 is written, interrupt + gets cleared. */ + __IM unsigned int WAKEUP : 1; /*!< [1..1] Double ranked version of wakeup. + Gets set when wakeup is enabled and occurs. + When 1 is written it gets cleared */ + __IOM unsigned int RESERVED1 : 1; /*!< [2..2] Reserved1 */ + __IOM unsigned int MASK_SET : 1; /*!< [3..3] Gives zero on read */ + __IOM unsigned int MASK_CLEAR : 1; /*!< [4..4] Gives zero on read */ + __IOM unsigned int RESERVED2 : 27; /*!< [31..5] Reserved2 */ + } GPIO_GRP_INTR_STS_b; + }; +} EGPIO_GPIO_GRP_INTR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief MCU_RET_NPSS_GPIO_CNTRL [NPSS_GPIO_CNTRL] ([0..4]) + */ +typedef struct { + union { + __IOM unsigned int NPSS_GPIO_CTRLS; /*!< (@ 0x00000000) NPSS GPIO Control register */ + + struct { + __IOM unsigned int NPSS_GPIO_MODE : 3; /*!< [2..0] NPSS GPIO 0 mode select. */ + __IOM unsigned int NPSS_GPIO_REN : 1; /*!< [3..3] NPSS GPIO 0 Input Buffer + Enable. 1- Enable 0- Disable. */ + __IOM unsigned int NPSS_GPIO_OEN : 1; /*!< [4..4] NPSS GPIO 0 Output Buffer Enable. 1- + Input Direction 0- Output Direction. */ + __IOM unsigned int NPSS_GPIO_OUT : 1; /*!< [5..5] NPSS GPIO 0 Output value. */ + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM unsigned int NPSS_GPIO_POLARITY : 1; /*!< [8..8] NPSS GPIO 0 Polarity 1 + - When signal is High 0 - When + signal is Ligh. */ + __IOM unsigned int RESERVED2 : 7; /*!< [15..9] Reserved2 */ + __IOM unsigned int USE_ULPSS_PAD : 1; /*!< [16..16] Input from ULPSS GPIOs. */ + __IOM unsigned int RESERVED3 : 15; /*!< [31..17] Reserved3 */ + } NPSS_GPIO_CTRLS_b; + }; +} MCU_RET_NPSS_GPIO_CNTRL_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief ULPCLK_ULP_SOC_GPIO_MODE_REG [ULP_SOC_GPIO_MODE_REG] ([0..15]) + */ +typedef struct { + union { + __IOM unsigned int ULP_SOC_GPIO_MODE_REG; /*!< (@ 0x00000000) ulp soc gpio mode + register */ + + struct { + __IOM unsigned int ULP_SOC_GPIO_MODE_REG : 3; /*!< [2..0] mode bits for soc gpio. */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } ULP_SOC_GPIO_MODE_REG_b; + }; +} ULPCLK_ULP_SOC_GPIO_MODE_REG_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG [ADC_CH_BIT_MAP_CONFIG] + * ([0..15]) + */ +typedef struct { + union { + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_0; /*!< (@ 0x00000000) This is configuration + register0 to explain the bit map for ADC + channels */ + + struct { + __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + } ADC_CH_BIT_MAP_CONFIG_0_b; + }; + + union { + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_1; /*!< (@ 0x00000004) This is configuration + register1 to explain the bit map for ADC + channels */ + + struct { + __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + } ADC_CH_BIT_MAP_CONFIG_1_b; + }; + + union { + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_2; /*!< (@ 0x00000008) This is configuration + register2 to explain the bit map for ADC + channels */ + + struct { + __IOM unsigned int CHANNEL_BITMAP : 32; /*!< [31..0] ADC Channels bit map */ + } ADC_CH_BIT_MAP_CONFIG_2_b; + }; + + union { + __IOM unsigned int ADC_CH_BIT_MAP_CONFIG_3; /*!< (@ 0x0000000C) This is configuration + register3 to explain the bit map for ADC + channels */ + + struct { + __IOM unsigned int CHANNEL_BITMAP : 5; /*!< [4..0] ADC Channels bit map */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } ADC_CH_BIT_MAP_CONFIG_3_b; + }; +} AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type; /*!< Size = 16 (0x10) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== + */ +/* ================ Device Specific Peripheral + * Section ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== + */ +/* ================ I2C0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Inter Integrated Circuit(I2C) is programmable control bus that + provides support for the communications link between integrated circuits in a + system (I2C0) + */ + +typedef struct { /*!< (@ 0x44010000) I2C0 Structure */ + + union { + __IOM unsigned int IC_CON; /*!< (@ 0x00000000) This register can be written only + when the i2c is disabled, which corresponds to + IC_ENABLE[0] being set to 0. Writes at other times + have no effect. */ + + struct { + __IOM unsigned int MASTER_MODE : 1; /*!< [0..0] This bit controls whether the + I2C master is enabled. */ + __IOM unsigned int SPEED : 2; /*!< [2..1] These bits control at which speed + the I2C operates. Hardware protects against + illegal values being programmed by software. + */ + __IOM unsigned int IC_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, + this bit controls whether the + I2C responds to 7- or + 10-bit addresses. */ + __IM unsigned int IC_10BITADDR_MASTER_RD_ONLY : 1; /*!< [4..4] the function of this bit + is handled by bit 12 of IC_TAR + register, and becomes a + read-only copy called + IC_10BITADDR_MASTER_rd_onl + */ + __IOM unsigned int IC_RESTART_EN : 1; /*!< [5..5] Determines whether RESTART conditions + may be sent when acting as a master */ + __IOM unsigned int IC_SLAVE_DISABLE : 1; /*!< [6..6] This bit controls whether + I2C has its slave disabled */ + __IOM unsigned int STOP_DET_IFADDRESSED : 1; /*!< [7..7] The STOP DETECTION interrupt is + generated only when the transmitted + address matches the slave address of SAR + */ + __IOM unsigned int TX_EMPTY_CTRL : 1; /*!< [8..8] This bit controls the + generation of the TX EMPTY interrupt, + as described in the IC RAW INTR + STAT register. */ + __IM unsigned int RESERVED1 : 1; /*!< [9..9] reserved1 */ + __IOM unsigned int STOP_DET_IF_MASTER_ACTIVE : 1; /*!< [10..10] In Master mode. */ + __IOM unsigned int BUS_CLEAR_FEATURE_CTRL : 1; /*!< [11..11] In Master mode. */ + __IOM unsigned int RESERVED2 : 20; /*!< [31..12] reserved2 */ + } IC_CON_b; + }; + + union { + __IOM unsigned int IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register */ + + struct { + __IOM unsigned int IC_TAR : 10; /*!< [9..0] This is the target address for any + master transaction */ + __IOM unsigned int GC_OR_START : 1; /*!< [10..10] If bit 11 (SPECIAL) is set + to 1, then this bit indicates whether a + General Call or START byte command is + to be performed by the DW_apb_i2c */ + __IOM unsigned int SPECIAL : 1; /*!< [11..11] This bit indicates whether software + performs a General Call or START BYTE command */ + __IOM unsigned int IC_10BITADDR_MASTER : 1; /*!< [12..12] This bit controls + whether the i2c starts its + transfers in 7-or 10-bit + addressing mode when acting as + a master */ + __IOM unsigned int DEVICE_ID : 1; /*!< [13..13] If bit 11 (SPECIAL) is set to 1, then + this bit indicates whether a Device-ID of a + particular slave mentioned in IC_TAR[6:0] is to be + performed by the I2C Master */ + __IM unsigned int RESERVED1 : 18; /*!< [31..14] reserved1 */ + } IC_TAR_b; + }; + + union { + __IOM unsigned int IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */ + + struct { + __IOM unsigned int IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the + I2C is operating as a slave. For 7-bit addressing, + only IC_SAR[6:0] is used. */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ + } IC_SAR_b; + }; + + union { + __IOM unsigned int IC_HS_MADDR; /*!< (@ 0x0000000C) I2C High Speed Master Mode + Code Address Register */ + + struct { + __IOM unsigned int IC_HS_MAR : 3; /*!< [2..0] This bit field holds the value + of the I2C HS mode master code */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } IC_HS_MADDR_b; + }; + + union { + __IOM unsigned int IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and + Command Register */ + + struct { + __IOM unsigned int DAT : 8; /*!< [7..0] This register contains the data to be + transmitted or received on the I2C bus */ + __OM unsigned int CMD : 1; /*!< [8..8] This bit controls whether a read or a + write is performed */ + __OM unsigned int STOP : 1; /*!< [9..9] This bit controls whether a STOP is + issued after the byte is sent or received */ + __OM unsigned int RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is + issued before the byte is sent or received */ + __IM unsigned int FIRST_DATA_BYTE : 1; /*!< [11..11] Indicates the first data byte + received after the address phase for receive + transfer in Master receiver or Slave + receiver mode */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ + } IC_DATA_CMD_b; + }; + + union { + __IOM unsigned int IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock + SCL High Count Register */ + + struct { + __IOM unsigned int IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_SS_SCL_HCNT_b; + }; + + union { + __IOM unsigned int IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock + SCL Low Count Register */ + + struct { + __IOM unsigned int IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_SS_SCL_LCNT_b; + }; + + union { + __IOM unsigned int IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Speed I2C Clock SCL + High Count Register */ + + struct { + __IOM unsigned int IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_FS_SCL_HCNT_b; + }; + + union { + __IOM unsigned int IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Speed I2C Clock SCL + Low Count Register */ + + struct { + __IOM unsigned int IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_FS_SCL_LCNT_b; + }; + + union { + __IOM unsigned int IC_HS_SCL_HCNT; /*!< (@ 0x00000024) High Speed I2C Clock SCL + High Count Register */ + + struct { + __IOM unsigned int IC_HS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_HS_SCL_HCNT_b; + }; + + union { + __IOM unsigned int IC_HS_SCL_LCNT; /*!< (@ 0x00000028) High Speed I2C Clock SCL + Low Count Register */ + + struct { + __IOM unsigned int IC_HS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any + I2C bus transaction can take place to ensure + proper I/O timing */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } IC_HS_SCL_LCNT_b; + }; + + union { + __IM unsigned int IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register */ + + struct { + __IM unsigned int R_RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to + read the receive buffer + when it is empty by reading + from the IC_DATA_CMD register */ + __IM unsigned int R_RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely + filled to IC_RX_BUFFER_DEPTH and an additional byte + is received from an external I2C device */ + __IM unsigned int R_RX_FULL : 1; /*!< [2..2] Set when the receive buffer + reaches or goes above the RX_TL threshold + in the IC_RX_TL register. */ + __IM unsigned int R_TX_OVER : 1; /*!< [3..3] Set during transmit if the + transmit buffer is filled to + IC_TX_BUFFER_DEPTH and the processor + attempts to issue another I2C command by + writing to the IC_DATA_CMD register. */ + __IM unsigned int R_TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the transmit + buffer is at or below the threshold value set in + the IC_TX_TL register. */ + __IM unsigned int R_RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is + acting as a slave and another I2C master is + attempting to read data from DW_apb_i2c. */ + __IM unsigned int R_TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C + transmitter, is unable to complete the intended + actions on the contents of the transmit FIFO */ + __IM unsigned int R_RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a + slave-transmitter, this bit is set to 1 if the + master does not acknowledge a transmitted byte */ + __IM unsigned int R_ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and + stays set until it is cleared */ + __IM unsigned int R_STOP_DET : 1; /*!< [9..9] Indicates whether a STOP + condition has occurred on the I2C + interface regardless of whether DW_apb_i2c + is operating in slave or master mode. */ + __IM unsigned int R_START_DET : 1; /*!< [10..10] Indicates whether a START or + RESTART condition has occurred on the + I2C interface regardless of whether + DW_apb_i2c is operating in slave or + master mode. */ + __IM unsigned int R_GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is + received and it is acknowledged */ + __IM unsigned int R_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + has occurred on the I2C interface when + DW_apb_i2c is operating in slave mode and the + slave is the addressed slave */ + __IM unsigned int R_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + the bus and the Tx FIFO is empty. */ + __IM unsigned int M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + SCL Line is stuck at low for + the IC_SCL_STUCK_LOW_TIMOUT + number of ic_clk periods */ + __IM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ + } IC_INTR_STAT_b; + }; + + union { + __IOM unsigned int IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register */ + + struct { + __IOM unsigned int M_RX_UNDER : 1; /*!< [0..0] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM unsigned int M_RX_OVER : 1; /*!< [1..1] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM unsigned int M_RX_FULL : 1; /*!< [2..2] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM unsigned int M_TX_OVER : 1; /*!< [3..3] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register */ + __IOM unsigned int M_TX_EMPTY : 1; /*!< [4..4] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM unsigned int M_RD_REQ : 1; /*!< [5..5] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM unsigned int M_TX_ABRT : 1; /*!< [6..6] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM unsigned int M_RX_DONE : 1; /*!< [7..7] This bit mask their corresponding interrupt + status bits in the IC_INTR_STAT register. */ + __IOM unsigned int M_ACTIVITY : 1; /*!< [8..8] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM unsigned int M_STOP_DET : 1; /*!< [9..9] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM unsigned int M_START_DET : 1; /*!< [10..10] This bit mask their corresponding + interrupt status bits in the IC_INTR_STAT + register. */ + __IOM unsigned int M_GEN_CALL : 1; /*!< [11..11] This bit mask their + corresponding interrupt status bits in + the IC_INTR_STAT register. */ + __IOM unsigned int M_RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + has occurred on the I2C interface when + DW_apb_i2c is operating in slave mode and the + slave is the addressed slave */ + __IOM unsigned int M_MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + the bus and the Tx FIFO is empty. */ + __IOM unsigned int M_SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + SCL Line is stuck at low for + the IC_SCL_STUCK_LOW_TIMOUT + number of ic_clk periods */ + __IM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ + } IC_INTR_MASK_b; + }; + + union { + __IM unsigned int IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status + Register */ + + struct { + __IM unsigned int RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the + receive buffer when it is empty by reading from the + IC_DATA_CMD register */ + __IM unsigned int RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely + filled to IC_RX_BUFFER_DEPTH and an additional byte is + received from an external I2C device */ + __IM unsigned int RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches + or goes above the RX_TL threshold in the + IC_RX_TL register. */ + __IM unsigned int TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is + filled to IC_TX_BUFFER_DEPTH and the processor + attempts to issue another I2C command by writing to + the IC_DATA_CMD register. */ + __IM unsigned int TX_EMPTY : 1; /*!< [4..4] This bit is set to 1 when the + transmit buffer is at or below the + threshold value set in the IC_TX_TL + register. */ + __IM unsigned int RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting + as a slave and another I2C master is attempting to read + data from DW_apb_i2c. */ + __IM unsigned int TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C + transmitter, is unable to complete the intended + actions on the contents of the transmit FIFO */ + __IM unsigned int RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a + slave-transmitter, this bit is set to 1 if the master + does not acknowledge a transmitted byte */ + __IM unsigned int ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and + stays set until it is cleared */ + __IM unsigned int STOP_DET : 1; /*!< [9..9] Indicates whether a STOP condition has + occurred on the I2C interface regardless of whether + DW_apb_i2c is operating in slave or master mode. */ + __IM unsigned int START_DET : 1; /*!< [10..10] Indicates whether a START or RESTART + condition has occurred on the I2C interface + regardless of whether DW_apb_i2c is operating in + slave or master mode. */ + __IM unsigned int GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is + received and it is acknowledged */ + __IM unsigned int RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition + has occurred on the I2C interface when DW_apb_i2c + is operating in slave mode and the slave is the + addressed slave */ + __IM unsigned int MST_ON_HOLD : 1; /*!< [13..13] Indicates whether a master is holding + the bus and the Tx FIFO is empty. */ + __IM unsigned int SCL_STUCK_AT_LOW : 1; /*!< [14..14] Indicates whether the + SCL Line is stuck at low for the + IC_SCL_STUCK_LOW_TIMOUT number of + ic_clk periods */ + __IM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ + } IC_RAW_INTR_STAT_b; + }; + + union { + __IOM unsigned int IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + + struct { + __IOM unsigned int RX_TL : 8; /*!< [7..0] Receive FIFO Threshold Level */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_RX_TL_b; + }; + + union { + __IOM unsigned int IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + + struct { + __IOM unsigned int TX_TL : 8; /*!< [7..0] Transmit FIFO Threshold Level */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_TX_TL_b; + }; + + union { + __IM unsigned int IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual + Interrupt Register */ + + struct { + __IM unsigned int CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined + interrupt, all individual interrupts, and the + IC_TXABRT_SOURCE register */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_INTR_b; + }; + + union { + __IM unsigned int IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt + Register */ + + struct { + __IM unsigned int CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear + the RX_UNDER interrupt (bit 0) of the + IC_RAW_INTR_STAT register. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RX_UNDER_b; + }; + + union { + __IM unsigned int IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt + Register */ + + struct { + __IM unsigned int CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the + RX_OVER interrupt (bit 1) of the + IC_RAW_INTR_STAT register */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RX_OVER_b; + }; + + union { + __IM unsigned int IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt + Register */ + + struct { + __IM unsigned int CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the + TX_OVER interrupt (bit 3) of the + IC_RAW_INTR_STAT register. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_TX_OVER_b; + }; + + union { + __IM unsigned int IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + + struct { + __IM unsigned int CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the + RD_REQ interrupt (bit 5) of the + IC_RAW_INTR_STAT register. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RD_REQ_b; + }; + + union { + __IM unsigned int IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt + Register */ + + struct { + __IM unsigned int CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT + interrupt (bit 6) of the C_RAW_INTR_STAT register, + and the IC_TX_ABRT_SOURCE register */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_TX_ABRT_b; + }; + + union { + __IM unsigned int IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt + Register */ + + struct { + __IM unsigned int CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the + RX_DONE interrupt (bit 7) of the + IC_RAW_INTR_STAT register */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RX_DONE_b; + }; + + union { + __IM unsigned int IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt + Register */ + + struct { + __IM unsigned int CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears + the ACTIVITY interrupt if the I2C is + not active any more */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_ACTIVITY_b; + }; + + union { + __IM unsigned int IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt + Register */ + + struct { + __IM unsigned int CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear + the STOP_DET interrupt (bit 9) of the + IC_RAW_INTR_STAT register. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_STOP_DET_b; + }; + + union { + __IM unsigned int IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET + Interrupt Register */ + + struct { + __IM unsigned int CLR_START_DET : 1; /*!< [0..0] Read this register to clear + the START_DET interrupt (bit 10) of + the IC_RAW_INTR_STAT register */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_START_DET_b; + }; + + union { + __IM unsigned int IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt + Register */ + + struct { + __IM unsigned int CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear + the GEN_CALL interrupt (bit 11) of + IC_RAW_INTR_STAT register */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_GEN_CALL_b; + }; + + union { + __IOM unsigned int IC_ENABLE; /*!< (@ 0x0000006C) Clear GEN_CALL Interrupt Register */ + + struct { + __IOM unsigned int EN : 1; /*!< [0..0] Controls whether the DW_apb_i2c is enabled */ + __IOM unsigned int ABORT : 1; /*!< [1..1] When set, the controller initiates + the transfer abort */ + __IOM unsigned int TX_CMD_BLOCK : 1; /*!< [2..2] none */ + __IOM unsigned int SDA_STUCK_RECOVERY_ENABLE : 1; /*!< [3..3] SDA STUCK + RECOVERY ENABLE */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_ENABLE_b; + }; + + union { + __IM unsigned int IC_STATUS; /*!< (@ 0x00000070) I2C Status Register */ + + struct { + __IM unsigned int ACTIVITY : 1; /*!< [0..0] I2C Activity Status */ + __IM unsigned int TFNF : 1; /*!< [1..1] Transmit FIFO Not Full */ + __IM unsigned int TFE : 1; /*!< [2..2] Transmit FIFO Completely Empty */ + __IM unsigned int RFNE : 1; /*!< [3..3] Receive FIFO Not Empty */ + __IM unsigned int RFF : 1; /*!< [4..4] Receive FIFO Completely Full */ + __IM unsigned int MST_ACTIVITY : 1; /*!< [5..5] Master FSM Activity Status */ + __IM unsigned int SLV_ACTIVITY : 1; /*!< [6..6] Slave FSM Activity Status */ + __IM unsigned int MST_HOLD_TX_FIFO_EMPTY : 1; /*!< [7..7] The I2C master stalls the + write transfer when Tx FIFO is empty, + and the the last byte does not have + the Stop bit set. */ + __IM unsigned int MST_HOLD_RX_FIFO_FULL : 1; /*!< [8..8] This bit indicates the BUS Hold + in Master mode due to Rx FIFO is Full + and additional byte has been received. + */ + __IM unsigned int SLV_HOLD_TX_FIFO_EMPTY : 1; /*!< [9..9] This bit indicates the BUS + Hold in Slave mode for the + Read request when the Tx FIFO is + empty. */ + __IM unsigned int SLV_HOLD_RX_FIFO_FULL : 1; /*!< [10..10] This bit indicates the BUS + Hold in Slave mode due to the Rx FIFO + being Full and an additional byte being + received. */ + __IM unsigned int SDA_STUCK_NOT_RECOVERED : 1; /*!< [11..11] This bit indicates that an + SDA stuck at low is not recovered + after the recovery mechanism. */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ + } IC_STATUS_b; + }; + + union { + __IM unsigned int IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register */ + + struct { + __IM unsigned int TXFLR : 4; /*!< [3..0] Contains the number of valid data + entries in the transmit FIFO. */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_TXFLR_b; + }; + + union { + __IM unsigned int IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register */ + + struct { + __IM unsigned int RXFLR : 4; /*!< [3..0] Receive FIFO Level. Contains the number of + valid data entries in the receive FIFO */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_RXFLR_b; + }; + + union { + __IOM unsigned int IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register */ + + struct { + __IOM unsigned int IC_SDA_TX_HOLD : 16; /*!< [15..0] Sets the required SDA hold time in + units of ic_clk period,when I2C acts as a + transmitter. */ + __IOM unsigned int IC_SDA_RX_HOLD : 8; /*!< [23..16] Sets the required SDA hold time in + units of ic_clk period,when I2C acts as a + receiver. */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ + } IC_SDA_HOLD_b; + }; + + union { + __IM unsigned int IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort + Source Register */ + + struct { + __IM unsigned int ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] 1: Master is in 7-bit addressing + mode and the address sent was not + acknowledged by any slave */ + __IM unsigned int ABRT_10ADDR1_NOACK : 1; /*!< [1..1] 1: Master is in 10-bit + address mode and the first 10-bit + address byte was not + acknowledged by any slave */ + __IM unsigned int ABRT_10ADDR2_NOACK : 1; /*!< [2..2] 1: Master is in 10-bit address + mode and the second address byte of the + 10-bit address was not acknowledged by any + slave */ + __IM unsigned int ABRT_TXDATA_NOACK : 1; /*!< [3..3] 1: This is a master-mode only bit. + Master has received an acknowledgement for + the address, but when it sent data byte(s) + following the address, it did not receive an + acknowledge from the remote slave(s) */ + __IM unsigned int ABRT_GCALL_NOACK : 1; /*!< [4..4] 1: DW_apb_i2c in master mode sent a + General Call and no slave on the bus + acknowledged the General Call */ + __IM unsigned int ABRT_GCALL_READ : 1; /*!< [5..5] 1: DW_apb_i2c in master mode sent a + General Call but the user programmed the byte + following the General Call + to be a read from the bus (IC_DATA_CMD[9] + is set to 1) */ + __IM unsigned int ABRT_HS_ACKDET : 1; /*!< [6..6] 1: Master is in High Speed + mode and the High Speed Master code + was acknowledged */ + __IM unsigned int ABRT_SBYTE_ACKDET : 1; /*!< [7..7] 1: Master has sent a START Byte and + the START Byte was acknowledged (wrong + behavior) */ + __IM unsigned int ABRT_HS_NORSTRT : 1; /*!< [8..8] 1: The restart is disabled + (IC_RESTART_EN bit (IC_CON[5]) = 0) and the + user is trying to use the master to transfer + data in High Speed mode */ + __IM unsigned int ABRT_SBYTE_NORSTRT : 1; /*!< [9..9] 1: The restart is disabled + (IC_RESTART_EN bit (IC_CON[5]) + = 0) and the user is trying to send a + START Byte */ + __IM unsigned int ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] 1: The restart is disabled + (IC_RESTART_EN bit (IC_CON[5]) = 0) and + the master sends a read command in 10-bit + addressing mode */ + __IM unsigned int ABRT_MASTER_DIS : 1; /*!< [11..11] 1: User tries to initiate a Master + operation with the Master mode disabled */ + __IM unsigned int ARB_LOST : 1; /*!< [12..12] 1: Master has lost arbitration, or if + IC_TX_ABRT_SOURCE[14] is also set, then the slave + transmitter has lost arbitration */ + __IM unsigned int ABRT_SLVFLUSH_TXFIFO : 1; /*!< [13..13] 1: Slave has received a + read command and some data exists in + the TX FIFO so the slave issues a + TX_ABRT interrupt to flush old data + in TX FIFO */ + __IM unsigned int ABRT_SLV_ARBLOST : 1; /*!< [14..14] 1: Slave lost the bus + while transmitting data to a remote + master. IC_TX_ABRT_SOURCE[12] is + set at the same time */ + __IM unsigned int ABRT_SLVRD_INTX : 1; /*!< [15..15] 1: When the processor side responds + to a slave mode request for data to be + transmitted to a remote master and + user writes a 1 in CMD (bit 8) of + IC_DATA_CMD register */ + __IM unsigned int ABRT_USER_ABRT : 1; /*!< [16..16] This is a master-mode-only bit. + Master has detected the transfer abort + (IC_ENABLE[1]). */ + __IM unsigned int ABRT_SDA_STUCK_AT_LOW : 1; /*!< [17..17] Master detects the + SDA is Stuck at low for the + IC_SDA_STUCK_AT_LOW_TI EOUT + value of ic_clks */ + __IM unsigned int ABRT_DEVICE_NOACK : 1; /*!< [18..18] Master initiates the DEVICE_ID + transfer and the device ID sent is not + acknowledged by any slave */ + __IM unsigned int ABRT_DEVICE_SLVADDR_NOACK : 1; /*!< [19..19] Master is initiating the + DEVICE_ID transfer and the slave + address sent was not acknowledged by + any slave */ + __IM unsigned int ABRT_DEVICE_WRITE : 1; /*!< [20..20] Master is initiating the + DEVICE_ID transfer and the + Tx- FIFO consists of write commands. */ + __IM unsigned int RESERVED1 : 2; /*!< [22..21] reserved1 */ + __IM unsigned int TX_FLUSH_CNT : 9; /*!< [31..23] This field indicates the number of Tx + FIFO data commands that are flushed due to + TX_ABRT interrupt */ + } IC_TX_ABRT_SOURCE_b; + }; + + union { + __IOM unsigned int IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave + Data NACK Register */ + + struct { + __IOM unsigned int NACK : 1; /*!< [0..0] Generate NACK. This NACK generation only occurs + when DW_apb_i2c is a slave receiver. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_SLV_DATA_NACK_ONLY_b; + }; + + union { + __IOM unsigned int IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register */ + + struct { + __IOM unsigned int RDMAE : 1; /*!< [0..0] Receive DMA Enable */ + __IOM unsigned int TDMAE : 1; /*!< [1..1] Transmit DMA Enable.This bit enables/disables + the transmit FIFO DMA channel */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ + } IC_DMA_CR_b; + }; + + union { + __IOM unsigned int IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + + struct { + __IOM unsigned int DMATDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the transmit logic */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_DMA_TDLR_b; + }; + + union { + __IOM unsigned int IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + + struct { + __IOM unsigned int DMARDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the receive logic */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } IC_DMA_RDLR_b; + }; + + union { + __IOM unsigned int IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register */ + + struct { + __IOM unsigned int SDA_SETUP : 8; /*!< [7..0] This register controls the amount of time + delay (in terms of number of ic_clk clock periods) + */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_SDA_SETUP_b; + }; + + union { + __IOM unsigned int IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call + Register */ + + struct { + __IOM unsigned int ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_ACK_GENERAL_CALL_b; + }; + + union { + __IM unsigned int IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register */ + + struct { + __IM unsigned int IC_EN : 1; /*!< [0..0] This bit always reflects the value + driven on the output port ic_en. */ + __IM unsigned int SLV_DISABLED_WHILE_BUSY : 1; /*!< [1..1] This bit indicates if a + potential or active Slave operation + has been aborted due to + the setting of the IC_ENABLE register + from 1 to 0 */ + __IM unsigned int SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } IC_ENABLE_STATUS_b; + }; + + union { + __IOM unsigned int IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS and FS Spike + Suppression Limit Register */ + + struct { + __IOM unsigned int IC_FS_SPKLEN : 8; /*!< [7..0] This register sets the + duration, measured in ic_clk cycles, + of the longest spike in the + SCL or SDA lines that are filtered + out by the spike + suppression logic */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_FS_SPKLEN_b; + }; + + union { + __IOM unsigned int IC_HS_SPKLEN; /*!< (@ 0x000000A4) I2C HS Spike Suppression + Limit Register */ + + struct { + __IOM unsigned int IC_HS_SPKLEN : 8; /*!< [7..0] This register sets the + duration, measured in ic_clk cycles, + of the longest spike in the + SCL or SDA lines that are filtered + out by the spike + suppression logic */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } IC_HS_SPKLEN_b; + }; + + union { + __IM unsigned int IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET + Interrupt Register */ + + struct { + __IM unsigned int CLR_RESTART_DET : 1; /*!< [0..0] Read this register to clear + the RESTART_DET interrupt (bit 12) + of the IC_RAW_INTR_STAT registe */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_RESTART_DET_b; + }; + + union { + __IOM unsigned int IC_SCL_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000AC) I2C SCL + Stuck at Low Timeout */ + + struct { + __IOM unsigned int IC_SCL_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Generates the interrupt to + indicate SCL stuck at low if it + detects the SCL stuck at low for the + IC_SCL_STUCK_LOW_TIMEOUT in units of + ic_clk period */ + } IC_SCL_STUCK_AT_LOW_TIMEOUT_b; + }; + + union { + __IOM unsigned int IC_SDA_STUCK_AT_LOW_TIMEOUT; /*!< (@ 0x000000B0) I2C SDA + Stuck at Low Timeout */ + + struct { + __IOM unsigned int IC_SDA_STUCK_LOW_TIMEOUT : 32; /*!< [31..0] Initiates the recovery of + SDA line , if it detects the SDA stuck + at low for the + IC_SDA_STUCK_LOW_TIMEOUT in units of + ic_clk period. */ + } IC_SDA_STUCK_AT_LOW_TIMEOUT_b; + }; + + union { + __IM unsigned int IC_CLR_SCL_STUCK_DET; /*!< (@ 0x000000B4) Clear SCL Stuck at + Low Detect Interrupt Register */ + + struct { + __IM unsigned int CLR_SCL_STUCK : 1; /*!< [0..0] Read this register to clear + the SCL_STUCK_DET interrupt */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } IC_CLR_SCL_STUCK_DET_b; + }; + + union { + __IM unsigned int IC_DEVICE_ID; /*!< (@ 0x000000B8) I2C Device ID */ + + struct { + __IM unsigned int DEVICE_ID : 24; /*!< [23..0] Contains the Device-ID of the component + assigned through the configuration parameter */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ + } IC_DEVICE_ID_b; + }; + + union { + __IOM unsigned int IC_SMBUS_CLOCK_LOW_SEXT; /*!< (@ 0x000000BC) SMBUS Slave Clock Extend + Timeout Register */ + + struct { + __IOM unsigned int SMBUS_CLK_LOW_SEXT_TIMEOUT : 32; /*!< [31..0] The values in this + register are in units of ic_clk + period. */ + } IC_SMBUS_CLOCK_LOW_SEXT_b; + }; + + union { + __IOM unsigned int IC_SMBUS_CLOCK_LOW_MEXT; /*!< (@ 0x000000C0) SMBUS Master extend clock + Timeout Register */ + + struct { + __IOM unsigned int SMBUS_CLK_LOW_MEXT_TIMEOUT : 32; /*!< [31..0] The values in this + register are in units of ic_clk + period.. */ + } IC_SMBUS_CLOCK_LOW_MEXT_b; + }; + + union { + __IOM unsigned int IC_SMBUS_THIGH_MAX_IDLE_COUNT; /*!< (@ 0x000000C4) SMBus Thigh MAX + Bus-Idle count Register */ + + struct { + __IOM unsigned int SMBUS_THIGH_MAX_BUS_IDLE_CNT : 16; /*!< [15..0] The values in this + register are in units of ic_clk + period. */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } IC_SMBUS_THIGH_MAX_IDLE_COUNT_b; + }; + + union { + __IOM unsigned int IC_SMBUS_INTR_STAT; /*!< (@ 0x000000C8) SMBUS Interrupt + Status Register */ + + struct { + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1 */ + } IC_SMBUS_INTR_STAT_b; + }; + + union { + __IOM unsigned int IC_SMBUS_INTR_MASK; /*!< (@ 0x000000CC) Interrupt Mask Register */ + + struct { + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1 */ + } IC_SMBUS_INTR_MASK_b; + }; + + union { + __IOM unsigned int IC_SMBUS_INTR_RAW_STATUS; /*!< (@ 0x000000D0) SMBUS Raw + Interrupt Status Register */ + + struct { + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1. */ + } IC_SMBUS_INTR_RAW_STATUS_b; + }; + + union { + __IOM unsigned int IC_CLR_SMBUS_INTR; /*!< (@ 0x000000D4) Clear SMBUS Interrupt + Register */ + + struct { + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] RESERVED1 */ + } IC_CLR_SMBUS_INTR_b; + }; + + union { + __IOM unsigned int IC_OPTIONAL_SAR; /*!< (@ 0x000000D8) Optional Slave Address + Register */ + + struct { + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved1. */ + } IC_OPTIONAL_SAR_b; + }; + + union { + __IOM unsigned int IC_SMBUS_UDID_LSB; /*!< (@ 0x000000DC) SMBUS ARP UDID LSB Register */ + + struct { + __IOM unsigned int IC_SMBUS_ARP_UDID_LSB : 32; /*!< [31..0] This field is used to store + the LSB 32 bit value of slave unique + device identifier used in Address + Resolution Protocol. */ + } IC_SMBUS_UDID_LSB_b; + }; + __IM unsigned int RESERVED[5]; + + union { + __IM unsigned int IC_COMP_PARAM_1; /*!< (@ 0x000000F4) I2C HS Spike Suppression + Limit Register */ + + struct { + __IM unsigned int CLR_RESTART_DET : 2; /*!< [1..0] Read this register to clear the + RESTART_DET interrupt (bit 12) of the + IC_RAW_INTR_STAT register */ + __IM unsigned int MAX_SPEED_MODE : 2; /*!< [3..2] Maximum Speed Mode */ + __IM unsigned int HC_COUNT_VALUES : 1; /*!< [4..4] Hard Code the count values */ + __IM unsigned int INTR_IO : 1; /*!< [5..5] Single Interrupt Output port */ + __IM unsigned int HAS_DMA : 1; /*!< [6..6] DMA Handshake Interface signal */ + __IM unsigned int ADD_ENCODED_PARAMS : 1; /*!< [7..7] Add Encoded Parameters */ + __IM unsigned int RX_BUFFER_DEPTH : 8; /*!< [15..8] Depth of receive buffer;the buffer + is 8 bits wide;2 to 256 */ + __IM unsigned int TX_BUFFER_DEPTH : 8; /*!< [23..16] Depth of Transmit buffer;the buffer + is 8 bits wide;2 to 256 */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ + } IC_COMP_PARAM_1_b; + }; + + union { + __IM unsigned int IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */ + + struct { + __IM unsigned int IC_COMP_VERSION : 32; /*!< [31..0] Signifies the component + version */ + } IC_COMP_VERSION_b; + }; + + union { + __IM unsigned int IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */ + + struct { + __IM unsigned int IC_COMP_TYPE : 32; /*!< [31..0] Design ware Component Type + number = 0x44_57_01_40 */ + } IC_COMP_TYPE_b; + }; +} I2C0_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== + */ +/* ================ MCPWM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The Motor Control PWM (MCPWM) controller is used to generate a + periodic pulse waveform, which is useful in motor control and power control + applications (MCPWM) + */ + +typedef struct { /*!< (@ 0x47070000) MCPWM Structure */ + + union { + __IM unsigned int PWM_INTR_STS; /*!< (@ 0x00000000) PWM Interrupt Status Register */ + + struct { + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH0 : 1; /*!< [0..0] This time base + interrupt for 0th channel + without considering + postscaler */ + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH0 : 1; /*!< [1..1] This time base interrupt + for 0th channel, which considers + postscaler value */ + __IM unsigned int FLT_A_INTR : 1; /*!< [2..2] When the fault A pin is driven + low, this interrupt is raised. */ + __IM unsigned int FLT_B_INTR : 1; /*!< [3..3] When the fault B pin is driven + low, this interrupt is raised. */ + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH1 : 1; /*!< [4..4] This time base + interrupt for 1st channel + without considering + postscaler value */ + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH1 : 1; /*!< [5..5] This time base interrupt + for 1st channel, which considers + postscaler value. */ + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH2 : 1; /*!< [6..6] This time base + interrupt for 2nd channel + without considering + postscaler value. */ + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH2 : 1; /*!< [7..7] This time base interrupt + for 2nd channel, which considers + postscaler value */ + __IM unsigned int RISE_PWM_TIME_PERIOD_MATCH_INTR_CH3 : 1; /*!< [8..8] This time base + interrupt for 3rd channel + without considering + postscaler value. */ + __IM unsigned int PWM_TIME_PRD_MATCH_INTR_CH3 : 1; /*!< [9..9] This time base interrupt + for 3rd channel, which considers + postscaler value. */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ + } PWM_INTR_STS_b; + }; + + union { + __IOM unsigned int PWM_INTR_UNMASK; /*!< (@ 0x00000004) PWM Interrupt Unmask Register */ + + struct { + __IOM unsigned int PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Unmask */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_INTR_UNMASK_b; + }; + + union { + __IOM unsigned int PWM_INTR_MASK; /*!< (@ 0x00000008) PWM Interrupt mask Register */ + + struct { + __IOM unsigned int PWM_INTR_UNMASK : 16; /*!< [15..0] Interrupt Mask */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_INTR_MASK_b; + }; + + union { + __IOM unsigned int PWM_INTR_ACK; /*!< (@ 0x0000000C) PWM Interrupt + Acknowledgement Register */ + + struct { + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : 1; /*!< [0..0] pwm time + period match + interrupt for 0th + channel will be + cleared. */ + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH0_ACK : 1; /*!< [1..1] pwm time period match + interrupt for 0th channel will + be cleared */ + __OM unsigned int FLT_A_INTR_ACK : 1; /*!< [2..2] pwm fault A interrupt will + be cleared. */ + __OM unsigned int FLT_B_INTR_ACK : 1; /*!< [3..3] pwm fault B interrupt will + be cleared. */ + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : 1; /*!< [4..4] pwm time + period match + interrupt for 1st + channel will be + cleared */ + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH1_ACK : 1; /*!< [5..5] pwm time period match + interrupt for 1st channel will + be cleared. */ + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : 1; /*!< [6..6] pwm time + period match + interrupt for 2nd + channel will be + cleared. */ + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH2_ACK : 1; /*!< [7..7] pwm time period match + interrupt for 2nd channel will + be cleared. */ + __OM unsigned int RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : 1; /*!< [8..8] pwm time + period match + interrupt for 3rd + channel will be + cleared. */ + __OM unsigned int PWM_TIME_PRD_MATCH_INTR_CH3_ACK : 1; /*!< [9..9] pwm time period match + interrupt for 3rd channel will + be cleared. */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ + } PWM_INTR_ACK_b; + }; + __IM unsigned int RESERVED[6]; + + union { + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH0; /*!< (@ 0x00000028) Base timer + period register of channel 0 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH0 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 0 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH0_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH0; /*!< (@ 0x0000002C) Base time + counter initial value + register for channel 0 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH0 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 0 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH0_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH0; /*!< (@ 0x00000030) Base time period config + parameter's register for channel0 */ + + struct { + __IOM unsigned int TMR_OPEARATING_MODE_CH0 : 3; /*!< [2..0] Base timer operating mode for + channel0 */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH0 : 3; /*!< [6..4] Base timer input + clock pre scale select value + for channel0. */ + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH0 : 4; /*!< [11..8] Time base output + post scale bits for + channel0 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH0_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH0; /*!< (@ 0x00000034) Base time counter initial + value register for channel 0 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH0 : 1; /*!< [1..1] Base timer enable for + channnel0 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH0_b; + }; + + union { + __IM unsigned int PWM_TIME_PRD_STS_REG_CH0; /*!< (@ 0x00000038) Base time period + status register for channel0 */ + + struct { + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH0 : 1; /*!< [0..0] Time period counter + direction status for channel0 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_STS_REG_CH0_b; + }; + + union { + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH0; /*!< (@ 0x0000003C) Base Time + period counter current value + register for channel0 */ + + struct { + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH0 : 16; /*!< [15..0] Time period counter + current value for channel0 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH0_b; + }; + __IM unsigned int RESERVED1[4]; + + union { + __IOM unsigned int PWM_DUTYCYCLE_CTRL_SET_REG; /*!< (@ 0x00000050) Duty cycle + Control Set Register */ + + struct { + __IOM unsigned int IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty + cycle immediately */ + __IOM unsigned int DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle register updation + disable. There is a separate + bit for each channel */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DUTYCYCLE_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int PWM_DUTYCYCLE_CTRL_RESET_REG; /*!< (@ 0x00000054) Duty cycle + Control Reset Register */ + + struct { + __IOM unsigned int IMDT_DUTYCYCLE_UPDATE_EN : 4; /*!< [3..0] Enable to update the duty + cycle immediately */ + __IOM unsigned int DUTYCYCLE_UPDATE_DISABLE : 4; /*!< [7..4] Duty cycle + register updation disable. + There is a separate bit + for each channel. */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DUTYCYCLE_CTRL_RESET_REG_b; + }; + + union { + __IOM unsigned int PWM_DUTYCYCLE_REG_WR_VALUE[4]; /*!< (@ 0x00000058) Duty cycle Value + Register for Channel0 to channel3 */ + + struct { + __IOM unsigned int PWM_DUTYCYCLE_REG_WR_VALUE_CH : 16; /*!< [15..0] Duty cycle value for + channel0 to channel3 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_DUTYCYCLE_REG_WR_VALUE_b[4]; + }; + __IM unsigned int RESERVED2[4]; + + union { + __IOM unsigned int PWM_DEADTIME_CTRL_SET_REG; /*!< (@ 0x00000078) Dead time + Control Set Register */ + + struct { + __IOM unsigned int DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM + going active */ + __IOM unsigned int DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for + PWM going inactive */ + __IOM unsigned int DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft + reset for each channel. */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ + } PWM_DEADTIME_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int PWM_DEADTIME_CTRL_RESET_REG; /*!< (@ 0x0000007C) Dead time + Control Reset Register */ + + struct { + __IOM unsigned int DEADTIME_SELECT_ACTIVE : 4; /*!< [3..0] Dead time select bits for PWM + going active */ + __IOM unsigned int DEADTIME_SELECT_INACTIVE : 4; /*!< [7..4] Dead time select bits for + PWM going inactive */ + __IOM unsigned int DEADTIME_DISABLE_FRM_REG : 4; /*!< [11..8] Dead time counter soft + reset for each channel. */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] reserved1 */ + } PWM_DEADTIME_CTRL_RESET_REG_b; + }; + + union { + __IOM unsigned int PWM_DEADTIME_PRESCALE_SELECT_A; /*!< (@ 0x00000080) Dead time Prescale + Select Register for A */ + + struct { + __IOM unsigned int DEADTIME_PRESCALE_SELECT_A : 8; /*!< [7..0] Dead time prescale + selection bits for unit A. */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DEADTIME_PRESCALE_SELECT_A_b; + }; + + union { + __IOM unsigned int PWM_DEADTIME_PRESCALE_SELECT_B; /*!< (@ 0x00000084) Dead time Prescale + Select Register for B */ + + struct { + __IOM unsigned int DEADTIME_PRESCALE_SELECT_B : 8; /*!< [7..0] Dead time prescale + selection bits for unit B */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_DEADTIME_PRESCALE_SELECT_B_b; + }; + __IOM MCPWM_PWM_DEADTIME_Type PWM_DEADTIME[4]; /*!< (@ 0x00000088) [0..3] */ + __IM unsigned int RESERVED3[8]; + + union { + __IOM unsigned int PWM_OP_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000C8) output override + control set register */ + + struct { + __IOM unsigned int OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm + time period depending on operating mode */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_OP_OVERRIDE_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int PWM_OP_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000CC) output override + control reset register */ + + struct { + __IOM unsigned int OP_OVERRIDE_SYNC : 1; /*!< [0..0] Output override is synced with pwm + time period depending on operating mode */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_OP_OVERRIDE_CTRL_RESET_REG_b; + }; + + union { + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_SET_REG; /*!< (@ 0x000000D0) output override + enable set register */ + + struct { + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over + ride enable */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_ENABLE_SET_REG_b; + }; + + union { + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_RESET_REG; /*!< (@ 0x000000D4) output override + enable reset register */ + + struct { + __IOM unsigned int PWM_OP_OVERRIDE_ENABLE_REG : 8; /*!< [7..0] Pwm output over + ride enable */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_ENABLE_RESET_REG_b; + }; + + union { + __IOM unsigned int PWM_OP_OVERRIDE_VALUE_SET_REG; /*!< (@ 0x000000D8) output override value + set register */ + + struct { + __IOM unsigned int OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_VALUE_SET_REG_b; + }; + + union { + __IOM unsigned int PWM_OP_OVERRIDE_VALUE_RESET_REG; /*!< (@ 0x000000DC) output override + enable reset register */ + + struct { + __IOM unsigned int OP_OVERRIDE_VALUE : 8; /*!< [7..0] Pwm output over ride value. */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_OP_OVERRIDE_VALUE_RESET_REG_b; + }; + + union { + __IOM unsigned int PWM_FLT_OVERRIDE_CTRL_SET_REG; /*!< (@ 0x000000E0) fault override + control set register */ + + struct { + __IOM unsigned int FLT_A_MODE : 1; /*!< [0..0] Fault A mode */ + __IOM unsigned int FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ + __IOM unsigned int OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, + H2, H1, H0) side signals */ + __IOM unsigned int OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, + L2, L1, L0) side signals. */ + __IOM unsigned int FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate + enable bit is present for channel */ + __IOM unsigned int FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate + enable bit is present for channel */ + __IOM unsigned int COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_FLT_OVERRIDE_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int PWM_FLT_OVERRIDE_CTRL_RESET_REG; /*!< (@ 0x000000E4) fault override + control reset register */ + + struct { + __IOM unsigned int FLT_A_MODE : 1; /*!< [0..0] Fault B mode */ + __IOM unsigned int FLT_B_MODE : 1; /*!< [1..1] Fault B mode */ + __IOM unsigned int OP_POLARITY_H : 1; /*!< [2..2] Ouput polarity for high (H3, + H2, H1, H0) side signals */ + __IOM unsigned int OP_POLARITY_L : 1; /*!< [3..3] Ouput polarity for low (L3, + L2, L1, L0) side signals. */ + __IOM unsigned int FLT_A_ENABLE : 4; /*!< [7..4] Fault A enable. Separate + enable bit is present for channel */ + __IOM unsigned int FLT_B_ENABLE : 4; /*!< [11..8] Fault B enable. Separate + enable bit is present for channel */ + __IOM unsigned int COMPLEMENTARY_MODE : 4; /*!< [15..12] PWM I/O pair mode */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_FLT_OVERRIDE_CTRL_RESET_REG_b; + }; + + union { + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_REG; /*!< (@ 0x000000E8) Fault input + A PWM override value */ + + struct { + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ + __IOM unsigned int PWM_FLT_A_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_FLT_A_OVERRIDE_VALUE_REG_b; + }; + + union { + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_REG; /*!< (@ 0x000000EC) Fault input + B PWM override value */ + + struct { + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L0 : 1; /*!< [0..0] 0 bit for L0 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L1 : 1; /*!< [1..1] 1 bit for L1 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L2 : 1; /*!< [2..2] 2 bit for L2 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_L3 : 1; /*!< [3..3] 3 bit for L3 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H0 : 1; /*!< [4..4] 4 bit for H0 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H1 : 1; /*!< [5..5] 5 bit for H1 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H2 : 1; /*!< [6..6] 6 bit for H2 */ + __IOM unsigned int PWM_FLT_B_OVERRIDE_VALUE_H3 : 1; /*!< [7..7] 7 bit for H3 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } PWM_FLT_B_OVERRIDE_VALUE_REG_b; + }; + + union { + __IOM unsigned int PWM_SVT_CTRL_SET_REG; /*!< (@ 0x000000F0) NONE */ + + struct { + __IOM unsigned int SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is + used to enable + generation special event trigger */ + __IOM unsigned int SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger + for time base direction */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ + } PWM_SVT_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int PWM_SVT_CTRL_RESET_REG; /*!< (@ 0x000000F4) Special event + control reset register */ + + struct { + __IOM unsigned int SVT_ENABLE_FRM : 1; /*!< [0..0] Special event trigger enable. This is + used to enable + generation special event trigger */ + __IOM unsigned int SVT_DIRECTION_FRM : 1; /*!< [1..1] Special event trigger + for time base direction */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ + } PWM_SVT_CTRL_RESET_REG_b; + }; + + union { + __IOM unsigned int PWM_SVT_PARAM_REG; /*!< (@ 0x000000F8) Special event + parameter register */ + + struct { + __IOM unsigned int SVT_POSTSCALER_SELECT : 4; /*!< [3..0] PWM special event trigger + output postscale select bits */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } PWM_SVT_PARAM_REG_b; + }; + + union { + __IOM unsigned int PWM_SVT_COMPARE_VALUE_REG; /*!< (@ 0x000000FC) Special event + compare value register */ + + struct { + __IOM unsigned int PWM_SVT_COMPARE_VALUE : 16; /*!< [15..0] Special event compare value. + This is used to compare with pwm time + period counter to generate special + event trigger */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_SVT_COMPARE_VALUE_REG_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH1; /*!< (@ 0x00000100) Base timer + period register of channel1 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH1 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH1_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH1; /*!< (@ 0x00000104) Base time + counter initial value + register for channel1 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH1 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 1 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH1_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH1; /*!< (@ 0x00000108) NONE */ + + struct { + __IOM unsigned int TMR_OPEARATING_MODE_CH1 : 3; /*!< [2..0] Base timer operating mode for + channel1 */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH1 : 3; /*!< [6..4] Base timer input + clock prescale select value + for channel1. */ + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH1 : 4; /*!< [11..8] Time base output + post scale bits for + channel1 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH1_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH1; /*!< (@ 0x0000010C) Base time period control + register for channel1 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH1 : 1; /*!< [1..1] Base timer enable for + channnel1 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH1_b; + }; + + union { + __IM unsigned int PWM_TIME_PRD_STS_REG_CH1; /*!< (@ 0x00000110) Base time period + status register for channel1 */ + + struct { + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH1 : 1; /*!< [0..0] Time period counter + direction status for channel1. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_STS_REG_CH1_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH1; /*!< (@ 0x00000114) Time period counter + current value for channel1 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH1 : 1; /*!< [0..0] Time period counter + current value for channel1 */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH1_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH2; /*!< (@ 0x00000118) Base timer + period register of channel2 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH2 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 2 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH2_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH2; /*!< (@ 0x0000011C) Base time + counter initial value + register for channel2 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH2 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 2 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH2_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH2; /*!< (@ 0x00000120) Base time period config + parameter's register for channel2 */ + + struct { + __IOM unsigned int TMR_OPEARATING_MODE_CH2 : 3; /*!< [2..0] Base timer operating mode for + channel2 */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH2 : 3; /*!< [6..4] Base timer input + clock pre scale select value + for channel2. */ + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH2 : 4; /*!< [11..8] Time base output + post scale bits for + channel2 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH2_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH2; /*!< (@ 0x00000124) Base time period control + register for channel2 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH2 : 1; /*!< [1..1] Base timer enable for + channnel2 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH2_b; + }; + + union { + __IM unsigned int PWM_TIME_PRD_STS_REG_CH2; /*!< (@ 0x00000128) Base time period + status register for channel2 */ + + struct { + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH2 : 1; /*!< [0..0] Time period counter + direction status for channel2. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } PWM_TIME_PRD_STS_REG_CH2_b; + }; + + union { + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH2; /*!< (@ 0x0000012C) Time period counter + current value register for channel2 */ + + struct { + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH2 : 1; /*!< [0..0] Time period counter + current value for channel2 */ + __IM unsigned int RESERVED1 : 11; /*!< [11..1] reserved1 */ + __IM unsigned int RESERVED2 : 20; /*!< [31..12] reserved2 */ + } PWM_TIME_PRD_CNTR_VALUE_CH2_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_WR_REG_CH3; /*!< (@ 0x00000130) Base timer + period register of channel3 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_REG_WR_VALUE_CH3 : 16; /*!< [15..0] To update the base + time counter initial value for + channel + 3 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_WR_REG_CH3_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH3; /*!< (@ 0x00000134) Base time + counter initial value + register for channel3 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_WR_REG_CH3 : 16; /*!< [15..0] Value to update the + base timer period register of + channel + 3 */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_WR_REG_CH3_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_PARAM_REG_CH3; /*!< (@ 0x00000138) Base time period config + parameter's register for channel3 */ + + struct { + __IOM unsigned int TMR_OPEARATING_MODE_CH3 : 3; /*!< [2..0] Base timer operating mode for + channel3 */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int PWM_TIME_PRD_PRE_SCALAR_VALUE_CH3 : 3; /*!< [6..4] Base timer input + clock pre scale select value + for channel2. */ + __IOM unsigned int RESERVED2 : 1; /*!< [7..7] reserved2 */ + __IOM unsigned int PWM_TIME_PRD_POST_SCALAR_VALUE_CH3 : 4; /*!< [11..8] Time base output + post scale bits for + channel3 */ + __IOM unsigned int RESERVED3 : 20; /*!< [31..12] reserved3 */ + } PWM_TIME_PRD_PARAM_REG_CH3_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_CTRL_REG_CH3; /*!< (@ 0x0000013C) Base time period control + register for channel3 */ + + struct { + __IOM unsigned int PWM_TIME_PRD_CNTR_RST_FRM_REG : 1; /*!< [0..0] Time period counter + soft reset */ + __IOM unsigned int PWM_TIME_BASE_EN_FRM_REG_CH3 : 1; /*!< [1..1] Base timer enable for + channnel3 */ + __IOM unsigned int PWM_SFT_RST : 1; /*!< [2..2] MC PWM soft reset */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } PWM_TIME_PRD_CTRL_REG_CH3_b; + }; + + union { + __IM unsigned int PWM_TIME_PRD_STS_REG_CH3; /*!< (@ 0x00000140) Base time period + status register for channel3 */ + + struct { + __IM unsigned int PWM_TIME_PRD_DIR_STS_CH3 : 1; /*!< [0..0] Time period counter + direction status for channel3. */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } PWM_TIME_PRD_STS_REG_CH3_b; + }; + + union { + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH3; /*!< (@ 0x00000144) Time period counter + current value register for channel3 */ + + struct { + __IM unsigned int PWM_TIME_PRD_CNTR_VALUE_CH3 : 16; /*!< [15..0] Time period counter + current value for channe3 */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } PWM_TIME_PRD_CNTR_VALUE_CH3_b; + }; + + union { + __IOM unsigned int PWM_TIME_PRD_COMMON_REG; /*!< (@ 0x00000148) Time period + common register */ + + struct { + __IOM unsigned int PWM_TIME_PRD_USE_0TH_TIMER_ONLY : 1; /*!< [0..0] Instead of use four + base timers for four channels, + use only one base timer for + all channels. */ + __IOM unsigned int PWM_TIME_PRD_COMMON_TIMER_VALUE : 2; /*!< [2..1] Base timers select to + generate special event trigger + */ + __IOM unsigned int USE_EXT_TIMER_TRIG_FRM_REG : 1; /*!< [3..3] Enable to use external + trigger for base time counter + increment or decrement. */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } PWM_TIME_PRD_COMMON_REG_b; + }; +} MCPWM_Type; /*!< Size = 332 (0x14c) */ + +/* =========================================================================================================================== + */ +/* ================ UDMA0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief DMA Performs data transfers along with Addresses and control + * information (UDMA0) + */ + +typedef struct { /*!< (@ 0x44030000) UDMA0 Structure */ + + union { + __IM unsigned int DMA_STATUS; /*!< (@ 0x00000000) UDMA Status Register */ + + struct { + __IM unsigned int MASTER_ENABLE : 1; /*!< [0..0] Enable status of controller */ + __IM unsigned int RESERVED1 : 3; /*!< [3..1] Reserved1 */ + __IM unsigned int STATE : 4; /*!< [7..4] Current state of the control state machine */ + __IM unsigned int RESERVED2 : 8; /*!< [15..8] Reserved2 */ + __IM unsigned int CHNLS_MINUS1 : 5; /*!< [20..16] Number of available DMA + channels minus one */ + __IM unsigned int RESERVED3 : 7; /*!< [27..21] Reserved3 */ + __IM unsigned int TEST_STATUS : 4; /*!< [31..28] To reduce the gate count you + can configure the controller */ + } DMA_STATUS_b; + }; + + union { + __OM unsigned int DMA_CFG; /*!< (@ 0x00000004) DMA Configuration */ + + struct { + __OM unsigned int MASTER_ENABLE : 1; /*!< [0..0] Enable for the controller */ + __OM unsigned int RESERVED1 : 4; /*!< [4..1] Reserved1 */ + __OM unsigned int CHNL_PROT_CTRL : 3; /*!< [7..5] Sets the AHB-Lite protection by + controlling the HPROT[3:1]] signal levels as + follows Bit[7]-Controls HPROT[3] to indicate if + cacheable access is occurring Bit[6]-Controls + HPROT[2] to indicate if cacheable access is + occurring Bit[5]-Controls + HPROT[1] to indicate if cacheable + access is occurring */ + __OM unsigned int RESERVED2 : 24; /*!< [31..8] Reserved2 */ + } DMA_CFG_b; + }; + + union { + __IOM unsigned int CTRL_BASE_PTR; /*!< (@ 0x00000008) Channel Control Data Base + Pointer */ + + struct { + __OM unsigned int RESERVED1 : 10; /*!< [9..0] Reserved1 */ + __IOM unsigned int CTRL_BASE_PTR : 22; /*!< [31..10] Pointer to the base address of the + primary data structure */ + } CTRL_BASE_PTR_b; + }; + + union { + __IM unsigned int ALT_CTRL_BASE_PTR; /*!< (@ 0x0000000C) Channel Alternate + Control Data Base Pointer */ + + struct { + __IM unsigned int ALT_CTRL_BASE_PTR : 32; /*!< [31..0] Base address of the + alternative data structure */ + } ALT_CTRL_BASE_PTR_b; + }; + + union { + __IM unsigned int DMA_WAITONREQUEST_STATUS; /*!< (@ 0x00000010) Channel Wait on + request status register */ + + struct { + __IM unsigned int DMA_WAITONREQ_STATUS : 32; /*!< [31..0] Per Channel wait on + request status */ + } DMA_WAITONREQUEST_STATUS_b; + }; + + union { + __OM unsigned int CHNL_SW_REQUEST; /*!< (@ 0x00000014) Channel Software Request */ + + struct { + __OM unsigned int CHNL_SW_REQUEST : 32; /*!< [31..0] Set the appropriate bit to generate + a software DMA request on the corresponding + DMA channel */ + } CHNL_SW_REQUEST_b; + }; + + union { + __IOM unsigned int CHNL_USEBURST_SET; /*!< (@ 0x00000018) UDMA Channel use burst set */ + + struct { + __IOM unsigned int CHNL_USEBURST_SET : 32; /*!< [31..0] The use burst status, + or disables dma_sreq[C] from + generating DMA requests. */ + } CHNL_USEBURST_SET_b; + }; + + union { + __OM unsigned int CHNL_USEBURST_CLR; /*!< (@ 0x0000001C) UDMA Channel use burst clear */ + + struct { + __OM unsigned int CHNL_USEBURST_CLR : 32; /*!< [31..0] Set the appropriate bit to enable + dma_sreq[] to generate requests */ + } CHNL_USEBURST_CLR_b; + }; + + union { + __IOM unsigned int CHNL_REQ_MASK_SET; /*!< (@ 0x00000020) UDMA Channel request + mask set Register */ + + struct { + __IOM unsigned int CHNL_REQ_MASK_SET : 32; /*!< [31..0] Returns the request mask status + of dma_req[] and dma_sreq[], or disables + the corresponding channel from generating + DMA requests */ + } CHNL_REQ_MASK_SET_b; + }; + + union { + __OM unsigned int CHNL_REQ_MASK_CLR; /*!< (@ 0x00000024) UDMA Channel request + mask clear */ + + struct { + __OM unsigned int CHNL_REQ_MASK_CLR : 32; /*!< [31..0] Set the appropriate bit + to enable DMA requests for the + channel corresponding to + dma_req[] and dma_sreq[] */ + } CHNL_REQ_MASK_CLR_b; + }; + + union { + __IOM unsigned int CHNL_ENABLE_SET; /*!< (@ 0x00000028) UDMA Channel enable register */ + + struct { + __IOM unsigned int CHNL_ENABLE_SET : 32; /*!< [31..0] This Bits are Used to Load the + 16bits of Source address */ + } CHNL_ENABLE_SET_b; + }; + + union { + __OM unsigned int CHNL_ENABLE_CLR; /*!< (@ 0x0000002C) UDMA Channel enable clear + register */ + + struct { + __OM unsigned int CHNL_ENABLE_CLR : 32; /*!< [31..0] Set the appropriate bit to disable + the corresponding DMA channel */ + } CHNL_ENABLE_CLR_b; + }; + + union { + __IOM unsigned int CHNL_PRI_ALT_SET; /*!< (@ 0x00000030) UDMA Channel primary or + alternate set */ + + struct { + __IOM unsigned int CHNL_PRI_ALT_SET : 32; /*!< [31..0] Returns the channel control data + structure status or selects the alternate + data structure for the corresponding DMA + channel */ + } CHNL_PRI_ALT_SET_b; + }; + + union { + __OM unsigned int CHNL_PRI_ALT_CLR; /*!< (@ 0x00000034) UDMA Channel primary + alternate clear */ + + struct { + __OM unsigned int CHNL_PRI_ALT_CLR : 32; /*!< [31..0] Set the appropriate bit to select + the primary data structure for the + corresponding DMA channel */ + } CHNL_PRI_ALT_CLR_b; + }; + + union { + __IOM unsigned int CHNL_PRIORITY_SET; /*!< (@ 0x00000038) UDMA Channel Priority Set */ + + struct { + __IOM unsigned int CHNL_PRIORITY_SET : 32; /*!< [31..0] Set the appropriate bit to select + the primary data structure for the + corresponding DMA channel */ + } CHNL_PRIORITY_SET_b; + }; + + union { + __OM unsigned int CHNL_PRIORITY_CLR; /*!< (@ 0x0000003C) UDMA Channel Priority Clear */ + + struct { + __OM unsigned int CHNL_PRIORITY_CLR : 32; /*!< [31..0] Set the appropriate bit to select + the default priority level for the + specified DMA channel */ + } CHNL_PRIORITY_CLR_b; + }; + __IM unsigned int RESERVED[3]; + + union { + __IOM unsigned int ERR_CLR; /*!< (@ 0x0000004C) UDMA Bus Error Clear Register */ + + struct { + __IOM unsigned int ERR_CLR : 1; /*!< [0..0] Returns the status of dma_err */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } ERR_CLR_b; + }; + + union { + __IOM unsigned int UDMA_SKIP_DESC_FETCH_REG; /*!< (@ 0x00000050) UDMA skip + descriptor fetch Register */ + + struct { + __IOM unsigned int SKIP_DESC_FETCH : 32; /*!< [31..0] improving the + performance of transfer and saves + bus cycles. This features has to + be enabled always. */ + } UDMA_SKIP_DESC_FETCH_REG_b; + }; + __IM unsigned int RESERVED1[491]; + + union { + __IOM unsigned int UDMA_DONE_STATUS_REG; /*!< (@ 0x00000800) UDMA Done status Register */ + + struct { + __IOM unsigned int DONE_STATUS_CHANNEL_0 : 1; /*!< [0..0] UDMA done Status of + the channel 0 */ + __IOM unsigned int DONE_STATUS_CHANNEL_1 : 1; /*!< [1..1] UDMA done Status of + the channel 1 */ + __IOM unsigned int DONE_STATUS_CHANNEL_2 : 1; /*!< [2..2] UDMA done Status of + the channel 2 */ + __IOM unsigned int DONE_STATUS_CHANNEL_3 : 1; /*!< [3..3] UDMA done Status of + the channel 3 */ + __IOM unsigned int DONE_STATUS_CHANNEL_4 : 1; /*!< [4..4] UDMA done Status of + the channel 4 */ + __IOM unsigned int DONE_STATUS_CHANNEL_5 : 1; /*!< [5..5] UDMA done Status of + the channel 5 */ + __IOM unsigned int DONE_STATUS_CHANNEL_6 : 1; /*!< [6..6] UDMA done Status of + the channel 6 */ + __IOM unsigned int DONE_STATUS_CHANNEL_7 : 1; /*!< [7..7] UDMA done Status of + the channel 7 */ + __IOM unsigned int DONE_STATUS_CHANNEL_8 : 1; /*!< [8..8] UDMA done Status of + the channel 8 */ + __IOM unsigned int DONE_STATUS_CHANNEL_9 : 1; /*!< [9..9] UDMA done Status of + the channel 9 */ + __IOM unsigned int DONE_STATUS_CHANNEL_10 : 1; /*!< [10..10] UDMA done Status + of the channel 10 */ + __IOM unsigned int DONE_STATUS_CHANNEL_11 : 1; /*!< [11..11] UDMA done Status + of the channel 3 */ + __IOM unsigned int DONE_STATUS_CHANNEL_12 : 1; /*!< [12..12] UDMA done Status + of the channel 12 */ + __IOM unsigned int DONE_STATUS_CHANNEL_13 : 1; /*!< [13..13] UDMA done Status + of the channel 13 */ + __IOM unsigned int DONE_STATUS_CHANNEL_14 : 1; /*!< [14..14] UDMA done Status + of the channel 14 */ + __IOM unsigned int DONE_STATUS_CHANNEL_15 : 1; /*!< [15..15] UDMA done Status + of the channel 15 */ + __IOM unsigned int DONE_STATUS_CHANNEL_16 : 1; /*!< [16..16] UDMA done Status + of the channel 16 */ + __IOM unsigned int DONE_STATUS_CHANNEL_17 : 1; /*!< [17..17] UDMA done Status + of the channel 17 */ + __IOM unsigned int DONE_STATUS_CHANNEL_18 : 1; /*!< [18..18] UDMA done Status + of the channel 18 */ + __IOM unsigned int DONE_STATUS_CHANNEL_19 : 1; /*!< [19..19] UDMA done Status + of the channel 19 */ + __IOM unsigned int DONE_STATUS_CHANNEL_20 : 1; /*!< [20..20] UDMA done Status + of the channel 3 */ + __IOM unsigned int DONE_STATUS_CHANNEL_21 : 1; /*!< [21..21] UDMA done Status + of the channel 21 */ + __IOM unsigned int DONE_STATUS_CHANNEL_22 : 1; /*!< [22..22] UDMA done Status + of the channel 22 */ + __IOM unsigned int DONE_STATUS_CHANNEL_23 : 1; /*!< [23..23] UDMA done Status + of the channel 23 */ + __IOM unsigned int DONE_STATUS_CHANNEL_24 : 1; /*!< [24..24] UDMA done Status + of the channel 24 */ + __IOM unsigned int DONE_STATUS_CHANNEL_25 : 1; /*!< [25..25] UDMA done Status + of the channel 25 */ + __IOM unsigned int DONE_STATUS_CHANNEL_26 : 1; /*!< [26..26] UDMA done Status + of the channel 26 */ + __IOM unsigned int DONE_STATUS_CHANNEL_27 : 1; /*!< [27..27] UDMA done Status + of the channel 27 */ + __IOM unsigned int DONE_STATUS_CHANNEL_28 : 1; /*!< [28..28] UDMA done Status + of the channel 28 */ + __IOM unsigned int DONE_STATUS_CHANNEL_29 : 1; /*!< [29..29] UDMA done Status + of the channel 29 */ + __IOM unsigned int DONE_STATUS_CHANNEL_30 : 1; /*!< [30..30] UDMA done Status + of the channel 30 */ + __IOM unsigned int DONE_STATUS_CHANNEL_31 : 1; /*!< [31..31] UDMA done Status + of the channel 31 */ + } UDMA_DONE_STATUS_REG_b; + }; + + union { + __IM unsigned int CHANNEL_STATUS_REG; /*!< (@ 0x00000804) Channel status Register */ + + struct { + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_0 : 1; /*!< [0..0] Reading 1 indicates + that the channel 0 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_1 : 1; /*!< [1..1] Reading 1 indicates + that the channel 1 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_2 : 1; /*!< [2..2] Reading 1 indicates + that the channel 2 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_3 : 1; /*!< [3..3] Reading 1 indicates + that the channel 3 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_4 : 1; /*!< [4..4] Reading 1 indicates + that the channel 4 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_5 : 1; /*!< [5..5] Reading 1 indicates + that the channel 5 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_6 : 1; /*!< [6..6] Reading 1 indicates + that the channel 6 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_7 : 1; /*!< [7..7] Reading 1 indicates + that the channel 7 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_8 : 1; /*!< [8..8] Reading 1 indicates + that the channel 8 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_9 : 1; /*!< [9..9] Reading 1 indicates + that the channel 9 is busy */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_10 : 1; /*!< [10..10] Reading 1 + indicates that the + channel 10 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_11 : 1; /*!< [11..11] Reading 1 + indicates that the + channel 11 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_12 : 1; /*!< [12..12] Reading 1 + indicates that the + channel 12 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_13 : 1; /*!< [13..13] Reading 1 + indicates that the + channel 13 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_14 : 1; /*!< [14..14] Reading 1 + indicates that the + channel 14 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_15 : 1; /*!< [15..15] Reading 1 + indicates that the + channel 15 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_16 : 1; /*!< [16..16] Reading 1 + indicates that the + channel 16 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_17 : 1; /*!< [17..17] Reading 1 + indicates that the + channel 17 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_18 : 1; /*!< [18..18] Reading 1 + indicates that the + channel 18 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_19 : 1; /*!< [19..19] Reading 1 + indicates that the + channel 19 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_20 : 1; /*!< [20..20] Reading 1 + indicates that the + channel 20 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_21 : 1; /*!< [21..21] Reading 1 + indicates that the + channel 21 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_22 : 1; /*!< [22..22] Reading 1 + indicates that the + channel 22 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_23 : 1; /*!< [23..23] Reading 1 + indicates that the + channel 23 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_24 : 1; /*!< [24..24] Reading 1 + indicates that the + channel 24 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_25 : 1; /*!< [25..25] Reading 1 + indicates that the + channel 25 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_26 : 1; /*!< [26..26] Reading 1 + indicates that the + channel 26 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_27 : 1; /*!< [27..27] Reading 1 + indicates that the + channel 27 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_28 : 1; /*!< [28..28] Reading 1 + indicates that the + channel 28 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_29 : 1; /*!< [29..29] Reading 1 + indicates that the + channel 29 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_30 : 1; /*!< [30..30] Reading 1 + indicates that the + channel 30 is busy + */ + __IM unsigned int BUSY_OR_IDEAL_STATUS_CHANNEL_31 : 1; /*!< [31..31] Reading 1 + indicates that the + channel 31 is busy + */ + } CHANNEL_STATUS_REG_b; + }; + __IM unsigned int RESERVED2[8]; + + union { + __IOM unsigned int UDMA_CONFIG_CTRL_REG; /*!< (@ 0x00000828) DMA Controller + Transfer Length Register */ + + struct { + __IOM unsigned int SINGLE_REQUEST_ENABLE : 1; /*!< [0..0] Enabled signal for + single request */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ + } UDMA_CONFIG_CTRL_REG_b; + }; + + union { + __IOM unsigned int UDMA_INTR_MASK_REG; /*!< (@ 0x0000082C) Mask the uDMA + interrupt register */ + + struct { + __IOM unsigned int UDMA_INTR_MASK : 12; /*!< [11..0] Mask the uDMA interrupt + register */ + __IM unsigned int RESERVED1 : 20; /*!< [31..12] RESERVED1 */ + } UDMA_INTR_MASK_REG_b; + }; +} UDMA0_Type; /*!< Size = 2096 (0x830) */ + +/* =========================================================================================================================== + */ +/* ================ GPDMA_G + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief GPDMA is an AMBA complaint peripheral unit supports 8-channels + * (GPDMA_G) + */ + +typedef struct { /*!< (@ 0x21080000) GPDMA_G Structure */ + __IM unsigned int RESERVED[1057]; + __IOM GPDMA_G_GLOBAL_Type GLOBAL; /*!< (@ 0x00001084) GLOBAL */ +} GPDMA_G_Type; /*!< Size = 4252 (0x109c) */ + +/* =========================================================================================================================== + */ +/* ================ GPDMA_C + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief GPDMAC (dma controller) is an AMBA complaint peripheral unit supports + * 8-channels (GPDMA_C) + */ + +typedef struct { /*!< (@ 0x21081004) GPDMA_C Structure */ + __IOM GPDMA_C_CHANNEL_CONFIG_Type CHANNEL_CONFIG[8]; /*!< (@ 0x00000000) [0..7] */ +} GPDMA_C_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== + */ +/* ================ HWRNG + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Random numbers generated are 16-bit random numbers and are generated + using either the True random number generator or the Pseudo random number + generator. (HWRNG) + */ + +typedef struct { /*!< (@ 0x45090000) HWRNG Structure */ + + union { + __IOM unsigned int HWRNG_CTRL_REG; /*!< (@ 0x00000000) Random Number Generator + Control Register */ + + struct { + __IOM unsigned int HWRNG_RNG_ST : 1; /*!< [0..0] This bit is used to start the + true number generation. */ + __IOM unsigned int HWRNG_PRBS_ST : 1; /*!< [1..1] This bit is used to start the pseudo + random number generation */ + __IOM unsigned int SOFT_RESET : 1; /*!< [2..2] This bit is used to start the + pseudo random number generation */ + __IOM unsigned int TAP_LFSR_INPUT : 1; /*!< [3..3] This bit is used to Enable bit for + Tapping LFSR input data which is coming from RING Oscillator */ + __IM unsigned int LFSR_32_BIT_INPUT_VALID : 1; /*!< [4..4] This bit is used to + Indicates when a valid 32 bit LFSR input data is latched + After setting this bit, Firmware has to read LFSR_INPUT_LATCH_REG */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] RESERVED1 */ + + } HWRNG_CTRL_REG_b; + }; + + union { + __IM unsigned int HWRNG_RAND_NUM_REG; /*!< (@ 0x00000004) Hardware Random Number + Register */ + + struct { + __IM unsigned int HWRNG_RAND_NUM : 32; /*!< [31..0] Generated random number + can be read from this register. */ + } HWRNG_RAND_NUM_REG_b; + struct { + __IM unsigned int HWRNG_LFSR_INPUT_LATCH_REG : 32; /*!< [31..0] LFSR Input Latch Register. */ + } HWRNG_LFSR_INPUT_LATCH_REG_REG_b; + }; +} HWRNG_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== + */ +/* ================ TIMERS + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief TIMER can be used to generate various timing events for the software + * (TIMERS) + */ + +typedef struct { /*!< (@ 0x24042000) TIMERS Structure */ + __IOM TIMERS_MATCH_CTRL_Type MATCH_CTRL[4]; /*!< (@ 0x00000000) [0..3] */ + __IM unsigned int RESERVED[24]; + + union { + __IOM unsigned int MCUULP_TMR_INTR_STAT; /*!< (@ 0x00000080) Timer Status Register */ + + struct { + __IOM unsigned int TMR0_INTR_STATUS : 1; /*!< [0..0] This bit indicates status of the + interrupt generated by timer 0 */ + __IOM unsigned int TMR1_INTR_STATUS : 1; /*!< [1..1] This bit indicates status of the + interrupt generated by timer 1 */ + __IOM unsigned int TMR2_INTR_STATUS : 1; /*!< [2..2] This bit indicates status of the + interrupt generated by timer 2 */ + __IOM unsigned int TMR3_INTR_STATUS : 1; /*!< [3..3] This bit indicates status of the + interrupt generated by timer 3 */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } MCUULP_TMR_INTR_STAT_b; + }; + + union { + __IOM unsigned int MCUULP_TMR_US_PERIOD_INT; /*!< (@ 0x00000084) Timer micro second period + Integral Part Register */ + + struct { + __IOM unsigned int TMR_US_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the + integer part of number + of clock cycles per microseconds of + the system clock used */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } MCUULP_TMR_US_PERIOD_INT_b; + }; + + union { + __IOM unsigned int MCUULP_TMR_US_PERIOD_FRAC; /*!< (@ 0x00000088) Timer microsecond period + Fractional Part Register */ + + struct { + __IOM unsigned int TMR_US_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the + fractional part of number of clock cycles + per microseconds of the system clock used + */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MCUULP_TMR_US_PERIOD_FRAC_b; + }; + + union { + __IOM unsigned int MCUULP_TMR_MS_PERIOD_INT; /*!< (@ 0x0000008C) Timer 256 microsecond + period Integral Part Register */ + + struct { + __IOM unsigned int TMR_MS_PERIOD_INT : 16; /*!< [15..0] This bits are used to program the + integer part of number of clock cycles per + 256 microseconds of the system clock used + */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } MCUULP_TMR_MS_PERIOD_INT_b; + }; + + union { + __IOM unsigned int MCUULP_TMR_MS_PERIOD_FRAC; /*!< (@ 0x00000090) Timer 256 microsecond + period Fractional Part Register */ + + struct { + __IOM unsigned int TMR_MS_PERIOD_FRAC : 8; /*!< [7..0] This bits are used to program the + fractional part of number of clock cycles + per 256 microseconds of the system clock + used */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MCUULP_TMR_MS_PERIOD_FRAC_b; + }; + __IM unsigned int RESERVED1[2]; + + union { + __IM unsigned int MCUULP_TMR_ACTIVE_STATUS; /*!< (@ 0x0000009C) Timer Active + Status Register */ + + struct { + __IM unsigned int TIMER_ACTIVE : 4; /*!< [3..0] Timer active status for each + timer. LSB bit specifies + the status for 0th timer + and so on. */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } MCUULP_TMR_ACTIVE_STATUS_b; + }; +} TIMERS_Type; /*!< Size = 160 (0xa0) */ + +/* =========================================================================================================================== + */ +/* ================ QEI + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The Quadrature Encoder Interface (QEI) module provides the interface + to incremental encoders for obtaining mechanical position data (QEI) + */ + +typedef struct { /*!< (@ 0x47060000) QEI Structure */ + + union { + __IM unsigned int QEI_STATUS_REG; /*!< (@ 0x00000000) Quadrature Encoder status + register */ + + struct { + __IM unsigned int QEI_INDEX : 1; /*!< [0..0] This is a direct value from the + position signal generator */ + __IM unsigned int QEI_POSITION_B : 1; /*!< [1..1] This is a direct value from the + position signal generator.Value refers to the + signal Position_B from the generator. */ + __IM unsigned int QEI_POSITION_A : 1; /*!< [2..2] This is a direct value from the + position signal generator.Value refers to the + signal Position_A from the generator. */ + __IM unsigned int POSITION_CNTR_ERR : 1; /*!< [3..3] Count Error Status Flag bit */ + __IM unsigned int POSITION_CNTR_DIRECTION : 1; /*!< [4..4] Position Counter + Direction Status bit */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } QEI_STATUS_REG_b; + }; + + union { + __IOM unsigned int QEI_CTRL_REG_SET; /*!< (@ 0x00000004) Quadrature Encoder + control set register */ + + struct { + __IM unsigned int QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. + It is self reset signal. */ + __IOM unsigned int QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B + Input Swap Select bit */ + __IOM unsigned int POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input + Swap Select bit */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM unsigned int POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ + __IOM unsigned int POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction + indication from user */ + __IOM unsigned int RESERVED2 : 1; /*!< [6..6] Reserved2 */ + __IOM unsigned int RESERVED3 : 1; /*!< [7..7] Reserved3 */ + __IOM unsigned int INDEX_CNT_RST_EN : 1; /*!< [8..8] Index count reset enable */ + __IOM unsigned int DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ + __IOM unsigned int TIMER_MODE : 1; /*!< [10..10] NONE */ + __IOM unsigned int START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. + It is self reset bit. */ + __IOM unsigned int QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ + __IOM unsigned int QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit + mode enable */ + __IOM unsigned int POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going + to reset */ + __IOM unsigned int INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going + to reset. */ + __IOM unsigned int RESERVED4 : 16; /*!< [31..16] Reserved4 */ + } QEI_CTRL_REG_SET_b; + }; + + union { + __IOM unsigned int QEI_CTRL_REG_RESET; /*!< (@ 0x00000008) Quadrature Encoder + control reset register */ + + struct { + __IM unsigned int QEI_SFT_RST : 1; /*!< [0..0] Quadrature encoder soft reset. + It is self reset signal */ + __IOM unsigned int QEI_SWAP_PHASE_AB : 1; /*!< [1..1] Phase A and Phase B + Input Swap Select bit */ + __IOM unsigned int POS_CNT_RST_WITH_INDEX_EN : 1; /*!< [2..2] Phase A and Phase B Input + Swap Select bit */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM unsigned int POS_CNT_DIRECTION_CTRL : 1; /*!< [4..4] NONE */ + __IOM unsigned int POS_CNT_DIR_FRM_REG : 1; /*!< [5..5] Position Counter Direction + indication from user */ + __IOM unsigned int RESERVED2 : 1; /*!< [6..6] Reserved2 */ + __IOM unsigned int RESERVED3 : 1; /*!< [7..7] Reserved3 */ + __IOM unsigned int INDEX_CNT_RST_EN : 1; /*!< [8..8] NONE */ + __IOM unsigned int DIGITAL_FILTER_BYPASS : 1; /*!< [9..9] NONE */ + __IOM unsigned int TIMER_MODE : 1; /*!< [10..10] NONE */ + __IOM unsigned int START_VELOCITY_CNTR : 1; /*!< [11..11] Starting the velocity counter. + It is self reset bit. */ + __IOM unsigned int QEI_STOP_IN_IDLE : 1; /*!< [12..12] NONE */ + __IOM unsigned int QEI_POS_CNT_16_BIT_MODE : 1; /*!< [13..13] Qei position counter 16 bit + mode enable */ + __IOM unsigned int POS_CNT_RST : 1; /*!< [14..14] 1=position counter is going + to reset */ + __IOM unsigned int INDEX_CNT_RST : 1; /*!< [15..15] 1= index counter is going + to reset. */ + __IOM unsigned int RESERVED4 : 16; /*!< [31..16] Reserved4 */ + } QEI_CTRL_REG_RESET_b; + }; + + union { + __IOM unsigned int QEI_CNTLR_INIT_REG; /*!< (@ 0x0000000C) Quadrature Encoder + initialization register */ + + struct { + __IOM unsigned int QEI_ENCODING_MODE : 2; /*!< [1..0] NONE */ + __IOM unsigned int RESERVED1 : 2; /*!< [3..2] Reserved1 */ + __IOM unsigned int INDEX_MATCH_VALUE : 2; /*!< [5..4] These bits allow user to specify + the state of position A and B during index + pulse generation. */ + __IOM unsigned int DF_CLK_DIVIDE_SLT : 4; /*!< [9..6] Digital Filter Clock + Divide Select bits */ + __IOM unsigned int UNIDIRECTIONAL_VELOCITY : 1; /*!< [10..10] Uni directional + velocity enable. */ + __IOM unsigned int UNIDIRECTIONAL_INDEX : 1; /*!< [11..11] Uni directional + index enable. */ + __IOM unsigned int INDEX_CNT_INIT : 1; /*!< [12..12] Index counter initial value in + unidirectional index enable mode. */ + __IOM unsigned int RESERVED2 : 19; /*!< [31..13] Reserved2 */ + } QEI_CNTLR_INIT_REG_b; + }; + + union { + __IOM unsigned int QEI_INDEX_CNT_REG; /*!< (@ 0x00000010) Quadrature Encoder + index counter register */ + + struct { + __IOM unsigned int QEI_INDEX_CNT : 16; /*!< [15..0] Index counter value.User + can initialize/change the index + counter using this register */ + __IOM unsigned int QEI_INDEX_CNT_WR_VALUE : 16; /*!< [31..16] User can initialize/change + the index counter using + this register. */ + } QEI_INDEX_CNT_REG_b; + }; + + union { + __IOM unsigned int QEI_INDEX_MAX_CNT_REG; /*!< (@ 0x00000014) Quadrature Encoder maximum + index counter value register */ + + struct { + __IOM unsigned int QEI_INDEX_MAX_CNT : 16; /*!< [15..0] This is a maximum count value + that is allowed to increment in the index + counter. If index counter reaches this + value, will get reset to zero */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } QEI_INDEX_MAX_CNT_REG_b; + }; + + union { + __IOM unsigned int QEI_POSITION_CNT_REG; /*!< (@ 0x00000018) Quadrature Encoder maximum + position counter value register */ + + struct { + __IOM unsigned int QEI_POSITION_CNT_WR_VALUE_L : 16; /*!< [15..0] This is a maximum count + value that is allowed to + increment in the position + counter. */ + __IOM unsigned int QEI_POSITION_CNT_WR_VALUE_H : 16; /*!< [31..16] This is a maximum + count value that is allowed to + increment in the position + counter. */ + } QEI_POSITION_CNT_REG_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int QEI_POSITION_MAX_CNT_LSW_REG; /*!< (@ 0x00000020) Quadrature + Encoder maximum position + counter value register */ + + struct { + __IOM unsigned int QEI_POSITION_MAX_CNT_L : 16; /*!< [15..0] This is a maximum + count value that is allowed + to increment in the + position counter. */ + __IOM unsigned int QEI_POSITION_MAX_CNT_H : 16; /*!< [31..16] This is a maximum count + value that is allowed to increment + in the position counter. + */ + } QEI_POSITION_MAX_CNT_LSW_REG_b; + }; + __IM unsigned int RESERVED1; + + union { + __IM unsigned int QEI_INTR_STS_REG; /*!< (@ 0x00000028) Quadrature Encoder + interrupt status register */ + + struct { + __IM unsigned int QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] This is raised when + the position counter reaches + it's extremes */ + __IM unsigned int QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] This is raised when + index counter reaches max value + loaded in to index_max_cnt + register. */ + __IM unsigned int POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Whenever number of + possible positions are mismatched + with actual positions are received + between two index pulses this will + raised */ + __IM unsigned int VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] When velocity count is + less than the value given in + velocity_value_to_c mpare + register, interrupt is raised */ + __IM unsigned int QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] This is raised when + the position counter reaches + position + match value, which is + programmable. */ + __IM unsigned int QEI_VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] When velocity + count is computed for + given delta time, than + interrupt is raised. */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved1 */ + } QEI_INTR_STS_REG_b; + }; + + union { + __IOM unsigned int QEI_INTR_ACK_REG; /*!< (@ 0x0000002C) Quadrature Encoder + interrupt acknowledge register */ + + struct { + __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_LEV : 1; /*!< [0..0] + Qei_position_cnt_reset_intr_ack + */ + __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_LEV : 1; /*!< [1..1] NONE */ + __IOM unsigned int POSITION_CNTR_ERR_INTR_LEV : 1; /*!< [2..2] Position_cntr_err_intr_ack + */ + __IOM unsigned int VELOCITY_LESS_THAN_INTR_LEV : 1; /*!< [3..3] + Velocity_less_than_intr_ack */ + __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_LEV : 1; /*!< [4..4] + Qei_position_cnt_match_intr_ack + */ + __IOM unsigned int VELOCITY_COMPUTATION_OVER_INTR_LEV : 1; /*!< [5..5] + Velocity_computation_over_intr_ack + */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved1 */ + } QEI_INTR_ACK_REG_b; + }; + + union { + __IOM unsigned int QEI_INTR_MASK_REG; /*!< (@ 0x00000030) Quadrature Encoder + interrupt mask register */ + + struct { + __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_MASK : 1; /*!< [0..0] + Qei_position_cnt_reset_intr_mask + */ + __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_MASK : 1; /*!< [1..1] + Qei_index_cnt_match_intr_mask + */ + __IOM unsigned int POSITION_CNTR_ERR_INTR_MASK : 1; /*!< [2..2] + Position_cntr_err_intr_mask */ + __IOM unsigned int VELOCITY_LESS_THAN_INTR_MASK : 1; /*!< [3..3] + Velocity_less_than_intr_mask */ + __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_MASK : 1; /*!< [4..4] + Qei_position_cnt_match_intr_mask + */ + __IOM unsigned int VELOCITY_COMPUTATION_OVER_INTR_MASK : 1; /*!< [5..5] + Velocity_computation_over_intr_mask + */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved1 */ + } QEI_INTR_MASK_REG_b; + }; + + union { + __IOM unsigned int QEI_INTR_UNMASK_REg; /*!< (@ 0x00000034) Quadrature Encoder + interrupt unmask register */ + + struct { + __IOM unsigned int QEI_POSITION_CNT_RESET_INTR_UNMASK : 1; /*!< [0..0] + Qei_position_cnt_reset_intr_unmask + */ + __IOM unsigned int QEI_INDEX_CNT_MATCH_INTR_UNMASK : 1; /*!< [1..1] + Qei_index_cnt_match_intr_unmask + */ + __IOM unsigned int POSITION_CNTR_ERR_INTR_UNMASK : 1; /*!< [2..2] + Position_cntr_err_intr_unmask + */ + __IOM unsigned int VELOCITY_LESS_THAN_INTR_UNMASK : 1; /*!< [3..3] + Velocity_less_than_intr_unmask + */ + __IOM unsigned int QEI_POSITION_CNT_MATCH_INTR_UNMASK : 1; /*!< [4..4] + Qei_position_cnt_match_intr_unmask + */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved1 */ + } QEI_INTR_UNMASK_REg_b; + }; + + union { + __IOM unsigned int QEI_CLK_FREQ_REG; /*!< (@ 0x00000038) Quadrature Encoder + clock frequency register */ + + struct { + __IOM unsigned int QEI_CLK_FREQ : 9; /*!< [8..0] Indication of clock frequency on which + QEI controller is running. */ + __IOM unsigned int RESERVED1 : 23; /*!< [31..9] Reserved1 */ + } QEI_CLK_FREQ_REG_b; + }; + + union { + __IOM unsigned int QEI_DELTA_TIME_REG; /*!< (@ 0x0000003C) Quadrature Delta time + register */ + + struct { + __IOM unsigned int DELTA_TIME_FOR_VELOCITY : 20; /*!< [19..0] Delta time LSW + to compute velocity */ + __IOM unsigned int RESERVED1 : 12; /*!< [31..20] Reserved1 */ + } QEI_DELTA_TIME_REG_b; + }; + __IM unsigned int RESERVED2; + + union { + __IOM unsigned int QEI_VELOCITY_REG; /*!< (@ 0x00000044) Quadrature velocity register */ + + struct { + __IOM unsigned int VELOCITY_VALUE_TO_COMPARE_L : 16; /*!< [15..0] For read operation :It + is the velocity count to compare + using NWP firmware For + write operation :It is the + velocity value to compare with + velocity count */ + __IOM unsigned int VELOCITY_VALUE_TO_COMPARE_H : 16; /*!< [31..16] For read operation :It + is the velocity count to compare + using NWP firmware For + write operation :It is the + velocity value to compare with + velocity count */ + } QEI_VELOCITY_REG_b; + }; + __IM unsigned int RESERVED3; + + union { + __IOM unsigned int QEI_POSITION_MATCH_REG; /*!< (@ 0x0000004C) Quadrature + position match register */ + + struct { + __IOM unsigned int POSTION_MATCH_VALUE_L : 16; /*!< [15..0] Position match value to + compare the position counter. */ + __IOM unsigned int POSTION_MATCH_VALUE_H : 16; /*!< [31..16] Position match value to + compare the position counter. */ + } QEI_POSITION_MATCH_REG_b; + }; +} QEI_Type; /*!< Size = 80 (0x50) */ + +/* =========================================================================================================================== + */ +/* ================ USART0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Universal Asynchronous Receiver/Transmitter is for serial + communication with peripherals, modems and datasets (USART0) + */ + +typedef struct { /*!< (@ 0x44000100) USART0 Structure */ + + union { + union { + __IOM unsigned int DLL; /*!< (@ 0x00000000) Divisor Latch Low */ + + struct { + __IOM unsigned int DLL : 8; /*!< [7..0] Lower 8-bits of a 16-bit, read/write, Divisor + Latch register that contains the baud rate divisor for + the UART. */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } DLL_b; + }; + + union { + __OM unsigned int THR; /*!< (@ 0x00000000) Transmit Holding Register */ + + struct { + __OM unsigned int THR : 8; /*!< [7..0] Data to be transmitted on serial + output port */ + __OM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } THR_b; + }; + + union { + __IM unsigned int RBR; /*!< (@ 0x00000000) Receive Buffer Register */ + + struct { + __IM unsigned int RBR : 8; /*!< [7..0] Receive Buffer Field */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } RBR_b; + }; + }; + + union { + union { + __IOM unsigned int IER; /*!< (@ 0x00000004) Interrupt Enable Register */ + + struct { + __IOM unsigned int ERBFI : 1; /*!< [0..0] Enable Received Data Available Interrupt */ + __IOM unsigned int ETBEI : 1; /*!< [1..1] Enable Transmit Holding Register + Empty Interrupt */ + __IOM unsigned int ELSI : 1; /*!< [2..2] Enable Receiver Line Status Interrupt */ + __IOM unsigned int EDSSI : 1; /*!< [3..3] Enable Modem Status Interrupt */ + __IM unsigned int RESERVED1 : 3; /*!< [6..4] reserved1 */ + __IOM unsigned int PTIME : 1; /*!< [7..7] Programmable THRE Interrupt Mode Enable */ + __IM unsigned int RESERVED2 : 24; /*!< [31..8] reserved2 */ + } IER_b; + }; + + union { + __IOM unsigned int DLH; /*!< (@ 0x00000004) Divisor Latch High */ + + struct { + __IOM unsigned int DLH : 8; /*!< [7..0] Upper 8-bits of a 16-bit, read/write, Divisor + Latch register that contains the baud rate divisor for + the UART */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } DLH_b; + }; + }; + + union { + union { + __OM unsigned int FCR; /*!< (@ 0x00000008) FIFO Control Register */ + + struct { + __OM unsigned int FIFOE : 1; /*!< [0..0] This enables/disables the transmit + (XMIT) and receive (RCVR) FIFOs */ + __OM unsigned int RFIFOR : 1; /*!< [1..1] RCVR FIFO Reset */ + __OM unsigned int XFIFOR : 1; /*!< [2..2] XMIT FIFO Reset */ + __OM unsigned int DMAM : 1; /*!< [3..3] DMA signalling mode */ + __OM unsigned int TET : 2; /*!< [5..4] TX Empty Trigger */ + __OM unsigned int RT : 2; /*!< [7..6] This is used to select the trigger level in the + receiver FIFO at which the Received Data Available + Interrupt is generated */ + __OM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } FCR_b; + }; + + union { + __IM unsigned int IIR; /*!< (@ 0x00000008) Interrupt Identity Register */ + + struct { + __IM unsigned int IID : 4; /*!< [3..0] Interrupt ID */ + __IM unsigned int RESERVED1 : 2; /*!< [5..4] reserved1 */ + __IM unsigned int FIFOSE : 2; /*!< [7..6] This is used to indicate whether + the FIFOs are enabled or disabled. */ + __IM unsigned int RESERVED2 : 24; /*!< [31..8] reserved2 */ + } IIR_b; + }; + }; + + union { + __IOM unsigned int LCR; /*!< (@ 0x0000000C) Line Control Register */ + + struct { + __IOM unsigned int DLS : 2; /*!< [1..0] Data Length Select,This is used to + select the number of data bits per character + that the peripheral transmits and receives */ + __IOM unsigned int STOP : 1; /*!< [2..2] This is used to select the number of + stop bits per character that the peripheral + transmits and receives */ + __IOM unsigned int PEN : 1; /*!< [3..3] This bit is used to enable and disable parity + generation and detection in transmitted and received + serial character */ + __IOM unsigned int EPS : 1; /*!< [4..4] This is used to select between even + and odd parity */ + __IOM unsigned int STICK_PARITY : 1; /*!< [5..5] This bit is used to force + parity value */ + __IOM unsigned int BC : 1; /*!< [6..6] This is used to cause a break condition + to be transmitted to the receiving device */ + __IOM unsigned int DLAB : 1; /*!< [7..7] This bit is used to enable reading + and writing of the Divisor Latch register to + set the baud rate of the UART */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LCR_b; + }; + + union { + __IOM unsigned int MCR; /*!< (@ 0x00000010) Modem Control Register */ + + struct { + __IOM unsigned int DTR : 1; /*!< [0..0] This is used to directly control the + Data Terminal Ready (dtr_n) output */ + __IOM unsigned int RTS : 1; /*!< [1..1] This is used to directly control the + Request to Send (rts_n) output */ + __IOM unsigned int OUT1 : 1; /*!< [2..2] This is used to directly control the + user-designated Output1 (out1_n) output */ + __IOM unsigned int OUT2 : 1; /*!< [3..3] This is used to directly control the + user-designated Output2 (out2_n) output */ + __IOM unsigned int LB : 1; /*!< [4..4] This is used to put the UART into a + diagnostic mode for test purposes */ + __IOM unsigned int AFCE : 1; /*!< [5..5] This is used to directly control the + user-designated Output2 (out2_n) output */ + __IOM unsigned int SIRE : 1; /*!< [6..6] This is used to enable/disable the + IrDA SIR Mode features */ + __IM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */ + } MCR_b; + }; + + union { + __IM unsigned int LSR; /*!< (@ 0x00000014) Line Status Register */ + + struct { + __IM unsigned int DR : 1; /*!< [0..0] This is used to indicate that the + receiver contains at least one character in the + RBR or the receiver FIFO */ + __IM unsigned int OE : 1; /*!< [1..1] This is used to indicate the occurrence + of an overrun error */ + __IM unsigned int PE : 1; /*!< [2..2] This is used to indicate the occurrence + of a parity error in the receiver if the Parity + Enable (PEN) bit (LCR[3]) is set */ + __IM unsigned int FE : 1; /*!< [3..3] This is used to indicate the occurrence + of a framing error in the receiver */ + __IM unsigned int BI : 1; /*!< [4..4] his is used to indicate the detection of + a break sequence on the serial input data */ + __IM unsigned int THRE : 1; /*!< [5..5] Transmit Holding Register Empty bit */ + __IM unsigned int TEMT : 1; /*!< [6..6] Transmitter Empty bit */ + __IM unsigned int RFE : 1; /*!< [7..7] This is used to indicate if there is at + least one parity error,framing error, or break + indication in the FIFO */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LSR_b; + }; + + union { + __IM unsigned int MSR; /*!< (@ 0x00000018) Modem Status Register */ + + struct { + __IM unsigned int DCTS : 1; /*!< [0..0] This is used to indicate that the modem control + line cts_n has changed since the last time the MSR was + read */ + __IM unsigned int DDSR : 1; /*!< [1..1] This is used to indicate that the modem control + line dsr_n has changed since the last time the MSR was + read */ + __IM unsigned int TERI : 1; /*!< [2..2] This is used to indicate that a change on the + input ri_n(from an active-low to an inactive-high state) + has occurred since the last time the MSR was read */ + __IM unsigned int DDCD : 1; /*!< [3..3] This is used to indicate that the modem control + line dcd_n has changed since the last time the MSR was + read */ + __IM unsigned int CTS : 1; /*!< [4..4] This is used to indicate the current + state of the modem control line cts_n */ + __IM unsigned int DSR : 1; /*!< [5..5] This is used to indicate the current + state of the modem control line dsr_n */ + __IM unsigned int RI : 1; /*!< [6..6] This is used to indicate the current + state of the modem control line ri_n */ + __IM unsigned int DCD : 1; /*!< [7..7] This is used to indicate the current + state of the modem control line dcd_n */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } MSR_b; + }; + + union { + __IOM unsigned int SCR; /*!< (@ 0x0000001C) Scratch pad Register */ + + struct { + __IOM unsigned int SCRATCH_PAD : 8; /*!< [7..0] This register is for programmers to use + as a temporary storage space. It has no defined + purpose */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } SCR_b; + }; + + union { + __IOM unsigned int LPDLL; /*!< (@ 0x00000020) Low Power Divisor Latch Low Register */ + + struct { + __IOM unsigned int LOW_POWER_DLL : 8; /*!< [7..0] This register makes up the lower 8-bits + of a 16-bit, read/write, Low Power Divisor Latch + register that contains the baud rate divisor for + the UART, which must give a baud + rate of 115.2K */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LPDLL_b; + }; + + union { + __IOM unsigned int LPDLH; /*!< (@ 0x00000024) Low Power Divisor Latch High Register */ + + struct { + __IOM unsigned int LOW_POWER_DLH : 8; /*!< [7..0] This register makes up the upper 8-bits + of a 16-bit, read/write, Low Power Divisor Latch + register that contains the baud rate divisor for + the UART, which must give a baud + rate of 115200 */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } LPDLH_b; + }; + __IM unsigned int RESERVED[6]; + + union { + __IOM unsigned int HDEN; /*!< (@ 0x00000040) none */ + + struct { + __IOM unsigned int FULL_DUPLEX_MODE : 1; /*!< [0..0] none */ + __IOM unsigned int TX_MODE_RX_MODE : 1; /*!< [1..1] This signal is valid when + full_duplex_mode is disabled */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ + } HDEN_b; + }; + __IM unsigned int RESERVED1[5]; + + union { + __IOM unsigned int SMCR; /*!< (@ 0x00000058) none */ + + struct { + __IOM unsigned int SYNC_MODE : 1; /*!< [0..0] none */ + __IOM unsigned int MST_MODE : 1; /*!< [1..1] none */ + __IOM unsigned int RESERVED1 : 2; /*!< [3..2] reserved1 */ + __IOM unsigned int CONTI_CLK_MODE : 1; /*!< [4..4] none */ + __IOM unsigned int START_STOP_EN : 1; /*!< [5..5] none */ + __IOM unsigned int RESERVED2 : 26; /*!< [31..6] reserved2 */ + } SMCR_b; + }; + __IM unsigned int RESERVED2[5]; + + union { + __IOM unsigned int FAR; /*!< (@ 0x00000070) none */ + + struct { + __IOM unsigned int SYNC_MODE : 1; /*!< [0..0] none */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } FAR_b; + }; + + union { + __IM unsigned int TFR; /*!< (@ 0x00000074) none */ + + struct { + __IM unsigned int TX_FIFO_RD : 8; /*!< [7..0] Transmit FIFO Read */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } TFR_b; + }; + + union { + __IOM unsigned int RFW; /*!< (@ 0x00000078) none */ + + struct { + __IOM unsigned int RFWD : 8; /*!< [7..0] Receive FIFO Write Data */ + __IOM unsigned int RFPE : 1; /*!< [8..8] Receive FIFO Parity Error */ + __IOM unsigned int RFFE : 1; /*!< [9..9] Receive FIFO Framing Error */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ + } RFW_b; + }; + + union { + __IM unsigned int USR; /*!< (@ 0x0000007C) UART Status Register */ + + struct { + __IM unsigned int BUSY : 1; /*!< [0..0] Indicates that a serial transfer is in + progress */ + __IM unsigned int TFNF : 1; /*!< [1..1] To Indicate that the transmit FIFO is + not full */ + __IM unsigned int TFE : 1; /*!< [2..2] To Indicate that the transmit FIFO is + completely empty */ + __IM unsigned int RFNE : 1; /*!< [3..3] To Indicate that the receive FIFO + contains one or more entries */ + __IM unsigned int RFE : 1; /*!< [4..4] To Indicate that the receive FIFO is + completely full */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ + } USR_b; + }; + + union { + __IM unsigned int TFL; /*!< (@ 0x00000080) Transmit FIFO Level */ + + struct { + __IM unsigned int FIFO_ADDR_WIDTH : 30; /*!< [29..0] Transmit FIFO Level. This + is indicates the number of data + entries in the transmit FIFO. */ + __IM unsigned int RESERVED1 : 2; /*!< [31..30] reserved1 */ + } TFL_b; + }; + + union { + __IM unsigned int RFL; /*!< (@ 0x00000084) Receive FIFO Level */ + + struct { + __IM unsigned int FIFO_ADDR_WIDTH : 30; /*!< [29..0] Receive FIFO Level. This + is indicates the number of data + entries in the receive FIFO. */ + __IM unsigned int RESERVED1 : 2; /*!< [31..30] reserved1 */ + } RFL_b; + }; + + union { + __OM unsigned int SRR; /*!< (@ 0x00000088) Software Reset Register */ + + struct { + __OM unsigned int UR : 1; /*!< [0..0] UART Reset */ + __OM unsigned int RFR : 1; /*!< [1..1] RCVR FIFO Reset */ + __OM unsigned int XFR : 1; /*!< [2..2] XMIT FIFO Reset */ + __OM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } SRR_b; + }; + + union { + __IOM unsigned int SRTS; /*!< (@ 0x0000008C) Shadow Request to Send */ + + struct { + __IOM unsigned int SRTS : 1; /*!< [0..0] Shadow Request to Send. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SRTS_b; + }; + + union { + __IOM unsigned int SBCR; /*!< (@ 0x00000090) Shadow Break Control Register */ + + struct { + __IOM unsigned int SBCR : 1; /*!< [0..0] Shadow Break Control Bit */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SBCR_b; + }; + + union { + __IOM unsigned int SDMAM; /*!< (@ 0x00000094) Shadow DMA Mode */ + + struct { + __IOM unsigned int SDMAM : 1; /*!< [0..0] Shadow DMA Mode */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SDMAM_b; + }; + + union { + __IOM unsigned int SFE; /*!< (@ 0x00000098) Shadow FIFO Enable */ + + struct { + __IOM unsigned int SFE : 1; /*!< [0..0] Shadow FIFO Enable */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } SFE_b; + }; + + union { + __IOM unsigned int SRT; /*!< (@ 0x0000009C) Shadow RCVR Trigger */ + + struct { + __IOM unsigned int SRT : 2; /*!< [1..0] Shadow RCVR Trigger */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ + } SRT_b; + }; + + union { + __IOM unsigned int STET; /*!< (@ 0x000000A0) Shadow TX Empty Trigger */ + + struct { + __IOM unsigned int STET : 2; /*!< [1..0] Shadow TX Empty Trigger */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ + } STET_b; + }; + + union { + __IOM unsigned int HTX; /*!< (@ 0x000000A4) Halt Transmit */ + + struct { + __IOM unsigned int HALT_TX : 1; /*!< [0..0] This register is use to halt + transmissions for testing */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } HTX_b; + }; + + union { + __IOM unsigned int DMASA; /*!< (@ 0x000000A8) DMA Software Acknowledge */ + + struct { + __OM unsigned int DMA_SOFTWARE_ACK : 1; /*!< [0..0] This register is use to perform a + DMA software acknowledge + if a transfer needs to be terminated + due to an error condition */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } DMASA_b; + }; + + union { + __IOM unsigned int TCR; /*!< (@ 0x000000AC) Transceiver Control Register. */ + + struct { + __IOM unsigned int RS485_EN : 1; /*!< [0..0] RS485 Transfer Enable. */ + __IOM unsigned int RE_POL : 1; /*!< [1..1] Receiver Enable Polarity. */ + __IOM unsigned int DE_POL : 1; /*!< [2..2] Driver Enable Polarity. */ + __IOM unsigned int XFER_MODE : 2; /*!< [4..3] Transfer Mode. */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ + } TCR_b; + }; + + union { + __IOM unsigned int DE_EN; /*!< (@ 0x000000B0) Driver Output Enable Register. */ + + struct { + __IOM unsigned int DE_EN : 1; /*!< [0..0] DE Enable control. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } DE_EN_b; + }; + + union { + __IOM unsigned int RE_EN; /*!< (@ 0x000000B4) Receiver Output Enable Register. */ + + struct { + __IOM unsigned int RE_EN : 1; /*!< [0..0] RE Enable control. */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } RE_EN_b; + }; + + union { + __IOM unsigned int DET; /*!< (@ 0x000000B8) Driver Output Enable Timing Register. */ + + struct { + __IOM unsigned int DE_ASSERT_TIME : 8; /*!< [7..0] Driver enable assertion time. */ + __IOM unsigned int RES : 8; /*!< [15..8] reserved. */ + __IOM unsigned int DE_DE_ASSERT_TIME : 8; /*!< [23..16] Driver enable + de-assertion time. */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ + } DET_b; + }; + + union { + __IOM unsigned int TAT; /*!< (@ 0x000000BC) TurnAround Timing Register */ + + struct { + __IOM unsigned int DE_RE : 16; /*!< [15..0] Driver Enable to Receiver Enable + TurnAround time. */ + __IOM unsigned int RE_DE : 16; /*!< [31..16] Receiver Enable to Driver Enable + TurnAround time. */ + } TAT_b; + }; + + union { + __IOM unsigned int DLF; /*!< (@ 0x000000C0) Divisor Latch Fraction Register. */ + + struct { + __IOM unsigned int DLF : 6; /*!< [5..0] Fractional part of divisor. */ + __IM unsigned int : 1; + __IM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */ + } DLF_b; + }; + + union { + __IOM unsigned int RAR; /*!< (@ 0x000000C4) Receive Address Register. */ + + struct { + __IOM unsigned int RAR : 8; /*!< [7..0] This is an address matching register + during receive mode. */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } RAR_b; + }; + + union { + __IOM unsigned int TAR; /*!< (@ 0x000000C8) Transmit Address Register. */ + + struct { + __IOM unsigned int TAR : 8; /*!< [7..0] This is an address matching register + during transmit mode. */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } TAR_b; + }; + + union { + __IOM unsigned int LCR_EXT; /*!< (@ 0x000000CC) Line Extended Control Register */ + + struct { + __IOM unsigned int DLS_E : 1; /*!< [0..0] Extension for DLS. */ + __IOM unsigned int ADDR_MATCH : 1; /*!< [1..1] Address Match Mode. */ + __IOM unsigned int SEND_ADDR : 1; /*!< [2..2] Send address control bit. */ + __IOM unsigned int TRANSMIT_MODE : 1; /*!< [3..3] Transmit mode control bit. */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } LCR_EXT_b; + }; + __IM unsigned int RESERVED3[9]; + + union { + __IM unsigned int CPR; /*!< (@ 0x000000F4) Component Parameter Register */ + + struct { + __IM unsigned int APB_DATA_WIDTH : 2; /*!< [1..0] APB data width register. */ + __IM unsigned int RESERVED1 : 2; /*!< [3..2] reserved1 */ + __IM unsigned int AFCE_MODE : 1; /*!< [4..4] none */ + __IM unsigned int THRE_MODE : 1; /*!< [5..5] none */ + __IM unsigned int SIR_MODE : 1; /*!< [6..6] none */ + __IM unsigned int SIR_LP_MODE : 1; /*!< [7..7] none */ + __IM unsigned int ADDITIONAL_FEAT : 1; /*!< [8..8] none */ + __IM unsigned int FIFO_ACCESS : 1; /*!< [9..9] none */ + __IM unsigned int FIFO_STAT : 1; /*!< [10..10] none */ + __IM unsigned int SHADOW : 1; /*!< [11..11] none */ + __IM unsigned int UART_ADD_ENCODED_PARAMS : 1; /*!< [12..12] none */ + __IM unsigned int DMA_EXTRA : 1; /*!< [13..13] none */ + __IM unsigned int RESERVED2 : 2; /*!< [15..14] reserved2 */ + __IM unsigned int FIFO_MODE : 8; /*!< [23..16] none */ + __IM unsigned int RESERVED3 : 8; /*!< [31..24] reserved3 */ + } CPR_b; + }; + + union { + __IM unsigned int UCV; /*!< (@ 0x000000F8) UART Component Version */ + + struct { + __IM unsigned int UART_COMP_VER : 32; /*!< [31..0] ASCII value for each number + in the version, followed by * */ + } UCV_b; + }; + + union { + __IM unsigned int CTR; /*!< (@ 0x000000FC) Component Type Register */ + + struct { + __IM unsigned int UART_COMP_VER : 32; /*!< [31..0] This register contains the + peripherals identification code. */ + } CTR_b; + }; +} USART0_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== + */ +/* ================ GSPI0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief GSPI, or Generic SPI, is a module which has been derived from QSPI. + * GSPI can act only as a master (GSPI0) + */ + +typedef struct { /*!< (@ 0x45030000) GSPI0 Structure */ + + union { + __IOM unsigned int GSPI_CLK_CONFIG; /*!< (@ 0x00000000) GSPI Clock Configuration + Register */ + + struct { + __IOM unsigned int GSPI_CLK_SYNC : 1; /*!< [0..0] If the clock frequency to FLASH + (spi_clk) and SOC clk is same. */ + __IOM unsigned int GSPI_CLK_EN : 1; /*!< [1..1] GSPI clock enable */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved for future use */ + } GSPI_CLK_CONFIG_b; + }; + + union { + __IOM unsigned int GSPI_BUS_MODE; /*!< (@ 0x00000004) GSPI Bus Mode Register */ + + struct { + __IOM unsigned int GSPI_DATA_SAMPLE_EDGE : 1; /*!< [0..0] Samples MISO data on + clock edges. This should be + ZERO for mode3 clock */ + __IOM unsigned int GSPI_CLK_MODE_CSN0 : 1; /*!< [1..1] NONE */ + __IOM unsigned int GSPI_CLK_MODE_CSN1 : 1; /*!< [2..2] NONE */ + __IOM unsigned int GSPI_CLK_MODE_CSN2 : 1; /*!< [3..3] NONE */ + __IOM unsigned int GSPI_CLK_MODE_CSN3 : 1; /*!< [4..4] NONE */ + __IOM unsigned int GSPI_GPIO_MODE_ENABLES : 6; /*!< [10..5] These bits are used to map + GSPI on GPIO pins */ + __IOM unsigned int SPI_HIGH_PERFORMANCE_EN : 1; /*!< [11..11] High performance + features are enabled when + this bit is set to one */ + __IOM unsigned int RESERVED1 : 20; /*!< [31..12] reserved for future use */ + } GSPI_BUS_MODE_b; + }; + __IM unsigned int RESERVED[2]; + + union { + __IOM unsigned int GSPI_CONFIG1; /*!< (@ 0x00000010) GSPI Configuration 1 Register */ + + struct { + __IOM unsigned int GSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ + __IOM unsigned int GSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual + mode when CS is low. */ + __IOM unsigned int GSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode + when CS is low */ + __IOM unsigned int GSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total + number of bytes to be read */ + __IOM unsigned int GSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which CSn is + valid. Can be programmable in manual + mode */ + __IOM unsigned int SPI_FULL_DUPLEX_EN : 1; /*!< [15..15] Full duplex mode enable */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved for future use */ + } GSPI_CONFIG1_b; + }; + + union { + __IOM unsigned int GSPI_CONFIG2; /*!< (@ 0x00000014) GSPI Manual Configuration 2 + Register */ + + struct { + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside + the GSPI controller it-self. */ + __IOM unsigned int GSPI_MANUAL_SIZE_FRM_REG : 1; /*!< [8..8] Manual reads and + manual writes */ + __IOM unsigned int RESERVED1 : 1; /*!< [9..9] reserved for future use */ + __IOM unsigned int TAKE_GSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [10..10] NONE */ + __IOM unsigned int MANUAL_GSPI_MODE : 1; /*!< [11..11] Internally the priority + is given to manual mode */ + __IOM unsigned int RESERVED2 : 20; /*!< [31..12] reserved for future use */ + } GSPI_CONFIG2_b; + }; + + union { + __IOM unsigned int GSPI_WRITE_DATA2; /*!< (@ 0x00000018) GSPI Write Data 2 Register */ + + struct { + __IOM unsigned int GSPI_MANUAL_WRITE_DATA2 : 4; /*!< [3..0] Number of bits to be written + in write mode */ + __IOM unsigned int RESERVED1 : 3; /*!< [6..4] reserved for future use */ + __IOM unsigned int USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length */ + __IOM unsigned int RESERVED2 : 24; /*!< [31..8] reserved for future use */ + } GSPI_WRITE_DATA2_b; + }; + + union { + __IOM unsigned int GSPI_FIFO_THRLD; /*!< (@ 0x0000001C) GSPI FIFO Threshold Register */ + + struct { + __IOM unsigned int FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ + __IOM unsigned int FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ + __IOM unsigned int WFIFO_RESET : 1; /*!< [8..8] Write FIFO reset */ + __IOM unsigned int RFIFO_RESET : 1; /*!< [9..9] read FIFO reset */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved for future use */ + } GSPI_FIFO_THRLD_b; + }; + + union { + __IM unsigned int GSPI_STATUS; /*!< (@ 0x00000020) GSPI Status Register */ + + struct { + __IM unsigned int GSPI_BUSY : 1; /*!< [0..0] State of Manual mode */ + __IM unsigned int FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Full status indication + for Wfifo in manual mode */ + __IM unsigned int FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Almost full status indication for + Wfifo in manual mode */ + __IM unsigned int FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Empty status indication + for Wfifo in manual mode */ + __IM unsigned int RESERVED1 : 1; /*!< [4..4] reserved for future use */ + __IM unsigned int FIFO_FULL_RFIFO : 1; /*!< [5..5] Full status indication for + Rfifo in manual mode */ + __IM unsigned int RESERVED2 : 1; /*!< [6..6] reserved for future use */ + __IM unsigned int FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Empty status indication + for Rfifo in manual mode */ + __IM unsigned int FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Aempty status indication for + Rfifo in manual mode */ + __IM unsigned int GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 + bits ORing counter */ + __IM unsigned int GSPI_MANUAL_CSN : 1; /*!< [10..10] Provide the status of + chip select signal */ + __IM unsigned int RESERVED3 : 21; /*!< [31..11] reserved for future use */ + } GSPI_STATUS_b; + }; + + union { + __IOM unsigned int GSPI_INTR_MASK; /*!< (@ 0x00000024) GSPI Interrupt Mask Register */ + + struct { + __IOM unsigned int GSPI_INTR_MASK : 1; /*!< [0..0] GSPI Interrupt mask bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int RESERVED1 : 25; /*!< [31..7] reserved for future use */ + } GSPI_INTR_MASK_b; + }; + + union { + __IOM unsigned int GSPI_INTR_UNMASK; /*!< (@ 0x00000028) GSPI Interrupt Unmask + Register */ + + struct { + __IOM unsigned int GSPI_INTR_UNMASK : 1; /*!< [0..0] GSPI Interrupt unmask bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_UNMASK : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int RESERVED1 : 25; /*!< [31..7] reserved for future use */ + } GSPI_INTR_UNMASK_b; + }; + + union { + __IM unsigned int GSPI_INTR_STS; /*!< (@ 0x0000002C) GSPI Interrupt Status Register */ + + struct { + __IM unsigned int GSPI_INTR_LVL : 1; /*!< [0..0] GSPI Interrupt status bit */ + __IM unsigned int FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ + __IM unsigned int FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ + __IM unsigned int FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ + __IM unsigned int FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ + __IM unsigned int FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ + __IM unsigned int FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ + __IM unsigned int RESERVED2 : 25; /*!< [31..7] reserved for future use */ + } GSPI_INTR_STS_b; + }; + + union { + __OM unsigned int GSPI_INTR_ACK; /*!< (@ 0x00000030) GSPI Interrupt Acknowledge + Register */ + + struct { + __OM unsigned int GSPI_INTR_ACK : 1; /*!< [0..0] GSPI Interrupt status bit */ + __OM unsigned int FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ + __OM unsigned int FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ + __OM unsigned int FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ + __OM unsigned int FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ + __OM unsigned int FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ + __OM unsigned int FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ + __OM unsigned int RESERVED2 : 25; /*!< [31..7] reserved1 */ + } GSPI_INTR_ACK_b; + }; + + union { + __IM unsigned int GSPI_STS_MC; /*!< (@ 0x00000034) GSPI State Machine Monitor + Register */ + + struct { + __IM unsigned int BUS_CTRL_PSTATE : 3; /*!< [2..0] Provides SPI bus controller + present state */ + __IM unsigned int SPI_RD_CNT : 13; /*!< [15..3] number of pending bytes to be + read by device */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } GSPI_STS_MC_b; + }; + + union { + __IOM unsigned int GSPI_CLK_DIV; /*!< (@ 0x00000038) GSPI Clock Division Factor + Register */ + + struct { + __IOM unsigned int GSPI_CLK_DIV_FACTOR : 8; /*!< [7..0] Provides GSPI clock division + factor to the clock divider, which takes + SOC clock as input clock and generates + required clock according to division + factor */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } GSPI_CLK_DIV_b; + }; + + union { + __IOM unsigned int GSPI_CONFIG3; /*!< (@ 0x0000003C) GSPI Configuration 3 Register */ + + struct { + __IOM unsigned int SPI_MANUAL_RD_LNTH_TO_BC : 15; /*!< [14..0] Bits are used to indicate + the total number of bytes + to read from flash during read + operation */ + __IOM unsigned int RESERVED1 : 17; /*!< [31..15] reserved1 */ + } GSPI_CONFIG3_b; + }; + __IM unsigned int RESERVED1[16]; + + union { + union { + __OM unsigned int GSPI_WRITE_FIFO[16]; /*!< (@ 0x00000080) GSPI fifo */ + + struct { + __OM unsigned int WRITE_FIFO : 32; /*!< [31..0] FIFO data is write to this + address space */ + } GSPI_WRITE_FIFO_b[16]; + }; + + union { + __IM unsigned int GSPI_READ_FIFO[16]; /*!< (@ 0x00000080) GSPI READ FIFO */ + + struct { + __IM unsigned int READ_FIFO : 32; /*!< [31..0] FIFO data is read from this + address space */ + } GSPI_READ_FIFO_b[16]; + }; + }; +} GSPI0_Type; /*!< Size = 192 (0xc0) */ + +/* =========================================================================================================================== + */ +/* ================ SSI0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Synchronous Serial Interface(SSI) (SSI0) + */ + +typedef struct { /*!< (@ 0x44020000) SSI0 Structure */ + + union { + __IOM unsigned int CTRLR0; /*!< (@ 0x00000000) Control Register 0 */ + + struct { + __IOM unsigned int DFS : 4; /*!< [3..0] Select the data frame length (4-bit to + 16-bit serial data transfers) */ + __IOM unsigned int FRF : 2; /*!< [5..4] Frame Format, Selects which serial + protocol transfers the data */ + __IOM unsigned int SCPH : 1; /*!< [6..6] Serial Clock Phase. Valid when the + frame format (FRF) is set to Motorola SPI */ + __IOM unsigned int SCPOL : 1; /*!< [7..7] Serial Clock Polarity. Valid when the frame + format (FRF) is set to Motorola SPI */ + __IOM unsigned int TMOD : 2; /*!< [9..8] Selects the mode of transfer for + serial communication */ + __IOM unsigned int SLV_OE : 1; /*!< [10..10] DW_apb_ssi is configured as a + serial-slave device */ + __IOM unsigned int SRL : 1; /*!< [11..11] Shift Register Loop Used for testing + purposes only */ + __IOM unsigned int CFS : 4; /*!< [15..12] Control Frame Size Selects the length of the + control word for the Micro wire frame format */ + __IOM unsigned int DFS_32 : 5; /*!< [20..16] Selects the data frame length */ + __IOM unsigned int SPI_FRF : 2; /*!< [22..21] Selects data frame format for + transmitting or receiving data */ + __IOM unsigned int RESERVED1 : 9; /*!< [31..23] Reserved for future use */ + } CTRLR0_b; + }; + + union { + __IOM unsigned int CTRLR1; /*!< (@ 0x00000004) Control Register 1 */ + + struct { + __IOM unsigned int NDF : 16; /*!< [15..0] Number of Data Frames.When TMOD = 10 or TMOD = + 11, this register field sets the number of data frames to + be continuously received by the ssi_master */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use. */ + } CTRLR1_b; + }; + + union { + __IOM unsigned int SSIENR; /*!< (@ 0x00000008) SSI Enable Register */ + + struct { + __IOM unsigned int SSI_EN : 1; /*!< [0..0] Enables and disables all ssi operations */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } SSIENR_b; + }; + + union { + __IOM unsigned int MWCR; /*!< (@ 0x0000000C) Micro wire Control Register */ + + struct { + __IOM unsigned int MWMOD : 1; /*!< [0..0] The Micro wire transfer is + sequential or non-sequential */ + __IOM unsigned int MDD : 1; /*!< [1..1] The direction of the data word when + the Micro wire serial protocol is used */ + __IOM unsigned int MHS : 1; /*!< [2..2] Microwire Handshaking. Used to enable + and disable the busy/ready handshaking + interface for the Microwire protocol */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use */ + } MWCR_b; + }; + + union { + __IOM unsigned int SER; /*!< (@ 0x00000010) SLAVE ENABLE REGISTER */ + + struct { + __IOM unsigned int SER : 4; /*!< [3..0] Each bit in this register corresponds to a slave + select line (ss_x_n) from the SSI master. */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } SER_b; + }; + + union { + __IOM unsigned int BAUDR; /*!< (@ 0x00000014) Baud Rate Select Register */ + + struct { + __IOM unsigned int SCKDV : 16; /*!< [15..0] SSI Clock Divider.The LSB for this + field is always set to 0 and is unaffected + by a write operation, which ensures + an even value is held in this + register */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } BAUDR_b; + }; + + union { + __IOM unsigned int TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */ + + struct { + __IOM unsigned int TFT : 4; /*!< [3..0] Controls the level of entries (or below) at which + the transmit FIFO controller triggers an interrupt */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } TXFTLR_b; + }; + + union { + __IOM unsigned int RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level */ + + struct { + __IOM unsigned int RFT : 4; /*!< [3..0] Controls the level of entries (or above) at which + the receive FIFO controller triggers an interrupt */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } RXFTLR_b; + }; + + union { + __IM unsigned int TXFLR; /*!< (@ 0x00000020) Transmit FIFO Level Register */ + + struct { + __IM unsigned int TXTFL : 5; /*!< [4..0] Contains the number of valid data + entries in the transmit FIFO */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } TXFLR_b; + }; + + union { + __IM unsigned int RXFLR; /*!< (@ 0x00000024) Receive FIFO Level Register */ + + struct { + __IM unsigned int RXTFL : 5; /*!< [4..0] Contains the number of valid data + entries in the receive FIFO */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } RXFLR_b; + }; + + union { + __IM unsigned int SR; /*!< (@ 0x00000028) Status Register */ + + struct { + __IM unsigned int BUSY : 1; /*!< [0..0] indicates that a serial transfer is in + progress */ + __IM unsigned int TFNF : 1; /*!< [1..1] Set when the transmit FIFO contains one or more + empty locations and is cleared when the FIFO is full */ + __IM unsigned int TFE : 1; /*!< [2..2] When the transmit FIFO is completely + empty this bit is set */ + __IM unsigned int RFNE : 1; /*!< [3..3] Set when the receive FIFO contains one + or more entries and is cleared when the + receive FIFO is empty */ + __IM unsigned int RFF : 1; /*!< [4..4] When the receive FIFO is completely + full this bit is set */ + __IM unsigned int TXE : 1; /*!< [5..5] This bit is cleared when read */ + __IM unsigned int DCOL : 1; /*!< [6..6] This bit is set if the ss_in_n input + is asserted by another master, while the ssi + master is in the middle of the transfer */ + __IM unsigned int RESERVED1 : 25; /*!< [31..7] Reserved for future use */ + } SR_b; + }; + + union { + __IOM unsigned int IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */ + + struct { + __IOM unsigned int TXEIM : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask */ + __IOM unsigned int TXOIM : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Mask */ + __IOM unsigned int RXUIM : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Mask */ + __IOM unsigned int RXOIM : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask */ + __IOM unsigned int RXFIM : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask */ + __IOM unsigned int MSTIM : 1; /*!< [5..5] Multi-Master Contention Interrupt Mask */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } IMR_b; + }; + + union { + __IM unsigned int ISR; /*!< (@ 0x00000030) Interrupt Status Register */ + + struct { + __IM unsigned int TXEIS : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Status */ + __IM unsigned int TXOIS : 1; /*!< [1..1] Transmit FIFO Overflow Interrupt Status */ + __IM unsigned int RXUIS : 1; /*!< [2..2] Receive FIFO Underflow Interrupt Status */ + __IM unsigned int RXOIS : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Status */ + __IM unsigned int RXFIS : 1; /*!< [4..4] Receive FIFO Full Interrupt Status */ + __IM unsigned int MSTIS : 1; /*!< [5..5] Multi-Master Contention Interrupt Status */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } ISR_b; + }; + + union { + __IM unsigned int RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ + + struct { + __IM unsigned int TXEIR : 1; /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */ + __IM unsigned int TXOIR : 1; /*!< [1..1] Transmit FIFO Overflow Raw Interrupt + Status */ + __IM unsigned int RXUIR : 1; /*!< [2..2] Receive FIFO Underflow Raw Interrupt + Status */ + __IM unsigned int RXOIR : 1; /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */ + __IM unsigned int RXFIR : 1; /*!< [4..4] Receive FIFO Full Raw Interrupt Status */ + __IM unsigned int MSTIR : 1; /*!< [5..5] Multi-Master Contention Raw Interrupt + Status */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } RISR_b; + }; + + union { + __IM unsigned int TXOICR; /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt + Clear Register */ + + struct { + __IM unsigned int TXOICR : 1; /*!< [0..0] Clear Transmit FIFO Overflow Interrupt This + register reflects the status of the interrupt */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } TXOICR_b; + }; + + union { + __IM unsigned int RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt + Clear Register */ + + struct { + __IM unsigned int RXOICR : 1; /*!< [0..0] This register reflects the status of + the interrupt A read from this register + clears the ssi_rxo_intr interrupt */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } RXOICR_b; + }; + + union { + __IM unsigned int RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt + Clear Register */ + + struct { + __IM unsigned int RXUICR : 1; /*!< [0..0] This register reflects the status of + the interrupt A read from this register + clears the ssi_rxu_intr interrupt */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } RXUICR_b; + }; + + union { + __IM unsigned int MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */ + + struct { + __IM unsigned int MSTICR : 1; /*!< [0..0] This register reflects the status of + the interrupt A read from this register + clears the ssi_mst_intr interrupt */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } MSTICR_b; + }; + + union { + __IM unsigned int ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ + + struct { + __IM unsigned int ICR : 1; /*!< [0..0] This register is set if any of the + interrupts below are active A read clears the + ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and + the ssi_mst_intr interrupts */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } ICR_b; + }; + + union { + __IOM unsigned int DMACR; /*!< (@ 0x0000004C) DMA Control Register */ + + struct { + __IOM unsigned int RDMAE : 1; /*!< [0..0] This bit enables/disables the + receive FIFO DMA channel */ + __IOM unsigned int TDMAE : 1; /*!< [1..1] This bit enables/disables the + transmit FIFO DMA channel */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved for future use */ + } DMACR_b; + }; + + union { + __IOM unsigned int DMATDLR; /*!< (@ 0x00000050) DMA Transmit Data Level */ + + struct { + __IOM unsigned int DMATDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the transmit logic */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } DMATDLR_b; + }; + + union { + __IOM unsigned int DMARDLR; /*!< (@ 0x00000054) DMA Receive Data Level Register */ + + struct { + __IOM unsigned int DMARDL : 4; /*!< [3..0] This bit field controls the level at which a + DMA request is made by the receive logic */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved for future use */ + } DMARDLR_b; + }; + + union { + __IM unsigned int IDR; /*!< (@ 0x00000058) Identification Register */ + + struct { + __IM unsigned int IDCODE : 32; /*!< [31..0] This register contains the + peripherals identification code */ + } IDR_b; + }; + + union { + __IM unsigned int SSI_COMP_VERSION; /*!< (@ 0x0000005C) coreKit version ID register */ + + struct { + __IM unsigned int SSI_COMP_VERSION : 32; /*!< [31..0] Contains the hex representation of + the Synopsys component version */ + } SSI_COMP_VERSION_b; + }; + + union { + __IOM unsigned int DR; /*!< (@ 0x00000060) Data Register */ + + struct { + __IOM unsigned int DR : 32; /*!< [31..0] When writing to this register must + right-justify the data */ + } DR_b; + }; + __IM unsigned int RESERVED[35]; + + union { + __IOM unsigned int RX_SAMPLE_DLY; /*!< (@ 0x000000F0) Rx Sample Delay Register */ + + struct { + __IOM unsigned int RSD : 8; /*!< [7..0] Receive Data (rxd) Sample Delay. This register is + used to delay the sample of the rxd input signal. */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved for future use */ + } RX_SAMPLE_DLY_b; + }; + + union { + __IOM unsigned int SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control Register */ + + struct { + __IOM unsigned int TRANS_TYPE : 2; /*!< [1..0] Address and instruction + transfer format */ + __IOM unsigned int ADDR_L : 4; /*!< [5..2] This bit defines length of address to be + transmitted, The transfer begins only after these many + bits are programmed into the FIFO */ + __IM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved for future use */ + __IOM unsigned int INST_L : 2; /*!< [9..8] DUAL/QUAD length in bits */ + __IM unsigned int RESERVED2 : 1; /*!< [10..10] Reserved for future use */ + __IOM unsigned int WAIT_CYCLES : 4; /*!< [14..11] This bit defines the wait cycles in + dual/quad mode between control frames transmit and + data reception, Specified as number of SPI clock + cycles */ + __IM unsigned int RESERVED3 : 17; /*!< [31..15] Reserved for future use */ + } SPI_CTRLR0_b; + }; +} SSI0_Type; /*!< Size = 248 (0xf8) */ + +/* =========================================================================================================================== + */ +/* ================ SIO + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief SERIAL GENERAL PERPOSE INPUT/OUTPUT (SIO) + */ + +typedef struct { /*!< (@ 0x47000000) SIO Structure */ + + union { + __IOM unsigned int SIO_ENABLE_REG; /*!< (@ 0x00000000) ENABLE REGISTER */ + + struct { + __IOM unsigned int SIO_OPERATION_ENABLE : 16; /*!< [15..0] Contains the + Enables for all SIO */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_ENABLE_REG_b; + }; + + union { + __IOM unsigned int SIO_PAUSE_REG; /*!< (@ 0x00000004) PAUSE REGISTER */ + + struct { + __IOM unsigned int SIO_POSITION_COUNTER_DISABLE : 16; /*!< [15..0] Contains + sio position counter + disable for all SIOs + */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PAUSE_REG_b; + }; + + union { + __IM unsigned int SIO_GPIO_IN_REG; /*!< (@ 0x00000008) GPIO Input Register */ + + struct { + __IM unsigned int IN_VALUE : 32; /*!< [31..0] GPIO input pin status */ + } SIO_GPIO_IN_REG_b; + }; + + union { + __IOM unsigned int SIO_GPIO_OUT_REG; /*!< (@ 0x0000000C) GPIO Output Register */ + + struct { + __IOM unsigned int OUT_VALUE : 32; /*!< [31..0] Value to be loaded on GPIO out pins */ + } SIO_GPIO_OUT_REG_b; + }; + + union { + __IOM unsigned int SIO_GPIO_OEN_REG; /*!< (@ 0x00000010) GPIO Output enable Register */ + + struct { + __IOM unsigned int OEN_VALUE : 32; /*!< [31..0] OEN for the GPIO pins */ + } SIO_GPIO_OEN_REG_b; + }; + + union { + __IOM unsigned int SIO_GPIO_INTR_EN_SET_REG; /*!< (@ 0x00000014) GPIO Interrupt + Enable Set Register */ + + struct { + __OM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] gpio interrupt enable set + register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_EN_SET_REG_b; + }; + + union { + __OM unsigned int SIO_GPIO_INTR_EN_CLEAR_REG; /*!< (@ 0x00000018) GPIO Interrupt + Enable Clear Register */ + + struct { + __OM unsigned int INTR_ENABLE_CLEAR : 16; /*!< [15..0] gpio interrupt enable + Clear register for all SIOs */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_GPIO_INTR_MASK_SET_REG; /*!< (@ 0x0000001C) GPIO Interrupt Enable + Clear Register */ + + struct { + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt mask + set register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_MASK_SET_REG_b; + }; + + union { + __OM unsigned int SIO_GPIO_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000020) GPIO Interrupt Enable + Clear Register */ + + struct { + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] gpio interrupt mask clear + register for all SIOs */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_GPIO_INTR_STATUS_REG; /*!< (@ 0x00000024) GPIO Interrupt + Status Register */ + + struct { + __OM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common gpio interrupt + status register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_GPIO_INTR_STATUS_REG_b; + }; + + union { + __IM unsigned int SIO_SHIFT_COUNTER[16]; /*!< (@ 0x00000028) Shift counter register */ + + struct { + __IM unsigned int SHIFT_COUNTER : 14; /*!< [13..0] shift counter current value */ + __IM unsigned int RESERVED1 : 18; /*!< [31..14] Reserved for future use */ + } SIO_SHIFT_COUNTER_b[16]; + }; + + union { + __IOM unsigned int SIO_BUFFER_REG[16]; /*!< (@ 0x00000068) Buffer Register */ + + struct { + __IOM unsigned int DATA : 32; /*!< [31..0] Data to load into the shift register */ + } SIO_BUFFER_REG_b[16]; + }; + + union { + __IOM unsigned int SIO_SHIFT_COUNT_PRELOAD_REG[16]; /*!< (@ 0x000000A8) Shift counter + Reload Register */ + + struct { + __IOM unsigned int RELOAD_VALUE : 14; /*!< [13..0] division factor required to + generate shift clock */ + __IM unsigned int RESERVED1 : 1; /*!< [14..14] Reserved for future use */ + __IOM unsigned int REVERSE_LOAD : 1; /*!< [15..15] When set, the data on APB is loaded to + buffer is reverse order */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_COUNT_PRELOAD_REG_b[16]; + }; + + union { + __IOM unsigned int SIO_DATA_POS_COUNT_REG[16]; /*!< (@ 0x000000E8) Data Position + Counter Register */ + + struct { + __IOM unsigned int RELOAD_VALUE : 8; /*!< [7..0] No. of shifts to happen before reloading + the shift register with data/ pausing the + operation */ + __IOM unsigned int POSITION_COUNTER : 8; /*!< [15..8] The position counter can + be loaded via AHB */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_DATA_POS_COUNT_REG_b[16]; + }; + + union { + __IOM unsigned int SIO_CONFIG_REG[16]; /*!< (@ 0x00000128) Configuration Register */ + + struct { + __IOM unsigned int FULL_ENABLE : 1; /*!< [0..0] When set, fifo full indication would be + asserted when internal buffer is full */ + __IOM unsigned int EMPTY_ENABLE : 1; /*!< [1..1] When set, fifo full indication would be + asserted when internal buffer is empty */ + __IOM unsigned int EDGE_SEL : 1; /*!< [2..2] edge selection */ + __IOM unsigned int CLK_SEL : 1; /*!< [3..3] clock selection */ + __IOM unsigned int IGNORE_FIRST_SHIFT_CONDITION : 1; /*!< [4..4] data shift + condition */ + __IOM unsigned int FLOW_CONTROL_ENABLED : 1; /*!< [5..5] flow control */ + __IOM unsigned int PATTERN_MATCH_ENABLE : 1; /*!< [6..6] pattern match */ + __IOM unsigned int QUALIFIER_MODE : 1; /*!< [7..7] qualifier mode */ + __IOM unsigned int QUALIFY_CLOCK : 1; /*!< [8..8] qualify clock */ + __IOM unsigned int INVERT_CLOCK : 1; /*!< [9..9] invert clock */ + __IOM unsigned int PARALLEL_MODE : 2; /*!< [11..10] No. of bits to + shift/capture at valid clk edge */ + __IOM unsigned int PIN_DETECTION_MODE : 2; /*!< [13..12] Pin mode to be considered for + gpio interrupt */ + __IOM unsigned int SET_CLK_OUT : 1; /*!< [14..14] When high sets the sio clock_out port. + This is used only when sio is not enabled */ + __IOM unsigned int RESET_CLK_OUT : 1; /*!< [15..15] When high resets the sio + clock_out port. This is used only + when sio is not enabled */ + __IOM unsigned int LOAD_DATA_POS_CNTR_VIA_APB : 1; /*!< [16..16] When set, data position + counter can be loaded via APB */ + __IM unsigned int RESERVED1 : 15; /*!< [31..17] Reserved for future use */ + } SIO_CONFIG_REG_b[16]; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_0; /*!< (@ 0x00000168) Pattern Match + Mask Register 0 */ + + struct { + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_0_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_1; /*!< (@ 0x0000016C) Pattern Match + Mask Register Slice 1 */ + + struct { + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_1_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_2; /*!< (@ 0x00000170) Pattern Match + Mask Register Slice 2 */ + + struct { + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_2_b; + }; + __IM unsigned int RESERVED[5]; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_8; /*!< (@ 0x00000188) Pattern Match + Mask Register Slice 8 */ + + struct { + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_8_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_9; /*!< (@ 0x0000018C) Pattern Match + Mask Register Slice 9 */ + + struct { + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_9_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_MASK_REG_SLICE_10; /*!< (@ 0x00000190) Pattern Match + Mask Register Slice 10 */ + + struct { + __IOM unsigned int MATCH_MASK_LOWER16_BITS : 32; /*!< [31..0] Enable for lower + 16 bits */ + } SIO_PATTERN_MATCH_MASK_REG_SLICE_10_b; + }; + __IM unsigned int RESERVED1[5]; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_0; /*!< (@ 0x000001A8) Pattern Match Mask + Register Slice 0 */ + + struct { + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_0_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_1; /*!< (@ 0x000001AC) Pattern Match Mask + Register Slice 1 */ + + struct { + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_1_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_2; /*!< (@ 0x000001B0) Pattern Match Mask + Register Slice 2 */ + + struct { + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16-bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_2_b; + }; + __IM unsigned int RESERVED2[5]; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_8; /*!< (@ 0x000001C8) Pattern Match Mask + Register Slice 8 */ + + struct { + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_8_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_9; /*!< (@ 0x000001CC) Pattern Match Mask + Register Slice 9 */ + + struct { + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_9_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_REG_SLICE_10; /*!< (@ 0x000001D0) Pattern Match Mask + Register Slice 10 */ + + struct { + __IOM unsigned int PATTERN_MATCH_LOWER16_BITS : 32; /*!< [31..0] Lower 16 bits of pattern + to be detected */ + } SIO_PATTERN_MATCH_REG_SLICE_10_b; + }; + __IM unsigned int RESERVED3[7]; + + union { + __IOM unsigned int SIO_SHIFT_INTR_EN_SET_REG; /*!< (@ 0x000001F0) Shift Interrupt Enable + Set Register */ + + struct { + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt enable set + register for all SIOs */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_EN_SET_REG_b; + }; + + union { + __OM unsigned int SIO_SHIFT_INTR_EN_CLEAR_REG; /*!< (@ 0x000001F4) Shift Interrupt Enable + Clear Register */ + + struct { + __OM unsigned int INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common shift interrupt enable + Clear register for all SIOs */ + __OM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_SHIFT_INTR_MASK_SET_REG; /*!< (@ 0x000001F8) Shift Interrupt Mask + Set Register */ + + struct { + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common shift interrupt enable Set + register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_MASK_SET_REG_b; + }; + + union { + __OM unsigned int SIO_SHIFT_INTR_MASK_CLEAR_REG; /*!< (@ 0x000001FC) Shift Interrupt Mask + Clear Register */ + + struct { + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common shift interrupt mask clear + register for all SIOs */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_SHIFT_INTR_STATUS_REG; /*!< (@ 0x00000200) Shift + Interrupt Status Register */ + + struct { + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common shift interrupt mask clear + register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SHIFT_INTR_STATUS_REG_b; + }; + + union { + __IOM unsigned int SIO_SWAP_INTR_EN_SET_REG; /*!< (@ 0x00000204) Swap Interrupt + Enable Set Register */ + + struct { + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Swap interrupt enable + set register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_EN_SET_REG_b; + }; + + union { + __OM unsigned int SIO_SWAP_INTR_EN_CLEAR_REG; /*!< (@ 0x00000208) Swap Interrupt + Enable Clear Register */ + + struct { + __OM unsigned int INTR_ENABLE_CLEAR : 16; /*!< [15..0] Swap interrupt enable + Clear register for all SIOs */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_SWAP_INTR_MASK_SET_REG; /*!< (@ 0x0000020C) Swap Interrupt Mask Set + Register */ + + struct { + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common swap interrupt mask + set register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_MASK_SET_REG_b; + }; + + union { + __OM unsigned int SIO_SWAP_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000210) Swap Interrupt Mask + Clear Register */ + + struct { + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common swap interrupt mask Clear + register for all SIOs */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_SWAP_INTR_STATUS_REG; /*!< (@ 0x00000214) Swap Interrupt + Statusr Register */ + + struct { + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common swap interrupt + status register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_SWAP_INTR_STATUS_REG_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_INTR_EN_SET_REG; /*!< (@ 0x00000218) Pattern Match + Interrupt Enable Set Register */ + + struct { + __IOM unsigned int INTR_ENABLE_SET : 16; /*!< [15..0] Common pattern or buffer under run + interrupt enable set register for all SIOs. + Each bit corresponds to one SIO */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_EN_SET_REG_b; + }; + + union { + __OM unsigned int SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG; /*!< (@ 0x0000021C) Pattern Match + Interrupt Enable Clear Register + */ + + struct { + __OM unsigned int INRT_ENABLE_CLEAR : 16; /*!< [15..0] Common pattern or buffer under + run interrupt enable + clear register for all SIOs */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_EN_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_INTR_MASK_SET_REG; /*!< (@ 0x00000220) Pattern Match + Interrupt Mask Set Register */ + + struct { + __IOM unsigned int INTR_MASK_SET : 16; /*!< [15..0] Common pattern or buffer under run + interrupt mask set register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_MASK_SET_REG_b; + }; + + union { + __OM unsigned int SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG; /*!< (@ 0x00000224) Pattern Match + Interrupt Mask Clear Register + */ + + struct { + __OM unsigned int INTR_MASK_CLEAR : 16; /*!< [15..0] Common pattern or buffer + under run interrupt mask clear + register for all SIOs */ + __OM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_MASK_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SIO_PATTERN_MATCH_INTR_STATUS_REG; /*!< (@ 0x00000228) Pattern Match + Interrupt Status Register */ + + struct { + __IOM unsigned int INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt + status register for all SIOs */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved for future use */ + } SIO_PATTERN_MATCH_INTR_STATUS_REG_b; + }; + + union { + __IOM unsigned int SIO_BUFFER_INTR_STATUS_REG; /*!< (@ 0x0000022C) Buffer + Interrupt Status Register */ + + struct { + __IOM unsigned int INTR_STATUS : 16; /*!< [15..0] Common pattern interrupt + status register for all SIOs */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved for future use */ + } SIO_BUFFER_INTR_STATUS_REG_b; + }; + + union { + __IOM unsigned int SIO_OUT_MUX_REG[16]; /*!< (@ 0x00000230) Output muxing Register */ + + struct { + __IOM unsigned int DOUT_OEN_SEL : 3; /*!< [2..0] OEN select for GPIO pin 0 */ + __IOM unsigned int DOUT_SEL : 3; /*!< [5..3] Output mux select for GPIO pin 0 */ + __IM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } SIO_OUT_MUX_REG_b[16]; + }; + + union { + __IOM unsigned int SIO_INPUT_MUX_REG[16]; /*!< (@ 0x00000270) Input muxing Register */ + + struct { + __IOM unsigned int CLK_SEL : 3; /*!< [2..0] Input clock select for SIO 0 */ + __IOM unsigned int QUALIFIER_SELECT : 2; /*!< [4..3] qualifier select */ + __IOM unsigned int QUALIFIER_MODE : 2; /*!< [6..5] qualifier mode */ + __IOM unsigned int DIN_SEL : 3; /*!< [9..7] Data in mux select */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved for future use */ + } SIO_INPUT_MUX_REG_b[16]; + }; + + union { + __IOM unsigned int SIO_FIFO_WR_RD_REG; /*!< (@ 0x000002B0) FIFO READ/WRITE Register */ + + struct { + __IOM unsigned int FIFO_DATA_REGISTER : 32; /*!< [31..0] Writes and read into + this register will be written + into SIO buffer register */ + } SIO_FIFO_WR_RD_REG_b; + }; + + union { + __IOM unsigned int SIO_FIFO_WR_OFFSET_START_REG; /*!< (@ 0x000002B4) Points to start slice + number forming the FIFO */ + + struct { + __IOM unsigned int SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number + forming the FIFO,On write, + FIFO_WR_OFFSET_CNT_REG will also be + reset to the value pointed written + into this register */ + } SIO_FIFO_WR_OFFSET_START_REG_b; + }; + + union { + __IOM unsigned int SIO_FIFO_WR_OFFSET_END_REG; /*!< (@ 0x000002B8) SIO last slice no + indication Register */ + + struct { + __IOM unsigned int SIO_END_SLICE_NUMBER : 32; /*!< [31..0] points to last + slice no forming fifo */ + } SIO_FIFO_WR_OFFSET_END_REG_b; + }; + + union { + __IOM unsigned int SIO_FIFO_WR_OFFSET_CNT_REG; /*!< (@ 0x000002BC) Points to current slice + number forming the FIFO */ + + struct { + __IOM unsigned int SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will + happen to buffer in the slice + pointed by this register */ + } SIO_FIFO_WR_OFFSET_CNT_REG_b; + }; + + union { + __IOM unsigned int SIO_FIFO_RD_OFFSET_START_REG; /*!< (@ 0x000002C0) Points to start slice + number forming the FIFO */ + + struct { + __IOM unsigned int SIO_START_SLICE_NUMBER : 32; /*!< [31..0] Points to start slice number + forming the FIFO */ + } SIO_FIFO_RD_OFFSET_START_REG_b; + }; + + union { + __IOM unsigned int SIO_FIFO_RD_OFFSET_END_REG; /*!< (@ 0x000002C4) Points to last slice + number forming the FIFO */ + + struct { + __IOM unsigned int SIO_END_SLICE_NUMBER : 32; /*!< [31..0] Points to last slice number + forming the FIFO */ + } SIO_FIFO_RD_OFFSET_END_REG_b; + }; + + union { + __IOM unsigned int SIO_FIFO_RD_OFFSET_CNT_REG; /*!< (@ 0x000002C8) Points to start current + number forming the FIFO */ + + struct { + __IOM unsigned int SIO_CURRENT_SLICE_NUMBER : 32; /*!< [31..0] Next FIFO operation will + happen to buffer in the slice pointed + by this register This register has to + be set to zero before starting fresh + DMA operation */ + } SIO_FIFO_RD_OFFSET_CNT_REG_b; + }; +} SIO_Type; /*!< Size = 716 (0x2cc) */ + +/* =========================================================================================================================== + */ +/* ================ QSPI + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The queued serial peripheral interface module provides a serial + * peripheral interface with queued transfer capability (QSPI) + */ + +typedef struct { /*!< (@ 0x12000000) QSPI Structure */ + + union { + __IOM unsigned int QSPI_CLK_CONFIG; /*!< (@ 0x00000000) QSPI Clock Configuration + Register */ + + struct { + __IOM unsigned int QSPI_AUTO_CSN_HIGH_CNT : 5; /*!< [4..0] Minimum SOC clock cycles, + during which QSPI auto csn should be + high between consecutive CSN assertions + */ + __IOM unsigned int QSPI_CLK_SYNC : 1; /*!< [5..5] If the clock frequency to + FLASH(spi_clk) and QSPI(hclk) controller is + same, this bit can be set to one to by-pass + the syncros results in time consumption */ + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] reserved1 */ + __IOM unsigned int QSPI_CLK_EN : 1; /*!< [8..8] QSPI clock enable */ + __IOM unsigned int RESERVED2 : 3; /*!< [11..9] reserved2 */ + __IOM unsigned int SPI_CLK_DELAY_VAL : 6; /*!< [17..12] Delay value programmed to RX QSPI + DLL on read side. This delay is used to + delay the pad clock/DQS according to the + requirement */ + __IOM unsigned int OCTA_MODE_ENABLE_WITH_DQS : 1; /*!< [18..18] Enables SPI octa mode + along with DQS in DDR mode */ + __IOM unsigned int QSPI_DLL_ENABLE : 1; /*!< [19..19] Enable for RX QSPI DLL in read + mode.This is used in M4SS QSPI DDR pads to + delay the pad clock DQS input */ + __IOM unsigned int DDR_CLK_POLARITY_FROM_REG : 1; /*!< [20..20] Used this bit to sample + the data at posedge negedge after + interface FFs with internal qspi clock + 0-Sample at negedge 1-Sample at + posedge */ + __IOM unsigned int QSPI_DLL_ENABLE_TX : 1; /*!< [21..21] Enable for TX QSPI DLL in write + path. This is used in M4SS QSPI DDR pads to + delay the qspi clock output. 0–DLL is + disabled bypassed 1–DLL is enabled */ + __IOM unsigned int SPI_CLK_DELAY_VAL_TX : 6; /*!< [27..22] Delay value programmed to TX + QSPI DLL in write path. This delay is used + to delay the qspi clock output according + to the requirement */ + __IOM unsigned int QSPI_RX_DQS_DLL_CALIB : 1; /*!< [28..28] Delay value programmed to TX + QSPI DLL in write path. This delay is used + to delay the qspi clock output according + to the requirement */ + __IOM unsigned int RESERVED3 : 3; /*!< [31..29] reserved3 */ + } QSPI_CLK_CONFIG_b; + }; + + union { + __IOM unsigned int QSPI_BUS_MODE; /*!< (@ 0x00000004) QSPI Bus Mode Register */ + + struct { + __IOM unsigned int QSPI_9116_FEATURE_EN : 1; /*!< [0..0] 9115 specific features are + enabled with this enable */ + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN0 : 2; /*!< [2..1] Configures the QSPI flash for + Single/Dual/Quad mode operation in + manual mode */ + __IOM unsigned int AUTO_MODE_RESET : 1; /*!< [3..3] QSPI Auto controller reset. This is + not a Self clearing bit */ + __IOM unsigned int QSPI_PREFETCH_EN : 1; /*!< [4..4] Pre-fetch of data from the model + which is connected to QSPI, automatically + with out reading on AHB and is supplied to + AHB, when address is matched with AHB read + transaction address */ + __IOM unsigned int QSPI_WRAP_EN : 1; /*!< [5..5] Model wrap is considered with this bit + and uses wrap instruction to read from FLASH */ + __IOM unsigned int QSPI_AUTO_MODE_FRM_REG : 1; /*!< [6..6] QSPI Mode of Operation */ + __IOM unsigned int PROGRAMMABLE_AUTO_CSN_BASE_ADDR_EN : 1; /*!< [7..7] Programmable auto + csn mode enable */ + __IOM unsigned int QSPI_D2_OEN_CSN0 : 1; /*!< [8..8] Direction Control for SPI_IO2 in + case of dual/single mode for chip select0 + csn0. It is used both in Auto and + Manual Mode */ + __IOM unsigned int QSPI_D3_OEN_CSN0 : 1; /*!< [9..9] Direction Control for SPI_IO3 in + case of dual/single mode for chip select0 + csn0. It is used both in Auto and Manual + Mode. */ + __IOM unsigned int QSPI_D2_DATA_CSN0 : 1; /*!< [10..10] Value of SPI_IO2 in case of + dual/single mode for chip select0 csn0. It + is used both in Auto and Manual Mode. */ + __IOM unsigned int QSPI_D3_DATA_CSN0 : 1; /*!< [11..11] Value of SPI_IO3 in case of + dual/single mode for chip select0 csn0. It + is used both in Auto and Manual Mode */ + __IOM unsigned int QSPI_D2_OEN_CSN1 : 1; /*!< [12..12] Direction Control for + SPI_IO2 in case of dual/single + mode for chip select1 csn1 */ + __IOM unsigned int QSPI_D3_OEN_CSN1 : 1; /*!< [13..13] Direction Control for + SPI_IO3 in case of dual/single + mode for chip select1 csn1 */ + __IOM unsigned int QSPI_D2_DATA_CSN1 : 1; /*!< [14..14] Direction Control for + SPI_IO3 in case of dual/single + mode for chip select1 csn1 */ + __IOM unsigned int QSPI_D3_DATA_CSN1 : 1; /*!< [15..15] Value of SPI_IO3 in case of + dual/single mode for chip select1 csn1 */ + __IOM unsigned int QSPI_DATA_SAMPLE_EDGE : 1; /*!< [16..16] Samples MISO data + on clock edges */ + __IOM unsigned int QSPI_CLK_MODE_CSN0 : 1; /*!< [17..17] QSPI Clock Mode */ + __IOM unsigned int QSPI_CLK_MODE_CSN1 : 1; /*!< [18..18] QSPI Clock Mode */ + __IOM unsigned int QSPI_CLK_MODE_CSN2 : 1; /*!< [19..19] QSPI Clock Mode */ + __IOM unsigned int QSPI_CLK_MODE_CSN3 : 1; /*!< [20..20] QSPI Clock Mode */ + __IOM unsigned int FLASH_AW_FIFO_LS_EN : 1; /*!< [21..21] Qspi flash auto write fifo + light sleep enable */ + __IOM unsigned int FLASH_SEC_AES_LS_EN : 1; /*!< [22..22] Qspi flash auto write fifo + light sleep enable */ + __IOM unsigned int RESERVED1 : 1; /*!< [23..23] reserved1 */ + __IOM unsigned int QSPI_D2_OEN_CSN2 : 1; /*!< [24..24] Direction Control for SPI_IO2 in + case of dual/single mode for chip select2 + csn2 */ + __IOM unsigned int QSPI_D3_OEN_CSN2 : 1; /*!< [25..25] Direction Control for SPI_IO3 in + case of dual/single mode for chip select2 + csn2 */ + __IOM unsigned int QSPI_D2_DATA_CSN2 : 1; /*!< [26..26] Value of SPI_IO2 in case of + dual/single mode for chip select2 csn2 */ + __IOM unsigned int QSPI_D3_DATA_CSN2 : 1; /*!< [27..27] Value of SPI_IO3 in case of + dual/single mode for chip select2 csn2 */ + __IOM unsigned int QSPI_D2_OEN_CSN3 : 1; /*!< [28..28] Direction Control for SPI_IO2 in + case of dual/single mode for chip select3 + csn3 */ + __IOM unsigned int QSPI_D3_OEN_CSN3 : 1; /*!< [29..29] Direction Control for SPI_IO3 in + case of dual/single mode for chip select3 + csn3 */ + __IOM unsigned int QSPI_D2_DATA_CSN3 : 1; /*!< [30..30] Value of SPI_IO2 in case of + dual/single mode for chip select3 csn3 */ + __IOM unsigned int QSPI_D3_DATA_CSN3 : 1; /*!< [31..31] Value of SPI_IO3 in case of + dual/single mode for chip select3 csn3 */ + } QSPI_BUS_MODE_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_CONFIG_1; /*!< (@ 0x00000008) QSPI Auto Controller + Configuration 1 Register */ + + struct { + __IOM unsigned int QSPI_EXT_BYTE_MODE_CSN0 : 2; /*!< [1..0] Mode of operation of QSPI in + the extra byte phase */ + __IOM unsigned int QSPI_DUMMY_MODE_CSN0 : 2; /*!< [3..2] Mode of operation of + QSPI in instruction phase */ + __IOM unsigned int QSPI_ADDR_MODE_CSN0 : 2; /*!< [5..4] Mode of operation of + QSPI in instruction phase */ + __IOM unsigned int QSPI_CMD_MODE_CSN0 : 2; /*!< [7..6] Mode of operation of + QSPI in instruction phase */ + __IOM unsigned int QSPI_DATA_MODE_CSN0 : 2; /*!< [9..8] Mode of operation of + QSPI in DATA phase */ + __IOM unsigned int QSPI_EXTRA_BYTE_CSN0 : 8; /*!< [17..10] Value of the extra byte to be + transmitted, if the extra byte mode is + enabled */ + __IOM unsigned int QSPI_EXTRA_BYTE_EN_CSN0 : 2; /*!< [19..18] Value of the extra byte to + be transmitted, if the extra + byte mode is enabled */ + __IOM unsigned int QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ + __IOM unsigned int RESERVED1 : 1; /*!< [22..22] reserved1 */ + __IOM unsigned int QSPI_PG_JUMP_CSN0 : 1; /*!< [23..23] NONE */ + __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [27..24] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode */ + __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [31..28] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction + */ + } QSPI_AUTO_CONFIG_1_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_CONFIG_2; /*!< (@ 0x0000000C) QSPI Auto Controller + Configuration 2 Register */ + + struct { + __IOM unsigned int QSPI_RD_DATA_SWAP_AUTO_CSN0 : 1; /*!< [0..0] NONE */ + __IOM unsigned int QSPI_ADR_SIZE_16_BIT_AUTO_MODE_CSN0 : 1; /*!< [1..1] NONE */ + __IOM unsigned int QSPI_CONTI_RD_EN_CSN0 : 1; /*!< [2..2] NONE */ + __IOM unsigned int DUMMY_BYTES_WR_RD_CSN0 : 1; /*!< [3..3] Dummy bytes to the model to be + read or to be write */ + __IOM unsigned int QSPI_DUMMY_BYTES_JMP_CSN : 4; /*!< [7..4] Dummy cycles to be selected + in case of JUMP */ + __IOM unsigned int QSPI_RD_INST_CSN0 : 8; /*!< [15..8] Read instruction to be used for + the selected SPI modes and when wrap */ + __IOM unsigned int QSPI_RD_WRAP_INT_CSN0 : 8; /*!< [23..16] Read instruction + to be used, when wrap mode is + supported by QSPI flash */ + __IOM unsigned int QSPI_PG_JUMP_INST_CSN0 : 8; /*!< [31..24] Read instruction to be used, + when Page jump is to be used */ + } QSPI_AUTO_CONFIG_2_b; + }; + + union { + __IOM unsigned int QSPI_MANUAL_CONFIG1; /*!< (@ 0x00000010) QSPI Manual + Configuration 1 Register */ + + struct { + __IOM unsigned int QSPI_MANUAL_CSN : 1; /*!< [0..0] SPI CS in manual mode */ + __IOM unsigned int QSPI_MANUAL_WR : 1; /*!< [1..1] Write enable for manual + mode when CS is low */ + __IOM unsigned int QSPI_MANUAL_RD : 1; /*!< [2..2] Read enable for manual mode + when CS is low */ + __IOM unsigned int QSPI_MANUAL_RD_CNT : 10; /*!< [12..3] Indicates total number of bytes + to be read along with 31:27 bits of this + register. Maximum length supported is + 32k bytes */ + __IOM unsigned int QSPI_MANUAL_CSN_SELECT : 2; /*!< [14..13] Indicates which + CSn is valid */ + __IOM unsigned int RESERVED1 : 4; /*!< [18..15] reserved1 */ + __IOM unsigned int QSPI_MANUAL_SIZE_FRM_REG : 2; /*!< [20..19] Manual reads and manual + writes follow this size */ + __IOM unsigned int TAKE_QSPI_MANUAL_WR_SIZE_FRM_REG : 1; /*!< [21..21] NONE */ + __IOM unsigned int QSPI_FULL_DUPLEX_EN : 1; /*!< [22..22] Full duplex mode enable. */ + __IOM unsigned int RESERVED2 : 2; /*!< [24..23] reserved2 */ + __IOM unsigned int HW_CTRLD_QSPI_MODE_CTRL : 1; /*!< [25..25] Hardware controlled qspi + mode in between AUTO and manual */ + __IOM unsigned int QSPI_MANUAL_QSPI_MODE : 1; /*!< [26..26] Internally the priority is + given to manual mode */ + __IOM unsigned int QSPI_MANUAL_RD_CNT1 : 5; /*!< [31..27] Indicates total + number of bytes or bits */ + } QSPI_MANUAL_CONFIG1_b; + }; + + union { + __IOM unsigned int QSPI_MANUAL_CONFIG2; /*!< (@ 0x00000014) QSPI Manual + Configuration 2 Register */ + + struct { + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN0 : 1; /*!< [0..0] Swap the write data inside + the QSPI controller it-self */ + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN1 : 1; /*!< [1..1] Swap the write data inside + the QSPI controller it-self. */ + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN2 : 1; /*!< [2..2] Swap the write data inside + the QSPI controller itself. */ + __IOM unsigned int QSPI_WR_DATA_SWAP_MNL_CSN3 : 1; /*!< [3..3] Swap the write data inside + the QSPI controller itself. */ + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN0 : 1; /*!< [4..4] Swap the read data inside + the QSPIcontroller it self. */ + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN1 : 1; /*!< [5..5] Swap the read data inside + the QSPIcontroller itself. */ + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN2 : 1; /*!< [6..6] Swap the read data inside + the QSPIcontroller it-self */ + __IOM unsigned int QSPI_RD_DATA_SWAP_MNL_CSN3 : 1; /*!< [7..7] Swap the read data inside + the QSPIcontroller itself */ + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN1 : 2; /*!< [9..8] Configures the QSPI flash for + Single/Dual/Quad mode operation in + manual mode for chip select1 csn1 */ + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN2 : 2; /*!< [11..10] Configures the QSPI flash + for Single or Dual or Quad mode + operation in manual mode for chip + select2 csn2 */ + __IOM unsigned int QSPI_MAN_MODE_CONF_CSN3 : 2; /*!< [13..12] Configures the QSPI flash + for Single or Dual or Quad mode + operation in manual mode for chip + select3 csn3 */ + __IOM unsigned int LOOP_BACK_EN : 1; /*!< [14..14] Internal loop back test mode. */ + __IOM unsigned int QSPI_MANUAL_DDR_PHASE : 1; /*!< [15..15] DDR operations can be + performed even in manual mode */ + __IOM unsigned int QSPI_DDR_CLK_EN : 1; /*!< [16..16] DDR operations can be + performed even in manual mode */ + __IOM unsigned int RESERVED1 : 1; /*!< [17..17] reserved1 */ + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [18..18] Set this bit + for read data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn0. */ + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [19..19] Set this bit + for read data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn1. */ + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [20..20] Set this bit + for read data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn2. */ + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN0 : 1; /*!< [21..21] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn0. */ + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN1 : 1; /*!< [22..22] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn1. */ + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN2 : 1; /*!< [23..23] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn2. */ + __IOM unsigned int QSPI_WR_DATA_SWAP_WORD_LVL_MNL_CSN3 : 1; /*!< [24..24] Set this bit + for write data byte + swapping within the word. + It is valid only for octa + ddr mode. It is valid + for csn3. */ + __IOM unsigned int QSPI_MANUAL_DUMMY_BYTE_OR_BIT_MODE : 1; /*!< [25..25] Indicates + qspi_manual_rd_cnt values + are dummy bytes + or bits in manual mode. + */ + __IOM unsigned int RESERVED2 : 6; /*!< [31..26] reserved2 */ + } QSPI_MANUAL_CONFIG2_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int QSPI_FIFO_THRLD; /*!< (@ 0x0000001C) QSPI FIFO Threshold Register */ + + struct { + __IOM unsigned int FIFO_AEMPTY_THRLD : 4; /*!< [3..0] FIFO almost empty threshold */ + __IOM unsigned int FIFO_AFULL_THRLD : 4; /*!< [7..4] FIFO almost full threshold */ + __IOM unsigned int WFIFO_RESET : 1; /*!< [8..8] Write fifo reset */ + __IOM unsigned int RFIFO_RESET : 1; /*!< [9..9] Read fifo reset */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ + } QSPI_FIFO_THRLD_b; + }; + + union { + __IM unsigned int QSPI_MANUAL_STATUS; /*!< (@ 0x00000020) QSPI Manual Status Register */ + + struct { + __IM unsigned int QSPI_BUSY : 1; /*!< [0..0] State of Manual mode. */ + __IM unsigned int FIFO_FULL_WFIFO_S : 1; /*!< [1..1] Status indication for + Wfifo in manual mode */ + __IM unsigned int FIFO_AFULL_WFIFO_S : 1; /*!< [2..2] Status indication for + Wfifo in manual mode */ + __IM unsigned int FIFO_EMPTY_WFIFO : 1; /*!< [3..3] Status indication for + Wfifo in manual mode */ + __IM unsigned int FIFO_AEMPTY_WFIFO : 1; /*!< [4..4] Status indication for + Wfifo in manual mode */ + __IM unsigned int FIFO_FULL_RFIFO : 1; /*!< [5..5] Status indication for Rfifo + in manual mode */ + __IM unsigned int FIFO_AFULL_RFIFO : 1; /*!< [6..6] Status indication for + Rfifo in manual mode */ + __IM unsigned int FIFO_EMPTY_RFIFO_S : 1; /*!< [7..7] Status indication for + Rfifo in manual mode */ + __IM unsigned int FIFO_AEMPTY_RFIFO_S : 1; /*!< [8..8] Status indication for + Rfifo in manual mode */ + __IM unsigned int GSPI_MANUAL_RD_CNT : 1; /*!< [9..9] This is a result of 10 + bits ORing counter */ + __IM unsigned int AUTO_MODE_FSM_IDLE_SCLK : 1; /*!< [10..10] Auto mode idle signal to + track auto controller is busy + or idle. */ + __IM unsigned int QSPI_AUTO_MODE : 1; /*!< [11..11] QSPI controller status. */ + __IM unsigned int QSPI_AUTO_MODE_FRM_REG_SCLK : 1; /*!< [12..12] QSPI auto mode status. + Valid only when + HW_CTRLD_QSPI_MODE_CTRL is zero. + */ + __IM unsigned int HW_CTRLD_MODE_SCLK : 1; /*!< [13..13] QSPI mode status in + HW_CTRLD_MODE */ + __IM unsigned int HW_CTRLD_MODE_CTRL_SCLK : 1; /*!< [14..14] HW_CTRLD_MODE status */ + __IM unsigned int AW_CTRL_BUSY : 1; /*!< [15..15] Auto write busy indication. */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } QSPI_MANUAL_STATUS_b; + }; + + union { + __IOM unsigned int QSPI_INTR_MASK; /*!< (@ 0x00000024) QSPI Interrupt Mask Register */ + + struct { + __IOM unsigned int QSPI_INTR_MASK : 1; /*!< [0..0] Interrupt Status bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_MASK : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_MASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_MASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_MASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_MASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_MASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int AHB_AUTO_WRITE_INTR_MASK : 1; /*!< [7..7] Rising interrupt for any + auto write operation on AHB + bus. This bit is a mask for this + interrupt */ + __IOM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_MASK : 1; /*!< [8..8] Rising interrupt + when no csn is selected + using programmable + auto base address. This + bit is a mask for this + interrupt. */ + __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_MASK : 1; /*!< [9..9] Rising interrupt when + M4 QSPI tries to do manual + mode transactions in Common + flash mode (3). This bit is a + mask for this interrupt. */ + __IOM unsigned int M4_AUTO_READ_OUT_range_intr_mask : 1; /*!< [10..10] Rising interrupt + when M4 QSPI tries to read NWP + locations in Common flash + mode (3). This bit is a mask + for this interrupt. */ + __IOM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_MASK_b; + }; + + union { + __IOM unsigned int QSPI_INTR_UNMASK; /*!< (@ 0x00000028) QSPI Interrupt Unmask + Register */ + + struct { + __IOM unsigned int QSPI_INTR_UNMASK : 1; /*!< [0..0] Interrupt Status bit */ + __IOM unsigned int FIFO_AEMPTY_RFIFO_UN : 1; /*!< [1..1] NONE */ + __IOM unsigned int FIFO_AFULL_RFIFO_UNMASK : 1; /*!< [2..2] NONE */ + __IOM unsigned int FIFO_AEMPTY_WFIFO_UNMASK : 1; /*!< [3..3] NONE */ + __IOM unsigned int FIFO_AFULL_WFIFO_UNMASK : 1; /*!< [4..4] NONE */ + __IOM unsigned int FIFO_FULL_WFIFO_UNMASK : 1; /*!< [5..5] NONE */ + __IOM unsigned int FIFO_EMPTY_RFIFO_UNMASK : 1; /*!< [6..6] NONE */ + __IOM unsigned int AHB_AUTO_WRITE_INTR_UNMASK : 1; /*!< [7..7] Rising interrupt for any + auto write operation on AHB + bus. This bit is a unmask for this + interrupt. */ + __IOM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_UNMASK : 1; /*!< [8..8] Rising interrupt + when M4 QSPI tries to do + manual mode transactions + in Common flash mode (3). + This bit is a unmask for + this interrupt. */ + __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_UNMASK : 1; /*!< [9..9] Rising interrupt + when M4 QSPI tries to do + manual mode transactions in + Common flash mode (3). This + bit is a unmask for this + interrupt. */ + __IOM unsigned int M4_AUTO_READ_OUT_RANGE_INTR_UNMASK : 1; /*!< [10..10] Rising interrupt + when M4 QSPI tries to read + NWP locations in Common + flash mode (3). This bit + is a unmask for this + interrupt. */ + __IOM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_UNMASK_b; + }; + + union { + __IM unsigned int QSPI_INTR_STS; /*!< (@ 0x0000002C) QSPI Interrupt Status Register */ + + struct { + __IM unsigned int QSPI_INTR_LVL : 1; /*!< [0..0] Interrupt Status bit */ + __IM unsigned int FIFO_AEMPTY_RFIFO_LVL : 1; /*!< [1..1] NONE */ + __IM unsigned int FIFO_AFULL_RFIFO_LVL : 1; /*!< [2..2] NONE */ + __IM unsigned int FIFO_AEMPTY_WFIFO_LVL : 1; /*!< [3..3] NONE */ + __IM unsigned int FIFO_AFULL_WFIFO_LVL : 1; /*!< [4..4] NONE */ + __IM unsigned int FIFO_FULL_WFIFO_LVL : 1; /*!< [5..5] NONE */ + __IM unsigned int FIFO_EMPTY_RFIFO_LVL : 1; /*!< [6..6] NONE */ + __IM unsigned int AHB_AUTO_WRITE_INTR_LEV : 1; /*!< [7..7] rising interrupt for any auto + write operation on AHB bus. */ + __IM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_LVL : 1; /*!< [8..8] Rising interrupt + when no csn is selected using + programmable auto base + address. */ + __IM unsigned int M4QSPI_MANUAL_BLOCKED_LVL : 1; /*!< [9..9] Rising interrupt when M4 + QSPI tries to do manual mode + transactions in Common flash mode + (3). */ + __IM unsigned int M4_AUTO_READ_OUT_RANGE_LVL : 1; /*!< [10..10] Rising interrupt when M4 + QSPI tries to read NWP locations + in Common flash mode (3). + */ + __IM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_STS_b; + }; + + union { + __IOM unsigned int QSPI_INTR_ACK; /*!< (@ 0x00000030) QSPI Interrupt Acknowledge + Register */ + + struct { + __OM unsigned int QSPI_INTR_ACK : 1; /*!< [0..0] Interrupt Status bit */ + __OM unsigned int FIFO_AEMPTY_RFIFO_ACK : 1; /*!< [1..1] NONE */ + __OM unsigned int FIFO_AFULL_RFIFO_ACK : 1; /*!< [2..2] NONE */ + __OM unsigned int FIFO_AEMPTY_WFIFO_ACK : 1; /*!< [3..3] NONE */ + __OM unsigned int FIFO_AFULL_WFIFO_ACK : 1; /*!< [4..4] NONE */ + __OM unsigned int FIFO_FULL_WFIFO_ACK : 1; /*!< [5..5] NONE */ + __OM unsigned int FIFO_EMPTY_RFIFO_ACK : 1; /*!< [6..6] NONE */ + __OM unsigned int AHB_AUTO_WRITE_INTR_ACK : 1; /*!< [7..7] Rising interrupt for any auto + write operation on AHB bus. This bit + is an ack for this interrupt. */ + __OM unsigned int QSPI_AUTO_BASE_ADDR_ERR_INTR_ACK : 1; /*!< [8..8] Rising interrupt + when no csn is selected using + programmable auto base + address. This bit is an ack + for this interrupt. */ + __IOM unsigned int M4QSPI_MANUAL_BLOCKED_INTR_ACK : 1; /*!< [9..9] Rising interrupt when + M4 QSPI tries to do manual mode + transactions in Common + flash mode (3). This bit is an + ack for this interrupt. + */ + __IOM unsigned int M4_AUTO_READ_OUT_RANGE_INTR_ACK : 1; /*!< [10..10] Rising interrupt + when M4 QSPI tries to read NWP + locations + in Common flash mode (3). + This bit is an ack for this + interrupt. */ + __OM unsigned int RESERVED1 : 21; /*!< [31..11] reserved1 */ + } QSPI_INTR_ACK_b; + }; + + union { + __IM unsigned int QSPI_STS_MC; /*!< (@ 0x00000034) QSPI State Machine Monitor + Register */ + + struct { + __IM unsigned int BUS_CTRL_PSTATE : 4; /*!< [3..0] Bus controller present state */ + __IM unsigned int AUTO_CTRL_PSTATE : 3; /*!< [6..4] Auto controller present state */ + __IM unsigned int QSPI_MASTER_PSTATE : 3; /*!< [9..7] Qspi master present state */ + __IM unsigned int QSPI_MANUAL_RD_CNT : 15; /*!< [24..10] Qspi manual read + counter value */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] reserved1 */ + } QSPI_STS_MC_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_CONFIG_1_CSN1; /*!< (@ 0x00000038) QSPI Auto Controller + Configuration 1 CSN1 Register */ + + struct { + __IOM unsigned int QSPI_EXT_BYTE_MODE_CSN1 : 2; /*!< [1..0] Mode of operation of QSPI in + instruction phase. */ + __IOM unsigned int QSPI_DUMMY_MODE_CSN1 : 2; /*!< [3..2] Mode of operation of + QSPI in instruction phase */ + __IOM unsigned int QSPI_ADDR_MODE_CSN1 : 2; /*!< [5..4] Mode of operation of + QSPI in instruction phase. */ + __IOM unsigned int QSPI_CMD_MODE_CSN1 : 2; /*!< [7..6] Mode of operation of + QSPI in instruction phase. */ + __IOM unsigned int QSPI_DATA_MODE_CSN1 : 2; /*!< [9..8] Mode of operation of + QSPI in DATA phase. */ + __IM unsigned int QSPI_EXTRA_BYTE_CSN1 : 8; /*!< [17..10] Value of the extra byte to be + transmitted, if the extra byte mode is + enabled. */ + __IOM unsigned int QSPI_EXTRA_BYTE_EN_CSN1 : 2; /*!< [19..18] Mode of operation of QSPI + in DATA phase. */ + __IOM unsigned int QSPI_WRAP_SIZE : 2; /*!< [21..20] Qspi auto wrap size */ + __IOM unsigned int RESERVED1 : 1; /*!< [22..22] reserved1 */ + __OM unsigned int QSPI_PG_JUMP_CSN1 : 1; /*!< [23..23] NONE */ + __IM unsigned int QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [27..24] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode. */ + __IM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [31..28] Specifies the number of + dummy bytes 0 to 7 for the selected + SPI mode in case of wrap instruction. + */ + } QSPI_AUTO_CONFIG_1_CSN1_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_CONFIG_2_CSN1_REG; /*!< (@ 0x0000003C) QSPI Auto Controller + Configuration 2 CSN1 Register */ + + struct { + __IOM unsigned int QSPI_RD_SWAP_AUTO_CSN1 : 1; /*!< [0..0] Swap the read data from the + flash in byte order for chip select1 + csn1 in auto mode. */ + __IOM unsigned int QSPI_ADR_SIZE_16BIT_AUTO_MODE_CSN1 : 1; /*!< [1..1] NONE */ + __IOM unsigned int QSPI_CONTI_RD_EN_CSN1 : 1; /*!< [2..2] Continuous read + enable bit. */ + __IOM unsigned int DUMMY_BYTES_WR_RD : 1; /*!< [3..3] Dummy bytes to the model + to be read or to be write. */ + __IOM unsigned int QSPI_DUMMY_BYTES_JMP_CSN1 : 4; /*!< [7..4] Dummy cycles to be selected + in case of JUMP */ + __IOM unsigned int QSPI_RD_INST_CSN1 : 8; /*!< [15..8] Read instruction to be + used for the selected SPI modes + and when wrap is not needed or + supported */ + __IOM unsigned int QSPI_RD_WRAP_INST_CSN1 : 8; /*!< [23..16] Read instruction to be used + for the selected SPI modes and when + wrap is not needed or supported */ + __IOM unsigned int QSPI_PG_JMP_INST_CSN1 : 8; /*!< [31..24] Read instruction to be used, + when Page jump is to be used. */ + } QSPI_AUTO_CONFIG_2_CSN1_REG_b; + }; + __IOM unsigned int QSPI_MANUAL_RDWR_FIFO[16]; /*!< (@ 0x00000040) QSPI FIFOs */ + + union { + __IOM unsigned int QSPI_MANUAL_WRITE_DATA2; /*!< (@ 0x00000080) QSPI Manual + Write Data 2 Register */ + + struct { + __IOM unsigned int QSPI_MANUAL_WRITE_DATA2 : 5; /*!< [4..0] Number of bits to be written + in write mode */ + __IOM unsigned int RESERVED1 : 2; /*!< [6..5] reserved1 */ + __IOM unsigned int USE_PREV_LENGTH : 1; /*!< [7..7] Use previous length. */ + __IOM unsigned int QSPI_CLK_ENABLE_HCLK : 1; /*!< [8..8] reserved2 */ + __IOM unsigned int RESERVED2 : 23; /*!< [31..9] reserved2 */ + } QSPI_MANUAL_WRITE_DATA2_b; + }; + __IM unsigned int RESERVED1[3]; + + union { + __IOM unsigned int QSPI_AUTO_CONFIG_3_CSN0_REG; /*!< (@ 0x00000090) QSPI Auto Controller + Configuration 3 CSN0 Register */ + + struct { + __IOM unsigned int QSPI_DUMMY_BYTE_OR_BIT_CSN0 : 1; /*!< [0..0] Indicates all above + mention values are dummy bytes or + bits in auto mode. */ + __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN0 : 4; /*!< [4..1] Specifies the number of + dummy bytes for the selected + SPI mode. It contains MS nibble for + byte. */ + __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN0 : 4; /*!< [8..5] Specifies the number of + dummy bytes for the selected SPI mode + in case of wrap instruction. It + contains MS nibble for byte. */ + __IOM unsigned int RESERVED1 : 3; /*!< [11..9] reserved1 */ + __IOM unsigned int QSPI_DDR_CMD_MODE_CSN0 : 1; /*!< [12..12] DDR Command mode */ + __IOM unsigned int QSPI_DDR_ADDR_MODE_CSN0 : 1; /*!< [13..13] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DUMMY_MODE_CSN0 : 1; /*!< [14..14] DDR Address mode */ + __IOM unsigned int QSPI_DDR_EXTRA_MODE_CSN0 : 1; /*!< [15..15] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DATA_MODE_CSN0 : 1; /*!< [16..16] DDR Address mode */ + __IOM unsigned int QSPI_AUTO_DDR_CMD_MODE_CSN0 : 1; /*!< [17..17] DDR data mode. */ + __IOM unsigned int QSPI_CMD_SIZE_16BIT_CSN0 : 1; /*!< [18..18] Enable for 16 read cmd + size for csn0. */ + __IOM unsigned int QSPI_ADR_SIZE_32BIT_AUTO_MODE : 1; /*!< [19..19] 32 bit addressing + support enable. */ + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN0 : 1; /*!< [20..20] Rd data swap + at word level in auto + mode for csn0. It is + valid for octa mode. */ + __IOM unsigned int RESERVED3 : 3; /*!< [23..21] reserved3 */ + __IOM unsigned int QSPI_RD_INST_CSN0_MSB : 8; /*!< [31..24] Read instruction MS byte to + be used the selected SPI + modes and when wrap is not needed or + supported. */ + } QSPI_AUTO_CONFIG_3_CSN0_REG_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_CONFIG_3_CSN1_REG; /*!< (@ 0x00000094) QSPI Auto Controller + Configuration 3 CSN1 Register */ + + struct { + __IOM unsigned int QSPI_DUMMY_BYTE_OR_BIT_CSN1 : 1; /*!< [0..0] Indicates all above + mention values are dummy bytes or + bits in auto mode. */ + __IOM unsigned int QSPI_DUMMY_BYTES_INCR_CSN1 : 4; /*!< [4..1] Specifies the number of + dummy bytes for the selected + SPI mode. It contains MS nibble for + byte. */ + __IOM unsigned int QSPI_DUMMY_BYTES_WRAP_CSN1 : 4; /*!< [8..5] Specifies the number of + dummy bytes for the selected SPI mode + in case of wrap instruction. It + contains MS nibble for byte. */ + __IOM unsigned int RESERVED1 : 3; /*!< [11..9] reserved1 */ + __IOM unsigned int QSPI_DDR_CMD_MODE_CSN1 : 1; /*!< [12..12] DDR Command mode */ + __IOM unsigned int QSPI_DDR_ADDR_MODE_CSN1 : 1; /*!< [13..13] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DUMMY_MODE_CSN1 : 1; /*!< [14..14] DDR Address mode */ + __IOM unsigned int QSPI_DDR_EXTRA_MODE_CSN1 : 1; /*!< [15..15] DDR Address mode */ + __IOM unsigned int QSPI_DDR_DATA_MODE_CSN1 : 1; /*!< [16..16] DDR Address mode */ + __IOM unsigned int QSPI_AUTO_DDR_CMD_MODE_CSN1 : 1; /*!< [17..17] DDR data mode. */ + __IOM unsigned int QSPI_CMD_SIZE_16BIT_CSN1 : 1; /*!< [18..18] Enable for 16 read cmd + size for csn1. */ + __IOM unsigned int RESERVED3 : 1; /*!< [19..19] RESERVED3 */ + __IOM unsigned int QSPI_RD_DATA_SWAP_WORD_LVL_AUTO_CSN1 : 1; /*!< [20..20] Rd data swap + at word level in auto + mode for csn1. It is + valid for octa mode. */ + __IOM unsigned int RESERVED4 : 3; /*!< [23..21] reserved4 */ + __IOM unsigned int QSPI_RD_INST_CSN1_MSB : 8; /*!< [31..24] Read instruction MS byte to + be used the selected SPI + modes and when wrap is not needed or + supported. */ + } QSPI_AUTO_CONFIG_3_CSN1_REG_b; + }; + __IM unsigned int RESERVED2[2]; + + union { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN0; /*!< (@ 0x000000A0) none */ + + struct { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN0 : 32; /*!< [31..0] Holds the 32 bit base + address for select chip select0 in + programmable auto csn mode. It is + valid only programmable + auto csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_CSN0_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN1; /*!< (@ 0x000000A4) none */ + + struct { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_CSN1 : 32; /*!< [31..0] Holds the 32 bit base + address for select chip select1 in + programmable auto csn mode. It is + valid only programmable + auto csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_CSN1_b; + }; + __IM unsigned int RESERVED3[2]; + + union { + __IOM unsigned int OCTASPI_BUS_CONTROLLER; /*!< (@ 0x000000B0) none */ + + struct { + __IOM unsigned int QSPI_D7TOD4_DATA_CSN0 : 4; /*!< [3..0] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select1 (cs_n0). It is used both in Auto + and Manual Mode. */ + __IOM unsigned int QSPI_D7TOD4_OEN_CSN0 : 4; /*!< [7..4] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select0 + (cs_n0). It is used both in Auto and + Manual Mode. */ + __IOM unsigned int QSPI_D7TOD4_DATA_CSN1 : 4; /*!< [11..8] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select1 (cs_n1). It is used both in + Auto and Manual Mode. */ + __IOM unsigned int QSPI_D7TOD4_OEN_CSN1 : 4; /*!< [15..12] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select1 (cs_n1). It is + used both in Auto and Manual Mode. */ + __IOM unsigned int QSPI_D7TOD4_DATA_CSN2 : 4; /*!< [19..16] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select2 (cs_n2). It is used both in + Auto and Manual Mode. */ + __IOM unsigned int QSPI_D7TOD4_OEN_CSN2 : 4; /*!< [23..20] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select2 (cs_n2). It is + used both in Auto and Manual Mode. */ + __IOM unsigned int QSPI_D7TOD4_DATA_CSN3 : 4; /*!< [27..24] Value of SPI_IO7,6,5 and 4 in + case of quad/dual/single mode for chip + select3 (cs_n3). It is used both in Auto + and Manual Mode. */ + __IOM unsigned int QSPI_D7TOD4_OEN_CSN3 : 4; /*!< [31..28] Direction Control for SPI_IO + 7,6,5 and 4 in case of quad/dual/single + mode for chip select3 (cs_n3). It is + used both in Auto and Manual Mode. */ + } OCTASPI_BUS_CONTROLLER_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; /*!< (@ 0x000000B4) none */ + + struct { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN0 : 32; /*!< [31..0] Holds the 32 bit + base address unmask value for + select chip select0 in + programmable auto csn mode. + It is valid + only programmable auto + csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_UNMASK_CSN0_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; /*!< (@ 0x000000B8) none */ + + struct { + __IOM unsigned int QSPI_AUTO_BASE_ADDR_UNMASK_CSN1 : 32; /*!< [31..0] Holds the 32 bit + base address unmask value for + select chip select1 in + programmable auto csn mode. + It is valid + only programmable auto + csn mode is enabled. */ + } QSPI_AUTO_BASE_ADDR_UNMASK_CSN1_b; + }; + __IM unsigned int RESERVED4[2]; + + union { + __IOM unsigned int OCTASPI_BUS_CONTROLLER_2_REG; /*!< (@ 0x000000C4) none */ + + struct { + __IOM unsigned int SET_IP_MODE : 1; /*!< [0..0] This bit enables the qspi + interface pins into HiZ mode */ + __IOM unsigned int AES_NONCE_INIT : 1; /*!< [1..1] This bit enables the AES + initialization with nonce */ + __IOM unsigned int AES_SEC_ENABLE : 1; /*!< [2..2] This bit enables the AES + security enable or not */ + __IOM unsigned int DUAL_MODE_EN : 1; /*!< [3..3] Dual flash mode enable control. */ + __IOM unsigned int CSN0_2_CSN : 2; /*!< [5..4] Map csn0 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM unsigned int CSN1_2_CSN : 2; /*!< [7..6] Map csn1 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM unsigned int CSN2_2_CSN : 2; /*!< [9..8] Map csn2 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM unsigned int CSN3_2_CSN : 2; /*!< [11..10] Map csn3 to the programmed csn. It is + valid for both manual and auto modes */ + __IOM unsigned int AES_SEC_ENABLE_SG1 : 1; /*!< [12..12] This bit enables the AES + security enable or not for segment 1 */ + __IOM unsigned int AES_SEC_ENABLE_SG2 : 1; /*!< [13..13] This bit enables the AES + security enable or not for segment 2 */ + __IOM unsigned int AES_SEC_ENABLE_SG3 : 1; /*!< [14..14] This bit enables the AES + security enable or not for segment 3 */ + __IOM unsigned int AES_SEC_ENABLE_SG4 : 1; /*!< [15..15] This bit enables the AES + security enable or not for segment 4 */ + __IOM unsigned int DUAL_MODE_SWAP_LINES : 1; /*!< [16..16] This bit controls the 8 lines + of qspi with 4 bit swap manner */ + __IOM unsigned int AUTO_MODE_IN_DEFAULT_EN : 1; /*!< [17..17] Qspi works in auto mode if + set this is bit by default. */ + __IOM unsigned int OTP_KEY_LOAD : 1; /*!< [18..18] Enable to load key from OTP/KH */ + __IOM unsigned int DUAL_STAGE_EN_MANUAL : 1; /*!< [19..19] Dual stage en for + dual flash mode */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved2 */ + } OCTASPI_BUS_CONTROLLER_2_REG_b; + }; + + union { + __IOM unsigned int QSPI_AES_CONFIG; /*!< (@ 0x000000C8) QSPI AES CONFIG REG */ + + struct { + __IOM unsigned int QSPI_AES_MODE : 9; /*!< [8..0] AES mode of decryption CTR/XTS */ + __IOM unsigned int QSPI_AES_DECKEYCAL : 1; /*!< [9..9] Enables pre-calculation of KEY + before decryption operation */ + __IOM unsigned int FLIP_KEY_FRM_REG : 1; /*!< [10..10] writing 1 to this Flips the 32-bit + endian key taken from kh */ + __IOM unsigned int FLIP_KEY_FRM_KH : 1; /*!< [11..11] writing 1 to this Flips the 32-bit + endian key taken from kh */ + __OM unsigned int QSPI_AES_SRST : 1; /*!< [12..12] Synchronous soft reset for + AES Module. Write only bit. Reading + this bit gives alway 0 */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ + } QSPI_AES_CONFIG_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY_IV_VALID; /*!< (@ 0x000000CC) QSPI AES KEYS and + IVS VALID */ + + struct { + __IOM unsigned int QSPI_AES_KEY1_VALID : 4; /*!< [3..0] Write enables for AES KEY 1. + Denotes which bytes of key1 is valid */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] reserved1 */ + __IOM unsigned int QSPI_AES_KEY2_VALID : 4; /*!< [11..8] Write enables for AES KEY 2. + Denotes which bytes of key2 is valid */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] reserved2 */ + __IOM unsigned int QSPI_AES_IV1_VALID : 4; /*!< [19..16] Write enables for AES IV 1. + Denotes which bytes of IV1 is valid */ + __IOM unsigned int RESERVED3 : 12; /*!< [31..20] reserved3 */ + } QSPI_AES_KEY_IV_VALID_b; + }; + + union { + __IM unsigned int QSPI_CMNFLASH_STS; /*!< (@ 0x000000D0) QSPI Common Flash Status */ + + struct { + __IM unsigned int QSPI_MANUAL_BLOCKED : 1; /*!< [0..0] 1 - Manual read/write transaction + initiated is blocked.0- No manual + transactions */ + __IM unsigned int AUTO_READ_OUT_RANGE : 1; /*!< [1..1] 1- Auto read transaction is out + of M4 Address range 0- Auto read + transaction is in Address range */ + __IM unsigned int QSPI_AUTO_RD_BUSY : 1; /*!< [2..2] 1 - Auto read transactions in + progress.0 - No Auto read transactions */ + __IM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } QSPI_CMNFLASH_STS_b; + }; + __IM unsigned int RESERVED5[4]; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_1; /*!< (@ 0x000000E4) + QSPI_AES_SEC_SEG_LS_ADDR_1 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_1 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 1st segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_1_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_1; /*!< (@ 0x000000E8) + QSPI_AES_SEC_SEG_MS_ADDR_1 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_1 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 1st segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_1_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_2; /*!< (@ 0x000000EC) + QSPI_AES_SEC_SEG_LS_ADDR_2 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_2 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 2nd segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_2_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_2; /*!< (@ 0x000000F0) + QSPI_AES_SEC_SEG_MS_ADDR_2 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_2 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 2nd segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_2_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_3; /*!< (@ 0x000000F4) + QSPI_AES_SEC_SEG_LS_ADDR_3 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_3 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 3rd segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_3_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_3; /*!< (@ 0x000000F8) + QSPI_AES_SEC_SEG_MS_ADDR_3 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_3 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 3rd segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_3_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_4; /*!< (@ 0x000000FC) + QSPI_AES_SEC_SEG_LS_ADDR_4 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_LS_ADDR_4 : 32; /*!< [31..0] This register specifies + the lower boundary address of + 4th segment */ + } QSPI_AES_SEC_SEG_LS_ADDR_4_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_4; /*!< (@ 0x00000100) + QSPI_AES_SEC_SEG_MS_ADDR_4 */ + + struct { + __IOM unsigned int QSPI_AES_SEC_SEG_MS_ADDR_4 : 32; /*!< [31..0] This register specifies + the upper boundary address of + 4th segment */ + } QSPI_AES_SEC_SEG_MS_ADDR_4_b; + }; + + union { + __IOM unsigned int QSPI_SRAM_CTRL_CSN_REG[4]; /*!< (@ 0x00000104) QSPI SRAM CTRL CSN */ + + struct { + __IOM unsigned int BIT_8_MODE : 1; /*!< [0..0] Flash 8bit (1 byte) boundary mode */ + __IOM unsigned int BYTE_32_MODE : 1; /*!< [1..1] Flash 32 byte boundary mode */ + __IOM unsigned int ADDR_16BIT_MODE : 1; /*!< [2..2] Send only lower 16bits of + Address enable. */ + __IOM unsigned int RESERVED1 : 5; /*!< [7..3] reserved1 */ + __IOM unsigned int CMD_MODE : 2; /*!< [9..8] writing cmd mode */ + __IOM unsigned int ADDR_MODE : 2; /*!< [11..10] writing address mode */ + __IOM unsigned int DATA_MODE : 2; /*!< [13..12] writing address mode */ + __IOM unsigned int RESERVED2 : 2; /*!< [15..14] reserved2 */ + __IOM unsigned int WR_CMD : 8; /*!< [23..16] Command to be used for writing */ + __IOM unsigned int RESERVED3 : 8; /*!< [31..24] reserved3 */ + } QSPI_SRAM_CTRL_CSN_REG_b[4]; + }; + __IM unsigned int RESERVED6[2]; + __IOM + unsigned int SEMI_AUTO_MODE_ADDR_REG; /*!< (@ 0x0000011C) Byte address to read + the data from flash in semi auto + mode. It is valid only semi auto + mode enable bit is asserted */ + + union { + __IOM unsigned int SEMI_AUTO_MODE_CONFIG_REG; /*!< (@ 0x00000120) none */ + + struct { + __IOM unsigned int QSPI_SEMI_AUTO_BSIZE : 8; /*!< [7..0] This is burst size to read data + from flash in semi auto mode */ + __IOM unsigned int QSPI_SEMI_AUTO_HSIZE : 2; /*!< [9..8] Indicates number of bytes valid + in each transaction */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ + } SEMI_AUTO_MODE_CONFIG_REG_b; + }; + + union { + __IOM unsigned int SEMI_AUTO_MODE_CONFIG2_REG; /*!< (@ 0x00000124) none */ + + struct { + __IOM unsigned int QSPI_SEMI_AUTO_RD_CNT : 12; /*!< [11..0] Total number of bytes to be + read flash continuously from the + address given by + SEMI_AUTO_MODE_ADDR_REG */ + __IOM unsigned int QSPI_SEMI_AUTO_MODE_EN : 1; /*!< [12..12] Enable for semi auto mode + read operation. Make sure manual mode + read/write operation is completed + before asserting this bit */ + __IOM unsigned int QSPI_SEMI_AUTO_RD_BUSY : 1; /*!< [13..13] Indicates status of semi + auto mode read status. If it is high, + semi auto mode read operation is + progressing */ + __IOM unsigned int RESERVED1 : 18; /*!< [31..14] reserved1 */ + } SEMI_AUTO_MODE_CONFIG2_REG_b; + }; + + union { + __IOM unsigned int QSPI_BUS_MODE2_REG; /*!< (@ 0x00000128) none */ + + struct { + __IOM unsigned int PREFETCH_ENBLD_MSTR_ID : 4; /*!< [3..0] Holds the programmable + prefetch enabled AHB master ID. This is + commonly used for enabling prefetch for + icache master. */ + __IOM unsigned int PREFETCH_EN_FOR_ICACHE_MSTR : 1; /*!< [4..4] Prefetch enable for + icache AHB master. */ + __IOM unsigned int RESERVED1 : 3; /*!< [7..5] Reserved for future use */ + __IOM + unsigned int QSPI_PREFETCH_ENBLD_TRANS_BYTES : 8; /*!< [15..8] Programmable + prefetch enabled AHB + master transfer bytes. + Assume this is used + for icache and dma ahb + master access in auto + mode. */ + __IOM unsigned int RESERVED2 : 16; /*!< [31..16] Reserved for future use */ + } QSPI_BUS_MODE2_REG_b; + }; + + union { + __IOM unsigned int QSPI_AES_SEC_KEY_FRM_KH_REG; /*!< (@ 0x0000012C) none */ + + struct { + __OM unsigned int START_LOADING_SEC_KEY_FRM_KH : 1; /*!< [0..0] Start Security key + loading from KH. */ + __IM unsigned int LOADING_SEC_KEY_FRM_KH : 1; /*!< [1..1] Indicates security key loading + status from KH. */ + __IOM unsigned int SEC_KEY_READING_INTERVAL : 4; /*!< [5..2] Security key + reading interval */ + __IOM unsigned int RESERVED1 : 26; /*!< [31..6] Reserved for future use */ + } QSPI_AES_SEC_KEY_FRM_KH_REG_b; + }; + + union { + __IOM unsigned int QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; /*!< (@ 0x00000130) none */ + + struct { + __IOM unsigned int CONTINUE_FETCH_WAIT_TIMEOUT_VALUE_FRM_REG : 12; /*!< [11..0] Maximum + Continue fetch wait time + between two qspi auto + reads. */ + __IOM unsigned int CONTINUE_FETCH_EN : 1; /*!< [12..12] Continue fetch feature + enable. */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] Reserved for future use */ + } QSPI_AUTO_CONITNUE_FETCH_CTRL_REG_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY1_0_3; /*!< (@ 0x00000134) QSPI_AES_KEY1_0_3 */ + + struct { + __IOM unsigned int QSPI_AES_KEY1_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes + key1 as 0 referred as lsb in the key */ + } QSPI_AES_KEY1_0_3_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY1_4_7; /*!< (@ 0x00000138) QSPI_AES_KEY1_4_7 */ + + struct { + __IOM unsigned int QSPI_AES_KEY1_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes + key1 as 0 referred as lsb */ + } QSPI_AES_KEY1_4_7_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY1_8_B; /*!< (@ 0x0000013C) QSPI_AES_KEY1_8_B */ + + struct { + __IOM unsigned int QSPI_AES_KEY1_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes + key1 as 0 referred as lsb */ + } QSPI_AES_KEY1_8_B_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY1_C_F; /*!< (@ 0x00000140) QSPI_AES_KEY1_C_F */ + + struct { + __IOM unsigned int QSPI_AES_KEY1_C_F : 32; /*!< [31..0] To hold first 11-8 bytes of aes + key1 as 0 referred as lsb */ + } QSPI_AES_KEY1_C_F_b; + }; + __IM unsigned int RESERVED7[4]; + + union { + __IOM unsigned int QSPI_AES_KEY2_0_3; /*!< (@ 0x00000154) QSPI_AES_KEY2_0_3 */ + + struct { + __IOM unsigned int QSPI_AES_KEY2_0_3 : 32; /*!< [31..0] To hold first 3-0 bytes of aes + key2 as 0 referred as lsb in the key */ + } QSPI_AES_KEY2_0_3_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY2_4_7; /*!< (@ 0x00000158) QSPI_AES_KEY2_4_7 */ + + struct { + __IOM unsigned int QSPI_AES_KEY2_4_7 : 32; /*!< [31..0] To hold first 7-4 bytes of aes + key2 as 0 referred as lsb */ + } QSPI_AES_KEY2_4_7_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY2_8_B; /*!< (@ 0x0000015C) QSPI_AES_KEY2_8_B */ + + struct { + __IOM unsigned int QSPI_AES_KEY2_8_B : 32; /*!< [31..0] To hold first 11-8 bytes of aes + key2 as 0 referred as lsb */ + } QSPI_AES_KEY2_8_B_b; + }; + + union { + __IOM unsigned int QSPI_AES_KEY2_C_F; /*!< (@ 0x00000160) QSPI_AES_KEY2_C_F */ + + struct { + __IOM unsigned int QSPI_AES_KEY2_C_F : 32; /*!< [31..0] To hold first 15-12 bytes of aes + key2 as 0 referred as lsb */ + } QSPI_AES_KEY2_C_F_b; + }; +} QSPI_Type; /*!< Size = 356 (0x164) */ + +/* =========================================================================================================================== + */ +/* ================ CRC + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief CRC is used in all wireless communication as a first data integrity + * check (CRC) + */ + +typedef struct { /*!< (@ 0x45080000) CRC Structure */ + + union { + __IOM unsigned int CRC_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set + register */ + + struct { + __IOM unsigned int SOFT_RST : 1; /*!< [0..0] Soft reset. This clears the FIFO and settles + all the state machines to their IDLE */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use. */ + } CRC_GEN_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int CRC_GEN_CTRL_RESET; /*!< (@ 0x00000004) General control reset + register */ + + struct { + __IOM unsigned int RESERVED1 : 32; /*!< [31..0] Reserved for future use. */ + } CRC_GEN_CTRL_RESET_b; + }; + + union { + __IM unsigned int CRC_GEN_STS; /*!< (@ 0x00000008) General status register */ + + struct { + __IM unsigned int CALC_DONE : 1; /*!< [0..0] When the computation of final CRC + with the data out of fifo, this will get + set to 1 otherwise 0 */ + __IM unsigned int DIN_NUM_BYTES_DONE : 1; /*!< [1..1] When number of bytes requested for + computation of final CRC is read from fifo + by internal FSM, this will get set to 1 + otherwise 0. */ + __IM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved for future use. */ + } CRC_GEN_STS_b; + }; + + union { + __IOM unsigned int CRC_POLYNOMIAL; /*!< (@ 0x0000000C) This register holds the polynomial + with which the final CRC is computed. */ + + struct { + __IOM unsigned int POLYNOMIAL : 32; /*!< [31..0] Polynomial register. This register holds + the polynomial with which the final CRC is + computed.When write Polynomial will be + updated.When read read polynomial. */ + } CRC_POLYNOMIAL_b; + }; + + union { + __IOM unsigned int CRC_POLYNOMIAL_CTRL_SET; /*!< (@ 0x00000010) Polynomial + control set register */ + + struct { + __IOM unsigned int POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width set. Number of + bits/width of the polynomial has to be + written here for the computation of final + CRC. If a new width has to be configured, + clear the existing length first by + writing 0x1f in polynomial_ctrl_reset + register. When read, actual polynomial + width is read. */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ + } CRC_POLYNOMIAL_CTRL_SET_b; + }; + + union { + __IOM unsigned int CRC_POLYNOMIAL_CTRL_RESET; /*!< (@ 0x00000014) Polynomial + control set register */ + + struct { + __IOM unsigned int POLYNOMIAL_WIDTH_SET : 5; /*!< [4..0] Polynomial width reset. If a new + width has to be configured, clear the + existing length first by writing 0x1f. + When read, actual polynomial width is + read. */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use. */ + } CRC_POLYNOMIAL_CTRL_RESET_b; + }; + + union { + __IOM unsigned int CRC_LFSR_INIT_VAL; /*!< (@ 0x00000018) LFSR initial value */ + + struct { + __IOM unsigned int LFSR_INIT : 32; /*!< [31..0] This holds LFSR initialization value. + When ever LFSR needs to be initialized, this has to + be updated with the init value and trigger + init_lfsr in LFSR_INIT_CTRL_SET register. For + example, in WiFi case, 0xffffffff is used as init + value of LFSR. */ + } CRC_LFSR_INIT_VAL_b; + }; + + union { + __IOM unsigned int CRC_LFSR_INIT_CTRL_SET; /*!< (@ 0x0000001C) LFSR state initialization + control set register */ + + struct { + __IOM unsigned int CLEAR_LFSR : 1; /*!< [0..0] Clear LFSR state. When this is + set, LFSR state is cleared to 0 */ + __IOM unsigned int INIT_LFSR : 1; /*!< [1..1] Initialize LFSR state. When this + is set LFSR state will be initialized + with LFSR_INIT_VAL/bit swapped + LFSR_INIT_VAL in the next cycle */ + __IOM unsigned int USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If + this is set bit swapped version of LFSR + init value will be loaded / initialized + to LFSR state */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] Reserved for future use. */ + } CRC_LFSR_INIT_CTRL_SET_b; + }; + + union { + __IOM unsigned int CRC_LFSR_INIT_CTRL_RESET; /*!< (@ 0x00000020) LFSR state initialization + control reset register */ + + struct { + __IOM unsigned int RESERVED1 : 1; /*!< [0..0] Reserved for future use. */ + __IOM unsigned int RESERVED2 : 1; /*!< [1..1] Reserved for future use. */ + __IOM unsigned int USE_SWAPPED_INIT_VAL : 1; /*!< [2..2] Use bit swapped init value. If + this is set bit swapped version of LFSR + init value will be loaded / initialized + to LFSR state */ + __IOM unsigned int RESERVED3 : 29; /*!< [31..3] Reserved for future use. */ + } CRC_LFSR_INIT_CTRL_RESET_b; + }; + + union { + __OM unsigned int CRC_DIN_FIFO; /*!< (@ 0x00000024) Data input FIFO register */ + + struct { + __OM unsigned int DIN_FIFO : 32; /*!< [31..0] FIFO input port is mapped to this + register. Data on which the final CRC has to be + computed has to be loaded to this FIFO */ + } CRC_DIN_FIFO_b; + }; + + union { + __IOM unsigned int CRC_DIN_CTRL_SET; /*!< (@ 0x00000028) Input data control set + register */ + + struct { + __IOM unsigned int DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data + in din_width_from_reg set mode. Before writing a + new value into this, din_ctrl_reset_reg has to + be written with 0x1f to clear this field as + these are set/clear bits. */ + __IOM unsigned int DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, whatever is the input + size, only din_ctrl_reg[4:0] is taken as + valid length/width for inout data. */ + __IOM unsigned int DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, a mix of ULI length + and number of bytes remaining will form the + valid bits (which ever is less + that will be considered as valid + bits). */ + __IOM unsigned int USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this + is set, input data will be swapped and filled + in to FIFO. Whatever read out from FIFO will + be directly fed to LFSR engine. */ + __IOM unsigned int RESET_FIFO_PTRS : 1; /*!< [8..8] Reset fifo pointer. This + clears the FIFO.When this is set, + FIFO will be cleared. */ + __IOM unsigned int RESERVED1 : 15; /*!< [23..9] Reserved for future use. */ + __IOM unsigned int FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold + value. This has to be cleared by writing + 0x0f000000 into din_ctrl_reset before + updating any new value. */ + __IOM unsigned int FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold + value. This has to be cleared by writing + 0xf0000000 into din_ctrl_reset before + updating any new value */ + } CRC_DIN_CTRL_SET_b; + }; + + union { + __IOM unsigned int CRC_DIN_CTRL_RESET_REG; /*!< (@ 0x0000002C) Input data + control set register */ + + struct { + __IOM unsigned int DIN_WIDTH_REG : 5; /*!< [4..0] Valid number of bits in the input data + in din_width_from_reg set mode. Before writing a + new value into this, din_ctrl_reset_reg has to + be written with 0x1f to clear this field as + these are set/clear bits. */ + __IOM unsigned int DIN_WIDTH_FROM_REG : 1; /*!< [5..5] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, whatever is the input + size, only din_ctrl_reg[4:0] is taken as + valid length/width for inout data. */ + __IOM unsigned int DIN_WIDTH_FROM_CNT : 1; /*!< [6..6] Valid number of bits in the input + data. In default, number of valid bits in + the input data is taken from ULI (uli_be). + If this is set, a mix of ULI length + and number of bytes remaining will form the + valid bits (which ever is less + that will be considered as valid + bits). */ + __IOM unsigned int USE_SWAPPED_DIN : 1; /*!< [7..7] Use bit swapped input data. If this + is set input data will be swapped and filled + in to FIFO. Whatever read out from FIFO will + be directly fed to LFSR engine. */ + __IOM unsigned int RESERVED1 : 1; /*!< [8..8] Reserved for future use. */ + __IOM unsigned int RESERVED2 : 15; /*!< [23..9] Reserved for future use. */ + __IOM unsigned int FIFO_AEMPTY_THRESHOLD : 4; /*!< [27..24] FIFO almost empty threshold + value. This has to be cleared by writing + 0x0f000000 into din_ctrl_reset before + updating any new value. */ + __IOM unsigned int FIFO_AFULL_THRESHOULD : 4; /*!< [31..28] FIFO almost full threshold + value. This has to be cleared by writing + 0xf0000000 into din_ctrl_reset before + updating any new value */ + } CRC_DIN_CTRL_RESET_REG_b; + }; + + union { + __IOM unsigned int CRC_DIN_NUM_BYTES; /*!< (@ 0x00000030) Data input FIFO register */ + + struct { + __IOM unsigned int DIN_NUM_BYTES : 32; /*!< [31..0] in out data number of bytes */ + } CRC_DIN_NUM_BYTES_b; + }; + + union { + __IM unsigned int CRC_DIN_STS; /*!< (@ 0x00000034) Input data status register */ + + struct { + __IM unsigned int FIFO_EMPTY : 1; /*!< [0..0] FIFO empty indication status */ + __IM unsigned int FIFO_AEMPTY : 1; /*!< [1..1] FIFO almost empty indication status. */ + __IM unsigned int FIFO_AFULL : 1; /*!< [2..2] FIFO almost full indication status */ + __IM unsigned int FIFO_FULL : 1; /*!< [3..3] FIFO full indication status */ + __IM unsigned int FIFO_OCC : 6; /*!< [9..4] FIFO occupancy */ + __IM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved for future use. */ + } CRC_DIN_STS_b; + }; + + union { + __IOM unsigned int CRC_LFSR_STATE; /*!< (@ 0x00000038) LFSR state register */ + + struct { + __IOM unsigned int LFSR_STATE : 32; /*!< [31..0] If LFSR dynamic loading is + required this can be used for writing + the LFSR state directly. */ + } CRC_LFSR_STATE_b; + }; +} CRC_Type; /*!< Size = 60 (0x3c) */ + +/* =========================================================================================================================== + */ +/* ================ EFUSE + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The EFUSE controller is used to provide an interface to one time + * program memory (EFUSE macro) to perform write and read operations (EFUSE) + */ + +typedef struct { /*!< (@ 0x4600C000) EFUSE Structure */ + + union { + __IOM unsigned int EFUSE_DA_ADDR_REG; /*!< (@ 0x00000000) Direct Access Registers */ + + struct { + __IOM unsigned int ADDR_BITS : 16; /*!< [15..0] These bits specifies the address to write + or read from EFUSE macro model */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } EFUSE_DA_ADDR_REG_b; + }; + + union { + __IOM unsigned int EFUSE_DA_CTRL_SET_REG; /*!< (@ 0x00000004) Direct Access Set + Registers */ + + struct { + __IOM unsigned int PGENB : 1; /*!< [0..0] Set Program enable */ + __IOM unsigned int CSB : 1; /*!< [1..1] Set Chip Enable */ + __IOM unsigned int STROBE : 1; /*!< [2..2] Set strobe enable */ + __IOM unsigned int LOAD : 1; /*!< [3..3] Set Load enable */ + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_DA_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int EFUSE_DA_CTRL_CLEAR_REG; /*!< (@ 0x00000008) Direct Access + Clear Registers */ + + struct { + __IOM unsigned int PGENB : 1; /*!< [0..0] Clear Program enable */ + __IOM unsigned int CSB : 1; /*!< [1..1] Clear Chip Enable */ + __IM unsigned int RESERVED1 : 1; /*!< [2..2] reserved1 */ + __IOM unsigned int LOAD : 1; /*!< [3..3] Clear Load enable */ + __IM unsigned int RESERVED2 : 12; /*!< [15..4] reserved2 */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] reserved3 */ + } EFUSE_DA_CTRL_CLEAR_REG_b; + }; + + union { + __IOM unsigned int EFUSE_CTRL_REG; /*!< (@ 0x0000000C) Control Register */ + + struct { + __IOM unsigned int EFUSE_ENABLE : 1; /*!< [0..0] This bit specifies whether the EFUSE + module is enabled or not */ + __IOM unsigned int EFUSE_DIRECT_PATH_ENABLE : 1; /*!< [1..1] This bit specifies whether + the EFUSE direct path is enabled or + not for direct accessing of the EFUSE + pins */ + __IOM unsigned int ENABLE_EFUSE_WRITE : 1; /*!< [2..2] Controls the switch on + VDDIQ for eFuse read/write. */ + __IM unsigned int RESERVED1 : 13; /*!< [15..3] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_CTRL_REG_b; + }; + + union { + __IOM unsigned int EFUSE_READ_ADDR_REG; /*!< (@ 0x00000010) Read address Register */ + + struct { + __IOM unsigned int READ_ADDR_BITS : 13; /*!< [12..0] These bits specifies the + address from which read operation + has to be performed */ + __IM unsigned int RESERVED1 : 2; /*!< [14..13] reserved1 */ + __OM unsigned int DO_READ : 1; /*!< [15..15] Enables read FSM after EFUSE is + enabled */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_READ_ADDR_REG_b; + }; + + union { + __IOM unsigned int EFUSE_READ_DATA_REG; /*!< (@ 0x00000014) Read address Register */ + + struct { + __IOM unsigned int READ_DATA_BITS : 8; /*!< [7..0] These bits specifies the data bits + that are read from a given address specified in + the EFUSE_READ_ADDRESS_REGISTER bits 8:0 */ + __IM unsigned int RESERVED1 : 7; /*!< [14..8] reserved1 */ + __IM unsigned int READ_FSM_DONE : 1; /*!< [15..15] Indicates read fsm is done. + After this read data is available in + EFUSE_READ_DATA_REGISTER bits 7:0 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_READ_DATA_REG_b; + }; + + union { + __IM unsigned int EFUSE_STATUS_REG; /*!< (@ 0x00000018) Read address Register */ + + struct { + __IM unsigned int EFUSE_ENABLED : 1; /*!< [0..0] This bit specifies whether + the EFUSE is enabled or not */ + __IM unsigned int RESERVED1 : 1; /*!< [1..1] reserved1 */ + __IM unsigned int EFUSE_DOUT_SYNC : 8; /*!< [9..2] This bit specifies the 8-bit data + read out from the EFUSE macro. This is + synchronized with pclk */ + __IM unsigned int STROBE_CLEAR_BIT : 1; /*!< [10..10] This bit indicates STROBE signal + goes low after strobe + count value reached '0' */ + __IM unsigned int RESERVED2 : 5; /*!< [15..11] reserved2 */ + __IM unsigned int RESERVED3 : 16; /*!< [31..16] reserved3 */ + } EFUSE_STATUS_REG_b; + }; + + union { + __IOM unsigned int EFUSE_RD_TMNG_PARAM_REG; /*!< (@ 0x0000001C) none */ + + struct { + __IOM unsigned int TSUR_CS : 4; /*!< [3..0] CSB to STROBE setup time into read mode */ + __IOM unsigned int TSQ : 4; /*!< [7..4] Q7-Q0 access time from STROBE rising edge */ + __IOM unsigned int THRA : 4; /*!< [11..8] for 32x8 macro: A4 A0 to STROBE hold + time into Read mode 5122x8 macro: A8 A0 to + STROBE hold time into Read mode */ + __IM unsigned int RESERVED1 : 4; /*!< [15..12] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_RD_TMNG_PARAM_REG_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int EFUSE_MEM_MAP_LENGTH_REG; /*!< (@ 0x00000024) none */ + + struct { + __IOM unsigned int EFUSE_MEM_MAP_LEN : 1; /*!< [0..0] 0: 8 bit read 1: 16 bit read */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_MEM_MAP_LENGTH_REG_b; + }; + + union { + __IOM + unsigned int EFUSE_READ_BLOCK_STARTING_LOCATION; /*!< (@ 0x00000028) Starting + address from which the read + has to be blocked. Once the + end address is written, it + cannot be changed till power + on reset is given */ + + struct { + __IOM unsigned int EFUSE_READ_BLOCK_STARTING_LOCATION : 16; /*!< [15..0] Starting address + from which the read has to + be blocked. Once the end + address is written, it + cannot be changed till + power on reset is given. + */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } EFUSE_READ_BLOCK_STARTING_LOCATION_b; + }; + + union { + __IOM unsigned int EFUSE_READ_BLOCK_END_LOCATION; /*!< (@ 0x0000002C) Starting address from + which the read has to be blocked. Once + the end address is written, it cannot + be changed till power on reset is + given */ + + struct { + __IOM unsigned int EFUSE_READ_BLOCK_END_LOCATION : 16; /*!< [15..0] End address till + which the read has to be + blocked. Once the end address + is written , it cannot be + changed till + power on reset is given. + */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reserved1 */ + } EFUSE_READ_BLOCK_END_LOCATION_b; + }; + + union { + __IOM unsigned int EFUSE_READ_BLOCK_ENABLE_REG; /*!< (@ 0x00000030) The Transmit Poll + Demand register enables the Transmit DMA + to check whether or not the current + descriptor is owned by DMA */ + + struct { + __IOM unsigned int EFUSE_READ_BLOCK_ENABLE : 1; /*!< [0..0] Enable for blocking the read + access from a programmable memory + location */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_READ_BLOCK_ENABLE_REG_b; + }; + + union { + __IOM unsigned int EFUSE_DA_CLR_STROBE_REG; /*!< (@ 0x00000034) none */ + + struct { + __IOM unsigned int EFUSE_STROBE_CLR_CNT : 9; /*!< [8..0] Strobe signal Clear count in + direct access mode. value + depends on APB clock frequency of + eFuse controller */ + __IOM unsigned int EFUSE_STROBE_ENABLE : 1; /*!< [9..9] none */ + __IM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IM unsigned int RESERVED2 : 16; /*!< [31..16] reserved2 */ + } EFUSE_DA_CLR_STROBE_REG_b; + }; +} EFUSE_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== + */ +/* ================ I2S0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief I2S(Inter-IC Sound) is transferring two-channel digital audio data + * from one IC device to another (I2S0) + */ + +typedef struct { /*!< (@ 0x47050000) I2S0 Structure */ + + union { + __IOM unsigned int I2S_IER; /*!< (@ 0x00000000) I2S Enable Register */ + + struct { + __IOM unsigned int IEN : 1; /*!< [0..0] Inter Block Enable */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_IER_b; + }; + + union { + __IOM unsigned int I2S_IRER; /*!< (@ 0x00000004) I2S Receiver Block Enable Register */ + + struct { + __IOM unsigned int RXEN : 1; /*!< [0..0] Receive Block Enable, Bit Overrides + any Individual Receive Channel Enables */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_IRER_b; + }; + + union { + __IOM unsigned int I2S_ITER; /*!< (@ 0x00000008) Transmitter Block Enable */ + + struct { + __IOM unsigned int TXEN : 1; /*!< [0..0] Transmitter Block Enable, Bit Overrides any + Individual Transmit Channel Enables */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_ITER_b; + }; + + union { + __IOM unsigned int I2S_CER; /*!< (@ 0x0000000C) Clock Enable Register */ + + struct { + __IOM unsigned int CLKEN : 1; /*!< [0..0] Clock generation enable/disable */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_CER_b; + }; + + union { + __IOM unsigned int I2S_CCR; /*!< (@ 0x00000010) Clock Configuration Register */ + + struct { + __IOM unsigned int SCLKG : 3; /*!< [2..0] These bits are used to program the + gating of sclk */ + __IOM unsigned int WSS : 2; /*!< [4..3] These bits are used to program the + number of sclk cycles */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] Reserved for future use */ + } I2S_CCR_b; + }; + + union { + __OM unsigned int I2S_RXFFR; /*!< (@ 0x00000014) Receiver Block FIFO Reset Register */ + + struct { + __OM unsigned int RXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes + All The RX FIFO's Receiver Block Must be + Disable Prior to Writing This Bit */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RXFFR_b; + }; + + union { + __OM unsigned int I2S_TXFFR; /*!< (@ 0x00000018) Transmitter Block FIFO Reset + Register */ + + struct { + __OM unsigned int TXFFR : 1; /*!< [0..0] Writing a 1 To This Register Flushes + All The RX FIFO's Receiver Block Must be + Disable Prior to Writing This Bit */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_TXFFR_b; + }; + __IM unsigned int RESERVED; + __IOM I2S0_CHANNEL_CONFIG_Type CHANNEL_CONFIG[4]; /*!< (@ 0x00000020) [0..3] */ + __IM unsigned int RESERVED1[40]; + + union { + __IM unsigned int I2S_RXDMA; /*!< (@ 0x000001C0) Receiver Block DMA Register */ + + struct { + __IM unsigned int RXDMA : 32; /*!< [31..0] Used to cycle repeatedly through the enabled + receive channels Reading stereo data pairs */ + } I2S_RXDMA_b; + }; + + union { + __OM unsigned int I2S_RRXDMA; /*!< (@ 0x000001C4) Reset Receiver Block DMA Register */ + + struct { + __OM unsigned int RRXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing + register resets the RXDMA register */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved for future use */ + } I2S_RRXDMA_b; + }; + + union { + __OM unsigned int I2S_TXDMA; /*!< (@ 0x000001C8) Transmitter Block DMA Register */ + + struct { + __OM unsigned int TXDMA : 32; /*!< [31..0] Used to cycle repeatedly through + the enabled transmit channels allow to + writing of stereo data pairs */ + } I2S_TXDMA_b; + }; + + union { + __OM unsigned int I2S_RTXDMA; /*!< (@ 0x000001CC) Reset Transmitter Block DMA + Register */ + + struct { + __OM unsigned int RTXDMA : 1; /*!< [0..0] Writing a 1 to this self-clearing + register resets the TXDMA register */ + __OM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } I2S_RTXDMA_b; + }; + __IM unsigned int RESERVED2[8]; + + union { + __IM unsigned int I2S_COMP_PARAM_2; /*!< (@ 0x000001F0) Component Parameter 2 + Register */ + + struct { + __IM unsigned int I2S_RX_WORDSIZE_0 : 3; /*!< [2..0] On Read returns the value + of word size of receiver channel + 0 */ + __IM unsigned int I2S_RX_WORDSIZE_1 : 3; /*!< [5..3] On Read returns the value + of word size of receiver channel + 1 */ + __IM unsigned int RESERVED1 : 1; /*!< [6..6] Reserved1 */ + __IM unsigned int I2S_RX_WORDSIZE_2 : 3; /*!< [9..7] On Read returns the value + of word size of receiver channel + 2 */ + __IM unsigned int I2S_RX_WORDSIZE_3 : 3; /*!< [12..10] On Read returns the value of word + size of receiver channel 3 */ + __IM unsigned int RESERVED2 : 19; /*!< [31..13] Reserved2 */ + } I2S_COMP_PARAM_2_b; + }; + + union { + __IM unsigned int I2S_COMP_PARAM_1; /*!< (@ 0x000001F4) Component Parameter 1 + Register */ + + struct { + __IM unsigned int APB_DATA_WIDTH : 2; /*!< [1..0] Width of APB data bus */ + __IM unsigned int I2S_FIFO_DEPTH_GLOBAL : 2; /*!< [3..2] Determines FIFO depth + for all channels */ + __IM unsigned int I2S_FIFO_MODE_EN : 1; /*!< [4..4] Determines whether component act as + Master or Slave */ + __IM unsigned int I2S_TRANSMITTER_BLOCK : 1; /*!< [5..5] Shows the presence of + the transmitter block */ + __IM unsigned int I2S_RECEIVER_BLOCK : 1; /*!< [6..6] Shows the presence of + the receiver block */ + __IM unsigned int I2S_RX_CHANNELS : 2; /*!< [8..7] Returns the number of + receiver channels */ + __IM unsigned int I2S_TX_CHANNELS : 2; /*!< [10..9] Returns the number of + transmitter channels */ + __IM unsigned int RESERVED1 : 5; /*!< [15..11] Reserved1 */ + __IM unsigned int I2S_TX_WORDSIZE_0 : 3; /*!< [18..16] Returns the value of + word size of transmitter channel + 0 */ + __IM unsigned int I2S_TX_WORDSIZE_1 : 3; /*!< [21..19] Returns the value of + word size of transmitter channel + 1 */ + __IM unsigned int I2S_TX_WORDSIZE_2 : 3; /*!< [24..22] Returns the value of + word size of transmitter channel + 2 */ + __IM unsigned int I2S_TX_WORDSIZE_3 : 3; /*!< [27..25] Returns the value of + word size of transmitter channel + 3 */ + __IM unsigned int RESERVED2 : 4; /*!< [31..28] Reserved2 */ + } I2S_COMP_PARAM_1_b; + }; + + union { + __IM unsigned int I2S_COMP_VERSION_REG; /*!< (@ 0x000001F8) Component Version ID */ + + struct { + __IM unsigned int I2S_COMP_VERSION : 32; /*!< [31..0] Return the component + version(1.02) */ + } I2S_COMP_VERSION_REG_b; + }; + + union { + __IM unsigned int I2S_COMP_TYPE_REG; /*!< (@ 0x000001FC) Component Type */ + + struct { + __IM unsigned int I2S_COMP_TYPE : 32; /*!< [31..0] Return the component type */ + } I2S_COMP_TYPE_REG_b; + }; +} I2S0_Type; /*!< Size = 512 (0x200) */ + +/* =========================================================================================================================== + */ +/* ================ IID_AES + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The AES module provides AES encoding and decoding functionality. It + * can be used in a microprocessor based environment (IID_AES) + */ + +typedef struct { /*!< (@ 0x20480500) IID_AES Structure */ + + union { + __IOM unsigned int AES_KCR; /*!< (@ 0x00000000) AES Key Control register */ + + struct { + __IOM unsigned int AES_KEY_CHNG_REQ : 1; /*!< [0..0] Programming 1 clears the current key + and starts a request a for a new key + Auto-reverts to 0 as soon as the request is + accepted */ + __IOM unsigned int AES_KEY_SIZE : 1; /*!< [1..1] Size of the AES key 0: + 128-bit 1: 256-bit */ + __IM unsigned int : 5; + __IOM unsigned int AES_KEY_SRC : 1; /*!< [7..7] Source of the AES key 0: + Interface 1: Register */ + __IM unsigned int : 24; + } AES_KCR_b; + }; + + union { + __IOM unsigned int AES_MODE_REG; /*!< (@ 0x00000004) AES Mode register */ + + struct { + __IOM unsigned int AES_MODE : 8; /*!< [7..0] The AES Mode register defines + which mode of AES is used. */ + __IM unsigned int : 24; + } AES_MODE_REG_b; + }; + + union { + __IOM unsigned int AES_ACT_REG; /*!< (@ 0x00000008) AES Action register */ + + struct { + __IOM unsigned int AES_ACTION : 2; /*!< [1..0] The AES Mode register defines + which mode of AES is used. */ + __IM unsigned int : 30; + } AES_ACT_REG_b; + }; + __IM unsigned int RESERVED[5]; + + union { + __IM unsigned int AES_SR_REG; /*!< (@ 0x00000020) AES Status register */ + + struct { + __IM unsigned int AES_BUSY : 1; /*!< [0..0] Indicates that the AES core is + processing data */ + __IM unsigned int : 1; + __IM unsigned int AES_CLEAR_DONE : 1; /*!< [2..2] Indicates that the Clear + action is finished */ + __IM unsigned int AES_KEY_PRESENT : 1; /*!< [3..3] Indicates that the Clear + action is finished */ + __IM unsigned int : 1; + __IM unsigned int AES_KEY_REQ : 1; /*!< [5..5] Indicates that a key must be + provided */ + __IM unsigned int AES_DATA_REQ : 1; /*!< [6..6] Indicates that data must be + provided */ + __IM unsigned int AES_DATA_AV : 1; /*!< [7..7] Indicates that data is available */ + __IM unsigned int : 24; + } AES_SR_REG_b; + }; + __IM unsigned int RESERVED1[7]; + + union { + __OM unsigned int AES_KEY_REG; /*!< (@ 0x00000040) The AES Key register is used + to program a key into the AES module. */ + + struct { + __OM unsigned int AES_KEY : 32; /*!< [31..0] 4 writes of 32 bits make up the 128-bit key + for AES, 8 writes make up the 256-bit key */ + } AES_KEY_REG_b; + }; + + union { + __OM unsigned int AES_DIN_REG; /*!< (@ 0x00000044) AES Data In register */ + + struct { + __OM unsigned int AES_DIN : 32; /*!< [31..0] Data for encoding or decoding, 4 writes of + 32 bits make up a 128-bit data word */ + } AES_DIN_REG_b; + }; + + union { + __IM unsigned int AES_DOUT_REG; /*!< (@ 0x00000048) AES Data out register */ + + struct { + __IM unsigned int AES_DOUT : 32; /*!< [31..0] Result from encoding or decoding, 4 reads + of 32 bits make up a 128-bit data word */ + } AES_DOUT_REG_b; + }; + __IM unsigned int RESERVED2[36]; + + union { + __OM unsigned int AES_IF_SR_C_REG; /*!< (@ 0x000000DC) AES Interface Status + Clear register */ + + struct { + __OM unsigned int IFB_ERROR : 1; /*!< [0..0] Clears the if_error bit */ + __IM unsigned int : 31; + } AES_IF_SR_C_REG_b; + }; + + union { + __IM unsigned int AES_IF_SR_REG; /*!< (@ 0x000000E0) AES Interface Status register */ + + struct { + __IM unsigned int IF_ERROR : 1; /*!< [0..0] Indicates that an interface error + has occurred */ + __IM unsigned int : 31; + } AES_IF_SR_REG_b; + }; + + union { + __IOM unsigned int AES_TEST_REG; /*!< (@ 0x000000E4) AES Test register */ + + struct { + __IOM unsigned int AES_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_aes + module and runs a BIST */ + __IM unsigned int : 3; + __IOM unsigned int AES_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or + finishing up */ + __IOM unsigned int AES_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is + running */ + __IOM unsigned int AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM unsigned int AES_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has + failed */ + __IM unsigned int : 24; + } AES_TEST_REG_b; + }; + __IM unsigned int RESERVED3[6]; + + union { + __IM unsigned int AES_VER_REG; /*!< (@ 0x00000100) AES Version register */ + + struct { + __IM unsigned int AES_VERSION : 32; /*!< [31..0] Version of iid_aes */ + } AES_VER_REG_b; + }; +} IID_AES_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== + */ +/* ================ IID_QK + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The purpose of Quiddikey is to provide secure key storage without + * storing the key. (IID_QK) + */ + +typedef struct { /*!< (@ 0x20480600) IID_QK Structure */ + + union { + __OM unsigned int QK_CR_REG; /*!< (@ 0x00000000) Quiddikey Control register.The + Quiddikey Control register defines which command + must be executed next. */ + + struct { + __OM unsigned int QK_ZEROIZE : 1; /*!< [0..0] Begin Zeroize operation and go + to Error state */ + __OM unsigned int QK_ENROLL : 1; /*!< [1..1] Begin Enroll operation */ + __OM unsigned int QK_START : 1; /*!< [2..2] Begin Start operation */ + __OM unsigned int QK_SET_IK : 1; /*!< [3..3] Begin Set Intrinsic Key operation */ + __OM unsigned int QK_SET_UK : 1; /*!< [4..4] Begin Set User Key operation */ + __OM unsigned int QK_SET_XK : 1; /*!< [5..5] Begin Set External Key operation */ + __OM unsigned int QK_GET_KEY : 1; /*!< [6..6] Begin Get Key operation */ + __IM unsigned int : 25; + } QK_CR_REG_b; + }; + + union { + __IOM unsigned int QK_KIDX_REG; /*!< (@ 0x00000004) The Quiddikey Key Index register + defines the key index for the next set_key command */ + + struct { + __IOM unsigned int QK_KEY_INDEX : 4; /*!< [3..0] Key index for Set Key operations */ + __IM unsigned int : 28; + } QK_KIDX_REG_b; + }; + + union { + __IOM unsigned int QK_KSZ_REG; /*!< (@ 0x00000008) Quiddikey Key Size register */ + + struct { + __IOM unsigned int QK_KEY_SIZE : 6; /*!< [5..0] Key size for Set Key operations */ + __IM unsigned int : 26; + } QK_KSZ_REG_b; + }; + + union { + __IOM unsigned int QK_KT_REG; /*!< (@ 0x0000000C) Quiddikey Key Size register */ + + struct { + __IOM unsigned int QK_KEY_TARGET : 1; /*!< [0..0] Target of reconstructed key */ + __IM unsigned int : 31; + } QK_KT_REG_b; + }; + __IM unsigned int RESERVED[4]; + + union { + __IM unsigned int QK_SR_REG; /*!< (@ 0x00000020) Quiddikey Status register */ + + struct { + __IM unsigned int QK_BUSY : 1; /*!< [0..0] Indicates that operation is in progress */ + __IM unsigned int QK_OK : 1; /*!< [1..1] Last operation was successful */ + __IM unsigned int QK_ERROR : 1; /*!< [2..2] Quiddikey is in the Error state + and no operations can be performed */ + __IM unsigned int QK_XO_AV : 1; /*!< [3..3] Next part of XKPD is available */ + __IM unsigned int QK_KI_REQ : 1; /*!< [4..4] Request for next part of key */ + __IM unsigned int QK_KO_AV : 1; /*!< [5..5] Next part of key is available */ + __IM unsigned int QK_CI_REQ : 1; /*!< [6..6] Request for next part of AC/KC */ + __IM unsigned int QK_CO_AV : 1; /*!< [7..7] Next part of AC/KC is available */ + __IM unsigned int : 24; + } QK_SR_REG_b; + }; + __IM unsigned int RESERVED1; + + union { + __IM unsigned int QK_AR_REG; /*!< (@ 0x00000028) Quiddikey allow register */ + + struct { + __IM unsigned int QK_ALLOW_ENROLL : 1; /*!< [0..0] Enroll operation is allowed */ + __IM unsigned int QK_ALLOW_START : 1; /*!< [1..1] Start operation is allowed */ + __IM unsigned int QK_ALLOW_SET_KEY : 1; /*!< [2..2] Set Key operations are allowed */ + __IM unsigned int QK_ALLOW_GET_KEY : 1; /*!< [3..3] Get Key operation is allowed */ + __IM unsigned int : 3; + __IM unsigned int QK_ALLOW_BIST : 1; /*!< [7..7] BIST is allowed to be started */ + __IM unsigned int : 24; + } QK_AR_REG_b; + }; + __IM unsigned int RESERVED2[5]; + + union { + __IOM unsigned int QK_KI_REG; /*!< (@ 0x00000040) Quiddikey Key Input register */ + + struct { + __IOM unsigned int QK_KI : 32; /*!< [31..0] Key input data */ + } QK_KI_REG_b; + }; + + union { + __IOM unsigned int QK_CI_REG; /*!< (@ 0x00000044) Quiddikey Code Input register */ + + struct { + __IOM unsigned int QK_CI : 32; /*!< [31..0] AC/KC input data */ + } QK_CI_REG_b; + }; + + union { + __IM unsigned int QK_CO_REG; /*!< (@ 0x00000048) Quiddikey Code Output register */ + + struct { + __IM unsigned int QK_CO : 32; /*!< [31..0] AC/KC output data */ + } QK_CO_REG_b; + }; + + union { + __IM unsigned int QK_XO_REG; /*!< (@ 0x0000004C) Quiddikey XKPD Output register */ + + struct { + __IM unsigned int QK_XO : 32; /*!< [31..0] XKPD output data */ + } QK_XO_REG_b; + }; + __IM unsigned int RESERVED3[4]; + + union { + __IM unsigned int QK_KO_IDX_REG; /*!< (@ 0x00000060) Quiddikey Key Output Index + register */ + + struct { + __IM unsigned int qk_ko_index : 4; /*!< [3..0] Key index for the key that is currently + output via the Key Output register */ + __IM unsigned int : 28; + } QK_KO_IDX_REG_b; + }; + + union { + __IM unsigned int QK_KO_REG; /*!< (@ 0x00000064) Quiddikey Code Output register */ + + struct { + __IM unsigned int QK_KO : 32; /*!< [31..0] Key output data */ + } QK_KO_REG_b; + }; + __IM unsigned int RESERVED4[29]; + + union { + __IM unsigned int QK_IF_SR_C_REG; /*!< (@ 0x000000DC) Quiddikey Interface Status + register */ + + struct { + __IM unsigned int IF_ERROR : 1; /*!< [0..0] Clears the if_error bit */ + __IM unsigned int : 31; + } QK_IF_SR_C_REG_b; + }; + + union { + __IM unsigned int QK_IF_SR_REG; /*!< (@ 0x000000E0) Quiddikey Interface Status + register */ + + struct { + __IM unsigned int IF_ERROR : 1; /*!< [0..0] Indicates that an interface error + has occurred */ + __IM unsigned int : 31; + } QK_IF_SR_REG_b; + }; + + union { + __IOM unsigned int QK_TEST_REG; /*!< (@ 0x000000E4) QK Test register */ + + struct { + __IOM unsigned int QK_BIST_ENABLE : 1; /*!< [0..0] Isolates the iid_quiddikey + module and runs a BIST */ + __IM unsigned int : 3; + __IOM unsigned int QK_BIST_RUNNING : 1; /*!< [4..4] BIST is in progress or + finishing up */ + __IOM unsigned int QK_BIST_ACTIVE : 1; /*!< [5..5] Indicates that the BIST is + running */ + __IOM unsigned int QK_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM unsigned int QK_BIST_ERROR : 1; /*!< [7..7] Indicates that the BIST has failed */ + __IM unsigned int : 24; + } QK_TEST_REG_b; + }; + __IM unsigned int RESERVED5[6]; + + union { + __IM unsigned int QK_VER_REG; /*!< (@ 0x00000100) QK Version register */ + + struct { + __IM unsigned int QK_VERSION : 32; /*!< [31..0] Version of iid_qk */ + } QK_VER_REG_b; + }; +} IID_QK_Type; /*!< Size = 260 (0x104) */ + +/* =========================================================================================================================== + */ +/* ================ IID_RPINE + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief none (IID_RPINE) + */ + +typedef struct { /*!< (@ 0x20480400) IID_RPINE Structure */ + + union { + __IOM unsigned int IID_BIST_CTRL_REG; /*!< (@ 0x00000000) Quiddikey Control register.The + Quiddikey Control register defines which command + must be executed next. */ + + struct { + __IOM unsigned int QK_BIST_ENABLE : 1; /*!< [0..0] none */ + __IOM unsigned int AES_BIST_ENABLE : 1; /*!< [1..1] none */ + __IOM unsigned int KH_BIST_ENABLE : 1; /*!< [2..2] none */ + __IM unsigned int : 29; + } IID_BIST_CTRL_REG_b; + }; + + union { + __IOM unsigned int IID_BIST_STATUS_REG; /*!< (@ 0x00000004) none */ + + struct { + __IOM unsigned int QK_BIST_ACTIVE : 1; /*!< [0..0] none */ + __IOM unsigned int QK_BIST_ERROR : 1; /*!< [1..1] Indicates that the BIST has failed */ + __IOM unsigned int QK_BIST_OK : 1; /*!< [2..2] Indicates that the BIST has passed */ + __IOM unsigned int QK_BIST_RUNNING : 1; /*!< [3..3] Indicates that the BIST is + running */ + __IOM unsigned int AES_BIST_ACTIVE : 1; /*!< [4..4] none */ + __IOM unsigned int AES_BIST_ERROR : 1; /*!< [5..5] none */ + __IOM unsigned int AES_BIST_OK : 1; /*!< [6..6] Indicates that the BIST has passed */ + __IOM unsigned int AES_BIST_RUNNING : 1; /*!< [7..7] Indicates that the BIST + is running */ + __IOM unsigned int KH_BIST_STATUS : 1; /*!< [8..8] none */ + __IM unsigned int : 23; + } IID_BIST_STATUS_REG_b; + }; + + union { + __IOM unsigned int IID_CTRL_REG; /*!< (@ 0x00000008) none */ + + struct { + __IOM unsigned int AES_MAX_KEY_SIZE : 1; /*!< [0..0] 1 256 bit key, 0 128 bit key */ + __IOM unsigned int SOURCE_KEY_KH : 1; /*!< [1..1] When set KH will source the key to AES + engine. When this is not QK key output is + connected to AES key input */ + __IOM unsigned int LATCH_KEY_KH : 1; /*!< [2..2] When set KH will latch the key given by + QK. When this is not QK key output is connected + to AES key input */ + __IOM unsigned int KH_RESET_N : 1; /*!< [3..3] 0 KH will be in reset 1 Out of reset */ + __IOM unsigned int KH_KEY_SIZE : 1; /*!< [4..4] 0 128 bit key 1 256 bit key + This is used by KH */ + __IOM unsigned int KH_CLOCK_RATIO : 3; /*!< [7..5] Indicates the division factor to be + used for generating kh_clk. */ + __IM unsigned int : 24; + } IID_CTRL_REG_b; + }; + + union { + __IOM unsigned int WKE_CTRL_REG; /*!< (@ 0x0000000C) none */ + + struct { + __IOM unsigned int ENABLE_WKE : 1; /*!< [0..0] When WKE will be enabled. This + is a self clearing bit. + Once enabled WKE can not be + disabled till process is done */ + __IOM unsigned int WKE_KEY_SIZE : 1; /*!< [1..1] 0 128 bit size 1 256 bit size */ + __IOM unsigned int WKE_FLUSH : 1; /*!< [2..2] When set, WKE will flush out the data from + AES. When WEK is active, firmware reads to AES + engine are masked. This gets cleared once four + dwords are read from AES */ + __IOM unsigned int WKE_COMPARE : 1; /*!< [3..3] When set, WKE will compare the data from + AES engine with the data provided by firmware */ + __IOM unsigned int WKE_SET_KEY : 1; /*!< [4..4] This has to be set after key + available from AES */ + __IOM unsigned int KEY_CODE_DONE : 1; /*!< [5..5] This has to be set after + reading key code */ + __IM unsigned int : 26; + } WKE_CTRL_REG_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int IID_AES_CTRL_REG; /*!< (@ 0x00000014) none */ + + struct { + __IOM unsigned int KEY_REQ_IN_DMA_PATH : 1; /*!< [0..0] Include key req in dma path. With + this KEY Also can be loaded using DMA. */ + __IOM unsigned int AES_MAX_KEY_SIZE_FRM_REG : 1; /*!< [1..1] This is valid + only when + aes_max_key_size_frm_reg_en + is set. */ + __IOM unsigned int AES_MAX_KEY_SIZE_FRM_REG_EN : 1; /*!< [2..2] When set, WKE will flush + out the data from AES. When WEK is + active, firmware reads to AES engine + are masked. This gets cleared once + four dwords are read from AES */ + __IOM unsigned int OTP_KEY_LOADING : 1; /*!< [3..3] When set, WKE will compare + the data from AES engine with the + data provided by firmware */ + __IM unsigned int : 28; + } IID_AES_CTRL_REG_b; + }; + + union { + __IM unsigned int IID_AES_STS_REG; /*!< (@ 0x00000018) none */ + + struct { + __IM unsigned int DIN_FIFO_FULL : 1; /*!< [0..0] Input data fifo full indication */ + __IM unsigned int DOUT_FIFO_EMPTY : 1; /*!< [1..1] Output data fifo empty + indication */ + __IM unsigned int : 30; + } IID_AES_STS_REG_b; + }; + __IM unsigned int RESERVED1; + + union { + __IOM unsigned int WKE_STATUS_REG; /*!< (@ 0x00000020) none */ + + struct { + __IOM unsigned int WKE_ACTIVE : 1; /*!< [0..0] Will be high when WKE is active */ + __IOM unsigned int WKE_KEY_FEED_IN_PROGRESS : 1; /*!< [1..1] Will be high when WKE is + feeding key to AES engine */ + __IOM unsigned int WKE_FLUSH_IN_PROGRESS : 1; /*!< [2..2] Will be high when WKE flushing + out the data from AES */ + __IOM unsigned int WKE_COMPARE_IN_PROGRESS : 1; /*!< [3..3] Will be high when WKE is + comparing the data from AES */ + __IOM unsigned int WKE_SET_KEY_IN_PROGRESS : 1; /*!< [4..4] Will be high when WKE is + doing set key operation with QK */ + __IOM unsigned int WKE_KEY_READY : 1; /*!< [5..5] Firmware has to load the + authentication, which will be + compared with AES output, when this + bit is low */ + __IOM unsigned int WKE_CMP_DATA_READY : 1; /*!< [6..6] Firmware has to load + the authentication, which will + be compared with AES output, + when this bit is low */ + __IOM unsigned int WKE_COMPARE_FAIL : 1; /*!< [7..7] This bit will be set when + authentication data comparison fails */ + __IM unsigned int : 24; + } WKE_STATUS_REG_b; + }; + __IM unsigned int RESERVED2; + __IOM unsigned int WKE_DATA_REG; /*!< (@ 0x00000028) none */ +} IID_RPINE_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== + */ +/* ================ CT0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Configurable timer is used in counting clocks, events and states with + reference clock external clock and system clock (CT0) + */ + +typedef struct { /*!< (@ 0x45060000) CT0 Structure */ + + union { + __IOM unsigned int CT_GEN_CTRL_SET_REG; /*!< (@ 0x00000000) General control set + register */ + + struct { + __IOM unsigned int COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will + be merged and used as a single 32 bit + counter */ + __IOM unsigned int SOFT_RESET_COUNTER_0_FRM_REG : 1; /*!< [1..1] This is applied to 32 + bits of counter only when the + counter is in 32 bit counter mode + otherwise this will be applied + to only lower 16 bits of + counter */ + __IOM unsigned int PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 + bits of counter only when the + counter is in 32 bit counter + mode otherwise this will be + applied + to only lower 16 bits of + counter */ + __IOM unsigned int COUNTER_0_TRIG_FRM_REG : 1; /*!< [3..3] This enables the + counter to run/active */ + __IOM unsigned int COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in + up/down/up-down/down-up directions */ + __IOM unsigned int COUNTER_0_SYNC_TRIG : 1; /*!< [6..6] This is applied to 32 bits of + counter only when the counter is in 32 bit + counter mode otherwise this will be + applied to only lower 16 bits of counter. + This enables the counter to run/active + when sync is found. */ + __IOM unsigned int BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled + for MATCH REG. MATCH_BUF_REG is always + available and whenever this bit is set + only, gets copied to MATCH REG. */ + __IOM unsigned int RESERVED1 : 9; /*!< [16..8] Reserved1 */ + __IOM unsigned int SOFT_RESET_COUNTER_1_FRM_REG : 1; /*!< [17..17] This resets the + counter on the write */ + __IOM unsigned int PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the + counter on the write */ + __IOM unsigned int COUNTER_1_TRIG_FRM : 1; /*!< [19..19] This enables the + counter to run/active */ + __IOM unsigned int COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run + in upward direction */ + __IOM unsigned int COUNTER_1_SYNC_TRIG : 1; /*!< [22..22] This is applied to 32 bits of + counter only when the counter is in 32 bit + counter mode otherwise this will be + applied to only lower 16 bits of + counter. This enables the counter to + run/active when sync is found. */ + __IOM unsigned int BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH + REG. MATCH_BUF_REG is always available and + whenever this bit is set only, gets copied to + MATCH REG. */ + __IOM unsigned int RESERVED2 : 8; /*!< [31..24] Reserved2 */ + } CT_GEN_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int CT_GEN_CTRL_RESET_REG; /*!< (@ 0x00000004) General control + reset register */ + + struct { + __IOM unsigned int COUNTER_IN_32_BIT_MODE : 1; /*!< [0..0] Counter_1 and Counter_0 will + be merged and used as a single 32 bit + counter */ + __IM unsigned int RESERVED1 : 1; /*!< [1..1] Reserved1 */ + __IOM unsigned int PERIODIC_EN_COUNTER_0_FRM_REG : 1; /*!< [2..2] This is applied to 32 + bits of counter only when the + counter is in 32 bit counter + mode otherwise this will be + applied + to only lower 16 bits of + counter */ + __IM unsigned int RESERVED2 : 1; /*!< [3..3] Reserved2 */ + __IOM unsigned int COUNTER_0_UP_DOWN : 2; /*!< [5..4] This enables the counter to run in + up/down/up-down/down-up directions */ + __IM unsigned int RESERVED3 : 1; /*!< [6..6] Reserved3 */ + __IOM unsigned int BUF_REG_0_EN : 1; /*!< [7..7] Buffer register gets enabled + for MATCH REG. MATCH_BUF_REG is always + available and whenever this bit is set + only, gets copied to MATCH REG. */ + __IM unsigned int RESERVED4 : 9; /*!< [16..8] Reserved4 */ + __IM unsigned int RESERVED5 : 1; /*!< [17..17] Reserved5 */ + __IOM unsigned int PERIODIC_EN_COUNTER_1_FRM_REG : 1; /*!< [18..18] This resets the + counter on the write */ + __IM unsigned int RESERVED6 : 1; /*!< [19..19] Reserved6 */ + __IOM unsigned int COUNTER_1_UP_DOWN : 2; /*!< [21..20] This enables the counter to run + in upward direction */ + __IM unsigned int RESERVED7 : 1; /*!< [22..22] Reserved7 */ + __IOM unsigned int BUF_REG_1_EN : 1; /*!< [23..23] Buffer register gets enabled for MATCH + REG. MATCH_BUF_REG is always available and + whenever this bit is set only, gets copied to + MATCH REG. */ + __IM unsigned int RESERVED8 : 8; /*!< [31..24] Reserved8 */ + } CT_GEN_CTRL_RESET_REG_b; + }; + + union { + __IM unsigned int CT_INTR_STS; /*!< (@ 0x00000008) Interrupt status */ + + struct { + __IM unsigned int INTR_0_L : 1; /*!< [0..0] Indicates the FIFO full signal of + channel-0 */ + __IM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Indicates the FIFO full + signal of channel-0 */ + __IM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Counter 0 hit zero in + active mode. */ + __IM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Counter 0 hit peak + (MATCH) in active mode. */ + __IM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IM unsigned int INTR_1_L : 1; /*!< [16..16] Indicates the FIFO full signal + of channel-1 */ + __IM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Indicates the FIFO full + signal of channel-1 */ + __IM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Counter 1 hit zero in + active mode. */ + __IM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Counter 1 hit peak + (MATCH) in active mode. */ + __IM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTR_STS_b; + }; + + union { + __IOM unsigned int CT_INTR_MASK; /*!< (@ 0x0000000C) Interrupts mask */ + + struct { + __IOM unsigned int INTR_0_L : 1; /*!< [0..0] Interrupt mask signal. */ + __IOM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt mask signal. */ + __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt mask signal. */ + __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt mask signal. */ + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM unsigned int INTR_1_L : 1; /*!< [16..16] Interrupt mask signal. */ + __IOM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt mask signal. */ + __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt mask signal. */ + __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt mask signal. */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTR_MASK_b; + }; + + union { + __IOM unsigned int CT_INTER_UNMASK; /*!< (@ 0x00000010) Interrupts unmask */ + + struct { + __IOM unsigned int INTR_0_L : 1; /*!< [0..0] Interrupt unmask signal. */ + __IOM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt unmask signal. */ + __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt unmask signal. */ + __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt unmask signal. */ + __IM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM unsigned int INTR_1_L : 1; /*!< [16..16] Interrupt unmask signal. */ + __IOM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt unmask signal */ + __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt unmask signal. */ + __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt unmask signal. */ + __IM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTER_UNMASK_b; + }; + + union { + __IOM unsigned int CT_INTR_ACK; /*!< (@ 0x00000014) Interrupt clear/ack register */ + + struct { + __IOM unsigned int INTR_0_L : 1; /*!< [0..0] Interrupt ack signal. */ + __IOM unsigned int FIFO_0_FULL_L : 1; /*!< [1..1] Interrupt ack signal. */ + __IOM unsigned int COUNTER_0_IS_ZERO_L : 1; /*!< [2..2] Interrupt ack signal. */ + __IOM unsigned int COUNTER_0_IS_PEAK_L : 1; /*!< [3..3] Interrupt ack signal. */ + __IM unsigned int RESERVED1 : 12; /*!< [15..4] Reserved1 */ + __IOM unsigned int INTR_1_L : 1; /*!< [16..16] Interrupt ack signal. */ + __IOM unsigned int FIFO_1_FULL_L : 1; /*!< [17..17] Interrupt ack signal. */ + __IOM unsigned int COUNTER_1_IS_ZERO_L : 1; /*!< [18..18] Interrupt ack signal. */ + __IOM unsigned int COUNTER_1_IS_PEAK_L : 1; /*!< [19..19] Interrupt ack signal. */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CT_INTR_ACK_b; + }; + + union { + __IOM unsigned int CT_MATCH_REG; /*!< (@ 0x00000018) Match value register */ + + struct { + __IOM unsigned int COUNTER_0_MATCH : 16; /*!< [15..0] This will be used as + lower match */ + __IOM unsigned int COUNTER_1_MATCH : 16; /*!< [31..16] This will be used as + upper match */ + } CT_MATCH_REG_b; + }; + + union { + __IOM unsigned int CT_MATCH_BUF_REG; /*!< (@ 0x0000001C) Match Buffer register */ + + struct { + __IOM unsigned int COUNTER_0_MATCH_BUF : 16; /*!< [15..0] This gets copied to MATCH + register if bug_reg_0_en is set. Copying + is done when counter 0 is active and hits + 0. */ + __IOM unsigned int COUNTER_1_MATCH_BUF : 16; /*!< [31..16] This gets copied to MATCH + register if bug_reg_1_en is set. Copying + is done when counter 1 is active and hits + 0. */ + } CT_MATCH_BUF_REG_b; + }; + + union { + __IM unsigned int CT_CAPTURE_REG; /*!< (@ 0x00000020) Capture Register */ + + struct { + __IM unsigned int COUNTER_0_CAPTURE : 16; /*!< [15..0] This is a latched value of + counter lower part when the selected + capture_event occurs */ + __IM unsigned int COUNTER_1_CAPTURE : 16; /*!< [31..16] This is a latched value of + counter upper part when the selected + capture_event occurs */ + } CT_CAPTURE_REG_b; + }; + + union { + __IOM unsigned int CT_COUNTER_REG; /*!< (@ 0x00000024) Counter Register */ + + struct { + __IM unsigned int COUNTER0 : 16; /*!< [15..0] This holds the value of counter-0 */ + __IM unsigned int COUNTER1 : 16; /*!< [31..16] This holds the value of counter-1 */ + } CT_COUNTER_REG_b; + }; + + union { + __IOM unsigned int CT_OCU_CTRL_REG; /*!< (@ 0x00000028) OCU control register */ + + struct { + __IOM unsigned int OUTPUT_IS_OCU_0 : 1; /*!< [0..0] Indicates whether the output is in + OCU mode or not for channel-0 */ + __IOM unsigned int SYNC_WITH_0 : 3; /*!< [3..1] Indicates whether the other channel is in + sync with this channel */ + __IOM unsigned int OCU_0_DMA_MODE : 1; /*!< [4..4] Indicates whether the OCU DMA mode is + active or not for channel 0 */ + __IOM unsigned int OCU_0_MODE_8_16 : 1; /*!< [5..5] Indicates whether entire 16 bits or + only 8-bits of the channel 0 are used in OCU + mode */ + __IOM unsigned int MAKE_OUTPUT_0_HIGH_SEL : 3; /*!< [8..6] Check counter ocus for + possibilities. When this is hit + output will be made high. */ + __IOM unsigned int MAKE_OUTPUT_0_LOW_SEL : 3; /*!< [11..9] Check counter ocus for + possibilities. When this is hit output + will be made low. */ + __IOM unsigned int RESERVED1 : 4; /*!< [15..12] Reserved1 */ + __IOM unsigned int OUTPUT_1_IS_OCU : 1; /*!< [16..16] Indicates whether the output is in + OCU mode or not for channel 1 */ + __IOM unsigned int SYNC_WITH_1 : 3; /*!< [19..17] Indicates whether the other channel is + in sync with this channel */ + __IOM unsigned int OCU_1_DMA_MODE : 1; /*!< [20..20] Indicates whether the OCU DMA mode + is active or not for channel 1 */ + __IOM unsigned int OCU_1_MODE_8_16_MODE : 1; /*!< [21..21] Indicates whether entire 16 + bits or only 8-bits of + the channel 1 are used in OCU mode */ + __IOM unsigned int MAKE_OUTPUT_1_HIGH_SEL : 3; /*!< [24..22] Check counter ocus for + possibilities. When this is + hit output will be made high. */ + __IOM unsigned int MAKE_OUTPUT_1_LOW_SEL : 3; /*!< [27..25] Check counter ocus for + possibilities. When this is hit output + will be made low. */ + __IOM unsigned int RESERVED2 : 4; /*!< [31..28] Reserved2 */ + } CT_OCU_CTRL_REG_b; + }; + + union { + __IOM unsigned int CT_OCU_COMPARE_REG; /*!< (@ 0x0000002C) OCU Compare Register */ + + struct { + __IOM unsigned int OCU_COMPARE_0_REG : 16; /*!< [15..0] Holds the threshold value of + present OCU period which denotes the number + of clock cycles for which the OCU output + should be considered (counter 0) */ + __IOM unsigned int OCU_COMPARE_1_REG : 16; /*!< [31..16] Holds the threshold value of + present OCU period which denotes the number + of clock cycles for which the OCU output + should be considered (counter 1) */ + } CT_OCU_COMPARE_REG_b; + }; + + union { + __IOM unsigned int CT_OCU_COMPARE2_REG; /*!< (@ 0x00000030) OCU Compare2 Register */ + + struct { + __IOM unsigned int OCU_COMPARE2_0_REG : 16; /*!< [15..0] Holds the threshold + value of present OCU period2 + which denotes the number of + clock cycles for which the OCU + output should be considered + (counter 0) */ + __IOM unsigned int OCU_COMPARE2_1_REG : 16; /*!< [31..16] Holds the threshold + value of present OCU period2 + which denotes the number of + clock cycles for which the OCU + output should be considered + (counter 1) */ + } CT_OCU_COMPARE2_REG_b; + }; + + union { + __IOM unsigned int CT_OCU_SYNC_REG; /*!< (@ 0x00000034) OCU Synchronization Register */ + + struct { + __IOM unsigned int OCU_SYNC_CHANNEL0_REG : 16; /*!< [15..0] Starting point of channel 0 + for synchronization purpose */ + __IOM unsigned int OCU_SYNC_CHANNEL1_REG : 16; /*!< [31..16] Starting point of channel 1 + for synchronization purpose */ + } CT_OCU_SYNC_REG_b; + }; + + union { + __IOM unsigned int CT_OCU_COMPARE_NXT_REG; /*!< (@ 0x00000038) PWM compare next + register */ + + struct { + __IOM unsigned int OCU_COMPARE_NXT_COUNTER1 : 16; /*!< [15..0] OCU output should be high + for counter 1 */ + __IOM unsigned int OCU_COMPARE_NXT_COUNTER0 : 16; /*!< [31..16] PWM output should be high + for counter 0 */ + } CT_OCU_COMPARE_NXT_REG_b; + }; + + union { + __IOM unsigned int CT_WFG_CTRL_REG; /*!< (@ 0x0000003C) WFG control register */ + + struct { + __IOM unsigned int MAKE_OUTPUT_0_TGL_0_SEL : 3; /*!< [2..0] Check the counter ocus + possibilities for description for + channel 0. */ + __IOM unsigned int MAKE_OUTPUT_0_TGL_1_SEL : 3; /*!< [5..3] Check the counter ocus + possibilities for description for + channel 0. */ + __IOM unsigned int RESERVED1 : 2; /*!< [7..6] Reserved1 */ + __IOM unsigned int WFG_TGL_CNT_0_PEAK : 8; /*!< [15..8] WFG mode output toggle + count clock for channel 0. */ + __IOM unsigned int MAKE_OUTPUT_1_TGL_0_SEL : 3; /*!< [18..16] Check the counter ocus + possibilities for description for + channel 1. */ + __IOM unsigned int MAKE_OUTPUT_1_TGL_1_SEL : 3; /*!< [21..19] Check the counter ocus + possibilities for description for + channel 1. */ + __IOM unsigned int RESERVED2 : 2; /*!< [23..22] Reserved2 */ + __IOM unsigned int WFG_TGL_CNT_1_PEAK : 8; /*!< [31..24] WFG mode output toggle count + clock for channel 1 */ + } CT_WFG_CTRL_REG_b; + }; + + union { + __IOM unsigned int CT_OCU_COMPARE2_NXT_REG; /*!< (@ 0x00000040) PWM compare next + register */ + + struct { + __IOM unsigned int OCU_COMPARE2_NXT_COUNTER0 : 16; /*!< [15..0] OCU output should be high + for counter 1 */ + __IOM unsigned int OCU_COMPARE2_NXT_COUNTER1 : 16; /*!< [31..16] PWM output should be + high for counter 0 */ + } CT_OCU_COMPARE2_NXT_REG_b; + }; + __IM unsigned int RESERVED[3]; + + union { + __IOM unsigned int CT_START_COUNTER_EVENT_SEL; /*!< (@ 0x00000050) Start counter + event select register */ + + struct { + __IOM unsigned int START_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for starting the + Counter 0 For 32 bit counter mode: + Event select for starting counter */ + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int START_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for starting the + Counter 1. For 32 bit counter mode: + Invalid. Please refer to events + table for description */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_START_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_START_COUNTER_AND_EVENT; /*!< (@ 0x00000054) Start counter + AND event register */ + + struct { + __IOM unsigned int START_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: AND expression valids for AND + event in start Counter 0 event For 32 + bit counter mode + AND expression valids for AND event in + start counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int START_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int START_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in start counter event For 32 + bit counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int START_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_START_COUNTER_AND_EVENT_b; + }; + + union { + __IOM unsigned int CT_START_COUNTER_OR_EVENT; /*!< (@ 0x00000058) Start counter + OR event register */ + + struct { + __IOM unsigned int START_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + OR expression valids for OR event in + start Counter 0 event For 32 bit + counter mode + OR expression valids for OR event in + start counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int START_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int START_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in start counter event For 32 + bit counter mode : Invalid. */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int START_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_START_COUNTER_OR_EVENT_b; + }; + + union { + __IOM unsigned int CT_CONTINUE_COUNTER_EVENT_SEL; /*!< (@ 0x0000005C) Continue counter + event select register */ + + struct { + __IOM unsigned int CONTINUE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for continuing + the Counter 0 For 32 bit + counter mode: Event select for + continuing counter */ + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int CONTINUE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit + counters mode: Event select for + continuing + the Counter 1 For 32 bit + counter mode: Invalid. */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_CONTINUE_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_CONTINUE_COUNTER_AND_EVENT; /*!< (@ 0x00000060) Continue counter AND + event register */ + + struct { + __IOM unsigned int CONTINUE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: AND expression valids for + AND event in continue + Counter 0 event For 32 bit + counter mode AND expression + valids for AND event in continue + counter event. */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CONTINUE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CONTINUE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit + counters mode: AND expression + valids for AND event in continue + counter event For 32 bit counter + mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CONTINUE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CONTINUE_COUNTER_AND_EVENT_b; + }; + + union { + __IOM unsigned int CT_CONTINUE_COUNTER_OR_EVENT; /*!< (@ 0x00000064) Continue counter OR + event register */ + + struct { + __IOM unsigned int CONTINUE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: OR expression valids for OR + event in continue Counter 0 event For + 32 bit counter mode OR expression + valids for OR event in continue + counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CONTINUE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CONTINUE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in continue counter event For + 32 bit counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CONTINUE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CONTINUE_COUNTER_OR_EVENT_b; + }; + + union { + __IOM unsigned int CT_STOP_COUNTER_EVENT_SEL; /*!< (@ 0x00000068) Stop counter + event select register */ + + struct { + __IOM unsigned int STOP_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for Stopping the + Counter 0 For 32 bit counter mode: + Event select for Stopping counter */ + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int STOP_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for Stopping the + Counter 1 For 32 bit counter mode: + Invalid */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_STOP_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_STOP_COUNTER_AND_EVENT; /*!< (@ 0x0000006C) Stop counter + AND event register */ + + struct { + __IOM unsigned int STOP_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + AND expression valids for AND event in + stop Counter 0 event For 32 bit + counter mode + AND expression valids for AND event in + stop counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int STOP_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which + bits in 3:0 are valid for + considering AND event */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int STOP_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in stop counter event For 32 bit + counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int STOP_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_STOP_COUNTER_AND_EVENT_b; + }; + + union { + __IOM unsigned int CT_STOP_COUNTER_OR_EVENT; /*!< (@ 0x00000070) Stop counter OR + event register */ + + struct { + __IOM unsigned int STOP_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + OR expression valids for OR event in + Stop Counter 0 event For 32 bit + counter mode + OR expression valids for OR event in + Stop counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int STOP_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IOM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int STOP_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in Stop counter event For 32 bit + counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int STOP_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_STOP_COUNTER_OR_EVENT_b; + }; + + union { + __IOM unsigned int CT_HALT_COUNTER_EVENT_SEL; /*!< (@ 0x00000074) Halt counter + event select register */ + + struct { + __IOM unsigned int HALT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for Halting the + Counter 0 For 32 bit counter mode: + Event select for Halting counter */ + __OM unsigned int RESUME_FROM_HALT_COUNTER_0 : 1; /*!< [6..6] For two 16 bit counters + mode: Event select for Halting the + Counter 0 For 32 bit counter mode: + Event select for Halting counter */ + __IM unsigned int RESERVED1 : 9; /*!< [15..7] Reserved1 */ + __IOM unsigned int HALT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for Halting the + Counter 1 For 32 bit counter mode: + Invalid */ + __OM unsigned int RESUME_FROM_HALT_COUNTER_1 : 1; /*!< [22..22] For two 16 bit + counters mode: Event select for + Halting the Counter 0 For 32 + bit counter mode: Event select + for Halting counter */ + __IM unsigned int RESERVED2 : 9; /*!< [31..23] Reserved2 */ + } CT_HALT_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_HALT_COUNTER_AND_EVENT; /*!< (@ 0x00000078) Halt counter + AND event register */ + + struct { + __IOM unsigned int HALT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + AND expression valids for AND event in + stop Counter 0 event For 32 bit + counter mode + AND expression valids for AND event in + stop counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int HALT_COUNTER_0_AND_VLD : 4; /*!< [11..8] Indicates which + bits in 3:0 are valid for + considering AND event */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int HALT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in stop counter event For 32 bit + counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int HALT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_HALT_COUNTER_AND_EVENT_b; + }; + + union { + __IOM unsigned int CT_HALT_COUNTER_OR_EVENT; /*!< (@ 0x0000007C) Halt counter OR + event register */ + + struct { + __IOM unsigned int HALT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter mode: + OR expression valids for OR event in + Halt Counter 0 event For 32 bit + counter mode + OR expression valids for OR event in + Halt counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int HALT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int HALT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in Halt counter event For 32 bit + counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int HALT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_HALT_COUNTER_OR_EVENT_b; + }; + + union { + __IOM unsigned int CT_INCREMENT_COUNTER_EVENT_SEL; /*!< (@ 0x00000080) Increment counter + event select register */ + + struct { + __IOM unsigned int INCREMENT_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for + Incrementing the Counter 0 For + 32 bit counter mode: Event + select for + Incrementing counter */ + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int INCREMENT_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 + bit counters mode: + Event select for + Incrementing the + Counter 1 For 32 bit + counter mode: Invalid + */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_INCREMENT_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_INCREMENT_COUNTER_AND_EVENT; /*!< (@ 0x00000084) Increment counter + AND event register */ + + struct { + __IOM unsigned int INCREMENT_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: AND expression valids for + AND event in stop Counter + 0 event For 32 bit counter mode + AND expression valids for + AND event in stop counter event + */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INCREMENT_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INCREMENT_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit + counters mode: AND expression + valids for AND event in stop + counter event For 32 bit counter + mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int INCREMENT_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_INCREMENT_COUNTER_AND_EVENT_b; + }; + + union { + __IOM unsigned int CT_INCREMENT_COUNTER_OR_EVENT; /*!< (@ 0x00000088) Increment counter OR + event register */ + + struct { + __IOM unsigned int INCREMENT_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: OR expression valids for OR + event in Increment Counter 0 + event For 32 bit counter mode OR + expression valids for OR event in + Increment counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INCREMENT_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INCREMENT_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit + counters mode: OR expression valids + for OR event in Increment counter + event For 32 bit counter mode : + Invalid */ + __IM unsigned int RESERVED4 : 4; /*!< [23..20] Reserved4 */ + __IOM unsigned int INCREMENT_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED5 : 4; /*!< [31..28] Reserved5 */ + } CT_INCREMENT_COUNTER_OR_EVENT_b; + }; + + union { + __IOM unsigned int CT_CAPTURE_COUNTER_EVENT_SEL; /*!< (@ 0x0000008C) Capture counter event + select register */ + + struct { + __IOM unsigned int CAPTURE_COUNTER_0_EVENT_SEL : 6; /*!< [5..0] For two 16 bit counters + mode: Event select for Capturing + the Counter 0 For 32 bit + counter mode: Event select for + Capturing counter */ + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int CAPTURE_COUNTER_1_EVENT_SEL : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for Capturing + the Counter 1 For 32 bit + counter mode : Invalid */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_CAPTURE_COUNTER_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_CAPTURE_COUNTER_AND_EVENT; /*!< (@ 0x00000090) Capture counter AND + event register */ + + struct { + __IOM + unsigned int CAPTURE_COUNTER_0_AND_EVENT : 4; /*!< [3..0] For two 16 bit + counter mode: AND expression + valids for AND event in stop + Counter 0 event For 32 bit + counter mode AND expression + valids for AND event in stop + counter event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CAPTURE_COUNTER_0_AND_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CAPTURE_COUNTER_1_AND_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: AND expression valids for AND + event in stop counter event For 32 bit + counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CAPTURE_COUNTER_1_AND_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CAPTURE_COUNTER_AND_EVENT_b; + }; + + union { + __IOM unsigned int CT_CAPTURE_COUNTER_OR_EVENT; /*!< (@ 0x00000094) Capture counter OR + event register */ + + struct { + __IOM unsigned int CAPTURE_COUNTER_0_OR_EVENT : 4; /*!< [3..0] For two 16 bit counter + mode: OR expression valids for OR + event in Capture Counter 0 event For + 32 bit counter mode OR expression + valids for OR event in Capture counter + event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int CAPTURE_COUNTER_0_OR_VLD : 4; /*!< [11..8] none */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int CAPTURE_COUNTER_1_OR_EVENT : 4; /*!< [19..16] For two 16 bit counters + mode: OR expression valids for OR + event in Capture counter event For 32 + bit counter mode : Invalid */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int CAPTURE_COUNTER_1_OR_VLD : 4; /*!< [27..24] none */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_CAPTURE_COUNTER_OR_EVENT_b; + }; + + union { + __IOM unsigned int CT_OUTPUT_EVENT_SEL; /*!< (@ 0x00000098) Output event select + register */ + + struct { + __IOM unsigned int OUTPUT_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: + Event select for output event from Counter + 0 For 32 bit counter mode: Event select + for output event */ + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int OUTPUT_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters mode: + Event select for output + event from counter 1 For 32 bit + counter mode : Invalid */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_OUTPUT_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_OUTPUT_AND_EVENT_REG; /*!< (@ 0x0000009C) Output AND event + Register */ + + struct { + __IOM unsigned int OUTPUT_0_AND_EVENT : 4; /*!< [3..0] AND expression for AND event in + output Counter_0 event. */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int OUTPUT_0_AND_VLD : 4; /*!< [11..8] AND expression for AND event in + output Counter_0 event. */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int OUTPUT_1_AND_EVENT : 4; /*!< [19..16] AND expression for AND event in + output Counter_1 event. */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int OUTPUT_1_AND_VLD : 4; /*!< [27..24] AND expression for AND event in + output Counter_1 event. */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_OUTPUT_AND_EVENT_REG_b; + }; + + union { + __IOM unsigned int CT_OUTPUT_OR_EVENT; /*!< (@ 0x000000A0) Output OR event Register */ + + struct { + __IOM unsigned int OUTPUT_0_OR_EVENT : 4; /*!< [3..0] OR expression for OR event in + output Counter_0 event */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int OUTPUT_0_OR_VLD : 4; /*!< [11..8] Indicates which bits in 3:0 are + valid for considering OR event */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int OUTPUT_1_OR_EVENT : 4; /*!< [19..16] OR expression for OR event in + output Counter_0 event */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int OUTPUT_1_OR_VLD : 4; /*!< [27..24] Indicates which bits in 3:0 are + valid for considering OR event */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_OUTPUT_OR_EVENT_b; + }; + + union { + __IOM unsigned int CT_INTR_EVENT_SEL; /*!< (@ 0x000000A4) Interrupt Event Select + Register */ + + struct { + __IOM unsigned int INTR_EVENT_SEL_0 : 6; /*!< [5..0] For two 16 bit counters mode: Event + select for interrupt event from Counter 0 For + 32 bit counter mode: Event select + for output event */ + __IM unsigned int RESERVED1 : 10; /*!< [15..6] Reserved1 */ + __IOM unsigned int INTR_EVENT_SEL_1 : 6; /*!< [21..16] For two 16 bit counters + mode: Event select for interrupt + event from counter 1 For 32 + bit counter mode : Invalid */ + __IM unsigned int RESERVED2 : 10; /*!< [31..22] Reserved2 */ + } CT_INTR_EVENT_SEL_b; + }; + + union { + __IOM unsigned int CT_INTR_AND_EVENT; /*!< (@ 0x000000A8) Interrupt AND Event Register */ + + struct { + __IOM unsigned int INTR_0_AND_EVENT : 4; /*!< [3..0] None */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INTR_0_AND_VLD : 4; /*!< [11..8] None */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INTR_1_AND_EVENT : 4; /*!< [19..16] None */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int INTR_1_AND_VLD : 4; /*!< [27..24] None */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_INTR_AND_EVENT_b; + }; + + union { + __IOM unsigned int CT_INTR_OR_EVENT_REG; /*!< (@ 0x000000AC) Interrupt OR Event + Register */ + + struct { + __IOM unsigned int INTR_0_OR_EVENT : 4; /*!< [3..0] None */ + __IOM unsigned int RESERVED1 : 4; /*!< [7..4] Reserved1 */ + __IOM unsigned int INTR_0_OR_VLD : 4; /*!< [11..8] None */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] Reserved2 */ + __IOM unsigned int INTR_1_OR_EVENT : 4; /*!< [19..16] None */ + __IM unsigned int RESERVED3 : 4; /*!< [23..20] Reserved3 */ + __IOM unsigned int INTR_1_OR_VLD : 4; /*!< [27..24] None */ + __IM unsigned int RESERVED4 : 4; /*!< [31..28] Reserved4 */ + } CT_INTR_OR_EVENT_REG_b; + }; +} CT0_Type; /*!< Size = 176 (0xb0) */ + +/* =========================================================================================================================== + */ +/* ================ CT_MUX_REG + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief Configurable timer is used in counting clocks, events and states with + reference clock external clock and system clock (CT_MUX_REG) + */ + +typedef struct { /*!< (@ 0x4506F000) CT_MUX_REG Structure */ + + union { + __IOM unsigned int CT_MUX_SEL_0_REG; /*!< (@ 0x00000000) MUX_SEL_0_REG Register */ + + struct { + __IOM unsigned int MUX_SEL_0 : 4; /*!< [3..0] Select value to select first output value + fifo_0_full[0] out of all the fifo_0_full_muxed + signals of counter 0 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_0_REG_b; + }; + + union { + __IOM unsigned int CT_MUX_SEL_1_REG; /*!< (@ 0x00000004) MUX_SEL_1_REG Register */ + + struct { + __IOM unsigned int MUX_SEL_1 : 4; /*!< [3..0] Select value to select first output value + fifo_0_full[1] out of all the fifo_0_full_muxed + signals of counter 0 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_1_REG_b; + }; + + union { + __IOM unsigned int CT_MUX_SEL_2_REG; /*!< (@ 0x00000008) MUX_SEL_2_REG Register */ + + struct { + __IOM unsigned int MUX_SEL_2 : 4; /*!< [3..0] Select value to select first output value + fifo_1_full[0] out of all the fifo_1_full_muxed + signals of counter 1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_2_REG_b; + }; + + union { + __IOM unsigned int CT_MUX_SEL_3_REG; /*!< (@ 0x0000000C) MUX_SEL_3_REG Register */ + + struct { + __IOM unsigned int MUX_SEL_3 : 4; /*!< [3..0] Select value to select first output value + fifo_1_full[1] out of all the fifo_1_full_muxed + signals of counter 1 */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_MUX_SEL_3_REG_b; + }; + __IM unsigned int RESERVED[2]; + + union { + __IOM unsigned int CT_OUTPUT_EVENT1_ADC_SEL; /*!< (@ 0x00000018) OUTPUT_EVENT_ADC_SEL + Register */ + + struct { + __IOM + unsigned int OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one + output event out of all the output + events output_event_0 output_event_1, + output_event_2, output_event_3 to + enable ADC module */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_OUTPUT_EVENT1_ADC_SEL_b; + }; + + union { + __IOM unsigned int CT_OUTPUT_EVENT2_ADC_SEL; /*!< (@ 0x0000001C) OUTPUT_EVENT_ADC_SEL + Register */ + + struct { + __IOM + unsigned int OUTPUT_EVENT_ADC_SEL : 4; /*!< [3..0] Select signals to select one + output event out of all the output + events output_event_0 output_event_1, + output_event_2, output_event_3 to + enable ADC module */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] Reserved1 */ + } CT_OUTPUT_EVENT2_ADC_SEL_b; + }; +} CT_MUX_REG_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== + */ +/* ================ EGPIO + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief ENHANCED GENERAL PERPOSE INPUT/OUTPUT (EGPIO) + */ + +typedef struct { /*!< (@ 0x46130000) EGPIO Structure */ + __IOM EGPIO_PIN_CONFIG_Type PIN_CONFIG[80]; /*!< (@ 0x00000000) [0..79] */ + __IM unsigned int RESERVED[704]; + __IOM EGPIO_PORT_CONFIG_Type PORT_CONFIG[6]; /*!< (@ 0x00001000) [0..5] */ + __IM unsigned int RESERVED1[80]; + __IOM EGPIO_INTR_Type INTR[8]; /*!< (@ 0x00001200) [0..7] */ + __IOM EGPIO_GPIO_GRP_INTR_Type GPIO_GRP_INTR[4]; /*!< (@ 0x00001240) [0..3] */ +} EGPIO_Type; /*!< Size = 4704 (0x1260) */ + +/* =========================================================================================================================== + */ +/* ================ SDIO0 + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The Secure Digital I/O (SDIO) Slave module implements the + * functionality of the SDIO card based on the SDIO specifications version 2.0. + * (SDIO0) + */ + +typedef struct { /*!< (@ 0x40000000) SDIO0 Structure */ + + union { + __IOM unsigned int SDIO_INTR_FN1_STATUS_CLEAR_REG; /*!< (@ 0x00000000) SDIO Function1 + Interrupt Enable Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int SDIO_WR_RDZ : 1; /*!< [8..8] SDIO_WR_RDZ */ + __IOM unsigned int SDIO_CSA_ACCESS : 1; /*!< [9..9] csa_window_access When set, indicates + that current request is for CSA window + register. This is only status signal */ + __IOM unsigned int RES : 22; /*!< [31..10] reserved1 */ + } SDIO_INTR_FN1_STATUS_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN1_ENABLE_REG; /*!< (@ 0x00000004) SDIO Function1 + Interrupt Enable Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN1_ENABLE_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN1_MASK_REG; /*!< (@ 0x00000008) SDIO Function1 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN1_MASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN1_UNMASK_REG; /*!< (@ 0x0000000C) SDIO Function1 + Interrupt UnMask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN1_UNMASK_REG_b; + }; + + union { + __IM unsigned int SDIO_BLK_LEN_REG; /*!< (@ 0x00000010) SDIO Block Length Register */ + + struct { + __IM unsigned int SDIO_BLK_LEN : 12; /*!< [11..0] Length of each block for the + last received CMD53 */ + __IM unsigned int RES : 20; /*!< [31..12] reserved5 */ + } SDIO_BLK_LEN_REG_b; + }; + + union { + __IM unsigned int SDIO_BLK_CNT_REG; /*!< (@ 0x00000014) SDIO Block Length Register */ + + struct { + __IM unsigned int SDIO_BLK_CNT : 9; /*!< [8..0] Block count for the last + received CMD53 */ + __IM unsigned int RES : 23; /*!< [31..9] reserved5 */ + } SDIO_BLK_CNT_REG_b; + }; + + union { + __IM unsigned int SDIO_ADDRESS_REG; /*!< (@ 0x00000018) SDIO Address Register */ + + struct { + __IM unsigned int SDIO_ADDR : 16; /*!< [15..0] Lower 16-bits of the 17-bit address field + in the last received CMD53 */ + __IM unsigned int RES : 16; /*!< [31..16] reserved5 */ + } SDIO_ADDRESS_REG_b; + }; + __IOM unsigned int SDIO_CMD52_RDATA_REGISTER; /*!< (@ 0x0000001C) SDIO CMD52 RDATA + Register */ + __IOM unsigned int SDIO_CMD52_WDATA_REGISTER; /*!< (@ 0x00000020) SDIO CMD52 WDATA + Register */ + + union { + __IM unsigned int SDIO_INTR_STATUS_REG; /*!< (@ 0x00000024) SDIO Interrupt + Status Register */ + + struct { + __IM unsigned int SDIO_INT_ERROR : 1; /*!< [0..0] Interrupt is pending because of error + condition from any of the functions */ + __IM unsigned int SDIO_INT_FN1 : 1; /*!< [1..1] Interrupt is pending for function1 */ + __IM unsigned int SDIO_INT_FN2 : 1; /*!< [2..2] Interrupt is pending for function2 */ + __IM unsigned int SDIO_INT_FN3 : 1; /*!< [3..3] Interrupt is pending for function3 */ + __IM unsigned int SDIO_INT_FN4 : 1; /*!< [4..4] Interrupt is pending for function4 */ + __IM unsigned int SDIO_INT_FN5 : 1; /*!< [5..5] Interrupt is pending for function5 */ + __IM unsigned int RES : 26; /*!< [31..6] reserved5 */ + } SDIO_INTR_STATUS_REG_b; + }; + + union { + __IM unsigned int SDIO_INTR_FN_NUMBER_REG; /*!< (@ 0x00000028) SDIO Interrupt + Function Number Register */ + + struct { + __IM unsigned int SDIO_INTR_FN_NUM : 3; /*!< [2..0] Indicates the function number to + which interrupt is pending. */ + __IM unsigned int RES : 29; /*!< [31..3] reserved5 */ + } SDIO_INTR_FN_NUMBER_REG_b; + }; + + union { + __IM unsigned int SDIO_FIFO_STATUS_REG; /*!< (@ 0x0000002C) SDIO FIFO Status Register */ + + struct { + __IM unsigned int SDIO_WFIFO_FULL : 1; /*!< [0..0] When set, indicates that + WFIFO is full WFIFO is used + in SDIO reads from host for + sending data from AHB to Host */ + __IM unsigned int SDIO_WFIFO_AFULL : 1; /*!< [1..1] When set, indicates that + WFIFO is almost full */ + __IM unsigned int SDIO_RFIFO_EMPTY : 1; /*!< [2..2] When set, indicates that RFIFO is + empty RFIFO is used in SDIO writes from host + for sending data from host to AHB */ + __IM unsigned int SDIO_RFIFO_AEMPTY : 1; /*!< [3..3] When set, indicates that + RFIFO is almost empty */ + __IM unsigned int SDIO_CURRENT_FN_NUM : 3; /*!< [6..4] Indicates the function number of + the last received command */ + __IM unsigned int SDIO_BUS_CONTROL_STATE : 5; /*!< [11..7] Indicates the function number + of the last received command */ + __IM unsigned int RES : 20; /*!< [31..12] reserved5 */ + } SDIO_FIFO_STATUS_REG_b; + }; + + union { + __IM unsigned int SDIO_FIFO_OCC_REG; /*!< (@ 0x00000030) SDIO FIFO Occupancy Register */ + + struct { + __IM unsigned int SDIO_WFIFO_OCC : 8; /*!< [7..0] Indicates the occupancy + level of the write FIFO */ + __IM unsigned int SDIO_RFIFO_AVAIL : 8; /*!< [15..8] Indicates the available + space in the read FIFO */ + __IM unsigned int RES : 16; /*!< [31..16] reserved5 */ + } SDIO_FIFO_OCC_REG_b; + }; + + union { + __IOM unsigned int SDIO_HOST_INTR_SET_REG; /*!< (@ 0x00000034) SDIO Host + Interrupt Set Register */ + + struct { + __IOM unsigned int SDIO_INTSET_FN2 : 1; /*!< [0..0] This bit is used to raise an + interrupt to host for function2. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM unsigned int SDIO_INTSET_FN3 : 1; /*!< [1..1] This bit is used to raise an + interrupt to host for function3. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM unsigned int SDIO_INTSET_FN4 : 1; /*!< [2..2] This bit is used to raise an + interrupt to host for function4. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM unsigned int SDIO_INTSET_FN5 : 1; /*!< [3..3] This bit is used to raise an + interrupt to host for function5. Setting this + bit will raise the interrupt Clearing this + bit has no effect */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved5 */ + } SDIO_HOST_INTR_SET_REG_b; + }; + + union { + __IOM unsigned int SDIO_HOST_INTR_CLEAR_REG; /*!< (@ 0x00000038) SDIO Host + Interrupt Clear Register */ + + struct { + __IOM unsigned int SDIO_INTCLR_FN2 : 1; /*!< [0..0] This bit is used to clear the + interrupt to host for function2. Setting this + bit will clear the interrupt Clearing this + bit has no effect */ + __IOM unsigned int SDIO_INTCLR_FN3 : 1; /*!< [1..1] This bit is used to clear the + interrupt to host for function3. Setting this + bit will clear the interrupt Clearing this + bit has no effect */ + __IOM unsigned int SDIO_INTCLR_FN4 : 1; /*!< [2..2] This bit is used to clear the + interrupt to host for function4. Setting this + bit will clear the interrupt Clearing this + bit has no effectt */ + __IOM unsigned int SDIO_INTCLR_FN5 : 1; /*!< [3..3] This bit is used to clear the + interrupt to host for function5. Setting this + bit will clear the interrupt Clearing this + bit has no effect */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved5 */ + } SDIO_HOST_INTR_CLEAR_REG_b; + }; + __IM unsigned int RESERVED; + + union { + __OM unsigned int SDIO_RFIFO_DATA_REG[16]; /*!< (@ 0x00000040) SDIO Read FIFO + Data Register */ + + struct { + __OM unsigned int SDIO_RFIFO : 32; /*!< [31..0] Data to be written into SDIO Read FIFO + has to be written in this register. */ + } SDIO_RFIFO_DATA_REG_b[16]; + }; + + union { + __IM unsigned int SDIO_WFIFO_DATA_REG[16]; /*!< (@ 0x00000080) SDIO Write FIFO + Data Register */ + + struct { + __IM unsigned int SDIO_WFIFO : 32; /*!< [31..0] SDIO Write FIFO data can be + read through this register. */ + } SDIO_WFIFO_DATA_REG_b[16]; + }; + + union { + __IOM unsigned int SDIO_INTR_FN2_STATUS_CLEAR_REG; /*!< (@ 0x000000C0) SDIO Function2 + Status Clear Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_STATUS_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN2_ENABLE_REG; /*!< (@ 0x000000C4) SDIO Function1 + Interrupt Enable Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_ENABLE_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN2_MASK_REG; /*!< (@ 0x000000C8) SDIO Function2 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_MASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN2_UNMASK_REG; /*!< (@ 0x000000CC) SDIO Function2 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN2_UNMASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN3_STATUS_CLEAR_REG; /*!< (@ 0x000000D0) SDIO Function3 + Status Clear Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_STATUS_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN3_ENABLE_REG; /*!< (@ 0x000000D4) SDIO Function3 + Interrupt Enable Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_ENABLE_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN3_MASK_REG; /*!< (@ 0x000000D8) SDIO Function3 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_MASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN3_UNMASK_REG; /*!< (@ 0x000000DC) SDIO Function3 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN3_UNMASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN4_STATUS_CLEAR_REG; /*!< (@ 0x000000E0) SDIO Function4 + Status Clear Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_STATUS_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN4_ENABLE_REG; /*!< (@ 0x000000E4) SDIO Function4 + Interrupt Enable Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_ENABLE_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN4_MASK_REG; /*!< (@ 0x000000E8) SDIO Function4 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_MASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN4_UNMASK_REG; /*!< (@ 0x000000EC) SDIO Function4 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN4_UNMASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN5_STATUS_CLEAR_REG; /*!< (@ 0x000000F0) SDIO Function5 + Status Clear Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_CLR : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. =1 + Interrupt is enabled =0 - + Interrupt is disabled */ + __IOM unsigned int SDIO_RD_INT_CLR : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_CLR : 1; /*!< [2..2] This bit is used to + enable CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_CLR : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_CLR : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_CLR : 1; /*!< [5..5] This bit is used to enable CRC + error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_CLR : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_CLR : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_STATUS_CLEAR_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN5_ENABLE_REG; /*!< (@ 0x000000F4) SDIO Function5 + Interrupt Enable Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + CMD53 write interrupt. */ + __IOM unsigned int SDIO_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_INT_EN : 1; /*!< [2..2] This bit is used to enable + CMD53 CSA interrupt */ + __IOM unsigned int SDIO_CMD52_INT_EN : 1; /*!< [3..3] This bit is used to + enable CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_INT_EN : 1; /*!< [4..4] This bit is used to enable power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_INT_EN : 1; /*!< [5..5] This bit is used to + enable CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_INT_EN : 1; /*!< [6..6] This bit is used to + enable abort interrupt */ + __IOM unsigned int SDIO_TOUT_INT_EN : 1; /*!< [7..7] This bit is used to enable ?read + FIFO wait time over? interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_ENABLE_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN5_MASK_REG; /*!< (@ 0x000000F8) SDIO Function5 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_MSK : 1; /*!< [0..0] This bit is used to mask + CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_MSK : 1; /*!< [1..1] This bit is used to mask + CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_MSK : 1; /*!< [2..2] This bit is used to mask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_MSK : 1; /*!< [3..3] This bit is used to mask + CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_MSK : 1; /*!< [4..4] This bit is used to mask + power level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_MSK : 1; /*!< [5..5] This bit is used to mask + CRC error interrupt */ + __IOM unsigned int SDIO_ABORT_MSK : 1; /*!< [6..6] This bit is used to mask abort + interrupt Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_TOUT_MSK : 1; /*!< [7..7] This bit is used to mask read FIFO wait + time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_MASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_INTR_FN5_UNMASK_REG; /*!< (@ 0x000000FC) SDIO Function5 + Interrupt Mask Register */ + + struct { + __IOM unsigned int SDIO_WR_INT_UNMSK : 1; /*!< [0..0] This bit is used to + unmask CMD53 write interrupt */ + __IOM unsigned int SDIO_RD_INT_UNMSK : 1; /*!< [1..1] This bit is used to + unmask CMD53 read interrupt */ + __IOM unsigned int SDIO_CSA_UNMSK : 1; /*!< [2..2] This bit is used to unmask CMD53 CSA + interrupt.Setting this bit will mask the + interrupt Clearing this bit has no effect */ + __IOM unsigned int SDIO_CMD52_UNMSK : 1; /*!< [3..3] This bit is used to + unmask CMD52 interrupt */ + __IOM unsigned int SDIO_PWR_LEV_UNMSK : 1; /*!< [4..4] This bit is used to unmask power + level change interrupt */ + __IOM unsigned int SDIO_CRC_ERR_UNMSK : 1; /*!< [5..5] This bit is used to + unmask CRC error interrupt */ + __IOM + unsigned int SDIO_ABORT_UNMSK : 1; /*!< [6..6] This bit is used to unmask + abort interrupt Setting this bit + will mask the interrupt Clearing + this bit has no effect */ + __IOM unsigned int SDIO_TOUT_UNMSK : 1; /*!< [7..7] This bit is used to unmask read FIFO + wait time over interrupt */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved5 */ + } SDIO_INTR_FN5_UNMASK_REG_b; + }; + + union { + __IOM unsigned int SDIO_ERROR_COND_CHK_ENABLE_REG; /*!< (@ 0x00000100) SDIO error condition + check enable register */ + + struct { + __IOM unsigned int SDIO_CRC_EN : 1; /*!< [0..0] When set, stops the DMA from doing data + accesses till CRC error interrupt is cleared */ + __IOM unsigned int SDIO_ABORT_EN : 1; /*!< [1..1] When set, stops the DMA from doing data + accesses till ABORT interrupt is cleared */ + __IOM unsigned int SDIO_SPI_RD_DATA_ERROR_EN : 1; /*!< [2..2] When set, stops the DMA + from doing data accesses till read + data error interrupt is cleared in SPI + mode */ + __IOM unsigned int RES : 29; /*!< [31..3] reserved5 */ + } SDIO_ERROR_COND_CHK_ENABLE_REG_b; + }; + + union { + __IOM unsigned int SDIO_ERROR_COND_STATE_REG; /*!< (@ 0x00000104) SDIO error + condition state register */ + + struct { + __IOM unsigned int SDIO_ERROR_BYTE_CNT : 12; /*!< [11..0] Indicates byte count when one + of the error condition occurred */ + __IOM unsigned int RESERVED1 : 4; /*!< [15..12] RESERVED1 */ + __IOM unsigned int SDIO_ERROR_BLK_CNT : 7; /*!< [22..16] Indicates block count when one + of error condition occurred */ + __IOM unsigned int RESERVED2 : 9; /*!< [31..23] RESERVED2 */ + } SDIO_ERROR_COND_STATE_REG_b; + }; + + union { + __IM unsigned int SDIO_BOOT_CONFIG_VALS_0_REG; /*!< (@ 0x00000108) SDIO Boot + Config Values Register 0 */ + + struct { + __IM unsigned int OCR_R : 24; /*!< [23..0] Operating conditions. The value + written by bootloader can be read here. */ + __IM unsigned int CSA_MSBYTE : 8; /*!< [31..24] MS byre of CSA address. Lower + 24 bits of CSA will come through SDIO CSA + registers. Whenever CSA access is + done, 32-bit address will + be prepared using these fields. */ + } SDIO_BOOT_CONFIG_VALS_0_REG_b; + }; + + union { + __IM unsigned int SDIO_BOOT_CONFIG_VALS_1_REG; /*!< (@ 0x0000010C) SDIO Boot + Config Values Register 1 */ + + struct { + __IM unsigned int NO_OF_IO_FUNCTIONS : 3; /*!< [2..0] Indicates number functions + supported. The value written + by bootloader can be read here. */ + __IM unsigned int COMBOCARD : 1; /*!< [3..3] When set, combo mode will be enabled. */ + __IM unsigned int SDMEM_IGNOTRE_SDMEM_PRESENT : 1; /*!< [4..4] When set, sdmem_present + signal, coming from GPIO, will be + ignored. */ + __IM unsigned int SDMEM_DRIVE_HIZ_MB_READ : 1; /*!< [5..5] When set, High will be driven + in the second cycle of interrupt period + during sd memory mb read transfer */ + __IM unsigned int SDMEM_DISABLE_INTERRUPT_MB_READ : 1; /*!< [6..6] When set, + interrupt will be + not be driven during + sd memory mb read + transfer */ + __IM unsigned int IGNORE_DISABLE_HS : 1; /*!< [7..7] if ignore_disable_hs is set, + sdmem_disable_high_speed_switching coming + from combo mode module is ignored */ + __IM unsigned int RESERVED2 : 24; /*!< [31..8] RESERVED2 */ + } SDIO_BOOT_CONFIG_VALS_1_REG_b; + }; +} SDIO0_Type; /*!< Size = 272 (0x110) */ + +/* =========================================================================================================================== + */ +/* ================ SPI_SLAVE + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The SPI Interface is a full duplex serial host interface, which + supports 8-bit and 32-bit data granularity. It also supports gated mode of SPI + clock and both the low and the high frequency modes (SPI_SLAVE) + */ + +typedef struct { /*!< (@ 0x20200000) SPI_SLAVE Structure */ + + union { + __IOM uint8_t SPI_HOST_INTR; /*!< (@ 0x00000000) SPI Host interupt resgister. */ + + struct { + __IOM uint8_t SPI_HOST_INTR : 8; /*!< [7..0] These bits indicate the interrupt + vector value coming from system side. */ + } SPI_HOST_INTR_b; + }; + __IM uint8_t RESERVED; + + union { + __IOM uint8_t SPI_RFIFO_START; /*!< (@ 0x00000002) SPI FIFO start Level Register. */ + + struct { + __IOM uint8_t SPI_RFIFO_ST : 8; /*!< [7..0] These bits indicate the interrupt vector + value coming from system side. */ + } SPI_RFIFO_START_b; + }; + __IM uint8_t RESERVED1; + + union { + __IOM uint8_t SPI_RFIFO_AFULL_LEV; /*!< (@ 0x00000004) SPI RFIFO AFULL Level + Register. */ + + struct { + __IOM uint8_t SPI_RFIFO_AFULL_LEV : 8; /*!< [7..0] These bits are used to program + the FIFO occupancy level to trigger the + Almost Full indication. */ + } SPI_RFIFO_AFULL_LEV_b; + }; + __IM uint8_t RESERVED2; + + union { + __IOM uint8_t SPI_RFIFO_AEMPTY_LEV; /*!< (@ 0x00000006) SPI WFIFO Almost + Empty Register. */ + + struct { + __IOM uint8_t SPI_RFIFO_AEMPTY_LEV : 8; /*!< [7..0] These bits are used to + program the occupancy level to + trigger the Almost Empty + indication. */ + } SPI_RFIFO_AEMPTY_LEV_b; + }; + __IM uint8_t RESERVED3; + + union { + __IOM uint8_t SPI_MODE; /*!< (@ 0x00000008) SPI Mode Register. */ + + struct { + __IOM uint8_t SPI_OP_MODE : 1; /*!< [0..0] This bit is used to program the + mode of working of SPI Interface. */ + __IOM uint8_t SPI_FIX_EN : 1; /*!< [1..1] This bit is used to enable the + fix made for bus_ctrl_busy being asserted + when success_state is being asserted + getting deasserted when FSM has decided + to move to BUSY_STATE or not. */ + __IOM uint8_t VHS_EN : 1; /*!< [2..2] This bit is used to enable Very high + speed mode (120Mhz). */ + __IOM uint8_t BYPASS_INIT : 1; /*!< [3..3] This bit is used to bypass the + SPI initialization.0 - + Doesn't bypass,1 - bypasses + SPI initialization */ + __IOM uint8_t RESERVED1 : 4; /*!< [7..4] reserved1 */ + } SPI_MODE_b; + }; + __IM uint8_t RESERVED4; + + union { + __IOM uint16_t SPI_INTR_STATUS; /*!< (@ 0x0000000A) SPI interrupt status register. */ + + struct { + __IOM uint16_t SPI_WR_REQ : 1; /*!< [0..0] Write request received. */ + __IOM uint16_t SPI_RD_REQ : 1; /*!< [1..1] Read request received. */ + __IOM uint16_t SPI_CS_DEASSERT : 1; /*!< [2..2] SPI chip deassert interrupt. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_STATUS_b; + }; + + union { + __IOM uint16_t SPI_INTR_EN; /*!< (@ 0x0000000C) SPI interrupt enable register. */ + + struct { + __IOM uint16_t SPI_WR_INT_EN : 1; /*!< [0..0] This bit is used to enable + the write interrupt. */ + __IOM uint16_t SPI_RD_INT_EN : 1; /*!< [1..1] This bit is used to enable + the read interrupt. */ + __IOM uint16_t SPI_CS_DEASSERT_INT_EN : 1; /*!< [2..2] This bit is used to enable the + interrupt due to wrong deassertion of + CS. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_EN_b; + }; + + union { + __IOM uint16_t SPI_INTR_MASK; /*!< (@ 0x0000000E) SPI interrupt Mask register */ + + struct { + __IOM uint16_t SPI_WR_INTR_MSK : 1; /*!< [0..0] This bit is used to mask + the write interrupt. */ + __IOM uint16_t SPI_RD_INTR_MSK : 1; /*!< [1..1] This bit is used to mask + the read interrupt. */ + __IOM uint16_t SPI_CS_DEASSERT_INT_MSK : 1; /*!< [2..2] This bit is used to mask the + CS deassertion interrupt. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_MASK_b; + }; + + union { + __IOM uint16_t SPI_INTR_UNMASK; /*!< (@ 0x00000010) SPI interrupt unmask register */ + + struct { + __IOM uint16_t SPI_WR_INT_UNMASK : 1; /*!< [0..0] This bit is used to + unmask the write interrupt. */ + __IOM uint16_t SPI_RD_INTR_UNMSK : 1; /*!< [1..1] This bit is used to + unmask the read interrupt. */ + __IOM uint16_t SPI_CS_DEASSERT_INT_UNMSK : 1; /*!< [2..2] This bit is used to unmask + the CS deassertion interrupt. */ + __IOM uint16_t RESERVED1 : 13; /*!< [15..3] reserved1 */ + } SPI_INTR_UNMASK_b; + }; + + union { + __IM uint16_t SPI_LENGTH; /*!< (@ 0x00000012) SPI Length Register */ + + struct { + __IM uint16_t SPI_LEN : 16; /*!< [15..0] These bit indicate the length of + the transfer as transmitted + in the Commands C3 and C4. + */ + } SPI_LENGTH_b; + }; + + union { + __IM uint16_t SPI_COMMAND; /*!< (@ 0x00000014) SPI Command Register */ + + struct { + __IM uint16_t SPI_C1 : 8; /*!< [7..0] These bits store the received command C1. */ + __IM uint16_t SPI_C2 : 8; /*!< [15..8] These bits store the received + command C2. */ + } SPI_COMMAND_b; + }; + + union { + __IM uint16_t SPI_DEV_ID; /*!< (@ 0x00000016) SPI Device ID Register */ + + struct { + __IM uint16_t SPI_DEVID : 16; /*!< [15..0] These bits store the Device ID + information. */ + } SPI_DEV_ID_b; + }; + + union { + __IM uint16_t SPI_VERSION; /*!< (@ 0x00000018) SPI Device ID Register */ + + struct { + __IM uint16_t SPI_VERNO : 8; /*!< [7..0] These bits store the version number. */ + __IM uint16_t RESERVED1 : 8; /*!< [15..8] reserved1 */ + } SPI_VERSION_b; + }; + + union { + __IM uint16_t SPI_STATUS; /*!< (@ 0x0000001A) SPI Status Register */ + + struct { + __IM uint16_t SPI_RFIFO_FULL : 1; /*!< [0..0] This bit indicates if the + read FIFO is almost full. */ + __IM uint16_t SPI_RFIFO_AFULL : 1; /*!< [1..1] This bit indicates if the + read FIFO is almost full. */ + __IM uint16_t SPI_WFIFO_EMPTY : 1; /*!< [2..2] This bit indicates if write + FIFO is empty. */ + __IM uint16_t SPI_WFIFO_AEMPTY : 1; /*!< [3..3] This bit indicates if + write FIFO is almost empty. */ + __IM uint16_t SPI_RFIFO_EMPTY : 1; /*!< [4..4] This bit indicates if read FIFO is + empty (Read from SOC to host). */ + __IM uint16_t SPI_RFIFO_AEMPTY : 1; /*!< [5..5] This bit indicates if read FIFO is + empty (Read from SOC to host). */ + __IM uint16_t SPI_WFIFO_FULL : 1; /*!< [6..6] This bit indicates if write FIFO is + full (Write from Host to SOC). */ + __IM uint16_t SPI_WFIFO_AFULL : 1; /*!< [7..7] This bit indicates if write FIFO is + full (Write from Host to SOC). */ + __IM uint16_t RESERVED1 : 8; /*!< [15..8] reserved1 */ + } SPI_STATUS_b; + }; + + union { + __IM uint16_t SPI_BC_STATE; /*!< (@ 0x0000001C) SPI Bus Controller State Register */ + + struct { + __IM uint16_t SPI_BC : 14; /*!< [13..0] These bits indicate the Bus + Controller FSM state. */ + __IM uint16_t RESERVED1 : 2; /*!< [15..14] reserved1 */ + } SPI_BC_STATE_b; + }; + __IM uint16_t RESERVED5; + __IM unsigned int RESERVED6[23]; + + union { + __IOM uint16_t SPI_SYS_RESET_REQ; /*!< (@ 0x0000007C) SPI SYS Reset Req Register */ + + struct { + __IOM + uint16_t SPI_SYS_RESET_REQ : 1; /*!< [0..0] When set generates system reset + request to reset controller. This gets + reset once, reset controller generates + reset. Host should not reset this bit. + With this reset request, reset + controller generates non por reset. */ + __IOM uint16_t RESERVED1 : 15; /*!< [15..1] reserved1 */ + } SPI_SYS_RESET_REQ_b; + }; + + union { + __IOM uint16_t SPI_WAKE_UP; /*!< (@ 0x0000007E) SPI Wakeup Register */ + + struct { + __IOM uint16_t SPI_WAKEUP : 1; /*!< [0..0] Wakeup Interrupt,Interrupt for waking up + the system from Deep Sleep. */ + __IOM uint16_t SPI_DEEP_SLEEP_ST : 1; /*!< [1..1] Deep Sleep Start,Indicates the + device to enter Deep Sleep + state for maximum power save. */ + __IOM uint16_t RESERVED1 : 14; /*!< [15..2] reserved1 */ + } SPI_WAKE_UP_b; + }; + __IM unsigned int RESERVED7[192]; + + union { + __IM unsigned int SPI_RFIFO_DATA; /*!< (@ 0x00000380) SPI RFIFO Data Register */ + + struct { + __IM unsigned int SPI_RFIFO : 32; /*!< [31..0] These bits store the data + received from the host */ + } SPI_RFIFO_DATA_b; + }; + __IM unsigned int RESERVED8[15]; + + union { + __OM unsigned int SPI_WFIFO_DATA; /*!< (@ 0x000003C0) SPI WFIFO Data Register */ + + struct { + __OM unsigned int SPI_WFIFO : 32; /*!< [31..0] These bits are used to write, + the data to be sent to the host. */ + } SPI_WFIFO_DATA_b; + }; +} SPI_SLAVE_Type; /*!< Size = 964 (0x3c4) */ + +/* =========================================================================================================================== + */ +/* ================ M4CLK + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief MCU HP (High Performance) domain contains the Cortex-M4F Processor, + * FPU, Debugger, MCU High Speed Interfaces, MCU HP Peripherals, MCU HP DMA and + * MCU/SZP shareable Interfaces (M4CLK) + */ + +typedef struct { /*!< (@ 0x46000000) M4CLK Structure */ + + union { + __IOM unsigned int CLK_ENABLE_SET_REG1; /*!< (@ 0x00000000) Clock Enable Set + Register 1 */ + + struct { + __IOM unsigned int USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable for + usart1 pclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM unsigned int USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for + usart1 sclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM unsigned int USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for + usart2 pclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM unsigned int USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock gating Enable for + usart2 sclk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM unsigned int Reserved1 : 5; /*!< [8..4] It is recommended to write these + bits to 0. */ + __IOM unsigned int CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable + for sct clk1'b1 => Clock is + enabled 1'b0 => Invalid. */ + __IOM unsigned int CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating + Enable for sct pclk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating Enable for + icache clk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable + for icache 2x clk1'b1 => Clock is + enabled 1'b0 => Invalid. */ + __IOM unsigned int RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for + rpdma hclk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable + for soc pll spi clk1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM unsigned int Reserved2 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM unsigned int IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating + Enable for iid clk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable + for sdio sys hclk1'b1 => Clock is + enabled 1'b0 => Invalid */ + __IOM unsigned int CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating + Enable for crc clk1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM unsigned int Reserved3 : 3; /*!< [21..19] It is recommended to write + these bits to 0. */ + __IOM unsigned int HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating Enable for + HWRNG pclk1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable + for GNSS mem clk1'b1 => + Clock is enabled 1'b0 => Invalid */ + __IOM unsigned int Reserved4 : 3; /*!< [26..24] It is recommended to write + these bits to 0. */ + __IOM unsigned int MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether + to wait for a fixed number of xtal + clock cycles(based on + mask31_host_clk_cnt) or wait for a + internally generated signal to come + out of WAIT state in host mux FSM 1'b1 + => Wait for fixed number of xtal clk + cycles 1'b0 => Invalid This bit along + with mask_host_clk_available_fix and + mask31_host_clk_cnt are to take care + in case of any bugs. */ + __IOM unsigned int MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix + is 1'b1, this bit decides whether to + count for 32 0r 16 xtal clock cycles to + come out of WAIT state in host mux FSM + 1'b1 => Wait for 32 clock cycles 1'b0 => + Invalid This bit along with + mask_host_clk_available_fix and + mask_host_clk_wait_fix are to take care + in case of any bugs. */ + __IOM unsigned int Reserved5 : 1; /*!< [29..29] It is recommended to write + these bits to 0. */ + __IOM unsigned int MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides + whether to consider negedge of + host_clk_available in the + generation of clock enable for + host_clk gate in host mux 1'b1 + => Don't consider 1'b0 => + Invalid This bit along with + mask_host_clk_wait_fix and + mask31_host_clk_cnt + are to take care in case + of any bugs. */ + __IOM unsigned int ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for + m4 soc_clk to ulpss1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + } CLK_ENABLE_SET_REG1_b; + }; + + union { + __IOM unsigned int CLK_ENABLE_CLEAR_REG1; /*!< (@ 0x00000004) Clock Enable Clear + Register 1 */ + + struct { + __IOM unsigned int USART1_PCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear + for usart1 pclk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM unsigned int USART1_SCLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear + for usart1 sclk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM unsigned int USART2_PCLK_ENABLE_b : 1; /*!< [2..2] Static Clock Clear + for usart2 pclk 1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM unsigned int USART2_SCLK_ENABLE_b : 1; /*!< [3..3] Static Clock Clear + for usart2 sclk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM unsigned int Reserved1 : 5; /*!< [8..4] It is recommended to write these + bits to 0. */ + __IOM unsigned int CT_CLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for sct clk1'b1 => + Clock is Clear 1'b0 => Invalid. */ + __IOM unsigned int CT_PCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for + sct pclk1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM unsigned int ICACHE_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear + for icache clk1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int ICACHE_CLK_2X_ENABLE_b : 1; /*!< [12..12] Static Clock Clear for + icache 2x clk1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM unsigned int RPDMA_HCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear + for rpdma hclk1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int SOC_PLL_SPI_CLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for soc + pll spi clk1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int Reserved2 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM unsigned int IID_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Clear for iid clk1'b1 + => Clock is Clear 1'b0 => Invalid. */ + __IOM unsigned int SDIO_SYS_HCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for sdio + sys hclk1'b1 => Clock is + Clear 1'b0 => Invalid */ + __IOM unsigned int CRC_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear for crc clk1'b1 + => Clock is Clear 1'b0 => Invalid */ + __IOM unsigned int Reserved3 : 3; /*!< [21..19] It is recommended to write + these bits to 0. */ + __IOM unsigned int HWRNG_PCLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear + for HWRNG pclk1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int GNSS_MEM_CLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear + for GNSS mem clk1'b1 => Clock + is Clear 1'b0 => Invalid */ + __IOM unsigned int Reserved4 : 3; /*!< [26..24] It is recommended to write + these bits to 0. */ + __IOM unsigned int MASK_HOST_CLK_WAIT_FIX_b : 1; /*!< [27..27] This bit decides whether + to wait for a fixed number of xtal + clock cycles(based on + mask31_host_clk_cnt) or wait for a + internally generated signal to come + out of WAIT state in host mux FSM 1'b1 + => Wait for fixed number of xtal clk + cycles 1'b0 => Invalid This bit along + with mask_host_clk_available_fix and + mask31_host_clk_cnt are to take care + in case of any bugs. */ + __IOM unsigned int MASK31_HOST_CLK_CNT_b : 1; /*!< [28..28] When mask_host_clk_wait_fix + is 1'b1, this bit decides whether to + count for 32 0r 16 xtal clock cycles to + come out of WAIT state in host mux FSM + 1'b1 => Wait for 32 clock cycles 1'b0 => + Invalid This bit along with + mask_host_clk_available_fix and + mask_host_clk_wait_fix are to take care + in case of any bugs. */ + __IOM unsigned int Reserved5 : 1; /*!< [29..29] It is recommended to write + these bits to 0. */ + __IOM unsigned int MASK_HOST_CLK_AVAILABLE_FIX_b : 1; /*!< [30..30] This bit decides + whether to consider negedge of + host_clk_available in the + generation of clock enable for + host_clk gate in host mux 1'b1 + => Don't consider 1'b0 => + Invalid This bit along with + mask_host_clk_wait_fix and + mask31_host_clk_cnt + are to take care in case + of any bugs. */ + __IOM unsigned int ULPSS_CLK_ENABLE_b : 1; /*!< [31..31] Static Clock gating Enable for + m4 soc_clk to ulpss1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + } CLK_ENABLE_CLEAR_REG1_b; + }; + + union { + __IOM unsigned int CLK_ENABLE_SET_REG2; /*!< (@ 0x00000008) Clock Enable Set + Register 2 */ + + struct { + __IOM unsigned int GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating Enable + for gen spi master1 hclk 1'b1 + => Clock is enabled 1'b0 + => Invalid */ + __IOM unsigned int Reserved1 : 5; /*!< [5..1] It is recommended to write these + bits to 0. */ + __IOM unsigned int UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for + udma hclk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock gating Enable for + i2c-1 bus clk1'b1 => Clock is enabled + 1'b0 => Invalid. */ + __IOM unsigned int I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock gating Enable for + i2c-2 bus clk 1'b1 => + Clock is enabled 1'b0 => Invalid. */ + __IOM unsigned int SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock gating Enable for + ssi slave pclk 1'b1 => + Clock is enabled 1'b0 => Invalid. */ + __IOM + unsigned int SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock gating + Enable for ssi slave sclk 1'b1 + => Clock is enabled 1'b0 => + Invalid. */ + __IOM unsigned int QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock gating + Enable for qspi clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock gating Enable for + qspi hclk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable for + sclk of I2S at Root Clock generation 1'b1 + => Clock is enabled 1'b0 => Invalid. */ + __IOM unsigned int I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock gating Enable + for i2s interface sclk 1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM unsigned int I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock gating Enable for + i2s master pclk 1'b1 + => Clock is enabled 1'b0 => Invalid. */ + __IOM unsigned int Reserved2 : 1; /*!< [16..16] It is recommended to write + these bits to 0. */ + __IOM unsigned int QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating Enable for qe + pclk 1'b1 => Clock is enabled 1'b0 => + Invalid. */ + __IOM unsigned int MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating Enable for + mcpwm pclk 1'b1 => Clock is enabled 1'b0 + => Invalid. */ + __IOM unsigned int Reserved3 : 1; /*!< [19..19] It is recommended to write + these bits to 0. */ + __IOM unsigned int SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating Enable for + sgpio pclk 1'b1 => Clock is enabled 1'b0 + => Invalid. */ + __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock gating Enable for + egpio pclk 1'b1 => Clock is enabled 1'b0 + => Invalid. */ + __IOM unsigned int ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock gating + Enable for arm clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock gating Enable + for ssi master pclk 1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM unsigned int SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock gating Enable + for ssi master sclk 1'b1 + => Clock is enabled 1'b0 => Invalid. + */ + __IOM unsigned int Reserved4 : 1; /*!< [25..25] It is recommended to write + these bits to 0. */ + __IOM unsigned int MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock gating Enable for + mem ulp clk 1'b1 => + Clock is enabled 1'b0 => Invalid. */ + __IOM unsigned int ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock gating + Enable for rom clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock gating Enable + for pll intf clk 1'b1 => Clock is + enabled 1'b0 => Invalid. */ + __IOM unsigned int Reserved5 : 3; /*!< [31..29] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_SET_REG2_b; + }; + + union { + __IOM unsigned int CLK_ENABLE_CLEAR_REG2; /*!< (@ 0x0000000C) Clock Enable Clear + Register 2 */ + + struct { + __IOM unsigned int GEN_SPI_MST1_HCLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for gen + spi master1 hclk 1'b1 => Clock is + Clear 1'b0 => Invalid */ + __IOM unsigned int Reserved1 : 5; /*!< [5..1] It is recommended to write these + bits to 0. */ + __IOM unsigned int UDMA_HCLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for + udma hclk 1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM unsigned int I2C_BUS_CLK_ENABLE_b : 1; /*!< [7..7] Static Clock Clear + for i2c-1 bus clk1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int I2C_2_BUS_CLK_ENABLE_b : 1; /*!< [8..8] Static Clock Clear for i2c-2 + bus clk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int SSI_SLV_PCLK_ENABLE_b : 1; /*!< [9..9] Static Clock Clear for ssi + slave pclk 1'b1 => Clock is Clear 1'b0 + => Invalid. */ + __IOM unsigned int SSI_SLV_SCLK_ENABLE_b : 1; /*!< [10..10] Static Clock Clear for ssi + slave sclk 1'b1 => Clock is Clear 1'b0 + => Invalid. */ + __IOM unsigned int QSPI_CLK_ENABLE_b : 1; /*!< [11..11] Static Clock Clear for qspi clk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM unsigned int QSPI_HCLK_ENABLE_b : 1; /*!< [12..12] Static Clock Clear + for qspi hclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int I2SM_SCLK_ENABLE_b : 1; /*!< [13..13] Static Clock Clear + for sclk of I2S at Root Clock + generation 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int I2SM_INTF_SCLK_ENABLE_b : 1; /*!< [14..14] Static Clock Clear for i2s + interface sclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int I2SM_PCLK_ENABLE_b : 1; /*!< [15..15] Static Clock Clear for i2s + master pclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int Reserved2 : 1; /*!< [16..16] It is recommended to write + these bits to 0. */ + __IOM unsigned int QE_PCLK_ENABLE_b : 1; /*!< [17..17] Static Clock Clear for qe pclk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM unsigned int MCPWM_PCLK_ENABLE_b : 1; /*!< [18..18] Static Clock Clear + for mcpwm pclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int Reserved3 : 1; /*!< [19..19] It is recommended to write + these bits to 0. */ + __IOM unsigned int SGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] Static Clock Clear + for sgpio pclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1; /*!< [21..21] Static Clock Clear + for egpio pclk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int ARM_CLK_ENABLE_b : 1; /*!< [22..22] Static Clock Clear for arm clk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM unsigned int SSI_MST_PCLK_ENABLE_b : 1; /*!< [23..23] Static Clock Clear for ssi + master pclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int SSI_MST_SCLK_ENABLE_b : 1; /*!< [24..24] Static Clock Clear for ssi + master sclk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int Reserved4 : 1; /*!< [25..25] It is recommended to write + these bits to 0. */ + __IOM unsigned int MEM_CLK_ULP_ENABLE_b : 1; /*!< [26..26] Static Clock Clear + for mem ulp clk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int ROM_CLK_ENABLE_b : 1; /*!< [27..27] Static Clock Clear for rom clk + 1'b1 => Clock is Clear 1'b0 => Invalid. */ + __IOM unsigned int PLL_INTF_CLK_ENABLE_b : 1; /*!< [28..28] Static Clock Clear for pll + intf clk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int Reserved5 : 3; /*!< [31..29] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_CLEAR_REG2_b; + }; + + union { + __IOM unsigned int CLK_ENABLE_SET_REG3; /*!< (@ 0x00000010) Clock Enable Set + Register 3 */ + + struct { + __IOM unsigned int BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock gating + Enable for bus clk 1'b1 => Clock + is enabled 1'b0 => Invalid */ + __IOM unsigned int M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock gating Enable for + M4 Core clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm + bus clk1'b1 => Clock is enabled1'b0 => + Invalid. */ + __IOM unsigned int Reserved1 : 1; /*!< [3..3] It is recommended to write these + bits to 0. */ + __IOM unsigned int MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock gating Enable + for misc config regs clk 1'b1 + => Clock is enabled 1'b0 => + Invalid. */ + __IOM unsigned int EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock gating Enable for + efuse clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock gating Enable for icm + clk 1'b1 => Clock + is enabled 1'b0 => Invalid. */ + __IOM unsigned int Reserved2 : 6; /*!< [12..7] It is recommended to write + these bits to 0. */ + __IOM unsigned int QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock gating Enable + for QSPI clock generated from the + dynamic mux 1b1 - Clock is enabled 1b0 + - Invalid. */ + __IOM unsigned int QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is + in sync with Soc clock. Before enabling + this make sure that qspi_clk_onehot_enable + is 1b0 to enable glitch free switching + 1b1 - QSPI clock is in sync with M4 clock + 1b0 - Invalid. */ + __IOM unsigned int Reserved3 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM unsigned int EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock gating enable for + Enhanced-GPIO 1b1 - + Clock is enabled 1b0 - Invalid. */ + __IOM unsigned int I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock gating enable for + I2C-1 Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM unsigned int I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock gating enable for + I2C-2 Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM unsigned int EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock gating + enable for EFUSE APB Interface + 1b1 - Clock is enabled 1b0 + - Invalid. */ + __IOM unsigned int SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for + SIO Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM unsigned int TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ + __IOM unsigned int TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ + __IOM unsigned int TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ + __IOM unsigned int Reserved4 : 1; /*!< [24..24] It is recommended to write + these bits to 0. */ + __IOM unsigned int ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock gating enable + for rom ahb Clock 1b1 - Clock is + enabled 1b0 - Invalid. */ + __IOM unsigned int M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock gating + enable for M4-SOC Other Clock + 1b1 + - Clock is enabled 1b0 - + Invalid. */ + __IOM unsigned int ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock gating enable for + Icache. This has to be enable for Icache + operations. 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM unsigned int Reserved5 : 4; /*!< [31..28] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_SET_REG3_b; + }; + + union { + __IOM unsigned int CLK_ENABLE_CLEAR_REG3; /*!< (@ 0x00000014) Clock Enable Clear + Register 3 */ + + struct { + __IOM unsigned int BUS_CLK_ENABLE_b : 1; /*!< [0..0] Static Clock Clear for bus clk 1'b1 + => Clock is Clear 1'b0 => Invalid */ + __IOM unsigned int M4_CORE_CLK_ENABLE_b : 1; /*!< [1..1] Static Clock Clear + for M4 Core clk 1'b1 => Clock + is Clear 1'b0 => Invalid. */ + __IOM unsigned int CM_BUS_CLK_ENABLE_b : 1; /*!< [2..2] Static Clock gating Enable for cm + bus clk1'b1 => Clock is enabled1'b0 => + Invalid. */ + __IOM unsigned int Reserved1 : 1; /*!< [3..3] It is recommended to write these + bits to 0. */ + __IOM unsigned int MISC_CONFIG_PCLK_ENABLE_b : 1; /*!< [4..4] Static Clock Clear for misc + config regs clk 1'b1 => Clock is + Clear 1'b0 => Invalid. */ + __IOM unsigned int EFUSE_CLK_ENABLE_b : 1; /*!< [5..5] Static Clock Clear for + efuse clk 1'b1 => Clock is Clear + 1'b0 => Invalid. */ + __IOM unsigned int ICM_CLK_ENABLE_b : 1; /*!< [6..6] Static Clock Clear for icm clk 1'b1 + => Clock is Clear 1'b0 => Invalid. */ + __IOM unsigned int Reserved2 : 6; /*!< [12..7] It is recommended to write + these bits to 0. */ + __IOM unsigned int QSPI_CLK_ONEHOT_ENABLE_b : 1; /*!< [13..13] Static Clock Clear for + QSPI clock generated from the + dynamic mux 1b1 - Clock is Gated 1b0 - + Invalid. */ + __IOM unsigned int QSPI_M4_SOC_SYNC_b : 1; /*!< [14..14] Specifies whether QSPI clock is + in sync with Soc clock. Before enabling + this make sure that qspi_clk_onehot_enable + is 1b0 to enable glitch free switching + 1b1 - QSPI clock is in sync with M4 clock + 1b0 - Invalid. */ + __IOM unsigned int Reserved3 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM unsigned int EGPIO_CLK_ENABLE_b : 1; /*!< [16..16] Static Clock Disable for + Enhanced-GPIO 1b1 - Clock + is Disable 1b0 - Invalid. */ + __IOM unsigned int I2C_CLK_ENABLE_b : 1; /*!< [17..17] Static Clock Disable + for I2C-1 Module 1b1 - Clock is + Disable 1b0 - Invalid. */ + __IOM unsigned int I2C_2_CLK_ENABLE_b : 1; /*!< [18..18] Static Clock Disable + for I2C-2 Module 1b1 - Clock is + Disable 1b0 - Invalid. */ + __IOM unsigned int EFUSE_PCLK_ENABLE_b : 1; /*!< [19..19] Static Clock Disable for EFUSE + APB Interface 1b1 - + Clock is Disable 1b0 - Invalid. */ + __IOM unsigned int SGPIO_CLK_ENABLE_b : 1; /*!< [20..20] Static Clock gating enable for + SIO Module 1b1 - Clock is enabled 1b0 - + Invalid. */ + __IOM unsigned int TASS_M4SS_64K_SWITCH_CLK_ENABLE_b : 1; /*!< [21..21] Unused. */ + __IOM unsigned int TASS_M4SS_128K_SWITCH_CLK_ENABLE_b : 1; /*!< [22..22] Unused. */ + __IOM unsigned int TASS_M4SS_SDIO_SWITCH_CLK_ENABLE_b : 1; /*!< [23..23] Unused. */ + __IOM unsigned int Reserved4 : 1; /*!< [24..24] It is recommended to write + these bits to 0. */ + __IOM unsigned int ROM_MISC_STATIC_ENABLE_b : 1; /*!< [25..25] Static Clock Disable for + rom ahb Clock 1b1 - Clock is Disable + 1b0 - Invalid. */ + __IOM unsigned int M4_SOC_CLK_FOR_OTHER_ENABLE_b : 1; /*!< [26..26] Static Clock Disable + for M4-SOC Other Clock 1b1 - + Clock + is Disable 1b0 - Invalid. + */ + __IOM unsigned int ICACHE_ENABLE_b : 1; /*!< [27..27] Static Clock Disable for Icache. + This has to be enable for Icache operations. + 1b1 - Clock is Disable 1b0 - Invalid. */ + __IOM unsigned int Reserved5 : 4; /*!< [31..28] It is recommended to write + these bits to 0. */ + } CLK_ENABLE_CLEAR_REG3_b; + }; + + union { + __IOM unsigned int CLK_CONFIG_REG1; /*!< (@ 0x00000018) Clock Config Register 1 */ + + struct { + __IOM unsigned int QSPI_CLK_SEL : 3; /*!< [2..0] Selects one of the following clocks for + ssi master 000 + - ULP Ref Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 001 - Intf PLL Clock + Clock (program bypass_intf_pll_clk if the bypass + clock has to be selected) 010 - Modem PLL + Clock2(Not Intended for the programmer) + (program bypass_modem_pll_clk + if the bypass clock has to be selected) 011 - + SoC PLL Clock */ + __IOM unsigned int QSPI_CLK_DIV_FAC : 6; /*!< [8..3] Clock divison factor for QSPI. If + qspi_clk_enable is 1b0 clock is gated. Else + 1)when qspi_clk_swallow_sel is 1b1 and + qspi_odd_div_sel is 1b0 output clock is a + swallowed clock with the following frequency. + 6h0,6h1 => clk_out = clk_in >6h1 => clk_out = + clk_in/ qspi_clk_div_fac 2)when + qspi_clk_swallow_sel is 1b0 */ + __IOM + unsigned int QSPI_CLK_SWALLOW_SEL : 1; /*!< [9..9] Clock select for clock + swallow or clock divider for QSPI 1b0 + => 50% divider is selected with + division factor qspi_clk_div_fac 1b1 + => Swallowed clock is selected with + division factor qspi_clk_div_fac + Before Changing this ensure that the + input clocks are gated */ + __IOM unsigned int SLP_RF_CLK_SEL : 1; /*!< [10..10] clock select for + m4_soc_rf_ref_clk 0 - m4_soc_clk 1 + - rf_ref_clk. */ + __IOM unsigned int SSI_MST_SCLK_DIV_FAC : 4; /*!< [14..11] Clock division factor for + ssi_mst_sclk. If ssi_mst_sclk_enable is + 1b0 clock is gated. Else output clock is + a swallowed clock with the following + frequency. 4h0,4h1 => Divider + is bypassed >4h1 => clk_out = + clk_in/ ssi_mst_sclk_div_fac. */ + __IOM unsigned int SSI_MST_SCLK_SEL : 3; /*!< [17..15] Selects one of the following + clocks for ssi master 000 - ULP Ref + Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 001 - SoC PLL + Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock1(Not Intended for the programmer) + (program bypass_modem_pll_clk if the bypass + clock has to be selected) 011 - Intf PLL + Clock(program bypass_intf_pll_clk if + the */ + __IOM unsigned int PLL_INTF_CLK_SEL : 1; /*!< [18..18] Selects one of the following + clocks for pll intf clock 0 - Intf Pll + Clock(program bypass_intf_pll_clk if the + bypass clock has to be selected) 1 - SoC Pll + Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) */ + __IOM unsigned int PLL_INTF_CLK_DIV_FAC : 4; /*!< [22..19] Clock division factor for + pll_intf_clk. If pll_intf_clk_enable is + 1b0 clock is gated. Else, when + pll_intf_clk_swallow_sel is 1b1, output + clock is a swallowed clock. when + pll_intf_clk_swallow_sel is 1b0, output + clock is a 50 Per duty cycle clock. */ + __IOM unsigned int PLL_INTF_CLK_SWALLOW_SEL : 1; /*!< [23..23] Clock select for clock + swallow or clock divider for PLL INTF + Clk 1b0 - 50% divider is selected with + division factor 2; 1b1 - Swallowed + clock is selected with division + factor pll_intf_clk_div_fac */ + __IOM unsigned int GEN_SPI_MST1_SCLK_SEL : 3; /*!< [26..24] Selects one of the following + clocks for USART1 clk 000 - + m4_soc_clk_for_other_clocks 001 - ulp ref + Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 010 - SoC PLL + Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 011 - + Modem PLL Clock2(Not Intended for the + pragrammer) (program bypass_modem_pll_clk + if the bypass clock has to be sele */ + __IOM unsigned int Reserved1 : 5; /*!< [31..27] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG1_b; + }; + + union { + __IOM unsigned int CLK_CONFIG_REG2; /*!< (@ 0x0000001C) Clock Config Register 1 */ + + struct { + __IOM unsigned int USART1_SCLK_SEL : 3; /*!< [2..0] Selects one of the following clocks + for USART1 clk 000 + - ulp ref Clock(generated inside M4SS + based on m4ss_ref_clk_sel from NPSS) 001 - SoC + PLL Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock2(Not Intended for the + pragrammer)(program bypass_modem_pll_clk if + the bypass clock has to be selected) 011 - + Intf PLL + Clock(program bypass_intf_pll_clk if the b + */ + __IOM unsigned int USART1_SCLK_DIV_FAC : 4; /*!< [6..3] Clock division factor for USART1 + Clock. If usart1_sclk_enable is 1b0 clock + is gated. Else output clock is a swallowed + clock. */ + __IOM unsigned int USART2_SCLK_SEL : 3; /*!< [9..7] Selects one of the following clocks + for USART2 clk 000 + - ulp ref Clock(generated inside M4SS + based on m4ss_ref_clk_sel from NPSS) 001 - SoC + PLL Clock(program bypass_soc_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock2(Not Intended for the + pragrammer)(program bypass_modem_pll_clk if + the bypass clock has to be selected) 011 - + Intf PLL + Clock(program bypass_intf_pll_clk if the b + */ + __IOM unsigned int USART2_SCLK_DIV_FAC : 4; /*!< [13..10] Clock division factor for + USART2 Clock. If usart2_sclk_enable is 1b0 + clock is gated. Else output clock is a + swallowed clock. */ + __IOM unsigned int Reserved1 : 14; /*!< [27..14] It is recommended to write + these bits to 0. */ + __IOM unsigned int QSPI_ODD_DIV_SEL : 1; /*!< [28..28] Clock select for clock swallow or + 50% even clock divider or 50% odd divider + clock for QSPI 1b1 - 50% odd clock divider + output is selected with division factor + qspi_clk_div_fac 1b0 - 50% even clock divider + output or swallowed is selected + with division factor qspi_clk_div_fac + based on qspi_clk_swallow_sel. */ + __IOM unsigned int USART1_SCLK_FRAC_SEL : 1; /*!< [29..29] Selects the type of divider + for uart1_clk 1b0 - Clock Swallow is + selected 1b1 - Fractional Divider is + selected. */ + __IOM unsigned int USART2_SCLK_FRAC_SEL : 1; /*!< [30..30] Selects the type of divider + for uart2_clk 1b0 - Clock Swallow is + selected 1b1 - Fractional Divider is + selected. */ + __IOM unsigned int USART3_SCLK_FRAC_SEL : 1; /*!< [31..31] Selects the type of divider + for uart3_clk 1b0 - Clock Swallow is + selected 1b1 - Fractional Divider is + selected. */ + } CLK_CONFIG_REG2_b; + }; + + union { + __IOM unsigned int CLK_CONFIG_REG3; /*!< (@ 0x00000020) Clock Config Register 3 */ + + struct { + __IOM unsigned int Reserved1 : 8; /*!< [7..0] It is recommended to write these + bits to 0. */ + __IOM unsigned int MCU_CLKOUT_SEL : 4; /*!< [11..8] Clock Select for the clock + on mcu_clkout (Mapped to GPIO) */ + __IOM unsigned int MCU_CLKOUT_DIV_FAC : 6; /*!< [17..12] Division factor for + mcu_clkout (Mapped to GPIO) */ + __IOM unsigned int MCU_CLKOUT_ENABLE : 1; /*!< [18..18] Clock Enable for the clock on + nwp_clkout (Mapped to GPIO) 1b0 - Clock is + Gated 1b1 - Clock is Enabled */ + __IOM unsigned int Reserved2 : 13; /*!< [31..19] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG3_b; + }; + + union { + __IOM unsigned int CLK_CONFIG_REG4; /*!< (@ 0x00000024) Clock Config Register 4 */ + + struct { + __IOM unsigned int SOC_PLL_CLK_BYP_SEL : 2; /*!< [1..0] Selects one of the bypass clocks + for SoC PLL Clock */ + __IOM unsigned int I2S_PLL_CLK_BYP_SEL : 2; /*!< [3..2] Selects one of the bypass clocks + for I2S PLL Clock */ + __IOM unsigned int MODEM_PLL_CLK_BYP_SEL : 2; /*!< [5..4] Selects one of the bypass + clocks for Modem PLL Clock */ + __IOM unsigned int INTF_PLL_CLK_BYP_SEL : 2; /*!< [7..6] Selects one of the bypass clocks + for Intf PLL Clock */ + __IOM unsigned int SOC_INTF_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [8..8] Clock cleaner ON + Control for SoC PLL Bypass + Clock */ + __IOM unsigned int SOC_INTF_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [9..9] Clock cleaner OFF + Control for SoC PLL Bypass + Clock */ + __IOM unsigned int Reserved1 : 2; /*!< [11..10] It is recommended to write + these bits to 0. */ + __IOM unsigned int I2S_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [12..12] Clock cleaner ON Control + for I2S PLL Bypass Clock. */ + __IOM unsigned int I2S_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [13..13] Clock cleaner + OFF Control for I2S PLL + Bypass Clock. */ + __IOM unsigned int MODEM_PLL_BYPCLK_CLKCLNR_ON : 1; /*!< [14..14] Clock cleaner ON + Control for Modem PLL Bypass + Clock. */ + __IOM unsigned int MODEM_PLL_BYPCLK_CLKCLNR_OFF : 1; /*!< [15..15] Clock cleaner OFF + Control for Modem PLL Bypass + Clock. */ + __IOM unsigned int BYPASS_SOC_PLL_CLK : 1; /*!< [16..16] Select to choose bypass clock or + PLL clock 1b0 - soc_pll_clk 1b1 - One of + the bypass clocks based on + soc_pll_clk_byp_sel. */ + __IOM unsigned int BYPASS_I2S_PLL_CLK : 1; /*!< [17..17] Select to choose bypass clock or + PLL clock 1b0 - i2s_pll_clk 1b1 - One of + the bypass clocks based on + soc_pll_clk_byp_sel. */ + __IOM unsigned int BYPASS_MODEM_PLL_CLK1 : 1; /*!< [18..18] Select to choose bypass clock + or PLL clock 1b0 - modem_pll_clk1 + 1b1 - One of the bypass + clocks based on modem_pll_clk_byp_sel. + */ + __IOM unsigned int BYPASS_MODEM_PLL_CLK2 : 1; /*!< [19..19] Select to choose bypass clock + or PLL clock 1b0 - modem_pll_clk2 + 1b1 - One of the bypass + clocks based on modem_pll_clk_byp_sel. + */ + __IOM unsigned int BYPASS_INTF_PLL_CLK : 1; /*!< [20..20] Select to choose bypass clock + or PLL clock 1b0 - intf_pll_clk + 1b1 - One of the bypass clocks + based on soc_pll_clk_byp_sel. */ + __IOM unsigned int SLEEP_CLK_SEL : 2; /*!< [22..21] Select to choose sleep clk + 00 - ulp_32khz_rc_clk 01 + - ulp_32khz_xtal_clk 10 - + Gated 11 - ulp_32khz_ro_clk. */ + __IOM unsigned int Reserved2 : 2; /*!< [24..23] It is recommended to write + these bits to 0. */ + __IOM unsigned int ULPSS_CLK_DIV_FAC : 6; /*!< [30..25] Clock division factor for clock + to ULPSS. If ulpss_clk_enable is 1b0 clock + is gated. Else output clock is a divided + clock with the following frequency. 6h0 - + Divider is bypassed > 6h0 - clk_out = + clk_in/ 2* ulpss_clk_div_fac */ + __IOM unsigned int Reserved3 : 1; /*!< [31..31] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG4_b; + }; + + union { + __IOM unsigned int CLK_CONFIG_REG5; /*!< (@ 0x00000028) Clock Config Register 5 */ + + struct { + __IOM unsigned int M4_SOC_CLK_SEL : 4; /*!< [3..0] Selects one of the clock sources for + M4 SoC clock. These clocks are selected for + m4_soc_clk when 1)m4_soc_host_clk_sel is 1b0 or + 2)when m4_soc_host_clk_sel is 1b1, xtal is + ON(xtal_off from slp_fsm should be zero) and + host_clk_available(from host logic) is 1b0. + 0000 - ULP Ref Clock (generated inside M4SS + based on m4ss_ref_clk_sel from NPSS) 0001 - + Reserved 0010 - */ + __IOM unsigned int M4_SOC_CLK_DIV_FAC : 6; /*!< [9..4] Clock divison factor for NWP SoC + Clock If ta_soc_clk_enable(from NPSS) is + 1b0 clock is gated. Else output clock is a + swallowed clock with the following + frequency. 6h0,6h1 - Divider is bypassed + >6h1 - clk_out = clk_in/ ta_soc_clk_div_fac + */ + __IOM unsigned int I2S_CLK_SEL : 1; /*!< [10..10] Selects one of the following clocks for + config timer I2S interface 00/11 - I2S PLL Clock + (program bypass_i2s_pll_clk if the bypass clock + has to be selected) 01 - I2S PLL Clock_1 (program + bypass_i2s_pll_clk_1 if the bypass clock has to + be selected) 10 - + m4_soc_clk_for_other_clocks */ + __IOM unsigned int I2S_CLK_DIV_FAC : 6; /*!< [16..11] Clock division factor for i2s_clk. + Else output clock is a 50% divided clock with + the following frequency. 6h0 + - Divider is bypassed >6h0 - clk_out = + clk_in/ 2*i2s_clk_div_fac */ + __IOM unsigned int CT_CLK_SEL : 3; /*!< [19..17] Selects one of the following clocks for + config timer 000 - ulp ref Clock(generated inside + M4SS based on m4ss_ref_clk_sel from NPSS) 001 - + Intf PLL Clock(program bypass_intf_pll_clk if the + bypass clock has to be selected) 010 - SoC PLL + Clock(program bypass_soc_pll_clk if the bypass + clock has to be selected) 011 - + m4_soc_clk_for_other_clocks 100,110 - Invalid */ + __IOM unsigned int CT_CLK_DIV_FAC : 6; /*!< [25..20] Clock division factor for sct_clk. + If sct_clk_enable is 1b0 clock is gated. Else + output clock is a 50% divided clock with the + following frequency. 6h0 - Divider is bypassed + >6h0 - clk_out = clk_in/ + 2*sct_clk_div_fac */ + __IOM unsigned int M4_SOC_HOST_CLK_SEL : 1; /*!< [26..26] Selects the previous muxed + output(xtal_clk) or host_clk as the clock + source for M4 SoC clock based on the + following combinations of {xtal_off(from + slp fsm), host_clk_available(from host + logic),m4_soc_host_clk_sel} XX0 - xtal_clk + 001 - After wait time based on + mask_host_clk_wait_fix ; xtal_clk X11 + - host_clk 101 - No Clock */ + __IOM unsigned int Reserved1 : 1; /*!< [27..27] It is recommended to write + these bits to 0. */ + __IOM unsigned int ULPSS_ODD_DIV_SEL : 1; /*!< [28..28] Selects the type of divider for + m4_soc_clk_2ulpss 1b0 + - Clock Divider(even) is selected 1b1 + - Odd Divider is selected. */ + __IOM unsigned int Reserved2 : 2; /*!< [30..29] It is recommended to write + these bits to 0. */ + __IOM unsigned int I2S_CLK_SEL_1 : 1; /*!< [31..31] Selects one of the following clocks + for config timer for I2S interface 00/11 - I2S + PLL Clock (program bypass_i2s_pll_clk if the + bypass clock has to be selected) 01 - I2S PLL + Clock_1 (program bypass_i2s_pll_clk_1 if the + bypass clock has to be selected) 10 - + m4_soc_clk_for_other_clocks */ + } CLK_CONFIG_REG5_b; + }; + __IM unsigned int RESERVED[6]; + + union { + __IOM unsigned int DYN_CLK_GATE_DISABLE_REG; /*!< (@ 0x00000044) Dynamic Clock + Gate Disable Register */ + + struct { + __IOM unsigned int SDIO_SYS_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate + disable control sdio sys + clk1'b0 => Dynamic control of + the clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled */ + __IOM unsigned int BUS_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock gate disable + control bus clk1'b0 => Dynamic + control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM unsigned int Reserved1 : 2; /*!< [3..2] It is recommended to write these + bits to 0. */ + __IOM unsigned int GPDMA_HCLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock gate + disable control gpdma clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM unsigned int EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock gate + disable control egpio clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM unsigned int SGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate + disable control sgpio clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM unsigned int TOT_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate disable + control tot clk1'b0 => Dynamic + control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled + */ + __IOM unsigned int Reserved2 : 1; /*!< [8..8] It is recommended to write these + bits to 0. */ + __IOM unsigned int USART1_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock gate + disable control usart1 sclk1'b0 + => Dynamic control of the clock + is disbaled 1'b1 => Dynamic + control of the clock is + enabled. */ + __IOM unsigned int USART1_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock gate + disable control usart1 pclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM unsigned int USART2_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [11..11] Dynamic clock gate + disable control usart2 sclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM unsigned int USART2_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [12..12] Dynamic clock gate + disable control usart2 pclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM unsigned int Reserved3 : 2; /*!< [14..13] It is recommended to write + these bits to 0. */ + __IOM unsigned int SSI_SLV_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock gate + disable control ssi slave + sclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled */ + __IOM unsigned int SSI_SLV_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock gate + disable control ssi slave + pclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled */ + __IOM unsigned int Reserved4 : 2; /*!< [18..17] It is recommended to write + these bits to 0. */ + __IOM unsigned int SEMAPHORE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock gate + disable control semaphore + clk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic + control of the clock is + enabled. */ + __IOM unsigned int ARM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [20..20] Dynamic clock gate + disable control arm clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic control + of the clock is enabled. + */ + __IOM unsigned int SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [21..21] Dynamic clock gate + disable control ssi mst + sclk1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled. */ + __IOM unsigned int Reserved5 : 2; /*!< [23..22] It is recommended to write + these bits to 0. */ + __IOM unsigned int MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [24..24] Dynamic clock gate + disable control mem clk1'b0 => + Dynamic control of the clock is + disbaled 1'b1 => Dynamic + control of the clock is + enabled. */ + __IOM unsigned int Reserved6 : 3; /*!< [27..25] It is recommended to write + these bits to 0. */ + __IOM unsigned int SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [28..28] Dynamic clock gate + disable control ssi mst pclk + 1'b0 + => Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the clock + is enabled */ + __IOM unsigned int ICACHE_DYN_GATING_DISABLE_b : 1; /*!< [29..29] Dynamic clock gate + disable control icache clk1'b0 => + Dynamic control of the + clock is disbaled 1'b1 => Dynamic + control of the clock is + enabled */ + __IOM unsigned int Reserved7 : 1; /*!< [30..30] It is recommended to write + these bits to 0. */ + __IOM unsigned int MISC_CONFIG_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [31..31] Dynamic clock + gate disable control miscn + config pclk 1'b0 => + Dynamic control of the + clock is disbaled 1'b1 => + Dynamic control of the + clock is enabled. */ + } DYN_CLK_GATE_DISABLE_REG_b; + }; + __IM unsigned int RESERVED1[2]; + + union { + __IOM unsigned int PLL_ENABLE_SET_REG; /*!< (@ 0x00000050) PLL Enable Set Register */ + + struct { + __IOM unsigned int SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => + soft reset is enabled1'b0 + => Invalid */ + __IOM unsigned int Reserved1 : 31; /*!< [31..1] It is recommended to write + these bits to 0. */ + } PLL_ENABLE_SET_REG_b; + }; + + union { + __IOM unsigned int PLL_ENABLE_CLEAR_REG; /*!< (@ 0x00000054) PLL Enable Clear Register */ + + struct { + __IOM unsigned int SOCPLL_SPI_SW_RESET : 1; /*!< [0..0] SPI soft reset for SoC PLL1'b1 => + soft reset is disabled1'b0 + => Invalid */ + __IOM unsigned int Reserved1 : 31; /*!< [31..1] It is recommended to write + these bits to 0. */ + } PLL_ENABLE_CLEAR_REG_b; + }; + + union { + __IM unsigned int PLL_STAT_REG; /*!< (@ 0x00000058) PLL Status Register */ + + struct { + __IM unsigned int LCDPLL_LOCK : 1; /*!< [0..0] Lock Signal from LCD PLL */ + __IM unsigned int DDRPLL_LOCK : 1; /*!< [1..1] Lock Signal from DDR PLL */ + __IM unsigned int APPLL_LOCK : 1; /*!< [2..2] Lock Signal from AP PLL */ + __IM unsigned int INTFPLL_LOCK : 1; /*!< [3..3] Lock Signal from INTF PLL */ + __IM unsigned int I2SPLL_LOCK : 1; /*!< [4..4] Lock Signal from I2S PLL */ + __IM unsigned int SOCPLL_LOCK : 1; /*!< [5..5] Lock Signal from SoC PLL */ + __IM unsigned int MODEMPLL_LOCK : 1; /*!< [6..6] Lock Signal from Modem PLL */ + __IM unsigned int PLL_LOCK_DATA_TRIG : 1; /*!< [7..7] This is set to 1'b1 when the PLL + Locks are equal to pll_lock_int_data_r + g */ + __IM unsigned int M4_SOC_CLK_SWITCHED : 1; /*!< [8..8] Indication from M4 SoC + Clock Dynamic mux that the + switching happened */ + __IM unsigned int QSPI_CLK_SWITCHED : 1; /*!< [9..9] Indication from QSPI Clock Dynamic + mux that the switching happened */ + __IM unsigned int USART1_SCLK_SWITCHED : 1; /*!< [10..10] Indication from + USART1 Clock Dynamic mux that + the switching happened */ + __IM unsigned int USART2_SCLK_SWITCHED : 1; /*!< [11..11] Indication from + USART1 Clock Dynamic mux that + the switching happened */ + __IM unsigned int GEN_SPI_MST1_SCLK_SWITCHED : 1; /*!< [12..12] Indication from USART2 + Clock Dynamic mux that the + switching happened */ + __IM unsigned int SSI_MST_SCLK_SWITCHED : 1; /*!< [13..13] Indication from SSi + Master SClock Dynamic mux that + the switching happened */ + __IM unsigned int Reserved1 : 1; /*!< [14..14] It is recommended to write + these bits to 0. */ + __IM unsigned int CT_CLK_SWITCHED : 1; /*!< [15..15] Indication from SCT Clock Dynamic + mux that the switching happened */ + __IM unsigned int M4_TA_SOC_CLK_SWITCHED_SDIO : 1; /*!< [16..16] Indication + from M4-NWP Soc SDIO + Clock Dynamic mux that + the switching + happened(TBD) */ + __IM unsigned int I2S_CLK_SWITCHED : 1; /*!< [17..17] Indication from I2S Clock Dynamic + mux that the switching happened */ + __IM unsigned int PLL_INTF_CLK_SWITCHED : 1; /*!< [18..18] Indication from Pll + Intf Clock Dynamic mux that + the switching happened */ + __IM unsigned int Reserved2 : 2; /*!< [20..19] It is recommended to write + these bits to 0. */ + __IM unsigned int SLEEP_CLK_SWITCHED : 1; /*!< [21..21] Indication from Sleep + clcok Dynamic mux that the + switching happened */ + __IM unsigned int MCU_CLKOUT_SWITCHED : 1; /*!< [22..22] Indication from + mcu_clkout Dynamic mux that the + switching happened */ + __IM unsigned int QSPI_2_CLK_SWITCHED : 1; /*!< [23..23] Indication from QSPI + Clock Dynamic mux that the + switching happened */ + __IM unsigned int TASS_M4SS_64K_CLK_SWITCHED : 1; /*!< [24..24] Indication when NWP + accessing 2nd memory chunk of M4, + clock to Dynamic mux switching + happened */ + __IM unsigned int CC_CLOCK_MUX_SWITCHED : 1; /*!< [25..25] Indication from cc + clock Dynamic mux that the + switching happened */ + __IM unsigned int TASS_M4SS_192K_CLK_SWITCHED : 1; /*!< [26..26] Indication when NWP + accessing 0th memory chunk of M4, + clock to Dynamic mux switching + happened */ + __IM unsigned int USART1_CLK_SWITCHED : 1; /*!< [27..27] Indication from + usart1 sclk or pclk Dynamic mux + that the switching happened */ + __IM unsigned int USART2_CLK_SWITCHED : 1; /*!< [28..28] Indication from + usart2 sclk or pclk Dynamic mux + that the switching happened */ + __IM unsigned int TASS_M4SS_64K0_CLK_SWITCHED : 1; /*!< [29..29] Indication when NWP + accessing 1st memory chunk of M4, + clock to Dynamic mux switching + happened */ + __IM unsigned int CLK_FREE_OR_SLP_SWITCHED : 1; /*!< [30..30] Indication from + clk_free_or_slp Dynamic mux that the + switching happened */ + __IM unsigned int ULP_REF_CLK_SWITCHED : 1; /*!< [31..31] Indication from + ulp_ref_clk Dynamic mux that + the switching happened */ + } PLL_STAT_REG_b; + }; + + union { + __IOM unsigned int PLL_LOCK_INT_MASK_REG; /*!< (@ 0x0000005C) PLL Lock Interrupt + Mask Register */ + + struct { + __IOM unsigned int LCD_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM unsigned int DDR_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM unsigned int AP_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM unsigned int INTF_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int I2S_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM unsigned int SOC_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM unsigned int MODEM_PLL_LOCK_MASK_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b1 => + Masked;1'b0 => + Not Masked */ + __IOM unsigned int LCD_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int DDR_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int AP_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b1 => + Masked;1'b0 => Not Masked + */ + __IOM unsigned int INTF_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int I2S_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int SOC_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int MODEM_PLL_LOCK_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b1 => + Masked;1'b0 => Not + Masked */ + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_MASK_BIT_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b1 + => Masked;1'b0 + => Not Masked + */ + __IOM unsigned int Reserved1 : 16; /*!< [31..16] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_MASK_REG_b; + }; + + union { + __IOM unsigned int PLL_LOCK_INT_CLR_REG; /*!< (@ 0x00000060) PLL Lock Interrupt + Clear Register */ + + struct { + __IOM unsigned int LCD_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [0..0] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int DDR_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int AP_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int INTF_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int I2S_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int SOC_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int MODEM_PLL_LOCK_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => Not + Cleared 1'b1 => + Cleared */ + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 + => Not Cleared + 1'b1 => Cleared + */ + __IOM unsigned int LCD_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int DDR_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int AP_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int INTF_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => Not + Cleared 1'b1 => + Cleared */ + __IOM unsigned int I2S_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int SOC_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => Not + Cleared 1'b1 => Cleared + */ + __IOM unsigned int MODEM_PLL_LOCK_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => + Not Cleared 1'b1 => + Cleared */ + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_CLEAR_BIT_OF_FALLING_EDGE : 1; /*!< + [15..15] + 1'b0 + => + Not + Cleared + 1'b1 + => + Cleared + */ + __IOM unsigned int Reserved1 : 16; /*!< [31..16] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_CLR_REG_b; + }; + + union { + __IOM unsigned int PLL_LOCK_INT_DATA_REG; /*!< (@ 0x00000064) PLL Lock Interrupt + DATA Register */ + + struct { + __IOM unsigned int LCD_PLL_LOCK : 1; /*!< [0..0] 1'b1 => LCD PLL Lock has to be used as + trigger1'b0 => LCD PLL Lock not to be used as + trigger */ + __IOM unsigned int DDR_PLL_LOCK : 1; /*!< [1..1] 1'b1 => DDR PLL Lock has to be used as + trigger1'b0 => DDR PLL Lock not to be used as + trigger */ + __IOM unsigned int AP_PLL_LOCK : 1; /*!< [2..2] 1'b1 => AP PLL Lock has to be used as + trigger1'b0 => Ap PLL Lock not to be used as + trigger */ + __IOM unsigned int INTF_PLL_LOCK : 1; /*!< [3..3] 1'b1 => INTF PLL Lock has to + be used as trigger1'b0 => INTF PLL + Lock not to be used as trigger */ + __IOM unsigned int I2S_PLL_LOCK : 1; /*!< [4..4] 1'b1 => I2S PLL Lock has to be used as + trigger1'b0 => I2S PLL Lock not to be used as + trigger */ + __IOM unsigned int SOC_PLL_LOCK : 1; /*!< [5..5] 1'b1 => SoC PLL Lock has to be used as + trigger1'b0 => SoC PLL Lock not to be used as + trigger */ + __IOM unsigned int MODEM_PLL_LOCK : 1; /*!< [6..6] 1'b1 => Modem PLL Lock has + to be used as trigger1'b0 + => Modem PLL Lock not to be + used as trigger */ + __IOM unsigned int Reserved1 : 25; /*!< [31..7] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_DATA_REG_b; + }; + + union { + __IOM unsigned int SLEEP_CALIB_REG; /*!< (@ 0x00000068) Sleep Calib Register */ + + struct { + __IOM unsigned int SLP_CALIB_START_b : 1; /*!< [0..0] This bit is used to start the + calibration. 1b1 - Start calibration. + slp_calib_duration should be loaded before + this bit is set. This bit is + self-clearing. When read, + if high indicates the completion of + calibration process. */ + __IOM unsigned int SLP_CALIB_CYCLES : 2; /*!< [2..1] These bits are used to program the + number of clock cycles over which clock + calibration is to be done. */ + __IOM unsigned int SLP_CALIB_DURATION_b : 16; /*!< [18..3] Duration of the sleep clock in + terms of processor clocks. This has to + be divided with number of calibration + cycles to get number of clock + cycles(reference clock) in single clock + period). 1b1 - AP PLL Lock has to be + used as trigger1b0 + - Ap PLL Lock not to be used as + trigger */ + __IOM unsigned int SLP_CALIB_DONE_b : 1; /*!< [19..19] Indicates the end of + calibration */ + __IOM unsigned int Reserved1 : 12; /*!< [31..20] It is recommended to write + these bits to 0. */ + } SLEEP_CALIB_REG_b; + }; + + union { + __IOM unsigned int CLK_CALIB_CTRL_REG1; /*!< (@ 0x0000006C) Clock Calib Control + Register1 */ + + struct { + __IOM unsigned int CC_SOFT_RST_b : 1; /*!< [0..0] Soft Reset for clock + calibrator 1b1 - reset enabled 1b0 + - reset disabled. */ + __IOM unsigned int CC_START_b : 1; /*!< [1..1] start clk calibration 1b1 - start */ + __IOM unsigned int CC_CHANGE_TEST_CLK_b : 1; /*!< [2..2] change test clk. Set + this bit to 1'b1 only when + test_clk is being changed, + else this should be 1'b0. */ + __IOM unsigned int CC_CLKIN_SEL_b : 4; /*!< [6..3] select the clock to be calibrated 4d0 + - ulp_ref_clk 4d1 + - mems_ref_clk 4d2 - ulp_20mhz_ringosc_clk + 4d3 - modem_pll_clk1 4d4 - modem_pll_clk2 4d5 - + intf_pll_clk 4d6 - soc_pll_clk 4d7 - + i2s_pll_clk 4d8 - sleep_clk 4d9 - bus_clkby2_ap + */ + __IOM unsigned int Reserved1 : 25; /*!< [31..7] It is recommended to write + these bits to 0. */ + } CLK_CALIB_CTRL_REG1_b; + }; + + union { + __IOM unsigned int CLK_CALIB_CTRL_REG2; /*!< (@ 0x00000070) Clock Calib Control + Register2 */ + + struct { + __IOM unsigned int CC_NUM_REF_CLKS : 32; /*!< [31..0] number of ref_clk cycles to be + considered for calibrating. */ + } CLK_CALIB_CTRL_REG2_b; + }; + + union { + __IOM unsigned int CLK_CALIB_STS_REG1; /*!< (@ 0x00000074) Clock Calib Status + Register1 */ + + struct { + __IOM unsigned int CC_DONE_b : 1; /*!< [0..0] indicates clock calibratioon + done1'b1 => done1'b0 => none */ + __IOM unsigned int CC_ERROR_b : 1; /*!< [1..1] indicates clock calibration + error1'b1 => error1'b0 => none */ + __IOM unsigned int Reserved1 : 30; /*!< [31..2] It is recommended to write + these bits to 0. */ + } CLK_CALIB_STS_REG1_b; + }; + + union { + __IOM unsigned int CLK_CALIB_STS_REG2; /*!< (@ 0x00000078) Clock Calib Status + Register2 */ + + struct { + __IOM unsigned int CC_NUM_TEST_CLKS : 32; /*!< [31..0] number of test clk cycles occurred + for the specified number of ref_clk cycles + */ + } CLK_CALIB_STS_REG2_b; + }; + + union { + __IOM unsigned int CLK_CONFIG_REG6; /*!< (@ 0x0000007C) Clock Config Register6 */ + + struct { + __IOM unsigned int IID_KH_CLK_DIV_FAC : 3; /*!< [2..0] Clock division factor + for iid_clk. */ + __IOM unsigned int Reserved1 : 2; /*!< [4..3] It is recommended to write these + bits to 0. */ + __IOM unsigned int PADCFG_PCLK_DIV_FAC : 4; /*!< [8..5] Clock division factor + for pclk_pad_config_m4ss */ + __IOM unsigned int QSPI_2_CLK_SEL : 3; /*!< [11..9] Selects one of the following clocks + for ssi master 000 + - ULP Ref Clock(generated inside M4SS based on + m4ss_ref_clk_sel from NPSS) 001 - Intf PLL + Clock Clock (program bypass_intf_pll_clk if the + bypass clock has to be selected) 010 - Modem + PLL Clock2(Not Intended for the programmer) + (program bypass_modem_pll_clk if the bypass + clock has to be selected) 011 - SoC PLL Clock + */ + __IOM unsigned int QSPI_2_CLK_DIV_FAC : 6; /*!< [17..12] Clock divison factor for QSPI. + If qspi_clk_enable is 1b0 clock is gated. + Else 1)when qspi_clk_swallow_sel is 1b1 and + qspi_odd_div_sel is 1b0 output clock is a + swallowed clock with the following + frequency. 6h0,6h1 => clk_out = clk_in >6h1 + => clk_out = clk_in/ qspi_clk_div_fac + 2)when qspi_clk_swallow_sel is 1b0 */ + __IOM unsigned int QSPI_2_CLK_SWALLOW_SEL : 1; /*!< [18..18] Clock select for clock + swallow or clock divider for QSPI 1b0 + => 50% divider is selected with + division factor qspi_clk_div_fac 1b1 => + Swallowed clock is selected with + division factor qspi_clk_div_fac Before + Changing this ensure that the input + clocks are gated */ + __IOM unsigned int QSPI_2_ODD_DIV_SEL : 1; /*!< [19..19] Clock select for clock swallow + or 50% even clock divider or 50% odd + divider clock for QSPI 1b1 - 50% odd clock + divider output is selected with division + factor qspi_clk_div_fac 1b0 - 50% even + clock divider output or swallowed is + selected with division factor + qspi_clk_div_fac based on + qspi_clk_swallow_sel. */ + __IOM unsigned int Reserved2 : 12; /*!< [31..20] It is recommended to write + these bits to 0. */ + } CLK_CONFIG_REG6_b; + }; + + union { + __IOM unsigned int DYN_CLK_GATE_DISABLE_REG2; /*!< (@ 0x00000080) Dynamic Clock + Gate Disable Register2 */ + + struct { + __IOM unsigned int SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock gate + disable control soc pll spi + clk 1b1 + - Dynamic control of the + clock is disbaled 1b0 - + Dynamic control of the + clock is enabled */ + __IOM unsigned int Reserved1 : 2; /*!< [2..1] It is recommended to write these + bits to 0. */ + __IOM unsigned int CT_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock gate disable + control SCT pclk 1b1 - Dynamic + control of the clock is + disbaled 1b0 - Dynamic control + of the clock is enabled + */ + __IOM unsigned int Reserved2 : 2; /*!< [5..4] It is recommended to write these + bits to 0. */ + __IOM unsigned int EFUSE_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock gate + disable control efuse clk 1b1 - + Dynamic control of the clock is + disbaled 1b0 - Dynamic control + of the clock is enabled + */ + __IOM unsigned int EFUSE_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock gate + disable control efuse pclk 1b1 + - Dynamic control of the clock + is disbaled 1b0 - Dynamic + control of the clock is + enabled */ + __IOM unsigned int Reserved3 : 24; /*!< [31..8] It is recommended to write + these bits to 0. */ + } DYN_CLK_GATE_DISABLE_REG2_b; + }; + + union { + __IOM unsigned int PLL_LOCK_INT_STATUS_REG; /*!< (@ 0x00000084) PLL Lock + Interrupt Status Register */ + + struct { + __IOM unsigned int LCD_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [0..0] 1b0 - No Interrupt; 1b1 - + Interrupt encountered. */ + __IOM unsigned int DDR_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [1..1] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM unsigned int AP_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [2..2] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM unsigned int INTF_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [3..3] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int I2S_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [4..4] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM unsigned int SOC_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [5..5] 1'b0 => No Interrupt;1'b1 + => Interrupt encountered. */ + __IOM unsigned int MODEM_PLL_LOCK_OF_RISING_EDGE : 1; /*!< [6..6] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_INTR_OF_RISING_EDGE : 1; /*!< [7..7] 1'b0 => No + Interrupt;1'b1 => + Interrupt + encountered. */ + __IOM unsigned int LCD_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [8..8] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int DDR_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [9..9] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int AP_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [10..10] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int INTF_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [11..11] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int I2S_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [12..12] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int SOC_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [13..13] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int MODEM_PLL_LOCK_OF_FALLING_EDGE : 1; /*!< [14..14] 1'b0 => No + Interrupt;1'b1 => Interrupt + encountered. */ + __IOM unsigned int PLL_LOCK_DATA_TRIGGER_INTR_OF_FALLING_EDGE : 1; /*!< [15..15] 1'b0 => + No Interrupt;1'b1 + => Interrupt + encountered. */ + __IOM unsigned int Reserved1 : 16; /*!< [31..16] It is recommended to write + these bits to 0. */ + } PLL_LOCK_INT_STATUS_REG_b; + }; +} M4CLK_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== + */ +/* ================ TIME_PERIOD + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief In this the time periods of 32KHz RC clock, 32KHz RO clock and 32KHz + * XTAL clock can be calibrated (TIME_PERIOD) + */ + +typedef struct { /*!< (@ 0x24048200) TIME_PERIOD Structure */ + + union { + __IOM unsigned int MCU_CAL_RO_TIMEPERIOD_READ; /*!< (@ 0x00000000) RO timeperiod + read register */ + + struct { + __IM unsigned int TIMEPERIOD_RO : 25; /*!< [24..0] Calibrated RO timeperiod */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] reser */ + } MCU_CAL_RO_TIMEPERIOD_READ_b; + }; + + union { + __IOM unsigned int MCU_CAL_TIMER_CLOCK_PERIOD; /*!< (@ 0x00000004) MCU calender timer clock + period register */ + + struct { + __IOM unsigned int RTC_TIMER_CLK_PERIOD : 25; /*!< [24..0] RTC timer clock + period programmed by SOC */ + __IM unsigned int RESERVED1 : 6; /*!< [30..25] reser */ + __IM unsigned int SPI_RTC_TIMER_CLK_PERIOD_APPLIED_b : 1; /*!< [31..31] Indicated SOC + programmed rtc_timer clock + period is applied at KHz + clock domain */ + } MCU_CAL_TIMER_CLOCK_PERIOD_b; + }; + + union { + __IOM unsigned int MCU_CAL_TEMP_PROG_REG; /*!< (@ 0x00000008) temprature program + register */ + + struct { + __IOM unsigned int BYPASS_CALIB_PG : 1; /*!< [0..0] To bypass power gating and + keep all the blocks always on */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reser */ + __IOM unsigned int MAX_TEMP_CHANGE : 5; /*!< [20..16] maximum temperature change after + which rc calibration must be trigger */ + __IOM unsigned int TEMP_TRIGGER_TIME_SEL : 2; /*!< [22..21] temperature + trigger time select */ + __IOM unsigned int PERIODIC_TEMP_CALIB_EN : 1; /*!< [23..23] Enable periodic + checking of temperature */ + __IOM unsigned int RTC_TIMER_PERIOD_MUX_SEL : 1; /*!< [24..24] rtc timer + period mux select */ + __IM unsigned int RESERVED2 : 7; /*!< [31..25] reser */ + } MCU_CAL_TEMP_PROG_REG_b; + }; + + union { + __IOM unsigned int MCU_CAL_START_REG; /*!< (@ 0x0000000C) mcu cal start register */ + + struct { + __IOM unsigned int ALPHA_RO : 3; /*!< [2..0] alpha = 1/2^alpha_ro , averaging factor of + RO timeperiod T = alpha(t_inst) + (1- alpha )t_prev + */ + __IOM unsigned int ALPHA_RC : 3; /*!< [5..3] alpha = 1/2^alpha_rc , averaging factor of + RC timeperiod T = alpha(t_inst) + (1- alpha )t_prev + */ + __IOM unsigned int NO_OF_RO_CLKS : 4; /*!< [9..6] 2^no_of_ro_clks no of clocks + of ro clock counts for no of rc + clocks in that time to measure + timeperiod */ + __IOM unsigned int NO_OF_RC_CLKS : 3; /*!< [12..10] 2^no_of_rc_clocks = no of + rc clocks used in calibration */ + __IOM unsigned int RC_SETTLE_TIME : 3; /*!< [15..13] no of clocks of RO for the RC clk to + settle when enabled */ + __IOM unsigned int RO_TRIGGER_TIME_SEL : 2; /*!< [17..16] ro trigger time select */ + __IOM unsigned int RC_TRIGGER_TIME_SEL : 3; /*!< [20..18] rc trigger time select */ + __IOM unsigned int PERIODIC_RO_CALIB_EN : 1; /*!< [21..21] periodically calibrate RO + timeperiod based ro trigger time sel */ + __IOM unsigned int PERIODIC_RC_CALIB_EN : 1; /*!< [22..22] periodically calibrate RC + timeperiod based rc trigger time sel */ + __OM unsigned int START_CALIB_RO : 1; /*!< [23..23] to initiate RO calibration */ + __OM unsigned int START_CALIB_RC : 1; /*!< [24..24] to initiate RC calibration */ + __IOM unsigned int RC_XTAL_MUX_SEL : 1; /*!< [25..25] xtal mux select */ + __IOM unsigned int LOW_POWER_TRIGGER_SEL : 1; /*!< [26..26] power trigger select */ + __IOM unsigned int VBATT_TRIGGER_TIME_SEL : 3; /*!< [29..27] trigger to ipmu block for + checking vbatt status periodicaly */ + __IM unsigned int RESERVED1 : 2; /*!< [31..30] reser */ + } MCU_CAL_START_REG_b; + }; + + union { + __IOM unsigned int MCU_CAL_REF_CLK_SETTLE_REG; /*!< (@ 0x00000010) reference + clock settle register */ + + struct { + __IOM unsigned int XTAL_SETTLE : 7; /*!< [6..0] no of 32khz clocks for xtal + 40mhz clk to settle */ + __IM unsigned int RESERVED1 : 9; /*!< [15..7] reser */ + __IM unsigned int VALID_RC_TIMEPERIOD : 1; /*!< [16..16] Valid signal for reading RC + timeperiod calibrated */ + __IM unsigned int VALID_RO_TIMEPERIOD : 1; /*!< [17..17] Valid signal for + reading RO timeperiod */ + __IM unsigned int RESERVED2 : 14; /*!< [31..18] reser */ + } MCU_CAL_REF_CLK_SETTLE_REG_b; + }; + + union { + __IOM unsigned int MCU_CAL_RC_TIMEPERIOD_READ; /*!< (@ 0x00000014) rc timeperiod + read register */ + + struct { + __IM unsigned int TIMEPERIOD_RC : 25; /*!< [24..0] Calibrated RC timeperiod */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] reser */ + } MCU_CAL_RC_TIMEPERIOD_READ_b; + }; + + union { + __IOM unsigned int MCU_CAL_REF_CLK_TIEMPERIOD_REG; /*!< (@ 0x00000018) reference clock + timeperiod register */ + + struct { + __IOM unsigned int TIMEPERIOD_REF_CLK : 24; /*!< [23..0] timeperiod of reference clk with + each bit corresponding to granularity of + 2^27 = 1us */ + __IM unsigned int RESERVED1 : 8; /*!< [31..24] reser */ + } MCU_CAL_REF_CLK_TIEMPERIOD_REG_b; + }; +} TIME_PERIOD_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_WDT + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief A dedicated window watch dog timer for MCU applications (MCU_WDT) + */ + +typedef struct { /*!< (@ 0x24048300) MCU_WDT Structure */ + + union { + __IOM unsigned int MCU_WWD_INTERRUPT_TIMER; /*!< (@ 0x00000000) WATCHDOG + interrupt timer register */ + + struct { + __IOM unsigned int WWD_INTERRUPT_TIMER : 5; /*!< [4..0] Watchdog Timer + programming values */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reser */ + } MCU_WWD_INTERRUPT_TIMER_b; + }; + + union { + __IOM unsigned int MCU_WWD_SYSTEM_RESET_TIMER; /*!< (@ 0x00000004) MCU watchdog + system reset register */ + + struct { + __IOM unsigned int WWD_SYSTEM_RESET_TIMER : 5; /*!< [4..0] Watch dog soc reset delay + timer programming values */ + __IM unsigned int RESERVED1 : 27; /*!< [31..5] reser */ + } MCU_WWD_SYSTEM_RESET_TIMER_b; + }; + + union { + __IOM unsigned int MCU_WWD_WINDOW_TIMER; /*!< (@ 0x00000008) watchdog window + timer register */ + + struct { + __IOM unsigned int WINDOW_TIMER : 4; /*!< [3..0] watchdog window timer */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] reser */ + } MCU_WWD_WINDOW_TIMER_b; + }; + + union { + __IOM unsigned int MCU_WWD_ARM_STUCK_EN; /*!< (@ 0x0000000C) watchdog arm stuck + enable register */ + + struct { + __IM unsigned int RESERVED1 : 16; /*!< [15..0] reser */ + __OM unsigned int PROCESSOR_STUCK_RESET_EN : 1; /*!< [16..16] Enable to reset M4 core on + seeing LOCKUP signal */ + __IM unsigned int RESERVED2 : 7; /*!< [23..17] reser */ + __IM unsigned int PROCESSOR_STUCK_RESET_EN_ : 1; /*!< [24..24] Read signal for processor + stuck reset enable */ + __IM unsigned int RESERVED3 : 7; /*!< [31..25] reser */ + } MCU_WWD_ARM_STUCK_EN_b; + }; + + union { + __IOM unsigned int MCU_WWD_MODE_AND_RSTART; /*!< (@ 0x00000010) WATCHDOG mode + and restart register */ + + struct { + __IOM unsigned int WWD_MODE_RSTART : 1; /*!< [0..0] restart pulse to restart + watchdog timer */ + __IM unsigned int RESERVED1 : 15; /*!< [15..1] reser */ + __IOM unsigned int WWD_MODE_EN_STATUS : 8; /*!< [23..16] Watchdog timer mode */ + __IM unsigned int RESERVED2 : 8; /*!< [31..24] reser */ + } MCU_WWD_MODE_AND_RSTART_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int MCU_WWD_KEY_ENABLE; /*!< (@ 0x00000018) watchdog key enable + register */ + + struct { + __OM unsigned int WWD_KEY_ENABLE : 32; /*!< [31..0] enable access to program + Watch dog registers */ + } MCU_WWD_KEY_ENABLE_b; + }; +} MCU_WDT_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== + */ +/* ================ RTC + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The MCU calender acts as RTC with time in seconds, minutes, hours, + * days, months, years and centuries (RTC) + */ + +typedef struct { /*!< (@ 0x2404821C) RTC Structure */ + + union { + __IOM unsigned int MCU_CAL_ALARM_PROG_1; /*!< (@ 0x00000000) MCU calender alarm + prog register 1 */ + + struct { + __IOM unsigned int PROG_ALARM_MSEC : 10; /*!< [9..0] milli seconds value of + alarm time */ + __IOM unsigned int PROG_ALARM_SEC : 6; /*!< [15..10] seconds value of alarm time */ + __IOM unsigned int PROG_ALARM_MIN : 6; /*!< [21..16] mins value of alarm time */ + __IOM unsigned int PROG_ALARM_HOUR : 5; /*!< [26..22] hours value of alarm time */ + __IM unsigned int RESERVED1 : 5; /*!< [31..27] reser */ + } MCU_CAL_ALARM_PROG_1_b; + }; + + union { + __IOM unsigned int MCU_CAL_ALARM_PROG_2; /*!< (@ 0x00000004) MCU calender alarm + prog register 2 */ + + struct { + __IOM unsigned int PROG_ALARM_DAY : 5; /*!< [4..0] day count in alarm time 1-31 */ + __IM unsigned int RESERVED1 : 3; /*!< [7..5] reser */ + __IOM unsigned int PROG_ALARM_MONTH : 4; /*!< [11..8] month count in alarm time */ + __IM unsigned int RESERVED2 : 4; /*!< [15..12] reser */ + __IOM unsigned int PROG_ALARM_YEAR : 7; /*!< [22..16] year count in alarm time + 0 - 99 */ + __IOM unsigned int PROG_ALARM_CENTURY : 2; /*!< [24..23] century count in alarm time */ + __IM unsigned int RESERVED3 : 6; /*!< [30..25] reser */ + __IOM unsigned int ALARM_EN : 1; /*!< [31..31] alarm function enable for calendar */ + } MCU_CAL_ALARM_PROG_2_b; + }; + + union { + __IOM unsigned int MCU_CAL_POWERGATE_REG; /*!< (@ 0x00000008) MCU calender + powergate register */ + + struct { + __IOM unsigned int PG_EN_CALENDER : 1; /*!< [0..0] Start calender block */ + __IOM unsigned int ENABLE_CALENDER_COMBI : 1; /*!< [1..1] Enable calender + combitional logic block */ + __IOM unsigned int DISABLE_COMBI_DYN_PWRGATE_EN : 1; /*!< [2..2] Disable option for + dynamic combo RTC power gate */ + __IOM unsigned int STATIC_COMBI_RTC_PG_EN : 1; /*!< [3..3] Enable static combo + RTC power gate */ + __IM unsigned int RESERVED1 : 28; /*!< [31..4] RESERVED1 */ + } MCU_CAL_POWERGATE_REG_b; + }; + + union { + __IOM unsigned int MCU_CAL_PROG_TIME_1; /*!< (@ 0x0000000C) MCU calendar prog + time 1 register */ + + struct { + __IOM unsigned int PROG_MSEC : 10; /*!< [9..0] Milli seconds value to be programmed to + real time in calendar when pro_time_trig is 1 */ + __IOM unsigned int PROG_SEC : 6; /*!< [15..10] seconds value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IOM unsigned int PROG_MIN : 6; /*!< [21..16] minutes value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IOM unsigned int PROG_HOUR : 5; /*!< [26..22] hours value to be programmed to real time + in calendar when pro_time_trig is 1 */ + __IM unsigned int RESERVED2 : 5; /*!< [31..27] reser */ + } MCU_CAL_PROG_TIME_1_b; + }; + + union { + __IOM unsigned int MCU_CAL_PROG_TIME_2; /*!< (@ 0x00000010) MCU calendar prog + time 2 register */ + + struct { + __IOM unsigned int PROG_DAY : 5; /*!< [4..0] day count value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IOM unsigned int PROG_WEEK_DAY : 3; /*!< [7..5] program which week day it is */ + __IOM unsigned int PROG_MONTH : 4; /*!< [11..8] month value to be programmed to real time + in calendar when pro_time_trig is 1 */ + __IM unsigned int RES : 4; /*!< [15..12] reser */ + __IOM unsigned int PROG_YEAR : 7; /*!< [22..16] year value to be programmed to real time + in calendar when pro_time_trig is 1 */ + __IOM unsigned int PROG_CENTURY : 2; /*!< [24..23] century value to be programmed to real + time in calendar when pro_time_trig is 1 */ + __IM unsigned int RESERVED1 : 6; /*!< [30..25] reser */ + __OM unsigned int PROG_TIME_TRIG : 1; /*!< [31..31] load the programmed to the + real time in calendar block */ + } MCU_CAL_PROG_TIME_2_b; + }; + + union { + __IM unsigned int MCU_CAL_READ_TIME_MSB; /*!< (@ 0x00000014) MCU calendar read + time msb */ + + struct { + __IM unsigned int WEEK_DAY : 3; /*!< [2..0] week day */ + __IM unsigned int MONTHS_COUNT : 4; /*!< [6..3] months count */ + __IM unsigned int YEAR_COUNT : 7; /*!< [13..7] years count */ + __IM unsigned int CENTURY_COUNT : 2; /*!< [15..14] century count */ + __IM unsigned int RESERVED1 : 16; /*!< [31..16] reser */ + } MCU_CAL_READ_TIME_MSB_b; + }; + + union { + __IM unsigned int MCU_CAL_READ_TIME_LSB; /*!< (@ 0x00000018) MCU calendar read + time lsb */ + + struct { + __IM unsigned int MILLISECONDS_COUNT : 10; /*!< [9..0] milliseconds count */ + __IM unsigned int SECONDS_COUNT : 6; /*!< [15..10] seconds count */ + __IM unsigned int MINS_COUNT : 6; /*!< [21..16] mins count */ + __IM unsigned int HOURS_COUNT : 5; /*!< [26..22] hours count */ + __IM unsigned int DAYS_COUNT : 5; /*!< [31..27] days count */ + } MCU_CAL_READ_TIME_LSB_b; + }; + + union { + __IM unsigned int MCU_CAL_READ_COUNT_TIMER; /*!< (@ 0x0000001C) MCU calendar + read count timer */ + + struct { + __IM unsigned int READ_COUNT_TIMER : 27; /*!< [26..0] Read timer which increments by + time period value to reach to count + milliseconds */ + __IM unsigned int RESERVED1 : 5; /*!< [31..27] reser */ + } MCU_CAL_READ_COUNT_TIMER_b; + }; + + union { + __IM unsigned int MCU_CAL_SLEEP_CLK_COUNTERS; /*!< (@ 0x00000020) MCU calendar + sleep clock counter */ + + struct { + __IM unsigned int SLEEP_CLK_DURATION : 12; /*!< [11..0] No of sleep clks with respect to + APB clock so far from + the posedge of sleep clk */ + __IM unsigned int RESERVED1 : 4; /*!< [15..12] reser */ + __IM unsigned int PCLK_COUNT_WRT_SLEEP_CLK : 12; /*!< [27..16] no. of APB clks in 1 + sleep clock duration */ + __IM unsigned int RESERVED2 : 4; /*!< [31..28] reser */ + } MCU_CAL_SLEEP_CLK_COUNTERS_b; + }; + + union { + __OM unsigned int MCU_CAL_KEY_EANBLE; /*!< (@ 0x00000024) MCU calendar key enable */ + + struct { + __OM unsigned int RTC_KEY : 32; /*!< [31..0] enable access to program Watch + dog registers */ + } MCU_CAL_KEY_EANBLE_b; + }; +} RTC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== + */ +/* ================ BATT_FF + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The use of this is to store some information in ULP over wake-ups to + * reduce wake-up time (BATT_FF) + */ + +typedef struct { /*!< (@ 0x24048400) BATT_FF Structure */ + + union { + __IOM unsigned int M4SS_BYPASS_PWRCTRL_REG1; /*!< (@ 0x00000000) M4ss bypass + power control register 1 */ + + struct { + __IM unsigned int RES : 3; /*!< [2..0] reserved1 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_ULP_AON_b : 1; /*!< [3..3] Enables software + based control of isolation + and reset + for ULP AON M4ss */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_EFUSE_b : 1; /*!< [4..4] Enables software based + control of isolation and reset + for ULP EFUSE */ + __IOM unsigned int RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_RPDMA_b : 1; /*!< [9..9] Enables software based + control of isolation and reset + for RPDMA */ + __IOM unsigned int RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Enables + software based control of + isolation and reset for + HIF SDIO SPI */ + __IOM unsigned int RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Enables + software based control of + isolation and reset for + ULP quad SPI and ICACHE + */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_IID_b : 1; /*!< [14..14] Enables software based + control of isolation and reset + for ULP IID */ + __IOM unsigned int RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM + unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_DEBUG_b : 1; /*!< [17..17] Enables + software based control + of isolation and reset + for M4ss DEBUG */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b : 1; /*!< [18..18] Enables software + based control of isolation + and reset for M4ss CORE */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_AON_b : 1; /*!< [19..19] Enables software based + control of isolation and reset + for ULP AON */ + __IM unsigned int RESERVED6 : 2; /*!< [21..20] reserved6 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_ROM_b : 1; /*!< [22..22] Enables software based + control of isolation and reset + for M4ss ROM */ + __IM unsigned int RESERVED7 : 9; /*!< [31..23] reserved7 */ + } M4SS_BYPASS_PWRCTRL_REG1_b; + }; + + union { + __IOM unsigned int M4SS_BYPASS_PWRCTRL_REG2; /*!< (@ 0x00000004) M4SS bypass + power control register 2 */ + + struct { + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_SRAM_1 : 10; /*!< [9..0] Enables software based + control of isolation and reset + for M4ss SRAM 1 */ + __IM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int BYPASS_M4SS_PWRCTL_ULP_SRAM_2 : 4; /*!< [19..16] Enables software + based control of isolation and + reset for M4ss SRAM 2 */ + __IM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4SS_BYPASS_PWRCTRL_REG2_b; + }; + + union { + __IOM unsigned int M4SS_PWRCTRL_SET_REG; /*!< (@ 0x00000008) M4SS power control + set register */ + + struct { + __IM unsigned int RES : 4; /*!< [3..0] reserved1 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for + EFUSE */ + __IM unsigned int RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for + RPDMA */ + __IM unsigned int RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate + control for HIF SDIO SPI + */ + __IM unsigned int RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate + control for QSPI and + ICACHE */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for + IID Block.If set, powered ON + Clearing this bit has no effect */ + __IM unsigned int RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control + for M4 DEBUG */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control + for M4 CORE */ + __IM unsigned int RESERVED6 : 3; /*!< [21..19] reserved6 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate + enable signal for ROM */ + __IM unsigned int RESERVED7 : 9; /*!< [31..23] reserved7 */ + } M4SS_PWRCTRL_SET_REG_b; + }; + + union { + __IOM unsigned int M4SS_PWRCTRL_CLEAR_REG; /*!< (@ 0x0000000C) M4SS power + control clear register */ + + struct { + __IM unsigned int RES : 4; /*!< [3..0] reserved1 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_EFUSE_b : 1; /*!< [4..4] Power Gate control for + EFUSE */ + __IM unsigned int RESERVED2 : 4; /*!< [8..5] reserved2 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_RPDMA_b : 1; /*!< [9..9] Power Gate control for + RPDMA */ + __IM unsigned int RESERVED3 : 1; /*!< [10..10] reserved3 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_HIF_SDIO_SPI_b : 1; /*!< [11..11] Power Gate + control for HIF SDIO SPI + */ + __IM unsigned int RESERVED4 : 1; /*!< [12..12] reserved4 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_QSPI_ICACHE_b : 1; /*!< [13..13] Power Gate + control for QSPI and + ICACHE */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_IID_b : 1; /*!< [14..14] Power Gate control for + IID Block.If set, powered ON + Clearing this bit has no effect */ + __IM unsigned int RESERVED5 : 2; /*!< [16..15] reserved5 */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_DEBUG_b : 1; /*!< [17..17] Power Gate control + for M4 DEBUG */ + __IOM unsigned int M4SS_PWRGATE_EN_N_ULP_M4_CORE_b : 1; /*!< [18..18] Power Gate control + for M4 CORE */ + __IM unsigned int RESERVED6 : 3; /*!< [21..19] reserved6 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_ROM_b : 1; /*!< [22..22] External power gate + enable signal for ROM */ + __IM unsigned int RESERVED7 : 9; /*!< [31..23] reserved7 */ + } M4SS_PWRCTRL_CLEAR_REG_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG1; /*!< (@ 0x00000010) M4SS power + control set register 1 */ + + struct { + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control + signal for M4SS SRAM */ + __IM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control + signal for TASS SRAM shared + with M4SS */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG1_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000014) M4SS power + control clear register 1 */ + + struct { + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_1 : 10; /*!< [9..0] Functional Control + signal for M4SS SRAM */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_2 : 4; /*!< [19..16] Functional Control + signal for TASS SRAM shared + with M4SS */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG1_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000018) M4SS power + control set register 2 */ + + struct { + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional + Control signal for M4SS + SRAM Dual Rail pins */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional + Control signal for TASS + SRAM Dual Rail pins + shared with M4SS */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG2_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x0000001C) M4SS power + control clear register 2 */ + + struct { + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 10; /*!< [9..0] Functional + Control signal for M4SS + SRAM Dual Rail pins */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_2 : 4; /*!< [19..16] Functional + Control signal for TASS + SRAM Dual Rail pins + shared with M4SS */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG2_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG3; /*!< (@ 0x00000020) M4SS power + control set register 3 */ + + struct { + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input + isolation control for + M4SS SRAM */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input + isolation control for + TASS SRAM shared with + M4SS */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG3_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000024) M4SS power + control clear register 3 */ + + struct { + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_1 : 10; /*!< [9..0] Input + isolation control for + M4SS SRAM */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int M4SS_SRAM_INPUT_DISABLE_ISOLATION_ULP_2 : 4; /*!< [19..16] Input + isolation control for + TASS SRAM shared with + M4SS */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG3_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_SET_REG4; /*!< (@ 0x00000028) M4SS power + control set register 4 */ + + struct { + __IOM unsigned int M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for + M4SS SRAM */ + __IOM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ + } M4_SRAM_PWRCTRL_SET_REG4_b; + }; + + union { + __IOM unsigned int M4_SRAM_PWRCTRL_CLEAR_REG4; /*!< (@ 0x0000002C) M4SS power + control clear register 4 */ + + struct { + __IOM unsigned int M4SS_SRAM_DS_1 : 24; /*!< [23..0] Deep-Sleep control for + M4SS SRAM */ + __IOM unsigned int RESERVED1 : 8; /*!< [31..24] reserved1 */ + } M4_SRAM_PWRCTRL_CLEAR_REG4_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int M4SS_TASS_CTRL_SET_REG; /*!< (@ 0x00000034) M4SS_TASS control + set register */ + + struct { + __IOM unsigned int M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power + supply for TASS AON domain */ + __IOM unsigned int M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS + controlling Power supply + for TASS AON domains + isolation enable in + bypass mode */ + __IOM unsigned int M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS + controlling Power supply + for TASS AON domains + reset + pin in bypass mode */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } M4SS_TASS_CTRL_SET_REG_b; + }; + + union { + __IOM unsigned int M4SS_TASS_CTRL_CLEAR_REG; /*!< (@ 0x00000038) M4SS_TASS + control CLEAR register */ + + struct { + __IOM unsigned int M4SS_CTRL_TASS_AON_PWRGATE_EN : 1; /*!< [0..0] M4SS controlling Power + supply for TASS AON domain */ + __IOM unsigned int M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS : 1; /*!< [1..1] M4SS + controlling Power supply + for TASS AON domains + isolation enable in + bypass mode */ + __IOM unsigned int M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS : 1; /*!< [2..2] M4SS + controlling Power supply + for TASS AON domains + reset + pin in bypass mode */ + __IOM unsigned int RESERVED1 : 29; /*!< [31..3] reserved1 */ + } M4SS_TASS_CTRL_CLEAR_REG_b; + }; + + union { + __IOM unsigned int M4_ULP_MODE_CONFIG; /*!< (@ 0x0000003C) m4 ulp mode config register */ + + struct { + __IOM unsigned int ULPMODE_ISOLATION_CTRL_ULPSS : 1; /*!< [0..0] Isolation Control for + ULP-Mode non-functional paths for + ULPSS */ + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4SS_AON : 1; /*!< [1..1] Isolation Control for + ULP-Mode non-functional paths + for M4SS-AON */ + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_ULP : 1; /*!< [2..2] Isolation Control for + ULP-Mode non-functional paths + for M4ULP_AON */ + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_CORE : 1; /*!< [3..3] Isolation Control for + ULP-Mode non-functional paths + for M4_CORE */ + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_DEBUG_FPU : 1; /*!< [4..4] Isolation Control + for ULP-Mode + non-functional paths for + M4_DEBUG */ + __IOM unsigned int ULPMODE_ISOLATION_CTRL_M4_ROM : 1; /*!< [5..5] Isolation Control for + ULP-Mode non-functional paths + for ROM */ + __IOM unsigned int RES : 26; /*!< [31..6] reserved1 */ + } M4_ULP_MODE_CONFIG_b; + }; + + union { + __IOM unsigned int ULPSS_BYPASS_PWRCTRL_REG; /*!< (@ 0x00000040) ULPSS bypass + power control register */ + + struct { + __IOM unsigned int RES : 2; /*!< [1..0] reserved1 */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_AON : 1; /*!< [2..2] Enables software based + control of output isolation for + ULPTASS AON */ + __IOM + unsigned int BYPASS_ULPSDCSS_PWRCTRL_ULP_AON : 1; /*!< [3..3] Enables software + based control of output + isolation for + ULPSDCSS AON */ + __IOM unsigned int RESERVED2 : 1; /*!< [4..4] reser */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_MISC : 1; /*!< [5..5] Enables software based + control of output isolation for + ULP MISC */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_CAP : 1; /*!< [6..6] Enables software based + control of output isolation for + ULP CAP */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_VAD : 1; /*!< [7..7] Enables software based + control of output isolation for + ULP VAD */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_UART : 1; /*!< [8..8] Enables software based + control of output isolation for + ULP UART */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_SSI : 1; /*!< [9..9] Enables software based + control of output isolation for + ULP SSI */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_I2S : 1; /*!< [10..10] Enables software + based control of output + isolation for ULP I2S */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_I2C : 1; /*!< [11..11] Enables software + based control of output + isolation for ULP I2C */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_AUX : 1; /*!< [12..12] Enables software + based control of output isolation + for ULP AUX */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_IR : 1; /*!< [13..13] Enables software based + control of output isolation + for ULP IR */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_UDMA : 1; /*!< [14..14] Enables software + based control of output + isolation for ULP UDMA */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_FIM : 1; /*!< [15..15] Enables software + based control of output + isolation for ULP FIM */ + __IOM unsigned int RESERVED3 : 3; /*!< [18..16] reserved1 */ + __IOM unsigned int BYPASS_ULPTASS_PWRCTL_ULP_SRAM : 4; /*!< [22..19] Enables software + based control of output + isolation for ULPTASS SRAM */ + __IOM unsigned int RESERVED4 : 9; /*!< [31..23] reserved1 */ + } ULPSS_BYPASS_PWRCTRL_REG_b; + }; + + union { + __IOM unsigned int ULPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000044) ULPSS power + control set register */ + + struct { + __IOM unsigned int RES : 18; /*!< [17..0] reserved1 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional + Control signal for ULPTASS + MISC */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control + signal for ULPTASS CAP */ + __IOM unsigned int RESERVED2 : 1; /*!< [20..20] reserved2 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional + Control signal for ULPTASS + UART */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control + signal for ULPTASS SSI */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control + signal for ULPTASS I2S */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control + signal for ULPTASS I2C */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control + signal for ULPTASS AUX */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control + signal for ULPTASS IR */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional + Control signal for ULPTASS + UDMA */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control + signal for ULPTASS FIM */ + __IOM unsigned int RESERVED3 : 3; /*!< [31..29] RESERVED3 */ + } ULPSS_PWRCTRL_SET_REG_b; + }; + + union { + __IOM unsigned int ULPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000048) ULPSS power + control clear register */ + + struct { + __IOM unsigned int RESERVED1 : 18; /*!< [17..0] reserved1 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_MISC : 1; /*!< [18..18] Functional + Control signal for ULPTASS + MISC */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_CAP : 1; /*!< [19..19] Functional Control + signal for ULPTASS CAP */ + __IOM unsigned int RESERVED2 : 1; /*!< [20..20] reserved2 */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UART : 1; /*!< [21..21] Functional + Control signal for ULPTASS + UART */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SSI : 1; /*!< [22..22] Functional Control + signal for ULPTASS SSI */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2S : 1; /*!< [23..23] Functional Control + signal for ULPTASS I2S */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_I2C : 1; /*!< [24..24] Functional Control + signal for ULPTASS I2C */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_AUX : 1; /*!< [25..25] Functional Control + signal for ULPTASS AUX */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_IR : 1; /*!< [26..26] Functional Control + signal for ULPTASS IR */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_UDMA : 1; /*!< [27..27] Functional + Control signal for ULPTASS + UDMA */ + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_FIM : 1; /*!< [28..28] Functional Control + signal for ULPTASS FIM */ + __IOM unsigned int RESERVED3 : 3; /*!< [31..29] RESERVED3 */ + } ULPSS_PWRCTRL_CLEAR_REG_b; + }; + + union { + __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG1; /*!< (@ 0x0000004C) ULPSS ram power control + set register1 */ + + struct { + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control + signal for ULPSS SRAM pins + */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_SET_REG1_b; + }; + + union { + __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG1; /*!< (@ 0x00000050) ULPSS ram power + control clear register1 */ + + struct { + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM : 4; /*!< [3..0] Functional Control + signal for ULPSS SRAM pins + */ + __IOM unsigned int RESERVED1 : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_CLEAR_REG1_b; + }; + + union { + __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG2; /*!< (@ 0x00000054) ULPSS ram power control + set register2 */ + + struct { + __IOM unsigned int ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input + isolation control for + ULPTASS SRAM */ + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM unsigned int SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control + for ULPTASS SRAM */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } ULPSS_RAM_PWRCTRL_SET_REG2_b; + }; + + union { + __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG2; /*!< (@ 0x00000058) ULPSS ram power + control clear register2 */ + + struct { + __IOM unsigned int ULPTASS_SRAM_INPUT_DISABLE_ISOLATION_ULP : 4; /*!< [3..0] Input + isolation control for + ULPTASS SRAM */ + __IOM unsigned int RESERVED1 : 12; /*!< [15..4] reserved1 */ + __IOM unsigned int SRAM_DS_ULP_PROC_1 : 4; /*!< [19..16] Deep-Sleep control + for ULPTASS SRAM */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] reserved1 */ + } ULPSS_RAM_PWRCTRL_CLEAR_REG2_b; + }; + + union { + __IOM unsigned int ULPSS_RAM_PWRCTRL_SET_REG3; /*!< (@ 0x0000005C) ULPSS ram power control + set register3 */ + + struct { + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional + Control signal for + ULPTASS SRAM Dual Rail + pins */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_SET_REG3_b; + }; + + union { + __IOM unsigned int ULPSS_RAM_PWRCTRL_CLEAR_REG3; /*!< (@ 0x00000060) ULPSS ram power + control clear register3 */ + + struct { + __IOM unsigned int ULPTASS_EXT_PWRGATE_EN_N_ULP_SRAM_PERI_1 : 4; /*!< [3..0] Functional + Control signal for + ULPTASS SRAM Dual Rail + pins */ + __IOM unsigned int RES : 28; /*!< [31..4] reserved1 */ + } ULPSS_RAM_PWRCTRL_CLEAR_REG3_b; + }; + + union { + __IOM unsigned int MCU_FSM_CTRL_BYPASS; /*!< (@ 0x00000064) MCU FSM control + bypass register */ + + struct { + __IOM unsigned int MCU_XTAL_EN_40MHZ_BYPASS_CTRL : 1; /*!< [0..0] Xtal 40mhz enable + bypass from MCU */ + __IOM unsigned int MCU_XTAL_EN_40MHZ_BYPASS : 1; /*!< [1..1] Value of Xtal + Enable in bypass mode */ + __IOM unsigned int MCU_PMU_SHUT_DOWN_BYPASS_CTRL : 1; /*!< [2..2] Enable bypass mode to + Control pmu shut down */ + __IOM unsigned int MCU_PMU_SHUT_DOWN_BYPASS : 1; /*!< [3..3] Value of pmu shutdown in + bypass mode */ + __IOM unsigned int MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL : 1; /*!< [4..4] Enable software + control for buck boost + enable */ + __IOM unsigned int MCU_BUCK_BOOST_ENABLE_BYPASS : 1; /*!< [5..5] Value for MCU BuckBoost + Enable in bypass mode */ + __IOM unsigned int RES : 26; /*!< [31..6] reserved1 */ + } MCU_FSM_CTRL_BYPASS_b; + }; + + union { + __IOM unsigned int MCU_PMU_LDO_CTRL_SET; /*!< (@ 0x00000068) MCU PMU LD0 control + set register */ + + struct { + __IOM unsigned int MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ + __IOM unsigned int MCU_SCO_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ + __IOM unsigned int MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ + __IOM unsigned int RESER : 14; /*!< [16..3] reserved1 */ + __IOM unsigned int MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low + Voltage selection */ + __IOM unsigned int MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low + Voltage selection */ + __IOM unsigned int RES : 13; /*!< [31..19] reserved1 */ + } MCU_PMU_LDO_CTRL_SET_b; + }; + + union { + __IOM unsigned int MCU_PMU_LDO_CTRL_CLEAR; /*!< (@ 0x0000006C) MCU PMU LD0 + control clear register */ + + struct { + __IOM unsigned int MCU_FLASH_LDO_EN : 1; /*!< [0..0] Enable Flash LDO from M4SS */ + __IOM unsigned int MCU_SOC_LDO_EN : 1; /*!< [1..1] Enable SoC LDO from M4SS */ + __IOM unsigned int MCU_DCDC_EN : 1; /*!< [2..2] Enable PMU DCDC from M4SS */ + __IOM unsigned int RESER : 14; /*!< [16..3] reserved1 */ + __IOM unsigned int MCU_SOC_LDO_LVL : 1; /*!< [17..17] PMU SOC LDO High and Low + Voltage selection */ + __IOM unsigned int MCU_DCDC_LVL : 1; /*!< [18..18] PMU DCDC High and Low + Voltage selection */ + __IOM unsigned int RES : 13; /*!< [31..19] reserved1 */ + } MCU_PMU_LDO_CTRL_CLEAR_b; + }; + __IM unsigned int RESERVED1[4]; + + union { + __IOM unsigned int PLLCCI_PWRCTRL_REG; /*!< (@ 0x00000080) PLL CCI power control + register */ + + struct { + __IOM unsigned int I2SPLL_ISO_EN : 1; /*!< [0..0] Enables software based control of + isolation and reset for I2SPLL */ + __IOM unsigned int I2SPLL_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ + __IOM unsigned int INTFPLL_ISO_EN : 1; /*!< [2..2] Enables software based control of + isolation and reset for INTF PLL */ + __IOM unsigned int INTFPLL_BYPASS_ISO_GEN : 1; /*!< [3..3] Isolation value */ + __IOM unsigned int SOCPLL_ISO_ENABLE : 1; /*!< [4..4] Enables software based control of + isolation and reset for SOCPLL */ + __IOM unsigned int SOCPLL_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ + __IOM unsigned int SOCPLL_SPI_PG_EN : 1; /*!< [6..6] SOCPLL SPI Power Control */ + __IOM unsigned int SOCPLL_VDD13_ISO_EN : 1; /*!< [7..7] SOCPLL MACRO POC Control */ + __IOM unsigned int RES : 24; /*!< [31..8] reserved1 */ + } PLLCCI_PWRCTRL_REG_b; + }; + + union { + __IOM unsigned int DLL_PWRCTRL_REG; /*!< (@ 0x00000084) DLL power control register */ + + struct { + __IOM unsigned int QSPI_DLL_RX_ISO_ENABLE : 1; /*!< [0..0] Enables software based control + of isolation and reset + for QSPI_DLL_TX */ + __IOM unsigned int QSPI_DLL_RX_BYPASS_ISO_GEN : 1; /*!< [1..1] Isolation value */ + __IOM unsigned int QSPI_DLL_RX_PG_EN_N : 1; /*!< [2..2] QPSI DLL RX Power Control */ + __IOM unsigned int RESER : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int QSPI_DLL_TX_ISO_ENABLE : 1; /*!< [4..4] Enables software based control + of isolation and reset + for QSPI_DLL_TX */ + __IOM unsigned int QSPI_DLL_TX_BYPASS_ISO_GEN : 1; /*!< [5..5] Isolation value */ + __IOM unsigned int QSPI_DLL_TX_PG_EN_N : 1; /*!< [6..6] QPSI DLL TX Power Control */ + __IOM unsigned int RESERVED1 : 25; /*!< [31..7] reserved1 */ + } DLL_PWRCTRL_REG_b; + }; +} BATT_FF_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_FSM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief This is explain the Sleep FSM registers. (MCU_FSM) + */ + +typedef struct { /*!< (@ 0x24048100) MCU_FSM Structure */ + + union { + __IOM unsigned int MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE; /*!< (@ 0x00000000) Sleep Control + Signals and Wakeup source + selection */ + + struct { + __IOM unsigned int MCUFSM_SHUTDOWN_ENABLE : 1; /*!< [0..0] shutdown enable pulse. */ + __IOM unsigned int Reserved1 : 1; /*!< [1..1] It is recommended to write these + bits to 0. */ + __IOM unsigned int LP_SLEEP_MODE_b : 1; /*!< [2..2] setting this bit enables retention of + TASS-RAM, M4SS-RAM in PS2 Active/Sleep state + */ + __IOM unsigned int M4SS_RAM_RETENTION_MODE_EN : 1; /*!< [3..3] shutdown enable + pulse. */ + __IOM unsigned int M4ULP_RAM_RETENTION_MODE_EN_b : 1; /*!< [4..4] RAM retention enable + for ULP M4 ram during deep sleep + */ + __IOM unsigned int TA_RAM_RETENTION_MODE_EN : 1; /*!< [5..5] RAM retention enable for NWP + ram during deep sleep */ + __IOM unsigned int ULPSS_RAM_RETENTION_MODE_EN : 1; /*!< [6..6] RAM retention enable for + ulpss ram during deep sleep */ + __IOM unsigned int M4ULP_RAM16K_RETENTION_MODE_EN : 1; /*!< [7..7] To enable retention + mode for m4ulp 16k RAM */ + __IOM unsigned int LDO_SOC_ON_b : 1; /*!< [8..8] ON ldo soc during deep sleep */ + __IOM unsigned int LDO_FLASH_ON_b : 1; /*!< [9..9] ON flash ldo during deep sleep */ + __IOM unsigned int PMU_DCDC_ON_b : 1; /*!< [10..10] 1: PMU DCDC(BUCK) ON,0: + PMU DCDC(BUCK) OFF. */ + __IOM unsigned int SKIP_XTAL_WAIT_TIME : 1; /*!< [11..11] 1 : Skips Xtal Good + Delay wait time. */ + __IOM unsigned int Reserved2 : 2; /*!< [13..12] It is recommended to write + these bits to 0. */ + __IOM unsigned int MCUFSM_WAKEUP_NWPFSM : 1; /*!< [14..14] When Set, mcufsm wakeup enable + will wakeup both NWP FSM and MCU + FSM.Clear this BIT if this feature is not + required.. */ + __IOM unsigned int SLEEP_WAKEUP : 1; /*!< [15..15] Wakeup indication from Processor */ + __IOM unsigned int TIMER_BASED_WAKEUP_b : 1; /*!< [16..16] wakeup enable after deep sleep + counter elapses */ + __IOM unsigned int HOST_BASED_WAKEUP_b : 1; /*!< [17..17] host based wakeup enable */ + __IOM unsigned int WIRELESS_BASED_WAKEUP_b : 1; /*!< [18..18] wireless based + wakeup enable */ + __IOM unsigned int M4_PROC_BASED_WAKEUP_b : 1; /*!< [19..19] wakeup based on + m4 processor enable */ + __IOM unsigned int GPIO_BASED_WAKEUP_b : 1; /*!< [20..20] wakeup on gpio interrupt enable + based in configuration in GPIO WAKEUP + REGISTER */ + __IOM unsigned int COMPR_BASED_WAKEUP_b : 1; /*!< [21..21] compartor based + wakeup enable, either of any 6 + comparator interrupts */ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + __IOM unsigned int SYSRTC_BASED_WAKEUP_b : 1; /*!< [22..22] SYSRTC Based Wakeup */ +#else + __IOM unsigned int Reserved3 : 1; /*!< [22..22] It is recommended to write + these bits to 0. */ +#endif + __IOM unsigned int WIC_BASED_WAKEUP_b : 1; /*!< [23..23] WIC based wakeup mask */ + __IOM unsigned int ULPSS_BASED_WAKEUP_b : 1; /*!< [24..24] ULPSS peripheral + based wakeup */ + __IOM unsigned int SDCSS_BASED_WAKEUP_b : 1; /*!< [25..25] Sensor Data + collector based wakeup */ + __IOM unsigned int ALARM_BASED_WAKEUP_b : 1; /*!< [26..26] Alarm Based wakeup */ + __IOM unsigned int SEC_BASED_WAKEUP_b : 1; /*!< [27..27] Second Pulse Based wakeup */ + __IOM unsigned int MSEC_BASED_WAKEUP_b : 1; /*!< [28..28] Millisecond Pulse + Based wakeup */ + __IOM unsigned int WDT_INTR_BASED_WAKEUP_b : 1; /*!< [29..29] Millisecond + Pulse Based wakeup */ + __IOM unsigned int ULPSS_BASED_SLEEP : 1; /*!< [30..30] ULPSS initiated DeepSleep. */ + __IOM unsigned int SDCSS_BASED_SLEEP : 1; /*!< [31..31] SDCSS initiated DeepSleep. */ + } MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b; + }; + + union { + __IOM unsigned int MCU_FSM_PERI_CONFIG_REG; /*!< (@ 0x00000004) Configuration + for Ultra Low-Power Mode of the + processor + (PS2 State) */ + + struct { + __IOM unsigned int ULP_MCU_MODE_EN : 1; /*!< [0..0] Enables voltage switching + for PS2-PS4/PS3 and PS4/PS3-PS2 + state transitions. */ + __IOM unsigned int M4SS_CONTEXT_SWITCH_TOP_ULP_MODE : 2; /*!< [2..1] Enable functional + switching for PS2-PS4/PS3 and + PS4/PS3-PS2 + state transitions */ + __IOM unsigned int WICENREQ : 1; /*!< [3..3] Its enable or disable maximum of 32KB of + LP-SRAM for operation in PS2 state */ + __IOM unsigned int Reserved1 : 12; /*!< [15..4] It is recommended to write + these bits to 0. */ + __IOM unsigned int BGPMU_SAMPLING_EN_R : 1; /*!< [16..16] Controls the mode of Band-Gap + for DC-DC 1.35 during PS2 state. */ + __IOM unsigned int Reserved2 : 15; /*!< [31..17] It is recommended to write + these bits to 0. */ + } MCU_FSM_PERI_CONFIG_REG_b; + }; + + union { + __IOM unsigned int GPIO_WAKEUP_REGISTER; /*!< (@ 0x00000008) GPIO Wakeup Register */ + + struct { + __IOM unsigned int GPIO_0_WAKEUP : 1; /*!< [0..0] Enable gpio 0 based wakeup. */ + __IOM unsigned int GPIO_1_WAKEUP : 1; /*!< [1..1] Enable gpio 1 based wakeup */ + __IOM unsigned int GPIO_2_WAKEUP : 1; /*!< [2..2] Enable gpio 2 based wakeup */ + __IOM unsigned int GPIO_3_WAKEUP : 1; /*!< [3..3] Enable gpio 3 based wakeup */ + __IOM unsigned int GPIO_4_WAKEUP : 1; /*!< [4..4] Enable gpio 3 based wakeup */ + __IOM unsigned int Reserved1 : 11; /*!< [15..5] It is recommended to write + these bits to 0. */ + __IOM unsigned int CONTINIOUS_START : 1; /*!< [16..16] Trigger Deep sleep + timer to start counting. */ + __IOM unsigned int CONTINIOUS_TIMER_ENABLE : 1; /*!< [17..17] Enable Deep sleep timer + mode continuous. */ + __IOM unsigned int DS_TIMER_SOFT_RESET : 1; /*!< [18..18] Enable Deep sleep + timer mode continuous. */ + __IOM unsigned int Reserved2 : 13; /*!< [31..19] It is recommended to write + these bits to 0. */ + } GPIO_WAKEUP_REGISTER_b; + }; + + union { + __IOM unsigned int MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG; /*!< (@ 0x0000000C) MCU FSM DEEP + SLEEP DURATION LSB Register */ + + struct { + __IOM + unsigned int MCUFSM_DEEPSLEEP_DURATION_COUNT : 32; /*!< [31..0] LSB bits of + deep sleep duration + counter after which + system wakes up is + timeout wakeup is + enabled. */ + } MCU_FSM_DEEP_SLEEP_DURATION_LSB_REG_b; + }; + + union { + __IOM unsigned int MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG; /*!< (@ 0x00000010) MCU FSM XTAL + AND PMU GOOD COUNT Register */ + + struct { + __IOM unsigned int MCUFSM_PMU_POWERGOOD_DURATION_COUNT : 7; /*!< [6..0] Wait Delay for + PMU POWER GOOD 0 - 5us 1 - + 10us 2 - 12.5us + 3 - 25us 4 - 50us 5 - + 75us. */ + __IOM unsigned int Reserved1 : 9; /*!< [15..7] It is recommended to write + these bits to 0. */ + __IOM unsigned int MCUFSM_XTAL_GOODTIME_DURATION_COUNT : 7; /*!< [22..16] Wait Delay for + XTAL GOOD Time 0 - 5us 1 - + 10us. */ + __IOM unsigned int Reserved2 : 9; /*!< [31..23] It is recommended to write + these bits to 0. */ + } MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b; + }; + + union { + __IOM unsigned int MCU_FSM_POWER_CTRL_AND_DELAY; /*!< (@ 0x00000014) Power Control and + Delay Configuration for Ultra + Low-Power Mode of the + processor (PS2 State) */ + + struct { + __IOM unsigned int PS2_PMU_LDO_OFF_DELAY : 5; /*!< [4..0] PMU BUCK And LDO + Turn-OFF Delay. */ + __IOM unsigned int Reserved1 : 3; /*!< [7..5] It is recommended to write these + bits to 0. */ + __IOM unsigned int PS4_SOCLDO_ON_DELAY : 4; /*!< [11..8] PMU SOCLDO Turn-ON Delay. */ + __IOM unsigned int PG4_BUCK_ON_DELAY : 4; /*!< [15..12] PMU Buck Turn-ON Delay. */ + __IOM unsigned int FSM_PERI_SOC_LDO_EN : 1; /*!< [16..16] Enable SOCLDO in + Peri mode. */ + __IOM unsigned int FSM_PERI_DCDC_EN : 1; /*!< [17..17] Enable DCDC in Peri mode. */ + __IOM unsigned int Reserved2 : 1; /*!< [18..18] It is recommended to write + these bits to 0. */ + __IOM unsigned int POWER_MUX_SEL_ULPSS : 1; /*!< [19..19] Select value for + ULPSS(Peripherals) Power Mux */ + __IOM unsigned int POWER_MUX_SEL_M4_ULP : 2; /*!< [21..20] Select value for M4 + ULP (Peripherals + Cortex Core + )Power Mux. */ + __IOM unsigned int POWER_MUX_SEL_M4_ULP_RAM_16K : 2; /*!< [23..22] Select value for M4 + ULP RAM 16K Power Mux */ + __IOM unsigned int POWER_MUX_SEL_M4_ULP_RAM : 2; /*!< [25..24] Select value for M4 ULP + RAM Power Mux. */ + __IOM unsigned int POWER_MUX_SEL_ULPSS_RAM : 2; /*!< [27..26] Select value for + ULPSS RAM Power Mux. */ + __IOM unsigned int Reserved3 : 4; /*!< [31..28] It is recommended to write + these bits to 0. */ + } MCU_FSM_POWER_CTRL_AND_DELAY_b; + }; + + union { + __IOM unsigned int MCU_FSM_CLKS_REG; /*!< (@ 0x00000018) MCU FSM Clocks Register */ + + struct { + __IOM unsigned int Reserved1 : 2; /*!< [1..0] It is recommended to write these + bits to 0. */ + __IOM unsigned int HF_FSM_CLK_SELECT : 3; /*!< [4..2] Disable signal for m4ss + reference clock. */ + __IOM unsigned int Reserved2 : 10; /*!< [14..5] It is recommended to write + these bits to 0. */ + __IOM unsigned int HF_FSM_CLK_SWITCHED_SYNC : 1; /*!< [15..15] If high freq fsm clock + select is modified. */ + __IOM unsigned int HF_FSM_CLK_FREQ : 6; /*!< [21..16] High Frequency Source + Clock value in MHz. */ + __IOM unsigned int US_DIV_COUNT : 2; /*!< [23..22] One Micro second division factor. + Program value to + 3. If hf_fsm_gen_2mhz is 0 Program + value to 1. If hf_fsm_gen_2mhz is 1. */ + __IOM unsigned int HF_FSM_GEN_2MHZ : 1; /*!< [24..24] Enable 2Mhz clock for FSM 1 -Enable + 2Mhz option 0- Enable 4MHz option. */ + __IOM unsigned int HF_FSM_CLK_EN : 1; /*!< [25..25] high frequency mcu fsm + clock enable. */ + __IOM unsigned int Reserved3 : 6; /*!< [31..26] It is recommended to write + these bits to 0. */ + } MCU_FSM_CLKS_REG_b; + }; + + union { + __IOM unsigned int MCU_FSM_REF_CLK_REG; /*!< (@ 0x0000001C) MCU FSM Clocks Register */ + + struct { + __IOM unsigned int M4SS_REF_CLK_SEL : 3; /*!< [2..0] Dynamic Reference Clock Mux select + of M4SS 0 - Clock will be gated at dynamic + mux output of M4SS 1 - ulp_mhz_rc_byp_clk + 2 - ulp_mhz_rc_clk 3 - rf_ref_clk 4 + - mems_ref_clk 5 + - ulp_20mhz_ringosc_clk 6 - + ulp_doubler_clk 7 - ref_byp_clk to TASS. */ + __IOM unsigned int Reserved1 : 4; /*!< [6..3] It is recommended to write these + bits to 0. */ + __IOM unsigned int M4SS_REF_CLK_CLEANER_OFF_b : 1; /*!< [7..7] Disable signal for m4ss + reference clock. */ + __IOM unsigned int M4SS_REF_CLK_CLEANER_ON_b : 1; /*!< [8..8] Enable clk cleaner for m4ss + reference clock. */ + __IOM unsigned int Reserved2 : 3; /*!< [11..9] It is recommended to write + these bits to 0. */ + __IOM unsigned int TASS_REF_CLK_SEL : 3; /*!< [14..12] Dynamic Reference Clock Mux select + of TASS controlled by M4. 0 : Clock will be + gated at dynamic mux output of TASS 1 : + ulp_mhz_rc_byp_clk 2 : ulp_mhz_rc_clk 3 : + rf_ref_clk 4 : mems_ref_clk 5 : + ulp_20mhz_ringosc_clk 6 : ref_byp_clk to + TASS. */ + __IOM unsigned int Reserved3 : 1; /*!< [15..15] It is recommended to write + these bits to 0. */ + __IOM unsigned int ULPSS_REF_CLK_SEL_b : 3; /*!< [18..16] Dynamic Reference Clock Mux + select of TASS controlled by M4. 0 : Clock + will be gated at dynamic mux output of + TASS 1 : ulp_mhz_rc_byp_clk 2 : + ulp_mhz_rc_clk 3 : rf_ref_clk 4 : + mems_ref_clk 5 : ulp_20mhz_ringosc_clk 6 + : ref_byp_clk to TASS. */ + __IOM unsigned int Reserved4 : 4; /*!< [22..19] It is recommended to write + these bits to 0. */ + __IOM unsigned int ULPSS_REF_CLK_CLEANER_OFF_b : 1; /*!< [23..23] Clock cleaner Off + signal for ulpss ref clock. */ + __IOM unsigned int ULPSS_REF_CLK_CLEANER_ON_b : 1; /*!< [24..24] Clock cleaner Off signal + for ulpss ref clock. */ + __IOM unsigned int Reserved5 : 3; /*!< [27..25] It is recommended to write + these bits to 0. */ + __IOM unsigned int SDCSS_CLK_SEL_b : 2; /*!< [29..28] select between RC / RO + 32KHz clk in sdcss 01 - MHz RC + Clock 10- 20MHz RO Clock. */ + __IOM unsigned int SDCSS_CLK_EN_b : 1; /*!< [30..30] To enable dynamic clock + for sdcss */ + __IOM unsigned int SDCSS_STATIC_CLK_EN_b : 1; /*!< [31..31] To enable static clk for + sensor data collector subsystem */ + } MCU_FSM_REF_CLK_REG_b; + }; + + union { + __IOM unsigned int MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP; /*!< (@ 0x00000020) MCU FSM + And First Bootup */ + + struct { + __IOM unsigned int FIRST_BOOTUP_MCU_N_b : 1; /*!< [0..0] Indication for S/W to + distinguish b/w First Power or ULP + wakeup.S/W need to set this Bit after + first power .. */ + __IM unsigned int RAM_RETENTION_STATUS_M4SS_b : 1; /*!< [1..1] Indicates to S/W that + RAM's were in retention mode + during Sleep time. 1 - RAM are in + retention mode during sleep. 0 - + RAM are not in retention mode + during sleep.Domain is OFF.. */ + __IOM unsigned int RETENTION_DOMAIN_ON_b : 1; /*!< [2..2] Indicates to S/W that Retention + domain is ON. 1 - Domain is ON. 0 - + Domain is OFF.. */ + __IOM unsigned int CHIP_MODE_VALID_b : 1; /*!< [3..3] Indicates to S/W that ChipMode + programming are valid and need not read + EFUSE. 1 - ChipMode are Valid. 0 - ChipModes + are invalid. */ + __IOM unsigned int STORAGE_DOMAIN_ON_b : 1; /*!< [4..4] Indicates to S/W that + MCU Data Storage 1 domain is + ON. 1 - Domain is ON. 0 - + Domain is OFF.. */ +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + __IOM unsigned int Reserved1 : 10; /*!< [14..5] It is recommended to write + these bits to 0. */ +#else + __IOM unsigned int Reserved1 : 9; /*!< [13..5] It is recommended to write + these bits to 0. */ + __IOM unsigned int MCU_ULP_1KHZ_RC_CLK_EN_b : 1; /*!< [14..14] Enables ULP 1KHz Rc Clock + (For SYSRTC and MCU WWD). */ +#endif + __IOM unsigned int MCU_FSM_RESET_N_SYNC_b : 1; /*!< [15..15] Indicated MCU FSM is out of + reset. 1 : Indicated MCU + FSM is out of reset 0 : Indicated MCU + FSM is in reset. */ + __IOM unsigned int MCU_ULP_32KHZ_RC_CLK_EN_b : 1; /*!< [16..16] Enables ULP + 32KHz Rc Clock. */ + __IOM unsigned int MCU_ULP_32KHZ_RO_CLK_EN_b : 1; /*!< [17..17] Enables ULP + 32KHz RO Clock. */ + __IOM unsigned int MCU_ULP_32KHZ_XTAL_CLK_EN_b : 1; /*!< [18..18] Enables ULP + 32KHz Xtal Clock. */ + __IOM unsigned int MCU_ULP_MHZ_RC_CLK_EN_b : 1; /*!< [19..19] Enables ULP + MHz RC Clock. */ + __IOM unsigned int MCU_ULP_20MHZ_RING_OSC_CLK_EN_b : 1; /*!< [20..20] Enables ULP 20mhz + RO Clock. */ + __IOM unsigned int MCU_ULP_DOUBLER_CLK_EN_b : 1; /*!< [21..21] Enables ULP + Doubler Clock. */ + __IOM unsigned int MCU_ULP_40MHZ_CLK_EN_b : 1; /*!< [22..22] Enables 40MHz + XTAL clock. */ + __IOM unsigned int Reserved2 : 9; /*!< [31..23] It is recommended to write + these bits to 0. */ + } MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b; + }; + + union { + __IOM unsigned int MCU_FSM_CRTL_PDM_AND_ENABLES; /*!< (@ 0x00000024) Power Domains + Controlled by Sleep FSM. */ + + struct { + __IOM unsigned int ENABLE_WDT_IN_SLEEP_b : 1; /*!< [0..0] Its enable or disable WDT + during Sleep/Shutdown states. */ + __IOM unsigned int ENABLE_WURX_DETECTION_b : 1; /*!< [1..1] Its enable or disable + detection of On-Air Pattern using + Wake-Fi Rx. */ + __IOM unsigned int RESET_MCU_BBF_DM_EN_b : 1; /*!< [2..2] Its enable or disable reset of + Power Domain Control Battery FF's on + wakeup. */ + __IOM unsigned int DISABLE_TURNOFF_SRAM_PERI_b : 1; /*!< [3..3] Enable MCU SRAM periphery + during Deepsleep 1 - Enable SRAM + periphery during Deepsleep 0 - Disable + SRAM periphery during Deepsleep. */ + __IOM unsigned int ENABLE_SRAM_DS_CRTL_b : 1; /*!< [4..4] Enable signal for controlling + Deepsleep signal of all SRAM used by M4 1- + Enable SRAM Deepsleep Signal 0- Disable + SRAM Deepsleep Signal. */ + __IOM unsigned int Reserved1 : 11; /*!< [15..5] It is recommended to write + these bits to 0. */ + __IOM unsigned int POWER_ENABLE_FSM_PERI_b : 1; /*!< [16..16] Its enable or disable Power + to Low-Power FSM. */ + __IOM unsigned int POWER_ENABLE_TIMESTAMPING_b : 1; /*!< [17..17] Its enable or disable + Power to TIMESTAMP. */ + __IOM unsigned int POWER_ENABLE_DEEPSLEEP_TIMER_b : 1; /*!< [18..18] Its enable or + disable Power to DEEP SLEEP + Timer. */ + __IOM unsigned int POWER_ENABLE_RETENTION_DM_b : 1; /*!< [19..19] Its enable or disable + Power to Retention Flops during + SHIP state.These Flops + are used for storing Chip + Configuration. */ + __IOM unsigned int Reserved2 : 12; /*!< [31..20] It is recommended to write + these bits to 0. */ + } MCU_FSM_CRTL_PDM_AND_ENABLES_b; + }; + + union { + __IOM unsigned int MCU_GPIO_TIMESTAMPING_CONFIG; /*!< (@ 0x00000028) MCU GPIO + TIMESTAMPING CONFIG. */ + + struct { + __IOM unsigned int ENABLE_GPIO_TIMESTAMPING_b : 1; /*!< [0..0] Enable GPIO time stamping + Feature.. */ + __IOM unsigned int TIMESTAMPING_ON_GPIO0_b : 1; /*!< [1..1] Enable GPIO time + stamping on GPIO0. */ + __IOM unsigned int TIMESTAMPING_ON_GPIO1_b : 1; /*!< [2..2] Enable GPIO time + stamping on GPIO1. */ + __IOM unsigned int TIMESTAMPING_ON_GPIO2_b : 1; /*!< [3..3] Enable GPIO time + stamping on GPIO2. */ + __IOM unsigned int TIMESTAMPING_ON_GPIO3_b : 1; /*!< [4..4] Enable GPIO time + stamping on GPIO3. */ + __IOM unsigned int TIMESTAMPING_ON_GPIO4_b : 1; /*!< [5..5] Enable GPIO time + stamping on GPIO4. */ + __IOM unsigned int Reserved1 : 26; /*!< [31..6] It is recommended to write + these bits to 0. */ + } MCU_GPIO_TIMESTAMPING_CONFIG_b; + }; + + union { + __IM unsigned int MCU_GPIO_TIMESTAMP_READ; /*!< (@ 0x0000002C) MCU GPIO + TIMESTAMPING READ. */ + + struct { + __IM unsigned int GPIO_EVENT_COUNT_PARTIAL : 11; /*!< [10..0] Counter value indicating + the duration from GPIO going high to + first Sleep clock( MCU FSM Clock) + posedge from GPIO going high with + respect to MHz RC clock. */ + __IM unsigned int Reserved1 : 5; /*!< [15..11] It is recommended to write + these bits to 0. */ + __IM unsigned int GPIO_EVENT_COUNT_FULL : 11; /*!< [26..16] Counter value indicating + number for RC MHz clock present in 1 + Sleep clock (MCU FSM Clock). */ + __IM unsigned int Reserved2 : 5; /*!< [31..27] It is recommended to write + these bits to 0. */ + } MCU_GPIO_TIMESTAMP_READ_b; + }; + + union { + __IOM unsigned int MCU_SLEEPHOLD_REQ; /*!< (@ 0x00000030) MCU SLEEP HOLD REQ. */ + + struct { + __IOM unsigned int SLEEPHOLDREQn : 1; /*!< [0..0] Sleepholdreq when enable + will gate the clock to M4. 1 + - Sleepholdreq is Disabled. + 0 - Sleepholdreq is Enabled. */ + __IM unsigned int SLEEPHOLDACKn : 1; /*!< [1..1] SLEEPHOLDACK response to + SLEEPHOLDREQ. */ + __IOM unsigned int Reserved1 : 14; /*!< [15..2] It is recommended to write + these bits to 0. */ + __IOM unsigned int SELECT_FSM_MODE : 1; /*!< [16..16] Enable for selecting secondary FSM. + 1 - Select Secondary FSM 0 - Select Primary + FSM. */ + __IOM unsigned int Reserved2 : 15; /*!< [31..17] It is recommended to write + these bits to 0. */ + } MCU_SLEEPHOLD_REQ_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int MCU_FSM_WAKEUP_STATUS_REG; /*!< (@ 0x00000038) MCU FSM Wakeup + Status Register. */ + + struct { + __IOM unsigned int WAKEUP_STATUS : 11; /*!< [10..0] To know the wakeup source. */ + __IOM unsigned int Reserved1 : 5; /*!< [15..11] It is recommended to write + these bits to 0. */ + __IOM unsigned int MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Indication to Processor that + system came out first power up. */ + __IOM unsigned int MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Indication to Processor + that system came out of Reset. */ + __IOM unsigned int Reserve2 : 14; /*!< [31..18] It is recommended to write + these bits to 0. */ + } MCU_FSM_WAKEUP_STATUS_REG_b; + }; + + union { + __IOM unsigned int MCU_FSM_WAKEUP_STATUS_CLEAR; /*!< (@ 0x0000003C) MCU FSM + Wakeup Status Clear. */ + + struct { + __IOM unsigned int WWD_INTERRUPT_STATUS_CLEAR_b : 1; /*!< [0..0] To Clear WatchDog + Interrupt status indication. */ + __IOM unsigned int MILLI_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [1..1] To Clear Milli-Second + Wakeup status indication. */ + __IOM unsigned int RTC_SEC_BASED_STATUS_CLEAR_b : 1; /*!< [2..2] To Clear Second Tick + wakeup status indication. */ + __IOM unsigned int RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [3..3] To Clear RTC + Alarm wakeup status + indicaition. */ + __IOM unsigned int COMP1_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [4..4] To Clear comp1 + wakeup (Analog IP1 and + Analog IP2) status + indication. */ + __IOM unsigned int COMP2_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [5..5] To Clear comp2 + wakeup (Analog IP1 and + BandGap Scale) status + indication. */ + __IOM + unsigned int COMP3_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [6..6] To Clear comp3 + wakeup (Analog IP1 and + VBatt Scale) status + indication. */ + __IOM + unsigned int COMP4_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [7..7] To Clear Comp4 + wakeup (Bandgap En and + VBatt Scale) status + indication. */ + __IOM unsigned int COMP5_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [8..8] To Clear BOD Wakeup + status indication. */ + __IOM unsigned int COMP6_BASED_WAKEUP_STATUS_CLEAR_b : 1; /*!< [9..9] To Clear + Button-wake status + indication. */ +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + __IOM unsigned int RF_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear WuRX status + indication. */ +#else + __IOM unsigned int SYSRTC_WAKEUP_CLEAR_b : 1; /*!< [10..10] To Clear SYSRTC Wakeup status + indication. */ +#endif + __IOM unsigned int Reserved1 : 21; /*!< [31..11] It is recommended to write + these bits to 0. */ + } MCU_FSM_WAKEUP_STATUS_CLEAR_b; + }; + + union { + __IOM unsigned int MCU_FSM_PMU_STATUS_REG; /*!< (@ 0x00000040) MCU FSM PMU + Status Register. */ + + struct { + __IOM unsigned int SCDCDC_LP_MODE_EN : 1; /*!< [0..0] SCDC in LP mode. */ + __IOM unsigned int BGPMU_SLEEP_EN_R_b : 1; /*!< [1..1] Sleep en for BG PMU. */ + __IOM unsigned int Reserved1 : 15; /*!< [16..2] It is recommended to write + these bits to 0. */ + __IOM unsigned int STANDBY_LDORF_R : 1; /*!< [17..17] Standby state for LDO RF. */ + __IOM unsigned int STANDBY_LDOSOC_R : 1; /*!< [18..18] Standby state for LDO soc. */ + __IOM unsigned int STANDBY_DC1P3_R : 1; /*!< [19..19] Standby state for DC1p3. */ + __IM unsigned int POWERGOOD_LDOSOC : 1; /*!< [20..20] Powergood signal from ldosoc. */ + __IM unsigned int LEVEL_OK_DC1P3 : 1; /*!< [21..21] Powergood signal from LDORF. */ + __IM unsigned int CL_FLAG_DC1P3 : 1; /*!< [22..22] Powergood signal read for + DC 1.3V. */ + __IOM unsigned int Reserved2 : 9; /*!< [31..23] It is recommended to write + these bits to 0. */ + } MCU_FSM_PMU_STATUS_REG_b; + }; + + union { + __IOM unsigned int MCU_FSM_PMUX_CTRLS_RET; /*!< (@ 0x00000044) MCU FSM PMUX + Controls Retention. */ + + struct { + __IOM unsigned int POWER_SW_CTRL_TASS_RAM_IN_RETAIN : 1; /*!< [0..0] Select value for + TASS RAM Power Mux In + Retention mode */ + __IOM unsigned int POWER_SW_CTRL_M4SS_RAM_IN_RETAIN : 1; /*!< [1..1] Select value for + M4SS RAM Power Mux In + Retention mode */ + __IOM unsigned int POWER_SW_CTRL_M4ULP_RAM_IN_RETAIN : 2; /*!< [3..2] Select value for + M4ULP RAM Power Mux In + Retention mode */ + __IOM unsigned int POWER_SW_CTRL_M4ULP_RAM16K_IN_RETAIN : 2; /*!< [5..4] Select value for + M4ULP 16K RAM Power Mux + In Retention mode */ + __IOM unsigned int POWER_SW_CTRL_ULPSS_RAM_IN_RETAIN : 2; /*!< [7..6] Select value for + ULPSS RAM Power Mux In + Retention mode */ + __IOM unsigned int Reserved1 : 24; /*!< [31..8] It is recommended to write + these bits to 0. */ + } MCU_FSM_PMUX_CTRLS_RET_b; + }; + + union { + __IOM unsigned int MCU_FSM_TOGGLE_COUNT; /*!< (@ 0x00000048) MCU FSM Toggle Count. */ + + struct { + __OM unsigned int TOGGLE_COUNT_RSTART : 1; /*!< [0..0] Start counting GIPO Toggles. */ + __IOM unsigned int Reserved1 : 14; /*!< [14..1] It is recommended to write + these bits to 0. */ + __OM unsigned int LATCH_TOGGLE_DATA : 1; /*!< [15..15] Trigger indication to + read GPIO toggle data. */ + __IM unsigned int GPIO_TOGGLE_COUNT : 12; /*!< [27..16] GPIO toogle data count. */ + __IOM unsigned int Reserved2 : 3; /*!< [30..28] It is recommended to write + these bits to 0. */ + __IM unsigned int TOGGLE_DATA_READY : 1; /*!< [31..31] GPIO toogle data count. */ + } MCU_FSM_TOGGLE_COUNT_b; + }; +} MCU_FSM_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_ProcessSensor + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The process sensor module, count the process clock (high frequency + ring clock) over one MCU FSM clock and divide this clock by programmable + value. (MCU_ProcessSensor) + */ + +typedef struct { /*!< (@ 0x24048540) MCU_ProcessSensor Structure */ + + union { + __IOM unsigned int PROCESS_SENSOR_ENABLE_AND_READ; /*!< (@ 0x00000000) Process sensor + enable and read for operation */ + + struct { + __IOM unsigned int PROCESS_SENSOR_EN : 1; /*!< [0..0] enable or on the process sensor,if + this bit is set the sensor enable else + sensor is disable. */ + __IOM unsigned int PS_RING_CLK_START : 1; /*!< [1..1] Start Ring-Oscillator clock for + estimating process corner. */ + __IOM unsigned int PS_CLK_SW_ON : 1; /*!< [2..2] Clock cleaner on signal to clock cleaner + block on clock generated by delay chain. */ + __IOM unsigned int PS_CLK_SW_OFF : 1; /*!< [3..3] Clock cleaner off signal to clock + cleaner block on clock + generated by delay chain. */ + __IOM unsigned int NUM_CYCLES : 2; /*!< [5..4] Number of MCU FSM clock(32KHz)for which + measurement need to be done.if bits is 1 then 1 + clock, 2 then 2 clocks,3 then 3 clocks,4 then 4 + clocks. */ + __IM unsigned int PS_MEAS_DONE_SYNC : 1; /*!< [6..6] Processor sensor + measurement done. */ + __IOM unsigned int RESERVED1 : 9; /*!< [15..7] Reserved1 */ + __IM unsigned int PS_COUNT : 16; /*!< [31..16] Processor sensor read back */ + } PROCESS_SENSOR_ENABLE_AND_READ_b; + }; +} MCU_ProcessSensor_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_RET + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief NPSS has Retention domain logic which is a power domain . + This domain consisted all logic which will turned off if none of + the M4 memories are retained. (MCU_RET) + */ + +typedef struct { /*!< (@ 0x24048600) MCU_RET Structure */ + + union { + __IOM unsigned int MCURET_QSPI_WR_OP_DIS; /*!< (@ 0x00000000) MCURET QSPI WR OP DIS */ + + struct { + __IOM unsigned int M4SS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [0..0] M4SS Write operation + disable to Flash. 1 - Write + Operation to Flash is not + allowed. 0 - Write Operation to + Flash is allowed. */ + __IM unsigned int TASS_QSPI_WRSR_WR_OP_DISABLE : 1; /*!< [1..1] TASS Write operation + disable to Flash. 1 - Write + Operation to Flash is not + allowed. 0 - Write Operation to + Flash is allowed. */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] Reserved1 */ + } MCURET_QSPI_WR_OP_DIS_b; + }; + + union { + __IM unsigned int MCURET_BOOTSTATUS; /*!< (@ 0x00000004) MCURET BOOT Status */ + + struct { + __IM unsigned int BOOT_STATUS : 1; /*!< [0..0] Boot Status/Configuration + information to MCU */ + __IM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } MCURET_BOOTSTATUS_b; + }; + __IM unsigned int RESERVED; + + union { + __IM unsigned int CHIP_CONFIG_MCU_READ; /*!< (@ 0x0000000C) MCURET BOOT Status */ + + struct { + __IM unsigned int DISABLE_M4 : 1; /*!< [0..0] When set, disables the M4 by + clock gating and putting M4 in reset */ + __IM unsigned int LIMIT_M4_FREQ_110MHZ_b : 1; /*!< [1..1] When set, limits the M4SS SoC + clock to Max clock/2 */ + __IM unsigned int DISABLE_M4_ULP_MODE : 1; /*!< [2..2] When set, limits the M4SS SoC + clock to Max clock/2 */ + __IM unsigned int RESERVED1 : 7; /*!< [9..3] Reserved1 */ + __IM unsigned int M4_FLASH_SIZE : 3; /*!< [12..10] 0xx - Unrestricted 100 - Auto mode + accesses to flash are restricted to 4 MBit 101 - + Auto mode accesses to flash are restricted to 8 + MBit 110 - Auto mode accesses to flash are + restricted to 16 MBit 111 - Auto mode accesses + to flash are restricted to 32 MBit */ + __IM unsigned int DISABLE_FIM_COP : 1; /*!< [13..13] When set, disable FIMV */ + __IM unsigned int DISABLE_VAP : 1; /*!< [14..14] When set, disables VAD */ + __IM unsigned int DISABLE_TOUCH : 1; /*!< [15..15] When set, disables touch + interface */ + __IM unsigned int RESERVED2 : 1; /*!< [16..16] Reserved2 */ + __IM unsigned int DISABLE_ANALOG_PERIPH : 1; /*!< [17..17] When set, disables + analog peripherals */ + __IM unsigned int DISABLE_JTAG : 1; /*!< [18..18] When set, disable JTAG + interface(both M4 and NWP) */ + __IM unsigned int DISABLE_M4SS_KH_ACCESS : 1; /*!< [19..19] When set, disables + access to key in the key + holder from M4SS QSPI */ + __IM unsigned int DISABLE_M4SS_ACCESS_FRM_TASS_SEC : 1; /*!< [20..20] When set, M4 can + not access TASS memory or + registers except for host + communication registers */ + __IM unsigned int RESERVED3 : 11; /*!< [31..21] Reserved3 */ + } CHIP_CONFIG_MCU_READ_b; + }; + + union { + __IOM unsigned int MCUAON_CTRL_REG4; /*!< (@ 0x00000010) MCURET Control Register4 */ + + struct { + __IOM unsigned int RESERVED1 : 16; /*!< [15..0] Reserved1 */ + __IOM unsigned int ULP_GPIO_2_TEST_MODE_OUT_SEL : 4; /*!< [19..16] NPSS Test modes */ + __IOM unsigned int ULP_GPIO_1_TEST_MODE_OUT_SEL : 4; /*!< [23..20] NPSS Test modes */ + __IOM unsigned int ULP_GPIO_0_TEST_MODE_OUT_SEL : 4; /*!< [27..24] NPSS Test modes */ + __IOM unsigned int ULP_GPIOS_IN_TEST_MODE : 1; /*!< [28..28] NPSS Test modes */ + __IOM unsigned int RESERVED2 : 3; /*!< [31..29] Reserved2 */ + } MCUAON_CTRL_REG4_b; + }; + __IM unsigned int RESERVED1[2]; + __IOM MCU_RET_NPSS_GPIO_CNTRL_Type NPSS_GPIO_CNTRL[5]; /*!< (@ 0x0000001C) [0..4] */ +} MCU_RET_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_TEMP + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The temperature sensor is used to read the temperature by using APB + registers, which is access through direct to ULPSS system. (MCU_TEMP) + */ + +typedef struct { /*!< (@ 0x24048500) MCU_TEMP Structure */ + + union { + __IOM unsigned int TS_ENABLE_AND_TEMPERATURE_DONE; /*!< (@ 0x00000000) Temperature sensor + enable and measurement calculation + done + indication register */ + + struct { + __OM unsigned int TEMP_SENS_EN : 1; /*!< [0..0] Temperature sensing + enable,self clearing register */ + __IOM unsigned int REF_CLK_SEL : 1; /*!< [1..1] if this bit is zero then reference RO + clock from analog,else this bit is one then MCU + FSM clock */ + __IOM unsigned int CONT_COUNT_FREEZE : 10; /*!< [11..2] Count of reference clock on which + ptat clock counts */ + __IM unsigned int TEMP_MEASUREMENT_DONE : 1; /*!< [12..12] temperature measurement done + indication. */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ + } TS_ENABLE_AND_TEMPERATURE_DONE_b; + }; + + union { + __IOM unsigned int TS_SLOPE_SET; /*!< (@ 0x00000004) temperature sensor slope set(slope + will be change with respect to temperature change) */ + + struct { + __IOM unsigned int SLOPE : 10; /*!< [9..0] This is one time measurement for one package + after chip arrives from fab,this is signed bit. */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM unsigned int TEMPERATURE_SPI : 11; /*!< [26..16] temperature known */ + __OM unsigned int TEMP_UPDATED : 1; /*!< [27..27] temperature updated signal for the reg + to capture this temperature. */ + __IOM unsigned int BJT_BASED_TEMP : 1; /*!< [28..28] Temperature is updated through which + is calculated using bjt based if bit is high(1) + through spi and bit is low(0) then through + calculation RO based */ + __IOM unsigned int RESERVED2 : 3; /*!< [31..29] Reserved2 */ + } TS_SLOPE_SET_b; + }; + + union { + __IOM unsigned int TS_FE_COUNTS_NOMINAL_SETTINGS; /*!< (@ 0x00000008) determine + calibrated temperature */ + + struct { + __IOM unsigned int F2_NOMINAL : 10; /*!< [9..0] ptat clock count during calibration,This + will vary with chip to chip. */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM unsigned int NOMINAL_TEMPERATURE : 7; /*!< [22..16] calibrated temperature */ + __IOM unsigned int RESERVED2 : 9; /*!< [31..23] Reserved2 */ + } TS_FE_COUNTS_NOMINAL_SETTINGS_b; + }; + + union { + __IM unsigned int TS_COUNTS_READ; /*!< (@ 0x0000000C) temperature sensor count read. */ + + struct { + __IM unsigned int COUNT_F2 : 10; /*!< [9..0] COUNT_F2 */ + __IM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IM unsigned int COUNT_F1 : 10; /*!< [25..16] COUNT_F1 */ + __IM unsigned int RESERVED2 : 6; /*!< [31..26] Reserved2 */ + } TS_COUNTS_READ_b; + }; + + union { + __IOM unsigned int TEMPERATURE_READ; /*!< (@ 0x00000010) read the temperature */ + + struct { + __IM unsigned int TEMPERATURE_RD : 11; /*!< [10..0] Temperature value for read + in signed format */ + __IOM unsigned int RES10 : 21; /*!< [31..11] reserved10 */ + } TEMPERATURE_READ_b; + }; +} MCU_TEMP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== + */ +/* ================ MCU_AON + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief NPSS has always ON domain logic which is not power gatable Which + consistes of power, reset, isolation controls for different power domains in + NPSS. (MCU_AON) + */ + +typedef struct { /*!< (@ 0x24048000) MCU_AON Structure */ + + union { + __IOM unsigned int MCUAON_NPSS_PWRCTRL_SET_REG; /*!< (@ 0x00000000) This register used for + NPSS power control set register. */ + + struct { + __IOM unsigned int RES : 1; /*!< [0..0] bit is reserved */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery + FF's power gate enable.If + set,Power + Supply is On clearing + this bit has no effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate + enable,If set power supply is on + clearing + this bit has no effect. + */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate + enable if set,power supply is on + clearing + this bit has no effect. + */ + __IOM + unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power + gate enable if + set,power supply is on + clearing this bit has + no effect */ + __IOM + unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate + enable.if set,power supply is + on clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor + power gate enable if set,power + supply is on.clearing + this bit has no effect */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power + gate enable for 64-bit.if + set,power supply is + on,clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power + gate enable for 64-bit.if + set,power supply is + on,clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power + gate enable for 64-bit.if + set,power supply is + on,clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power + gate enable. */ + __IOM unsigned int RESERVED1 : 5; /*!< [15..11] reserved1 */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU + control power gate + enable */ + __IOM unsigned int RESERVED2 : 15; /*!< [31..17] reserved2 */ + } MCUAON_NPSS_PWRCTRL_SET_REG_b; + }; + + union { + __IOM unsigned int MCUAON_NPSS_PWRCTRL_CLEAR_REG; /*!< (@ 0x00000004) This register used + for NPSS power control clear + register. */ + + struct { + __IOM unsigned int RES : 1; /*!< [0..0] bit is reserved */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUBFFS : 1; /*!< [1..1] MCU domain battery + FF's power gate enable.If + set,Power Supply is OFF + clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUFSM : 1; /*!< [2..2] MCU FSM power gate + enable,If set power supply is + OFF clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCURTC : 1; /*!< [3..3] MCU RTC power gate + enable if set,power supply is + OFF clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUWDT : 1; /*!< [4..4] MCU WDT power gate + enable if set,power supply is + OFF clearing this bit has no + effect */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUPS : 1; /*!< [5..5] MCU PS power gate + enable.if set,power supply is OFF + clearing + this bit has no effect. + */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUTS : 1; /*!< [6..6] MCU temperature sensor + power gate enable if set,power + supply is OFF.clearing + this bit has no effect */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE1 : 1; /*!< [7..7] MCU Storage 1 power + gate enable for 64-bit.if + set,power supply is + OFF,clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE2 : 1; /*!< [8..8] MCU Storage 2 power + gate enable for 64-bit.if + set,power supply is + OFF,clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_MCUSTORE3 : 1; /*!< [9..9] MCU Storage 3 power + gate enable for 64-bit.if + set,power supply is + OFF,clearing this bit has no + effect. */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_TIMEPERIOD : 1; /*!< [10..10] TIMEPERIOD power + gate enable. */ + __IOM unsigned int RESERVED1 : 5; /*!< [15..11] reserved1 */ + __IOM unsigned int SLPSS_PWRGATE_EN_N_ULP_NWPAPB_MCU_CTRL : 1; /*!< [16..16] NWPAPB MCU + control power gate + enable */ + __IOM unsigned int RESERVED2 : 15; /*!< [31..17] reserved2 */ + } MCUAON_NPSS_PWRCTRL_CLEAR_REG_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int MCUAON_IPMU_RESET_CTRL; /*!< (@ 0x0000000C) This register used for ipmu + reset control register */ + + struct { + __IOM unsigned int ULP_ANALOG_SPI_RESET_N : 1; /*!< [0..0] ULP Analog SPI Reset Signal, + if bit is 1 then outoff reset,else in + reset */ + __IOM unsigned int IPMU_SPI_RESET_N : 1; /*!< [1..1] IPMU SPI Reset Signal,if bit is 1 + then outoff reset,else in reset */ + __IOM unsigned int RESERVED1 : 30; /*!< [31..2] reserved1 */ + } MCUAON_IPMU_RESET_CTRL_b; + }; + + union { + __IOM unsigned int MCUAON_SHELF_MODE; /*!< (@ 0x00000010) This register used for + control shelf mode. */ + + struct { + __OM unsigned int ENTER_SHELF_MODE : 16; /*!< [15..0] Program 0xAAAA for + entering shelf mode. */ + __IOM unsigned int SHUTDOWN_WAKEUP_MODE : 2; /*!< [17..16] GPIO based wakeup + mode configuration. */ + __IOM unsigned int SHELF_MODE_GPIOBASED : 1; /*!< [18..18] GPIO based shelf mode + entering,If set 1 by processor, On + Falling edge of GPIO (Based on the option + used in shutdown_wakeup_mode register) + chip will enter Shelf mode. */ + __IOM unsigned int SHELF_MODE_WAKEUP_DELAY : 3; /*!< [21..19] Programmable delay for + resetting Chip during exit phase of + shelf mode. */ + __IOM unsigned int RESERVED1 : 10; /*!< [31..22] reserved1 */ + } MCUAON_SHELF_MODE_b; + }; + + union { + __IOM unsigned int MCUAON_GEN_CTRLS; /*!< (@ 0x00000014) This register used for + MCUON gen control mode. */ + + struct { + __IOM unsigned int XTAL_CLK_FROM_GPIO : 1; /*!< [0..0] Select external 32KHz clock from + NPSS GPIO's,if bit is 1 then select XTAL + clock from GPIO Pins. Please refer to NPSS + GPIO Pin muxing for configuration.else + select XTAL clock from IPMU clock sources. + */ + __IOM unsigned int ULP_ANALOG_WAKEUP_ACCESS : 1; /*!< [1..1] ULP analog wakeup Source + Access,if bit is 1 then TASS + else bit is 0 then M4SS. */ + __IOM unsigned int RES : 14; /*!< [15..2] reser */ + __IOM unsigned int ENABLE_PDO : 1; /*!< [16..16] Enable turning Off POD power + domain when SOC_LDO EN is low,When Set + to 1, Up on SoC LDO Enable going low, IO + supply (3.3v)to SOC Pads + will be tuned-off. */ + __IOM unsigned int NPSS_SUPPLY_0P9 : 1; /*!< [17..17] keep npss supply always at 0.9V,if + bit is 1 then npss supply always at 0.9V else + bit is zero then npss supply will switch from + 0.6V to 0.9V based on high frequency + enables. */ + __IOM unsigned int RESERVED1 : 14; /*!< [31..18] reser */ + } MCUAON_GEN_CTRLS_b; + }; + + union { + __IOM unsigned int MCUAON_PDO_CTRLS; /*!< (@ 0x00000018) This register used for + MCUON PDO control mode. */ + + struct { + __IOM + unsigned int SOC_B_IO_DOMAIN_EN_B : 1; /*!< [0..0] Turn-Off IO supply of SOC + domain on bottom side,if bit is 1 + then turn-off and 0 then turn on */ + __IOM unsigned int SOC_L_IO_DOMAIN_EN_B : 1; /*!< [1..1] Turn-Off IO supply of SOC domain + on left side,if bit is 1 then turn-off + and 0 then turn on */ + __IOM unsigned int SOC_T_IO_DOMAIN_EN_B : 1; /*!< [2..2] Turn-Off IO supply of SOC domain + on top side,if bit is 1 then turn-off + and 0 then turn on */ + __IOM unsigned int QSPI_IO_DOMAIN_EN_B : 1; /*!< [3..3] Turn-Off IO supply of QSPI + domain,if bit is 1 then turn-off and 0 + then turn on */ + __IOM unsigned int SDIO_IO_DOMAIN_EN_B : 1; /*!< [4..4] Turn-Off IO supply of SDIO + domain.,if bit is 1 then turn-off and 0 + then turn on */ + __IOM unsigned int RES : 27; /*!< [31..5] reser */ + } MCUAON_PDO_CTRLS_b; + }; + + union { + __IOM unsigned int MCUAON_WDT_CHIP_RST; /*!< (@ 0x0000001C) This register used + for wdt chip reset purpose. */ + + struct { + __IOM unsigned int MCU_WDT_BASED_CHIP_RESET : 1; /*!< [0..0] When cleared, Up on host + reset request.Power-On Reset (POR) + will be generated */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] reserved1 */ + } MCUAON_WDT_CHIP_RST_b; + }; + + union { + __IOM unsigned int MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS; /*!< (@ 0x00000020) This register + used for khz clock select and + reset status */ + + struct { + __IOM unsigned int AON_KHZ_CLK_SEL : 3; /*!< [2..0] NPSS AON KHz clock selection,if 001 + Khz RO clock select,else + if 010 - Khz RC clock select,else 100 + Khz Xtal clock select */ + __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED : 1; /*!< [3..3] If Khz clock mux + select is modified,please poll + this bit and wait till it + becomes one. */ + +#if defined(SLI_SI917B0) || defined(SLI_SI915) + __IOM unsigned int AON_KHZ_CLK_SEL_WWD : 4; /* [4 .. 7] NPSS AON KHz clock + selection for WWD */ + __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED_WWD : 1; /*!< [8..8] If Khz clock mux + select is modified for + wwd,please poll this bit + and wait till it becomes + one. */ + __IOM unsigned int AON_KHZ_CLK_SEL_SYSRTC : 4; /* [9 .. 12] NPSS AON KHz clock + selection for SYSRTC */ + __IM unsigned int AON_KHZ_CLK_SEL_CLOCK_SWITCHED_SYSRTC : 1; /*!< [13..13] If Khz clock + mux select is modified + for sysrtc,please poll + this + bit and + wait till it becomes + one. */ + __IOM unsigned int RES : 2; /*!< [14..15] reserved */ +#else + __IOM unsigned int RES : 12; /*!< [15..4] reser */ +#endif + + __IOM unsigned int MCU_FIRST_POWERUP_POR : 1; /*!< [16..16] Program this bit to '1' upon + power_up.It will be clear when Vbatt + power is removed */ + __IOM unsigned int MCU_FIRST_POWERUP_RESET_N : 1; /*!< [17..17] Program this bit to '1' + upon power_up,It will be clear + when reset pin is pulled + low. */ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + __IOM unsigned int SYSRTC_32KHZ_RC_CLK_DIV_FACTOR : 6; /* [18..23] Clock division factor + for 32Khz_rc_clk (Used in + SYSRTC and MCU WWD) */ + __IOM unsigned int RESERVED1 : 8; /*!< [24..31] reserved1 */ +#else + __IOM unsigned int RESERVED1 : 14; /*!< [31..18] reserved1 */ +#endif + } MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b; + }; +} MCU_AON_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== + */ +/* ================ ULPCLK + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief This block provides programming support for miscellaneous blocks in + the chip. Various features in the chip are enabled using this. (ULPCLK) + */ + +typedef struct { /*!< (@ 0x24041400) ULPCLK Structure */ + + union { + __IOM unsigned int ULP_MISC_SOFT_SET_REG; /*!< (@ 0x00000000) ULP MISC soft + register set. */ + + struct { + __IOM unsigned int PCM_ENABLE_b : 1; /*!< [0..0] Used in pcm */ + __IOM unsigned int PCM_FSYNC_START_b : 1; /*!< [1..1] Used in pcm */ + __IOM unsigned int BIT_RES : 2; /*!< [3..2] Used in pcm */ + __IOM unsigned int IR_PCLK_EN_b : 1; /*!< [4..4] Static clock enable for IR + APB Interface */ + __IOM unsigned int PCLK_ENABLE_I2C_b : 1; /*!< [5..5] This bit is used as Static enable + for APB clock to I2C module,if bit is zero + then clock is disabled else bit is + one then clock is enabled. */ + __IOM unsigned int CLK_ENABLE_I2S_b : 1; /*!< [6..6] This bit is used to enable clock to + I2S module if bit is set(1)then clock is + enabled is bit is zero then clock disabled. + */ + __IOM unsigned int PCLK_ENABLE_SSI_MASTER_b : 1; /*!< [7..7] This bit is used to enable + APB bus clock to SSI master,if bit is + zero clock will be available only + when the request from the module is + present.else bit is one then clock + is enabled. */ + __IOM unsigned int SCLK_ENABLE_SSI_MASTER_b : 1; /*!< [8..8] This bit is used to enable + clock serial clock to SSI master,if + bit is zero clock will be available + only when the request from the module + is present.else bit is one + then clock is enabled. */ + __IOM unsigned int PCLK_ENABLE_UART_b : 1; /*!< [9..9] This bit is used to enable + peripheral bus clock to UART4,if bit zero + then clock will be available only when the + request from the module is present or a + transaction is pending + on the APB bus,else bit is one then + clock is enabled. */ + __IOM unsigned int SCLK_ENABLE_UART_b : 1; /*!< [10..10] This bit is used to enable + asynchronous serial clock to UART4,if bit + is zero clock will be available only when + the request from the module is + present.else bit is one then clock is + enabled. */ + __IOM unsigned int FIM_PCLK_ENABLE_b : 1; /*!< [11..11] This bit is used to enable clock + to FIM reg file,if this bit is zero then + clock will be available only when the + request from the module is present else bit + is set(1)then clock is enabled. */ + __IOM unsigned int VAD_PCLK_ENABLE_b : 1; /*!< [12..12] This bit is used to enable clock + to FIM reg file,if this bit is zero then + clock will be available only when the + request from the module is present else bit + is set(1)then clock is enabled. */ + __IOM unsigned int CLK_ENABLE_TIMER_b : 1; /*!< [13..13] This bit is used to enable clock + to Timer,if this bit is zero then clock + will be available only when the request + from the module is present else bit + is set(1)then clock is enabled. */ + __IOM unsigned int EGPIO_CLK_EN_b : 1; /*!< [14..14] This bit is used to enable clock to + gpio,if this bit is zero then clock will be + available only when the request from the module + is present else bit is set(1)then clock is + enabled. */ + __IOM unsigned int REG_ACCESS_SPI_CLK_EN_b : 1; /*!< [15..15] This bit is used to enable + clock to register access spi,if this + bit is zero then clock will be + available only when the request from + the module is present else bit is + set(1)then clock is enabled. */ + __IOM unsigned int FIM_CLK_EN_b : 1; /*!< [16..16] This bit is used to enable clock to + FIM module,if this bit is zero then clock will be + gated,else bit is one then clock is enabled. */ + __IOM unsigned int VAD_CLK_EN_b : 1; /*!< [17..17] This bit is used to enable clock to + vad module,if this bit is zero then clock will be + gated,else bit is one then clock is enabled. */ + __IOM unsigned int CLK_ENABLE_ULP_MEMORIES_b : 1; /*!< [18..18] This bit is used to + enable clock to memories,if this bit + is zero then clock will be available + only when the request from the module + is present else bit is set(1)then + clock is enabled. */ + __IOM unsigned int EGPIO_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] This bit is used to + disable dynamic clock gating on + APB clock to egpio */ + __IOM unsigned int EGPIO_PCLK_ENABLE_b : 1; /*!< [20..20] This bit is used to enable + static clock to egpio APB interface */ + __IOM unsigned int TIMER_PCLK_EN_b : 1; /*!< [21..21] This bit is used to enable static + clock to Timer APB Interface */ + __IOM unsigned int AUX_ULP_EXT_TRIG_1_SEL_b : 1; /*!< [22..22] aux adc dac controller + external trigger2 mux select, to + choose between ulp gpio aux ext + trigger2 and timer interrupt. */ + __IOM unsigned int AUX_ULP_EXT_TRIG_2_SEL_b : 1; /*!< [23..23] aux adc dac controller + external trigger2 mux select, to + choose between ulp gpio aux ext + trigger2 and timer interrupt. */ + __IOM unsigned int AUX_SOC_EXT_TRIG_1_SEL_b : 1; /*!< [24..24] aux adc dac controller + external trigger3 mux select, to + choose between soc aux ext + trigger1and soc aux ext trigger3. */ + __IOM unsigned int AUX_SOC_EXT_TRIG_2_SEL_b : 1; /*!< [25..25] aux adc dac controller + external trigger4 mux select, to + choose between soc aux ext trigger2and + soc aux ext trigger4. */ + __IOM unsigned int ULPSS_M4SS_SLV_SEL_b : 1; /*!< [26..26] select slave */ + __IOM unsigned int ULPSS_TASS_QUASI_SYNC_b : 1; /*!< [27..27] TASS quasi sync */ + __IOM unsigned int RESERVED1 : 2; /*!< [29..28] reserved1 */ + __IOM unsigned int FIM_AHB_CLK_ENABLE_b : 1; /*!< [30..30] static clock enable + for FIM AHB interface */ + __IOM unsigned int TOUCH_SENSOR_PCLK_ENABLE_b : 1; /*!< [31..31] Static clock enable for + touch APB interface */ + } ULP_MISC_SOFT_SET_REG_b; + }; + + union { + __IOM unsigned int ULP_TA_PERI_ISO_REG; /*!< (@ 0x00000004) ULP NWP isolation register. */ + + struct { + __IOM unsigned int UDMA_ISO_CNTRL_b : 1; /*!< [0..0] UDMA module isolation enable,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int IR_ISO_CNTRL_b : 1; /*!< [1..1] IR module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int I2C_ISO_CNTRL_b : 1; /*!< [2..2] I2C module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int I2S_ISO_CNTRL_b : 1; /*!< [3..3] I2S module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int SSI_ISO_CNTRL_b : 1; /*!< [4..4] SSI module isolation enable ,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int UART_ISO_CNTRL_b : 1; /*!< [5..5] UART module isolation enable,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int AUX_A2D_ISO_CNTRL_b : 1; /*!< [6..6] AUX a2d module isolation + enable,if bit is set(1) then enable else + bit is zero then disable. */ + __IOM unsigned int VAD_ISO_CNTRL_b : 1; /*!< [7..7] VAD module isolation enable,if bit is + set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int TOUCH_ISO_CNTRL_b : 1; /*!< [8..8] CAP sensor module isolation + enable,if bit is set(1) then + enable else bit is zero then disable. */ + __IOM unsigned int PROC_MISC_ISO_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, + interrupt cntrl, Timer) module isolation + enable ,if bit is set(1) then enable + else bit is zero then disable. */ + __IOM unsigned int RESERVED0 : 1; /*!< [10..10] reserved0 */ + __IOM unsigned int RESERVED1 : 1; /*!< [11..11] reserved1 */ + __IOM unsigned int RESERVED2 : 1; /*!< [12..12] reserved2 */ + __IOM unsigned int RESERVED3 : 1; /*!< [13..13] reserved3 */ + __IOM unsigned int FIM_ISO_CNTRL_b : 1; /*!< [14..14] FIM module isolation enable ,if bit + is set(1) then enable else bit is zero then + disable. */ + __IOM unsigned int MEM_2K_1_ISO_CNTRL_b : 1; /*!< [15..15] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM unsigned int MEM_2K_2_ISO_CNTRL_b : 1; /*!< [16..16] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM unsigned int MEM_2K_3_ISO_CNTRL_b : 1; /*!< [17..17] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM unsigned int MEM_2K_4_ISO_CNTRL_b : 1; /*!< [18..18] 2k SRAM memory isolation + enable ,if bit is set(1) then + enable else bit is zero then disable. + */ + __IOM unsigned int RESERVED4 : 13; /*!< [31..19] reserved4 */ + } ULP_TA_PERI_ISO_REG_b; + }; + + union { + __IOM unsigned int ULP_TA_PERI_RESET_REG; /*!< (@ 0x00000008) ULP NWP peri reset + register. */ + + struct { + __IOM unsigned int UDMA_SOFT_RESET_CNTRL_b : 1; /*!< [0..0] UDMA module soft reset + enable,if bit is set(1) then out of + soft reset else bit is zero then in + reset. */ + __IOM unsigned int IR_SOFT_RESET_CNTRL_b : 1; /*!< [1..1] IR module soft reset enable,if + bit is set(1) then out of soft reset + else bit is zero then in reset. */ + __IOM unsigned int I2C_SOFT_RESET_CNTRL_b : 1; /*!< [2..2] I2C module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM unsigned int I2S_SOFT_RESET_CNTRL_b : 1; /*!< [3..3] I2S module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM unsigned int SSI_SOFT_RESET_CNTRL_b : 1; /*!< [4..4] SSI module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM unsigned int UART_SOFT_RESET_CNTRL_b : 1; /*!< [5..5] UART module soft reset enable + ,if bit is set(1) then out of soft + reset else bit is zero then in reset. + */ + __IOM unsigned int AUX_A2D_SOFT_RESET_CNTRL_b : 1; /*!< [6..6] AUX a2d module soft reset + enable,if bit is set(1) then out of + soft reset else bit is zero then in + reset. */ + __IOM unsigned int VAD_SOFT_RESET_CNTRL_b : 1; /*!< [7..7] VAD module soft reset + enable,if bit is set(1) then out of soft + reset else bit is zero then in reset. */ + __IOM unsigned int TOUCH_SOFT_RESET_CNTRL_b : 1; /*!< [8..8] CAP Sensor module soft reset + enable,if bit is set(1) + then out of soft reset else bit is zero + then in reset. */ + __IOM unsigned int PROC_MISC_SOFT_RESET_CNTRL_b : 1; /*!< [9..9] mis top(TOT, semaphore, + interrupt control, Timer) module + soft reset enable,if bit is + set(1) then out of soft reset + else bit is zero then in reset + */ + __IOM unsigned int COMP1_OUTPUT_CNTRL_b : 1; /*!< [10..10] This is ULP comparator1 + interrupt unmasking signal. 0 means + comparator1 interrupt is masked and 1 + means unmasking. + It is masked at power-on time. */ + __IOM unsigned int COMP2_OUTPUT_CNTRL_b : 1; /*!< [11..11] This is ULP comparator2 + interrupt unmasking signal. 0 means + comparator2 interrupt is masked and 1 + means unmasking. + It is masked at power-on time. */ + __IOM unsigned int RESERVED1 : 2; /*!< [13..12] reserved1 */ + __IOM unsigned int FIM_SOFT_RESET_CNTRL_b : 1; /*!< [14..14] FIM module soft reset + enable,if bit is set(1) then out of + soft reset else bit is zero then in + reset */ + __IOM unsigned int RESERVED2 : 17; /*!< [31..15] reserved2 */ + } ULP_TA_PERI_RESET_REG_b; + }; + __IM unsigned int RESERVED[2]; + + union { + __IOM unsigned int ULP_TA_CLK_GEN_REG; /*!< (@ 0x00000014) ULP NWP clock + generation register. */ + + struct { + __IOM unsigned int ULP2M4_A2A_BRDG_CLK_EN_b : 1; /*!< [0..0] Clock enable for ULP-M4SS + AHB-AHB bridge,if bit is set(1) + then enable else bit is + zero then in disable */ + __IOM unsigned int ULP_PROC_CLK_SEL : 4; /*!< [4..1] ulp bus clock select. */ + __IOM unsigned int ULP_PROC_CLK_DIV_FACTOR : 8; /*!< [12..5] ulp bus clock + division factor */ + __IOM unsigned int RES : 19; /*!< [31..13] reserved1 */ + } ULP_TA_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int ULP_I2C_SSI_CLK_GEN_REG; /*!< (@ 0x00000018) ULP I2C SSI + clock generation register. */ + + struct { + __IOM unsigned int ULP_I2C_CLK_EN_b : 1; /*!< [0..0] ulp i2c clock enable,if bit is + set(1) then enable else bit is zero then in + disable */ + __IOM unsigned int RESERVED1 : 4; /*!< [4..1] reserved1 */ + __IOM unsigned int RESERVED2 : 8; /*!< [12..5] reserved2 */ + __IOM unsigned int RESERVED3 : 3; /*!< [15..13] reserved3 */ + __IOM unsigned int ULP_SSI_CLK_EN_b : 1; /*!< [16..16] ssi clk enable if set(1) then + enable else bit is zero then disable */ + __IOM unsigned int ULP_SSI_CLK_DIV_FACTOR : 7; /*!< [23..17] ssi clk enable if + set(1) then enable else bit + is zero then disable */ + __IOM unsigned int RESERVED4 : 4; /*!< [27..24] reserved4 */ + __IOM unsigned int ULP_SSI_CLK_SEL : 4; /*!< [31..28] Ulp ssi clock select. */ + } ULP_I2C_SSI_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int ULP_I2S_CLK_GEN_REG; /*!< (@ 0x0000001C) ULP I2S clock + generation register. */ + + struct { + __IOM unsigned int ULP_I2S_CLK_EN_b : 1; /*!< [0..0] ulp i2s clk enable,if bit is set(1) + then enable else + bit is zero then in disable */ + __IOM unsigned int ULP_I2S_CLK_SEL_b : 4; /*!< [4..1] ulp i2s clock select. */ + __IOM unsigned int ULP_I2S_CLKDIV_FACTOR : 8; /*!< [12..5] ulp i2s clock + division factor. */ + __IOM unsigned int ULP_I2S_MASTER_SLAVE_MODE_b : 1; /*!< [13..13] i2s master slave mode + decide field. */ + __IOM unsigned int ULP_I2S_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Disable dynamic + clock gating of System clock + in I2S */ + __IOM unsigned int RESERVED1 : 1; /*!< [15..15] reserved1 */ + __IOM unsigned int ULP_I2S_LOOP_BACK_MODE_b : 1; /*!< [16..16] Enables loop + back mode in I2S. */ + __IOM unsigned int ULP_I2S_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [17..17] Disable dynamic + clock gating of APB clock in + I2S */ + __IOM unsigned int ULP_I2S_PCLK_EN_b : 1; /*!< [18..18] Static clock enable + for APB clock in I2S */ + __IOM unsigned int RESERVED2 : 13; /*!< [31..19] reserved2 */ + } ULP_I2S_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int ULP_UART_CLK_GEN_REG; /*!< (@ 0x00000020) ulp uart clock + generation register. */ + + struct { + __IOM unsigned int ULP_UART_FRAC_CLK_SEL_b : 1; /*!< [0..0] ulp uart clk selection,if bit + is set(1) then fractional divider + output is selected else swallow + divider output is selected */ + __IOM unsigned int ULP_UART_CLK_SEL : 4; /*!< [4..1] ulp uart clock select. */ + __IOM unsigned int ULP_UART_CLKDIV_FACTOR : 3; /*!< [7..5] ulp uart clock + division factor */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] reserved1 */ + } ULP_UART_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int M4LP_CTRL_REG; /*!< (@ 0x00000024) m4 ulp control register */ + + struct { + __IOM unsigned int RESERVED0 : 2; /*!< [1..0] reserved0 */ + __IOM unsigned int ULP_M4_CORE_CLK_ENABLE_b : 1; /*!< [2..2] Static clock + enable m4 core in ULP + mode,if bit is set(1) + then clock enable else + clock is disable */ + __IOM unsigned int ULP_MEM_CLK_ULP_ENABLE_b : 1; /*!< [3..3] Static clock enable for M4 + memories in ULP mode,if bit + is set(1) then clock enable else + dynamic control */ + __IOM unsigned int ULP_MEM_CLK_ULP_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Disable the + dynamic clock gating for M4 + memories in ULP mode,if bit + is set(1) then dynamic + control disabled else + dynamic control enabled. + */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ + } M4LP_CTRL_REG_b; + }; + + union { + __IOM unsigned int CLOCK_STAUS_REG; /*!< (@ 0x00000028) read clock status register */ + + struct { + __IM unsigned int CLOCK_SWITCHED_UART_CLK_b : 1; /*!< [0..0] status of clock mux for + uart,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM unsigned int CLOCK_SWITCHED_I2S_CLK_b : 1; /*!< [1..1] Status of clock mux for + i2s,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM unsigned int CLOCK_SWITCHED_CORTEX_SLEEP_CLK_b : 1; /*!< [2..2] Status of clock mux + for m4 sleep clk,if bit is + set(1) then clock is + switched,else bit is zero + then clock not switched. */ + __IM unsigned int CLOCK_SWITCHED_PROC_CLK_b : 1; /*!< [3..3] Status of clock mux for + pclk,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM unsigned int CLOCK_SWITCHED_I2C_b : 1; /*!< [4..4] Status of clock mux for i2c,if + bit is set(1) then clock + is switched,else bit is zero then clock + not switched. */ + __IM unsigned int CLOCK_SWITCHED_SSI_b : 1; /*!< [5..5] Status of clock mux for ssi,if + bit is set(1) then clock + is switched,else bit is zero then clock + not switched. */ + __IM unsigned int CLOCK_SWITCHED_VAD_b : 1; /*!< [6..6] Status of clock mux for vad,if + bit is set(1) then clock + is switched,else bit is zero then clock + not switched. */ + __IM unsigned int CLOCK_SWITCHED_AUXADC_b : 1; /*!< [7..7] Status of clock mux for aux + adc dac clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IM unsigned int CLOCK_SWITCHED_TIMER_b : 1; /*!< [8..8] Status of clock mux for async + timers,if bit is set(1) then clock is + switched,else bit is zero then clock + not switched. */ + __IM unsigned int CLOCK_SWITCHED_TOUCH_SENSOR_b : 1; /*!< [9..9] Status of clock mux for + touch sensor,if bit is set(1) + then clock is + switched,else bit is zero then + clock not switched. */ + __IM unsigned int CLOCK_SWITCHED_FCLK_VAD_b : 1; /*!< [10..10] Status of clock mux for + vad fast clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IM unsigned int CLOCK_SWITCHED_SCLK_VAD_b : 1; /*!< [11..11] Status of clock mux for + vad slow clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IM unsigned int CLOCK_SWITCHED_SYSTICK_b : 1; /*!< [12..12] Status of clock mux for + systick clock,if bit is set(1) then + clock is switched,else bit is zero + then clock not switched. */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ + } CLOCK_STAUS_REG_b; + }; + + union { + __IOM unsigned int ULP_TOUCH_CLK_GEN_REG; /*!< (@ 0x0000002C) ULP touch clock + generation register */ + + struct { + __IOM unsigned int ULP_TOUCH_CLK_EN_b : 1; /*!< [0..0] ulp touch clk enable,if bit is + set(1) then enable,else bit is zero then + disable. */ + __IOM unsigned int ULP_TOUCH_CLK_SEL : 4; /*!< [4..1] ulp touch clock select. */ + __IOM unsigned int ULP_TOUCH_CLKDIV_FACTOR : 8; /*!< [12..5] ulp touch clock + division factor. */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ + } ULP_TOUCH_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int ULP_TIMER_CLK_GEN_REG; /*!< (@ 0x00000030) ULP clock + generation for timer */ + + struct { + __IOM unsigned int RESERVED1 : 1; /*!< [0..0] reserved1 */ + __IOM unsigned int ULP_TIMER_CLK_SEL : 4; /*!< [4..1] ulp timer clock select. */ + __IOM unsigned int RESERVED2 : 8; /*!< [12..5] reserved2 */ + __IOM unsigned int ULP_TIMER_IN_SYNC_b : 1; /*!< [13..13] Ulp timer in synchronous mode + to ULPSS pclk */ + __IOM unsigned int RESERVED3 : 18; /*!< [31..14] reserved3 */ + } ULP_TIMER_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int ULP_AUXADC_CLK_GEN_REG; /*!< (@ 0x00000034) ULP AUX clock + generation register */ + + struct { + __IOM unsigned int ULP_AUX_CLK_EN_b : 1; /*!< [0..0] ulp aux clk enable,if bit is one + then clock enable else + bit is zero then clock disable. */ + __IOM unsigned int ULP_AUX_CLK_SEL : 4; /*!< [4..1] ulp aux clock select. */ + __IOM unsigned int RESERVED1 : 27; /*!< [31..5] reserved1 */ + } ULP_AUXADC_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int ULP_VAD_CLK_GEN_REG; /*!< (@ 0x00000038) ULP vad clock + generation register */ + + struct { + __IOM unsigned int ULP_VAD_CLK_EN_b : 1; /*!< [0..0] ulp vad clk enable ,if bit is one + then clock enable else + bit is zero then clock disable. */ + __IOM unsigned int ULP_VAD_CLK_SEL : 3; /*!< [3..1] ulp vad clock select. */ + __IOM unsigned int ULP_VAD_FCLK_EN : 1; /*!< [4..4] Enables Fast clock to VAD. */ + __IOM unsigned int ULP_VAD_FCLK_SEL : 4; /*!< [8..5] ulp vad Fast clock select. */ + __IOM unsigned int ULP_VAD_CLKDIV_FACTOR : 8; /*!< [16..9] ulp vad clock + division factor */ + __IOM unsigned int RESERVED1 : 15; /*!< [31..17] reserved1 */ + } ULP_VAD_CLK_GEN_REG_b; + }; + + union { + __IOM unsigned int BYPASS_I2S_CLK_REG; /*!< (@ 0x0000003C) bypass i2s clock register */ + + struct { + __IOM unsigned int BYPASS_I2S_PLL_SEL : 1; /*!< [0..0] Bypass_I2S PLL clock,if + bit is one bypass clock is used + else bit is zero then I2S + Clock is used. */ + __IOM unsigned int BYPASS_I2S_PLL_CLK_CLN_ON : 1; /*!< [1..1] I2S PLL Bypass + clock cleaner ON */ + __IOM unsigned int BYPASS_I2S_PLL_CLK_CLN_OFF : 1; /*!< [2..2] I2S PLL Bypass + clock cleaner OFF */ + __IOM unsigned int RESERVED3 : 29; /*!< [31..3] reserved3 */ + } BYPASS_I2S_CLK_REG_b; + }; + __IM unsigned int RESERVED1; + + union { + __IOM unsigned int ULP_RM_RME_REG; /*!< (@ 0x00000044) ulp rm rem register */ + + struct { + __IOM unsigned int ULP_MEM_RME_b : 1; /*!< [0..0] RM enable signal for memories internal + tp peripherals. This needs to be programmed when + the peripheral memories are not active. */ + __IOM unsigned int ULP_MEM_RM : 2; /*!< [2..1] RM ports for memories internal to + peripheral. This needs to be programmed when the + peripheral memories are not active. */ + __IM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int ULP_MEM_RME_SRAM_b : 1; /*!< [4..4] RM enable signal for + sram memories. This needs to be + programmed when the SRAM is + not active. */ + __IOM unsigned int ULP_MEM_RM_SRAM : 2; /*!< [6..5] RM ports for sram memories. This + needs to be programmed when the SRAM is not + active */ + __IOM unsigned int RESERVED2 : 25; /*!< [31..7] reserved2 */ + } ULP_RM_RME_REG_b; + }; + + union { + __IOM unsigned int ULP_CLK_ENABLE_REG; /*!< (@ 0x00000048) ulp clock enable register. */ + + struct { + __IOM unsigned int ULP_32KHZ_RO_CLK_EN_PROG_b : 1; /*!< [0..0] Static Clock enable to + iPMU for 32KHz RO Clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM unsigned int ULP_32KHZ_RC_CLK_EN_PROG_b : 1; /*!< [1..1] Static Clock enable to + iPMU for 32KHz RC Clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM unsigned int ULP_32KHZ_XTAL_CLK_EN_PROG_b : 1; /*!< [2..2] Static Clock enable to + iPMU for 32KHz XTAL Clock,if bit + is one(set) then clock enable else + not enable. */ + __IOM unsigned int ULP_DOUBLER_CLK_EN_PROG_b : 1; /*!< [3..3] Static Clock + enable to iPMU for Doubler + Clock,if bit is one(set) + then clock enable else not + enable. */ + __IOM unsigned int ULP_20MHZ_RO_CLK_EN_PROG_b : 1; /*!< [4..4] Static Clock enable to + iPMU for 20MHz RO clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM unsigned int ULP_MHZ_RC_CLK_EN_PROG_b : 1; /*!< [5..5] Static Clock enable to + iPMU for MHz RC Clock,if bit is + one(set) then clock enable else not + enable. */ + __IOM unsigned int SOC_CLK_EN_PROG_b : 1; /*!< [6..6] Static Clock enable to iPMU for + PLL-500 Clock,if bit is one(set) then clock + enable else not enable. */ + __IOM unsigned int I2S_PLLCLK_EN_PROG_b : 1; /*!< [7..7] Static clock enable + to iPMU for I2S-PLL Clock,if bit + is one(set) then clock enable + else not enable. */ + __IOM unsigned int REF_CLK_EN_IPS_PROG_b : 1; /*!< [8..8] Static Clock enable to iPMU for + REF Clock,if bit is one(set) + then clock enable else not + enable. */ + __IOM unsigned int RESERVED1 : 23; /*!< [31..9] reserved1 */ + } ULP_CLK_ENABLE_REG_b; + }; + __IM unsigned int RESERVED2; + + union { + __IOM unsigned int SYSTICK_CLK_GEN_REG; /*!< (@ 0x00000050) sys tick clock + generation register. */ + + struct { + __IOM unsigned int SYSTICK_CLK_EN_b : 1; /*!< [0..0] sys tick clock enable ,if bit is + one(set) then clock enable else not enable. + */ + __IOM unsigned int SYSTICK_CLK_SEL : 4; /*!< [4..1] sys tick clock select */ + __IOM unsigned int SYSTICK_CLKDIV_FACTOR : 8; /*!< [12..5] sys tick clock + division factor */ + __IOM unsigned int RESERVED1 : 19; /*!< [31..13] reserved1 */ + } SYSTICK_CLK_GEN_REG_b; + }; + __IM unsigned int RESERVED3[3]; + __IOM ULPCLK_ULP_SOC_GPIO_MODE_REG_Type ULP_SOC_GPIO_MODE_REG[16]; /*!< (@ 0x00000060) [0..15] */ + + union { + __IOM unsigned int ULP_DYN_CLK_CTRL_DISABLE; /*!< (@ 0x000000A0) this register used for ULP + dynamic clock control disable. */ + + struct { + __IOM unsigned int I2C_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [0..0] Dynamic clock control + disable for APB interface in i2c + module,if bit is one(set) then + dynamic control disabled + else bit is zero then Dynamic control + enabled. */ + __IOM unsigned int I2S_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [1..1] Dynamic clock control + disable for i2s module,if bit is + one(set) then dynamic control + disabled else bit is zero + then Dynamic control enabled. */ + __IOM unsigned int SSI_MST_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [2..2] Dynamic clock control + disable for pclk ssi module,if + bit is one(set) then + dynamic control disabled else + bit is zero then Dynamic + control enabled. */ + __IOM unsigned int SSI_MST_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [3..3] Dynamic clock control + disable for ssi module,if bit + is one(set) then dynamic + control disabled else bit is + zero then Dynamic control + enabled. */ + __IOM unsigned int UART_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [4..4] Dynamic clock control + disable for pclk uart module ,if + bit is one(set) then + dynamic control disabled else bit + is zero then Dynamic + control enabled. */ + __IOM unsigned int UART_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [5..5] Dynamic clock + control disable for uart + module,if bit is one(set) + then dynamic control + disabled else bit is zero + then Dynamic control + enabled. */ + __IOM unsigned int TIMER_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [6..6] Dynamic clock control + disable for timer pclk module,if + bit is one(set) then + dynamic control disabled else + bit + is zero then Dynamic + control enabled. */ + __IOM unsigned int TIMER_SCLK_DYN_CTRL_DISABLE_b : 1; /*!< [7..7] Dynamic clock control + disable for timer sclk module,if + bit is one(set) then + dynamic control disabled else + bit + is zero then Dynamic + control enabled. */ + __IOM unsigned int REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [8..8] Dynamic clock + control disable for reg + access spi module,if bit + is one(set) then dynamic + control disabled else bit + is zero then Dynamic + control enabled. */ + __IOM unsigned int FIM_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [9..9] Dynamic clock control + disable for fim module,if bit is + one(set) then dynamic control + disabled else bit is zero + then Dynamic control enabled. */ + __IOM unsigned int VAD_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [10..10] Dynamic clock + control disable for vad + module,if bit is one(set) + then dynamic control + disabled else bit is zero + then Dynamic control + enabled. */ + __IOM unsigned int AUX_PCLK_EN_b : 1; /*!< [11..11] Static Enable for Aux adc pclk. */ + __IOM unsigned int AUX_CLK_EN_b : 1; /*!< [12..12] Static Enable for Aux adc clk. */ + __IOM unsigned int AUX_MEM_EN_b : 1; /*!< [13..13] Static Enable for Aux adc mem. */ + __IOM unsigned int AUX_PCLK_DYN_CTRL_DISABLE_b : 1; /*!< [14..14] Dynamic clock control + disable for aux adc module,if bit is + one(set) then dynamic control + disabled else bit + is zero then Dynamic control enabled. + */ + __IOM unsigned int AUX_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [15..15] Dynamic clock control + disable for aux adc module,if bit is + one(set) then dynamic control disabled + else bit is zero then Dynamic control + enabled. */ + __IOM unsigned int AUX_CLK_MEM_DYN_CTRL_DISABLE_b : 1; /*!< [16..16] Dynamic clock + control disable for aux adc + mem,if bit is one(set) then + dynamic control disabled else + bit is zero then Dynamic + control enabled. */ + __IOM unsigned int UDMA_CLK_ENABLE_b : 1; /*!< [17..17] Static Enable for UDMA. */ + __IOM unsigned int IR_CLK_ENABLE_b : 1; /*!< [18..18] Static Enable for IR. */ + __IOM + unsigned int IR_CLK_DYN_CTRL_DISABLE_b : 1; /*!< [19..19] Dynamic clock control + disable for ir module ,if bit is + one(set) then dynamic control + disabled else bit is zero then + Dynamic control enabled. */ + __IOM unsigned int RESERVED1 : 12; /*!< [31..20] reserved1 */ + } ULP_DYN_CLK_CTRL_DISABLE_b; + }; + + union { + __IOM unsigned int SLP_SENSOR_CLK_REG; /*!< (@ 0x000000A4) this register used + for SLP sensor clock register. */ + + struct { + __IOM unsigned int DIVISON_FACTOR : 8; /*!< [7..0] Division factor for apb interface + clock to sleep sensor subsystem. */ + __IOM unsigned int ENABLE_b : 1; /*!< [8..8] Enable for APB clock to SLPSS */ + __IOM unsigned int RESERVED1 : 23; /*!< [31..9] reserved1 */ + } SLP_SENSOR_CLK_REG_b; + }; +} ULPCLK_Type; /*!< Size = 168 (0xa8) */ + +/* =========================================================================================================================== + */ +/* ================ FIM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief FIM support fixed point Multiplications implemented through + * programmable shifting. (FIM) + */ + +typedef struct { /*!< (@ 0x24070000) FIM Structure */ + + union { + __IOM unsigned int FIM_MODE_INTERRUPT; /*!< (@ 0x00000000) Configuration for FIM Operation + Mode and Interrupt Control */ + + struct { + __IOM unsigned int LATCH_MODE : 1; /*!< [0..0] Enable latch mode */ + __IOM unsigned int OPER_MODE : 8; /*!< [8..1] Indicates the Mode of Operation + to be performed. */ + __IM unsigned int RESERVED1 : 1; /*!< [9..9] reserved1 */ + __OM unsigned int INTR_CLEAR : 1; /*!< [10..10] Writing 1 to this bit clears + the interrupt */ + __IM unsigned int RESERVED2 : 21; /*!< [31..11] reserved2 */ + } FIM_MODE_INTERRUPT_b; + }; + + union { + __IOM unsigned int FIM_INP1_ADDR; /*!< (@ 0x00000004) This register used for COP + input address for 0 register. */ + + struct { + __IOM unsigned int INP1_ADDR : 32; /*!< [31..0] Indicates the Start Address of + 1st Input Data for FIM Operations */ + } FIM_INP1_ADDR_b; + }; + + union { + __IOM unsigned int FIM_INP2_ADDR; /*!< (@ 0x00000008) This register used for COP + input address for 1 register */ + + struct { + __IOM unsigned int INP2_ADDR : 32; /*!< [31..0] Indicates the Start Address of + 2nd Input Data for FIM Operations */ + } FIM_INP2_ADDR_b; + }; + + union { + __IOM unsigned int FIM_OUT_ADDR; /*!< (@ 0x0000000C) Memory Offset Address for + Output from FIM Operations */ + + struct { + __IOM unsigned int OUT_ADDR : 32; /*!< [31..0] Indicates the Start Address of + Output Data for FIM Operations */ + } FIM_OUT_ADDR_b; + }; + + union { + __IOM unsigned int FIM_SCALAR_POLE_DATA1; /*!< (@ 0x00000010) Indicates the Input Scalar + Data for Scalar Operations indicates the + feedback coefficient for IIR Operations */ + + struct { + __IOM unsigned int SCALAR_POLE_DATA1 : 32; /*!< [31..0] Pole 0/Scalar Value */ + } FIM_SCALAR_POLE_DATA1_b; + }; + + union { + __IOM unsigned int FIM_POLE_DATA2; /*!< (@ 0x00000014) Feedback coefficient for + IIR filter operation */ + + struct { + __IOM unsigned int POLE_DATA2 : 32; /*!< [31..0] Indicates the feedback + coefficient for IIR Operations */ + } FIM_POLE_DATA2_b; + }; + + union { + __IOM unsigned int FIM_SAT_SHIFT; /*!< (@ 0x00000018) Configuration for precision of Output + Data for FIM Operations */ + + struct { + __IOM unsigned int SAT_VAL : 5; /*!< [4..0] Indicates the number of MSB's to + be saturated for Output Data */ + __IOM unsigned int TRUNCATE : 5; /*!< [9..5] Truncate */ + __IOM unsigned int SHIFT_VAL : 6; /*!< [15..10] Indicates the number of bits + to be right-shifted for Output Data */ + __IOM unsigned int ROUND : 2; /*!< [17..16] Round */ + __IOM unsigned int SAT_EN : 1; /*!< [18..18] Saturation enable bit */ + __IM unsigned int RESERVED2 : 13; /*!< [31..19] reserved2 */ + } FIM_SAT_SHIFT_b; + }; + + union { + __IOM unsigned int FIM_CONFIG_REG1; /*!< (@ 0x0000001C) Configuration Register + for FIM Operations. */ + + struct { + __IOM unsigned int MAT_LEN : 6; /*!< [5..0] Indicates the number of columns in 1st input + for Matrix Multiplication. This is same as number of + rows in 2nd input for Matrix Multiplication. */ + __IOM unsigned int INP1_LEN : 10; /*!< [15..6] Indicates the length of 1st input for FIM + Operations other than filtering (FIR, IIR) and + Interpolation */ + __IOM unsigned int INP2_LEN : 10; /*!< [25..16] Indicates the length of 2nd input for FIM + Operations other than filtering (FIR, IIR) and + Interpolation. */ + __IOM unsigned int DECIM_FAC : 6; /*!< [31..26] Decimation Factor */ + } FIM_CONFIG_REG1_b; + }; + + union { + __IOM unsigned int FIM_CONFIG_REG2; /*!< (@ 0x00000020) Configuration Register + for FIM Operations */ + + struct { + __OM unsigned int START_OPER : 1; /*!< [0..0] Start trigger for the FIM operations,this + is reset upon write register */ + __IOM unsigned int INSTR_BUFF_ENABLE : 1; /*!< [1..1] Instruction buffer enable */ + __IM unsigned int RES : 6; /*!< [7..2] reserved5 */ + __IOM unsigned int CPLX_FLAG : 2; /*!< [9..8] Complex Flag,not valid in matrix mode */ + __IOM unsigned int COL_M2 : 6; /*!< [15..10] Indicates the number of columns + in 2nd input for Matrix Multiplication */ + __IOM unsigned int ROW_M1 : 6; /*!< [21..16] Indicates the number of rows in + 1st input for Matrix Multiplication */ + __IOM unsigned int INTRP_FAC : 6; /*!< [27..22] Indicates the Interpolation Factor */ + __IM unsigned int RESERVED1 : 4; /*!< [31..28] reserved1 */ + } FIM_CONFIG_REG2_b; + }; +} FIM_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== + */ +/* ================ NWP_FSM + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief NWP FSM one register Structure (NWP_FSM) + */ + +typedef struct { /*!< (@ 0x41300110) NWP_FSM Structure */ + + union { + __IOM unsigned int TASS_REF_CLOCK_SELECT; /*!< (@ 0x00000000) TASS REF CLOCK SELECT */ + + struct { + __IOM unsigned int M4SS_REF_CLK_SEL_NWP : 3; /*!< [2..0] M4SS REF CLK SEL NWP */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] reserved1 */ + __IOM unsigned int ULPSS_REF_CLK_SEL_NWP : 3; /*!< [6..4] ULPSS REF CLK SEL NWP */ + __IOM unsigned int RESERVED2 : 9; /*!< [15..7] reserved2 */ + __IOM unsigned int TASS_REF_CLK_SEL_NWP : 3; /*!< [18..16] TASS REF CLK SEL NWP */ + __IOM unsigned int RESERVED3 : 3; /*!< [21..19] reserved3 */ + __IOM unsigned int TASS_REF_CLK_CLEANER_OFF_NWP : 1; /*!< [22..22] TASS REF CLK CLEANER + OFF NWP */ + __IOM unsigned int TASS_REF_CLK_CLEANER_ON_NWP : 1; /*!< [23..23] TASS REF CLK + CLEANER ON NWP */ + __IOM unsigned int RESERVED4 : 8; /*!< [31..24] reserved4 */ + } TASS_REF_CLOCK_SELECT_b; + }; +} NWP_FSM_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== + */ +/* ================ OPAMP + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The opamps top consists of 3 general purpose Operational Amplifiers + * (OPAMP) offering rail-to-rail inputs and outputs (OPAMP) + */ + +typedef struct { /*!< (@ 0x24043A14) OPAMP Structure */ + + union { + __IOM unsigned int OPAMP_1; /*!< (@ 0x00000000) Programs opamp1 */ + + struct { + __IOM unsigned int OPAMP1_ENABLE : 1; /*!< [0..0] To enable opamp 1 */ + __IOM unsigned int OPAMP1_LP_MODE : 1; /*!< [1..1] Enable or disable low power mode */ + __IOM unsigned int OPAMP1_R1_SEL : 2; /*!< [3..2] Programmability to select + resister bank R1 */ + __IOM unsigned int OPAMP1_R2_SEL : 3; /*!< [6..4] Programmability to select + resister bank R2 */ + __IOM unsigned int OPAMP1_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + enable 0 for disable */ + __IOM unsigned int OPAMP1_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + registor bank */ + __IOM unsigned int OPAMP1_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out + or vdd i.e 0-out and 1-vdd */ + __IOM unsigned int OPAMP1_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ + __IOM unsigned int OPAMP1_INN_SEL : 3; /*!< [15..13] selecting -ve input of opamp */ + __IOM unsigned int OPAMP1_INP_SEL : 4; /*!< [19..16] selecting +ve input of opamp */ + __IOM unsigned int OPAMP1_OUT_MUX_SEL : 1; /*!< [20..20] to connect opamp1 + output to pad */ + __IOM unsigned int MEMS_RES_BANK_EN : 1; /*!< [21..21] enables mems res bank */ + __IOM unsigned int VREF_MUX_EN : 4; /*!< [25..22] vref mux enable */ + __IOM unsigned int MUX_EN : 1; /*!< [26..26] Mux Enable */ + __IOM unsigned int VREF_MUX_SEL : 4; /*!< [30..27] vref mux enable */ + __IOM unsigned int OPAMP1_DYN_EN : 1; /*!< [31..31] dynamic enable for opamp1 */ + } OPAMP_1_b; + }; + + union { + __IOM unsigned int OPAMP_2; /*!< (@ 0x00000004) Programs opamp2 */ + + struct { + __IOM unsigned int OPAMP2_ENABLE : 1; /*!< [0..0] enables the opamp2 */ + __IOM unsigned int OPAMP2_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode + and 1-low power mode */ + __IOM unsigned int OPAMP2_R1_SEL : 2; /*!< [3..2] Programmability to select + resister bank R1 */ + __IOM unsigned int OPAMP2_R2_SEL : 3; /*!< [6..4] Programmability to select + resister bank R2 */ + __IOM unsigned int OPAMP2_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + enable 0 for disable */ + __IOM unsigned int OPAMP2_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + registor bank */ + __IOM unsigned int OPAMP2_RES_TO_OUT_VDD : 2; /*!< [12..11] connect resistor bank to out + or vdd or gnd or DAC i.e + 0-out and 1-vdd 2-DAC 3-gnd */ + __IOM unsigned int OPAMP2_OUT_MUX_EN : 1; /*!< [13..13] out mux enable */ + __IOM unsigned int OPAMP2_INN_SEL : 2; /*!< [15..14] selecting -ve input of opamp */ + __IOM unsigned int OPAMP2_INP_SEL : 3; /*!< [18..16] selecting +ve input of opamp2 */ + __IOM unsigned int OPAMP2_DYN_EN : 1; /*!< [19..19] dynamic enable for opamp2 */ + __IOM unsigned int RESERVED1 : 12; /*!< [31..20] res */ + } OPAMP_2_b; + }; + + union { + __IOM unsigned int OPAMP_3; /*!< (@ 0x00000008) Programs opamp3 */ + + struct { + __IOM unsigned int OPAMP3_ENABLE : 1; /*!< [0..0] enables the opamp3 1 for + enable 0 for disable */ + __IOM unsigned int OPAMP3_LP_MODE : 1; /*!< [1..1] select the power mode 0-normal mode + and 1-low power mode */ + __IOM unsigned int OPAMP3_R1_SEL : 2; /*!< [3..2] Programmability to select + resister bank R1 */ + __IOM unsigned int OPAMP3_R2_SEL : 3; /*!< [6..4] Programmability to select + resister bank R2 */ + __IOM unsigned int OPAMP3_EN_RES_BANK : 1; /*!< [7..7] enables the resistor bank 1 for + enable 0 for disable */ + __IOM unsigned int OPAMP3_RES_MUX_SEL : 3; /*!< [10..8] selecting input for + registor bank */ + __IOM unsigned int OPAMP3_RES_TO_OUT_VDD : 1; /*!< [11..11] connect resistor bank to out + or vdd i.e 0-out and 1-vdd */ + __IOM unsigned int OPAMP3_OUT_MUX_EN : 1; /*!< [12..12] out mux enable */ + __IOM unsigned int OPAMP3_INN_SEL : 2; /*!< [14..13] selecting -ve input of opamp */ + __IOM unsigned int OPAMP3_INP_SEL : 3; /*!< [17..15] selecting +ve input of opamp */ + __IOM unsigned int OPAMP3_DYN_EN : 1; /*!< [18..18] dynamic enable for opamp2 */ + __IOM unsigned int RESERVED1 : 13; /*!< [31..19] res */ + } OPAMP_3_b; + }; +} OPAMP_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== + */ +/* ================ AUX_ADC_DAC_COMP + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The ADC-DAC Controller works on a ADC with a resolution of 12bits at + 5Mega sample per second when ADC reference Voltage is greater than 2.8v or + 5Mega sample per second when ADC reference Voltage is less than 2.8v. + (AUX_ADC_DAC_COMP) + */ + +typedef struct { /*!< (@ 0x24043800) AUX_ADC_DAC_COMP Structure */ + + union { + __IOM unsigned int AUXDAC_CTRL_1; /*!< (@ 0x00000000) Control register1 for DAC */ + + struct { + __IOM unsigned int ENDAC_FIFO_CONFIG : 1; /*!< [0..0] This bit activates the + DAC path in Aux ADC-DAC + controller. Data samples will be + played on DAC only when this bit + is set. */ + __IOM unsigned int DAC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select + non-FIFO mode in DAC. */ + __IOM unsigned int DAC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush + the DAC FIFO. */ + __IOM unsigned int DAC_FIFO_THRESHOLD : 3; /*!< [5..3] These bits control the DAC FIFO + threshold. When used by DMA, this will act + as almost full threshold. For NWP, it acts + as almost empty threshold */ + __IOM unsigned int DAC_ENABLE_F : 1; /*!< [6..6] This bit is used to enable + AUX DAC controller ,valid only when + DAC enable is happpen */ + __IOM unsigned int DAC_WORD_MODE : 1; /*!< [7..7] This bit is used to select + the data size valid on the APB */ + __IOM unsigned int AUX_DAC_MAC_MUX_SEL : 1; /*!< [8..8] It is recommended to + write these bits to 0 */ + + __IOM unsigned int DAC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [12..9] It is recommended to write + these bits to 0 */ + + __IOM unsigned int DAC_FIFO_AFULL_THRESHOLD : 4; /*!< [16..13] It is recommended to write + these bits to 0 */ + + __IOM unsigned int RESERVED1 : 15; /*!< [31..9] Reserved1 */ + } AUXDAC_CTRL_1_b; + }; + + union { + __IOM unsigned int AUXADC_CTRL_1; /*!< (@ 0x00000004) Control register1 for ADC */ + + struct { + __IOM unsigned int ADC_ENABLE : 1; /*!< [0..0] This bits activates the ADC + path in Aux ADC-DAC controller. */ + __IOM unsigned int ADC_STATIC_MODE : 1; /*!< [1..1] This bit is used to select + non-FIFO mode in ADC. */ + __IOM unsigned int ADC_FIFO_FLUSH : 1; /*!< [2..2] This bit is used to flush + the ADC FIFO */ + __IOM unsigned int RESERVED1 : 3; /*!< [5..3] RESERVED1 */ + __IOM unsigned int ADC_MULTIPLE_CHAN_ACTIVE : 1; /*!< [6..6] This bit is used to control + the auxadc sel signal going + to the Aux ADC. */ + __IOM unsigned int ADC_CH_SEL_MSB : 2; /*!< [8..7] It is recommended to write + these bits to 0 */ + __IOM unsigned int BYPASS_NOISE_AVG : 1; /*!< [9..9] ADC in Bypass noise avg mode. */ + __IOM unsigned int EN_ADC_CLK : 1; /*!< [10..10] Enable AUX ADC Divider output clock */ + __IOM unsigned int ENDIFF : 1; /*!< [11..11] Control to the Aux ADC */ + __IOM unsigned int ADC_CH_SEL_LS : 2; /*!< [13..12] Aux ADC channel number from which the + data has to be sampled This is valid only when + adc multiple channel active is zero. When + channel number is greater than three, upper bits + should also be programmed ADC CHANNEL SELECT MS + to bits in this register */ + __IOM unsigned int ADC_WORD_MODE : 1; /*!< [14..14] This bit is used to select the read + data size valid on the APB */ + __IOM unsigned int AUX_ADC_MAC_MUX_SEK : 1; /*!< [15..15] When set, AUX-ADC control is + handed over to Aux ADC-ADC controller. By + default, AUX-ADC is under the control of + baseband. */ + __IOM + unsigned int OVERRUN_DMA : 1; /*!< [16..16] overrun bit in dma mode to + enable the over-writing of buffer from + beginning when buffer is full. */ + __IOM unsigned int RESERVED2 : 4; /*!< [20..17] Reserved2 */ + __IOM unsigned int ADC_WAKE_UP_TIME : 5; /*!< [25..21] overrun bit in dma mode to enable + the over-writing of buffer from beginning + when buffer is wake up time (number + of clock cycles) , dependant upon AUX + ADC latency. */ + __IOM unsigned int EN_ADC_TRUN_OFF : 1; /*!< [26..26] Enable power save mode to turn off + AUX ADC when sampling clock is idle and enable + it before sampling event, programmed by + adc_wake_up_time */ + __IOM unsigned int ADC_NUM_PHASE : 1; /*!< [27..27] ADC number of phase */ + __IOM unsigned int RESERVED3 : 4; /*!< [31..28] Reserved3 */ + } AUXADC_CTRL_1_b; + }; + + union { + __IOM unsigned int AUXDAC_CLK_DIV_FAC; /*!< (@ 0x00000008) DAC clock division register */ + + struct { + __IOM unsigned int DAC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the + DAC clock division factor */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved1 */ + } AUXDAC_CLK_DIV_FAC_b; + }; + + union { + __IOM unsigned int AUXADC_CLK_DIV_FAC; /*!< (@ 0x0000000C) ADC clock division register */ + + struct { + __IOM unsigned int ADC_CLK_DIV_FAC : 10; /*!< [9..0] These bits control the + Total-Duration of the ADC clock */ + __IOM unsigned int RESERVED1 : 6; /*!< [15..10] Reserved1 */ + __IOM unsigned int ADC_CLK_ON_DUR : 9; /*!< [24..16] These bits control the + On-Duration of the ADC clock */ + __IOM unsigned int RESERVED2 : 7; /*!< [31..25] Reserved2 */ + } AUXADC_CLK_DIV_FAC_b; + }; + + union { + __IOM unsigned int AUXDAC_DATA_REG; /*!< (@ 0x00000010) Writing to this register will fill + DAC FIFO for streaming Data to DAC */ + + struct { + __IOM unsigned int AUXDAC_DATA : 10; /*!< [9..0] Writing to this register will fill DAC + FIFO for streaming Data to DAC */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved1 */ + } AUXDAC_DATA_REG_b; + }; + + union { + __IOM unsigned int AUXADC_DATA; /*!< (@ 0x00000014) AUXADC Data Read through Register. */ + + struct { + __IM unsigned int AUXADC_DATA : 12; /*!< [11..0] AUXADC Data Read through Register */ + __IM unsigned int AUXADC_CH_ID : 4; /*!< [15..12] AUXADC Channel ID */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } AUXADC_DATA_b; + }; + + union { + __IOM unsigned int ADC_DET_THR_CTRL_0; /*!< (@ 0x00000018) ADC detection + threshold control 0 */ + + struct { + __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_0 : 8; /*!< [7..0] The value against + which the ADC output has to be + compared is to be programmed + in this register */ + __IOM unsigned int COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller + raises an interrupt to processor when the + Aux ADC output falls below the programmed + Aux ADC detection threshold. */ + __IOM + unsigned int COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC + controller raises an interrupt to + processor when the Aux ADC output is + greater than the programmed Aux ADC + detection threshold.. */ + __IOM unsigned int COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises + an interrupt to processor when the Aux ADC output + is equal to the programmed Aux ADC detection + threshold */ + __IOM unsigned int RANGE_COMPARISON_ENABLE : 1; /*!< [11..11] When set, Aux ADC-DAC + controller raises an interrupt to + processor when the Aux ADC output + falls within the range specified in + AUX ADC Detection threshold0 and AUX + ADC Detection threshold1 */ + __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_1 : 4; /*!< [15..12] Carries upper four + bits of ADC detection + threshold */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } ADC_DET_THR_CTRL_0_b; + }; + + union { + __IOM unsigned int ADC_DET_THR_CTRL_1; /*!< (@ 0x0000001C) ADC detection + threshold control 1 */ + + struct { + __IOM unsigned int ADC_INPUT_DETECTION_THRESHOLD_2 : 8; /*!< [7..0] The value against + which the ADC output has to be + compared is to be programmed + in this register. */ + __IOM unsigned int COMP_LESS_THAN_EN : 1; /*!< [8..8] When set, Aux ADC-DAC controller + raises an interrupt to NWP when the Aux ADC + output falls below the programmed Aux ADC + detection threshold. */ + __IOM unsigned int COMP_GRTR_THAN_EN : 1; /*!< [9..9] When set, Aux ADC-DAC controller + raises an interrupt to NWP when the Aux ADC + output is greater than the programmed Aux + ADC detection threshold. */ + __IOM unsigned int COMP_EQ_EN : 1; /*!< [10..10] When set, Aux ADC-DAC controller raises + an interrupt to NWP when the Aux ADC output is + equal to the programmed Aux ADC detection + threshold. */ + __IOM unsigned int ADC_DETECTION_THRESHOLD_4_UPPER_BITS : 4; /*!< [14..11] Upper 4 bits + of ADC detection + threshold 2 for ADC */ + __IOM unsigned int RESERVED1 : 17; /*!< [31..15] Reserved1 */ + } ADC_DET_THR_CTRL_1_b; + }; + + union { + __IOM unsigned int INTR_CLEAR_REG; /*!< (@ 0x00000020) ADC detection threshold + control 1 */ + + struct { + __IOM unsigned int CLR_INTR : 1; /*!< [0..0] This bit is used to clear + threshold detection interrupt */ + __IOM unsigned int RESERVED1 : 7; /*!< [7..1] Reserved1 */ + __IOM unsigned int INTR_CLEAR_REG : 16; /*!< [23..8] If enabled, corresponding + first_mem_switch_intr bits + will be cleared. */ + __IOM unsigned int RESERVED2 : 8; /*!< [31..24] Reserved2 */ + } INTR_CLEAR_REG_b; + }; + + union { + __IOM unsigned int INTR_MASK_REG; /*!< (@ 0x00000024) Mask interrupt register */ + + struct { + __IOM unsigned int THRESHOLD_DETECTION_INTR_EN : 1; /*!< [0..0] When Cleared, threshold + detection interrupt will be + unmasked */ + __IOM unsigned int DAC_FIFO_EMPTY_INTR_MASK : 1; /*!< [1..1] When Cleared, dac_FIFO_empty + interrupt will be unmasked */ + __IOM unsigned int DAC_FIFO_AEMPTY_INTR_MASK : 1; /*!< [2..2] When Cleared, adc FIFO full + interrupt will be unmasked */ + __IOM unsigned int ADC_FIFO_FULL_INTR_MASK : 1; /*!< [3..3] When Cleared, adc FIFO full + interrupt will be unmasked */ + __IOM unsigned int ADC_FIFO_AFULL_INTR_MASK : 1; /*!< [4..4] When Cleared, adc FIFO afull + interrupt will be unmasked */ + __IOM unsigned int ADC_FIFO_OVERFLOW_INTR_MASK : 1; /*!< [5..5] When Cleared, dac FIFO + underrun interrupt will be + unmasked */ + __IOM unsigned int DAC_FIFO_UNDERRUN_INTR_MASK : 1; /*!< [6..6] When Cleared, dac FIFO + underrun interrupt will be + unmasked */ + __IOM unsigned int FIRST_MEM_SWITCH_INTR_MASK : 16; /*!< [22..7] When Cleared, + first_mem_switch_intr + will be unmasked */ + __IOM unsigned int ADC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [23..23] When Cleared, adc + static_mode_data_intr will be + unmasked */ + __IOM unsigned int DAC_STATIC_MODE_DATA_INTR_MASK : 1; /*!< [24..24] When Cleared, dac + static_mode_data_intr will be + unmasked */ + __IOM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } INTR_MASK_REG_b; + }; + + union { + __IM unsigned int INTR_STATUS_REG; /*!< (@ 0x00000028) Status interrupt register */ + + struct { + __IM unsigned int ADC_THRESHOLD_DETECTION_INTR : 1; /*!< [0..0] This bit is set when ADC + threshold matches with the + programmed conditions This will + be be cleared as soon as this + interrupt is acknowledged by + processor */ + __IM unsigned int DAC_FIFO_EMPTY : 1; /*!< [1..1] Set when DAC FIFO is empty. This bit + gets cleared when the DAC FIFO at least a + single sample is available in DAC FIFO */ + __IM unsigned int DAC_FIFO_AEMPTY : 1; /*!< [2..2] Set when the FIFO occupancy grater + than or equal to DAC FIFO threshold. */ + __IM unsigned int ADC_FIFO_FULL : 1; /*!< [3..3] Set when ADC FIFO is full,This bit gets + cleared when data is read from the FIFO */ + __IM unsigned int ADC_FIFO_AFULL : 1; /*!< [4..4] Set when ADC FIFO occupancy less than + or equal to ADC FIFO threshold */ + __IM unsigned int ADC_FIFO_OVERFLOW : 1; /*!< [5..5] Set when a write attempt is made to + ADC FIFO when the FIFO is already full */ + __IM unsigned int DAC_FIFO_UNDERRUN : 1; /*!< [6..6] Set when a read is done on DAC FIFO + when the FIFO is empty */ + __IM unsigned int FIRST_MEM_SWITCH_INTR : 16; /*!< [22..7] Interrupt + indicating the first memory + has been filled and the DMA + write is being shifted to + second memory chunk for + ping-pong operation */ + __IM unsigned int ADC_STATIC_MODE_DATA_INTR : 1; /*!< [23..23] Set when a proper data + packet is ready to read in static + mode for ADC */ + __IM unsigned int DAC_STATIC_MODE_DATA_INTR : 1; /*!< [24..24] Set when a proper data + packet is ready to read in static + mode for DAC */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } INTR_STATUS_REG_b; + }; + + union { + __IM unsigned int INTR_MASKED_STATUS_REG; /*!< (@ 0x0000002C) Interrupt masked + status register */ + + struct { + __IM unsigned int ADC_THRESHOLD_DETECTION_INTR_MASKED : 1; /*!< [0..0] Masked Interrupt. + This bit is set when ADC + threshold matches with + the programmed conditions + */ + __IM unsigned int DAC_FIFO_EMPTY_MASKED : 1; /*!< [1..1] Masked Interrupt.Set + when DAC FIFO is empty */ + __IM unsigned int DAC_FIFO_AEMPTY_MASKED : 1; /*!< [2..2] Masked Interrupt. Set when the + FIFO occupancy less than equal to DAC + FIFO threshold. */ + __IM unsigned int ADC_FIFO_FULL_MASKED : 1; /*!< [3..3] Masked Interrupt. Set + when ADC FIFO is full. */ + __IM unsigned int ADC_FIFO_AFULL_MASKED : 1; /*!< [4..4] Masked Interrupt. Set when ADC + FIFO occupancy greater than ADC FIFO + threshold */ + __IM unsigned int ADC_FIFO_OVERFLOW_MASKED : 1; /*!< [5..5] Masked Interrupt. Set when a + write attempt is made to ADC FIFO + when the FIFO is already full. */ + __IM unsigned int DAC_FIFO_UNDERRUN_MASKED : 1; /*!< [6..6] Masked Interrupt. Set when a + read is done on DAC FIFO when the + FIFO is empty. */ + __IM unsigned int FIRST_MEM_SWITCH_INTR_MASKED : 16; /*!< [22..7] Masked Interrupt + status indicating the first memory + has been filled and the DMA write is + being shifted to + second memory chunk for ping-pong + operation */ + __IM unsigned int ADC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [23..23] Masked Interrupt. + Set when a proper data packet + is ready to read in static + mode for ADC */ + __IM unsigned int DAC_STATIC_MODE_DATA_INTR_MASKED : 1; /*!< [24..24] Masked Interrupt. + Set when a proper data packet + is ready to read in static + mode for DAC */ + __IM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } INTR_MASKED_STATUS_REG_b; + }; + + union { + __IM unsigned int FIFO_STATUS_REG; /*!< (@ 0x00000030) Interrupt masked status + register */ + + struct { + __IM unsigned int DAC_FIFO_FULL : 1; /*!< [0..0] Set when DAC FIFO is full. In + word mode, FIFO will be shown as full + unless there is space for 16-bits. */ + __IM unsigned int DAC_FIFO_AFULL : 1; /*!< [1..1] Set when DAC FIFO occupancy + greater than FIFO threshold */ + __IM unsigned int ADC_FIFO_EMPTY : 1; /*!< [2..2] Set when FIFO is empty. This bit gets + cleared when the ADC FIFO is not empty. */ + __IM unsigned int ADC_FIFO_AEMPTY : 1; /*!< [3..3] Set when the FIFO occupancy + less than ADC FIFO threshold */ + __IM unsigned int DAC_FIFO_EMPTY : 1; /*!< [4..4] Set when FIFO is empty. This bit gets + cleared when the DAC FIFO is not empty. */ + __IM unsigned int DAC_FIFO_AEMPTY : 1; /*!< [5..5] Set when the FIFO occupancy + less than DAC FIFO threshold */ + __IM unsigned int ADC_FIFO_FULL : 1; /*!< [6..6] Set when ADC FIFO is full. + This bit gets cleared when data is + read from the FIFO. */ + __IM unsigned int ADC_FIFO_AFULL : 1; /*!< [7..7] Set when ADC FIFO occupancy + greater than ADC FIFO threshold. */ + __IM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } FIFO_STATUS_REG_b; + }; + + union { + __IOM unsigned int ADC_CTRL_REG_2; /*!< (@ 0x00000034) ADC Control register2 */ + + struct { + __IOM unsigned int EXT_TRIG_DETECT_1 : 2; /*!< [1..0] Condition to detect event on + external trigger 1 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM unsigned int EXT_TRIG_DETECT_2 : 2; /*!< [3..2] Condition to detect event on + external trigger 2 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM unsigned int EXT_TRIG_DETECT_3 : 2; /*!< [5..4] Condition to detect event on + external trigger 3 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM unsigned int EXT_TRIG_DETECT_4 : 2; /*!< [7..6] Condition to detect event on + external trigger 4 00: None (trigger + disabled) 01: Positive edge 10: Negative + edge 11: Positive or negative edge. */ + __IOM unsigned int EXT_TRIGGER_SEL_4 : 4; /*!< [11..8] 4-bit Channel ID corresponding to + external trigger 4. */ + __IOM unsigned int EXT_TRIGGER_SEL_3 : 4; /*!< [15..12] 4-bit Channel ID corresponding to + external trigger 3. */ + __IOM unsigned int EXT_TRIGGER_SEL_2 : 4; /*!< [19..16] Enable bit corresponding to + channel id selected for trigger 2. */ + __IOM unsigned int EXT_TRIGGER_SEL_1 : 4; /*!< [23..20] 4-bit Channel ID corresponding to + external trigger 1. */ + __IOM unsigned int TRIG_1_MATCH : 1; /*!< [24..24] indicating trigger 1 is matched. Write + 1 to clear this bit. */ + __IOM unsigned int TRIG_2_MATCH : 1; /*!< [25..25] indicating trigger 2 is matched. Write + 1 to clear this bit. */ + __IOM unsigned int TRIG_3_MATCH : 1; /*!< [26..26] indicating trigger 3 is matched. Write + 1 to clear this bit. */ + __IOM unsigned int TRIG_4_MATCH : 1; /*!< [27..27] indicating trigger 4 is matched. Write + 1 to clear this bit. */ + __IOM unsigned int RESERVED1 : 4; /*!< [31..28] Reserved1 */ + } ADC_CTRL_REG_2_b; + }; + __IOM AUX_ADC_DAC_COMP_ADC_CH_BIT_MAP_CONFIG_Type ADC_CH_BIT_MAP_CONFIG[16]; /*!< (@ 0x00000038) [0..15] */ + + union { + __IOM unsigned int ADC_CH_OFFSET[16]; /*!< (@ 0x00000138) This Register specifies initial + offset value with respect to AUX_ADC clock after + which Channel(0-16)should be sampled. */ + + struct { + __IOM unsigned int CH_OFFSET : 16; /*!< [15..0] This Register field specifies initial + offset value with respect to AUX_ADC clock after + which Channel(0-16)should be sampled. */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } ADC_CH_OFFSET_b[16]; + }; + + union { + __IOM unsigned int ADC_CH_FREQ[16]; /*!< (@ 0x00000178) This register specifies Sampling + frequency rate at which AUX ADC Date is sampled for + Channel(1 to 16 ) */ + + struct { + __IOM unsigned int CH_FREQ_VALUE : 16; /*!< [15..0] This register specifies Sampling + frequency rate at which AUX ADC Date is sampled + for Channel all respective channel (1-16) */ + __IOM unsigned int RESERVED1 : 16; /*!< [31..16] Reserved1 */ + } ADC_CH_FREQ_b[16]; + }; + + union { + __IOM unsigned int ADC_CH_PHASE_1; /*!< (@ 0x000001B8) ADC Channel Phase 1 */ + + struct { + __IOM unsigned int CH1_PHASE : 4; /*!< [3..0] Phase corresponding to channel-1 */ + __IOM unsigned int CH2_PHASE : 4; /*!< [7..4] Phase corresponding to channel-2 */ + __IOM unsigned int CH3_PHASE : 4; /*!< [11..8] Phase corresponding to channel-3 */ + __IOM unsigned int CH4_PHASE : 4; /*!< [15..12] Phase corresponding to channel-4 */ + __IOM unsigned int CH5_PHASE : 4; /*!< [19..16] Phase corresponding to channel-5 */ + __IOM unsigned int CH6_PHASE : 4; /*!< [23..20] Phase corresponding to channel-6 */ + __IOM unsigned int CH7_PHASE : 4; /*!< [27..24] Phase corresponding to channel-7 */ + __IOM unsigned int CH8_PHASE : 4; /*!< [31..28] Phase corresponding to channel-8 */ + } ADC_CH_PHASE_1_b; + }; + + union { + __IOM unsigned int ADC_CH_PHASE_2; /*!< (@ 0x000001BC) ADC Channel Phase 2 */ + + struct { + __IOM unsigned int CH9_PHASE : 4; /*!< [3..0] Phase corresponding to channel-9 */ + __IOM unsigned int CH10_PHASE : 4; /*!< [7..4] Phase corresponding to channel-10 */ + __IOM unsigned int CH11_PHASE : 4; /*!< [11..8] Phase corresponding to channel-11 */ + __IOM unsigned int CH12_PHASE : 4; /*!< [15..12] Phase corresponding to channel-12 */ + __IOM unsigned int CH13_PHASE : 4; /*!< [19..16] Phase corresponding to channel-13 */ + __IOM unsigned int CH14_PHASE : 4; /*!< [23..20] Phase corresponding to channel-14 */ + __IOM unsigned int CH15_PHASE : 4; /*!< [27..24] Phase corresponding to channel-15 */ + __IOM unsigned int CH16_PHASE : 4; /*!< [31..28] Phase corresponding to channel-16 */ + } ADC_CH_PHASE_2_b; + }; + __IM unsigned int RESERVED; + + union { + __IOM unsigned int ADC_SINGLE_CH_CTRL_1; /*!< (@ 0x000001C4) ADC SINGLE Channel + Configuration */ + + struct { + __IOM unsigned int ADC_CH_INDEX_SINGLE_CHAN_1 : 32; /*!< [31..0] [31:0]out of total 48 + bits of bit map for single channel + mode of a particular + channel. */ + } ADC_SINGLE_CH_CTRL_1_b; + }; + + union { + __IOM unsigned int ADC_SINGLE_CH_CTRL_2; /*!< (@ 0x000001C8) ADC SINGLE Channel + Configuration */ + + struct { + __IOM unsigned int ADC_CH_INDEX_SINGLE_CHAN_2 : 16; /*!< [15..0] [47:32] out of total 48 + bits of bit map for single channel + mode of a particular + channel. */ + __IOM unsigned int ADC_INTERPOL_SINGLE_CHAN : 2; /*!< [17..16] Interpolation angle for + the particular channel in single + channel mode whose bit + sequence has been written to + adc_ch_index_single_c an. */ + __IOM unsigned int RESERVED1 : 14; /*!< [31..18] Reserved1 */ + } ADC_SINGLE_CH_CTRL_2_b; + }; + + union { + __IOM unsigned int ADC_SEQ_CTRL; /*!< (@ 0x000001CC) This register explain + configuration parameter for AUXADC */ + + struct { + __IOM unsigned int ADC_SEQ_CTRL_PING_PONG : 16; /*!< [15..0] To enable/disable per + channel DAM mode (One-hot coding) */ + __IOM unsigned int ADC_SEQ_CTRL_DMA_MODE : 16; /*!< [31..16] To enable/disable per + channel ping-pong operation (One-hot + coding). */ + } ADC_SEQ_CTRL_b; + }; + + union { + __IOM unsigned int VAD_BBP_ID; /*!< (@ 0x000001D0) This register explain VDD BBP ID */ + + struct { + __IOM unsigned int BPP_ID : 4; /*!< [3..0] Channel id for bbp samples. */ + __IOM unsigned int BPP_EN : 1; /*!< [4..4] Enables Aux-ADC samples to BBP */ + __IOM unsigned int AUX_ADC_BPP_EN : 1; /*!< [5..5] Enable Indication for BBP */ + __IOM unsigned int RESERVED1 : 10; /*!< [15..6] RESERVED1 */ + __IOM unsigned int DISCONNET_MODE : 16; /*!< [31..16] Per channel discontinuous mode + enable signal. When discontinuous mode is + enabled, data is sampled only once from that + channel and the enable bit is reset to 0. */ + } VAD_BBP_ID_b; + }; + + union { + __IOM unsigned int ADC_INT_MEM_1; /*!< (@ 0x000001D4) This register explain start address + of first/second buffer corresponding to the channel + location ADC INT MEM 2 */ + + struct { + __IOM unsigned int PROG_WR_DATA : 32; /*!< [31..0] These 32-bits specifies the + start address of first/second + buffer corresponding to the + channel location ADC INT MEM */ + } ADC_INT_MEM_1_b; + }; + + union { + __IOM unsigned int ADC_INT_MEM_2; /*!< (@ 0x000001D8) This register explain ADC + INT MEM2. */ + + struct { + __IOM unsigned int PROG_WR_DATA : 10; /*!< [9..0] These 10-bits specify the buffer length + of first/second buffer corresponding to the + channel location ADC INT MEM2 */ + __IOM unsigned int PROG_WR_ADDR : 5; /*!< [14..10] These bits correspond to + the address of the internal memory + basing on the channel number, whose + information we want to program */ + __IOM unsigned int PROG_WR_DATA1 : 1; /*!< [15..15] Valid bit for first/second buffers + corresponding to ADC INT MEM2 */ + __IOM unsigned int RESERVED3 : 16; /*!< [31..16] Reserved3 */ + } ADC_INT_MEM_2_b; + }; + + union { + __IOM unsigned int INTERNAL_DMA_CH_ENABLE; /*!< (@ 0x000001DC) This register is + internal channel enable */ + + struct { + __IOM unsigned int PER_CHANNEL_ENABLE : 16; /*!< [15..0] Enable bit for Each + channel,like channel0 for bit0 + to channel15 for bit15 etc */ + __IOM unsigned int RESERVED3 : 15; /*!< [30..16] Reserved3 */ + __IOM unsigned int INTERNAL_DMA_ENABLE : 1; /*!< [31..31] When Set, Internal DMA will be + used for reading ADC + samples from ADC FIFO and writing + them to ULP SRAM Memories. */ + } INTERNAL_DMA_CH_ENABLE_b; + }; + + union { + __IOM unsigned int TS_PTAT_ENABLE; /*!< (@ 0x000001E0) This register is enable + PTAT for temperature sensor */ + + struct { + __IOM unsigned int TS_PTAT_EN : 1; /*!< [0..0] BJT based Temperature sensor */ + __IOM unsigned int RESERVED1 : 31; /*!< [31..1] Reserved1 */ + } TS_PTAT_ENABLE_b; + }; + + union { + __OM unsigned int ADC_FIFO_THRESHOLD; /*!< (@ 0x000001E4) Configured FIFO to ADC */ + + struct { + __OM unsigned int ADC_FIFO_AEMPTY_THRESHOLD : 4; /*!< [3..0] FIFO almost empty + threshold for ADC */ + __OM unsigned int ADC_FIFO_AFULL_THRESHOLD : 4; /*!< [7..4] FIFO almost full + threshold for ADC */ + __OM unsigned int RESERVED1 : 24; /*!< [31..8] Reserved1 */ + } ADC_FIFO_THRESHOLD_b; + }; + __IM unsigned int RESERVED1[6]; + + union { + __IOM unsigned int BOD; /*!< (@ 0x00000200) Programs resistor bank, reference + buffer and scaler */ + + struct { + __IOM unsigned int EN_BOD_TEST_MUX : 1; /*!< [0..0] 1 - To enable test mux */ + __IOM unsigned int BOD_TEST_SEL : 2; /*!< [2..1] Select bits for test mux */ + __IOM unsigned int REFBUF_EN : 1; /*!< [3..3] Reference buffer configuration 1 + for enable 0 for disable */ + __IOM unsigned int REFBUF_VOLT_SEL : 4; /*!< [7..4] selection of voltage of + reference buffer */ + __IOM unsigned int BOD_RES_EN : 1; /*!< [8..8] configuration of register bank + 1 for enable and 0 for disable */ + __IOM unsigned int BOD_THRSH : 5; /*!< [13..9] Programmability for resistor bank */ + __IOM unsigned int RESERVED2 : 18; /*!< [31..14] Reserved2 */ + } BOD_b; + }; + + union { + __IOM unsigned int COMPARATOR1; /*!< (@ 0x00000204) Programs comparators1 and + comparators2 */ + + struct { + __IOM unsigned int CMP1_EN : 1; /*!< [0..0] To enable comparator1 */ + __IOM unsigned int CMP1_EN_FILTER : 1; /*!< [1..1] To enable filter for comparator 1 */ + __IOM unsigned int CMP1_HYST : 2; /*!< [3..2] Programmability to control + hysteresis of comparator1 */ + __IOM unsigned int CMP1_MUX_SEL_P : 4; /*!< [7..4] Select for positive input + of comparator_1 */ + __IOM unsigned int CMP1_MUX_SEL_N : 4; /*!< [11..8] Select for negative input + of comparator_1 */ + __IOM unsigned int CMP2_EN : 1; /*!< [12..12] To enable comparator 2 */ + __IOM unsigned int CMP2_EN_FILTER : 1; /*!< [13..13] To enable filter for + comparator 2 */ + __IOM unsigned int CMP2_HYST : 2; /*!< [15..14] Programmability to control + hysteresis of comparator2 */ + __IOM unsigned int CMP2_MUX_SEL_P : 4; /*!< [19..16] Select for positive input + of comparator_2 */ + __IOM unsigned int CMP2_MUX_SEL_N : 4; /*!< [23..20] Select for negative input + of comparator_2 */ + __IOM unsigned int COM_DYN_EN : 1; /*!< [24..24] Dynamic enable for registers */ + __IOM unsigned int RESERVED1 : 7; /*!< [31..25] Reserved1 */ + } COMPARATOR1_b; + }; + + union { + __IOM unsigned int AUXADC_CONFIG_2; /*!< (@ 0x00000208) This register is AUX-ADC + config2 */ + + struct { + __IOM unsigned int AUXADC_INP_SEL : 5; /*!< [4..0] Mux select for positive + input of adc */ + __IOM unsigned int AUXADC_INN_SEL : 4; /*!< [8..5] Mux select for negetive + input of adc */ + __IOM unsigned int AUXADC_DIFF_MODE : 1; /*!< [9..9] AUX ADC Differential Mode */ + __IOM unsigned int AUXADC_ENABLE : 1; /*!< [10..10] Static Enable */ + __IOM unsigned int AUXADC_DYN_ENABLE : 1; /*!< [11..11] Aux ADC Configuration Enable */ + __IOM unsigned int RESERVED2 : 20; /*!< [31..12] Reserved2 */ + } AUXADC_CONFIG_2_b; + }; + + union { + __IOM unsigned int AUXDAC_CONIG_1; /*!< (@ 0x0000020C) This register is AUX-DAC + config1 */ + + struct { + __IOM unsigned int AUXDAC_EN_S : 1; /*!< [0..0] Enable signal DAC */ + __IOM unsigned int AUXDAC_OUT_MUX_EN : 1; /*!< [1..1] Aux OUT mux Enable */ + __IOM unsigned int AUXDAC_OUT_MUX_SEL : 1; /*!< [2..2] AUXDAC OUT MUX SELECT Enable */ + __IOM unsigned int RESERVED1 : 1; /*!< [3..3] Reserved1 */ + __IOM unsigned int AUXDAC_DATA_S : 10; /*!< [13..4] Satatic AUX Dac Data */ + __IOM unsigned int AUXDAC_DYN_EN : 1; /*!< [14..14] Satatic AUX Dac Data */ + __IOM unsigned int RESERVED2 : 17; /*!< [31..15] RESERVED2 */ + } AUXDAC_CONIG_1_b; + }; + + union { + __IOM unsigned int AUX_LDO; /*!< (@ 0x00000210) This register is AUX-LDO configuration */ + + struct { + __IOM unsigned int LDO_CTRL : 4; /*!< [3..0] Enable ldo control field */ + __IOM unsigned int LDO_DEFAULT_MODE : 1; /*!< [4..4] ldo default mode enable */ + __IOM unsigned int BYPASS_LDO : 1; /*!< [5..5] bypass the LDO */ + __IOM unsigned int ENABLE_LDO : 1; /*!< [6..6] Turn LDO */ + __IOM unsigned int DYN_EN : 1; /*!< [7..7] Dynamic Enable */ + __IOM unsigned int RESERVED1 : 24; /*!< [31..8] It is recommended to write + these bits to 0. */ + } AUX_LDO_b; + }; +} AUX_ADC_DAC_COMP_Type; /*!< Size = 532 (0x214) */ + +/* =========================================================================================================================== + */ +/* ================ IR + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief IR Decoder are used for the decoding the external ir sensor input. + * (IR) + */ + +typedef struct { /*!< (@ 0x24040C00) IR Structure */ + + union { + __IOM unsigned int IR_OFF_TIME_DURATION; /*!< (@ 0x00000000) This register used for IR + sleep duration timer value. */ + + struct { + __IOM unsigned int IR_OFF_TIME_DURATION : 17; /*!< [16..0] This field define + ir off time */ + __IM unsigned int RES : 15; /*!< [31..17] reserved5 */ + } IR_OFF_TIME_DURATION_b; + }; + + union { + __IOM unsigned int IR_ON_TIME_DURATION; /*!< (@ 0x00000004) This register used for IR + Detection duration timer value. */ + + struct { + __IOM unsigned int IR_ON_TIME_DURATION : 12; /*!< [11..0] This field define ir on time + for ir detection on */ + __IM unsigned int RES : 20; /*!< [31..12] reserved5 */ + } IR_ON_TIME_DURATION_b; + }; + + union { + __IOM unsigned int IR_FRAME_DONE_THRESHOLD; /*!< (@ 0x00000008) This register used count + with respect to 32KHz clock after not more + toggle are expected to a given pattern. */ + + struct { + __IOM unsigned int IR_FRAME_DONE_THRESHOLD : 15; /*!< [14..0] count with respect to 32KHz + clock after not more toggle are + expected to a given pattern */ + __IM unsigned int RES : 17; /*!< [31..15] reserved5 */ + } IR_FRAME_DONE_THRESHOLD_b; + }; + + union { + __IOM unsigned int IR_DET_THRESHOLD; /*!< (@ 0x0000000C) This register used Minimum Number + of edges to detected during on-time failing which + IR detection is re-stated. */ + + struct { + __IOM unsigned int IR_DET_THRESHOLD : 7; /*!< [6..0] Minimum Number of edges to detected + during on-time failing + which IR detection is re-stated. */ + __IM unsigned int RES : 25; /*!< [31..7] reserved5 */ + } IR_DET_THRESHOLD_b; + }; + + union { + __IOM unsigned int IR_CONFIG; /*!< (@ 0x00000010) This register used to configure the ir + structure for application purpose. */ + + struct { + __IOM unsigned int EN_IR_DET : 1; /*!< [0..0] Enable IR detection logic bit if bit 1 then + detection enable if 0 then not enable. */ + __IOM unsigned int IR_DET_RSTART : 1; /*!< [1..1] Enable IR detection re-start logic bit + if bit 1 then re-start. */ + __IOM unsigned int EN_CLK_IR_CORE : 1; /*!< [2..2] Enable 32KHz clock to IR Core bit ,if + bit 1 then clock gating disable and bit is 0 + then clock gating Enable */ + __IM unsigned int RES : 5; /*!< [7..3] reserved5 */ + __IOM unsigned int EN_CONT_IR_DET : 1; /*!< [8..8] This bit is Enable continues IR + detection,When enabled there will be no power + cycling on External IR Sensor. */ + __IM unsigned int RES1 : 7; /*!< [15..9] reserved6 */ + __IOM unsigned int SREST_IR_CORE : 1; /*!< [16..16] This bit is used soft + reset IR core block */ + __IM unsigned int RES2 : 15; /*!< [31..17] reserved7 */ + } IR_CONFIG_b; + }; + + union { + __IOM unsigned int IR_MEM_ADDR_ACCESS; /*!< (@ 0x00000014) This register used to access + memory address for application purpose. */ + + struct { + __IOM unsigned int IR_MEM_ADDR : 7; /*!< [6..0] This field is used to IR read + address. */ + __IOM unsigned int RES : 1; /*!< [7..7] reserved5 */ + __IOM unsigned int IR_MEM_WR_EN : 1; /*!< [8..8] IR memory write enable. */ + __IOM unsigned int IR_MEM_RD_EN : 1; /*!< [9..9] This field used to IR memory + read enable. */ + __IOM unsigned int RES1 : 6; /*!< [15..10] reserved1 */ + __IOM unsigned int IR_MEM_WR_TEST_MODE : 1; /*!< [16..16] IR memory write + enable in test mode.. */ + __IOM unsigned int RES2 : 15; /*!< [31..17] reserved2 */ + } IR_MEM_ADDR_ACCESS_b; + }; + + union { + __IM unsigned int IR_MEM_READ; /*!< (@ 0x00000018) This register used to IR Read + data from memory. */ + + struct { + __IM unsigned int IR_MEM_DATA_OUT : 16; /*!< [15..0] This field is used to IR + Read data from memory. */ + __IM unsigned int RES : 8; /*!< [23..16] reserved5 */ + __IM unsigned int IR_DATA_MEM_DEPTH : 7; /*!< [30..24] This field used to indicated + valid number of IR Address + in the memory to be read. */ + __IM unsigned int RES1 : 1; /*!< [31..31] reserved6 */ + } IR_MEM_READ_b; + }; +} IR_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== + */ +/* ================ CTS + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief The capacitive touch sensor (CTS) controller is used to detect the + position of the touch from the user on the capacitive touch screen (CTS) + */ + +typedef struct { /*!< (@ 0x24042C00) CTS Structure */ + + union { + __IOM unsigned int CTS_CONFIG_REG_0_0; /*!< (@ 0x00000000) Configuration Register 0_0 */ + + struct { + __IOM unsigned int CLK_SEL1 : 2; /*!< [1..0] Mux select for clock_mux_1 */ + __IOM unsigned int PRE_SCALAR_1 : 8; /*!< [9..2] Division factor for clock divider */ + __IOM unsigned int PRE_SCALAR_2 : 4; /*!< [13..10] Division factor for clock divider */ + __IOM unsigned int CLK_SEL2 : 1; /*!< [14..14] Mux select for clock_mux_2 */ + __IOM unsigned int CTS_STATIC_CLK_EN : 1; /*!< [15..15] Enable static for + capacitive touch sensor */ + __IOM unsigned int FIFO_AFULL_THRLD : 6; /*!< [21..16] Threshold for fifo afull */ + __IOM unsigned int FIFO_AEMPTY_THRLD : 6; /*!< [27..22] Threshold for fifo aempty */ + __IM unsigned int FIFO_EMPTY : 1; /*!< [28..28] FIFO empty status bit */ + __IM unsigned int RESERVED1 : 3; /*!< [31..29] Reserved1 */ + } CTS_CONFIG_REG_0_0_b; + }; + + union { + __IOM unsigned int CTS_FIFO_ADDRESS; /*!< (@ 0x00000004) FIFO Address Register */ + + struct { + __IOM unsigned int FIFO : 32; /*!< [31..0] Used for FIFO reads and write operations */ + } CTS_FIFO_ADDRESS_b; + }; + __IM unsigned int RESERVED[62]; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_1; /*!< (@ 0x00000100) Configuration Register 1_1 */ + + struct { + __IOM unsigned int POLYNOMIAL_LEN : 2; /*!< [1..0] Length of polynomial */ + __IOM unsigned int SEED_LOAD : 1; /*!< [2..2] Seed of polynomial */ + __IOM unsigned int BUFFER_DELAY : 5; /*!< [7..3] Delay of buffer. Delay programmed will + be equal to delay in nano seconds. Max delay + value is 32.Default delay should be programmed + before using Capacitive touch sensor module. */ + __IOM unsigned int WAKE_UP_ACK : 1; /*!< [8..8] Ack for wake up interrupt. This is a + level signal. To acknowledge wake up , set this + bit to one and reset it + . */ + __IOM unsigned int ENABLE1 : 1; /*!< [9..9] Enable signal */ + __IOM unsigned int SOFT_RESET_2 : 1; /*!< [10..10] Reset the FIFO write and + FIFO read occupancy pointers */ + __IOM unsigned int CNT_ONEHOT_MODE : 1; /*!< [11..11] Continuous or One hot mode */ + __IOM unsigned int SAMPLE_MODE : 2; /*!< [13..12] Select bits for FIFO write + and FIFO average */ + __IOM unsigned int RESET_WR_FIFO : 1; /*!< [14..14] Resets the signal fifo_wr_int */ + __OM unsigned int BYPASS : 1; /*!< [15..15] Bypass signal */ + __IOM unsigned int BIT_SEL : 2; /*!< [17..16] Selects different set of 12 bits + to be stored in FIFO */ + __IOM unsigned int EXT_TRIG_SEL : 1; /*!< [18..18] Select bit for NPSS clock + or Enable */ + __IOM unsigned int EXT_TRIG_EN : 1; /*!< [19..19] Select bit for NPSS clock or + Enable */ + __IOM unsigned int RESERVED2 : 12; /*!< [31..20] Reserved2 */ + } CTS_CONFIG_REG_1_1_b; + }; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_2; /*!< (@ 0x00000104) Configuration Register 1_2 */ + + struct { + __IOM unsigned int PWM_ON_PERIOD : 16; /*!< [15..0] PWM ON period */ + __IOM unsigned int PWM_OFF_PERIOD : 16; /*!< [31..16] PWM OFF period */ + } CTS_CONFIG_REG_1_2_b; + }; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_3; /*!< (@ 0x00000108) Configuration Register 1_3 */ + + struct { + __IOM unsigned int PRS_SEED : 32; /*!< [31..0] Pseudo random generator (PRS) + seed value */ + } CTS_CONFIG_REG_1_3_b; + }; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_4; /*!< (@ 0x0000010C) Configuration Register 1_4 */ + + struct { + __IOM unsigned int PRS_POLY : 32; /*!< [31..0] Polynomial programming register + for PRS generator */ + } CTS_CONFIG_REG_1_4_b; + }; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_5; /*!< (@ 0x00000110) Configuration Register 1_5 */ + + struct { + __IOM unsigned int INTER_SENSOR_DELAY : 16; /*!< [15..0] Inter-sensor scan + delay value */ + __IOM unsigned int N_SAMPLE_COUNT : 16; /*!< [31..16] Number of repetitions of + sensor scan */ + } CTS_CONFIG_REG_1_5_b; + }; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_6; /*!< (@ 0x00000114) Configuration Register 1_6 */ + + struct { + __IOM unsigned int SENSOR_CFG : 32; /*!< [31..0] Register of scan controller + containing the programmed bit map */ + } CTS_CONFIG_REG_1_6_b; + }; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_7; /*!< (@ 0x00000118) Configuration Register 1_7 */ + + struct { + __IOM unsigned int VALID_SENSORS : 4; /*!< [3..0] Value of number of sensors + valid in the bit map */ + __IOM unsigned int RESERVED1 : 2; /*!< [5..4] Reserved1 */ + __IOM unsigned int REF_VOLT_CONFIG : 9; /*!< [14..6] This is given as an input voltage to + analog model as + comparator reference voltage. */ + __IOM unsigned int WAKEUP_MODE : 1; /*!< [15..15] Select bit for high/low mode. */ + __IOM unsigned int WAKE_UP_THRESHOLD : 16; /*!< [31..16] Wakeup threshold. */ + } CTS_CONFIG_REG_1_7_b; + }; + + union { + __IM unsigned int CTS_CONFIG_REG_1_8; /*!< (@ 0x0000011C) Configuration Register 1_8 */ + + struct { + __IM unsigned int PRS_STATE : 32; /*!< [31..0] Current state of PRS */ + } CTS_CONFIG_REG_1_8_b; + }; + + union { + __IOM unsigned int CTS_CONFIG_REG_1_9; /*!< (@ 0x00000120) Configuration Register 1_9 */ + + struct { + __IOM unsigned int TRIG_DIV : 10; /*!< [9..0] Allows one pulse for every 'trig_div' no. + of pulses of 1 ms clock */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] Reserved1 */ + } CTS_CONFIG_REG_1_9_b; + }; +} CTS_Type; /*!< Size = 292 (0x124) */ + +/* =========================================================================================================================== + */ +/* ================ MISC_CONFIG + * ================ */ +/* =========================================================================================================================== + */ + +/** + * @brief MISC CONFIG Register (MISC_CONFIG) + */ + +typedef struct { /*!< (@ 0x46008000) MISC_CONFIG Structure */ + + union { + __IOM unsigned int MISC_CFG_HOST_INTR_MASK; /*!< (@ 0x00000000) MISC CFG HOST + INTR MASK */ + + struct { + __IOM unsigned int HOST_INTR_MSK : 8; /*!< [7..0] Writing 1 in any bit masks + the corresponding interrupt in + HOST_INTR_STATUS. */ + __IOM unsigned int HOST_SPI_INTR_OPEN_DRAIN_MODE : 1; /*!< [8..8] Writing 1 to this bit + configures the host SPI + interrupt in open drain mode. + When open drain mode is enabled + and interrupt is configured in + active high mode, external + PULLDOWN has to be used + on the board. */ + __IOM + unsigned int HOST_SPI_INTR_ACTIVE_LOW_MODE : 1; /*!< [9..9] Writing 1 to this + bit configures the host SPI + interrupt in active low + mode. By default, it will be + active high. */ + __IOM unsigned int RESERVED1 : 22; /*!< [31..10] reserved1 */ + } MISC_CFG_HOST_INTR_MASK_b; + }; +} MISC_CONFIG_Type; /*!< Size = 4 (0x4) */ + +#if defined(SLI_SI917B0) || defined(SLI_SI915) +/**************************************************************************/ /** + * @defgroup RSI_DEVICE_SYSRTC SYSRTC + * @{ + * @brief RSI_DEVICE SYSRTC Register Declaration. + *****************************************************************************/ + +/** SYSRTC Register Declaration. */ +typedef struct { + __IM unsigned int IPVERSION; /**< IP VERSION */ + __IOM unsigned int EN; /**< Module Enable Register */ + __IOM unsigned int SWRST; /**< Software Reset Register */ + __IOM unsigned int CFG; /**< Configuration Register */ + __IOM unsigned int CMD; /**< Command Register */ + __IM unsigned int STATUS; /**< Status register */ + __IOM unsigned int CNT; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK; /**< Configuration Lock Register */ + unsigned int RESERVED0[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK; /**< FAILDET Lock Register */ + unsigned int RESERVED1[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY; /**< Synchronization busy Register */ + unsigned int RESERVED2[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY; /**< Synchronization busy Register */ + unsigned int RESERVED3[33U]; /**< GRP2 - GRP7,Reserved for future use */ + __IM unsigned int IPVERSION_SET; /**< IP VERSION */ + __IOM unsigned int EN_SET; /**< Module Enable Register */ + __IOM unsigned int SWRST_SET; /**< Software Reset Register */ + __IOM unsigned int CFG_SET; /**< Configuration Register */ + __IOM unsigned int CMD_SET; /**< Command Register */ + __IM unsigned int STATUS_SET; /**< Status register */ + __IOM unsigned int CNT_SET; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK_SET; /**< Configuration Lock Register */ + unsigned int RESERVED4[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL_SET; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK_SET; /**< FAILDET Lock Register */ + unsigned int RESERVED5[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL_SET; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + unsigned int RESERVED6[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF_SET; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN_SET; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL_SET; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY_SET; /**< Synchronization busy Register */ + unsigned int RESERVED7[33U]; /**< Reserved for future use */ + __IM unsigned int IPVERSION_CLR; /**< IP VERSION */ + __IOM unsigned int EN_CLR; /**< Module Enable Register */ + __IOM unsigned int SWRST_CLR; /**< Software Reset Register */ + __IOM unsigned int CFG_CLR; /**< Configuration Register */ + __IOM unsigned int CMD_CLR; /**< Command Register */ + __IM unsigned int STATUS_CLR; /**< Status register */ + __IOM unsigned int CNT_CLR; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK_CLR; /**< Configuration Lock Register */ + unsigned int RESERVED8[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL_CLR; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK_CLR; /**< FAILDET Lock Register */ + unsigned int RESERVED9[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + unsigned int RESERVED10[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF_CLR; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN_CLR; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL_CLR; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY_CLR; /**< Synchronization busy Register */ + unsigned int RESERVED11[33U]; /**< Reserved for future use */ + __IM unsigned int IPVERSION_TGL; /**< IP VERSION */ + __IOM unsigned int EN_TGL; /**< Module Enable Register */ + __IOM unsigned int SWRST_TGL; /**< Software Reset Register */ + __IOM unsigned int CFG_TGL; /**< Configuration Register */ + __IOM unsigned int CMD_TGL; /**< Command Register */ + __IM unsigned int STATUS_TGL; /**< Status register */ + __IOM unsigned int CNT_TGL; /**< Counter Value Register */ + __IM unsigned int SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM unsigned int LOCK_TGL; /**< Configuration Lock Register */ + unsigned int RESERVED12[3U]; /**< Reserved for future use */ + __IOM unsigned int FAILDETCTRL_TGL; /**< Failure Detection */ + __IOM unsigned int FAILDETLOCK_TGL; /**< FAILDET Lock Register */ + unsigned int RESERVED13[2U]; /**< Reserved for future use */ + __IOM unsigned int GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM unsigned int GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM unsigned int GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM unsigned int GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM unsigned int GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM unsigned int GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM unsigned int GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + unsigned int RESERVED14[1U]; /**< Reserved for future use */ + __IOM unsigned int GRP1_IF_TGL; /**< Group Interrupt Flags */ + __IOM unsigned int GRP1_IEN_TGL; /**< Group Interrupt Enables */ + __IOM unsigned int GRP1_CTRL_TGL; /**< Group Control Register */ + __IOM unsigned int GRP1_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM unsigned int GRP1_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM unsigned int GRP1_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM unsigned int GRP1_SYNCBUSY_TGL; /**< Synchronization busy Register */ + unsigned int RESERVED15[32U]; /**< Reserved for future use */ + __IOM unsigned int MCUSYSRTC_REG1; /**< input and output configuration */ + +} SYSRTC_TypeDef; + +/* =========================================================================================================================== */ +/* ================ SDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SDC_SDC_DATA_REG [SDC_DATA_REG] (SDC Data registers (0-15)) + */ +typedef struct { + union { + __IM unsigned int DATA_REG; /*!< (@ 0x00000000) SDC Data register */ + + struct { + __IM unsigned int + SDC_DATA_SAMPLE : 12; /*!< [11..0] Sample 0 collected from Sensor through Aux ADC. */ + __IM unsigned int SMP_ID_CH : 2; /*!< [13..12] Channel iD for sample */ + __IM unsigned int + RESERVED1 : 18; /*!< [31..14] reserved1 */ + } DATA_REG_b; + }; +} SDC_SDC_DATA_REG_Type; + +/** + * @brief Sensor Data Collector Register structure (SDC) + */ + +typedef struct { /*!< (@ 0x24042400) SDC Structure */ + + union { + __IOM unsigned int + SDC_GEN_CONFIG_0; /*!< (@ 0x00000000) SDC general configuration 0 */ + + struct { + __IOM unsigned int INTR_STATUS_CLEAR : 1; /*!< [0..0] Writing 1 clears interrupt, reading gives SDC Interrupt + status */ + __IOM unsigned int + RESERVED1 : 31; /*!< [31..1] Reserevd */ + } SDC_GEN_CONFIG_0_b; + }; + + union { + __IOM unsigned int + SDC_GEN_CONFIG_1; /*!< (@ 0x00000004) SDC general configuration 1 */ + + struct { + __IOM unsigned int RST_WRT_PTR : 1; /*!< [0..0] Writing 1 will resets the write pointer so that new samples + can be filled in Buffer. */ + __IM unsigned int WRT_PTR : 4; /*!< [4..1] Write pointer Value */ + __IOM unsigned int SAMP_THRESH : 4; /*!< [8..5] Number of data sampled to be collected from Aux-ADC and + stored in Buffer before interrupt is raised/wakeup is initialed */ + __IOM unsigned int + RESERVED1 : 23; /*!< [31..9] Reserevd */ + } SDC_GEN_CONFIG_1_b; + }; + + union { + __IOM unsigned int + SDC_GEN_CONFIG_2; /*!< (@ 0x00000008) SDC general configuration 2 */ + + struct { + __IOM unsigned int + SDC_SAMP_EN : 1; /*!< [0..0] SDC Data Sampling mode */ + __IOM unsigned int + NUM_CH_SEL : 3; /*!< [3..1] Number of Channels to be used */ + __IOM unsigned int + RESERVED1 : 28; /*!< [31..4] Reserevd */ + } SDC_GEN_CONFIG_2_b; + }; + + union { + __IOM unsigned int + SDC_GEN_CONFIG_3; /*!< (@ 0x00000014) SDC general configuration 3 */ + + struct { + __IOM unsigned int + SAMP_TRIG_SEL : 1; /*!< [0..0] select the trigger event on which AUX-ADC Data is sampled */ + __IOM unsigned int + CNT_TRIG_EVNT : 10; /*!< [10..1] which trigger event AUX-ADC Data will sampled */ + __IOM unsigned int + SDC_CLK_DIV : 10; /*!< [20..11] SDCSS clock division factor */ + __IOM unsigned int + RESERVED1 : 11; /*!< [31..21] Reserevd */ + } SDC_GEN_CONFIG_3_b; + }; + __IM unsigned int RESERVED[2]; + union { + __IOM unsigned int + SDC_AUXADC_CONFIG_1; /*!< (@ 0x00000018) SDC AUX ADC configuration 1 */ + + struct { + __IOM unsigned int + SDC_AUXADC_INPUT_P_SEL_CH1 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-1 */ + __IOM unsigned int + SDC_AUXADC_INPUT_N_SEL_CH1 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-1 */ + __IOM unsigned int + SDC_AUXADC_DIFF_MODE_CH1 : 1; /*!< [9..9] Enable Differential Mode in AUX ADC for Channel -1 */ + __IOM unsigned int + SDC_AUXADC_EN : 1; /*!< [10..10] AUXADC Enable from SDC Block */ + __IOM unsigned int SDC_ADC_CONFIG_EN : 1; /*!< [11..11] On Enabling this register, SDC ADC Configuration will + be Applied. */ + __IOM unsigned int + RESERVED1 : 20; /*!< [31..12] Reserevd */ + } SDC_AUXADC_CONFIG_1_b; + }; + + union { + __IOM unsigned int + SDC_AUXDAC_CONFIG_1; /*!< (@ 0x0000001C) SDC AUX DAC configuration 1 */ + + struct { + __IOM unsigned int + SDC_DAC_EN : 1; /*!< [0..0] Enable signal DAC */ + __IOM unsigned int + SDC_DAC_OUT_MUX_EN : 1; /*!< [1..1] Enable signal for Connecting DAC Output to GPIO */ + __IOM unsigned int SDC_DAC_OUT_MUX_SEL : 1; /*!< [2..2] Programming register for choosing GPIO in which DAC Output + is connected */ + __IOM unsigned int + RESERVED1 : 1; /*!< [3..3] Reserved */ + __IOM unsigned int + SDC_DAC_DATA : 10; /*!< [13..4] SDC Aux DAC Data */ + __IOM unsigned int SDC_DAC_CONFIG_EN : 1; /*!< [14..14] On Enabling this register, SDC DAC Configuration will + be Applied. */ + __IOM unsigned int + RESERVED2 : 17; /*!< [31..15] Reserevd */ + } SDC_AUXDAC_CONFIG_1_b; + }; + + union { + __IOM unsigned int + SDC_AUXLDO_CONFIG; /*!< (@ 0x00000020) SDC AUX LDO configuration */ + + struct { + __IOM unsigned int + SDC_AUXLDO_VOLT_CTRL : 4; /*!< [3..0] SDC AUX LDO Voltage Control Selection */ + __IOM unsigned int + RESERVED1 : 1; /*!< [4..4] RESERVED */ + __IOM unsigned int SDC_AUXLDO_BYP_EB : 1; /*!< [5..5] Configure AUXLDO in Buypass mode.When Enabled, Ouput + supply of LDO will be same as Input supply. */ + __IOM unsigned int + SDC_AUXLDO_EN : 1; /*!< [6..6] Turn-On AUX LDO */ + __IOM unsigned int + SDC_AUXLDO_CONFIG_EN : 1; /*!< [7..7] SDC Aux LDO Configuration Control Enable */ + __IOM unsigned int + RESERVED2 : 24; /*!< [31..8] Reserved */ + } SDC_AUXLDO_CONFIG_b; + }; + + union { + __IOM unsigned int + SDC_AUXOPAMP_CONFIG_1; /*!< (@ 0x00000024) SDC AUX OPAMP configuration 1 */ + + struct { + __IOM unsigned int SDC_OPAMP_EN_CH1 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-1 + Operation */ + __IOM unsigned int + SDC_OPAMP_LP_MODE : 1; /*!< [1..1] Configuration of OPAMP1 Operation mode */ + __IOM unsigned int + SDC_OPAMP_R1_SEL : 2; /*!< [3..2] Configuration for Resistor Ladder R1 of OPAMP1 for controlling + it gain. */ + __IOM unsigned int + SDC_OPAMP_R2_SEL : 3; /*!< [6..4] Configuration for Resistor Ladder R2 of OPAMP1 for controlling + it gain. */ + __IOM unsigned int SDC_OPAMP_RES_BACK_EN : 1; /*!< [7..7] Configuration register for controlling Resistor Bank + of OPAMP */ + __IOM unsigned int + SDC_OPAMP_RES_MUX_SEL : 3; /*!< [10..8] Configuration register for Connecting R1 Resistor Ladder + input */ + __IOM unsigned int + SDC_OPAMP_RES_TO_OUT_VDD : 1; /*!< [11..11] Configuration register for Connecting R2 Resistor Ladder + input */ + __IOM unsigned int + SDC_OPAMP_OUT_MUX_EN : 1; /*!< [12..12] Configur this register to OPAMP1 Output will be connected + to GPIO */ + __IOM unsigned int + SDC_OPAMP_IN_N_SEL : 3; /*!< [15..13] Configuration register for selecting N Input of OPAMP1. */ + __IOM unsigned int + SDC_OPAMP_IN_P_SEL_CH1 : 4; /*!< [19..16] Configuration register for selecting P Input of OPAMP1.,for + CH1 */ + __IOM unsigned int SDC_OPAMP_OUT_MUX_SEL : 1; /*!< [20..20] Configuration register for connecting OPAMP1 output + to GPIO */ + __IM unsigned int RESERVED1 : 1; /*!< [21..21] Reserved */ + __IOM unsigned int SDC_VREF_MUX_1_EN : 1; /*!< [22..22] Connect Low Drive Strength voltage reference for ULP + GPIO 1 For external use */ + __IOM unsigned int SDC_VREF_MUX_2_EN : 1; /*!< [23..23] Connect Low Drive Strength voltage reference for ULP + GPIO 3 For external use */ + __IOM unsigned int SDC_VREF_MUX_3_EN : 1; /*!< [24..24] Connect Low Drive Strength voltage reference for ULP + GPIO 4 For external use */ + __IOM unsigned int SDC_VREF_MUX_4_EN : 1; /*!< [25..25] Connect Low Drive Strength voltage reference for ULP + GPIO 15 For external use */ + __IOM unsigned int + RESERVED2 : 1; /*!< [26..26] Reserved */ + __IOM unsigned int SDC_VREF_MUX_1_SEL : 1; /*!< [27..27] Selection register for choosing Voltage reference to + external use on ULP_GPIO_1 */ + __IOM unsigned int SDC_VREF_MUX_2_SEL : 1; /*!< [28..28] Selection register for choosing Voltage reference to + external use on ULP_GPIO_3 */ + __IOM unsigned int SDC_VREF_MUX_3_SEL : 1; /*!< [29..29] Selection register for choosing Voltage reference to + external use on ULP_GPIO_4 */ + __IOM unsigned int SDC_VREF_MUX_4_SEL : 1; /*!< [30..30] Selection register for choosing Voltage reference to + external use on ULP_GPIO_15 */ + __IOM unsigned int SDC_OPAMP_CONFIG_EN : 1; /*!< [31..31] On Enabling this register, SDC OPAMP Configuration + will be Applied. */ + } SDC_AUXOPAMP_CONFIG_1_b; + }; + + union { + __IOM unsigned int + SDC_AUXADC_CONFIG_2; /*!< (@ 0x00000028) SDC AUX ADC configuration 2 */ + + struct { + __IOM unsigned int + SDC_AUXADC_INPUT_P_SEL_CH2 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-2 */ + __IOM unsigned int + SDC_AUXADC_INPUT_N_SEL_CH2 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-2 */ + __IOM unsigned int + SDC_AUXADC_DIFF_MODE_CH2 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ + __IOM unsigned int + RESERVED1 : 22; /*!< [31..10] Reserevd */ + } SDC_AUXADC_CONFIG_2_b; + }; + + union { + __IOM unsigned int + SDC_AUXADC_CONFIG_3; /*!< (@ 0x0000002C) SDC AUX ADC configuration 3 */ + + struct { + __IOM unsigned int + SDC_AUXADC_INPUT_P_SEL_CH3 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-3 */ + __IOM unsigned int + SDC_AUXADC_INPUT_N_SEL_CH3 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-3 */ + __IOM unsigned int + SDC_AUXADC_DIFF_MODE_CH3 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ + __IOM unsigned int + RESERVED1 : 22; /*!< [31..10] Reserved */ + } SDC_AUXADC_CONFIG_3_b; + }; + + union { + __IOM unsigned int + SDC_AUXADC_CONFIG_4; /*!< (@ 0x00000030) SDC AUX ADC configuration 4 */ + + struct { + __IOM unsigned int + SDC_AUXADC_INPUT_P_SEL_CH4 : 5; /*!< [4..0] AUXADC's Positive Input Mux Select for Channel-4 */ + __IOM unsigned int + SDC_AUXADC_INPUT_N_SEL_CH4 : 4; /*!< [8..5] AUXADC's Negative Input Mux Select for Channel-4 */ + __IOM unsigned int + SDC_AUXADC_DIFF_MODE_CH4 : 1; /*!< [9..9] 1-AUX ADC Differencial mode, 0 - Single Ended Mode */ + __IOM unsigned int + RESERVED1 : 22; /*!< [31..10] Reserved */ + } SDC_AUXADC_CONFIG_4_b; + }; + + union { + __IOM unsigned int + SDC_AUXOPAMP_CONFIG_2; /*!< (@ 0x00000034) SDC AUX OPAMP Configuration 2 */ + + struct { + __IOM unsigned int SDC_OPAMP_EN_CH2 : 1; /*!< [0..0] Enable signal for turning OPAMP to used for Channel-2 + Operation */ + __IOM unsigned int SDC_OPAMP_IN_P_SEL_CH2 : 4; /*!< [4..1] Configuration register for selecting P Input of OPAMP1 + for Channel-2 */ + __IOM unsigned int SDC_OPAMP_EN_CH3 : 1; /*!< [5..5] Enable signal for turning OPAMP to used for Channel-4 + Operation */ + __IOM unsigned int SDC_OPAMP_IN_P_SEL_CH3 : 4; /*!< [9..6] Configuration register for selecting P Input of OPAMP1 + for Channel-3 */ + __IOM unsigned int SDC_OPAMP_EN_CH4 : 1; /*!< [10..10] Enable signal for turning OPAMP to used for Channel-4 + Operation */ + __IOM unsigned int + SDC_OPAMP_IN_P_SEL_CH4 : 1; /*!< [11..11] Configuration register for selecting P Input of OPAMP1 + for Channel-4 */ + unsigned int : 3; + __IOM unsigned int + RESERVED1 : 17; /*!< [31..15] Reserved */ + } SDC_AUXOPAMP_CONFIG_2_b; + }; + __IOM SDC_SDC_DATA_REG_Type + SDC_DATA_REG[16]; /*!< (@ 0x00000038) SDC Data registers (0-15) */ +} SDC_Type; +/** @} End of group RSI_DEVICE_SYSRTC */ + +#include "si91x_mvp.h" + +#endif + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== + */ +/* ================ Device Specific Peripheral Address + * Map ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define I2C0_BASE 0x44010000UL +#define I2C1_BASE 0x47040000UL +#define I2C2_BASE 0x24040000UL +#define MCPWM_BASE 0x47070000UL +#define UDMA0_BASE 0x44030000UL +#define UDMA1_BASE 0x24078000UL +#define GPDMA_G_BASE 0x21080000UL +#define GPDMA_C_BASE 0x21081004UL +#define HWRNG_BASE 0x45090000UL +#define TIMERS_BASE 0x24042000UL +#define QEI_BASE 0x47060000UL +#define USART0_BASE 0x44000100UL +#define UART0_BASE 0x44000000UL +#define UART1_BASE 0x45020000UL +#define ULP_UART_BASE 0x24041800UL +#define GSPI0_BASE 0x45030000UL +#define SSI0_BASE 0x44020000UL +#define SSISlave_BASE 0x45010000UL +#define SSI2_BASE 0x24040800UL +#define SIO_BASE 0x47000000UL +#define QSPI_BASE 0x12000000UL +#define CRC_BASE 0x45080000UL +#define EFUSE_BASE 0x4600C000UL +#define I2S0_BASE 0x47050000UL +#define I2S1_BASE 0x24040400UL +#define IID_AES_BASE 0x20480500UL +#define IID_QK_BASE 0x20480600UL +#define IID_RPINE_BASE 0x20480400UL +#define CT0_BASE 0x45060000UL +#define CT1_BASE 0x45060100UL +#define CT2_BASE 0x45061000UL +#define CT3_BASE 0x45061100UL +#define CT_MUX_REG_BASE 0x4506F000UL +#define EGPIO_BASE 0x46130000UL +#define EGPIO1_BASE 0x2404C000UL +#define SDIO0_BASE 0x20200000UL +#define SPI_SLAVE_BASE 0x20200000UL +#define M4CLK_BASE 0x46000000UL +#define TIME_PERIOD_BASE 0x24048200UL +#define MCU_WDT_BASE 0x24048300UL +#define RTC_BASE 0x2404821CUL +#define BATT_FF_BASE 0x24048400UL +#define MCU_FSM_BASE 0x24048100UL +#define MCU_ProcessSensor_BASE 0x24048540UL +#define MCU_RET_BASE 0x24048600UL +#define MCU_TEMP_BASE 0x24048500UL +#define MCU_AON_BASE 0x24048000UL +#define ULPCLK_BASE 0x24041400UL +#define SDC_BASE 0x24042400UL + +#if defined(SLI_SI917B0) || defined(SLI_SI915) +#define SYSRTC_BASE 0x24048C00UL + +#define MVP_S_BASE (0x24000000UL) /* MVP_S base address */ +#define MVP_NS_BASE (0x24000000UL) /* MVP_NS base address */ + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) \ + || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S == 1))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif /* SL_TRUSTZONE_PERIPHERAL_MVP_S */ +#endif + +#if ((defined ENHANCED_FIM) && (defined INST_BUFF_ENABLE)) +/* Asign some random ULPSS memory when instruction buffer is enabled */ +#define FIM_BASE 0x24060100UL +#else +#define FIM_BASE 0x24070000UL +#endif +#define NWP_FSM_BASE 0x41300110UL +#define OPAMP_BASE 0x24043A14UL +#define AUX_ADC_DAC_COMP_BASE 0x24043800UL +#define IR_BASE 0x24040C00UL +#define CTS_BASE 0x24042C00UL +#define MISC_CONFIG_BASE 0x46008000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== + */ +/* ================ Peripheral declaration + * ================ */ +/* =========================================================================================================================== + */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define I2C0 ((I2C0_Type *)I2C0_BASE) +#define I2C1 ((I2C0_Type *)I2C1_BASE) +#define I2C2 ((I2C0_Type *)I2C2_BASE) +#define MCPWM ((MCPWM_Type *)MCPWM_BASE) +#define UDMA0 ((UDMA0_Type *)UDMA0_BASE) +#define UDMA1 ((UDMA0_Type *)UDMA1_BASE) +#define GPDMA_G ((GPDMA_G_Type *)GPDMA_G_BASE) +#define GPDMA_C ((GPDMA_C_Type *)GPDMA_C_BASE) +#define HWRNG ((HWRNG_Type *)HWRNG_BASE) +#define QEI ((QEI_Type *)QEI_BASE) +#define USART0 ((USART0_Type *)USART0_BASE) +#define UART0 ((USART0_Type *)UART0_BASE) +#define UART1 ((USART0_Type *)UART1_BASE) +#define ULP_UART ((USART0_Type *)ULP_UART_BASE) +#define GSPI0 ((GSPI0_Type *)GSPI0_BASE) +#define SSI0 ((SSI0_Type *)SSI0_BASE) +#define SSISlave ((SSI0_Type *)SSISlave_BASE) +#define SSI2 ((SSI0_Type *)SSI2_BASE) +#define SIO ((SIO_Type *)SIO_BASE) +#define QSPI ((QSPI_Type *)QSPI_BASE) +#define CRC ((CRC_Type *)CRC_BASE) +#define EFUSE ((EFUSE_Type *)EFUSE_BASE) +#define I2S0 ((I2S0_Type *)I2S0_BASE) +#define I2S1 ((I2S0_Type *)I2S1_BASE) +#define IID_AES ((IID_AES_Type *)IID_AES_BASE) +#define IID_QK ((IID_QK_Type *)IID_QK_BASE) +#define IID_RPINE ((IID_RPINE_Type *)IID_RPINE_BASE) +#define CT0 ((CT0_Type *)CT0_BASE) +#define CT1 ((CT0_Type *)CT1_BASE) +#define CT2 ((CT0_Type *)CT2_BASE) +#define CT3 ((CT0_Type *)CT3_BASE) +#define CT_MUX_REG ((CT_MUX_REG_Type *)CT_MUX_REG_BASE) +#define EGPIO ((EGPIO_Type *)EGPIO_BASE) +#define EGPIO1 ((EGPIO_Type *)EGPIO1_BASE) +#define SDIO0 ((SDIO0_Type *)SDIO0_BASE) +#define SPI_SLAVE ((SPI_SLAVE_Type *)SPI_SLAVE_BASE) +#define M4CLK ((M4CLK_Type *)M4CLK_BASE) +#define TIME_PERIOD ((TIME_PERIOD_Type *)TIME_PERIOD_BASE) +#define MCU_WDT ((MCU_WDT_Type *)MCU_WDT_BASE) +#define RTC ((RTC_Type *)RTC_BASE) +#define BATT_FF ((BATT_FF_Type *)BATT_FF_BASE) +#define MCU_FSM ((MCU_FSM_Type *)MCU_FSM_BASE) +#define MCU_ProcessSensor ((MCU_ProcessSensor_Type *)MCU_ProcessSensor_BASE) +#define MCU_RET ((MCU_RET_Type *)MCU_RET_BASE) +#define MCU_TEMP ((MCU_TEMP_Type *)MCU_TEMP_BASE) +#define MCU_AON ((MCU_AON_Type *)MCU_AON_BASE) +#define ULPCLK ((ULPCLK_Type *)ULPCLK_BASE) +#define FIM ((FIM_Type *)FIM_BASE) +#define NWP_FSM ((NWP_FSM_Type *)NWP_FSM_BASE) +#define OPAMP ((OPAMP_Type *)OPAMP_BASE) +#define AUX_ADC_DAC_COMP ((AUX_ADC_DAC_COMP_Type *)AUX_ADC_DAC_COMP_BASE) +#define IR ((IR_Type *)IR_BASE) +#define CTS ((CTS_Type *)CTS_BASE) +#define MISC_CONFIG ((MISC_CONFIG_Type *)MISC_CONFIG_BASE) +#define SDC ((SDC_Type *)SDC_BASE) +#define ULP_I2C I2C2 // Renaming I2C2 base address as ULP_I2C +#if defined(SLI_SI917B0) || defined(SLI_SI915) +#define SYSRTC0 ((SYSRTC_TypeDef *)SYSRTC_BASE) +#define MVP ((MVP_TypeDef *)MVP_BASE) /**< MVP base pointer */ +#endif +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous + * unions ========================================= */ +#if defined(__CC_ARM) +#pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined(__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) +#pragma warning restore +#elif defined(__CSMC__) +/* anonymous unions are enabled by default */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* RS1XXXX_H */ + +/** @} */ /* End of group RS1xxxx */ + +/** @} */ /* End of group Silicon Lab Inc. */ \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h new file mode 100644 index 000000000..3d3efa500 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/si91x_mvp.h @@ -0,0 +1,1604 @@ +/****************************************************************************** +* @file si91x_mvp.h +* @brief SI91X MVP register and bit field definitions + ****************************************************************************** +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#ifndef SI91X_MVP_H +#define SI91X_MVP_H +#define MVP_HAS_SET_CLEAR + +/******************************************************************************/ +/**************************************************************************/ /** + * @brief SI91X MVP Register Declaration. + *****************************************************************************/ + +/** MVP PERF Register Group Declaration. */ +typedef struct { + __IM uint32_t CNT; /**< Run Counter */ +} MVP_PERF_TypeDef; + +/** MVP ARRAYST Register Group Declaration. */ +typedef struct { + __IOM uint32_t INDEXSTATE; /**< Index State */ +} MVP_ARRAYST_TypeDef; + +/** MVP LOOPST Register Group Declaration. */ +typedef struct { + __IOM uint32_t STATE; /**< Loop State */ +} MVP_LOOPST_TypeDef; + +/** MVP ALU Register Group Declaration. */ +typedef struct { + __IOM uint32_t REGSTATE; /**< ALU Rn Register */ +} MVP_ALU_TypeDef; + +/** MVP ARRAY Register Group Declaration. */ +typedef struct { + __IOM uint32_t ADDRCFG; /**< Array Base Address */ + __IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */ + __IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */ + __IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */ +} MVP_ARRAY_TypeDef; + +/** MVP LOOP Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Loop Configuration */ + __IOM uint32_t RST; /**< Loop Reset */ +} MVP_LOOP_TypeDef; + +/** MVP INSTR Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */ + __IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */ + __IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */ +} MVP_INSTR_TypeDef; + +/** MVP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Configuration */ + __IM uint32_t STATUS; /**< Status */ + MVP_PERF_TypeDef PERF[2U]; /**< */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS; /**< Fault Status */ + __IM uint32_t FAULTADDR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST[8U]; /**< */ + MVP_ALU_TypeDef ALU[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY[5U]; /**< */ + MVP_LOOP_TypeDef LOOP[8U]; /**< */ + MVP_INSTR_TypeDef INSTR[8U]; /**< */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR; /**< Array Address State */ + __IM uint32_t LOAD1ADDR; /**< Array Address State */ + __IM uint32_t STOREADDR; /**< Array Address State */ + uint32_t RESERVED1[891U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IM uint32_t STATUS_SET; /**< Status */ + MVP_PERF_TypeDef PERF_SET[2U]; /**< */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_SET; /**< Fault Status */ + __IM uint32_t FAULTADDR_SET; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_SET; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */ + MVP_ALU_TypeDef ALU_SET[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR_SET; /**< Array Address State */ + __IM uint32_t LOAD1ADDR_SET; /**< Array Address State */ + __IM uint32_t STOREADDR_SET; /**< Array Address State */ + uint32_t RESERVED3[891U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IM uint32_t STATUS_CLR; /**< Status */ + MVP_PERF_TypeDef PERF_CLR[2U]; /**< */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */ + __IM uint32_t FAULTADDR_CLR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */ + MVP_ALU_TypeDef ALU_CLR[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR_CLR; /**< Array Address State */ + __IM uint32_t LOAD1ADDR_CLR; /**< Array Address State */ + __IM uint32_t STOREADDR_CLR; /**< Array Address State */ + uint32_t RESERVED5[891U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IM uint32_t STATUS_TGL; /**< Status */ + MVP_PERF_TypeDef PERF_TGL[2U]; /**< */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */ + __IM uint32_t FAULTADDR_TGL; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */ + MVP_ALU_TypeDef ALU_TGL[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */ + __IM uint32_t LOAD0ADDR_TGL; /**< Array Address State */ + __IM uint32_t LOAD1ADDR_TGL; /**< Array Address State */ + __IM uint32_t STOREADDR_TGL; /**< Array Address State */ +} MVP_TypeDef; +/** @} End of group SI91X_MVP */ + +/**************************************************************************/ /** + *****************************************************************************/ + +/* Bit fields for MVP IPVERSION */ +#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */ +#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */ +#define MVP_IPVERSION_IPVERSION_DEFAULT \ + (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */ + +/* Bit fields for MVP EN */ +#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */ +#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */ +#define MVP_EN_EN (0x1UL << 0) /**< Enable */ +#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */ +#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */ +#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */ +#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */ +#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */ + +/* Bit fields for MVP SWRST */ +#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */ +#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */ +#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */ +#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */ +#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */ +#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */ +#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING_DEFAULT \ + (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */ + +/* Bit fields for MVP CFG */ +#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */ +#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */ +#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */ +#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */ +#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT \ + (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */ +#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS_DEFAULT \ + (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */ +#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS_DEFAULT \ + (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_DEFAULT \ + (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_ALUACTIVE \ + (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_PIPESTALL \ + (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL \ + (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0STALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1STALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STORESTALL \ + (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_BUSSTALL \ + (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL \ + (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_DEFAULT \ + (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_ALUACTIVE \ + (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_PIPESTALL \ + (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL \ + (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0STALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1STALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STORESTALL \ + (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_BUSSTALL \ + (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL \ + (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ + +/* Bit fields for MVP STATUS */ +#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */ +#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */ +#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */ +#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_RUNNING_DEFAULT \ + (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */ +#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */ +#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */ +#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */ +#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */ + +/* Bit fields for MVP PERFCNT */ +#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */ +#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */ +#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */ +#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */ + +/* Bit fields for MVP IF */ +#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */ +#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */ +#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */ +#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */ +#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */ +#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */ +#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */ +#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */ +#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF_DEFAULT \ + (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */ +#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF_DEFAULT \ + (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF_DEFAULT \ + (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN_DEFAULT \ + (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */ +#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */ +#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT_DEFAULT \ + (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */ +#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT_DEFAULT \ + (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */ +#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */ +#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */ + +/* Bit fields for MVP IEN */ +#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */ +#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */ +#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */ +#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */ +#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */ +#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */ +#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */ +#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF_DEFAULT \ + (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF_DEFAULT \ + (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */ +#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF_DEFAULT \ + (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */ +#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN_DEFAULT \ + (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */ +#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */ +#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT_DEFAULT \ + (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */ +#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT_DEFAULT \ + (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */ +#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */ +#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT_DEFAULT \ + (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */ + +/* Bit fields for MVP FAULTSTATUS */ +#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTPC_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_NONE \ + (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM \ + (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM \ + (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM \ + (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/ +#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT \ + (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ + +/* Bit fields for MVP FAULTADDR */ +#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */ +#define MVP_FAULTADDR_FAULTADDR_DEFAULT \ + (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */ + +/* Bit fields for MVP PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */ +#define MVP_PROGRAMSTATE_PC_DEFAULT \ + (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */ + +/* Bit fields for MVP ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT \ + (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT \ + (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT \ + (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ + +/* Bit fields for MVP LOOPSTATE */ +#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */ +#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE_DEFAULT \ + (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_PCBEGIN_DEFAULT \ + (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ + +/* Bit fields for MVP ALUREGSTATE */ +#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FREAL_DEFAULT \ + (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FIMAG_DEFAULT \ + (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ + +/* Bit fields for MVP ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */ +#define MVP_ARRAYADDRCFG_BASE_DEFAULT \ + (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */ + +/* Bit fields for MVP ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT \ + (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT \ + (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 \ + (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 \ + (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 \ + (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT \ + (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR \ + (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX \ + (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT \ + (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ + +/* Bit fields for MVP ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT \ + (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT \ + (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ + +/* Bit fields for MVP ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT \ + (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT \ + (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ + +/* Bit fields for MVP LOOPCFG */ +#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_NUMITERS_DEFAULT \ + (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT \ + (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT \ + (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT \ + (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ + +/* Bit fields for MVP LOOPRST */ +#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */ +#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT \ + (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT \ + (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT \ + (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */ + +/* Bit fields for MVP INSTRCFG0 */ +#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT \ + (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT \ + (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ + +/* Bit fields for MVP INSTRCFG1 */ +#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT \ + (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT \ + (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ + +/* Bit fields for MVP INSTRCFG2 */ +#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT \ + (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END_DEFAULT \ + (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEFAULT \ + (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NRELU2 \ + (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RSQR2B \ + (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XREALC2 \ + (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XIMAGC2 \ + (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR2B \ + (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2A \ + (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2B \ + (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 \ + (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_PRELU2B \ + (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAXAC2 \ + (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MINAC2 \ + (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2A \ + (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2B \ + (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2A \ + (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2B \ + (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */ +#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG_DEFAULT \ + (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ + +/* Bit fields for MVP CMD */ +#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */ +#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */ +#define MVP_CMD_START (0x1UL << 0) /**< Start Command */ +#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */ +#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */ +#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */ +#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */ +#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */ +#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */ +#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */ +#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */ +#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */ +#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */ +#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */ +#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */ + +/* Bit fields for MVP DEBUGEN */ +#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */ +#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT \ + (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT \ + (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT \ + (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF_DEFAULT \ + (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF_DEFAULT \ + (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT \ + (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT \ + (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT \ + (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT \ + (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ + +/* Bit fields for MVP DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */ +#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT \ + (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */ + +/* Bit fields for MVP LOAD0ADDR */ +#define _MVP_LOAD0ADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_LOAD0ADDR */ +#define _MVP_LOAD0ADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_LOAD0ADDR */ +#define _MVP_LOAD0ADDR_ADDR_SHIFT 0 /**< Shift value for MVP_ADDR */ +#define _MVP_LOAD0ADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_ADDR */ +#define _MVP_LOAD0ADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOAD0ADDR */ +#define MVP_LOAD0ADDR_ADDR_DEFAULT \ + (_MVP_LOAD0ADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOAD0ADDR */ + +/* Bit fields for MVP LOAD1ADDR */ +#define _MVP_LOAD1ADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_LOAD1ADDR */ +#define _MVP_LOAD1ADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_LOAD1ADDR */ +#define _MVP_LOAD1ADDR_ADDR_SHIFT 0 /**< Shift value for MVP_ADDR */ +#define _MVP_LOAD1ADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_ADDR */ +#define _MVP_LOAD1ADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOAD1ADDR */ +#define MVP_LOAD1ADDR_ADDR_DEFAULT \ + (_MVP_LOAD1ADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOAD1ADDR */ + +/* Bit fields for MVP STOREADDR */ +#define _MVP_STOREADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_STOREADDR */ +#define _MVP_STOREADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_STOREADDR */ +#define _MVP_STOREADDR_ADDR_SHIFT 0 /**< Shift value for MVP_ADDR */ +#define _MVP_STOREADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_ADDR */ +#define _MVP_STOREADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STOREADDR */ +#define MVP_STOREADDR_ADDR_DEFAULT \ + (_MVP_STOREADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STOREADDR */ + +#endif /* SI91X_MVP_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h new file mode 100644 index 000000000..4b7bdbde0 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/inc/system_si91x.h @@ -0,0 +1,320 @@ +/****************************************************************************** +* @file system_si91x.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#include + +#ifndef __SYSTEM_ARMCM4_H__ +#define __SYSTEM_ARMCM4_H__ + +/** + * + */ +#include "rsi_error.h" +#include "rsi_ccp_user_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t npssIntrState; +extern uint32_t __sp; +extern uint32_t SiliconRev; +extern uint32_t package_type; + +void RSI_PS_ConfigureTaMemories(void); +/*WiSeAOC specific VTOR values*/ +#if defined(WISE_AOC_MODE) +#define VECTOR_OFF_SET_TA_ROM (0x100000 + 0x70100) /*Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#ifdef SLI_SI91X_MCU_INTERFACE +#include +#include "rsi_ipmu.h" +#include "rsi_system_config.h" +#define IPMU_DOTC_PROG +#define IPMU_CALIB_DATA +typedef uint16_t uint16; +typedef uint32_t uint32; +typedef int32_t int32; +typedef uint8_t uint8; +#define cmemcpy memcpy +#endif +#ifndef SLI_SI91X_MCU_INTERFACE +#include "data_types.h" +#include "defines.h" +#include "pm.h" +#include "soc_intf.h" +#include "lib_intf.h" +#include "gpio.h" +#include "timer.h" +#include "semaphore.h" +#include "error_code.h" +#include "common_intf.h" +#include "sleep_state.h" +#include "pll.h" +#include "pmu.h" +#include "misc_config.h" +#include "intr.h" +#include "bb_rf_prog_intf.h" +#include "bb_rf_prog.h" +#include "wlan_coex_intf.h" +#include "dev_ps.h" +#include "common_lmac.h" +#include "dbg.h" +#include "soft_timer.h" +#include "bb_rf_prog.h" +#include "dma.h" +#include "dynamic_clock.h" +#include "structures.h" +#include "ps.h" +#include "spi.h" +#include "hwrng.h" +#include "fmc.h" +#ifdef CHIP_9118 +#include "pwr_ctrl.h" +#endif +#include "rsi_global_non_rom.h" +#include "obe_low_pwr.h" +#include "common_ram.h" +#include "bb_rf_prog_ram.h" +#include "soc_address_map.h" +#include "ipmu_defines.h" +#include "no_host_intf.h" /* BT_DEV_MODE */ +#include "bt/bt.h" +#include "bt/bt_common.h" +#include "wakefi.h" +#include "cortex_m4.h" +#include "bb_rf_calib.h" +#include "wrappers_common.h" +#endif +void program_ipmu_data(const uint32_t *src); +#ifndef BT_LE_ONLY_MODE +#ifdef SLI_SI91X_MCU_INTERFACE +void ipmu_init_mcu(void); +#else +void ipmu_init_mcu(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void set_scdc(uint32 Deepsleep); +void ipmu_init_mcu(void) +{ +#ifdef IPMU_DOTC_PROG + program_ipmu_data(ipmu_common_config); //IPMU1 + program_ipmu_data(pmu_common_config); //PMU1 +#ifndef SLI_SI91X_MCU_INTERFACE + if (HF_RC_CLK_MODE == 0) { + program_ipmu_data(m20rc_osc_trim_efuse); //M20RC_EFUSE + } else if (HF_RC_CLK_MODE == 1) { + program_ipmu_data(m32rc_osc_trim_efuse); //M32RC_EFUSE + } + program_ipmu_data(dblr_32m_trim_efuse); //DBLR_EFUSE + program_ipmu_data(m20ro_osc_trim_efuse); //M20RO_EFUSE + program_ipmu_data(ro_32khz_trim_efuse); //RO32K_EFUSE + if (RC_CLK_MODE == 0) { + program_ipmu_data(rc_16khz_trim_efuse); //RC16K_EFUSE + } else if (RC_CLK_MODE == 1) { + program_ipmu_data(rc_32khz_trim_efuse); //RC32K_EFUSE + } else if (RC_CLK_MODE == 2) { + program_ipmu_data(rc_64khz_trim_efuse); //RC64K_EFUSE + } +#endif +#ifdef SLI_SI91X_MCU_INTERFACE + if (HF_RC_CLK_MODE == 0) { + /* program the trim value for 20Mhz RC oscillator */ + RSI_IPMU_M20rcOsc_TrimEfuse(); //M20RC_EFUSE + } else if (HF_RC_CLK_MODE == 1) { + /* program the trim value for 32Mhz RC oscillator */ + RSI_IPMU_M32rc_OscTrimEfuse(); //M32RC_EFUSE + } + /* program the trim value for RC 32MHz doubler */ + RSI_IPMU_DBLR32M_TrimEfuse(); //DBLR_EFUSE + /* program the trim value for 20MHz RC oscillator */ + RSI_IPMU_M20roOsc_TrimEfuse(); //M20RO_EFUSE + /* program the trim value for 32KHZ RO oscillator */ + RSI_IPMU_RO32khz_TrimEfuse(); //RO32K_EFUSE + if (RC_CLK_MODE == 0) { + /* program the trim value for 16KHz RC oscillator */ + RSI_IPMU_RC16khz_TrimEfuse(); //RC16K_EFUSE + } else if (RC_CLK_MODE == 1) { + /* program the trim value for 32KHz RC oscillator */ + RSI_IPMU_RC32khz_TrimEfuse(); //RC32K_EFUSE + } else if (RC_CLK_MODE == 2) { + /* program the trim value for 64KHz RC oscillator */ + RSI_IPMU_RC64khz_TrimEfuse(); //RC64K_EFUSE + } +#endif + program_ipmu_data(vbatt_status_trim_efuse); //VBATT_MON_EFUSE +#ifndef SLI_SI91X_MCU_INTERFACE + program_ipmu_data(ro_ts_efuse); //RO_TS_EFUSE + program_ipmu_data(vbg_tsbjt_efuse); //VBG_TS_EFUSE + program_ipmu_data(auxadc_off_diff_efuse); //AUXADC_DIFFOFF_EFUSE + program_ipmu_data(auxadc_gain_diff_efuse); //AUXADC_DIFFGAIN_EFUSE + program_ipmu_data(auxadc_off_se_efuse); //AUXADC_SEOFF_EFUSE + program_ipmu_data(auxadc_gain_se_efuse); //AUXADC_SEGAIN_EFUSE +#endif + program_ipmu_data(bg_trim_efuse); //bg_trim_efuse + program_ipmu_data(blackout_trim_efuse); //blackout_trim_efuse + program_ipmu_data(poc_bias_efuse); //poc_bias_efuse + program_ipmu_data(buck_trim_efuse); + program_ipmu_data(ldosoc_trim_efuse); + program_ipmu_data(dpwm_freq_trim_efuse); + program_ipmu_data(delvbe_tsbjt_efuse); + program_ipmu_data(xtal1_bias_efuse); +#ifdef SLI_SI91X_MCU_INTERFACE + program_ipmu_data(xtal2_bias_efuse); +#endif +#ifdef V1P20_IPMU_CHANGES + //http://192.168.1.215:8090/display/RS9116/Release+V1.19+Porting+Guide + //Retention-LDO Configuration + program_ipmu_data(retn_ldo_lpmode); //RETN1 + program_ipmu_data(retnLP_volt_trim_efuse); //RETNLP_TRIM_EFUSE +#ifdef SCDC_EXTCAP_MODE + program_ipmu_data(lp_scdc_extcapmode); //SCDC1 +#endif +#endif +#endif +} +#endif + +#ifdef IPMU_CALIB_DATA +/** + * @brief This function reads, modifies & writes to the iPMU registers based on different PMU SPI register type + * @param void + * @return void + */ +void update_ipmu_data(uint32_t reg_addr, uint32_t reg_type, uint32_t data, uint32_t mask) +{ + uint32_t value = 0; + + if (reg_type == ULP_SPI) { + value = PMU_DIRECT_ACCESS(reg_addr); + } else if (reg_type == PMU_SPI) { + value = PMU_SPI_DIRECT_ACCESS(reg_addr); + } else if (reg_type == DIRECT) { + value = *(volatile uint32_t *)(reg_addr); + } + value &= ~mask; + value |= data; + if (reg_type == ULP_SPI) { + PMU_DIRECT_ACCESS(reg_addr) = value; + } else if (reg_type == PMU_SPI) { + PMU_SPI_DIRECT_ACCESS(reg_addr) = value; + } else if (reg_type == DIRECT) { + *(volatile uint32_t *)(reg_addr) = value; + } +} +uint16 scdc_active; +uint16 scdc_sleep; +/** + * @brief This function prepares the data from the ipmu calib structure content and writes to each specific register + * @param void + * @return void + */ +void update_ipmu_calib_data(const efuse_ipmu_t *ipmu_calib_data) __attribute__((section(".common_tcm_code"))); +void update_ipmu_calib_data(const efuse_ipmu_t *ipmu_calib_data) +{ + uint32_t data; + uint32_t mask; + uint32 calibratedtrim_scdc; + uint32 calibratedtrim; +#ifndef SLI_SI91X_MCU_INTERFACE + common_info_ext_t *glbl_common_info_ext_p = (common_info_ext_t *)glbl_common_info.reserved_ptr; +#endif + //ROW 4,5,6 +#ifdef SLI_SI91X_MCU_INTERFACE + data = (ipmu_calib_data->trim_0p5na1 << 18); + mask = MASK_BITS(1, 18); +#else + data = (0 << 18) | (ipmu_calib_data->resbank_trim << 10); + mask = MASK_BITS(1, 18) | MASK_BITS(2, 10); +#endif + update_ipmu_data(iPMU_SPARE_REG1_OFFSET, ULP_SPI, data, mask); + + //ROW 5 + data = (ipmu_calib_data->bg_r_ptat_vdd_ulp << 19); + mask = MASK_BITS(3, 19); + if (ipmu_calib_data->set_vref1p3 == 0) { + data |= (2 << 10) | (2 << 7); + } else { + data |= (uint32_t)(ipmu_calib_data->scdc_dcdc_trim << 10) | (ipmu_calib_data->scdc_hpldo_trim << 7); + } + mask |= MASK_BITS(3, 10) | MASK_BITS(3, 7); + update_ipmu_data(BG_SCDC_PROG_REG_1_OFFSET, ULP_SPI, data, mask); + + scdc_active = (uint16)data; + + calibratedtrim = ((data >> 7) & 7); + calibratedtrim_scdc = ((data >> 10) & 7); +#ifdef DEEPSLEEP_SCDC_0P95 + if (calibratedtrim_scdc < 4) { + calibratedtrim_scdc = calibratedtrim_scdc + 2; + } else if (calibratedtrim_scdc == 4) { + calibratedtrim_scdc = calibratedtrim_scdc + 1; + } + if (calibratedtrim == 0) { + calibratedtrim = calibratedtrim + 3; + } else if (calibratedtrim == 1) { + calibratedtrim = calibratedtrim + 1; + } else if ((calibratedtrim == 2) || (calibratedtrim == 3)) { + calibratedtrim = calibratedtrim + 2; + } else if (calibratedtrim == 4) { + calibratedtrim = calibratedtrim + 1; + } +#else + if (calibratedtrim_scdc < 5) { + calibratedtrim_scdc = calibratedtrim_scdc + 1; + } + if (calibratedtrim == 0) { + calibratedtrim = calibratedtrim + 2; + } else if (calibratedtrim == 1) { + calibratedtrim = calibratedtrim - 1; + } else if ((calibratedtrim == 2) || (calibratedtrim == 3) || (calibratedtrim == 4)) { + calibratedtrim = calibratedtrim + 1; + } +#endif + scdc_sleep = (uint16)((calibratedtrim << 7) | (calibratedtrim_scdc << 10)); + //ROW 2 + data = ipmu_calib_data->bg_r_vdd_ulp; + mask = MASK_BITS(5, 0); + update_ipmu_data(BG_BLACKOUT_REG_OFFSET, ULP_SPI, data, mask); + + //ROW 7,17 + update_ipmu_data(ULPCLKS_MRC_CLK_REG_OFFSET, ULP_SPI, (ipmu_calib_data->trim_sel << 14), MASK_BITS(7, 14)); + + //ROW 9 + update_ipmu_data(ULPCLKS_DOUBLER_XTAL_REG_OFFSET, ULP_SPI, (ipmu_calib_data->del_2x_sel << 15), MASK_BITS(6, 15)); + + //ROW 10 + update_ipmu_data(ULPCLKS_32KRO_CLK_REG_OFFSET, + ULP_SPI, + (ipmu_calib_data->ro_32khz_00_trim << 16), + MASK_BITS(5, 16)); //rahul + + //ROW 11 + if (RC_CLK_MODE == 0) { + data = (ipmu_calib_data->fine_trim_16k << 14); + } else if (RC_CLK_MODE == 1) { + data = (ipmu_calib_data->fine_trim_32k << 14); + } else if (RC_CLK_MODE == 2) { + data = (ipmu_calib_data->fine_trim_64k << 14); + } + mask = MASK_BITS(7, 14); + update_ipmu_data(ULPCLKS_32KRC_CLK_REG_OFFSET, ULP_SPI, data, mask); + + //ROW 12 + if (XTAL_SEL == 1) { + data = ipmu_calib_data->xtal1_trim_32k << 13; + } else if (XTAL_SEL == 2) { + data = ipmu_calib_data->xtal2_trim_32k << 13; + } + update_ipmu_data(ULPCLKS_32KXTAL_CLK_REG_OFFSET, ULP_SPI, data, MASK_BITS(4, 13)); + + //ROW 13 + update_ipmu_data(ULPCLKS_HF_RO_CLK_REG_OFFSET, ULP_SPI, (ipmu_calib_data->trim_ring_osc << 14), MASK_BITS(7, 14)); + + //ROW 16 + data = (ipmu_calib_data->f2_nominal); + mask = MASK_BITS(10, 0); + update_ipmu_data((TEMP_SENSOR_BASE_ADDRESS + TS_NOMINAL_SETTINGS_OFFSET), DIRECT, data, mask); + + //ROW 18 + data = *(volatile uint32_t *)(ULP_TASS_MISC_CONFIG_REG + 0x34); + //! For AUX_LDO register access, need to enable ulp_aux_clock + *(volatile uint32_t *)(ULP_TASS_MISC_CONFIG_REG + 0x34) = 0x1; + update_ipmu_data((AUX_BASE_ADDR + 0x210), DIRECT, ipmu_calib_data->ldo_ctrl, MASK_BITS(4, 0)); + //! restore the reg + *(volatile uint32_t *)(ULP_TASS_MISC_CONFIG_REG + 0x34) = data; + + //ROW 34 + if (ipmu_calib_data->set_vref1p3 == 0) { + data = (0xC << 17); + } else { + data = (ipmu_calib_data->set_vref1p3 << 17); + } + mask = MASK_BITS(4, 17); + update_ipmu_data(PMU_1P3_CTRL_REG_OFFSET, PMU_SPI, data, mask); + + //ROW 38 + data = ipmu_calib_data->trim_r1_resistorladder; + mask = MASK_BITS(4, 0); + update_ipmu_data(SPARE_REG_3_OFFSET, PMU_SPI, data, mask); + + //ROW 48 + data = (ipmu_calib_data->dpwm_freq_trim) << 13; + mask = MASK_BITS(4, 13); + update_ipmu_data(PMU_ADC_REG_OFFSET, PMU_SPI, data, mask); + +#ifdef V1P20_IPMU_CHANGES + if (ipmu_calib_data->set_vref1p3 == 0) { + data = (0x2 << 18); + } else { + data = ((ipmu_calib_data->retn_ldo_lptrim) << 18); + } + mask = MASK_BITS(3, 18); + update_ipmu_data(BG_LDO_REG_OFFSET, ULP_SPI, data, mask); +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + glbl_common_info_ext_p->eeprom_calib_values.vbatt_status_trim_efuse = ipmu_calib_data->vbatt_status_1; +#endif +} +/** + * @brief This API is used to reduce or increase the SCDC voltage by 1 value + * @param Deepsleep : provide '1' before going to sleep.(i.e.Reduce the SCDC voltage by one value) + * provide '0' after wake up.(i.e.Set the SCDC voltage to the actual value) + * @return void + */ +void set_scdc(uint32 Deepsleep) +{ + uint32 mask; + + mask = MASK_BITS(3, 10) | MASK_BITS(3, 7); + update_ipmu_data(BG_SCDC_PROG_REG_1_OFFSET, ULP_SPI, Deepsleep ? scdc_sleep : scdc_active, mask); +} +/** + * @brief This function checks for magic byte in efuse/flash, copies the content if valid data present and calls to update the ipmu registers + * @param void + * @return void + */ +uint32_t init_ipmu_calib_data(uint32_t m4_present) +{ + (void)m4_present; + efuse_ipmu_t ipmu_calib_data; + efuse_ipmu_t *ipmu_calib_data_p; +#ifndef SLI_SI91X_MCU_INTERFACE + common_info_ext_t *glbl_common_info_ext_p; +#endif + ipmu_calib_data_p = &ipmu_calib_data; +#ifndef SLI_SI91X_MCU_INTERFACE + common_info_t *glbl_common_info_p = &glbl_common_info; + glbl_common_info_ext_p = (common_info_ext_t *)glbl_common_info_p->reserved_ptr; + + if ((*(uint8 *)(MANF_DATA_BASE_ADDR + BASE_OFFSET_BB_RF_IN_FLASH)) != MAGIC_WORD) { + //NO CALIB DATA. Return + return 1; + } +#endif + if (*(uint8 *)(MANF_DATA_BASE_ADDR + IPMU_VALUES_OFFSET) == 0x00) { + // NO CALIB DATA. Return + return 1; + } + if (*(uint8 *)(MANF_DATA_BASE_ADDR + IPMU_VALUES_OFFSET) == 0xFF) { + // NO CALIB DATA. Return + return 1; + } + memcpy(ipmu_calib_data_p, (efuse_ipmu_t *)(MANF_DATA_BASE_ADDR + IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); +#ifndef SLI_SI91X_MCU_INTERFACE + glbl_common_info_ext_p->auxadc_offset_single = ipmu_calib_data_p->auxadc_offset_single; + glbl_common_info_ext_p->vbg_tsbjt_efuse = ipmu_calib_data_p->vbg_tsbjt_efuse; + glbl_common_info_ext_p->str_bjt_temp_sense_off = ipmu_calib_data_p->str_bjt_temp_sense_off; + if (m4_present == 0) { +#endif + //Dummy read + PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); + + update_ipmu_calib_data(ipmu_calib_data_p); +#ifdef SLI_SI91X_MCU_INTERFACE + RSI_IPMU_UpdateIpmuCalibData_efuse(ipmu_calib_data_p); +#endif + //Dummy read + PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); +#ifndef SLI_SI91X_MCU_INTERFACE + } +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + //ROW 38 + update_ipmu_data((NWP_AHB_ADDR + 0x604), DIRECT, (ipmu_calib_data_p->scale_soc_ldo_vref << 31), MASK_BITS(1, 31)); +#endif + return 0; +} +#endif +#ifdef IPMU_DOTC_PROG +#ifdef SLI_SI91X_MCU_INTERFACE +void program_ipmu_data(const uint32_t *src); +#else +void program_ipmu_data(const uint32_t *src) __attribute__((section(".common_non_tcm_code"))); +#endif +void program_ipmu_data(const uint32_t *src) +{ + uint32_t write_data; + uint32_t num_of_reg; + uint32_t mask = 0; + uint32_t read_data; + uint32_t addr; + uint32_t ls_shift; + uint32_t ms_shift; + uint32_t mask_bits; + uint32_t inx = 0; + num_of_reg = src[inx]; + inx++; + + //Dummy Read + PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); + + while (num_of_reg--) { + addr = src[inx]; + //! 32bit Write data [31:27] ms shift and [26:22] ls shift and [21:0] data + write_data = src[inx + 1]; + //! extracting bit positions in which the data should be updated + ls_shift = (write_data >> LS_SHIFT) & 0x1F; + ms_shift = (write_data >> MS_SHIFT) & 0x1F; + //! Extracting 21-bit data from the structure + write_data = write_data & IPMU_DATAMASK; + read_data = *(uint32_t *)addr; + //! no of bits be updated + mask_bits = ms_shift - ls_shift + 1; + //! creating mask for the no of bits to be updated + while (mask_bits--) { + mask |= BIT(mask_bits); + } + //! resetting the bits in the read_data to update the data and writing the data to it + read_data &= ~(mask << ls_shift); + read_data |= (write_data & mask) << ls_shift; + *(uint32_t *)addr = read_data; + inx += 2; + mask = 0; + } +} +#endif +#ifdef SLI_SI91X_MCU_INTERFACE +void shut_down_non_wireless_mode_pds(void); +#else +// Power Domain Controls +void shut_down_non_wireless_mode_pds(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void shut_down_non_wireless_mode_pds(void) +{ + uint32_t reg_val = 0; + // WuRX + PMU_DIRECT_ACCESS(iPMU_SPARE_REG2_OFFSET) &= ~(wurx_lvl_shift_en); + PMU_DIRECT_ACCESS(iPMU_SPARE_REG2_OFFSET) &= ~(wurx_pg_en_1); + + PMU_DIRECT_ACCESS(ULPCLKS_REF_CLK_REG_OFFSET) &= ~pass_clk_40m_buffer_enable; + +#ifndef IPMU_DOTC_PROG + PMU_DIRECT_ACCESS(0x125) |= (BIT(2)); //! Added by Nagaraj + PMU_DIRECT_ACCESS(0x127) &= ~((BIT(3)) | BIT(4)); //! Added by Nagaraj +#else + program_ipmu_data(ana_perif_ptat_common_config2); + program_ipmu_data(ipmu_bod_clks_common_config2); +#endif + + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(cmp_npss_pg_enb | ulp_ang_clks_pg_enb | wurx_corr_pg_enb | wurx_pg_enb | auxadc_pg_enb | auxdac_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; +#ifndef SLI_SI91X_MCU_INTERFACE + // MHz RC + PMU_DIRECT_ACCESS(ULPCLKS_MRC_CLK_REG_OFFSET) &= ~rc_mhz_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_mhz_rc_clk_en; +#endif +#if 0 + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(wurx_corr_pg_enb | wurx_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; + + // BG-PMU_SPI + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(ulp_ang_pwrsupply_pg_enb | wurx_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; + + // Button-Wakeup + PMU_DIRECT_ACCESS(BOD_TEST_PG_VBATT_STATUS_REG_OFFSET) &= ~bod_pwrgate_en_n_ulp_button_calib; + + // Clk Calibration + PMU_DIRECT_ACCESS(ULPCLKS_TRIM_SEL_REG_OFFSET) &= ~calib_powergate_en; + + // Adaptive Calibration + PMU_DIRECT_ACCESS(ULPCLKS_ADAPTIVE_REG_OFFSET) &= ~adapt_powergate_en; + + // High Freq RO + PMU_DIRECT_ACCESS(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= ~ro_hf_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_20mhz_ring_osc_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_20mhz_ring_osc_clk_en; + + // 32KHz XTAL + PMU_DIRECT_ACCESS(ULPCLKS_32KXTAL_CLK_REG_OFFSET) &= ~xtal_32khz_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_32khz_xtal_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_32khz_xtal_clk_en; + + // 32MHz Doubler + PMU_DIRECT_ACCESS(ULPCLKS_DOUBLER_XTAL_REG_OFFSET) &= ~doubler_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_doubler_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_doubler_clk_en; + + // MHz RC + PMU_DIRECT_ACCESS(ULPCLKS_MRC_CLK_REG_OFFSET) &= ~rc_mhz_en; + MCU_FSM_DIRECT_ACCESS(MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP) &= ~mcu_ulp_mhz_rc_clk_en; + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_mhz_rc_clk_en; + + // Tempsense_RO + TS_ENABLE_AND_TEMPERATURE_DONE &= ~temp_sens_en; + + // Tempsense_BJT + //TEMP_SENSOR_BJT &= ~BIT(0); + + // Aux-ADC/Aux-DAC + reg_val = (PMU_DIRECT_ACCESS(POWERGATE_REG_READ_OFFSET) >> 5); + reg_val &= ~(auxadc_pg_enb | auxdac_pg_enb); + PMU_DIRECT_ACCESS(POWERGATE_REG_WRITE_OFFSET) = reg_val; +#endif +} +#ifdef SLI_SI91X_MCU_INTERFACE +void ipmu_init(void); +#else +void ipmu_init(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void ipmu_init(void) +{ +#ifndef SLI_SI91X_MCU_INTERFACE + //http://192.168.1.215:8090/display/IPMU40GF/Registers+Summary + uint32_t ipmu_calb_data_invalid = 1; +#endif +#ifndef IPMU_DOTC_PROG + uint32_t pmu_1p3_ctrl_data; +#endif + uint32_t pmu_1p2_ctrl_word; + uint32_t bypass_curr_ctrl_data; + const retention_boot_status_word_t *retention_reg = (const retention_boot_status_word_t *)MCURET_BOOTSTATUS; + + //! If M4 present and host interface with M4(M4 master) case, total IPMU and MCU FSM registers has to be initialised in M4. + //! Always NWP FSM registers has to be programmed here. + //! In WiSE MCU BLE only mode IPMU programming will be done in MCU + +#ifndef SLI_SI91X_MCU_INTERFACE +#ifndef BT_LE_ONLY_MODE + if (!retention_reg->m4_present) { + ipmu_init_mcu(); + } +#endif +#ifdef IPMU_CALIB_DATA + //! Read calib data from efuse/flash and update to iPMU registers + ipmu_calb_data_invalid = init_ipmu_calib_data(retention_reg->m4_present); +#endif +#else + ipmu_init_mcu(); + //! Read calib data from efuse/flash and update to iPMU registers + init_ipmu_calib_data(retention_reg->m4_present); +#endif + +#ifndef DISABLE_M4SS_SWITCH_OFF +#ifndef SLI_SI91X_MCU_INTERFACE + if (!retention_reg->m4_present) +#endif + { +#ifdef SLI_SI91X_MCU_INTERFACE + MCU_PMU_LDO_CTRL_CLEAR_REG_1 = +#else + MCU_PMU_LDO_CTRL_CLEAR = +#endif + (mcu_soc_ldo_lvl | mcu_dcdc_lvl); //Dynamic control of LDO-SoC and VOUTBCK o/p volt from NWP + MCU_FSM_PMU_CTRL |= standby_dc1p3; //Dynamic control of PFM Mode from NWP + MCU_FSM_DIRECT_ACCESS(MCU_FSM_PMU_STATUS_REG_OFFSET) |= (scdcdc_lp_mode_en); + MCU_FSM_DIRECT_ACCESS(MCU_FSM_PMU_STATUS_REG_OFFSET) |= (bgpmu_sleep_en); + +#ifdef IPMU_DOTC_PROG +#ifndef IPMU_POWER_ENHANCEMENT + //This is commented sothat retention ldo trim value BG_LDO_REG_OFFSET[20:18] is not over written + program_ipmu_data(retn_ldo_lpmode); +#endif +#else + PMU_DIRECT_ACCESS(0x129) |= (BIT(15) | BIT(16)); //! Added by Nagaraj + PMU_DIRECT_ACCESS(0x140) |= (BIT(15) | BIT(18) | BIT(19)); //! Added by Nagaraj +#endif + +#ifdef IPMU_DOTC_PROG +#if 0 + program_ipmu_data(lp_scdc_extcapmode); +#endif +#else + PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_2_OFFSET); + PMU_DIRECT_ACCESS(SCDC_CTRL_REG_0_OFFSET) = 0x3e002f; + PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_2_OFFSET) = 0x200020; + PMU_DIRECT_ACCESS(BG_LDO_REG_OFFSET) = 0x58000; +#endif + + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET) |= BIT(1); //! BG-PMU Clock configured to MCU_FSM_SLEEP_CLK +#ifndef SLI_SI91X_MCU_INTERFACE + shut_down_non_wireless_mode_pds(); +#endif +#ifdef SLI_SI91X_MCU_INTERFACE + MCUAON_GEN_CTRLS_REG &= ~NPSS_SUPPLY_0P9_BIT; //Dynamic switching of NPSS/iPMU supply during sleep + MCUAON_GEN_CTRLS_REG |= ENABLE_PDO_BIT; //Dynamic control of PADs PDO during sleep +#else + MCUAON_GEN_CTRLS_REG &= ~NPSS_SUPPLY_0P9; //Dynamic switching of NPSS/iPMU supply during sleep + MCUAON_GEN_CTRLS_REG |= ENABLE_PDO; //Dynamic control of PADs PDO during sleep +#endif +#ifndef IPMU_DOTC_PROG + PMU_SPI_DIRECT_ACCESS(PMU_LDO_REG_OFFSET) &= ~LDOSOC_DEFAULT_MODE_EN; //LDO-SoC o/p Volt is configurable from NPSS + PMU_SPI_DIRECT_ACCESS(PMU_PWRTRAIN_REG_OFFSET) |= BYPASS_LDORF_CTRL; //LDO-FLASH is configurable from NPSS + + if (ipmu_calb_data_invalid) { + PMU_SPI_DIRECT_ACCESS(0x1DA) = 0x2818; + PMU_SPI_DIRECT_ACCESS(0x1DD) = 0x26249A; + PMU_SPI_DIRECT_ACCESS(0x1D0) = 0x132241; + PMU_SPI_DIRECT_ACCESS(0x1D2) = 0xE80D7; + PMU_SPI_DIRECT_ACCESS(0x1D3) = 0x872B; + } + + // Setting VOUTBCK to 1.35V (Finally Done from Calibration Data in EFUSE) + pmu_1p3_ctrl_data = PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET); + pmu_1p3_ctrl_data &= ~(0xF << 17); + PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET) = (pmu_1p3_ctrl_data | (0xA << 17)); + //////////////////////////////////////////////////////////// +#endif + + // Setting VOUTBCK_LOW to 1.25V based on the data obtained from Calibration Data + bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET); + pmu_1p2_ctrl_word = ((bypass_curr_ctrl_data >> 17) & 0xF) - 2; + bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET); + bypass_curr_ctrl_data &= (uint32_t)(~(0xF << 5)); + PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET) = (bypass_curr_ctrl_data | (pmu_1p2_ctrl_word << 5)); + + PMU_DIRECT_ACCESS(BG_SLEEP_TIMER_REG_OFFSET) |= BIT(19); //bgs_active_timer_sel + //http://192.168.1.215:8090/display/RS9116/MCU+AON+Registers#MCUAONRegisters-MCUAON_SHELF_MODE + MCUAON_SHELF_MODE |= (7 << 19); //Programmable delay for resetting Chip + } +#endif + +#ifndef SLI_SI91X_MCU_INTERFACE + +#ifdef BGPMU_SAMPLING_EN + ULP_DIRECT_ACCESS(NWP_PMU_CTRLS) |= (scdcdc_lp_mode_en); + ULP_DIRECT_ACCESS(NWP_PMU_CTRLS) |= (bgpmu_sleep_en); //Disabling Brownout Detection. enable once issue is fixed. +#endif +#ifdef DCDC_STANDBY_MODE_EN + ULP_DIRECT_ACCESS(NWP_PMU_CTRLS) |= standby_dc1p3; +#endif + + //BIT(16) is added for smooth reset of bandgap in 1.4REV Silicon + ULP_DIRECT_ACCESS(NWPAON_POR_CTRL_BITS) |= (poc_cntrl_reg_0 | BIT(16)); + + //! RC MHz disable from NWP + ULP_DIRECT_ACCESS(NWP_FSM_FIRST_BOOTUP) &= ~nwp_ulp_mhz_rc_clk_en; + + TASS_FSM_CTRL_BYPASS &= ~ta_pmu_shut_down_bypass; + TASS_FSM_CTRL_BYPASS &= ~ta_pmu_shut_down_bypass_cntrl; + + TASS_FSM_CTRL_BYPASS |= ta_buck_boost_enable_bypass; +#endif +} +#ifdef SLI_SI91X_MCU_INTERFACE +void configure_uulp_gpio_to_1p8v(void); +#else +void configure_uulp_gpio_to_1p8v(void) __attribute__((section(".common_non_tcm_code"))); +#endif +void configure_uulp_gpio_to_1p8v(void) +{ + //! UULP GPIO to operate at 1.8v + //http://192.168.1.215:8090/display/IPMU40GF/Registers+Summary + PMU_DIRECT_ACCESS(iPMU_SPARE_REG1_OFFSET); //Dummy read + PMU_DIRECT_ACCESS(iPMU_SPARE_REG1_OFFSET) |= BIT(13); +} + +#ifdef SLI_SI91X_MCU_INTERFACE +void configure_ipmu_mode(uint32_t mode); +#else +void configure_ipmu_mode(uint32_t mode) __attribute__((section(".common_non_tcm_code"))); +#endif +void configure_ipmu_mode(uint32_t mode) +{ + if (mode) { + //program_ipmu_data(hpldo_volt_trim_efuse); //HPLDO_TRIM_EFUSE + program_ipmu_data(hpldo_tran); //SCDC3 + program_ipmu_data(buck_fast_transient_duty_1p8); //SCDC3 + program_ipmu_data(LDOFLASH_BYPASS); //keeping ldoflash in bypass mode in 1p8V supply mode; + } else { + //program_ipmu_data(scdc_volt_trim_efuse); //SCDC_TRIM_EFUSE + program_ipmu_data(ipmu_scdc_enable); //EXT CAP Mode + program_ipmu_data(lp_scdc_extcapmode); //EXT CAP Mode + } +} +#ifndef SLI_SI91X_MCU_INTERFACE +void disable_ipmu_write_access() __attribute__((section(".common_non_tcm_code"))); +void disable_ipmu_write_access() +{ + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET); + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET) &= + ~(latch_transparent_lf | latch_transparent_hf | latch_top_spi); //! Added by Nagaraj + PMU_DIRECT_ACCESS(SELECT_BG_CLK_OFFSET); +} +// temp sensor +uint16 adc_read_data_func() +{ + uint16 adc_data; + uint32_t dummy_read; + uint32_t adc_data_avg; + //uint16 fifo_data[16][32]; + uint32_t inxx2 = 0; + + adc_data_avg = 0; + + for (dummy_read = 0; dummy_read < 32; dummy_read++) { + while ((*(volatile uint32_t *)(0x24043830)) & BIT(2)) + ; + adc_data = ((*(volatile uint32_t *)(0x24043814)) & 0xFFF); + adc_data = BIT(11) ^ adc_data; + if (dummy_read > 15) { + adc_data_avg += adc_data; + } + //fifo_data[inxx2][dummy_read] = adc_data; + } + adc_data_avg /= 16; + inxx2 = (inxx2 + 1) & 15; + return adc_data_avg; +} + +uint32_t adccalibDone; +#define ULP_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(PMU_SPI_BASE_ADDR + (0xa000 + (REG_ADR * 4))))) +#define AUX_LDO *(volatile uint32_t *)(0x24043a10) +void calibrate_adc() +{ + uint32_t auxadcCalibValueLoad = 0, auxadcCalibValue = 0; + + if (adccalibDone == 0) { + ULP_SPI_MEM_MAP(0x110) |= BIT(11); + ULP_SPI_MEM_MAP(0x110) |= (BIT(12) | BIT(13) | BIT(8) | BIT(7) | BIT(6)); + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + while (!(ULP_SPI_MEM_MAP(0x1C1) & BIT(0))) + ; + while ((ULP_SPI_MEM_MAP(0x1C1) & BIT(0))) + ; + usleep(20); + auxadcCalibValue = ULP_SPI_MEM_MAP(0x112); + usleep(20); + auxadcCalibValueLoad |= BIT(0) | BIT(7); + auxadcCalibValueLoad |= (auxadcCalibValue & 0x1F) << 2; + auxadcCalibValueLoad |= (((auxadcCalibValue >> 6) & 0x1F) << 8); + auxadcCalibValueLoad |= (((auxadcCalibValue >> 11) & 0x1F) << 13); + adccalibDone = 1; + } + ULP_SPI_MEM_MAP(0x111) = (auxadcCalibValueLoad); + + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + + /* read calibrated p and n values */ + //calibrated_value = ULP_SPI_MEM_MAP(0x112); +} + +void get_ipmu_temperature(common_info_t *glbl_common_info_p) +{ + int32 adc_off; + int32 Vbg; + int32 Voffset; + uint32_t pmu_reg; + int32 irf_temperature; + int32 adc_bjt; + int32 adc_bg; + // int32 dbg_adc_bjt[32]; + // int32 dbg_adc_bg[32]; + // int16 temp[32]; + uint8 inxx = 0; + common_info_ext_t *glbl_common_info_ext_p = (common_info_ext_t *)glbl_common_info_p->reserved_ptr; + + if ((glbl_common_info_p->host_if == CORTEX_M4) || (!glbl_common_info_ext_p->chip_version_1p4_or_more)) { + irf_temperature = 70; + goto end_temp_measurement; + } + get_m4ss_access(); + *(volatile uint32_t *)(0x2405a000 + (0x142 * 4)); //dummy read + + //reg_val1 = PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_1_OFFSET); + + //PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_1_OFFSET) = reg_val1 | BIT(4); + + *(volatile uint32_t *)(0x2405a000 + (0x143 * 4)) = 0; + *(volatile uint32_t *)(0x2405a000 + (0x142 * 4)) = 0x1F910; + + ULPSS_PWRCTRL_SET_REG = ulpss_ext_pwrgate_en_n_ulp_AUX; + + ULP_DYN_CLK_CTRL_DISABLE |= BIT(11) | BIT(12) | BIT(13); + ULP_MISC_SOFT_SET_REG &= 0xfff8001f; + ULP_MISC_SOFT_SET_REG |= 0x0007ffe0; + ULP_AUXADC_CLK_GEN_REG = 0x1; + AUX_LDO = 0x7b; + + *(volatile uint32_t *)(0x2404380C) = 40; + + // wait for 50us + usleep(100); + + //*(uint32_t*)(0x2404C000 + 9 *(0x10))=(7<<2);//FIXME DELETE + + pmu_reg = ~0x1E & (*(volatile uint32_t *)(0x2405a000 + (0x129 * 4))); + *(volatile uint32_t *)(0x2405a000 + (0x129 * 4)) = pmu_reg | (8 << 1); + *(volatile uint32_t *)(0x24043a18) = 0x2e005; + + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + + *(volatile uint32_t *)(0x24043800 + 0x24) &= ~BIT(4); + *((volatile uint32_t *)(0x24043800 + (512 + 8))) = 0x00000C15; //OPAMP2 Channel21 + *((volatile uint32_t *)(0x24043800 + (78 * 4))) = 0x00000000; + *((volatile uint32_t *)(0x24043800 + (94 * 4))) = 0x00000001; + *((volatile uint32_t *)(0x24043800 + (119 * 4))) = 0x00000001; + *((volatile uint32_t *)(0x24043800 + (1 * 4))) = 0x8000C05; + + usleep(400); + calibrate_adc(); + + adc_bg = adc_read_data_func(); + + *((volatile uint32_t *)(0x24043800 + (1 * 4))) = 0x0; + *((volatile uint32_t *)(0x24043800 + (512 + 8))) = 0x15; + ////////////TS BJT ///////////////////////// + + TS_SLOPE_SET |= BIT(28); + VAD_BBP_ID |= BIT(16); + //To control ADC channel + ADC_CHANNEL = 0x002e0000; + //For ADC channel contro + ADC_CHANNEL_CNTRL = 0x00000000; + //Internal DMA disable and channel enable + DMA = 0x00000001; + + //Enbale temperature sensor + TEM = 0x00000001; + + //BJT TEMP TEST MUX + *(volatile uint32_t *)(0x2405a000 + (0x143 * 4)) = 0x3C0010; + *(volatile uint32_t *)(0x2405a000 + (0x140 * 4)) = 0x220; + while (*(volatile uint32_t *)(0x24050000 + 0x02) & BIT(8)) + ; + + *(volatile uint32_t *)(0x2404380C) = 20; + *(volatile uint32_t *)(0x24043800 + 0x24) &= ~BIT(4); + *((volatile uint32_t *)(0x24043800 + (512 + 8))) = 0x00000C17; + *((volatile uint32_t *)(0x24043800 + (1 * 4))) = 0x8000C05; + + adc_bjt = adc_read_data_func(); + + ADC_CHANNEL = 0x00000000; + ADC_CHANNEL; + /* turn off adc */ + *((volatile uint32_t *)(0x24043800 + (512 + 8))) &= ~((BIT(10) | BIT(11))); + *((volatile uint32_t *)(0x24043800 + (1 * 4))) &= ~BIT(0); + //PMU_DIRECT_ACCESS(BG_SCDC_PROG_REG_1_OFFSET) = reg_val1; + + adc_off = glbl_common_info_ext_p->auxadc_offset_single; + Vbg = glbl_common_info_ext_p->vbg_tsbjt_efuse; + Voffset = 961 - glbl_common_info_ext_p->str_bjt_temp_sense_off; + + //dbg_adc_bg[inxx] = adc_bg; + //dbg_adc_bjt[inxx] = adc_bjt; + irf_temperature = -268 + (310 * (((Vbg * (adc_bjt - adc_off)) / (adc_bg - adc_off)) + Voffset) / 1000) + 40; + + //temp[inxx] = irf_temperature -40; + if ((irf_temperature > 100) || (irf_temperature < 50)) { + //while(1); + } + if (inxx == 7) + while (1) + ; + inxx = (inxx + 1) & 31; + release_m4ss_access(); +end_temp_measurement: + glbl_common_info_ext_p->chip_temperature = irf_temperature; +} +#endif + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c new file mode 100644 index 000000000..d8d55ac15 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c @@ -0,0 +1,510 @@ +#ifdef SLI_SI91X_MCU_ENABLE_IPMU_APIS +/****************************************************************************** +* @file rsi_system_config_917.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#include +#include + +#ifdef ONEBOXE +#define _COMMON_IPMU_RAM_ __attribute__((section(".rodata .rodata."))); +#elif defined(SLI_SI91X_MCU_INTERFACE) +#define _COMMON_IPMU_RAM_ ; +#else +#define _COMMON_IPMU_RAM_ __attribute__((section(".common_tcm_rodata"))); +#endif + +uint32_t ipmu_common_config[] _COMMON_IPMU_RAM_ //IPMU1 + uint32_t ipmu_common_config[] = { + 9, 0x2405A49C, 0x49C00001, // ldo trim =1 for 1.15V in 9117 + 0x2405A4A4, 0x84000001, 0x2405A500, 0x9BC00019, 0x2405A494, + 0x10800001, 0x2405A414, 0x63000001, 0x2405A494, 0x8C000001, // active timer sel 9117 + 0x2405A494, 0xAD000002, // sleeptimer_sel 9117 + 0x2405A4AC, 0x29400000, // blackout disable 9117 + 0x2405A510, 0x29400001, // powergate_top_spi_disable - to keep ulp_analog_top spi always ON - 9117 + }; +uint32_t pmu_common_config[] _COMMON_IPMU_RAM_ //PMU1 + uint32_t pmu_common_config[] = { +#ifdef BUCK_UNDERSHOOT_DUTY_CYCLE_50 + 20, +#else + 19, +#endif + 0x24058740, 0xA440000C, 0x24058740, 0x600000BF, 0x24058748, 0x60000026, 0x24058748, 0x94400003, 0x2405874C, + 0x70000320, 0x24058768, 0x20C00003, 0x24058744, 0x9CC00001, 0x24058760, 0x10800001, 0x24058778, 0x41400007, + 0x24058758, 0x580000CC, //ldo soc set to 1.15V by default + 0x24058774, 0xA812249A, //9117 trim change,Buck Undershoot voltage of 20mV + 0x24058774, 0x41800003, 0x24058740, 0x83400008, 0x24058770, 0x7B000005, 0x24058770, 0x10000004, 0x24058774, + 0xAD000002, 0x24058770, 0x84000001, 0x2405877C, 0x8C400001, 0x24058738, 0x10800001, // 1CE 2nd BIT enabled +#ifdef BUCK_UNDERSHOOT_DUTY_CYCLE_50 + 0x24058774, 0x9C400003, //fast transient duty cycle changed to 50% +#endif + }; +uint32 pmu_pfm_mode[] _COMMON_IPMU_RAM_ //PMU2 + uint32 pmu_pfm_mode[] = { + 2, 0x24058754, 0x21000001, 0x24058744, 0x8C400001, + }; +uint32 pmu_pwm_mode[] _COMMON_IPMU_RAM_ //PMU2 + uint32 pmu_pwm_mode[] = { + 2, 0x24058754, 0x21000000, 0x24058744, 0x8C400000, + }; +uint32 buck_op_1p35[] _COMMON_IPMU_RAM_ //BUCK1 + uint32 buck_op_1p35[] = { + 1, + 0x24058740, + 0xA440000C, + }; +uint32 buck_op_1p2[] _COMMON_IPMU_RAM_ //BUCK1 + uint32 buck_op_1p2[] = { + 1, + 0x24058740, + 0xA4400009, + }; +uint32 pmu_LP_config[] _COMMON_IPMU_RAM_ //PMU2 + uint32 pmu_LP_config[] = { + 6, 0x24058774, 0x41800003, 0x24058748, 0x83400000, 0x24058740, 0x83400003, + 0x24058770, 0x7B000002, 0x24058770, 0x10000007, 0x24058774, 0xAD000002, // 9117 trim change,Buck Undershoot voltage of 20mV + }; +uint32 pmu_HP_config[] _COMMON_IPMU_RAM_ //PMU3 + uint32 pmu_HP_config[] = { + 5, 0x24058774, 0xA82224DA, 0x24058748, 0x83400000, 0x24058740, + 0x8340000C, 0x24058770, 0x7B00000C, 0x24058770, 0x10000004, + }; +uint32 pmu_socldo_0p95[] _COMMON_IPMU_RAM_ //PMU4 + uint32 pmu_socldo_0p95[] = { + 1, + 0x24058778, + 0x18000008, + }; +uint32 pmu_socldo_1p0[] _COMMON_IPMU_RAM_ //PMU5 + uint32 pmu_socldo_1p0[] = { + 1, + 0x24058778, + 0x18000009, + }; +uint32 ultrasleep_less_than_2V[] _COMMON_IPMU_RAM_ //PMU6 + uint32 ultrasleep_less_than_2V[] = { + 2, 0x24058760, 0xAC800003, 0x24058770, 0xAD400001, + }; +uint32_t buck_fast_transient_duty_1p8[] _COMMON_IPMU_RAM_ //PMU6 + uint32_t buck_fast_transient_duty_1p8[] = { + 3, 0x24058760, 0xAC800003, //pfm pon time set to max setting for 1p8V supply + 0x24058774, 0x9C400006, //fast transient duty cycle changed to 86% for 1p8V supply + 0x24058774, 0x5A400004, //increasing buck max duty cycle threshold from 92% to 95% to maintain output voltage at 1.71V supply and 250mA load condition + }; +uint32 LDOFLASH_BYPASS[] _COMMON_IPMU_RAM_ //PMU7 + uint32 LDOFLASH_BYPASS[] = { + 1, + 0x24058758, + 0x52800001, + }; +uint32 LDOSOC_BYPASS[] _COMMON_IPMU_RAM_ //PMU8 + uint32 LDOSOC_BYPASS[] = { + 2, 0x24058754, 0x39C00001, //set LDOSOC bypass + 0x24058758, 0x21000001, //set LDOSOC bypass, 2 reg programming needed + }; +uint32_t ipmu_scdc_enable[] _COMMON_IPMU_RAM_ //IPMU1_1 + uint32_t ipmu_scdc_enable[] = { + 2, 0x2405A498, 0xA83E002F, 0x2405A4A0, 0xA8200020, + }; +uint32 scdc_volt_sel1[] _COMMON_IPMU_RAM_ //SCDC0 + uint32 scdc_volt_sel1[] = { + 2, 0x2405A49C, 0x49C00002, // ldo trim =2 for 1.05V in 9117 + 0x2405A4A0, 0xAD400000, + }; +uint32 scdc_volt_sel2[] _COMMON_IPMU_RAM_ //SCDC0_1 + uint32 scdc_volt_sel2[] = { + 2, 0x2405A498, 0xA34000F0, 0x2405A4A0, 0xAD400001, + }; +uint32_t lp_scdc_extcapmode[] _COMMON_IPMU_RAM_ //SCDC1 + uint32_t lp_scdc_extcapmode[] = { + 5, 0x2405A4A0, 0xAD400000, 0x2405A49C, 0x62800002, // scdc trim = 2 ,trim change for 9117 + 0x2405A498, 0xA34000F8, 0x2405A4A0, 0x51800010, 0x2405A4A0, 0xAD400001, + }; +uint32 hp_ldo_voltsel[] _COMMON_IPMU_RAM_ //SCDC2 + uint32 hp_ldo_voltsel[] = { + 2, 0x2405A49C, 0x49C00000, 0x2405A4A0, 0xAD400000, + }; +uint32_t hpldo_tran[] _COMMON_IPMU_RAM_ //SCDC3 + uint32_t hpldo_tran[] = { + 1, + 0x2405A4A0, + 0xAD400000, + }; +uint32 SCDC_tran[] _COMMON_IPMU_RAM_ //SCDC4 + uint32 SCDC_tran[] = { + 3, 0x2405A498, 0xA34000F8, 0x2405A4A0, 0x51800010, 0x2405A4A0, 0xAD400001, + }; +uint32 retn_ldo_voltsel[] _COMMON_IPMU_RAM_ //RETN0 + uint32 retn_ldo_voltsel[] = { + 1, + 0x2405A4A4, + 0xA4800002, + }; +uint32 retn_ldo_0p75[] _COMMON_IPMU_RAM_ //RETN3 + uint32 retn_ldo_0p75[] = { + 1, + 0x2405A4A4, + 0xA4800001, + }; +uint32_t retn_ldo_lpmode[] _COMMON_IPMU_RAM_ //RETN1 + uint32_t retn_ldo_lpmode[] = { + 2, 0x2405A4A4, 0xA4800000, 0x2405A4A4, 0x84000001, + }; +uint32 retn_ldo_hpmode[] _COMMON_IPMU_RAM_ //RETN2 + uint32 retn_ldo_hpmode[] = { + 2, 0x2405A4A4, 0xA4800000, 0x2405A4A4, 0x84000000, + }; +uint32 poc_bias_current[] _COMMON_IPMU_RAM_ //POC1 + uint32 poc_bias_current[] = { + 1, + 0x2405A500, + 0x9C800000, + }; +uint32 poc_bias_current_11[] _COMMON_IPMU_RAM_ //POC2 + uint32 poc_bias_current_11[] = { + 1, + 0x2405A500, + 0x9C800003, + }; +uint32 ref_sel_pmu[] _COMMON_IPMU_RAM_ //BG_PMU_PFM + uint32 ref_sel_pmu[] = { + 1, + 0x2405A49C, + 0x10000000, + }; +uint32 bg_sleep_time[] _COMMON_IPMU_RAM_ //BG_SLEEP1 + uint32 bg_sleep_time[] = { + 2, 0x2405A494, 0x94000001, // active timer sel 9117 + 0x2405A494, 0xAD000002, // sleeptimer_sel 9117 + }; +uint32 ana_perif_ptat_common_config1[] _COMMON_IPMU_RAM_ //ANAPERIF_BIAS_EN + uint32 ana_perif_ptat_common_config1[] = { + 1, + 0x2405A49C, + 0x18C00001, + }; +uint32_t ana_perif_ptat_common_config2[] _COMMON_IPMU_RAM_ //ANAPERIF_BIAS_DIS + uint32_t ana_perif_ptat_common_config2[] = { + 1, + 0x2405A49C, + 0x18C00000, + }; +uint32 ipmu_bod_clks_common_config1[] _COMMON_IPMU_RAM_ //BOD_BIAS_EN + uint32 ipmu_bod_clks_common_config1[] = { + 1, + 0x2405A49C, + 0x21000001, + }; +uint32_t ipmu_bod_clks_common_config2[] _COMMON_IPMU_RAM_ //BOD_BIAS_DIS + uint32_t ipmu_bod_clks_common_config2[] = { + 1, + 0x2405A49C, + 0x21000000, + }; +uint32 xtal1_khz_fast_start_en[] _COMMON_IPMU_RAM_ //XTAL1_FS_EN + uint32 xtal1_khz_fast_start_en[] = { + 1, + 0x2405A438, + 0xA440000F, + }; +uint32 xtal1_khz_fast_start_disable[] _COMMON_IPMU_RAM_ //XTAL1_FS_DIS + uint32 xtal1_khz_fast_start_disable[] = { + 1, + 0x2405A438, + 0xA4400007, + }; +uint32 xtal2_khz_fast_start_en[] _COMMON_IPMU_RAM_ //XTAL2_FS_EN + uint32 xtal2_khz_fast_start_en[] = { + 1, + 0x2405A438, + 0xA440000F, + }; +uint32 xtal2_khz_fast_start_disable[] _COMMON_IPMU_RAM_ //XTAL2_FS_DIS + uint32 xtal2_khz_fast_start_disable[] = { + 1, + 0x2405A438, + 0xA4400007, + }; +uint32 button_wakeup_thresh[] _COMMON_IPMU_RAM_ //BOD_BUTTON + uint32 button_wakeup_thresh[] = { + 1, + 0x2405A400, + 0xA0830556, + }; +uint32 bod_cmp_hyst[] _COMMON_IPMU_RAM_ //BOD_CMP_HYST + uint32 bod_cmp_hyst[] = { + 1, + 0x2405A400, + 0x8000000, + }; +uint32 buck_op_ctrl[] _COMMON_IPMU_RAM_ //BUCK1 + uint32 buck_op_ctrl[] = { + 1, + 0x24058740, + 0xA440000C, + }; +uint32 ldosoc_op_ctrl[] _COMMON_IPMU_RAM_ //LDOSOC3 + uint32 ldosoc_op_ctrl[] = { + 1, + 0x24058758, + 0x2800000C, + }; +uint32 ldoflash_op_ctrl[] _COMMON_IPMU_RAM_ //LDORF3 + uint32 ldoflash_op_ctrl[] = { + 1, + 0x24058758, + 0x59800003, + }; +uint32 ro_tempsense_config[] _COMMON_IPMU_RAM_ //RO_TS_CONFIG + uint32 ro_tempsense_config[] = { + 1, + 0x2405A4D0, + 0x800000F2, + }; +uint32 bjt_tempsense_config[] _COMMON_IPMU_RAM_ //BJT_TS_CONFIG + uint32 bjt_tempsense_config[] = { + 1, + 0x2405A4D4, + 0x78000001, + }; + +uint32_t poc_bias_efuse[] _COMMON_IPMU_RAM_ //POC_BIAS_EFUSE + uint32_t poc_bias_efuse[] = { + 1, + 0x2405A500, + 0x9C800003, + }; +uint32_t bg_trim_efuse[] _COMMON_IPMU_RAM_ //BG_TRIM_EFUSE + uint32_t bg_trim_efuse[] = { + 2, 0x2405A49C, 0xACC00003, // BG_R_PTAT in 9117 + 0x2405A4AC, 0x20000010, // BG_R in 9117 + }; +uint32_t blackout_trim_efuse[] _COMMON_IPMU_RAM_ //POC3 + uint32_t blackout_trim_efuse[] = { + 1, + 0x2405A500, + 0x5A800000, + }; +uint32 m32rc_osc_trim_efuse[] _COMMON_IPMU_RAM_ //M32RC_EFUSE + uint32 m32rc_osc_trim_efuse[] = { + 1, + 0x2405A410, + 0xA380005A, + }; +uint32 m20rc_osc_trim_efuse[] _COMMON_IPMU_RAM_ //M20RC_EFUSE + uint32 m20rc_osc_trim_efuse[] = { + 1, + 0x2405A410, + 0xA3800038, + }; +uint32 dblr_32m_trim_efuse[] _COMMON_IPMU_RAM_ //DBLR_EFUSE + uint32 dblr_32m_trim_efuse[] = { + 1, + 0x2405A404, + 0xA3C00020, + }; +uint32 ro_32khz_trim_efuse[] _COMMON_IPMU_RAM_ //RO32K_EFUSE + uint32 ro_32khz_trim_efuse[] = { + 1, + 0x2405A408, + 0xA4000007, + }; +uint32 ro_32khz_trim00_efuse[] _COMMON_IPMU_RAM_ //RO32K_00_EFUSE + uint32 ro_32khz_trim00_efuse[] = { + 1, + 0x2405A408, + 0xA4000015, + }; +uint32 rc_16khz_trim_efuse[] _COMMON_IPMU_RAM_ //RC16K_EFUSE + uint32 rc_16khz_trim_efuse[] = { + 3, 0x2405A40C, 0xA380005A, // register bits changed in 9117 + 0x2405A40C, 0x10400000, 0x2405A40C, 0x00000000, + + }; +uint32 rc_64khz_trim_efuse[] _COMMON_IPMU_RAM_ //RC64K_EFUSE + uint32 rc_64khz_trim_efuse[] = { + 3, 0x2405A40C, 0xA380005A, // register bits changed in 9117 + 0x2405A40C, 0x10400003, 0x2405A40C, 0x00000000, + }; +uint32 rc_32khz_trim_efuse[] _COMMON_IPMU_RAM_ //RC32K_EFUSE + uint32 rc_32khz_trim_efuse[] = { + 3, 0x2405A40C, 0xA380005A, // register bits changed in 9117 + 0x2405A40C, 0x10400002, 0x2405A40C, 0x00000000, + }; +uint32_t xtal1_bias_efuse[] _COMMON_IPMU_RAM_ //XTAL1_BIAS_EFUSE + uint32_t xtal1_bias_efuse[] = { + 1, + 0x2405A438, + 0x83400003, + }; +uint32_t xtal2_bias_efuse[] _COMMON_IPMU_RAM_ //XTAL2_BIAS_EFUSE + uint32_t xtal2_bias_efuse[] = { + 1, + 0x2405A438, + 0x83400003, + }; +uint32 m20ro_osc_trim_efuse[] _COMMON_IPMU_RAM_ //M20RO_EFUSE + uint32 m20ro_osc_trim_efuse[] = { + 1, + 0x2405A414, + 0xA3800027, + }; +uint32_t vbatt_status_trim_efuse[] _COMMON_IPMU_RAM_ //VBATT_MON_EFUSE + uint32_t vbatt_status_trim_efuse[] = { + 1, + 0x2405A438, + 0x28000000, + }; +uint32 ro_ts_efuse[] _COMMON_IPMU_RAM_ //RO_TS_EFUSE + uint32 ro_ts_efuse[] = { + 1, + 0x2405A4D8, + 0x4800010E, + }; +uint32 vbg_tsbjt_efuse[] _COMMON_IPMU_RAM_ //VBG_TS_EFUSE + uint32 vbg_tsbjt_efuse[] = { + 1, + 0x2405A4DC, + 0x580004BF, + }; +uint32_t delvbe_tsbjt_efuse[] _COMMON_IPMU_RAM_ //DELVBE_TS_EFUSE + uint32_t delvbe_tsbjt_efuse[] = { + 1, + 0x2405A4E0, + 0x500003D9, + }; +uint32 auxadc_off_diff_efuse[] _COMMON_IPMU_RAM_ //AUXADC_DIFFOFF_EFUSE + uint32 auxadc_off_diff_efuse[] = { + 1, + 0x2405A4C0, + 0x58000064, + }; +uint32 auxadc_gain_diff_efuse[] _COMMON_IPMU_RAM_ //AUXADC_DIFFGAIN_EFUSE + uint32 auxadc_gain_diff_efuse[] = { + 1, + 0x2405A4C4, + 0x78008000, + }; +uint32 auxadc_off_se_efuse[] _COMMON_IPMU_RAM_ //AUXADC_SEOFF_EFUSE + uint32 auxadc_off_se_efuse[] = { + 1, + 0x2405A4C8, + 0x58000064, + }; +uint32 auxadc_gain_se_efuse[] _COMMON_IPMU_RAM_ //AUXADC_SEGAIN_EFUSE + uint32 auxadc_gain_se_efuse[] = { + 1, + 0x2405A4CC, + 0x78008000, + }; +uint32_t buck_trim_efuse[] _COMMON_IPMU_RAM_ //BUCK_TRIM_EFUSE + uint32_t buck_trim_efuse[] = { + 1, + 0x24058740, + 0xA440000C, + }; +uint32_t ldosoc_trim_efuse[] _COMMON_IPMU_RAM_ //LDOSOC_TRIM_EFUSE + uint32_t ldosoc_trim_efuse[] = { + 1, + 0x2405877C, + 0x18000000, + }; +uint32_t dpwm_freq_trim_efuse[] _COMMON_IPMU_RAM_ //DPWM_FREQ_TRIM_EFUSE + uint32_t dpwm_freq_trim_efuse[] = { + 1, + 0x24058748, + 0x83400000, + }; +uint32 scdc_volt_trim_efuse[] _COMMON_IPMU_RAM_ //SCDC_TRIM_EFUSE + uint32 scdc_volt_trim_efuse[] = { + 1, + 0x2405A49C, + 0x62800000, + }; +uint32 hpldo_volt_trim_efuse[] _COMMON_IPMU_RAM_ //HPLDO_TRIM_EFUSE + uint32 hpldo_volt_trim_efuse[] = { + 1, + 0x2405A49C, + 0x49C00001, // in 9117, trim for max voltage is 1 + }; +uint32 retnHP_volt_trim_efuse[] _COMMON_IPMU_RAM_ //RETNHP_TRIM_EFUSE + uint32 retnHP_volt_trim_efuse[] = { + 1, + 0x2405A4A4, + 0xA4800000, + }; +uint32 retnLP_volt_trim_efuse[] _COMMON_IPMU_RAM_ //RETNLP_TRIM_EFUSE + uint32 retnLP_volt_trim_efuse[] = { + 1, + 0x2405A4A4, + 0xA4800000, + }; +uint32 scdc_volt_trim_bump_efuse[] _COMMON_IPMU_RAM_ //SCDC_TRIM_BUMP_EFUSE + uint32 scdc_volt_trim_bump_efuse[] = { + 1, + 0x2405A49C, + 0x62800000, + }; +uint32 hpldo_volt_trim_bump_efuse[] _COMMON_IPMU_RAM_ //HPLDO_TRIM_BUMP_EFUSE + uint32 hpldo_volt_trim_bump_efuse[] = { + 1, + 0x2405A49C, + 0x49C00001, // in 9117, trim for max voltage is 1 + }; +uint32 scdc_freq_efuse[] _COMMON_IPMU_RAM_ //SCDC_FREQ_EFUSE + uint32 scdc_freq_efuse[] = { + 1, + 0x2405A4C4, + 0x2000001F, + }; +uint32 scdc_freqtrim_efuse[] _COMMON_IPMU_RAM_ // SCDC_FREQTRIM_EFUSE + uint32 scdc_freqtrim_efuse[] = { + 1, + 0x2405A504, + 0x20C00000, + }; +uint32 blackout_enable[] _COMMON_IPMU_RAM_ //IPMU1 + uint32 blackout_enable[] = { + 1, + 0x2405A4AC, + 0x29400001, // blackout enable 9117 + }; +uint32 blackout_disable[] _COMMON_IPMU_RAM_ //IPMU1 + uint32 blackout_disable[] = { + 1, + 0x2405A4AC, + 0x29400000, // blackout disable 9117 + }; +uint32 dblr_input_sel[] _COMMON_IPMU_RAM_ //IPMU1 + uint32 dblr_input_sel[] = { + 1, + 0x2405A404, + 0x42000000, // doubler inp clk sel - 9117 + }; +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c new file mode 100644 index 000000000..a037ffd15 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c @@ -0,0 +1,697 @@ +/****************************************************************************** +* @file rsi_deepsleep_soc.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/** + * Includes + */ +#include "rsi_ccp_common.h" +#include "rsi_power_save.h" +#include "rsi_temp_sensor.h" +#include "rsi_retention.h" +#ifdef DEBUG_UART +#include "rsi_debug.h" +#endif + +void fpuInit(void); +#define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR_1 (*(volatile uint32_t *)(0x41300000 + 0x4)) +#define NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 (*(volatile uint32_t *)(0x41300000 + 0x0)) +#define M4SS_TASS_CTRL_SET_REG (*(volatile uint32_t *)(0x24048400 + 0x34)) +#define M4SS_TASS_CTRL_CLEAR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) +#define M4SS_TASS_CTRL_CLR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) +#define MAX_NVIC_REGS 3 // Max Interrupts register +#define MAX_IPS 240 // Max Interrupt Priority registers +#define MAX_SHP 12 // Max System Handlers Priority registers +#define NPSS_GPIO_CLR_VALUE 0x3E // NPSS GPIO rising edge interrupt clear value + +#ifdef SLI_SI91X_MCU_4MB_LITE_IMAGE +#define MBR_MAGIC_WORD (*(volatile uint32_t *)(0x8160000)) +#else +#define MBR_MAGIC_WORD (*(volatile uint32_t *)(0x81F0000)) +#endif + +#define SL_SCDC_SLEEP 1 +#define SL_SCDC_ACTIVE 0 + +/* MACRO definition for External LDO Handle, the user must provide the definition for External LDO ON/OFF Handle*/ +#ifndef EXTERNAL_LDO_HANDLE +/*If User Handle definition is not available keep a Null Definition*/ +#define EXTERNAL_LDO_HANDLE +#endif + +extern void set_scdc(uint32_t Deepsleep); + +#ifdef SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE +#include "sl_si91x_psram_config.h" +#endif + +uint32_t nvic_enable[MAX_NVIC_REGS] = { 0 }; +uint8_t nvic_ip_reg[MAX_IPS] = { 0 }; +uint8_t scs_shp_reg[MAX_SHP] = { 0 }; +volatile uint32_t msp_value; +volatile uint32_t psp_value; +volatile uint32_t control_reg_val; +uint32_t npss_gpio_config = 0; + +#if defined(SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION) +extern char ram_vector[SI91X_VECTOR_TABLE_ENTRIES]; +#endif + +/** + * @fn void RSI_Save_Context(void) + * @brief This function is to save Stack pointer value and Control registers. + * + */ +void RSI_Save_Context(void) +{ + msp_value = __get_MSP(); + psp_value = __get_PSP(); + control_reg_val = __get_CONTROL(); +} +/** + * @fn void RSI_Restore_Context(void) + * @brief This function is to Restore Stack pointer value and Control registers. + * + */ +#ifdef SLI_SI91X_ENABLE_OS +STATIC INLINE void RSI_Restore_Context(void) +{ + __set_CONTROL(control_reg_val); + __set_PSP(psp_value); + __set_MSP(msp_value); +} +#endif +#if defined(__CC_ARM) /*------------------ARM CC Compiler -----------------*/ +/** + * @fn __asm void RSI_PS_SaveCpuContext(void) + * @brief This API is used to save the CPU status register into RAM, this API should be used when sleep with RET is required + * @return none + */ +__asm void RSI_PS_SaveCpuContext(void) +{ + IMPORT __sp; + PUSH{ r0 }; + PUSH{ r1 }; + PUSH{ r2 }; + PUSH{ r3 }; + PUSH{ r4 }; + PUSH{ r5 }; + PUSH{ r6 }; + PUSH{ r7 }; + PUSH{ r8 }; + PUSH{ r9 }; + PUSH{ r10 }; + PUSH{ r11 }; + PUSH{ r12 }; + PUSH{ r14 }; + LDR r0, = __sp; + MRS r1, msp; + STR r1, [r0]; + WFI; +} + +/** + * @fn void RSI_PS_RestoreCpuContext(void) + * @brief This API is used to restore the current CPU processing content from (POP) stack + * @return none + */ +__asm void RSI_PS_RestoreCpuContext(void) +{ + IMPORT __sp; + LDR r0, = __sp; + LDR sp, [r0, #0]; + POP{ r14 }; + POP{ r12 }; + POP{ r11 }; + POP{ r10 }; + POP{ r9 }; + POP{ r8 }; + POP{ r7 }; + POP{ r6 }; + POP{ r5 }; + POP{ r4 }; + POP{ r3 }; + POP{ r2 }; + POP{ r1 }; + POP{ r0 }; + BX LR; +} +#endif /*------------------ARM CC Compiler -----------------*/ + +#if defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ + +/** + * @fn void RSI_PS_SaveCpuContext(void) + * @brief This API is used to save the CPU status register into RAM, this API should be used when sleep with RET is required + * @return none + */ +void RSI_PS_SaveCpuContext(void) +{ + __asm("push {r0}"); + __asm("push {r1}"); + __asm("push {r2}"); + __asm("push {r3}"); + __asm("push {r4}"); + __asm("push {r5}"); + __asm("push {r6}"); + __asm("push {r7}"); + __asm("push {r8}"); + __asm("push {r9}"); + __asm("push {r10}"); + __asm("push {r11}"); + __asm("push {r12}"); + __asm("push {r14}"); + + /*R13 Stack pointer */ + __asm("mov %0, sp\n\t" : "=r"(__sp)); + __asm("WFI"); +} + +/** + * @fn void RSI_PS_RestoreCpuContext(void) + * @brief This API is used to restore the current CPU processing content from (POP) stack + * @return none + */ +void RSI_PS_RestoreCpuContext(void) +{ + __asm("ldr r0 , =__sp"); + __asm("ldr sp , [r0 , #0]"); + __asm("pop {r14}"); + __asm("pop {r12}"); + __asm("pop {r11}"); + __asm("pop {r10}"); + __asm("pop {r9}"); + __asm("pop {r8}"); + __asm("pop {r7}"); + __asm("pop {r6}"); + __asm("pop {r5}"); + __asm("pop {r4}"); + __asm("pop {r3}"); + __asm("pop {r2}"); + __asm("pop {r1}"); + __asm("pop {r0}"); +} +#endif /*------------------ GNU Compiler ---------------------*/ + +#if defined(__ICCARM__) /*------------------ IAR Compiler ---------------------*/ +/** + * @fn void RSI_PS_SaveCpuContext(void) + * @brief This API is used to save the CPU status register into RAM, this API should be used when sleep with RET is required + * @return none + */ +void RSI_PS_SaveCpuContext(void) +{ + __asm("push {r0}"); + __asm("push {r1}"); + __asm("push {r2}"); + __asm("push {r3}"); + __asm("push {r4}"); + __asm("push {r5}"); + __asm("push {r6}"); + __asm("push {r7}"); + __asm("push {r8}"); + __asm("push {r9}"); + __asm("push {r10}"); + __asm("push {r11}"); + __asm("push {r12}"); + __asm("push {r14}"); + + /*R13 Stack pointer */ + __asm("mov %0, sp\n\t" : "=r"(__sp)); + __asm("WFI"); +} + +/** + * @fn void RSI_PS_RestoreCpuContext(void) + * @brief This API is used to restore the current CPU processing content from (POP) stack + * @return none + */ +void RSI_PS_RestoreCpuContext(void) +{ + __asm("ldr r0 , =__sp"); + __asm("ldr sp , [r0 , #0]"); + __asm("pop {r14}"); + __asm("pop {r12}"); + __asm("pop {r11}"); + __asm("pop {r10}"); + __asm("pop {r9}"); + __asm("pop {r8}"); + __asm("pop {r7}"); + __asm("pop {r6}"); + __asm("pop {r5}"); + __asm("pop {r4}"); + __asm("pop {r3}"); + __asm("pop {r2}"); + __asm("pop {r1}"); + __asm("pop {r0}"); +} +#endif /*------------------ IAR Compiler ---------------------*/ + +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE +/** + * @fn void RSI_Set_Cntrls_To_M4(void) + * @brief This API is used to set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl, AON domain power supply controls + * from NWP to M4 + * + * + * @return none + */ +void RSI_Set_Cntrls_To_M4(void) +{ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + //!take TASS ref clock control to M4 + MCUAON_CONTROL_REG4 &= ~(MCU_TASS_REF_CLK_SEL_MUX_CTRL); +#else + /* m4ss_ref_clk_mux_ctrl and tass_ref_clk_mux_ctr in M4 Control */ + NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR_1 = (M4SS_REF_CLK_MUX_CTRL | TASS_REF_CLK_MUX_CTRL); +#endif + /* M4SS controlling Power supply for TASS AON domain */ + BATT_FF->M4SS_TASS_CTRL_SET_REG_b.M4SS_CTRL_TASS_AON_PWRGATE_EN = ENABLE; + /* M4SS controlling Power supply for TASS AON domains isolation enable in bypass mode*/ + BATT_FF->M4SS_TASS_CTRL_SET_REG_b.M4SS_CTRL_TASS_AON_DISABLE_ISOLATION_BYPASS = ENABLE; + /* M4SS controlling Power supply for TASS AON domains reset pin in bypass mode. */ + M4SS_TASS_CTRL_CLR_REG = M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS_BIT; + for (volatile uint8_t delay = 0; delay < 10; delay++) { + __ASM("NOP"); + } +} +/** + * @fn void RSI_Set_Cntrls_To_TA(void) + * @brief This API is used to set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl ,AON domain power supply controls + * from M4 to NWP + * + * + * @return none + */ +void RSI_Set_Cntrls_To_TA(void) +{ + /* tass_ref_clk_mux_ctr in NWP Control */ + NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 = TASS_REF_CLK_MUX_CTRL; +} +#endif + +/** + * @fn rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType , uint8_t lf_clk_mode) + * @brief This is the common API to keep the system in sleep state. from all possible active states. + * @param[in] sleepType : selects the retention or non retention mode of processor. refer 'SLEEP_TYPE_T'. + * SLEEP_WITH_RETENTION : When this is used, user must configure the which RAMs to be retained during sleep by using the 'RSI_PS_SetRamRetention()' function. + * @param[in] lf_clk_mode : This parameter is used to switch the processor clock from high frequency clock to low-frequency clock. This is used in some critical power save cases. + * 0: 'DISABLE_LF_MODE' Normal mode of operation , recommended in most of the applications. + * 1: 'LF_32_KHZ_RC' Processor clock is configured to low-frequency RC clock + * 2: 'LF_32_KHZ_XTAL' Processor clock is configured to low-frequency XTAL clock + * 3: 'EXTERNAL_CAP_MODE' Switches the supply to internal cap mode 0.95V. + * @par note + \n User must ensure the selected clocks are active before selecting the 'LF_32_KHZ_RC' and 'LF_32_KHZ_XTAL' clocks to the processor using this API. + * @return Returns the execution status. + */ +rsi_error_t RSI_PS_EnterDeepSleep(SLEEP_TYPE_T sleepType, uint8_t lf_clk_mode) +{ + volatile int var = 0; + volatile int enable_sdcss_based_wakeup = 0; + volatile int enable_m4ulp_retention = 0; + volatile int Temp; + + volatile uint8_t in_ps2_state = 0; + + uint32_t ipmuDummyRead = 0; + uint32_t m4ulp_ram_core_status = 0; + uint32_t m4ulp_ram_peri_status = 0; + uint32_t disable_pads_ctrl = 0; + uint32_t ulp_proc_clk = 0; + sl_p2p_intr_status_bkp_t p2p_intr_status_bkp; + + /*Save the NVIC registers */ + for (var = 0; var < MAX_NVIC_REGS; ++var) { + nvic_enable[var] = NVIC->ISER[var]; + } + /* Save the Interrupt Priority Register */ + for (var = 0; var < MAX_IPS; ++var) { + nvic_ip_reg[var] = NVIC->IP[var]; + } + /* Save the System Handlers Priority Registers */ + for (var = 0; var < MAX_SHP; ++var) { + scs_shp_reg[var] = SCB->SHP[var]; + } + /*store the NPSS interrupt mask clear status*/ + npssIntrState = NPSS_INTR_MASK_CLR_REG; + // Stores the NPSS GPIO interrupt configurations + npss_gpio_config = NPSS_GPIO_CONFIG_REG; + + /*Clear AUX and DAC pg enables */ + if (!((MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.SDCSS_BASED_WAKEUP_b) + || (MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b))) { + RSI_IPMU_PowerGateClr(AUXDAC_PG_ENB | AUXADC_PG_ENB); + } + /*Check the PS2 state or not*/ + if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { + + in_ps2_state = 1U; + + if (!((MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.SDCSS_BASED_WAKEUP_b) + || (MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b))) { + disable_pads_ctrl = (ULP_SPI_MEM_MAP(0x141) & BIT(11)); // ULP PADS PDO Status + ULP_SPI_MEM_MAP(0x141) &= ~(BIT(11)); // ULP PADS PDO OFF + enable_sdcss_based_wakeup = 1; + RSI_PS_SetWkpSources(SDCSS_BASED_WAKEUP); + } + + if (!(MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.M4ULP_RAM_RETENTION_MODE_EN_b)) { + enable_m4ulp_retention = 1; + m4ulp_ram_core_status = RSI_PS_M4ssRamBanksGetPowerSts(); + m4ulp_ram_peri_status = RSI_PS_M4ssRamBanksGetPeriPowerSts(); + RSI_PS_M4ssRamBanksPowerDown(RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9); + RSI_PS_M4ssRamBanksPeriPowerDown(RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9); +#ifdef CHIP_9118 + RSI_PS_SetRamRetention(M4ULP_RAM_RETENTION_MODE_EN); +#endif + } + } + /*Move to LP mode */ + RSI_IPMU_RetnLdoLpmode(); + if (sleepType == SLEEP_WITHOUT_RETENTION) { + /*POC1 */ + RSI_IPMU_PocbiasCurrent(); + /*RO32K_00_EFUSE. */ + RSI_IPMU_RO32khzTrim00Efuse(); + /*RETN1 */ + RSI_IPMU_RetnLdoLpmode(); + /*RETN0 */ + RSI_IPMU_RetnLdoVoltsel(); + } + + if (!in_ps2_state && MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b +#if (XTAL_CAP_MODE == POWER_TARN_CONDITIONAL_USE) + && (lf_clk_mode & BIT(4)) +#endif + ) { +#if (XTAL_CAP_MODE == POWER_TARN_CONDITIONAL_USE) + RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCUTS); + /*configure the slope,nominal temperature and f2_nominal*/ + RSI_TS_Config(MCU_TEMP, 25); + /*disable the bjt based temp sensor*/ + RSI_TS_RoBjtEnable(MCU_TEMP, 0); + /*Enable the RO based temp sensor*/ + RSI_TS_Enable(MCU_TEMP, 1); + /*update the temperature periodically*/ + RSI_Periodic_TempUpdate(TIME_PERIOD, 1, 0); + /*read the temperature*/ + Temp = (int)RSI_TS_ReadTemp(MCU_TEMP); + if (Temp > 45) { + // disable the XTAL CAP mode + RSI_IPMU_ProgramConfigData(lp_scdc_extcapmode); + } +#endif + +#if (XTAL_CAP_MODE == POWER_TARN_ALWAYS_USE) + // disable the XTAL CAP mode + RSI_IPMU_ProgramConfigData(lp_scdc_extcapmode); +#endif + } + + /*Clear IPMU BITS*/ + RSI_PS_LatchCntrlClr(LATCH_TOP_SPI | LATCH_TRANSPARENT_HF | LATCH_TRANSPARENT_LF); + + ipmuDummyRead = MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP; + + /*Update the SCB with Deep sleep BIT */ + SCB->SCR = 0x4; + + if (in_ps2_state) { + /*Read processor clock */ + ulp_proc_clk = ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL; + + /*LF processor clock configuration */ + switch (lf_clk_mode & 0x7) { + case DISABLE_LF_MODE: + /*Do nothing*/ + break; + case LF_32_KHZ_RC: + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = 2U; + break; + case LF_32_KHZ_XTAL: + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = 3U; + break; + case HF_MHZ_RO: + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = 5U; + break; + default: + return INVALID_PARAMETERS; + } + /* HF processor clock */ + } + + /* Before sleep,Reduce the SCDC voltage by one value */ + set_scdc(SL_SCDC_SLEEP); + +#ifdef SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE +#if (defined SLI_SI91X_MCU_INTERNAL_LDO_FOR_PSRAM) + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + if (sleepType == SLEEP_WITH_RETENTION) { + //!enable flash LDO and PMU DCDC ON in M4 for PSRAM with retention + MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_REG |= (LDO_FLASH_ON | PMU_DCDC_ON); +#if PSRAM_HALF_SLEEP_SUPPORTED != FALSE + /* Put PSRAM device to sleep */ + sl_si91x_psram_sleep(); +#endif + } +#elif (defined SLI_SI91X_MCU_EXTERNAL_LDO_FOR_PSRAM) +#if PSRAM_HALF_SLEEP_SUPPORTED != FALSE + if (sleepType == SLEEP_WITH_RETENTION) { + /* Put PSRAM device to sleep */ + sl_si91x_psram_sleep(); + } else { + /* External LDO handle for PSRAM */ + EXTERNAL_LDO_HANDLE; + } +#endif +#endif +#endif + +#ifdef SLI_SI91X_ENABLE_OS + /* Save Stack pointer value and Control registers */ + RSI_Save_Context(); +#endif + /* Take backup before going to PowerSave */ + p2p_intr_status_bkp.tass_p2p_intr_mask_clr_bkp = TASS_P2P_INTR_MASK_CLR; + p2p_intr_status_bkp.m4ss_p2p_intr_set_reg_bkp = M4SS_P2P_INTR_SET_REG; + +#if ((defined SLI_SI91X_MCU_COMMON_FLASH_MODE) && (!(defined(RAM_COMPILATION)))) + /* Reset M4_USING_FLASH bit before going to sleep */ + M4SS_P2P_INTR_CLR_REG = M4_USING_FLASH; +/*Before M4 is going to deep sleep , set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctr, AON domain power supply controls from M4 to NWP */ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + MCUAON_CONTROL_REG4 |= (MCU_TASS_REF_CLK_SEL_MUX_CTRL); + MCUAON_CONTROL_REG4; +#else + NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 = TASS_REF_CLK_MUX_CTRL; +#endif +#endif + /*Enter sleep with retention*/ + if (sleepType == SLEEP_WITH_RETENTION) { + /*If retention mode is enabled save the CPU context*/ + RSI_PS_SaveCpuContext(); + } else { + /*Clear RAM retentions*/ + RSI_PS_ClrRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN + | M4SS_RAM_RETENTION_MODE_EN); + /*do not save CPU context and go to deep sleep */ + __asm("WFI"); + } + //Disable the NVIC interrupts. + __asm volatile("cpsid i" ::: "memory"); + __asm volatile("dsb"); + __asm volatile("isb"); +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + /* if flash is not initialised ,then raise a request to NWP */ + if (!(in_ps2_state) && !(M4SS_P2P_INTR_SET_REG & M4_USING_FLASH)) { + //!check NWP wokeup or not + if (!(P2P_STATUS_REG & TA_IS_ACTIVE)) { + //!wakeup NWP + P2P_STATUS_REG |= M4_WAKEUP_TA; + + //!wait for NWP active + while (!(P2P_STATUS_REG & TA_IS_ACTIVE)) + ; + } + //!Check for TA_USING flash bit + if (!(TASS_P2P_INTR_CLEAR_REG & TA_USING_FLASH)) { + //! Request NWP to program flash + //! raise an interrupt to NWP register + M4SS_P2P_INTR_SET_REG = PROGRAM_COMMON_FLASH; + + //!Wait for NWP using flash bit + while (!(TASS_P2P_INTR_CLEAR_REG & TA_USING_FLASH)) + ; + } + M4SS_P2P_INTR_SET_REG = M4_USING_FLASH; + } +#endif +#ifdef SLI_SI91X_MCU_ENABLE_PSRAM_FEATURE +#if PSRAM_HALF_SLEEP_SUPPORTED != FALSE + /* Exit PSRAM device from sleep */ + sl_si91x_psram_wakeup(); +#endif +#endif + +#ifdef SLI_SI91X_ENABLE_OS + /* Restore Stack pointer value and Control registers */ + RSI_Restore_Context(); +#endif + /*Restore the default value to the processor clock */ + if ((in_ps2_state)) { + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = (unsigned int)(ulp_proc_clk & 0xF); + } + +#if ((defined SLI_SI91X_MCU_COMMON_FLASH_MODE) && (!(defined(RAM_COMPILATION)))) + /* Before NWP is going to power save mode, set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl ,AON domain power supply controls from NWP to M4 */ + RSI_Set_Cntrls_To_M4(); +#endif + +// READ_MBR_MAGIC_WORD_ON_WAKEUP +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + if (!(in_ps2_state)) { + //!Poll for flash magic word + while (MBR_MAGIC_WORD != 0x5A5A) + ; + } +#endif + +#ifndef SL_SI91X_NPSS_GPIO_BTN_HANDLER + // Clearing NPSS GPIO rise edge interrupts to avoid false triggering after wakeup + NPSS_GPIO_CONFIG_CLR_REG = NPSS_GPIO_CLR_VALUE; + + // Restoring the NPSS GPIO interrupt configurations after wakeup + NPSS_GPIO_CONFIG_REG = npss_gpio_config; +#endif + /* After wake-up, Set the SCDC voltage to the actual value*/ + /* As this function is located in flash accessing this fucntion only after getting controls*/ + set_scdc(SL_SCDC_ACTIVE); + + /*Update the REG Access SPI division factor to increase the SPI read/write speed*/ + + RSI_SetRegSpiDivision(1U); + + /*IPMU dummy read to make IPMU block out of RESET*/ + ipmuDummyRead = ULP_SPI_MEM_MAP(0x144); + // After Wakeup + if (!((in_ps2_state) && (MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.ULPSS_BASED_WAKEUP_b))) { +#if (XTAL_CAP_MODE == POWER_TARN_CONDITIONAL_USE) + if (lf_clk_mode & BIT(4)) { + // disable the XTAL CAP mode + RSI_PS_NpssPeriPowerUp(SLPSS_PWRGATE_ULP_MCUTS); + /*configure the slope,nominal temperature and f2_nominal*/ + RSI_TS_Config(MCU_TEMP, 25); + /*disable the bjt based temp sensor*/ + RSI_TS_RoBjtEnable(MCU_TEMP, 0); + /*Enable the RO based temp sensor*/ + RSI_TS_Enable(MCU_TEMP, 1); + /*update the temperature periodically*/ + RSI_Periodic_TempUpdate(TIME_PERIOD, 1, 0); + /*read the temperature*/ + Temp = (int)RSI_TS_ReadTemp(MCU_TEMP); + if (Temp > 45) { + //SCDC0 + RSI_IPMU_ProgramConfigData(scdc_volt_sel1); + RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); + //SCDC0_1 + RSI_IPMU_ProgramConfigData(scdc_volt_sel2); + } + } +#endif + +#if (XTAL_CAP_MODE == POWER_TARN_ALWAYS_USE) + // disable the XTAL CAP mode + //SCDC0 + RSI_IPMU_ProgramConfigData(scdc_volt_sel1); + RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); + //SCDC0_1 + RSI_IPMU_ProgramConfigData(scdc_volt_sel2); +#endif + } + /*Spare register write sequence*/ + ipmuDummyRead = ULP_SPI_MEM_MAP(0x1C1); + ULP_SPI_MEM_MAP(0x141) = ipmuDummyRead; + + ipmuDummyRead = ULP_SPI_MEM_MAP(0x1C0); + ULP_SPI_MEM_MAP(0x140) = ipmuDummyRead; + RSI_PS_LatchCntrlSet(LATCH_TOP_SPI); + + if (in_ps2_state) { + /*Come out of LP mode */ + /* enabling the RETN_LDO HP MODE */ + RSI_IPMU_RetnLdoHpmode(); + } + /*I2S-PLL Bypass*/ + *(volatile uint32_t *)(0x24041400 + 0x3C) |= BIT(0); + + if (enable_sdcss_based_wakeup) { + RSI_PS_ClrWkpSources(SDCSS_BASED_WAKEUP); + enable_sdcss_based_wakeup = 0; + } + if (enable_m4ulp_retention) { + RSI_PS_M4ssRamBanksPowerUp(m4ulp_ram_core_status); + RSI_PS_M4ssRamBanksPeriPowerUp(m4ulp_ram_peri_status); + enable_m4ulp_retention = 0; + } + if (disable_pads_ctrl) { + ULP_SPI_MEM_MAP(0x141) |= (BIT(11)); // ULP PADS PDO ON + disable_pads_ctrl = 0; + } + + /* powerup FPU domain*/ + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_M4_DEBUG_FPU); + + /*Initialize floating point unit */ + fpuInit(); + +#if defined(SLI_SI91X_MCU_ENABLE_RAM_BASED_EXECUTION) + //passing the ram vector address to VTOR register + SCB->VTOR = (uint32_t)ram_vector; +#endif + + /* Restore NPSS INTERRUPTS*/ + NPSS_INTR_MASK_CLR_REG = ~npssIntrState; + + /* Restore P2P register values from backup */ + TASS_P2P_INTR_MASK_CLR = ~p2p_intr_status_bkp.tass_p2p_intr_mask_clr_bkp; + M4SS_P2P_INTR_SET_REG = p2p_intr_status_bkp.m4ss_p2p_intr_set_reg_bkp; + + /* Restore the Interrupt Priority Register */ + for (var = 0; var < MAX_IPS; ++var) { + NVIC->IP[var] = nvic_ip_reg[var]; + } + /* Restore the System Handlers Priority Registers */ + for (var = 0; var < MAX_SHP; ++var) { + SCB->SHP[var] = scs_shp_reg[var]; + } + /* Restore the NVIC registers */ + for (var = 0; var < MAX_NVIC_REGS; ++var) { + NVIC->ISER[var] = nvic_enable[var]; + } + return RSI_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c new file mode 100644 index 000000000..7a0b5356b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c @@ -0,0 +1,294 @@ +/****************************************************************************** +* @file system_si91x.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/** + * Includes + */ + +#include +#include "system_si91x.h" +#include "rsi_error.h" +#include "rsi_ccp_common.h" +#include "rsi_ps_ram_func.h" +#include "rsi_ipmu.h" +#include "rsi_pll.h" +#include "rsi_power_save.h" +#include "rsi_ulpss_clk.h" +#include "rsi_rom_ulpss_clk.h" +#include "rsi_rom_clks.h" +#if defined(SLI_SI91X_MCU_PSRAM_PRESENT) +#include "rsi_d_cache.h" +#endif + +#if defined(SI91X_32kHz_EXTERNAL_OSCILLATOR) +#include "sl_si91x_external_oscillator.h" +#define MCU_RETENTION_BASE_ADDRESS 0x24048600 +#define NPSS_GPIO_CTRL (MCU_RETENTION_BASE_ADDRESS + 0x1C) +#endif + +#if defined(SLI_SI915) +#define BG_LDO_REG1 0x129 //IPMU Bandgap Top register +#define LDO_0P6_BYPASS_BIT 21 //Retention LDO bypass +#endif +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +/*Cortex-m4 FPU registers*/ +#define FPU_CPACR 0xE000ED88 +#define SCB_MVFR0 0xE000EF40 +#define SCB_MVFR0_RESET 0x10110021 +#define SCB_MVFR1 0xE000EF44 +#define SCB_MVFR1_RESET 0x11000011 + +/*Simulation macros*/ +#define SIMULATION_SILICON_REV 0x14 +#define SIMULATION_PACKAGE_TYPE 0x1 + +/* Constants required to manipulate the NVIC. */ +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ + +SYSTEM_CLOCK_SOURCE_FREQUENCIES_T system_clocks; /*!< System Clock sources Frequencies */ + +uint32_t npssIntrState = 0; +uint32_t __sp; +uint32_t SiliconRev; +uint32_t package_type; + +/** + * @fn void SystemCoreClockUpdate (void) + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + * @return none + */ +void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ +{ + const retention_boot_status_word_t *retention_reg = (const retention_boot_status_word_t *)MCURET_BOOTSTATUS; + + /*Updated the default SOC clock frequency*/ + SystemCoreClock = DEFAULT_40MHZ_CLOCK; +#if (defined(RAM_COMPILATION) && defined(SLI_SI91X_MCU_COMMON_FLASH_MODE)) + /*Initialize QSPI for RAM based execution for common flash boards */ + RSI_FLASH_Initialize(); +#endif +#ifndef SIMULATION +#ifdef RAM_COMPILATION + if (retention_reg->product_mode == MCU) { + SiliconRev = SIMULATION_SILICON_REV; + package_type = SIMULATION_PACKAGE_TYPE; + } else { + SiliconRev = SILICON_REV_WMCU; + package_type = PACKAGE_TYPE_WMCU; + } +#else + if (retention_reg->product_mode == MCU) { + SiliconRev = SILICON_REV_MCU; + package_type = PACKAGE_TYPE_MCU; + } else { + SiliconRev = SILICON_REV_WMCU; + package_type = PACKAGE_TYPE_WMCU; + } +#endif +#if defined(SLI_SI91X_MCU_PSRAM_PRESENT) + rsi_d_cache_invalidate_all(); +#endif + /*Initialize IPMU and MCU FSM blocks */ + RSI_Ipmu_Init(); + /*configures chip supply mode */ + RSI_Configure_Ipmu_Mode(); + +#endif + /*Default clock mux configurations */ + RSI_CLK_PeripheralClkEnable3(M4CLK, M4_SOC_CLK_FOR_OTHER_ENABLE); + + /* NWP clock is selected as 40MHZ clock from MCU */ + MCU_FSM->MCU_FSM_REF_CLK_REG_b.TASS_REF_CLK_SEL = ULP_MHZ_RC_CLK; + /* Changing NPSS GPIO 0 mode to 0, to disable buck-boost enable mode*/ + MCU_RET->NPSS_GPIO_CNTRL[0].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 0; + /* Configuring MCU FSM clock for BG_PMU */ + RSI_IPMU_ClockMuxSel(2); + +#if defined(SI91X_32kHz_EXTERNAL_OSCILLATOR) + + // Configuring the UULP_GPIOs for external oscillator + *(volatile uint32 *)(NPSS_GPIO_CTRL + (4 * OSC_UULP_GPIO)) = (BIT(3) | UULP_GPIO_OSC_MODE); + MCUAON_GEN_CTRLS_REG |= BIT(0); + MCUAON_GEN_CTRLS_REG; + + // Configuring RC 32KHz Clock for LF-FSM + RSI_PS_FsmLfClkSel(KHZ_RC_CLK_SEL); +#else + /* Configuring XTAL 32.768kHz Clock for LF-FSM */ + RSI_PS_FsmLfClkSel(KHZ_XTAL_CLK_SEL); +#endif // SI91X_32kHz_EXTERNAL_OSCILLATOR + + /* Configuring RC-MHz Clock for HF-FSM */ + RSI_PS_FsmHfClkSel(FSM_MHZ_RC); + + /* XTAL control pointed to Software and XTAL is Turned-Off from M4 */ + RSI_ConfigXtal(XTAL_DISABLE_FROM_M4, XTAL_IS_IN_SW_CTRL_FROM_M4); + +#if ((defined SLI_SI91X_MCU_COMMON_FLASH_MODE) && (!(defined(RAM_COMPILATION)))) + /* Before NWP is going to power save mode ,set m4ss_ref_clk_mux_ctrl , + tass_ref_clk_mux_ctrl, AON domain power supply controls from NWP to M4 */ + RSI_Set_Cntrls_To_M4(); + +#endif +#if defined(SLI_SI915) + ULP_SPI_MEM_MAP(BG_LDO_REG1) |= BIT(LDO_0P6_BYPASS_BIT); //bypassing the retention LDO +#endif + /*Update the system clock sources with source generating frequency*/ + system_clocks.m4ss_ref_clk = DEFAULT_40MHZ_CLOCK; + system_clocks.ulpss_ref_clk = DEFAULT_40MHZ_CLOCK; + system_clocks.soc_pll_clock = DEFAULT_SOC_PLL_CLOCK; + system_clocks.modem_pll_clock = DEFAULT_MODEM_PLL_CLOCK; + system_clocks.modem_pll_clock2 = DEFAULT_MODEM_PLL_CLOCK; + system_clocks.intf_pll_clock = DEFAULT_INTF_PLL_CLOCK; + system_clocks.soc_clock = DEFAULT_40MHZ_CLOCK; + system_clocks.rc_32khz_clock = DEFAULT_32KHZ_RC_CLOCK; + system_clocks.rc_mhz_clock = DEFAULT_MHZ_RC_CLOCK; + system_clocks.ro_20mhz_clock = DEFAULT_20MHZ_RO_CLOCK; + system_clocks.ro_32khz_clock = DEFAULT_32KHZ_RO_CLOCK; + system_clocks.xtal_32khz_clock = DEFAULT_32KHZ_XTAL_CLOCK; + system_clocks.doubler_clock = DEFAULT_DOUBLER_CLOCK; + system_clocks.rf_ref_clock = DEFAULT_40MHZ_CLOCK; + system_clocks.mems_ref_clock = DEFAULT_MEMS_REF_CLOCK; + system_clocks.byp_rc_ref_clock = DEFAULT_MHZ_RC_CLOCK; + system_clocks.i2s_pll_clock = DEFAULT_I2S_PLL_CLOCK; + + return; +} + +/** + * @fn void fpuInit(void) + * @brief This API is used to Early initialization of the FPU + * @return none + * + */ +void fpuInit(void) +{ +#if __FPU_PRESENT != 0 + // from arm trm manual: + // ; CPACR is located at address 0xE000ED88 + // LDR.W R0, =0xE000ED88 + // ; Read CPACR + // LDR R1, [R0] + // ; Set bits 20-23 to enable CP10 and CP11 coprocessors + // ORR R1, R1, #(0xF << 20) + // ; Write back the modified value to the CPACR + // STR R1, [R0] + + volatile uint32_t *regCpacr = (uint32_t *)FPU_CPACR; + volatile const uint32_t *regMvfr0 = (volatile const uint32_t *)SCB_MVFR0; + volatile const uint32_t *regMvfr1 = (volatile const uint32_t *)SCB_MVFR1; + volatile uint32_t Cpacr; + volatile uint32_t Mvfr0; + volatile uint32_t Mvfr1; + char vfpPresent = 0; + + Mvfr0 = *regMvfr0; + Mvfr1 = *regMvfr1; + + vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); + + if (vfpPresent) { + Cpacr = *regCpacr; + Cpacr |= (0xF << 20); + *regCpacr = Cpacr; // enable CP10 and CP11 for full access + } +#endif /* __FPU_PRESENT != 0 */ +} + +/** + * @fn void SystemInit (void) + * @brief This API is used Setup the RS1xxxx chip(Initialize the system) + * @return none + */ +void SystemInit(void) +{ + volatile uint32_t ipmuDummyRead = 0; + volatile uint32_t spareReg2 = 0; + + /*IPMU dummy read to make IPMU block out of RESET*/ + ipmuDummyRead = ULP_SPI_MEM_MAP(0x144); + ipmuDummyRead = ipmuDummyRead; + + /*Update the REG Access SPI division factor to increase the SPI read/write speed*/ + RSI_SetRegSpiDivision(0U); + + ULP_SPI_MEM_MAP(BG_SCDC_PROG_REG_1) &= REF_SEL_LP_DCDC; + + /*Spare register write sequence*/ + spareReg2 = ULP_SPI_MEM_MAP(0x1C1); + ULP_SPI_MEM_MAP(0x141) = spareReg2; + //while(GSPI_CTRL_REG1 & SPI_ACTIVE); + /*Spare register write sequence*/ + spareReg2 = ULP_SPI_MEM_MAP(0x1C0); + ULP_SPI_MEM_MAP(0x140) = spareReg2; + + /*Set IPMU BITS*/ + ULP_SPI_MEM_MAP(SELECT_BG_CLK) |= (LATCH_TOP_SPI | LATCH_TRANSPARENT_HF | LATCH_TRANSPARENT_LF); + + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + + MCU_AON->MCUAON_GEN_CTRLS_b.ENABLE_PDO = 1; + MCU_AON->MCUAON_GEN_CTRLS_b.NPSS_SUPPLY_0P9 = 0; + + /*Enable FPU*/ + fpuInit(); + + /* Enable REF Clock Control*/ + //FIXME: This will be configured by boot-loader based on product mode + *(volatile uint32_t *)0x41300004 = BIT(24); + + /*Moving to BG sampling mode */ + *(volatile uint32_t *)0x24048140 = (BIT(19) | BIT(1) | BIT(0)); + + /*Disable WIC based wake up */ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.WICENREQ = 0; + + /*Set ulp_wakeup_por*/ + MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.MCU_FIRST_POWERUP_POR = 1U; + MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.MCU_FIRST_POWERUP_RESET_N = 1U; + /*Programmable delay 4mes for WDT reset */ + PMU_DIRECT_ACCESS(BG_SLEEP_TIMER_REG_OFFSET) |= BIT(19); //bgs_active_timer_sel + /*Programmable delay 4mes for WDT reset */ + MCU_AON->MCUAON_SHELF_MODE_b.SHELF_MODE_WAKEUP_DELAY = 0x7; + /* Enables software based control of isolation and reset for ULP AON */ + BATT_FF->M4SS_BYPASS_PWRCTRL_REG1_b.BYPASS_M4SS_PWRCTL_ULP_AON_b = 1; + /* Enables software based control of isolation and reset for M4ss CORE */ + BATT_FF->M4SS_BYPASS_PWRCTRL_REG1_b.BYPASS_M4SS_PWRCTL_ULP_M4_CORE_b = 1; + return; +} +/** + *@} + */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h b/wiseconnect/components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h new file mode 100644 index 000000000..6e04b6d36 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/core/config/rsi_ccp_user_config.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* @file rsi_ccp_user_config.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/*rsi_ccp_user_config.h --> user configurations w.r.t CCP*/ + +/* To enable 917 chip --> Add #define SLI_SI917 */ +/* To enable 9116 chip --> Add #define CHIP_9118 */ +/* To enable 9115 chip --> Add #define CHIP_915 */ + +/* #define CHIP_9118 */ +/* #define CHIP_915 */ +//#define SLI_SI917 + +#ifdef CHIP_915 +#if !defined(SLI_SI917) && !defined(SLI_SI915) +#define SLI_SI917 +#endif +#endif + +/*1. By default A10 ROM is enabled */ +/*2. To enable A11 ROM --> Add #define A11_ROM (this disables A10 ROM) */ +/*3. To enable OS --> Add SLI_SI91X_ENABLE_OS in preprocessor */ +/*4. To enable ROM Wireless --> Add #define ROM_WIRELESS */ +#define A11_ROM + +#ifndef SLI_SI91X_MCU_MOV_ROM_API_TO_FLASH +#define ROMDRIVER_PRESENT +#endif + +#if defined(SLI_SI917B0) || defined(SLI_SI915) +#define SI91X_SYSRTC_COUNT 2 +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h new file mode 100644 index 000000000..a59dc9cca --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_Common.h @@ -0,0 +1,73 @@ +/* ----------------------------------------------------------------------------- + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 2. Jan 2014 + * $Revision: V2.00 + * + * Project: Common Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.00 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Added General return codes definitions + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_COMMON_H +#define __DRIVER_COMMON_H + +#include +#include +#include + +#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor)) + +/** +\brief Driver Version +*/ +typedef struct _ARM_DRIVER_VERSION { + uint16_t api; ///< API version + uint16_t drv; ///< Driver version +} ARM_DRIVER_VERSION; + +/* General return codes */ +#define ARM_DRIVER_OK 0 ///< Operation succeeded +#define ARM_DRIVER_ERROR -1 ///< Unspecified error +#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy +#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred +#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported +#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error +#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors + +/** +\brief General power states +*/ +typedef enum _ARM_POWER_STATE { + ARM_POWER_OFF, ///< Power off: no operation possible + ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events + ARM_POWER_FULL ///< Power on: full operation at maximum performance +} ARM_POWER_STATE; + +#endif /* __DRIVER_COMMON_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h new file mode 100644 index 000000000..b6f0d7576 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_I2C.h @@ -0,0 +1,209 @@ +/* ----------------------------------------------------------------------------- + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. May 2014 + * $Revision: V2.02 + * + * Project: I2C (Inter-Integrated Circuit) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.02 + * Removed function ARM_I2C_MasterTransfer in order to simplify drivers + * and added back parameter "xfer_pending" to functions + * ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Version 2.01 + * Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending" + * from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive + * Added function ARM_I2C_GetDataCount + * Removed flag "address_nack" from ARM_I2C_STATUS + * Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE + * with event ARM_I2C_EVENT_TRANSFER_DONE + * Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE + * Removed parameter "arg" from function ARM_I2C_SignalEvent + * Version 2.00 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * Added: + * Slave Mode + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_I2C_H +#define __DRIVER_I2C_H + +#include "Driver_Common.h" + + +#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ + + +/****** I2C Control Codes *****/ + +#define ARM_I2C_OWN_ADDRESS (0x01) ///< Set Own Slave Address; arg = address +#define ARM_I2C_BUS_SPEED (0x02) ///< Set Bus Speed; arg = speed +#define ARM_I2C_BUS_CLEAR (0x03) ///< Execute Bus clear: send nine clock pulses +#define ARM_I2C_ABORT_TRANSFER (0x04) ///< Abort Master/Slave Transmit/Receive + +/*----- I2C Bus Speed -----*/ +#define ARM_I2C_BUS_SPEED_STANDARD (0x01) ///< Standard Speed (100kHz) +#define ARM_I2C_BUS_SPEED_FAST (0x02) ///< Fast Speed (400kHz) +#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03) ///< Fast+ Speed ( 1MHz) +#define ARM_I2C_BUS_SPEED_HIGH (0x04) ///< High Speed (3.4MHz) + + +/****** I2C Address Flags *****/ + +#define ARM_I2C_ADDRESS_10BIT 0x0400 ///< 10-bit address flag +#define ARM_I2C_ADDRESS_GC 0x8000 ///< General Call flag + + +/** +\brief I2C Status +*/ +typedef struct _ARM_I2C_STATUS { + unsigned int busy : 1; ///< Busy flag + unsigned int mode : 1; ///< Mode: 0=Slave, 1=Master + unsigned int direction : 1; ///< Direction: 0=Transmitter, 1=Receiver + unsigned int general_call : 1; ///< General Call indication (cleared on start of next Slave operation) + unsigned int arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation) + unsigned int bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation) +} ARM_I2C_STATUS; + + +/****** I2C Event *****/ +#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished +#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer +#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Slave Transmit operation requested +#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Slave Receive operation requested +#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave +#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< General Call indication +#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration +#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position) +#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_I2C_CAPABILITIES + + \fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event) + \brief Initialize I2C Interface. + \param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_I2C_Uninitialize (void) + \brief De-initialize I2C Interface. + \return \ref execution_status + + \fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state) + \brief Control I2C Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start transmitting data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[in] data Pointer to buffer with data to transmit to I2C Slave + \param[in] num Number of data bytes to transmit + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) + \brief Start receiving data as I2C Master. + \param[in] addr Slave address (7-bit or 10-bit) + \param[out] data Pointer to buffer for data to receive from I2C Slave + \param[in] num Number of data bytes to receive + \param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num) + \brief Start transmitting data as I2C Slave. + \param[in] data Pointer to buffer with data to transmit to I2C Master + \param[in] num Number of data bytes to transmit + \return \ref execution_status + + \fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num) + \brief Start receiving data as I2C Slave. + \param[out] data Pointer to buffer for data to receive from I2C Master + \param[in] num Number of data bytes to receive + \return \ref execution_status + + \fn int32_t ARM_I2C_GetDataCount (void) + \brief Get transferred data count. + \return number of data bytes transferred; -1 when Slave is not addressed by Master + + \fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg) + \brief Control I2C Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return \ref execution_status + + \fn ARM_I2C_STATUS ARM_I2C_GetStatus (void) + \brief Get I2C status. + \return I2C status \ref ARM_I2C_STATUS + + \fn void ARM_I2C_SignalEvent (uint32_t event) + \brief Signal I2C Events. + \param[in] event \ref I2C_events notification mask +*/ + +typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event. + + +/** +\brief I2C Driver Capabilities. +*/ +typedef struct _ARM_I2C_CAPABILITIES { + uint32_t address_10_bit : 1; ///< supports 10-bit addressing +} ARM_I2C_CAPABILITIES; + + +/** +\brief Access structure of the I2C Driver. +*/ +typedef struct _ARM_DRIVER_I2C { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version. + ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power. + int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master. + int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master. + int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave. + int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave. + int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface. + ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status. +} const ARM_DRIVER_I2C; + +#endif /* __DRIVER_I2C_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h new file mode 100644 index 000000000..8c049d12b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SAI.h @@ -0,0 +1,299 @@ +/* ----------------------------------------------------------------------------- + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. Dec 2014 + * $Revision: V1.00 + * + * Project: SAI (Serial Audio Interface) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_SAI_H +#define __DRIVER_SAI_H + +#include "Driver_Common.h" + +#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00) /* API version */ + + +/****** SAI Control Codes *****/ + +#define ARM_SAI_CONTROL_Msk (0xFFU) +#define ARM_SAI_CONFIGURE_TX (0x01U) ///< Configure Transmitter; arg1 and arg2 provide additional configuration +#define ARM_SAI_CONFIGURE_RX (0x02U) ///< Configure Receiver; arg1 and arg2 provide additional configuration +#define ARM_SAI_CONTROL_TX (0x03U) ///< Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute +#define ARM_SAI_CONTROL_RX (0x04U) ///< Control Receiver; arg1.0: 0=disable (default), 1=enable +#define ARM_SAI_MASK_SLOTS_TX (0x05U) ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default +#define ARM_SAI_MASK_SLOTS_RX (0x06U) ///< Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default +#define ARM_SAI_ABORT_SEND (0x07U) ///< Abort \ref ARM_SAI_Send +#define ARM_SAI_ABORT_RECEIVE (0x08U) ///< Abort \ref ARM_SAI_Receive + +/*----- SAI Control Codes: Configuration Parameters: Mode -----*/ +#define ARM_SAI_MODE_Pos 8 +#define ARM_SAI_MODE_Msk (1U << ARM_SAI_MODE_Pos) +#define ARM_SAI_MODE_MASTER (1U << ARM_SAI_MODE_Pos) ///< Master Mode +#define ARM_SAI_MODE_SLAVE (0U << ARM_SAI_MODE_Pos) ///< Slave Mode (default) + +/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/ +#define ARM_SAI_SYNCHRONIZATION_Pos 9 +#define ARM_SAI_SYNCHRONIZATION_Msk (1U << ARM_SAI_SYNCHRONIZATION_Pos) +#define ARM_SAI_ASYNCHRONOUS (0U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Asynchronous (default) +#define ARM_SAI_SYNCHRONOUS (1U << ARM_SAI_SYNCHRONIZATION_Pos) ///< Synchronous + +/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/ +#define ARM_SAI_PROTOCOL_Pos 10 +#define ARM_SAI_PROTOCOL_Msk (7U << ARM_SAI_PROTOCOL_Pos) +#define ARM_SAI_PROTOCOL_USER (0U << ARM_SAI_PROTOCOL_Pos) ///< User defined (default) +#define ARM_SAI_PROTOCOL_I2S (1U << ARM_SAI_PROTOCOL_Pos) ///< I2S +#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED (2U << ARM_SAI_PROTOCOL_Pos) ///< MSB (left) justified +#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED (3U << ARM_SAI_PROTOCOL_Pos) ///< LSB (right) justified +#define ARM_SAI_PROTOCOL_PCM_SHORT (4U << ARM_SAI_PROTOCOL_Pos) ///< PCM with short frame +#define ARM_SAI_PROTOCOL_PCM_LONG (5U << ARM_SAI_PROTOCOL_Pos) ///< PCM with long frame +#define ARM_SAI_PROTOCOL_AC97 (6U << ARM_SAI_PROTOCOL_Pos) ///< AC'97 + +/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/ +#define ARM_SAI_DATA_SIZE_Pos 13 +#define ARM_SAI_DATA_SIZE_Msk (0x1FU << ARM_SAI_DATA_SIZE_Pos) +#define ARM_SAI_DATA_SIZE(n) ((((n)-1)&0x1FU) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32) + +/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/ +#define ARM_SAI_BIT_ORDER_Pos 18 +#define ARM_SAI_BIT_ORDER_Msk (1U << ARM_SAI_BIT_ORDER_Pos) +#define ARM_SAI_MSB_FIRST (0U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with MSB first (default) +#define ARM_SAI_LSB_FIRST (1U << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with LSB first; User Protocol only (ignored otherwise) + +/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/ +#define ARM_SAI_MONO_MODE (1U << 19) ///< Mono Mode (only for I2S, MSB/LSB justified) + +/*----- SAI Control Codes:Configuration Parameters: Companding -----*/ +#define ARM_SAI_COMPANDING_Pos 20 +#define ARM_SAI_COMPANDING_Msk (3U << ARM_SAI_COMPANDING_Pos) +#define ARM_SAI_COMPANDING_NONE (0U << ARM_SAI_COMPANDING_Pos) ///< No compading (default) +#define ARM_SAI_COMPANDING_A_LAW (2U << ARM_SAI_COMPANDING_Pos) ///< A-Law companding +#define ARM_SAI_COMPANDING_U_LAW (3U << ARM_SAI_COMPANDING_Pos) ///< u-Law companding + +/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/ +#define ARM_SAI_CLOCK_POLARITY_Pos 23 +#define ARM_SAI_CLOCK_POLARITY_Msk (1U << ARM_SAI_CLOCK_POLARITY_Pos) +#define ARM_SAI_CLOCK_POLARITY_0 (0U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on falling edge, Capture on rising edge (default) +#define ARM_SAI_CLOCK_POLARITY_1 (1U << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on rising edge, Capture on falling edge + +/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/ +#define ARM_SAI_MCLK_PIN_Pos 24 +#define ARM_SAI_MCLK_PIN_Msk (3U << ARM_SAI_MCLK_PIN_Pos) +#define ARM_SAI_MCLK_PIN_INACTIVE (0U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK not used (default) +#define ARM_SAI_MCLK_PIN_OUTPUT (1U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is output (Master only) +#define ARM_SAI_MCLK_PIN_INPUT (2U << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is input (Master only) + + +/****** SAI Configuration (arg1) *****/ + +/*----- SAI Configuration (arg1): Frame Length -----*/ +#define ARM_SAI_FRAME_LENGTH_Pos 0 +#define ARM_SAI_FRAME_LENGTH_Msk (0x3FFU << ARM_SAI_FRAME_LENGTH_Pos) +#define ARM_SAI_FRAME_LENGTH(n) ((((n)-1)&0x3FFU) << ARM_SAI_FRAME_LENGTH_Pos) ///< Frame length in bits (8..1024); default depends on protocol and data + +/*----- SAI Configuration (arg1): Frame Sync Width -----*/ +#define ARM_SAI_FRAME_SYNC_WIDTH_Pos 10 +#define ARM_SAI_FRAME_SYNC_WIDTH_Msk (0xFFU << ARM_SAI_FRAME_SYNC_WIDTH_Pos) +#define ARM_SAI_FRAME_SYNC_WIDTH(n) ((((n)-1)&0xFFU) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/ +#define ARM_SAI_FRAME_SYNC_POLARITY_Pos 18 +#define ARM_SAI_FRAME_SYNC_POLARITY_Msk (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) +#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active high (default); User Protocol only (ignored otherwise) +#define ARM_SAI_FRAME_SYNC_POLARITY_LOW (1U << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active low; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Frame Sync Early -----*/ +#define ARM_SAI_FRAME_SYNC_EARLY (1U << 19) ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Slot Count -----*/ +#define ARM_SAI_SLOT_COUNT_Pos 20 +#define ARM_SAI_SLOT_COUNT_Msk (0x1FU << ARM_SAI_SLOT_COUNT_Pos) +#define ARM_SAI_SLOT_COUNT(n) ((((n)-1)&0x1FU) << ARM_SAI_SLOT_COUNT_Pos) ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Slot Size -----*/ +#define ARM_SAI_SLOT_SIZE_Pos 25 +#define ARM_SAI_SLOT_SIZE_Msk (3U << ARM_SAI_SLOT_SIZE_Pos) +#define ARM_SAI_SLOT_SIZE_DEFAULT (0U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size is equal to data size (default) +#define ARM_SAI_SLOT_SIZE_16 (1U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 16 bits; User Protocol only (ignored otherwise) +#define ARM_SAI_SLOT_SIZE_32 (3U << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 32 bits; User Protocol only (ignored otherwise) + +/*----- SAI Configuration (arg1): Slot Offset -----*/ +#define ARM_SAI_SLOT_OFFSET_Pos 27 +#define ARM_SAI_SLOT_OFFSET_Msk (0x1FU << ARM_SAI_SLOT_OFFSET_Pos) +#define ARM_SAI_SLOT_OFFSET(n) (((n)&0x1FU) << ARM_SAI_SLOT_OFFSET_Pos) ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise) + +/****** SAI Configuration (arg2) *****/ + +/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/ +#define ARM_SAI_AUDIO_FREQ_Msk (0x0FFFFFU) ///< Audio frequency mask + +/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/ +#define ARM_SAI_MCLK_PRESCALER_Pos 20 +#define ARM_SAI_MCLK_PRESCALER_Msk (0xFFFU << ARM_SAI_MCLK_PRESCALER_Pos) +#define ARM_SAI_MCLK_PRESCALER(n) ((((n)-1)&0xFFFU) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1) + + +/****** SAI specific error codes *****/ +#define ARM_SAI_ERROR_SYNCHRONIZATION (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Synchronization not supported +#define ARM_SAI_ERROR_PROTOCOL (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Protocol not supported +#define ARM_SAI_ERROR_DATA_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified Data size not supported +#define ARM_SAI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported +#define ARM_SAI_ERROR_MONO_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Mono mode not supported +#define ARM_SAI_ERROR_COMPANDING (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Companding not supported +#define ARM_SAI_ERROR_CLOCK_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock polarity not supported +#define ARM_SAI_ERROR_AUDIO_FREQ (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Audio frequency not supported +#define ARM_SAI_ERROR_MCLK_PIN (ARM_DRIVER_ERROR_SPECIFIC - 9) ///< Specified MCLK Pin setting not supported +#define ARM_SAI_ERROR_MCLK_PRESCALER (ARM_DRIVER_ERROR_SPECIFIC - 10) ///< Specified MCLK Prescaler not supported +#define ARM_SAI_ERROR_FRAME_LENGHT (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported +#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH (ARM_DRIVER_ERROR_SPECIFIC - 12) ///< Specified Frame Sync width not supported +#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 13) ///< Specified Frame Sync polarity not supported +#define ARM_SAI_ERROR_FRAME_SYNC_EARLY (ARM_DRIVER_ERROR_SPECIFIC - 14) ///< Specified Frame Sync early not supported +#define ARM_SAI_ERROR_SLOT_COUNT (ARM_DRIVER_ERROR_SPECIFIC - 15) ///< Specified Slot count not supported +#define ARM_SAI_ERROR_SLOT_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 16) ///< Specified Slot size not supported +#define ARM_SAI_ERROR_SLOT_OFFESET (ARM_DRIVER_ERROR_SPECIFIC - 17) ///< Specified Slot offset not supported + + +/** +\brief SAI Status +*/ +typedef struct _ARM_SAI_STATUS { + unsigned int tx_busy : 1; ///< Transmitter busy flag + unsigned int rx_busy : 1; ///< Receiver busy flag + unsigned int tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + unsigned int rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + unsigned int frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation) +} ARM_SAI_STATUS; + + +/****** SAI Event *****/ +#define ARM_SAI_EVENT_SEND_COMPLETE (1U << 0) ///< Send completed +#define ARM_SAI_EVENT_RECEIVE_COMPLETE (1U << 1) ///< Receive completed +#define ARM_SAI_EVENT_TX_UNDERFLOW (1U << 2) ///< Transmit data not available +#define ARM_SAI_EVENT_RX_OVERFLOW (1U << 3) ///< Receive data overflow +#define ARM_SAI_EVENT_FRAME_ERROR (1U << 4) ///< Sync Frame error in Slave mode (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_SAI_CAPABILITIES + + \fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event) + \brief Initialize SAI Interface. + \param[in] cb_event Pointer to \ref ARM_SAI_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_SAI_Uninitialize (void) + \brief De-initialize SAI Interface. + \return \ref execution_status + + \fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state) + \brief Control SAI Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_SAI_Send (const void *data, uint32_t num) + \brief Start sending data to SAI transmitter. + \param[in] data Pointer to buffer with data to send to SAI transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_SAI_Receive (void *data, uint32_t num) + \brief Start receiving data from SAI receiver. + \param[out] data Pointer to buffer for data to receive from SAI receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn uint32_t ARM_SAI_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_SAI_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2) + \brief Control SAI Interface. + \param[in] control Operation + \param[in] arg1 Argument 1 of operation (optional) + \param[in] arg2 Argument 2 of operation (optional) + \return common \ref execution_status and driver specific \ref sai_execution_status + + \fn ARM_SAI_STATUS ARM_SAI_GetStatus (void) + \brief Get SAI status. + \return SAI status \ref ARM_SAI_STATUS + + \fn void ARM_SAI_SignalEvent (uint32_t event) + \brief Signal SAI Events. + \param[in] event \ref SAI_events notification mask + \return none +*/ + +typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event. + + +/** +\brief SAI Driver Capabilities. +*/ +typedef struct _ARM_SAI_CAPABILITIES { + uint32_t asynchronous : 1; ///< supports asynchronous Transmit/Receive + uint32_t synchronous : 1; ///< supports synchronous Transmit/Receive + uint32_t protocol_user : 1; ///< supports user defined Protocol + uint32_t protocol_i2s : 1; ///< supports I2S Protocol + uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol + uint32_t protocol_pcm : 1; ///< supports PCM short/long frame Protocol + uint32_t protocol_ac97 : 1; ///< supports AC'97 Protocol + uint32_t mono_mode : 1; ///< supports Mono mode + uint32_t companding : 1; ///< supports Companding + uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin + uint32_t event_frame_error : 1; ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR +} ARM_SAI_CAPABILITIES; + + +/** +\brief Access structure of the SAI Driver. +*/ +typedef struct _ARM_DRIVER_SAI { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version. + ARM_SAI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_SAI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface. + ARM_SAI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status. +} const ARM_DRIVER_SAI; + +#endif /* __DRIVER_SAI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h new file mode 100644 index 000000000..4d707e26e --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_SPI.h @@ -0,0 +1,239 @@ +/* ----------------------------------------------------------------------------- + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 17. Apr 2014 + * $Revision: V2.01 + * + * Project: SPI (Serial Peripheral Interface) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.01 + * Renamed status flag "tx_rx_busy" to "busy" + * Version 2.00 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * Added: + * Slave Mode + * Half-duplex Modes + * Configurable number of data bits + * Support for TI Mode and Microwire + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added "send_done_event" to Capabilities + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_SPI_H +#define __DRIVER_SPI_H + +#include "Driver_Common.h" + +#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,00) /* API version */ + + +/****** SPI Control Codes *****/ + +#define ARM_SPI_CONTROL_Pos 0 +#define ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos) + +/*----- SPI Control Codes: Mode -----*/ +#define ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) ///< SPI Inactive +#define ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps +#define ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output on MISO, Input on MOSI) +#define ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps +#define ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output/Input on MISO) + +/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/ +#define ARM_SPI_FRAME_FORMAT_Pos 8 +#define ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos) +#define ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 0 (default) +#define ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 1 +#define ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 0 +#define ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 1 +#define ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Texas Instruments Frame Format +#define ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) ///< National Microwire Frame Format + +/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_SPI_DATA_BITS_Pos 12 +#define ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos) +#define ARM_SPI_DATA_BITS(n) (((n) & 0x3F) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits + +/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/ +#define ARM_SPI_BIT_ORDER_Pos 18 +#define ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos) +#define ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from MSB to LSB (default) +#define ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from LSB to MSB + +/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/ +#define ARM_SPI_SS_MASTER_MODE_Pos 19 +#define ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos) +#define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default) +#define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled +#define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output +#define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input +#define ARM_SPI_SS_SLAVE_MODE_Pos 21 +#define ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) +#define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Hardware monitored (default) +#define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Software controlled + + +/*----- SPI Control Codes: Miscellaneous Controls -----*/ +#define ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) ///< Set Bus Speed in bps; arg = value +#define ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) ///< Get Bus Speed in bps +#define ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) ///< Set default Transmit value; arg = value +#define ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) ///< Control Slave Select; arg: 0=inactive, 1=active +#define ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) ///< Abort current data transfer + + +/****** SPI Slave Select Signal definitions *****/ +#define ARM_SPI_SS_INACTIVE 0 ///< SPI Slave Select Signal Inactive +#define ARM_SPI_SS_ACTIVE 1 ///< SPI Slave Select Signal Active + + +/****** SPI specific error codes *****/ +#define ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported +#define ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported +#define ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported + + +/** +\brief SPI Status +*/ +typedef struct _ARM_SPI_STATUS { + unsigned int busy : 1; ///< Transmitter/Receiver busy flag + unsigned int data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + unsigned int mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation) +} ARM_SPI_STATUS; + + +/****** SPI Event *****/ +#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed +#define ARM_SPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow +#define ARM_SPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master) +#define ARM_SPI_EVENT_SEND_COMPLETE (1UL << 3) ///< Master Mode Fault (SS deactivated when Master) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_SPI_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void) + \brief Get driver capabilities. + \return \ref ARM_SPI_CAPABILITIES + + \fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event) + \brief Initialize SPI Interface. + \param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_SPI_Uninitialize (void) + \brief De-initialize SPI Interface. + \return \ref execution_status + + \fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state) + \brief Control SPI Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_SPI_Send (const void *data, uint32_t num) + \brief Start sending data to SPI transmitter. + \param[in] data Pointer to buffer with data to send to SPI transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_SPI_Receive (void *data, uint32_t num) + \brief Start receiving data from SPI receiver. + \param[out] data Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_SPI_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from SPI transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to SPI transmitter + \param[out] data_in Pointer to buffer for data to receive from SPI receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_SPI_GetDataCount (void) + \brief Get transferred data count. + \return number of data items transferred + + \fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg) + \brief Control SPI Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref spi_execution_status + + \fn ARM_SPI_STATUS ARM_SPI_GetStatus (void) + \brief Get SPI status. + \return SPI status \ref ARM_SPI_STATUS + + \fn void ARM_SPI_SignalEvent (uint32_t event) + \brief Signal SPI Events. + \param[in] event \ref SPI_events notification mask + \return none +*/ + +typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event. + + +/** +\brief SPI Driver Capabilities. +*/ +typedef struct _ARM_SPI_CAPABILITIES { + unsigned int simplex : 1; ///< supports Simplex Mode (Master and Slave) + unsigned int ti_ssi : 1; ///< supports TI Synchronous Serial Interface + unsigned int microwire : 1; ///< supports Microwire Interface + unsigned int event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT +} ARM_SPI_CAPABILITIES; + + +/** +\brief Access structure of the SPI Driver. +*/ +typedef struct _ARM_DRIVER_SPI { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version. + ARM_SPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_SPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface. + int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI. + uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface. + ARM_SPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status. +} const ARM_DRIVER_SPI; + +#endif /* __DRIVER_SPI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h new file mode 100644 index 000000000..5704eed8d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include/Driver_USART.h @@ -0,0 +1,331 @@ +/* ----------------------------------------------------------------------------- + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 24. Nov 2014 + * $Revision: V2.02 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 2.02 + * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions + * Version 2.01 + * Removed optional argument parameter from Signal Event + * Version 2.00 + * New simplified driver: + * complexity moved to upper layer (especially data handling) + * more unified API for different communication interfaces + * renamed driver UART -> USART (Asynchronous & Synchronous) + * Added modes: + * Synchronous + * Single-wire + * IrDA + * Smart Card + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.01 + * Added events: + * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT + * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD + * Added functions: SetTxThreshold, SetRxThreshold + * Added "rx_timeout_event" to capabilities + * Version 1.00 + * Initial release + */ + +#ifndef __DRIVER_USART_H +#define __DRIVER_USART_H + +#include "Driver_Common.h" + +#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,02) /* API version */ + + +/****** USART Control Codes *****/ + +#define ARM_USART_CONTROL_Pos 0 +#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) + +/*----- USART Control Codes: Mode -----*/ +#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate +#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) +#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate +#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate +#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate + +/*----- USART Control Codes: Mode Parameters: Data Bits -----*/ +#define ARM_USART_DATA_BITS_Pos 8 +#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) +#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits +#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit +#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits +#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) +#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits + +/*----- USART Control Codes: Mode Parameters: Parity -----*/ +#define ARM_USART_PARITY_Pos 12 +#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) +#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) +#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity +#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity + +/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ +#define ARM_USART_STOP_BITS_Pos 14 +#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) +#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) +#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits +#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits +#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits + +/*----- USART Control Codes: Mode Parameters: Flow Control -----*/ +#define ARM_USART_FLOW_CONTROL_Pos 16 +#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) +#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) +#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control +#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control +#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control + +/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ +#define ARM_USART_CPOL_Pos 18 +#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) +#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) +#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 + +/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ +#define ARM_USART_CPHA_Pos 19 +#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) +#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) +#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 + + +/*----- USART Control Codes: Miscellaneous Controls -----*/ +#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value +#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period +#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods +#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated +#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled +#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled +#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send +#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive +#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer + + + +/****** USART specific error codes *****/ +#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported +#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported +#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported +#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported +#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported +#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported +#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported +#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported + + +/** +\brief USART Status +*/ +typedef struct _ARM_USART_STATUS { + unsigned int tx_busy : 1; ///< Transmitter busy flag + unsigned int rx_busy : 1; ///< Receiver busy flag + unsigned int tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) + unsigned int rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) + unsigned int rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) + unsigned int rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) + unsigned int rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) +} ARM_USART_STATUS; + +/** +\brief USART Modem Control +*/ +typedef enum _ARM_USART_MODEM_CONTROL { + ARM_USART_RTS_CLEAR, ///< Deactivate RTS + ARM_USART_RTS_SET, ///< Activate RTS + ARM_USART_DTR_CLEAR, ///< Deactivate DTR + ARM_USART_DTR_SET ///< Activate DTR +} ARM_USART_MODEM_CONTROL; + +/** +\brief USART Modem Status +*/ +typedef struct _ARM_USART_MODEM_STATUS { + unsigned int cts : 1; ///< CTS state: 1=Active, 0=Inactive + unsigned int dsr : 1; ///< DSR state: 1=Active, 0=Inactive + unsigned int dcd : 1; ///< DCD state: 1=Active, 0=Inactive + unsigned int ri : 1; ///< RI state: 1=Active, 0=Inactive +} ARM_USART_MODEM_STATUS; + + +/****** USART Event *****/ +#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data +#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed +#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed +#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) +#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) +#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow +#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) +#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive +#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive +#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive +#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) +#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) +#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) +#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) + + +// Function documentation +/** + \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) + \brief Get driver version. + \return \ref ARM_DRIVER_VERSION + + \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) + \brief Get driver capabilities + \return \ref ARM_USART_CAPABILITIES + + \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) + \brief Initialize USART Interface. + \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent + \return \ref execution_status + + \fn int32_t ARM_USART_Uninitialize (void) + \brief De-initialize USART Interface. + \return \ref execution_status + + \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) + \brief Control USART Interface Power. + \param[in] state Power state + \return \ref execution_status + + \fn int32_t ARM_USART_Send (const void *data, uint32_t num) + \brief Start sending data to USART transmitter. + \param[in] data Pointer to buffer with data to send to USART transmitter + \param[in] num Number of data items to send + \return \ref execution_status + + \fn int32_t ARM_USART_Receive (void *data, uint32_t num) + \brief Start receiving data from USART receiver. + \param[out] data Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to receive + \return \ref execution_status + + \fn int32_t ARM_USART_Transfer (const void *data_out, + void *data_in, + uint32_t num) + \brief Start sending/receiving data to/from USART transmitter/receiver. + \param[in] data_out Pointer to buffer with data to send to USART transmitter + \param[out] data_in Pointer to buffer for data to receive from USART receiver + \param[in] num Number of data items to transfer + \return \ref execution_status + + \fn uint32_t ARM_USART_GetTxCount (void) + \brief Get transmitted data count. + \return number of data items transmitted + + \fn uint32_t ARM_USART_GetRxCount (void) + \brief Get received data count. + \return number of data items received + + \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) + \brief Control USART Interface. + \param[in] control Operation + \param[in] arg Argument of operation (optional) + \return common \ref execution_status and driver specific \ref usart_execution_status + + \fn ARM_USART_STATUS ARM_USART_GetStatus (void) + \brief Get USART status. + \return USART status \ref ARM_USART_STATUS + + \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) + \brief Set USART Modem Control line state. + \param[in] control \ref ARM_USART_MODEM_CONTROL + \return \ref execution_status + + \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) + \brief Get USART Modem Status lines state. + \return modem status \ref ARM_USART_MODEM_STATUS + + \fn void ARM_USART_SignalEvent (uint32_t event) + \brief Signal USART Events. + \param[in] event \ref USART_events notification mask + \return none +*/ + +typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. + + +/** +\brief USART Device Driver Capabilities. +*/ +typedef struct _ARM_USART_CAPABILITIES { + unsigned int asynchronous : 1; ///< supports UART (Asynchronous) mode + unsigned int synchronous_master : 1; ///< supports Synchronous Master mode + unsigned int synchronous_slave : 1; ///< supports Synchronous Slave mode + unsigned int single_wire : 1; ///< supports UART Single-wire mode + unsigned int irda : 1; ///< supports UART IrDA mode + unsigned int smart_card : 1; ///< supports UART Smart Card mode + unsigned int smart_card_clock : 1; ///< Smart Card Clock generator available + unsigned int flow_control_rts : 1; ///< RTS Flow Control available + unsigned int flow_control_cts : 1; ///< CTS Flow Control available + unsigned int event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE + unsigned int event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT + unsigned int rts : 1; ///< RTS Line: 0=not available, 1=available + unsigned int cts : 1; ///< CTS Line: 0=not available, 1=available + unsigned int dtr : 1; ///< DTR Line: 0=not available, 1=available + unsigned int dsr : 1; ///< DSR Line: 0=not available, 1=available + unsigned int dcd : 1; ///< DCD Line: 0=not available, 1=available + unsigned int ri : 1; ///< RI Line: 0=not available, 1=available + unsigned int event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS + unsigned int event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR + unsigned int event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD + unsigned int event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI +} ARM_USART_CAPABILITIES; + + +/** +\brief Access structure of the USART Driver. +*/ +typedef struct _ARM_DRIVER_USART { + ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. + ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. + int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. + int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. + int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. + int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. + int32_t (*Receive) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. + int32_t (*Transfer) (const void *data_out, + void *data_in, + uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. + uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. + uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. + int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. + ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. + int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. + ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. +} const ARM_DRIVER_USART; + +#endif /* __DRIVER_USART_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h new file mode 100644 index 000000000..fb0b30847 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/GSPI.h @@ -0,0 +1,177 @@ +/****************************************************************************** +* @file GSPI.h +******************************************************************************* +* # License +* Copyright 2023,2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + + +#ifndef __GSPI_H__ +#define __GSPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_pll.h" +#include "Driver_SPI.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" + + + +/* Current driver status flag definition */ +#define SPI_INITIALIZED (1 << 0) // SPI initialized +#define SPI_POWERED (1 << 1) // SPI powered on +#define SPI_CONFIGURED (1 << 2) // SPI configured +#define SPI_DATA_LOST (1 << 3) // SPI data lost occurred +#define SPI_MODE_FAULT (1 << 4) // SPI mode fault occurred +#define RSI_MUTLI_SLAVE_SELECT_ERROR -7 + +/** + * Macro defines for GSPI MANUAL STATUS Register + */ + +#define GSPI_MANUAL_STATUS_BITMASK 0x07AF /*!< GSPI Manual Status reg bitmask*/ +#define GSPI_BUSY_F 0x01 /*!< A read,write or dummy cycle operation is in process in manual mode*/ +#define GSPI_FIFO_FULL_WFIFO_S 0x02 /*!< Full status indication for Wfifo in manual mode*/ +#define GSPI_FIFO_AFULL_WFIFO_S 0x04 /*!< AFull status indication for Wfifo in manual mode*/ +#define GSPI_FIFO_EMPTY_WFIFO_S 0x08 /*!< Empty status indication for Wfifo in manual mode*/ +#define GSPI_FIFO_EMPTY_RFIFO_S 0x80 /*!< Empty status indication for Rfifo in manual mode*/ +#define GSPI_FIFO_AEMPTY_WFIFO_S 0x100 /*!< AEmpty status indication for Rfifo in manual mode*/ +#define GSPI_MAN_CSN 0x400 /*!< Status of chip select signal*/ + +/** + * Macro defines for GSPI INTR MASK Register + */ +#define GSPI_INTR_MASK_BITMASK 0x7F /*!< GSPI Interrupt mask reg bitmask*/ +#define GSPI_INTR_MASK_BIT 0x01 /*!< Mask the GSPI intr*/ +#define GSPI_FIFO_AEMPTY_RFIFO_MASK 0x02 /*!< read fifo almost empty intr mask */ +#define GSPI_FIFO_AFULL_RFIFO_MASK 0x04 /*!< read fifo almost full intr mask*/ +#define GSPI_FIFO_AEMPTY_WFIFO_MASK 0x08 /*!< write fifo almost empty intr mask*/ +#define GSPI_FIFO_AFULL_WFIFO_MASK 0x10 /*!< Write Fifo almost full intr mask*/ +#define GSPI_FIFO_FULL_WFIFO_MASK 0x20 /*!< write fifo is full intr mask*/ +#define GSPI_FIFO_EMPTY_RFIFO_MASK 0x40 /*!< read fifo is empty intr mask*/ +/** + * Macro defines for GSPI INTR UNMASK Register + */ +#define GSPI_INTR_UNMASK_BITMASK 0x7F /*!< GSPI Interrupt Unmask reg bitmask*/ +#define GSPI_INTR_UNMASK_BIT 0x01 /*!< Unmask the GSPI intr*/ +#define GSPI_FIFO_AEMPTY_RFIFO_UNMASK 0x02 /*!< read fifo almost empty intr unmask */ +#define GSPI_FIFO_AFULL_RFIFO_UNMASK 0x04 /*!< read fifo almost full intr unmask*/ +#define GSPI_FIFO_AEMPTY_WFIFO_UNMASK 0x08 /*!< write fifo almost empty intr unmask*/ +#define GSPI_FIFO_AFULL_WFIFO_UNMASK 0x10 /*!< Write Fifo almost full intr unmask*/ +#define GSPI_FIFO_FULL_WFIFO_UNMASK 0x20 /*!< write fifo is full intr unmask*/ +#define GSPI_FIFO_EMPTY_RFIFO_UNMASK 0x40 /*!< read fifo is empty intr unmask*/ + +#define GSPI_CS0 0 +#define GSPI_CS1 1 +#define GSPI_CS2 2 + +// SPI DMA +typedef struct _SPI_DMA +{ + RSI_UDMA_CHA_CFG_T chnl_cfg; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} GSPI_DMA; +/* SPI status */ +typedef struct _SPI_STATUS { + uint8_t busy; // Transmitter/Receiver busy flag + uint8_t data_lost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint8_t mode_fault; // Mode fault detected; optional (cleared on start of transfer operation) +} GSPI_STATUS; + +/* SPI Information (Run-time) */ +typedef struct _SPI_INFO { + ARM_SPI_SignalEvent_t cb_event; // Event Callback + GSPI_STATUS status; // Status flags + uint8_t state; // Current SPI state + uint32_t mode; // Current SPI mode +} GSPI_INFO; + +/* SPI Transfer Information (Run-Time) */ +typedef struct _SPI_TRANSFER_INFO { + uint32_t num; // Total number of transfers + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint32_t dump_val; // Variable for dumping DMA data + uint16_t def_val; // Default transfer value +} GSPI_TRANSFER_INFO; + +/* SPI Pins Configuration */ +typedef const struct _GSPI_PIN { + uint8_t port; ///< SPI GPIO port + uint8_t pin; ///< SPI GPIO pin + uint8_t mode; ///< SPI GPIO mode + uint8_t pad_sel; ///< SPI GPIO pad selection +}GSPI_PIN; + +// SPI Input/Output Configuration +typedef struct GSPI_IO_PINS { + GSPI_PIN *clock; + GSPI_PIN *cs0; +#ifdef GSPI_MULTI_SLAVE + GSPI_PIN *cs1; + GSPI_PIN *cs2; +#endif + GSPI_PIN *mosi; + GSPI_PIN *miso; +} GSPI_IO; + +typedef struct __GSPI_FIFO_THRESHOLDS { + uint8_t txdma_arb_size; + uint8_t rxdma_arb_size; + uint8_t gspi_afull_threshold ; + uint8_t gspi_aempty_threshold; +}GSPI_FIFO_THRESHOLDS; + +/* SPI Resources */ +typedef const struct { + GSPI0_Type *reg; // SPI peripheral register interface + IRQn_Type irq_num; // SPI IRQ number + GSPI_DMA *rx_dma; // Receive stream register interface + GSPI_DMA *tx_dma; // Transmit stream register interface + GSPI_INFO *info; // SPI Run-time information + GSPI_TRANSFER_INFO *xfer; // SPI transfer information + GSPI_IO io; + GSPI_CLK_SRC_SEL_T clock_source; + GSPI_FIFO_THRESHOLDS *threshold; + uint32_t cs_en; +} GSPI_RESOURCES; + +void RSI_GSPI_SetSlaveSelectNumber(uint8_t slavenumber); +uint8_t RSI_GSPI_GetSlaveSelectNumber(void); +ARM_DRIVER_VERSION GSPI_MASTER_GetVersion(void); +uint8_t RSI_GSPI_GetSlaveSelectNumber(void); +ARM_SPI_CAPABILITIES GSPI_MASTER_GetCapabilities(void); +void GSPI_WriteDummyByte(void); +#ifdef __cplusplus +} +#endif +#endif // __GSPI_H__ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h new file mode 100644 index 000000000..e818e3547 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/I2C.h @@ -0,0 +1,300 @@ +/* ----------------------------------------------------------------------------- + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 29. March 2016 + * $Revision: V2.6 + * + * Project: Inter Integrated Circuit(I2C) Definitions for Silicon Labs MCU + * -------------------------------------------------------------------------- */ + +#ifndef __I2C_H +#define __I2C_H + +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "Driver_I2C.h" +#include "rsi_ccp_common.h" + + +/* I2C Interrupt Events */ +#define RSI_I2C_EVENT_RECEIVE_UNDER (1UL << 0) /*!< read the receive buffer when it is empty inerrupt */ +#define RSI_I2C_EVENT_RECEIVE_OVER (1UL << 1) /*!< receive buffer is completely filled interrupt */ +#define RSI_I2C_EVENT_RECEIVE_FULL (1UL << 2) /*!< receive buffer above the RX_TL threshold interrupt */ +#define RSI_I2C_EVENT_TRANSMIT_OVER (1UL << 3) /*!< issue write command after transmit buffer is filled completely */ +#define RSI_I2C_EVENT_TRANSMIT_EMPTY (1UL << 4) /*!< TX FIFO is empty interrupt */ +#define RSI_I2C_EVENT_READ_REQ (1UL << 5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ +#define RSI_I2C_EVENT_TRANSMIT_ABRT (1UL << 6) /*!< Transmit abort interrupt */ +#define RSI_I2C_EVENT_RECEIVE_DONE (1UL << 7) /*!< receive done interrupt */ +#define RSI_I2C_EVENT_ACTIVITY_ON_BUS (1UL << 8) /*!< I2C activity interrupt */ +#define RSI_I2C_EVENT_STOP_DETECT (1UL << 9) /*!< Stop condition on bus detection interrupt */ +#define RSI_I2C_EVENT_START_DETECT (1UL << 10) /*!< START or RESTART condition interrupt */ +#define RSI_I2C_EVENT_GENERAL_CALL (1UL << 11) /*!< General call interrupt */ +#define RSI_I2C_EVENT_RESTART_DET (1UL << 12) /*!< RESTART condition in slave mode */ +#define RSI_I2C_EVENT_MST_ON_HOLD (1UL << 13) /*!< master is holding the bus and the Tx FIFO is empty */ +#define RSI_I2C_EVENT_SCL_STUCK_AT_LOW (1UL << 14) + +#define I2C_RECEIVE_UNDER (0) /*!< read the receive buffer when it is empty inerrupt */ +#define I2C_RECEIVE_OVER (1) /*!< receive buffer is completely filled interrupt */ +#define I2C_RECEIVE_FULL (2) /*!< receive buffer above the RX_TL threshold interrupt */ +#define I2C_TRANSMIT_OVER (3) /*!< issue write command after transmit buffer is filled completely */ +#define I2C_TRANSMIT_EMPTY (4) /*!< TX FIFO is empty interrupt */ +#define I2C_READ_REQ (5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ +#define I2C_TRANSMIT_ABRT (6) /*!< Transmit abort interrupt */ +#define I2C_RECEIVE_DONE (7) /*!< receive done interrupt */ +#define I2C_ACTIVITY_ON_BUS (8) /*!< I2C activity interrupt */ +#define I2C_STOP_DETECT (9) /*!< Stop condition on bus detection interrupt */ +#define I2C_START_DETECT (10) /*!< START or RESTART condition interrupt */ +#define I2C_GENERAL_CALL (11) /*!< General call interrupt */ +#define I2C_RESTART_DET (12) /*!< RESTART condition in slave mode */ +#define I2C_MST_ON_HOLD (13) /*!< master is holding the bus and the Tx FIFO is empty */ +#define I2C_SCL_STUCK_AT_LOW (14) + +/* TX Abort Sources */ +#define I2C_TX_ABRT_7B_ADDR_NOACK (15) +#define I2C_TX_ABRT_10ADDR1_NOACK (16) +#define I2C_TX_ABRT_10ADDR2_NOACK (17) +#define I2C_TX_ABRT_TXDATA_NOACK (18) +#define I2C_TX_ABRT_GCALL_NOACK (19) +#define I2C_TX_ABRT_GCALL_READ (20) +#define I2C_TX_ABRT_HS_ACKDET (21) +#define I2C_TX_ABRT_SBYTE_ACKDET (22) +#define I2C_TX_ABRT_HS_NORSTRT (23) +#define I2C_TX_ABRT_SBYTE_NORSTRT (24) +#define I2C_TX_ABRT_10B_RD_NORSTRT (25) +#define I2C_TX_ABRT_MASTER_DIS (26) +#define I2C_TX_ARB_LOST (27) +#define I2C_TX_ABRT_SLVFLUSH_TXFIFO (28) +#define I2C_TX_ABRT_SLV_ARBLOST (29) +#define I2C_TX_ABRT_SLVRD_INTX (30) +#define I2C_TX_ABRT_USER_ABRT (31) +#define I2C_TX_ABRT_SDA_STUCK_AT_LOW (32) +#define I2C_TX_ABRT_DEVICE_NOACK (33) +#define I2C_TX_ABRT_DEVICE_SLVADDR_NOACK (34) +#define I2C_TX_ABRT_DEVICE_WRITE (35) +#define I2C_TX_TX_FLUSH_CNT (36) + +#define SLAVE_ADDR_CHECK_ARG 0x01 +#define SLAVE_RX_ARG 0x02 +#define SLAVE_TX_ARG 0x03 + +#define NACK 1 +#define ACK 0 + +#define F_RX_UNDER 0 +#define F_RX_OVER 1 +#define F_RX_FULL 2 +#define F_TX_OVER 3 +#define F_TX_EMPTY 4 +#define F_RD_REQ 5 +#define F_TX_ABRT 6 +#define F_RX_DONE 7 +#define F_ACTIVITY 8 +#define F_STOP_DET 9 +#define F_START_DET 10 +#define F_GEN_CALL 11 +#define F_RESTART_DET 12 +#define F_MST_ON_HOLD 13 + +#define I2C_ACTIVITY (1UL << 0) +#define I2C_TFNF (1UL << 1) +#define I2C_TFE (1UL << 2) +#define I2C_RFNE (1UL << 3) +#define I2C_RFF (1UL << 4) +#define I2C_MST_ACTIVITY (1UL << 5) +#define I2C_SLV_ACTIVITY (1UL << 6) + + +#define I2C_STAT_ACTIVITY 0 +#define I2C_STAT_TFNF 1 +#define I2C_STAT_TFE 2 +#define I2C_STAT_RFNE 3 +#define I2C_STAT_RFF 4 +#define I2C_STAT_MST_ACTIVITY 5 +#define I2C_STAT_SLV_ACTIVITY 6 +#define I2C_TX_ABRT_SOURCE 7 + +#define TX_ABRT_7B_ADDR_NOACK (1UL << 0) +#define TX_ABRT_10ADDR1_NOACK (1UL << 1) +#define TX_ABRT_10ADDR2_NOACK (1UL << 2) +#define TX_ABRT_TXDATA_NOACK (1UL << 3) +#define TX_ABRT_GCALL_NOACK (1UL << 4) +#define TX_ABRT_GCALL_READ (1UL << 5) +#define TX_ABRT_HS_ACKDET (1UL << 6) +#define TX_ABRT_SBYTE_ACKDET (1UL << 7) +#define TX_ABRT_HS_NORSTRT (1UL << 8) +#define TX_ABRT_SBYTE_NORSTRT (1UL << 9) +#define TX_ABRT_10B_RD_NORSTRT (1UL << 10) +#define TX_ABRT_MASTER_DIS (1UL << 11) +#define TX_ARB_LOST (1UL << 12) +#define TX_ABRT_SLVFLUSH_TXFIFO (1UL << 13) +#define TX_ABRT_SLV_ARBLOST (1UL << 14) +#define TX_ABRT_SLVRD_INTX (1UL << 15) +#define TX_ABRT_USER_ABRT (1UL << 16) +#define TX_ABRT_SDA_STUCK_AT_LOW (1UL << 17) +#define TX_ABRT_DEVICE_NOACK (1UL << 18) +#define TX_ABRT_DEVICE_SLVADDR_NOACK (1UL << 19) +#define TX_ABRT_DEVICE_WRITE (1UL << 20) +#define TX_TX_FLUSH_CNT (1UL << 23) + +/* bit defines */ +#define I2C2_BUS_CLK_ENABLE (1UL << 8) +#define I2C_STATIC_CLK_EN (1UL << 17) +#define UDMA_HCLK_ENBALE (1UL << 6) +#define ULP_UDMA_STATIC_CLK_EN (1UL << 17) +#define I2C2_STATIC_CLK_EN (1UL << 18) +#define I2C_FIFO_DEPTH 8 + + +/* I2C example defines */ +#define CHNL_30 30 +#define CHNL_31 31 +#define PRIMARY 0 +#define ALTERNATE 1 + + +#define I2C_RESTART_EN 0x1 + +#define I2C_MST_ADDR_7BIT_MODE 0x0 +#define I2C_MST_ADDR_10BIT_MODE 0x1 +#define I2C_SLV_ADDR_7BIT_MODE 0x0 + +#define I2C_SLV_ADDR 0x50 + +#define I2C_SCL_LOW_CLK 0x6 +#define I2C_SCL_HIGH_CLK 0x1 + +#define I2C_TX_TL 0x1 +#define I2C_RX_TL 0x4 +#define ADDRESS_WIDTH 8 + +#define MULTI_PAGE_WRITE 1 +#define SINGLE_PAGE_WRITE 0 + +#define BIT_WIDTH_8 0 +#define BIT_WIDTH_16 1 +#define BIT_WIDTH_32 2 + +#define READ_CMD 1 +#define WRITE_CMD 0 + +#define TX_EN 1 +#define RX_EN 1 + +#define I2C_DMA_TX_REQ 0x2 +#define I2C_DMA_RX_REQ 0x2 +#define DMA_ACK (1UL << 7) + +/* PAD pin selection */ +#define I2C0_PAD_SEL_6_8 1 +#define GPIO_6_REN 6 +#define GPIO_8_REN 8 + +#define I2CM_BLOCKING_XFER 1 +#define I2CM_NONBLOCKING_XFER 0 + + +#define SS_MIN_SCL_HIGH 5200 +#define SS_MIN_SCL_LOW 4700 +#define FS_MIN_SCL_HIGH 1160 +#define FS_MIN_SCL_LOW 1300 +#define HS_MIN_SCL_HIGH_400PF 274 +#define HS_MIN_SCL_LOW_400PF 333 +#define HS_MIN_SCL_HIGH_100PF 60 +#define HS_MIN_SCL_LOW_100PF 120 + +#define RSI_I2C_HIGH_SPEED 0x3 + +/* I2C Driver state flags */ +#define I2C_FLAG_INIT (1 << 0) // Driver initialized +#define I2C_FLAG_POWER (1 << 1) // Driver power on +#define I2C_FLAG_SETUP (1 << 2) // Master configured, clock set +#define I2C_FLAG_SLAVE_RX (1 << 3) // Slave receive registered +#define I2C_FLAG_STOP_DET (1 << 4) + +/* I2C Stalled Status flags */ +#define I2C_MASTER (1 << 0) // Master stalled +#define I2C_SLAVE_TX (1 << 1) // Slave stalled on transmit +#define I2C_SLAVE_RX (1 << 2) // Slave stalled on receive +#define I2C_SLAVE (I2C_SLAVE_TX | I2C_SLAVE_RX) + +/* I2C Interrupt Events */ +#define I2C_EVENT_RECEIVE_UNDER (1UL << 0) /*!< read the receive buffer when it is empty inerrupt */ +#define I2C_EVENT_RECEIVE_OVER (1UL << 1) /*!< receive buffer is completely filled interrupt */ +#define I2C_EVENT_RECEIVE_FULL (1UL << 2) /*!< receive buffer above the RX_TL threshold interrupt */ +#define I2C_EVENT_TRANSMIT_OVER (1UL << 3) /*!< issue write command after transmit buffer is filled completely */ +#define I2C_EVENT_TRANSMIT_EMPTY (1UL << 4) /*!< TX FIFO is empty interrupt */ +#define I2C_EVENT_READ_REQ (1UL << 5) /*!< In slave mode holds SCL if another I2C master is attempting to read */ +#define I2C_EVENT_TRANSMIT_ABRT (1UL << 6) /*!< Transmit abort interrupt */ +#define I2C_EVENT_RECEIVE_DONE (1UL << 7) /*!< receive done interrupt */ +#define I2C_EVENT_ACTIVITY_ON_BUS (1UL << 8) /*!< I2C activity interrupt */ +#define I2C_EVENT_STOP_DETECT (1UL << 9) /*!< Stop condition on bus detection interrupt */ +#define I2C_EVENT_START_DETECT (1UL << 10) /*!< START or RESTART condition interrupt */ +#define I2C_EVENT_GENERAL_CALL (1UL << 11) /*!< General call interrupt */ +#define I2C_EVENT_RESTART_DET (1UL << 12) /*!< RESTART condition in slave mode */ +#define I2C_EVENT_MST_ON_HOLD (1UL << 13) /*!< master is holding the bus and the Tx FIFO is empty */ +#define I2C_EVENT_SCL_STUCK_AT_LOW (1UL << 14) + +#define TRANSMITTER 0 +#define RECEIVER 1 + +void I2C0_IRQHandler (void); +void I2C1_IRQHandler (void); +void I2C2_IRQHandler (void); +/* I2C Control Information */ +typedef struct +{ + ARM_I2C_SignalEvent_t cb_event; // Event callback + ARM_I2C_STATUS status; // Status flags + uint8_t flags; // Control and state flags + uint16_t sla_rw; // Slave address and RW bit + bool pending; // Transfer pending (no STOP) + uint8_t stalled; // Stall mode status flags + uint8_t con_aa; // I2C slave CON flag + int32_t cnt; // Master transfer count + uint8_t *data; // Master data to transfer + uint32_t num; // Number of bytes to transfer + uint8_t *sdata; // Slave data to transfer + uint32_t snum; // Number of bytes to transfer +} I2C_CTRL; + +typedef const struct _I2C_PIN { + uint8_t port; ///< CAN GPIO port + uint8_t pin; ///< CAN GPIO pin + uint8_t mode; ///< CAN GPIO mode + uint8_t pad_sel; ///< CAN GPIO pad selection +}I2C_PIN; + +typedef const struct _I2C_IO { + I2C_PIN *scl; + I2C_PIN *sda; +} I2C_IO; + +/* I2C Resource Configuration */ +typedef struct +{ + I2C0_Type *reg; // I2C register interface + IRQn_Type i2c_ev_irq; // I2C Event IRQ Numbe + I2C_CTRL *ctrl; // Run-Time control information + I2C_IO io; //pins +} I2C_RESOURCES; + +#endif + diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h new file mode 100644 index 000000000..dcad77053 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SAI.h @@ -0,0 +1,255 @@ +/* ----------------------------------------------------------------------------- + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 9. Dec 2014 + * $Revision: V1.00 + * + * Project: SAI (Serial Audio Interface) Driver definitions + * -------------------------------------------------------------------------- */ + +/* History: + * Version 1.00 + * Initial release + */ + +#ifndef __SAI_H__ +#define __SAI_H__ + +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "Driver_SAI.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" + + +/****** I2S Events *****/ +#define RSI_I2S_EVENT_RXDA 0x0 /*!< Receive Data available event */ +#define RSI_I2S_EVENT_RXDATA_OVERRUN 0x1 /*!< RX data overrun event */ +#define RSI_I2S_EVENT_TRANSMIT_EMPTY 0x2 /*!< TX FIFO empty event */ +#define RSI_I2S_EVENT_TXDATA_OVERRUN 0x3 /*!< TX data overrun event */ +#define RSI_I2S_EVENT_DMA_ENABLE 0x4 /*!< DMA enable event */ + +/****** I2S Status Flags *****/ +#define I2S_STAT_RXDA (1UL << 0) /*!< RXDA interrupt flag */ +#define I2S_STAT_RXDATA_OVERRUN (1UL << 1) /*!< RXDO interrupt flag */ +#define I2S_STAT_TRANSMIT_EMPTY (1UL << 4) /*!< TXFE interrupt flag */ +#define I2S_STAT_TXDATA_OVERRUN (1UL << 5) /*!< TXFO interrupt flag */ + +#define F_RXDA 0x01 +#define F_RXFO 0x02 +#define F_TXFE 0x03 +#define F_TXFO 0x04 + +#define F_RXDAM (1UL << 0) +#define F_RXFOM (1UL << 1) +#define F_TXFEM (1UL << 4) +#define F_TXFOM (1UL << 5) + +#define MASTER 0x1 +#define SLAVE 0x0 +#define RES_12 0x1 +#define RES_16 0x2 +#define RES_20 0x3 +#define RES_24 0x4 + +#define MISC_SOFT_SET_REG_2 (*((uint32_t volatile *)(0x46008000UL + 0x34))) +#define CHNL_0 0 +#define CHNL_1 1 + +/* Number of sclk cycles for which the word select + line (ws_out) stays in the left or right sample mode */ +#define WSS_24_CYCLES 0x1 +#define WSS_16_CYCLES 0x0 +#define WSS_32_CYCLES 0x2 + +#define SCLKG_12_CYCLES 0x1 +#define SCLKG_16_CYCLES 0x2 +#define SCLKG_20_CYCLES 0x3 +#define SCLKG_24_CYCLES 0x4 +#define SCLKG_NO_GATE 0x0 + + +#define RX_BLOCK_EN 0x1 +#define TX_BLOCK_EN 0x1 + +#define RES_12_BIT 0x1 +#define RES_16_BIT 0x2 +#define RES_20_BIT 0x3 +#define RES_24_BIT 0x4 +#define RES_32_BIT 0x5 + +#define I2S_FIFO_DEPTH 8 +#define I2S_TX_TL 7 +#define I2S_RX_TL 7 + +#define MASTER 0x1 +#define SLAVE 0x0 + +#define PCM_EN 1 +#define PCM_DIS 0 +#define FSYNC_EN 1 +#define FSYNC_DIS 0 + +#define ULP_I2S_CLK_SEL 8 +#define ULP_I2S_CLK_DIV_FACT 1 +#define M4_I2S_CLK_SEL 0 +#define M4_I2S_CLK_DIV_FACT 0 + +/** + \brief Macro defines for MISC_SOFT_SET3_REG + */ +#define PCM_ENA (1UL << 0) +#define PCM_FSYNC_START_M (1UL << 1) +#define PCM_BIT_RES_8_SET (0 << 2) +#define PCM_BIT_RES_12_SET (1 << 2) +#define PCM_BIT_RES_16_SET (2 << 2) +#define PCM_BIT_RES_24_SET (3 << 2) + +/** + \brief Macro defines for MISC_SOFT_CLR3_REG + */ +#define PCMEN (1UL << 0) +#define PCM_FSYNCSTART (1UL << 1) +#define PCM_BIT_RES_8_CLR (0 << 2) +#define PCM_BIT_RES_12_CLR (1 << 2) +#define PCM_BIT_RES_16_CLR (2 << 2) +#define PCM_BIT_RES_24_CLR (3 << 2) + +/** + \brief Macro defines for MISC_CFG_MISC_CTRL1 + */ +#define I2S_MASTER_SLAVE_MODE (1 << 23) /*!< Sets I2S/ PCM master mode */ +#define ARM_SOFT_RESET (1 << 19) + + +/** + \brief Macro defines for ULP_MISC_SOFT_SET_REG + */ +#define ULP_I2S_CLK_ENABLE (1UL << 6) +#define ULP_PCM_FSYNC_START (1UL << 1) +#define ULP_PCM_ENABLE (1UL << 0) +#define ULP_PCM_BIT_RES_8_SET (0 << 2) +#define ULP_PCM_BIT_RES_12_SET (1 << 2) +#define ULP_PCM_BIT_RES_16_SET (2 << 2) +#define ULP_PCM_BIT_RES_24_SET (3 << 2) + +#define I2S_BLOCKING_XFER 1 +#define I2S_NONBLOCKING_XFER 0 + +// I2S flags +#define I2S_FLAG_INITIALIZED (1U) +#define I2S_FLAG_POWERED (1U << 1) +#define I2S_FLAG_CONFIGURED (1U << 2) + +#define INTR_MASK 1 +#define INTR_UNMASK 0 + +#define I2S_PROTOCOL 0 +#define PCM_PROTOCOL 1 + + + +// I2S Stream Information (Run-Time) +typedef struct _I2S_STREAM_INFO +{ + uint32_t num; // Total number of data to be transmited/received + uint8_t *buf; // Pointer to data buffer + uint32_t cnt; // Number of data transmited/receive + uint8_t data_bits; // Number of data bits + uint8_t master; // Master flag + uint8_t residue_num; + uint8_t residue_buf[4]; + uint8_t residue_cnt; +} I2S_STREAM_INFO; + +typedef struct _I2S_STATUS { + uint8_t tx_busy; // Transmitter busy flag + uint8_t rx_busy; // Receiver busy flag + uint8_t tx_underflow; // Transmit data underflow detected (cleared on start of next send operation) + uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) + uint8_t frame_error; // Sync Frame error detected (cleared on start of next send/receive operation) +} I2S_STATUS; + +// I2S Information (Run-Time) +typedef struct _I2S_INFO +{ + ARM_SAI_SignalEvent_t cb_event; // Event callback + I2S_STATUS status; // Status flags + I2S_STREAM_INFO tx; // Transmit information + I2S_STREAM_INFO rx; // Receive information +} I2S_INFO; + +// I2S DMA +typedef struct _I2S_DMA +{ + RSI_UDMA_CHA_CONFIG_DATA_T control; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} I2S_DMA; + +// I2S Clock Config +typedef struct _I2S_CLK +{ + uint8_t clk_src; // I2S Clock Source + uint8_t div_fact; // Clock Division factor +} I2S_CLK; + +/* Pins Configuration */ +typedef const struct _I2S_PIN { + uint8_t port; ///< SPI GPIO port + uint8_t pin; ///< SPI GPIO pin + uint8_t mode; ///< SPI GPIO mode + uint8_t pad_sel; ///< SPI GPIO pad selection +}I2S_PIN; + +// Input/Output Configuration +typedef struct I2S_IO_PINS { + I2S_PIN *sclk; + I2S_PIN *wsclk; + I2S_PIN *din0; + I2S_PIN *dout0; + I2S_PIN *din1; + I2S_PIN *dout1; +}I2S_IO; + +// I2S Reseurces definitions +typedef struct +{ + ARM_SAI_CAPABILITIES capabilities; // Capabilities + I2S0_Type *reg; // Pointer to I2S peripheral + IRQn_Type irq_num; // I2S IRQ Number + I2S_DMA *dma_tx; // I2S TX DMA configuration + I2S_DMA *dma_rx; // I2S RX DMA configuration + uint8_t tx_fifo_level; // I2S transmit fifo level + uint8_t rx_fifo_level; // I2S receive fifo level + uint8_t xfer_chnl; + I2S_INFO *info; // Run-Time information + uint32_t flags; + uint8_t protocol; + I2S_CLK *clk; + I2S_IO io; +} I2S_RESOURCES; +void IRQ064_Handler (void); +void IRQ014_Handler (void); + + +#endif /* __DRIVER_SAI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h new file mode 100644 index 000000000..6d8be7510 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/SPI.h @@ -0,0 +1,431 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 02. March 2016 + * $Revision: V2.2 + * + * Project: SPI Driver Definitions for Silicon Labs MCU + * -------------------------------------------------------------------------- */ + +#ifndef __SPI_H +#define __SPI_H + +#include "rsi_pll.h" +#include "Driver_SPI.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" +#include "rsi_ulpss_clk.h" +#ifdef SSI_INSTANCE_CONFIG +#include "sl_ssi_common_config.h" +#elif SSI_CONFIG +#include "sl_si91x_ssi_common_config.h" +#endif + +#define SSI_DISABLE 0x00 /*!< Disable the SSI Operation*/ +#define SSI_ENABLE 0x01 /*!< Enable the SSI Operation*/ +#define TXEIM 0x1 +#define TXOIM 0x2 +#define RXUIM 0x4 +#define RXOIM 0x8 +#define RXFIM 0x10 +#define TRANSMIT_AND_RECEIVE 0x00 +#define TRANSMIT_ONLY 0x01 +#define RECEIVE_ONLY 0x02 +#define STANDARD_SPI_FORMAT 0x00 +#define MOTOROLA_SPI 0x00 +#define TEXAS_INSTRUMENTS_SSP 0x01 +#define NATIONAL_SEMICONDUCTORS_MICROWIRE 0x02 +#define SPI_MASTER_MODE 1U +#define SPI_SLAVE_MODE 2U +#define SPI_ULP_MASTER_MODE 3U +#define SSI_INSTANCE_BIT 30 // SSI Instance validation bits +#define SSI_INSTANCE_MASK 0x3FFFFFFF // Mask value for SSI instance +#define SSI_MASTER_INSTANCE 0 // SSI Master Instance +#define SSI_SLAVE_INSTANCE 1 // SSI Slave Instance +#define SSI_ULP_MASTER_INSTANCE 2 // SSI ULP Master Instance + +#define SPI_ISR_TX_FIFO_EMPTY BIT(0) +#define SPI_ISR_TX_FIFO_OVERFLOW BIT(1) +#define SPI_ISR_RX_FIFO_UNDERFLOW BIT(2) +#define SPI_ISR_RX_FIFO_OVERFLOW BIT(3) +#define SPI_ISR_RX_FIFO_FULL BIT(4) + + +ARM_DRIVER_VERSION SPI_GetVersion(void); +ARM_SPI_CAPABILITIES SPI_GetCapabilities(void); +void IRQ047_Handler(void) ; +void IRQ044_Handler(void); +void IRQ016_Handler(void); +void mySPI_callback(uint32_t event); + +#if ((defined(RTE_Drivers_SSI_MASTER) || \ + defined(RTE_Drivers_SSI_SLAVE) || \ + defined(RTE_Drivers_SSI_ULP_MASTER)) \ + && (RTE_SSI_MASTER == 0) \ + && (RTE_SSI_SLAVE == 0) \ + && (RTE_SSI_ULP_MASTER == 0)) +#error "SPI not configured in RTE_Device_917.h!" +#endif + + +#if defined(RTE_SSI_MASTER) && (RTE_SSI_MASTER == 1) +#define SSI_MASTER 1U +// Configuring DMA thresholds based on SSI instances. +#ifdef SSI_INSTANCE_CONFIG +#if defined (SL_SSI_PRIMARY_DMA_CONFIG_ENABLE) && (SL_SSI_PRIMARY_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_MASTER_RX_DMA 1 +#define RTE_SSI_MASTER_TX_DMA 1 +#endif + +#if defined (SL_SSI_SECONDARY_DMA_CONFIG_ENABLE) && (SL_SSI_SECONDARY_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_SLAVE_RX_DMA 1 +#define RTE_SSI_SLAVE_TX_DMA 1 +#endif + +#if defined (SL_SSI_ULP_PRIMARY_DMA_CONFIG_ENABLE) && (SL_SSI_ULP_PRIMARY_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_ULP_MASTER_RX_DMA 1 +#define RTE_SSI_ULP_MASTER_TX_DMA 1 +#endif +// DMA threshold configuration based on SSI unknown instance name. +#elif SSI_CONFIG +#if defined (SL_SSI_MASTER_DMA_CONFIG_ENABLE) && (SL_SSI_MASTER_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_MASTER_RX_DMA 1 +#define RTE_SSI_MASTER_TX_DMA 1 +#endif + +#if defined (SL_SSI_SLAVE_DMA_CONFIG_ENABLE) && (SL_SSI_SLAVE_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_SLAVE_RX_DMA 1 +#define RTE_SSI_SLAVE_TX_DMA 1 +#endif + +#if defined (SL_SSI_ULP_MASTER_DMA_CONFIG_ENABLE) && (SL_SSI_ULP_MASTER_DMA_CONFIG_ENABLE == ENABLE) +#define RTE_SSI_ULP_MASTER_RX_DMA 1 +#define RTE_SSI_ULP_MASTER_TX_DMA 1 +#endif +#endif + +#if defined(RTE_SSI_MASTER_RX_DMA) && (RTE_SSI_MASTER_RX_DMA == 1) +#define SSI_MASTER_RX_DMA_Instance 1U +#define SSI_MASTER_RX_DMA_Channel RTE_SSI_MASTER_UDMA_RX_CH +#endif + +#if defined(RTE_SSI_MASTER_TX_DMA) && (RTE_SSI_MASTER_TX_DMA == 1) +#define SSI_MASTER_TX_DMA_Instance 1U +#define SSI_MASTER_TX_DMA_Channel RTE_SSI_MASTER_UDMA_TX_CH +#endif + +#if defined(RTE_SSI_MASTER_MISO) && (RTE_SSI_MASTER_MISO == 1) +#define SSI_MASTER_MISO_SEL 1U +#define SSI_MASTER_MISO_PORT RTE_SSI_MASTER_MISO_PORT +#define SSI_MASTER_MISO_PIN RTE_SSI_MASTER_MISO_PIN +#define SSI_MASTER_MISO_MODE RTE_SSI_MASTER_MISO_MODE +#define SSI_MASTER_MISO_PADSEL RTE_SSI_MASTER_MISO_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_MOSI) && (RTE_SSI_MASTER_MOSI == 1) +#define SSI_MASTER_MOSI_SEL 1U +#define SSI_MASTER_MOSI_PORT RTE_SSI_MASTER_MOSI_PORT +#define SSI_MASTER_MOSI_PIN RTE_SSI_MASTER_MOSI_PIN +#define SSI_MASTER_MOSI_MODE RTE_SSI_MASTER_MOSI_MODE +#define SSI_MASTER_MOSI_PADSEL RTE_SSI_MASTER_MOSI_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_SCK) && (RTE_SSI_MASTER_SCK == 1) +#define SSI_MASTER_SCK_SEL 1U +#define SSI_MASTER_SCK_PORT RTE_SSI_MASTER_SCK_PORT +#define SSI_MASTER_SCK_PIN RTE_SSI_MASTER_SCK_PIN +#define SSI_MASTER_SCK_MODE RTE_SSI_MASTER_SCK_MODE +#define SSI_MASTER_SCK_PADSEL RTE_SSI_MASTER_SCK_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS0) && (RTE_SSI_MASTER_CS0 == 1) +#define SSI_MASTER_CS0_SEL 1U +#define SSI_MASTER_CS0_PORT RTE_SSI_MASTER_CS0_PORT +#define SSI_MASTER_CS0_PIN RTE_SSI_MASTER_CS0_PIN +#define SSI_MASTER_CS0_MODE RTE_SSI_MASTER_CS0_MODE +#define SSI_MASTER_CS0_PADSEL RTE_SSI_MASTER_CS0_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS1) && (RTE_SSI_MASTER_CS1 == 1) +#define SSI_MASTER_CS1_SEL 1U +#define SSI_MASTER_CS1_PORT RTE_SSI_MASTER_CS1_PORT +#define SSI_MASTER_CS1_PIN RTE_SSI_MASTER_CS1_PIN +#define SSI_MASTER_CS1_MODE RTE_SSI_MASTER_CS1_MODE +#define SSI_MASTER_CS1_PADSEL RTE_SSI_MASTER_CS1_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS2) && (RTE_SSI_MASTER_CS2 == 1) +#define SSI_MASTER_CS2_SEL 1U +#define SSI_MASTER_CS2_PORT RTE_SSI_MASTER_CS2_PORT +#define SSI_MASTER_CS2_PIN RTE_SSI_MASTER_CS2_PIN +#define SSI_MASTER_CS2_MODE RTE_SSI_MASTER_CS2_MODE +#define SSI_MASTER_CS2_PADSEL RTE_SSI_MASTER_CS2_PADSEL +#endif + +#if defined(RTE_SSI_MASTER_CS3) && (RTE_SSI_MASTER_CS3 == 1) +#define SSI_MASTER_CS3_SEL 1U +#define SSI_MASTER_CS3_PORT RTE_SSI_MASTER_CS3_PORT +#define SSI_MASTER_CS3_PIN RTE_SSI_MASTER_CS3_PIN +#define SSI_MASTER_CS3_MODE RTE_SSI_MASTER_CS3_MODE +#define SSI_MASTER_CS3_PADSEL RTE_SSI_MASTER_CS3_PADSEL +#endif +#endif + +#if defined(RTE_SSI_SLAVE) && (RTE_SSI_SLAVE == 1) +#define SSI_SLAVE 1U + +#if defined(RTE_SSI_SLAVE_RX_DMA) && (RTE_SSI_SLAVE_RX_DMA == 1) +#define SSI_SLAVE_RX_DMA_Instance 1U +#define SSI_SLAVE_RX_DMA_Channel RTE_SSI_SLAVE_UDMA_RX_CH +#endif + +#if defined(RTE_SSI_SLAVE_TX_DMA) && (RTE_SSI_SLAVE_TX_DMA == 1) +#define SSI_SLAVE_TX_DMA_Instance 1U +#define SSI_SLAVE_TX_DMA_Channel RTE_SSI_SLAVE_UDMA_TX_CH +#endif + +#if defined(RTE_SSI_SLAVE_MISO) && (RTE_SSI_SLAVE_MISO == 1) +#define SSI_SLAVE_MISO_SEL 1U +#define SSI_SLAVE_MISO_PORT RTE_SSI_SLAVE_MISO_PORT +#define SSI_SLAVE_MISO_PIN RTE_SSI_SLAVE_MISO_PIN +#define SSI_SLAVE_MISO_MODE RTE_SSI_SLAVE_MISO_MODE +#define SSI_SLAVE_MISO_PADSEL RTE_SSI_SLAVE_MISO_PADSEL +#endif + +#if defined(RTE_SSI_SLAVE_MOSI) && (RTE_SSI_SLAVE_MOSI == 1) +#define SSI_SLAVE_MOSI_SEL 1U +#define SSI_SLAVE_MOSI_PORT RTE_SSI_SLAVE_MOSI_PORT +#define SSI_SLAVE_MOSI_PIN RTE_SSI_SLAVE_MOSI_PIN +#define SSI_SLAVE_MOSI_MODE RTE_SSI_SLAVE_MOSI_MODE +#define SSI_SLAVE_MOSI_PADSEL RTE_SSI_SLAVE_MOSI_PADSEL +#endif + +#if defined(RTE_SSI_SLAVE_SCK) && (RTE_SSI_SLAVE_SCK == 1) +#define SSI_SLAVE_SCK_SEL 1U +#define SSI_SLAVE_SCK_PORT RTE_SSI_SLAVE_SCK_PORT +#define SSI_SLAVE_SCK_PIN RTE_SSI_SLAVE_SCK_PIN +#define SSI_SLAVE_SCK_MODE RTE_SSI_SLAVE_SCK_MODE +#define SSI_SLAVE_SCK_PADSEL RTE_SSI_SLAVE_SCK_PADSEL +#endif + +#if defined(RTE_SSI_SLAVE_CS) && (RTE_SSI_SLAVE_CS == 1) +#define SSI_SLAVE_CS0_SEL 1U +#define SSI_SLAVE_CS0_PORT RTE_SSI_SLAVE_CS_PORT +#define SSI_SLAVE_CS0_PIN RTE_SSI_SLAVE_CS_PIN +#define SSI_SLAVE_CS0_MODE RTE_SSI_SLAVE_CS_MODE +#define SSI_SLAVE_CS0_PADSEL RTE_SSI_SLAVE_CS_PADSEL +#endif +#endif + +#if defined(RTE_SSI_ULP_MASTER) && (RTE_SSI_ULP_MASTER == 1) +#define SSI_ULP_MASTER 1U + +#if defined(RTE_SSI_ULP_MASTER_RX_DMA) && (RTE_SSI_ULP_MASTER_RX_DMA == 1) +#define SSI_ULP_MASTER_RX_DMA_Instance 1U +#define SSI_ULP_MASTER_RX_DMA_Channel RTE_SSI_ULP_MASTER_UDMA_RX_CH +#endif + +#if defined(RTE_SSI_ULP_MASTER_TX_DMA) && (RTE_SSI_ULP_MASTER_TX_DMA == 1) +#define SSI_ULP_MASTER_TX_DMA_Instance 1U +#define SSI_ULP_MASTER_TX_DMA_Channel RTE_SSI_ULP_MASTER_UDMA_TX_CH +#endif + +#if defined(RTE_SSI_ULP_MASTER_MISO) && (RTE_SSI_ULP_MASTER_MISO == 1) +#define SSI_ULP_MASTER_MISO_SEL 1U +#define SSI_ULP_MASTER_MISO_PORT RTE_SSI_ULP_MASTER_MISO_PORT +#define SSI_ULP_MASTER_MISO_PIN RTE_SSI_ULP_MASTER_MISO_PIN +#define SSI_ULP_MASTER_MISO_MODE RTE_SSI_ULP_MASTER_MISO_MODE +#endif + +#if defined(RTE_SSI_ULP_MASTER_MOSI) && (RTE_SSI_ULP_MASTER_MOSI == 1) +#define SSI_ULP_MASTER_MOSI_SEL 1U +#define SSI_ULP_MASTER_MOSI_PORT RTE_SSI_ULP_MASTER_MOSI_PORT +#define SSI_ULP_MASTER_MOSI_PIN RTE_SSI_ULP_MASTER_MOSI_PIN +#define SSI_ULP_MASTER_MOSI_MODE RTE_SSI_ULP_MASTER_MOSI_MODE +#endif + +#if defined(RTE_SSI_ULP_MASTER_SCK) && (RTE_SSI_ULP_MASTER_SCK == 1) +#define SSI_ULP_MASTER_SCK_SEL 1U +#define SSI_ULP_MASTER_SCK_PORT RTE_SSI_ULP_MASTER_SCK_PORT +#define SSI_ULP_MASTER_SCK_PIN RTE_SSI_ULP_MASTER_SCK_PIN +#define SSI_ULP_MASTER_SCK_MODE RTE_SSI_ULP_MASTER_SCK_MODE +#endif + +#if defined(RTE_SSI_ULP_MASTER_CS0) && (RTE_SSI_ULP_MASTER_CS0 == 1) +#define SSI_ULP_MASTER_CS0_SEL 1U +#define SSI_ULP_MASTER_CS0_PORT RTE_SSI_ULP_MASTER_CS0_PORT +#define SSI_ULP_MASTER_CS0_PIN RTE_SSI_ULP_MASTER_CS0_PIN +#define SSI_ULP_MASTER_CS0_MODE RTE_SSI_ULP_MASTER_CS0_MODE +#endif +#if defined(RTE_SSI_ULP_MASTER_CS1) && (RTE_SSI_ULP_MASTER_CS1 == 1) +#define SSI_ULP_MASTER_CS1_SEL 1U +#define SSI_ULP_MASTER_CS1_PORT RTE_SSI_ULP_MASTER_CS1_PORT +#define SSI_ULP_MASTER_CS1_PIN RTE_SSI_ULP_MASTER_CS1_PIN +#define SSI_ULP_MASTER_CS1_MODE RTE_SSI_ULP_MASTER_CS1_MODE +#endif +#if defined(RTE_SSI_ULP_MASTER_CS2) && (RTE_SSI_ULP_MASTER_CS2 == 1) +#define SSI_ULP_MASTER_CS2_SEL 1U +#define SSI_ULP_MASTER_CS2_PORT RTE_SSI_ULP_MASTER_CS2_PORT +#define SSI_ULP_MASTER_CS2_PIN RTE_SSI_ULP_MASTER_CS2_PIN +#define SSI_ULP_MASTER_CS2_MODE RTE_SSI_ULP_MASTER_CS2_MODE +#endif +#endif + + +/* SPI Register Interface Definitions */ +#ifdef SSI_MASTER +#if (defined(SSI_MASTER_RX_DMA_Instance) || defined(SSI_MASTER_TX_DMA_Instance)) +#ifndef SSI_MASTER_RX_DMA_Instance +#error "SSI_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#ifndef SSI_MASTER_TX_DMA_Instance +#error "SSI_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#endif +#endif + +#ifdef SSI_SLAVE +#if (defined(SSI_SLAVE_RX_DMA_Instance) || defined(SSI_SLAVE_TX_DMA_Instance)) +#ifndef SSI_SLAVE_RX_DMA_Instance +#error "SSI_SLAVE using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#ifndef SSI_SLAVE_TX_DMA_Instance +#error "SSI_SLAVE using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#endif +#endif + +#ifdef SSI_ULP_MASTER +#if (defined(SSI_ULP_MASTER_RX_DMA_Instance) || defined(SSI_ULP_MASTER_TX_DMA_Instance)) +#ifndef SSI_ULP_MASTER_RX_DMA_Instance +#error "SSI_ULP_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#ifndef SSI_ULP_MASTER_TX_DMA_Instance +#error "SSI_ULP_MASTER using DMA requires Rx and Tx DMA channel enabled in RTE_Device_917.h!" +#endif +#endif +#endif + + +#if ((defined(SSI_MASTER) && defined(SSI_MASTER_RX_DMA_Instance)) || \ + (defined(SSI_SLAVE) && defined(SSI_SLAVE_RX_DMA_Instance)) || \ + (defined(SSI_ULP_MASTER) && defined(SSI_ULP_MASTER_RX_DMA_Instance))) +#define __SPI_DMA_RX +#endif +#if ((defined(SSI_MASTER) && defined(SSI_MASTER_TX_DMA_Instance)) || \ + (defined(SSI_SLAVE) && defined(SSI_SLAVE_TX_DMA_Instance)) || \ + (defined(SSI_ULP_MASTER) && defined(SSI_ULP_MASTER_TX_DMA_Instance))) +#define __SPI_DMA_TX +#endif +#if (defined(__SPI_DMA_RX) && defined(__SPI_DMA_TX)) +#define __SPI_DMA +#endif + +/* Current driver status flag definition */ +#define SPI_INITIALIZED (1 << 0) // SPI initialized +#define SPI_POWERED (1 << 1) // SPI powered on +#define SPI_CONFIGURED (1 << 2) // SPI configured +#define SPI_DATA_LOST (1 << 3) // SPI data lost occurred +#define SPI_MODE_FAULT (1 << 4) // SPI mode fault occurred + + +#define SPI_CS0 0 +#define SPI_CS1 1 +#define SPI_CS2 2 +#define SPI_CS3 3 + +/* SPI Pins Configuration */ +typedef const struct _SPI_PIN { + uint8_t port; ///< SPI GPIO port + uint8_t pin; ///< SPI GPIO pin + uint8_t mode; ///< SPI GPIO mode + uint8_t pad_sel; ///< SPI GPIO pad selection +}SPI_PIN; + +// SPI Input/Output Configuration +typedef const struct _SPI_IO { + SPI_PIN *mosi; // Pointer to MOSI pin configuration + SPI_PIN *miso; // Pointer to MISO pin configuration + SPI_PIN *sck; // Pointer to SCK pin configuration + SPI_PIN *cs0; // Pointer to CS(CHIP SELECT) pin configuration +#ifdef SPI_MULTI_SLAVE + SPI_PIN *cs1; // Pointer to CS(CHIP SELECT) pin configuration + SPI_PIN *cs2; // Pointer to CS(CHIP SELECT) pin configuration + SPI_PIN *cs3; // Pointer to CS(CHIP SELECT) pin configuration +#endif +} SPI_IO; + +// SPI DMA +typedef struct SPI_DMA +{ + RSI_UDMA_CHA_CFG_T chnl_cfg; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} SPI_DMA; + +/* SPI status */ +typedef struct SPI_STATUS { + uint8_t busy; // Transmitter/Receiver busy flag + uint8_t data_lost; // Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation) + uint8_t mode_fault; // Mode fault detected; optional (cleared on start of transfer operation) +} SPI_STATUS; + +/* SPI Information (Run-time) */ +typedef struct SPI_INFO { + ARM_SPI_SignalEvent_t cb_event; // Event Callback + SPI_STATUS status; // Status flags + uint8_t state; // Current SPI state + uint32_t mode; // Current SPI mode +} SPI_INFO; + +/* SPI Transfer Information (Run-Time) */ +typedef struct SPI_TRANSFER_INFO { + uint32_t num; // Total number of transfers + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint32_t dump_val; // Variable for dumping DMA data + uint16_t def_val; // Default transfer value +} SPI_TRANSFER_INFO; + +typedef struct _SPI_CLOCK +{ + SSI_MST_CLK_SRC_SEL_T spi_clk_src; + ULP_SSI_CLK_SELECT_T ulp_spi_clk_src; + uint32_t divfact; + }SPI_CLOCK; + +/* SPI Resources */ +typedef struct { + SSI0_Type *reg; // SPI peripheral register interface + SPI_IO io; // SPI pins configuration + IRQn_Type irq_num; // SPI IRQ number + SPI_DMA *rx_dma; // Receive stream register interface + SPI_DMA *tx_dma; // Transmit stream register interface + SPI_INFO *info; // SPI Run-time information + SPI_TRANSFER_INFO *xfer; // SPI transfer information + uint8_t instance_mode; + SPI_CLOCK clock; + +} const SPI_RESOURCES; + +void RSI_SPI_SetSlaveSelectNumber(uint8_t slavenumber); +void RSI_SPI_Slave_Disable(void); +void RSI_SPI_Slave_Set_CS_Init_State(void); +#endif /* __SPI_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h new file mode 100644 index 000000000..b5becb17d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/UDMA.h @@ -0,0 +1,104 @@ +/****************************************************************************** +* @file UDMA.h +******************************************************************************* +* # License +* Copyright 2023,2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#ifndef __UDMA_H__ +#define __UDMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_ccp_common.h" +#include "Driver_Common.h" +#include "rsi_udma.h" + +#define UDMA_EVENT_XFER_DONE (1) +#define UDMA_EVENT_ERROR (2) + +void IRQ033_Handler (void); +void IRQ010_Handler (void); +#if defined(DAC_FIFO_MODE_EN) || defined(ADC_MULTICHANNEL_WITH_EXT_DMA) +#define DAC_UDMA_CHANNEL 10 +#define ADC_UDMA_CHANNEL 11 +#endif + +/* UDMA Resource Configuration */ +typedef struct +{ + UDMA0_Type *reg; // UDMA register interface + IRQn_Type udma_irq_num; // UDMA Event IRQ Numbe + RSI_UDMA_DESC_T *desc; // Run-Time control information +} UDMA_RESOURCES; + +/* Number of UDMA channels */ +#define UDMA_NUMBER_OF_CHANNELS ((uint8_t) 32) +#define ULP_UDMA_NUMBER_OF_CHANNELS ((uint8_t) 12) + + +#define CONTROL_STRUCT0 (UDMA_NUMBER_OF_CHANNELS * 2) +#define CONTROL_STRUCT1 (ULP_UDMA_NUMBER_OF_CHANNELS * 2) + +/** + * @fn void UDMA_SignalEvent_t (uint32_t event) + * @brief Signal UDMA Events. + * @param[in] event UDMA Event mask + * @param[in] ch Channel no + * @return none +*/ +typedef void (*UDMA_SignalEvent_t) (uint32_t event, uint32_t ch); + + +/** +\brief Access structure of the UDMA Driver. +*/ +typedef struct _RSI_DRIVER_UDMA { + + int32_t (*Initialize) ( void ); + int32_t (*Uninitialize) ( void ); + int32_t (*ChannelConfigure)( uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T *config, + UDMA_SignalEvent_t cb_event ); + int32_t (*ChannelEnable) ( uint8_t ch ); + int32_t (*ChannelDisable) ( uint8_t ch ); + uint32_t (*ChannelGetCount) ( uint8_t ch, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T config ); + int32_t (*DMAEnable) ( void ); +} const RSI_DRIVER_UDMA; + +#ifdef __cplusplus +} +#endif +#endif // __UDMA_H__ + + diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h new file mode 100644 index 000000000..5e3d3f624 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/cmsis_driver/USART.h @@ -0,0 +1,276 @@ +/* ----------------------------------------------------------------------------- + * + * SPDX-License-Identifier: Zlib + * Copyright (c) 2013-2014 ARM Ltd. + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 24. Nov 2014 + * $Revision: V2.02 + * + * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) + * Driver definitions + * -------------------------------------------------------------------------- */ +/* + * Version 1.00 + * Initial release + */ + +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "Driver_USART.h" +#include "rsi_ccp_common.h" + +#include "UDMA.h" + +#define USART_INSTANCE_BIT 30 // USART Instance bit postion stored in event variable +#define USART_EVENT_MASK 0x3FFFFFFF // USART Event Mask + +// USART Transfer Information (Run-Time) +typedef struct _USART_TRANSFER_INFO { + uint32_t rx_num; // Total number of data to be received + uint32_t tx_num; // Total number of data to be send + uint8_t *rx_buf; // Pointer to in data buffer + uint8_t *tx_buf; // Pointer to out data buffer + uint32_t rx_cnt; // Number of data received + uint32_t tx_cnt; // Number of data sent + uint8_t tx_def_val; // Transmit default value (used in USART_SYNC_MASTER_MODE_RX) + uint8_t rx_dump_val; // Receive dump value (used in USART_SYNC_MASTER_MODE_TX) + uint8_t send_active; // Send active flag + uint8_t sync_mode; // Synchronous mode +} USART_TRANSFER_INFO; + +typedef struct _USART_RX_STATUS { + uint8_t rx_busy; // Receiver busy flag + uint8_t rx_overflow; // Receive data overflow detected (cleared on start of next receive operation) + uint8_t rx_break; // Break detected on receive (cleared on start of next receive operation) + uint8_t rx_framing_error; // Framing error detected on receive (cleared on start of next receive operation) + uint8_t rx_parity_error; // Parity error detected on receive (cleared on start of next receive operation) +} USART_RX_STATUS; + +// USART DMA +typedef struct _USART0_DMA +{ + RSI_UDMA_CHA_CONFIG_DATA_T control; + uint8_t channel; // DMA Channel number + UDMA_SignalEvent_t cb_event; // DMA Event callback +} USART_DMA; + + +// USART flags +#define USART_FLAG_INITIALIZED (1U << 0) +#define USART_FLAG_POWERED (1U << 1) +#define USART_FLAG_CONFIGURED (1U << 2) +#define USART_FLAG_TX_ENABLED (1U << 3) +#define USART_FLAG_RX_ENABLED (1U << 4) +#define USART_FLAG_SEND_ACTIVE (1U << 5) + +/*!< USART Configuration control bits (Line control Register)*/ +#define USART_CNTL_DATALEN_5 (0x00 << 0) /*!< USART 5 bit length mode */ +#define USART_CNTL_DATALEN_6 (0x01 << 0) /*!< USART 6 bit length mode */ +#define USART_CNTL_DATALEN_7 (0x02 << 0) /*!< USART 7 bit length mode */ +#define USART_CNTL_DATALEN_8 (0x03 << 0) /*!< USART 8 bit length mode */ +#define USART_CNTL_STOPBIT_1 (0x00 << 2) /*!< USART One Stop Bit Select */ +#define USART_CNTL_STOPBIT_2 (0x01 << 2) /*!< USART Two Stop Bits Select */ +#define USART_CNTL_STOPBIT_1P5 (0x01 << 2) /*!< USART Two Stop Bits Select */ +#define USART_CNTL_PARITY_OFF (0x00 << 3) /*!< Parity Enabled */ +#define USART_CNTL_PARITY_ON (0x01 << 3) /*!< Parity Disabled */ +#define USART_CNTL_PARITY_ODD (0x00 << 4) /*!< Odd parity */ +#define USART_CNTL_PARITY_EVEN (0x01 << 4) /*!< Even parity */ +#define USART_PARITY_ENABLE (0x01 << 3) /*!< Set parity */ +#define USART_CNTL_DLAB_SET (0x01 << 7) +#define USART_CNTL_DLAB_RESET (0x00) +#define USART_CNTL_DATALEN_9 (0x01 << 0) /*!< USART 9 bit length mode */ + +/*!< USART FIFO Configuration control bits (FIFO control Register)*/ +#define USART_FIFO_ENABLE (0x01 << 0) /*!< FIFO Enable */ +#define USART_FIFO_RX_RESET (0x01 << 1) /*!< Receive FIFO Reset */ +#define USART_FIFO_TX_RESET (0x01 << 2) /*!< Transmit FIFO Reset */ +#define USART_FIFO_TX_EMPTY (0x00 << 4) /*!< Transmit Empty */ +#define USART_FIFO_TX_AEMPTY (0x01 << 4) /*!< Transmit Almost Empty */ +#define USART_FIFO_TX_QUARTER_FULL (0x02 << 4) /*!< Transmit FIFO Quarter full */ +#define USART_FIFO_TX_HALF_FULL (0x03 << 4) /*!< Transmit FIFO Half full */ +#define USART_FIFO_RX_AEMPTY (0x00 << 6) /*!< Receive FIFO AEMPTY */ +#define USART_FIFO_RX_QUARTER_FULL (0x01 << 6) /*!< Receive FIFO Quarter full */ +#define USART_FIFO_RX_HALF_FULL (0x01 << 7) /*!< Receive FIFO half full */ +#define USART_FIFO_RX_AFULL (0x03 << 6) /*!< RX FIFO Almost Full */ +#define USART_DMA_MODE_EN (1UL << 3) + +/*!< USART (Interrupt Enable Register)*/ +#define USART_INTR_RX_DATA (0x01 << 0) /*!< Enable Received Data Available Interrupt. */ +#define USART_INTR_THRE (0x01 << 1) /*!< Enable Transmit Holding Register Empty Interrupt.*/ +#define USART_INTR_RXRDY (0x01 << 2) /*!< Receive Ready Interrupt */ +#define USART_INTR_MODEM_STATUS (0x01 << 3) /*!< TODO */ +#define USART_INTR_PROGRAMMABLE_THRE (0x01 << 7) /*!< TODO THRE Interrupt */ + +/*!< USART (Interrupt Identity Register)*/ +#define USART_MODEM_STATUS_INTR (0x00 << 0) +#define USART_NO_INTR_PENDING (0x01 << 0) /*!< NO Interrupt Pending */ +#define USART_THR_EMPTY (0x01 << 1) /*!< THR Empty */ +#define USART_RX_DATA_AVAILABLE (0x01 << 2) /*!< Received Data Available */ +#define USART_RX_LINE_STATUS (0x03 << 1) /*!< Receiver line status */ +#define USART_BUSY_DETECT (0x07 << 0) /*!< USART busy detect */ +#define USART_IIR_FIFO_ENABLE (0x03 << 6) /*!< IIR FIFO enabled */ + +/*!< USART (Modem status registers)*/ +#define USART_MSR_DCTS (0x1 << 0) /*!>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H +#include "rsi_ccp_user_config.h" + +// USART0 [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART +#define RTE_ENABLE_FIFO 1 + +#define RTE_USART0 1 + +#define RTE_USART0_CLK_SRC USART_INTFPLLCLK +#define RTE_USART0_CLK_DIV_FACT 1 +#define RTE_USART0_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_USART_MODE 0 //!Usart mode macros +#define RTE_CONTINUOUS_CLOCK_MODE 0 + +#define RTE_USART0_LOOPBACK 0 +#define RTE_USART0_DTR_EANBLE 0 + +#define RTE_USART0_DMA_MODE1_EN 0 //!dma mode + +#define RTE_USART0_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_USART0_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_USART0_DMA_TX_LEN_PER_DES 1024 +#define RTE_USART0_DMA_RX_LEN_PER_DES 1024 + +#define RTE_USART0_CHNL_UDMA_TX_EN 0 +#define RTE_USART0_CHNL_UDMA_TX_CH 25 + +#define RTE_USART0_CHNL_UDMA_RX_EN 0 +#define RTE_USART0_CHNL_UDMA_RX_CH 24 + + +// USART0_CLK <0=>P0_8 <1=>P0_25 <2=>P0_52 <3=>P0_64 +// CLK of USART0 +#define RTE_USART0_CLK_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_USART0_CLK_PORT_ID == 2)||(RTE_USART0_CLK_PORT_ID == 3)) + #error "Invalid USART0 RTE_USART0_CLK_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_CLK_PORT_ID == 0) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 8 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 3 +#elif(RTE_USART0_CLK_PORT_ID ==1) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 25 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 0//NO PAD +#elif(RTE_USART0_CLK_PORT_ID ==2) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 52 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 16 +#elif(RTE_USART0_CLK_PORT_ID ==3) +#define RTE_USART0_CLK_PORT 0 +#define RTE_USART0_CLK_PIN 64 +#define RTE_USART0_CLK_MUX 2 +#define RTE_USART0_CLK_PAD 22 +#else + #error "Invalid USART0 RTE_USART0_CLK_PIN Pin Configuration!" +#endif + +// USART0_TX <0=>P0_15 <1=>P0_30 <2=>P0_54 <3=>P0_68 <4=>P0_71 +// TX for USART0 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_TX_PORT_ID 1 +#else +#define RTE_USART0_TX_PORT_ID 0 +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_USART0_TX_PORT_ID 3 +#if((RTE_USART0_TX_PORT_ID == 0)||(RTE_USART0_TX_PORT_ID ==2)) + #error "Invalid USART0 RTE_USART0_TX_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_TX_PORT_ID == 0) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 15 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 8 +#elif(RTE_USART0_TX_PORT_ID == 1) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 30 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 0 //NO PAD +#elif(RTE_USART0_TX_PORT_ID ==2) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 54 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 18 +#elif(RTE_USART0_TX_PORT_ID ==3) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 68 +#define RTE_USART0_TX_MUX 2 +#define RTE_USART0_TX_PAD 26 +#elif(RTE_USART0_TX_PORT_ID ==4) +#define RTE_USART0_TX_PORT 0 +#define RTE_USART0_TX_PIN 71 +#define RTE_USART0_TX_MUX 4 +#define RTE_USART0_TX_PAD 29 +#else + #error "Invalid USART0 RTE_USART0_TX_PIN Pin Configuration!" +#endif + +// USART0_RX <0=>P0_10 <1=>P0_29 <2=>P0_55 <3=>P0_65 <4=>P0_70 +// RX for USART0 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_USART0_RX_PORT_ID 1 +#else +#define RTE_USART0_RX_PORT_ID 0 +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_USART0_RX_PORT_ID 0 +#if((RTE_USART0_RX_PORT_ID == 2)||(RTE_USART0_RX_PORT_ID == 3)) + #error "Invalid USART0 RTE_USART0_RX_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_RX_PORT_ID ==0) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 10 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 5 +#elif(RTE_USART0_RX_PORT_ID ==1) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 29 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 0//no pad +#elif(RTE_USART0_RX_PORT_ID ==2) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 55 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 19 +#elif(RTE_USART0_RX_PORT_ID ==3) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 65 +#define RTE_USART0_RX_MUX 2 +#define RTE_USART0_RX_PAD 24 +#elif(RTE_USART0_RX_PORT_ID ==4) +#define RTE_USART0_RX_PORT 0 +#define RTE_USART0_RX_PIN 70 +#define RTE_USART0_RX_MUX 4 +#define RTE_USART0_RX_PAD 28 +#else + #error "Invalid USART0 RTE_USART0_RX_PIN Pin Configuration!" +#endif + +// USART0_CTS <0=>P0_6 <1=>P0_26 <2=>P0_56 <3=>P0_70 +// CTS for USART0 +#define RTE_USART0_CTS_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_USART0_CTS_PORT_ID == 2)) + #error "Invalid USART0 RTE_USART0_CTS_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_CTS_PORT_ID ==0) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 6 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 1 +#elif(RTE_USART0_CTS_PORT_ID ==1) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 26 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 0//NO PAD +#elif(RTE_USART0_CTS_PORT_ID ==2) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 56 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 20 +#elif(RTE_USART0_CTS_PORT_ID ==3) +#define RTE_USART0_CTS_PORT 0 +#define RTE_USART0_CTS_PIN 70 +#define RTE_USART0_CTS_MUX 2 +#define RTE_USART0_CTS_PAD 28 +#else + #error "Invalid USART0 RTE_USART0_CTS_PIN Pin Configuration!" +#endif + + +// USART0_RTS <0=>P0_9 <1=>P0_28 <2=>P0_53 <3=>P0_69 +// RTS for USART0 +#define RTE_USART0_RTS_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_USART0_RTS_PORT_ID == 2)) + #error "Invalid USART0 RTE_USART0_RTS_PIN pin Configuration!" +#endif +#endif +#if(RTE_USART0_RTS_PORT_ID ==0) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 9 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 4 +#elif(RTE_USART0_RTS_PORT_ID ==1) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 28 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 0 //NO PAD +#elif(RTE_USART0_RTS_PORT_ID ==2) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 53 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 17 +#elif(RTE_USART0_RTS_PORT_ID ==3) +#define RTE_USART0_RTS_PORT 0 +#define RTE_USART0_RTS_PIN 69 +#define RTE_USART0_RTS_MUX 2 +#define RTE_USART0_RTS_PAD 27 +#else + #error "Invalid USART0 RTE_USART0_RTS_PIN Pin Configuration!" +#endif + +// USART0_IR_TX <0=>P0_48 <1=>P0_72 +// IR TX for USART0 +#ifndef CHIP_917_6x6 +#define RTE_IR_TX_PORT_ID 0 +#if((RTE_IR_TX_PORT_ID ==2 )) + #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_IR_TX_PORT_ID 2 +#if((RTE_IR_TX_PORT_ID ==0 )||(RTE_IR_TX_PORT_ID ==1 )) + #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif +#endif +#if(RTE_IR_TX_PORT_ID ==0) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 48 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 12 +#elif(RTE_IR_TX_PORT_ID ==1) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 72 +#define RTE_USART0_IR_TX_MUX 2 +#define RTE_USART0_IR_TX_PAD 30 +#elif(RTE_IR_TX_PORT_ID ==2) +#define RTE_USART0_IR_TX_PORT 0 +#define RTE_USART0_IR_TX_PIN 26 +#define RTE_USART0_IR_TX_MUX 13 +#define RTE_USART0_IR_TX_PAD 0//No pad +#else + #error "Invalid USART0 RTE_USART0_IR_TX_PIN Pin Configuration!" +#endif + + +// USART0_IR_RX <0=>P0_47 <1=>P0_71 <2=>P0_64 <3=>P0_25 +// IR RX for USART0 +#ifndef CHIP_917_6x6 +#define RTE_IR_RX_PORT_ID 0 +#if((RTE_IR_RX_PORT_ID ==2 )) + #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_IR_RX_PORT_ID 2 +#if((RTE_IR_RX_PORT_ID == 0)) + #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif +#endif +#if(RTE_IR_RX_PORT_ID ==0) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 47 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 11 +#elif(RTE_IR_RX_PORT_ID ==1) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 71 +#define RTE_USART0_IR_RX_MUX 2 +#define RTE_USART0_IR_RX_PAD 29 +#elif(RTE_IR_RX_PORT_ID ==2) +#define RTE_USART0_IR_RX_PORT 0 +#define RTE_USART0_IR_RX_PIN 25 +#define RTE_USART0_IR_RX_MUX 13 +#define RTE_USART0_IR_RX_PAD 0//no pad +#else + #error "Invalid USART0 RTE_USART0_IR_RX_PIN Pin Configuration!" +#endif + + +// USART0_RI <0=>P0_27 <1=>P0_46 <2=>P0_68 +// RI for USART0 +#define RTE_RI_PORT_ID 0 + +#ifndef CHIP_917_6x6 + +#if((RTE_RI_PORT_ID == 2)) + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif + +#endif + + +#ifdef CHIP_917_6x6 + +#if((RTE_RI_PORT_ID == 1)) + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif + +#endif +#if(RTE_RI_PORT_ID ==0) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 27 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 0//no pad +#elif(RTE_RI_PORT_ID ==1) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 46 +#define RTE_USART0_RI_MUX 2 +#define RTE_USART0_RI_PAD 10 +#elif(RTE_RI_PORT_ID ==2) +#define RTE_USART0_RI_PORT 0 +#define RTE_USART0_RI_PIN 68 +#define RTE_USART0_RI_MUX 11 +#define RTE_USART0_RI_PAD 26 +#else + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif + +// USART0_DSR <0=>P0_11 <1=>P0_57 +// DSR for USART0 +#define RTE_DSR_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_DSR_PORT_ID == 1)) + #error "Invalid USART0 RTE_USART0_RI_PIN pin Configuration!" +#endif +#endif +#if(RTE_DSR_PORT_ID == 0) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 11 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 6 +#elif(RTE_DSR_PORT_ID == 1) +#define RTE_USART0_DSR_PORT 0 +#define RTE_USART0_DSR_PIN 57 +#define RTE_USART0_DSR_MUX 2 +#define RTE_USART0_DSR_PAD 21 +#else + #error "Invalid USART0 RTE_USART0_RI_PIN Pin Configuration!" +#endif +// USART0_DCD <0=>P0_12 <1=>P0_29 +// DCD for USART0 + +#ifndef CHIP_917_6x6 +#define RTE_USART0_DCD_PORT 0 +#define RTE_USART0_DCD_PIN 12 +#define RTE_USART0_DCD_MUX 2 +#define RTE_USART0_DCD_PAD 7 +#endif + +#ifdef CHIP_917_6x6 +#define RTE_USART0_DCD_PORT 0 +#define RTE_USART0_DCD_PIN 29 +#define RTE_USART0_DCD_MUX 12 +#define RTE_USART0_DCD_PAD 0//no pad +#endif + + +// USART0_DTR <0=>P0_7 +// DTR for USART0 +#define RTE_USART0_DTR_PORT 0 +#define RTE_USART0_DTR_PIN 7 +#define RTE_USART0_DTR_MUX 2 +#define RTE_USART0_DTR_PAD 2 +// + +// UART1 [Driver_UART1] +// Configuration settings for Driver_UART1 in component ::CMSIS Driver:USART +#define RTE_UART1 1 + +#define RTE_UART1_CLK_SRC USART_INTFPLLCLK +#define RTE_UART1_CLK_DIV_FACT 1 +#define RTE_UART1_FRAC_DIV_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_UART1_LOOPBACK 0 +#define RTE_UART1_DMA_MODE1_EN 0 + +#define RTE_UART1_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_UART1_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_UART1_DMA_TX_LEN_PER_DES 1024 +#define RTE_UART1_DMA_RX_LEN_PER_DES 1024 + +#define RTE_UART1_CHNL_UDMA_TX_EN 0 +#define RTE_UART1_CHNL_UDMA_TX_CH 27 + +#define RTE_UART1_CHNL_UDMA_RX_EN 0 +#define RTE_UART1_CHNL_UDMA_RX_CH 26 + +/*UART1 PINS*/ +// UART1_TX <0=>P0_7 <1=>P0_30 <2=>P0_67 <3=>P0_69 <4=>P0_73 <5=>P0_75 <6=>P0_34 +// TX of UART1 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_TX_PORT_ID 4 +#else +#define RTE_UART1_TX_PORT_ID 0 +#endif + +#if((RTE_UART1_TX_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_TX_PORT_ID 0 +#if((RTE_UART1_TX_PORT_ID == 2)||(RTE_UART1_TX_PORT_ID == 4)||(RTE_UART1_TX_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_TX_PIN Configuration!" +#endif +#endif +#if(RTE_UART1_TX_PORT_ID ==0) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 7 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 2 +#elif(RTE_UART1_TX_PORT_ID ==1) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 30 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 0//no pad +#elif(RTE_UART1_TX_PORT_ID ==2) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 67 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 25 +#elif(RTE_UART1_TX_PORT_ID ==3) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 69 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 27 +#elif(RTE_UART1_TX_PORT_ID ==4) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 73 +#define RTE_UART1_TX_MUX 6 +#define RTE_UART1_TX_PAD 31 +#elif(RTE_UART1_TX_PORT_ID ==5) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 75 +#define RTE_UART1_TX_MUX 9 +#define RTE_UART1_TX_PAD 33 +#elif(RTE_UART1_TX_PORT_ID ==6) +#define RTE_UART1_TX_PORT 0 +#define RTE_UART1_TX_PIN 34 +#define RTE_UART1_TX_MUX 12 +#define RTE_UART1_TX_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_TX_PIN Pin Configuration!" +#endif + +// UART1_RX <0=>P0_6 <1=>P0_29 <2=>P0_66 <3=>P0_68 <4=>P0_72 <5=>P0_74 <6=>P0_33 +// RX of UART1 + +#ifndef CHIP_917_6x6 +#define RTE_UART1_RX_PORT_ID 0 +#if((RTE_UART1_RX_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_RX_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_RX_PORT_ID 0 +#if((RTE_UART1_RX_PORT_ID == 2)||(RTE_UART1_RX_PORT_ID == 4)||(RTE_UART1_RX_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_RX_PIN Configuration!" +#endif +#endif +#if(RTE_UART1_RX_PORT_ID ==0) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 6 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 1 +#elif(RTE_UART1_RX_PORT_ID ==1) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 29 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 0//no pad +#elif(RTE_UART1_RX_PORT_ID ==2) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 66 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 24 +#elif(RTE_UART1_RX_PORT_ID ==3) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 68 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 26 +#elif(RTE_UART1_RX_PORT_ID ==4) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 72 +#define RTE_UART1_RX_MUX 6 +#define RTE_UART1_RX_PAD 30 +#elif(RTE_UART1_RX_PORT_ID ==5) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 74 +#define RTE_UART1_RX_MUX 9 +#define RTE_UART1_RX_PAD 32 +#elif(RTE_UART1_RX_PORT_ID ==6) +#define RTE_UART1_RX_PORT 0 +#define RTE_UART1_RX_PIN 33 +#define RTE_UART1_RX_MUX 12 +#define RTE_UART1_RX_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_RX_PIN Pin Configuration!" +#endif + +// UART1_CTS <0=>P0_11 <1=>P0_28 <2=>P0_51 <3=>P0_65 <4=>P0_71 <5=>P0_73 <6=>P0_32 +// CTS of UART1 +#ifndef CHIP_917_6x6 +#define RTE_UART1_CTS_PORT_ID 0 +#if((RTE_UART1_CTS_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_CTS_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_CTS_PORT_ID 6 +#if((RTE_UART1_CTS_PORT_ID == 2)||(RTE_UART1_CTS_PORT_ID == 3)||(RTE_UART1_CTS_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_CTS_PIN Configuration!" +#endif +#endif + +#if(RTE_UART1_CTS_PORT_ID ==0) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 11 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 6 +#elif(RTE_UART1_CTS_PORT_ID ==1) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 28 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 0//no pad +#elif(RTE_UART1_CTS_PORT_ID ==2) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 51 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 15 +#elif(RTE_UART1_CTS_PORT_ID ==3) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 65 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 23 +#elif(RTE_UART1_CTS_PORT_ID ==4) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 71 +#define RTE_UART1_CTS_MUX 6 +#define RTE_UART1_CTS_PAD 29 +#elif(RTE_UART1_CTS_PORT_ID ==5) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 73 +#define RTE_UART1_CTS_MUX 9 +#define RTE_UART1_CTS_PAD 31 +#elif(RTE_UART1_CTS_PORT_ID ==6) +#define RTE_UART1_CTS_PORT 0 +#define RTE_UART1_CTS_PIN 32 +#define RTE_UART1_CTS_MUX 12 +#define RTE_UART1_CTS_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_CTS_PIN Pin Configuration!" +#endif + +// UART1_RTS <0=>P0_10 <1=>P0_27 <2=>P0_50 <3=>P0_64 <4=>P0_70 <5=>P0_72 <6=>P0_31 +// RTS of UART1 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_UART1_RTS_PORT_ID 1 +#else +#define RTE_UART1_RTS_PORT_ID 0 +#endif +#if((RTE_UART1_RTS_PORT_ID == 6)) + #error "Invalid UART1 RTE_UART1_RTS_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_UART1_RTS_PORT_ID 6 +#if((RTE_UART1_RTS_PORT_ID == 2)||(RTE_UART1_RTS_PORT_ID == 3)||(RTE_UART1_RTS_PORT_ID == 5)) + #error "Invalid UART1 RTE_UART1_RTS_PIN Configuration!" +#endif +#endif +#if(RTE_UART1_RTS_PORT_ID ==0) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 10 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 5 +#elif(RTE_UART1_RTS_PORT_ID == 1) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 27 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 0//no pad +#elif(RTE_UART1_RTS_PORT_ID ==2) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 50 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 14 +#elif(RTE_UART1_RTS_PORT_ID ==3) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 64 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 22 +#elif(RTE_UART1_RTS_PORT_ID ==4) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 70 +#define RTE_UART1_RTS_MUX 6 +#define RTE_UART1_RTS_PAD 28 +#elif(RTE_UART1_RTS_PORT_ID ==5) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 72 +#define RTE_UART1_RTS_MUX 9 +#define RTE_UART1_RTS_PAD 30 +#elif(RTE_UART1_RTS_PORT_ID ==6) +#define RTE_UART1_RTS_PORT 0 +#define RTE_UART1_RTS_PIN 31 +#define RTE_UART1_RTS_MUX 12 +#define RTE_UART1_RTS_PAD 9 +#else + #error "Invalid UART1 RTE_UART1_RTS_PIN Pin Configuration!" +#endif +// + +// ULP_UART [Driver_ULP_UART] +// Configuration settings for Driver_ULP_UART in component ::CMSIS Driver:USART +#define RTE_ULP_UART 1 + +#define RTE_ULP_UART_CLK_SRC ULP_UART_REF_CLK +#define RTE_ULP_UART_CLK_DIV_FACT 0 +#define RTE_ULP_UART_FRAC_SEL USART_FRACTIONAL_DIVIDER + +#define RTE_ULP_UART_LOOPBACK 0 +#define RTE_ULP_UART_DMA_MODE1_EN 0 + +#define RTE_ULP_UART_TX_FIFO_THRESHOLD USART_TRIGGER_TX_EMPTY +#define RTE_ULP_UART_RX_FIFO_THRESHOLD USART_TRIGGER_RX_AEMPTY + +#define RTE_ULP_UART_DMA_TX_LEN_PER_DES 1024 +#define RTE_ULP_UART_DMA_RX_LEN_PER_DES 1024 + +#define RTE_ULPUART_CHNL_UDMA_TX_EN 0 +#define RTE_ULPUART_CHNL_UDMA_TX_CH 1 + +#define RTE_ULPUART_CHNL_UDMA_RX_EN 0 +#define RTE_ULPUART_CHNL_UDMA_RX_CH 0 + +/*ULPSS UART PINS*/ +// UART1_TX <0=>P0_3 <1=>P0_7 <2=>P0_11 +// TX of ULPSS UART +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 +#define RTE_ULP_UART_TX_PORT_ID 2 +#else +#define RTE_ULP_UART_TX_PORT_ID 1 +#endif +#if (RTE_ULP_UART_TX_PORT_ID == 0) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 3 +#define RTE_ULP_UART_TX_MUX 3 +#elif (RTE_ULP_UART_TX_PORT_ID == 1) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 7 +#define RTE_ULP_UART_TX_MUX 3 +#elif (RTE_ULP_UART_TX_PORT_ID == 2) +#define RTE_ULP_UART_TX_PORT 0 +#define RTE_ULP_UART_TX_PIN 11 +#define RTE_ULP_UART_TX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_TX_PIN Pin Configuration!" +#endif + +// UART1_RX <0=>P0_2 <1=>P0_6 <2=>P0_9 +// RX of ULPSS UART +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2 +#define RTE_ULP_UART_RX_PORT_ID 2 +#else +#define RTE_ULP_UART_RX_PORT_ID 1 +#endif +#if (RTE_ULP_UART_RX_PORT_ID == 0) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 2 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 1) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 6 +#define RTE_ULP_UART_RX_MUX 3 +#elif (RTE_ULP_UART_RX_PORT_ID == 2) +#define RTE_ULP_UART_RX_PORT 0 +#define RTE_ULP_UART_RX_PIN 9 +#define RTE_ULP_UART_RX_MUX 3 +#else +#error "Invalid ULPSS UART RTE_ULP_UART_RX_PIN Pin Configuration!" +#endif + +// UART1_CTS <0=>P0_1 <1=>P0_5 <2=>P0_8 +// CTS of ULPSS UART +#define RTE_ULP_UART_CTS_PORT_ID 1 +#if(RTE_ULP_UART_CTS_PORT_ID ==0) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 1 +#define RTE_ULP_UART_CTS_MUX 3 +#elif(RTE_ULP_UART_CTS_PORT_ID ==1) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 5 +#define RTE_ULP_UART_CTS_MUX 3 +#elif(RTE_ULP_UART_CTS_PORT_ID ==2) +#define RTE_ULP_UART_CTS_PORT 0 +#define RTE_ULP_UART_CTS_PIN 8 +#define RTE_ULP_UART_CTS_MUX 3 +#else + #error "Invalid ULPSS UART RTE_ULP_UART_CTS_PIN Pin Configuration!" +#endif + +// UART1_RTS <0=>P0_0 <1=>P0_4 <2=>P0_10 +// RTS of ULPSS UART +#define RTE_ULP_UART_RTS_PORT_ID 1 +#if(RTE_ULP_UART_RTS_PORT_ID ==0) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 0 +#define RTE_ULP_UART_RTS_MUX 3 +#elif(RTE_ULP_UART_RTS_PORT_ID ==1) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 4 +#define RTE_ULP_UART_RTS_MUX 3 +#elif(RTE_ULP_UART_RTS_PORT_ID ==2) +#define RTE_ULP_UART_RTS_PORT 0 +#define RTE_ULP_UART_RTS_PIN 10 +#define RTE_ULP_UART_RTS_MUX 8 +#else + #error "Invalid ULPSS UART RTE_ULP_UART_RTS_PIN Pin Configuration!" +#endif +// + + + +// SSI_MASTER (Serial Peripheral Interface 1) [Driver_SSI_MASTER] +// Configuration settings for Driver_SSI_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_MASTER 1 + +// SSI_MASTER_MISO Pin <0=>GPIO_12 <1=>GPIO_27 <2=>GPIO_57 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_MASTER_MISO_PORT_ID 1 +#else +#define RTE_SSI_MASTER_MISO_PORT_ID 0 +#endif +#if((RTE_SSI_MASTER_MISO_PORT_ID == 3)) + #error "Invalid SSI RTE_SSI_MASTER_MISO_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_SSI_MASTER_MISO_PORT_ID 3 +#if((RTE_SSI_MASTER_MISO_PORT_ID == 0)||(RTE_SSI_MASTER_MISO_PORT_ID == 2)) + #error "Invalid SSI RTE_SSI_MASTER_MISO_PIN Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 12 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 7 +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 1) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 27 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 2) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 57 +#define RTE_SSI_MASTER_MISO_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MISO_PADSEL 21 +#elif (RTE_SSI_MASTER_MISO_PORT_ID == 3) +#define RTE_SSI_MASTER_MISO 1 +#define RTE_SSI_MASTER_MISO_PORT 0 +#define RTE_SSI_MASTER_MISO_PIN 10 +#define RTE_SSI_MASTER_MISO_MODE 12 +#define RTE_SSI_MASTER_MISO_PADSEL 5 +#else +#error "Invalid SSI_MASTER_MISO Pin Configuration!" +#endif + +// SSI_MASTER_MOSI Pin <0=>GPIO_11 <1=>GPIO_26 <2=>GPIO_56 +#define RTE_SSI_MASTER_MOSI_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_MASTER_MOSI_PORT_ID == 2)) + #error "Invalid SSI_MASTER_MOSI pin Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 11 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 6 +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 1) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 26 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_MOSI_PORT_ID == 2) +#define RTE_SSI_MASTER_MOSI 1 +#define RTE_SSI_MASTER_MOSI_PORT 0 +#define RTE_SSI_MASTER_MOSI_PIN 56 +#define RTE_SSI_MASTER_MOSI_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_MOSI_PADSEL 20 +#else +#error "Invalid SSI_MASTER_MOSI Pin Configuration!" +#endif + +// SSI_MASTER_SCK Pin <0=>GPIO_8 <1=>GPIO_25 <2=>GPIO_52 +#define RTE_SSI_MASTER_SCK_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_MASTER_SCK_PORT_ID == 2)) + #error "Invalid SSI_MASTER_SCK pin Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 8 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 3 +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 25 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_MASTER_SCK 1 +#define RTE_SSI_MASTER_SCK_PORT 0 +#define RTE_SSI_MASTER_SCK_PIN 52 +#define RTE_SSI_MASTER_SCK_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_SCK_PADSEL 16 +#else +#error "Invalid SSI_MASTER_SCK Pin Configuration!" +#endif + +#define M4_SSI_CS0 1 +#define M4_SSI_CS1 0 +#ifndef CHIP_917_6x6 +#define M4_SSI_CS2 0 +#define M4_SSI_CS3 0 +#endif + +// SSI_MASTER_CS Pin <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_53 <3=>GPIO_10 <4=>GPIO_15 <5=>GPIO_50 <6=>GPIO_51 +#define RTE_SSI_MASTER_CS0_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_MASTER_CS0_PORT_ID == 2)) + #error "Invalid SSI_MASTER_CS pin Configuration!" +#endif +#endif +#if (RTE_SSI_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 9 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 4 +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 28 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 0//NO PAD +#elif (RTE_SSI_MASTER_CS0_PORT_ID == 2) +#define RTE_SSI_MASTER_CS0 M4_SSI_CS0 +#define RTE_SSI_MASTER_CS0_PORT 0 +#define RTE_SSI_MASTER_CS0_PIN 53 +#define RTE_SSI_MASTER_CS0_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS0_PADSEL 17 +#else +#error "Invalid SSI_MASTER_CS0 Pin Configuration!" +#endif + +//CS1 +#define RTE_SSI_MASTER_CS1_PORT_ID 0 +#if (RTE_SSI_MASTER_CS1_PORT_ID == 0) +#define RTE_SSI_MASTER_CS1 M4_SSI_CS1 +#define RTE_SSI_MASTER_CS1_PORT 0 +#define RTE_SSI_MASTER_CS1_PIN 10 +#define RTE_SSI_MASTER_CS1_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS1_PADSEL 5 +#else +#error "Invalid SSI_MASTER_CS1 Pin Configuration!" +#endif + +#ifndef CHIP_917_6x6 +//CS2 +#define RTE_SSI_MASTER_CS2_PORT_ID 1 +#if (RTE_SSI_MASTER_CS2_PORT_ID == 0) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 15 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 8 +#elif (RTE_SSI_MASTER_CS2_PORT_ID == 1) +#define RTE_SSI_MASTER_CS2 M4_SSI_CS2 +#define RTE_SSI_MASTER_CS2_PORT 0 +#define RTE_SSI_MASTER_CS2_PIN 50 +#define RTE_SSI_MASTER_CS2_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS2_PADSEL 14 +#else +#error "Invalid SSI_MASTER_CS2 Pin Configuration!" +#endif + + +//CS3 +#define RTE_SSI_MASTER_CS3_PORT_ID 0 +#if (RTE_SSI_MASTER_CS3_PORT_ID == 0) +#define RTE_SSI_MASTER_CS3 M4_SSI_CS3 +#define RTE_SSI_MASTER_CS3_PORT 0 +#define RTE_SSI_MASTER_CS3_PIN 51 +#define RTE_SSI_MASTER_CS3_MODE EGPIO_PIN_MUX_MODE3 +#define RTE_SSI_MASTER_CS3_PADSEL 15 +#else +#error "Invalid SSI_MASTER_CS3 Pin Configuration!" +#endif +#endif + +// DMA Rx +// Channel <28=>28 +// Selects DMA Channel (only Channel 28 can be used) +// +#define RTE_SSI_MASTER_RX_DMA 0 +#define RTE_SSI_MASTER_UDMA_RX_CH 28 + +// DMA Tx +// Channel <29=>29 +// Selects DMA Channel (only Channel 29 can be used) +// +#define RTE_SSI_MASTER_TX_DMA 0 +#define RTE_SSI_MASTER_UDMA_TX_CH 29 +// + +// SSI_SLAVE (Serial Peripheral Interface 2) [Driver_SSI_SLAVE] +// Configuration settings for Driver_SSI_SLAVE in component ::CMSIS Driver:SPI +#define RTE_SSI_SLAVE 1 + + +#define RTE_SSI_SLAVE_INPUT_CLOCK SSISLAVE_CLK + +// SSI_SLAVE_MISO Pin <0=>Not Used <1=>GPIO_11 <2=>GPIO_28 <3=>GPIO_49 <4=>GPIO_57 +#define RTE_SSI_SLAVE_MISO_PORT_ID 2 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_SLAVE_MISO_PORT_ID == 3)||(RTE_SSI_SLAVE_MISO_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_MISO pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_MISO_PORT_ID == 0) +#define RTE_SSI_SLAVE_MISO 0 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 1) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 11 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 6 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 2) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 28 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 0//no pad +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 3) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 49 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 13 +#elif (RTE_SSI_SLAVE_MISO_PORT_ID == 4) +#define RTE_SSI_SLAVE_MISO 1 +#define RTE_SSI_SLAVE_MISO_PORT 0 +#define RTE_SSI_SLAVE_MISO_PIN 57 +#define RTE_SSI_SLAVE_MISO_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MISO_PADSEL 21 +#else +#error "Invalid SSI_SLAVE_MISO Pin Configuration!" +#endif + +// SSI_SLAVE_MOSI Pin <0=>Not Used <1=>GPIO_10 <2=>GPIO_27 <3=>GPIO_48 <4=>GPIO_56 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_SLAVE_MOSI_PORT_ID 2 +#else +#define RTE_SSI_SLAVE_MOSI_PORT_ID 1 +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_SSI_SLAVE_MOSI_PORT_ID 2 +#if((RTE_SSI_SLAVE_MOSI_PORT_ID == 3)||(RTE_SSI_SLAVE_MOSI_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_MOSI pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_MOSI_PORT_ID == 0) +#define RTE_SSI_SLAVE_MOSI 0 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 1) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 10 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 5 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 2) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 27 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 3) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 48 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 12 +#elif (RTE_SSI_SLAVE_MOSI_PORT_ID == 4) +#define RTE_SSI_SLAVE_MOSI 1 +#define RTE_SSI_SLAVE_MOSI_PORT 0 +#define RTE_SSI_SLAVE_MOSI_PIN 56 +#define RTE_SSI_SLAVE_MOSI_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_MOSI_PADSEL 20 +#else +#error "Invalid SSI_SLAVE_MOSI Pin Configuration!" +#endif + +// SSI_SLAVE_SCK Pin <0=>Not Used <1=>GPIO_8 <2=>GPIO_26 <3=>GPIO_47 <4=>GPIO_52 +#define RTE_SSI_SLAVE_SCK_PORT_ID 2 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_SLAVE_SCK_PORT_ID == 3)||(RTE_SSI_SLAVE_SCK_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_SCK pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_SCK_PORT_ID == 0) +#define RTE_SSI_SLAVE_SCK 0 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 1) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 8 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 3 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 2) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 26 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 0 //no pad +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 3) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 47 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 11 +#elif (RTE_SSI_SLAVE_SCK_PORT_ID == 4) +#define RTE_SSI_SLAVE_SCK 1 +#define RTE_SSI_SLAVE_SCK_PORT 0 +#define RTE_SSI_SLAVE_SCK_PIN 52 +#define RTE_SSI_SLAVE_SCK_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_SCK_PADSEL 16 +#else +#error "Invalid SSI_SLAVE_SCK Pin Configuration!" +#endif + +// SSI_SLAVE_CS Pin <0=>Not Used <1=>GPIO_9 <2=>GPIO_25 <3=>GPIO_46 <4=>GPIO_53 +#define RTE_SSI_SLAVE_CS_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_SSI_SLAVE_CS_PORT_ID == 3)||(RTE_SSI_SLAVE_CS_PORT_ID == 4)) + #error "Invalid SSI_SLAVE_CS pin Configuration!" +#endif +#endif +#if (RTE_SSI_SLAVE_CS_PORT_ID == 0) +#define RTE_SSI_SLAVE_CS 0 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 1) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 9 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 4 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 2) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 25 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 0//no pad +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 3) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 46 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 10 +#elif (RTE_SSI_SLAVE_CS_PORT_ID == 4) +#define RTE_SSI_SLAVE_CS 1 +#define RTE_SSI_SLAVE_CS_PORT 0 +#define RTE_SSI_SLAVE_CS_PIN 53 +#define RTE_SSI_SLAVE_CS_MODE EGPIO_PIN_MUX_MODE8 +#define RTE_SSI_SLAVE_CS_PADSEL 17 +#else +#error "Invalid SSI_SLAVE_CS Pin Configuration!" +#endif + +// DMA Rx +// Channel <22=>22 +// Selects DMA Channel (only Channel 22 can be used) +// +#define RTE_SSI_SLAVE_RX_DMA 1 +#define RTE_SSI_SLAVE_UDMA_RX_CH 22 +#define RTE_SSI_SLAVE_DMA_RX_LEN_PER_DES 1024 + +// DMA Tx +// Channel <23=>23 +// Selects DMA Channel (only Channel 23 can be used) +// +#define RTE_SSI_SLAVE_TX_DMA 1 +#define RTE_SSI_SLAVE_UDMA_TX_CH 23 +#define RTE_SSI_SLAVE_DMA_TX_LEN_PER_DES 1024 + +// + +// SSI_ULP_MASTER (Serial Peripheral Interface 3) [Driver_SSI_ULP_MASTER] +// Configuration settings for Driver_SSI_ULP_MASTER in component ::CMSIS Driver:SPI +#define RTE_SSI_ULP_MASTER 1 + +// Enable multiple CSN lines +#define ULP_SSI_CS0 1 +#define ULP_SSI_CS1 0 +#define ULP_SSI_CS2 0 + +// SSI_ULP_MASTER_MISO Pin <0=>Not Used <1=>ULP_GPIO_2 <2=>ULP_GPIO_9 +#define RTE_SSI_ULP_MASTER_MISO_PORT_ID 2 +#if (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MISO 0 +#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 1) +#if ( (PACKAGE_TYPE == CC0 ) || (PACKAGE_TYPE == SB0N_B00) || (PACKAGE_TYPE == SB00_B00) ) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 2 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#else + #error "Change RTE_SSI_ULP_MASTER_MISO_PORT_ID other than '1' as per PACKAGE_TYPE" +#endif +#elif (RTE_SSI_ULP_MASTER_MISO_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_MISO 1 +#define RTE_SSI_ULP_MASTER_MISO_PORT 0 +#define RTE_SSI_ULP_MASTER_MISO_PIN 9 +#define RTE_SSI_ULP_MASTER_MISO_MODE 1 +#else +#error "Invalid SSI_ULP_MISO Pin Configuration!" +#endif + +// SSI_ULP_MASTER_MOSI Pin <0=>Not Used <1=>ULP_GPIO_1 <2=>ULP_GPIO_11 +#define RTE_SSI_ULP_MASTER_MOSI_PORT_ID 2 +#if (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_MOSI 0 +#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 1) +#if ( !(PACKAGE_TYPE == SB0N_WMS )) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 1 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#else + #error "Change RTE_SSI_ULP_MASTER_MOSI_PORT_ID other than '1' as per PACKAGE_TYPE" +#endif +#elif (RTE_SSI_ULP_MASTER_MOSI_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_MOSI 1 +#define RTE_SSI_ULP_MASTER_MOSI_PORT 0 +#define RTE_SSI_ULP_MASTER_MOSI_PIN 11 +#define RTE_SSI_ULP_MASTER_MOSI_MODE 1 +#else +#error "Invalid SSI_ULP_MOSI Pin Configuration!" +#endif + +// SSI_ULP_MASTER_SCK Pin <0=>Not Used <1=>ULP_GPIO_0 <2=>ULP_GPIO_8 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 1 +#else +#define RTE_SSI_ULP_MASTER_SCK_PORT_ID 2 +#endif +#if (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_SCK 0 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 0 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#elif (RTE_SSI_ULP_MASTER_SCK_PORT_ID == 2) +#define RTE_SSI_ULP_MASTER_SCK 1 +#define RTE_SSI_ULP_MASTER_SCK_PORT 0 +#define RTE_SSI_ULP_MASTER_SCK_PIN 8 +#define RTE_SSI_ULP_MASTER_SCK_MODE 1 +#else +#error "Invalid SSI_ULP_SCK Pin Configuration!" +#endif + +// CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT_ID 0 +#if (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 0) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 3 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#elif (RTE_SSI_ULP_MASTER_CS0_PORT_ID == 1) +#define RTE_SSI_ULP_MASTER_CS0 ULP_SSI_CS0 +#define RTE_SSI_ULP_MASTER_CS0_PORT 0 +#define RTE_SSI_ULP_MASTER_CS0_PIN 10 +#define RTE_SSI_ULP_MASTER_CS0_MODE 1 +#else + #error "Change RTE_SSI_ULP_MASTER_CS_PORT_ID other than '1' or'3' as per PACKAGE_TYPE" +#endif + +// CS1 +#define RTE_SSI_ULP_MASTER_CS1 ULP_SSI_CS1 +#define RTE_SSI_ULP_MASTER_CS1_PORT 0 +#define RTE_SSI_ULP_MASTER_CS1_PIN 4 +#define RTE_SSI_ULP_MASTER_CS1_MODE 1 + +// CS2 +#define RTE_SSI_ULP_MASTER_CS2 ULP_SSI_CS2 +#define RTE_SSI_ULP_MASTER_CS2_PORT 0 +#define RTE_SSI_ULP_MASTER_CS2_PIN 6 +#define RTE_SSI_ULP_MASTER_CS2_MODE 1 + + +// DMA Rx +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// +#define RTE_SSI_ULP_MASTER_RX_DMA 1 +#define RTE_SSI_ULP_MASTER_UDMA_RX_CH 2 +#define RTE_SSI_ULP_MASTER_DMA_RX_LEN_PER_DES 96 + +// DMA Tx +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// +#define RTE_SSI_ULP_MASTER_TX_DMA 1 +#define RTE_SSI_ULP_MASTER_UDMA_TX_CH 3 +#define RTE_SSI_ULP_MASTER_DMA_TX_LEN_PER_DES 96 + +// +/*=================================================================== + UDMA Defines +====================================================================*/ +// UDMA [Driver_UDMA] +#define DESC_MAX_LEN 0x400 +#define RTE_UDMA0 1 +#define UDMA0_IRQHandler IRQ033_Handler +#define CHNL_MASK_REQ0 0 +#define CHNL_PRIORITY0 0 +#define DMA_PERI_ACK0 0 +#define BURST_REQ0_EN 1 +#define UDMA0_CHNL_PRIO_LVL 1 +#define UDMA0_SRAM_BASE 0x1FC00 + +#define RTE_UDMA1 1 +#define UDMA1_IRQHandler IRQ010_Handler +#define CHNL_MASK_REQ1 0 +#define CHNL_PRIORITY1 0 +#define BURST_REQ1_EN 1 +#define CHNL_HIGH_PRIO_EN1 1 +#define UDMA1_CHNL_PRIO_LVL 1 +#define ULP_SRAM_START_ADDR 0x24060000 +#define ULP_SRAM_END_ADDR 0x24063E00 +// RTE_UDMA1_BASE_MEM <0=>PS2 <1=>PS4 +#define RTE_UDMA1_BASE_MEM 0 +#if(RTE_UDMA1_BASE_MEM == 0) +#define UDMA1_SRAM_BASE 0x24060000 +#elif(RTE_UDMA1_BASE_MEM == 1) +#define UDMA1_SRAM_BASE 0x1CC00 +#else + #error "Invalid UDMA1 Control Base Address!" +#endif +// + +// I2S0 [Driver_I2S0] +// Configuration settings for Driver_I2S0 in component ::CMSIS Driver:I2S + +#define RTE_I2S0 1 +#define I2S0_IRQHandler IRQ064_Handler +/*I2S0 PINS*/ + +// I2S0_SCLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// SCLK of I2S0 +#define RTE_I2S0_SCLK_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_SCLK_PORT_ID == 2)||(RTE_I2S0_SCLK_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_SCLK pin Configuration!" +#endif +#endif +#if(RTE_I2S0_SCLK_PORT_ID == 0) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 8 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 3 +#elif(RTE_I2S0_SCLK_PORT_ID ==1) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 25 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 0//no pad +#elif(RTE_I2S0_SCLK_PORT_ID ==2) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 46 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 10 +#elif(RTE_I2S0_SCLK_PORT_ID ==3) +#define RTE_I2S0_SCLK_PORT 0 +#define RTE_I2S0_SCLK_PIN 52 +#define RTE_I2S0_SCLK_MUX 7 +#define RTE_I2S0_SCLK_PAD 16 +#else + #error "Invalid I2S0 RTE_I2S0_SCLK Pin Configuration!" +#endif + +// I2S0_WSCLK <0=>P0_9 <1=>P0_26 <2=>P0_47 <3=>P0_53 +// WSCLK for I2S0 +#define RTE_I2S0_WSCLK_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_WSCLK_PORT_ID == 2)||(RTE_I2S0_WSCLK_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_WSCLK pin Configuration!" +#endif +#endif +#if(RTE_I2S0_WSCLK_PORT_ID == 0) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 9 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 4 +#elif(RTE_I2S0_WSCLK_PORT_ID == 1) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 26 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 0//no pad +#elif(RTE_I2S0_WSCLK_PORT_ID ==2) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 47 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 11 +#elif(RTE_I2S0_WSCLK_PORT_ID ==3) +#define RTE_I2S0_WSCLK_PORT 0 +#define RTE_I2S0_WSCLK_PIN 53 +#define RTE_I2S0_WSCLK_MUX 7 +#define RTE_I2S0_WSCLK_PAD 17 +#else + #error "Invalid I2S0 RTE_I2S0_WSCLK Pin Configuration!" +#endif + +// I2S0_DOUT0 <0=>P0_11 <1=>P0_28 <2=>P0_49 <3=>P0_57 +// DOUT0 for I2S0 +#define RTE_I2S0_DOUT0_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_DOUT0_PORT_ID == 2)||(RTE_I2S0_DOUT0_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_DOUT0 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DOUT0_PORT_ID ==0) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 11 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 6 +#elif(RTE_I2S0_DOUT0_PORT_ID ==1) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 28 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 0// no pad +#elif(RTE_I2S0_DOUT0_PORT_ID ==2) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 49 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 13 +#elif(RTE_I2S0_DOUT0_PORT_ID ==3) +#define RTE_I2S0_DOUT0_PORT 0 +#define RTE_I2S0_DOUT0_PIN 57 +#define RTE_I2S0_DOUT0_MUX 7 +#define RTE_I2S0_DOUT0_PAD 21 +#else + #error "Invalid I2S0 RTE_I2S0_DOUT0 Pin Configuration!" +#endif + +// I2S0_DIN0 <0=>P0_10 <1=>P0_27 <2=>P0_48 <3=>P0_56 +// DIN0 for I2S0 +#define RTE_I2S0_DIN0_PORT_ID 1 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_DIN0_PORT_ID == 2)||(RTE_I2S0_DIN0_PORT_ID == 3)) + #error "Invalid USART0 RTE_I2S0_DIN0 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DIN0_PORT_ID ==0) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 10 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 5 +#elif(RTE_I2S0_DIN0_PORT_ID ==1) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 27 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 0 // no pad +#elif(RTE_I2S0_DIN0_PORT_ID ==2) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 48 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 12 +#elif(RTE_I2S0_DIN0_PORT_ID ==3) +#define RTE_I2S0_DIN0_PORT 0 +#define RTE_I2S0_DIN0_PIN 56 +#define RTE_I2S0_DIN0_MUX 7 +#define RTE_I2S0_DIN0_PAD 20 +#else + #error "Invalid I2S0 RTE_I2S0_DIN0 Pin Configuration!" +#endif + +// I2S0_DOUT1 <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// DOUT1 for I2S0 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S0_DOUT1_PORT_ID 1 +#else +#define RTE_I2S0_DOUT1_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_I2S0_DOUT1_PORT_ID 1 +#if((RTE_I2S0_DOUT1_PORT_ID == 2)||(RTE_I2S0_DOUT1_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_DOUT1 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DOUT1_PORT_ID ==0) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 7 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 2 +#elif(RTE_I2S0_DOUT1_PORT_ID ==1) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 30 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 0//no pad +#elif(RTE_I2S0_DOUT1_PORT_ID ==2) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 51 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 15 +#elif(RTE_I2S0_DOUT1_PORT_ID ==3) +#define RTE_I2S0_DOUT1_PORT 0 +#define RTE_I2S0_DOUT1_PIN 55 +#define RTE_I2S0_DOUT1_MUX 7 +#define RTE_I2S0_DOUT1_PAD 19 +#else + #error "Invalid I2S0 RTE_I2S0_DOUT1 Pin Configuration!" +#endif + +// I2S0_DIN1 <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// DIN1 for I2S0 +#define RTE_I2S0_DIN1_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_I2S0_DIN1_PORT_ID == 2)||(RTE_I2S0_DIN1_PORT_ID == 3)) + #error "Invalid I2S0 RTE_I2S0_DIN1 pin Configuration!" +#endif +#endif +#if(RTE_I2S0_DIN1_PORT_ID ==0) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 6 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 1 +#elif(RTE_I2S0_DIN1_PORT_ID ==1) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 29 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 0//no pad +#elif(RTE_I2S0_DIN1_PORT_ID ==2) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 50 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 14 +#elif(RTE_I2S0_DIN1_PORT_ID ==3) +#define RTE_I2S0_DIN1_PORT 0 +#define RTE_I2S0_DIN1_PIN 54 +#define RTE_I2S0_DIN1_MUX 7 +#define RTE_I2S0_DIN1_PAD 18 +#else + #error "Invalid I2S0 RTE_I2S0_DIN1 Pin Configuration!" +#endif +// FIFO level can have value 1 to 7 +#define I2S0_TX_FIFO_LEVEL ( 2U ) +#define I2S0_RX_FIFO_LEVEL ( 2U ) + +// I2S0_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_TX_RES 1 +#if (RTE_I2S0_TX_RES ==0) +#define I2S0_TX_RES RES_12_BIT +#elif(RTE_I2S0_TX_RES ==1) +#define I2S0_TX_RES RES_16_BIT +#elif(RTE_I2S0_TX_RES ==2) +#define I2S0_TX_RES RES_20_BIT +#elif(RTE_I2S0_TX_RES ==3) +#define I2S0_TX_RES RES_24_BIT +#else + #error "Invalid I2S0 TX channel resolution!" +#endif + +// I2S0_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S0_RX_RES 1 +#if (RTE_I2S0_RX_RES ==0) +#define I2S0_RX_RES RES_12_BIT +#elif(RTE_I2S0_RX_RES ==1) +#define I2S0_RX_RES RES_16_BIT +#elif(RTE_I2S0_RX_RES ==2) +#define I2S0_RX_RES RES_20_BIT +#elif(RTE_I2S0_RX_RES ==3) +#define I2S0_RX_RES RES_24_BIT +#else + #error "Invalid I2S0 RX channel resolution!" +#endif + +#define RTE_I2S0_CHNL_UDMA_TX_EN 1 +#define RTE_I2S0_CHNL_UDMA_TX_CH 15 + +#define RTE_I2S0_CHNL_UDMA_RX_EN 1 +#define RTE_I2S0_CHNL_UDMA_RX_CH 14 + +#define RTE_I2S0_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S0_DMA_RX_LEN_PER_DES 1024 + +// + +// I2S1 [Driver_I2S1] +// Configuration settings for Driver_I2S1 in component ::Drivers:I2S +#define RTE_I2S1 1 +#define I2S1_IRQHandler IRQ014_Handler + +// I2S1_SCLK Pin <0=>P0_3 <1=>P0_7 <2=>P0_8 +/*I2S1 PINS*/ +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2S1_SCLK_PORT_ID 0 +#else +#define RTE_I2S1_SCLK_PORT_ID 2 +#endif +#if(RTE_I2S1_SCLK_PORT_ID == 0) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 3 +#define RTE_I2S1_SCLK_MUX 2 +#elif(RTE_I2S1_SCLK_PORT_ID ==1) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 7 +#define RTE_I2S1_SCLK_MUX 2 +#elif(RTE_I2S1_SCLK_PORT_ID ==2) +#define RTE_I2S1_SCLK_PORT 0 +#define RTE_I2S1_SCLK_PIN 8 +#define RTE_I2S1_SCLK_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_SCLK Pin Configuration!" +#endif + +// I2S1_WSCLK Pin <0=>P0_2 <1=>P0_4 <2=>P0_10 +#define RTE_I2S1_WSCLK_PORT_ID 0 +#if(RTE_I2S1_WSCLK_PORT_ID == 0) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 2 +#define RTE_I2S1_WSCLK_MUX 2 +#elif(RTE_I2S0_WSCLK_PORT_ID == 1) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 4 +#define RTE_I2S1_WSCLK_MUX 2 +#elif(RTE_I2S1_WSCLK_PORT_ID ==2) +#define RTE_I2S1_WSCLK_PORT 0 +#define RTE_I2S1_WSCLK_PIN 10 +#define RTE_I2S1_WSCLK_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_WSCLK Pin Configuration!" +#endif + +// I2S1_DOUT0 Pin <0=>P0_1 <1=>P0_5 <2=>P0_11 +#define RTE_I2S1_DOUT0_PORT_ID 1 +#if(RTE_I2S1_DOUT0_PORT_ID ==0) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 1 +#define RTE_I2S1_DOUT0_MUX 2 +#elif(RTE_I2S1_DOUT0_PORT_ID ==1) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 5 +#define RTE_I2S1_DOUT0_MUX 2 +#elif(RTE_I2S1_DOUT0_PORT_ID ==2) +#define RTE_I2S1_DOUT0_PORT 0 +#define RTE_I2S1_DOUT0_PIN 11 +#define RTE_I2S1_DOUT0_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_DOUT0 Pin Configuration!" +#endif + +// I2S1_DIN0 Pin <0=>P0_0 <1=>P0_6 <2=>P0_9 <3=>P0_13 +#define RTE_I2S1_DIN0_PORT_ID 1 +#if(RTE_I2S1_DIN0_PORT_ID ==0) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 0 +#define RTE_I2S1_DIN0_MUX 2 +#elif(RTE_I2S1_DIN0_PORT_ID ==1) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 6 +#define RTE_I2S1_DIN0_MUX 2 +#elif(RTE_I2S1_DIN0_PORT_ID ==2) +#define RTE_I2S1_DIN0_PORT 0 +#define RTE_I2S1_DIN0_PIN 9 +#define RTE_I2S1_DIN0_MUX 2 +#else + #error "Invalid I2S1 RTE_I2S1_DIN0 Pin Configuration!" +#endif + +// FIFO level can have value 1 to 7 +#define I2S1_TX_FIFO_LEVEL ( 2U ) +#define I2S1_RX_FIFO_LEVEL ( 2U ) + +// I2S1_TX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_TX_RES 1 +#if (RTE_I2S1_TX_RES ==0) +#define I2S1_TX_RES RES_12_BIT +#elif(RTE_I2S1_TX_RES ==1) +#define I2S1_TX_RES RES_16_BIT +#elif(RTE_I2S1_TX_RES ==2) +#define I2S1_TX_RES RES_20_BIT +#elif(RTE_I2S1_TX_RES ==3) +#define I2S1_TX_RES RES_24_BIT +#else + #error "Invalid I2S1 TX channel resolution!" +#endif + +// I2S1_RX_RES <0=>12 +// <1=>16 +// <2=>20 +// <3=>24 +#define RTE_I2S1_RX_RES 1 +#if (RTE_I2S1_RX_RES ==0) +#define I2S1_RX_RES RES_12_BIT +#elif(RTE_I2S1_RX_RES ==1) +#define I2S1_RX_RES RES_16_BIT +#elif(RTE_I2S1_RX_RES ==2) +#define I2S1_RX_RES RES_20_BIT +#elif(RTE_I2S1_RX_RES ==3) +#define I2S1_RX_RES RES_24_BIT +#else + #error "Invalid I2S1 RX channel resolution!" +#endif + +#define RTE_I2S1_CHNL_UDMA_TX_EN 1 +#define RTE_I2S1_CHNL_UDMA_TX_CH 7 + +#define RTE_I2S1_CHNL_UDMA_RX_EN 1 +#define RTE_I2S1_CHNL_UDMA_RX_CH 6 + +#define RTE_I2S1_DMA_TX_LEN_PER_DES 1024 +#define RTE_I2S1_DMA_RX_LEN_PER_DES 1024 + +// I2S1 [Driver_I2S1] + +// I2C0 (Inter-integrated Circuit Interface 0) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C + +#define RTE_I2C0 1 +#define I2C0_IRQHandler IRQ042_Handler + +// I2C0_SCL Pin <0=>P0_7 <1=>P0_65 <2=>P0_66 <3=>P0_75 <4=>P0_32 + +#ifndef CHIP_917_6x6 +#define RTE_I2C0_SCL_PORT_ID 0 +#if((RTE_I2C0_SCL_PORT_ID == 4)) + #error "Invalid I2C0 RTE_I2C0_SCL_PIN Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_I2C0_SCL_PORT_ID 0 +#if((RTE_I2C0_SCL_PORT_ID == 1)||(RTE_I2C0_SCL_PORT_ID == 2)||(RTE_I2C0_SCL_PORT_ID == 3)) + #error "Invalid I2C0 RTE_I2C0_SCL_PIN Configuration!" +#endif +#endif +#if (RTE_I2C0_SCL_PORT_ID == 0) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 7 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 2 +#define RTE_I2C0_SCL_I2C_REN 7 +#elif(RTE_I2C0_SCL_PORT_ID == 1) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 65 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 23 +#define RTE_I2C0_SCL_I2C_REN 1 +#elif(RTE_I2C0_SCL_PORT_ID == 2) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 66 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 24 +#define RTE_I2C0_SCL_I2C_REN 2 +#elif(RTE_I2C0_SCL_PORT_ID == 3) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 75 +#define RTE_I2C0_SCL_MUX 4 +#define RTE_I2C0_SCL_PAD 33 +#define RTE_I2C0_SCL_I2C_REN 11 +#elif(RTE_I2C0_SCL_PORT_ID == 4) +#define RTE_I2C0_SCL_PORT 0 +#define RTE_I2C0_SCL_PIN 32 +#define RTE_I2C0_SCL_MUX 11 +#define RTE_I2C0_SCL_PAD 9 +#define RTE_I2C0_SCL_I2C_REN 32 +#else + #error "Invalid I2C0 RTE_I2C0_SCL Pin Configuration!" +#endif + +// I2C0_SCL Pin <0=>P0_6 <1=>P0_64 <2=>P0_67 <3=>P0_74 <4=>P0_31 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2C0_SDA_PORT_ID 3 +#else +#define RTE_I2C0_SDA_PORT_ID 0 +#endif +#if((RTE_I2C0_SDA_PORT_ID == 4)) + #error "Invalid I2C0 RTE_I2C0_SDA Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_I2C0_SDA_PORT_ID 0 +#if((RTE_I2C0_SDA_PORT_ID == 1)||(RTE_I2C0_SDA_PORT_ID == 2)||(RTE_I2C0_SDA_PORT_ID == 3)) + #error "Invalid I2C0 RTE_I2C0_SDA Configuration!" +#endif +#endif +#if (RTE_I2C0_SDA_PORT_ID == 0) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 6 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 1 +#define RTE_I2C0_SDA_I2C_REN 6 +#elif(RTE_I2C0_SDA_PORT_ID == 1) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 64 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 22 +#define RTE_I2C0_SDA_I2C_REN 0 +#elif(RTE_I2C0_SDA_PORT_ID == 2) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 67 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 25 +#define RTE_I2C0_SDA_I2C_REN 3 +#elif(RTE_I2C0_SDA_PORT_ID == 3) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 74 +#define RTE_I2C0_SDA_MUX 4 +#define RTE_I2C0_SDA_PAD 32 +#define RTE_I2C0_SDA_I2C_REN 10 +#elif(RTE_I2C0_SDA_PORT_ID == 4) +#define RTE_I2C0_SDA_PORT 0 +#define RTE_I2C0_SDA_PIN 31 +#define RTE_I2C0_SDA_MUX 11 +#define RTE_I2C0_SDA_PAD 9 +#define RTE_I2C0_SDA_I2C_REN 31 +#else + #error "Invalid I2C0 RTE_I2C0_SDA Pin Configuration!" +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define I2C_DMA 0 +#if (I2C_DMA == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif +// I2C0 [Driver_I2C0] + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#define I2C1_IRQHandler IRQ061_Handler +// I2C1_SCL Pin <0=>P0_6 <1=>P0_29 <2=>P0_50 <3=>P0_54 <4=>P0_64 <4=>P0_66 <4=>P0_70 <7=>P0_33 +#ifndef CHIP_917_6x6 +#define RTE_I2C1_SCL_PORT_ID 2 +#if((RTE_I2C1_SCL_PORT_ID == 7)) + #error "Invalid I2C1_SCL pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_I2C1_SCL_PORT_ID 7 +#if((RTE_I2C1_SCL_PORT_ID == 2)||(RTE_I2C1_SCL_PORT_ID == 3)||(RTE_I2C1_SCL_PORT_ID == 4)||(RTE_I2C1_SCL_PORT_ID == 5)) + #error "Invalid I2C1_SCL pin Configuration!" +#endif +#endif +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 6 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 1 +#define RTE_I2C1_SCL_REN 6 +#elif(RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 29 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 0//no pad +#define RTE_I2C1_SCL_REN 29 +#elif(RTE_I2C1_SCL_PORT_ID == 2) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 50 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 14 +#define RTE_I2C1_SCL_REN 50 +#elif(RTE_I2C1_SCL_PORT_ID == 3) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 54 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 18 +#define RTE_I2C1_SCL_REN 54 +#elif(RTE_I2C1_SCL_PORT_ID == 4) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 64 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 22 +#define RTE_I2C1_SCL_REN 0 +#elif(RTE_I2C1_SCL_PORT_ID == 5) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 66 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 24 +#define RTE_I2C1_SCL_REN 2 +#elif(RTE_I2C1_SCL_PORT_ID == 6) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 70 +#define RTE_I2C1_SCL_MUX 5 +#define RTE_I2C1_SCL_PAD 29 +#define RTE_I2C1_SCL_REN 6 +#elif(RTE_I2C1_SCL_PORT_ID == 7) +#define RTE_I2C1_SCL_PORT 0 +#define RTE_I2C1_SCL_PIN 33 +#define RTE_I2C1_SCL_MUX 11 +#define RTE_I2C1_SCL_PAD 9 +#define RTE_I2C1_SCL_REN 33 +/**/ +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SCL Pin <0=>P0_7 <1=>P0_30 <2=>P0_51 <3=>P0_55 <4=>P0_65 <4=>P0_67 <4=>P0_71 <7=>P0_34 +#ifdef CHIP_917_6x6 +#define RTE_I2C1_SDA_PORT_ID 7 +#if((RTE_I2C1_SDA_PORT_ID == 2)||(RTE_I2C1_SDA_PORT_ID == 3)||(RTE_I2C1_SDA_PORT_ID == 4)||(RTE_I2C1_SDA_PORT_ID == 5)) + #error "Invalid I2C1_SDA pin Configuration!" +#endif +#endif + +#ifndef CHIP_917_6x6 +#define RTE_I2C1_SDA_PORT_ID 2 +#if((RTE_I2C1_SDA_PORT_ID == 7)) + #error "Invalid I2C1_SDA pin Configuration!" +#endif +#endif +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 7 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 2 +#define RTE_I2C1_SDA_REN 7 +#elif(RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 30 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 0//no pad +#define RTE_I2C1_SDA_REN 30 +#elif(RTE_I2C1_SDA_PORT_ID == 2) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 51 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 15 +#define RTE_I2C1_SDA_REN 51 +#elif(RTE_I2C1_SDA_PORT_ID == 3) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 55 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 19 +#define RTE_I2C1_SDA_REN 55 +#elif(RTE_I2C1_SDA_PORT_ID == 4) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 65 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 23 +#define RTE_I2C1_SDA_REN 1 +#elif(RTE_I2C1_SDA_PORT_ID == 5) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 67 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 25 +#define RTE_I2C1_SDA_REN 3 +#elif(RTE_I2C1_SDA_PORT_ID == 6) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 71 +#define RTE_I2C1_SDA_MUX 5 +#define RTE_I2C1_SDA_PAD 29 +#define RTE_I2C1_SDA_REN 7 +#elif(RTE_I2C1_SDA_PORT_ID == 7) +#define RTE_I2C1_SDA_PORT 0 +#define RTE_I2C1_SDA_PIN 34 +#define RTE_I2C1_SDA_MUX 11 +#define RTE_I2C1_SDA_PAD 9 +#define RTE_I2C1_SDA_REN 34 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C1 [Driver_I2C1] + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 1 +#define I2C2_IRQHandler IRQ013_Handler + +// I2C2_SCL Pin <0=>P0_1 <1=>P0_5 <2=>P0_7 <3=>P0_8 <4=>P0_13 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_I2C2_SCL_PORT_ID 1 +#else +#define RTE_I2C2_SCL_PORT_ID 0 +#endif +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 1 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 1 +#elif(RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 5 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 5 +#elif(RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 7 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 7 +#elif(RTE_I2C2_SCL_PORT_ID == 3) +#define RTE_I2C2_SCL_PORT 0 +#define RTE_I2C2_SCL_PIN 8 +#define RTE_I2C2_SCL_MUX 4 +#define RTE_I2C2_SCL_REN 8 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>P0_0 <1=>P0_4 <2=>P0_6 <3=>P0_9 <4=>P0_11 <5=>P0_12 +#define RTE_I2C2_SDA_PORT_ID 1 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 0 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_I2C_REN 0 +#elif(RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 4 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 4 +#elif(RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 6 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 6 +#elif(RTE_I2C2_SDA_PORT_ID == 3) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 9 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_I2C_REN 9 +#elif(RTE_I2C2_SDA_PORT_ID == 4) +#define RTE_I2C2_SDA_PORT 0 +#define RTE_I2C2_SDA_PIN 11 +#define RTE_I2C2_SDA_MUX 4 +#define RTE_I2C2_SDA_REN 11 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif + +#define IC_SCL_STUCK_TIMEOUT 20 +#define IC_SDA_STUCK_TIMEOUT 20 + +#define DMA_EN 0 +#if (DMA_EN == 1) +#define DMA_TX_TL 1 +#define DMA_RX_TL 1 +#endif + +// I2C2 [Driver_I2C2] + +// GSPI (Generic SPI master) [Driver_GSPI_MASTER] +// Configuration settings for Driver_GSPI_MASTER in component ::Drivers:GSPI +#define RTE_GSPI_MASTER 1 + +// GSPI_MASTER_CLK <0=>P0_8 <1=>P0_25 <2=>P0_46 <3=>P0_52 +// CLK of GSPI0 +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CLK_PORT_ID 1 +#endif + +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CLK_PORT_ID 1 +#if((RTE_GSPI_MASTER_CLK_PORT_ID == 2)||(RTE_GSPI_MASTER_CLK_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_CLK_PORT_ID == 0) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 8 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 3 +#elif(RTE_GSPI_MASTER_CLK_PORT_ID ==1) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 25 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CLK_PORT_ID ==2) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 46 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 10 +#elif(RTE_GSPI_MASTER_CLK_PORT_ID ==3) +#define RTE_GSPI_MASTER_CLK_PORT 0 +#define RTE_GSPI_MASTER_CLK_PIN 52 +#define RTE_GSPI_MASTER_CLK_MUX 4 +#define RTE_GSPI_MASTER_CLK_PAD 16 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CLK_PIN Pin Configuration!" +#endif + +// GSPI_MASTER_CS0 +// <0=>P0_9 <1=>P0_28 <2=>P0_49 <3=>P0_53 +// CS0 of GSPI0 +// +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CS0_PORT_ID 0 +#endif + +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_CS0_PORT_ID 1 +#if((RTE_GSPI_MASTER_CS0_PORT_ID == 2)||(RTE_GSPI_MASTER_CS0_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_CS0_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 9 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 4 +#elif(RTE_GSPI_MASTER_CS0_PORT_ID ==1) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 28 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CS0_PORT_ID ==2) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 49 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 13 +#elif(RTE_GSPI_MASTER_CS0_PORT_ID ==3) +#define RTE_GSPI_MASTER_CS0 1 +#define RTE_GSPI_MASTER_CS0_PORT 0 +#define RTE_GSPI_MASTER_CS0_PIN 53 +#define RTE_GSPI_MASTER_CS0_MUX 4 +#define RTE_GSPI_MASTER_CS0_PAD 17 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS0_PIN Pin Configuration!" +#endif + +#ifndef CHIP_917_6x6 +// GSPI_MASTER_CS1 +// <0=>P0_10 <1=>P0_29 <2=>P0_50 <3=>P0_54 +// CS1 of GSPI0 +// +#define RTE_GSPI_MASTER_CS1_PORT_ID 2 +#if(RTE_GSPI_MASTER_CS1_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 10 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 5 +#elif(RTE_GSPI_MASTER_CS1_PORT_ID ==1) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 29 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CS1_PORT_ID ==2) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 50 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 14 +#elif(RTE_GSPI_MASTER_CS1_PORT_ID ==3) +#define RTE_GSPI_MASTER_CS1 1 +#define RTE_GSPI_MASTER_CS1_PORT 0 +#define RTE_GSPI_MASTER_CS1_PIN 54 +#define RTE_GSPI_MASTER_CS1_MUX 4 +#define RTE_GSPI_MASTER_CS1_PAD 18 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS1_PIN Pin Configuration!" +#endif + +// GSPI_MASTER_CS2 +// <0=>P0_15 <1=>P0_30 <2=>P0_51 <3=>P0_55 +// CS2 of GSPI0 +// +#define RTE_GSPI_MASTER_CS2_PORT_ID 1 +#if(RTE_GSPI_MASTER_CS2_PORT_ID == 0) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 15 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 8 +#elif(RTE_GSPI_MASTER_CS2_PORT_ID ==1) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 30 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_CS2_PORT_ID ==2) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 51 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 15 +#elif(RTE_GSPI_MASTER_CS2_PORT_ID ==3) +#define RTE_GSPI_MASTER_CS2 1 +#define RTE_GSPI_MASTER_CS2_PORT 0 +#define RTE_GSPI_MASTER_CS2_PIN 55 +#define RTE_GSPI_MASTER_CS2_MUX 4 +#define RTE_GSPI_MASTER_CS2_PAD 19 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_CS2_PIN Pin Configuration!" +#endif +#endif + +// GSPI_MASTER_MOSI <0=>P0_12 <1=>P0_27 <2=>P0_48 <3=>P0_57 <4=>P0_6 +// MOSI of GSPI0 +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MOSI_PORT_ID 1 +#if((RTE_GSPI_MASTER_MOSI_PORT_ID == 4)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN pin Configuration!" +#endif +#endif + +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MOSI_PORT_ID 1 +#if((RTE_GSPI_MASTER_MOSI_PORT_ID == 0)||(RTE_GSPI_MASTER_MOSI_PORT_ID == 2)||(RTE_GSPI_MASTER_MOSI_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_MOSI_PORT_ID == 0) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 12 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 7 +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==1) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 27 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==2) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 48 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 12 +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==3) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 57 +#define RTE_GSPI_MASTER_MOSI_MUX 4 +#define RTE_GSPI_MASTER_MOSI_PAD 21 +#elif(RTE_GSPI_MASTER_MOSI_PORT_ID ==4) +#define RTE_GSPI_MASTER_MOSI_PORT 0 +#define RTE_GSPI_MASTER_MOSI_PIN 6 +#define RTE_GSPI_MASTER_MOSI_MUX 12 +#define RTE_GSPI_MASTER_MOSI_PAD 1 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_MOSI_PIN Pin Configuration!" +#endif + +// GSPI_MASTER_MISO <0=>P0_11 <1=>P0_26 <2=>P0_47 <3=>P0_56 +// MISO of GSPI0 +#ifndef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MISO_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_GSPI_MASTER_MISO_PORT_ID 1 +#if((RTE_GSPI_MASTER_MISO_PORT_ID == 2)||(RTE_GSPI_MASTER_MISO_PORT_ID == 3)) + #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN pin Configuration!" +#endif +#endif +#if(RTE_GSPI_MASTER_MISO_PORT_ID == 0) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 11 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 6 +#elif(RTE_GSPI_MASTER_MISO_PORT_ID ==1) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 26 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 0//NO PAD +#elif(RTE_GSPI_MASTER_MISO_PORT_ID ==2) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 47 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 11 +#elif(RTE_GSPI_MASTER_MISO_PORT_ID ==3) +#define RTE_GSPI_MASTER_MISO_PORT 0 +#define RTE_GSPI_MASTER_MISO_PIN 56 +#define RTE_GSPI_MASTER_MISO_MUX 4 +#define RTE_GSPI_MASTER_MISO_PAD 20 +#else + #error "Invalid GSPI0 RTE_GSPI_MASTER_MISO_PIN Pin Configuration!" +#endif + +#if defined(HIGH_THROUGHPUT_EN) && (HIGH_THROUGHPUT_EN == 1) +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 1 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 3 +#define RTE_FIFO_AEMPTY_THRLD 7 + +#define TX_DMA_ARB_SIZE ARBSIZE_4 +#define RX_DMA_ARB_SIZE ARBSIZE_8 +#else +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_TX_CH 11 + +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_EN 0 +#define RTE_GSPI_MASTER_CHNL_UDMA_RX_CH 10 + +#define RTE_FIFO_AFULL_THRLD 0 +#define RTE_FIFO_AEMPTY_THRLD 0 + +#define TX_DMA_ARB_SIZE ARBSIZE_1 +#define RX_DMA_ARB_SIZE ARBSIZE_1 +#endif + +// (Generic SPI master)[Driver_GSPI_MASTER] + + +// (State Configurable Timer) Interface +#define SCT_CLOCK_SOURCE CT_INTFPLLCLK +#define SCT_CLOCK_DIV_FACT 2 + +//SCT_IN_0 <0=>GPIO_25 <1=>GPIO_64 <2=>GPIO_68 +#ifndef CHIP_917_6x6 +#define RTE_SCT_IN_0_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_0_PORT_ID 0 +#if((RTE_SCT_IN_0_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_0_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_0_PORT_ID == 0) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 25 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 0//no pad +#elif(RTE_SCT_IN_0_PORT_ID == 1) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 64 +#define RTE_SCT_IN_0_MUX 7 +#define RTE_SCT_IN_0_PAD 22 +#elif(RTE_SCT_IN_0_PORT_ID == 2) +#define RTE_SCT_IN_0_PORT 0 +#define RTE_SCT_IN_0_PIN 68 +#define RTE_SCT_IN_0_MUX 9 +#define RTE_SCT_IN_0_PAD 26 +#else + #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif + +//SCT_IN_1 <0=>GPIO_26 <1=>GPIO_65 <2=>GPIO_69 +#ifndef CHIP_917_6x6 +#define RTE_SCT_IN_1_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_1_PORT_ID 0 +#if((RTE_SCT_IN_1_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_1_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_1_PORT_ID == 0) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 26 +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 0//no pad +#elif(RTE_SCT_IN_1_PORT_ID == 1) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 65 +#define RTE_SCT_IN_1_MUX 7 +#define RTE_SCT_IN_1_PAD 23 +#elif(RTE_SCT_IN_1_PORT_ID == 2) +#define RTE_SCT_IN_1_PORT 0 +#define RTE_SCT_IN_1_PIN 69 +#define RTE_SCT_IN_1_MUX 9 +#define RTE_SCT_IN_1_PAD 27 +#else + #error "Invalid RTE_SCT_IN_1_PIN Pin Configuration!" +#endif + +//SCT_IN_2 <0=>GPIO_27 <1=>GPIO_66 <2=>GPIO_70 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_2_PORT_ID 0 +#else +#define RTE_SCT_IN_2_PORT_ID 1 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_2_PORT_ID 0 +#if((RTE_SCT_IN_2_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_2_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_2_PORT_ID == 0) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 27 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 0//no pad +#elif(RTE_SCT_IN_2_PORT_ID == 1) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 66 +#define RTE_SCT_IN_2_MUX 7 +#define RTE_SCT_IN_2_PAD 24 +#elif(RTE_SCT_IN_2_PORT_ID == 2) +#define RTE_SCT_IN_2_PORT 0 +#define RTE_SCT_IN_2_PIN 70 +#define RTE_SCT_IN_2_MUX 9 +#define RTE_SCT_IN_2_PAD 28 +#else + #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif + +//SCT_IN_3 <0=>GPIO_28 <1=>GPIO_67 <2=>GPIO_71 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SCT_IN_3_PORT_ID 0 +#else +#define RTE_SCT_IN_3_PORT_ID 1 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_IN_3_PORT_ID 0 +#if((RTE_SCT_IN_3_PORT_ID == 1)) + #error "Invalid RTE_SCT_IN_3_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_IN_3_PORT_ID == 0) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 28 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 0//no pad +#elif(RTE_SCT_IN_3_PORT_ID == 1) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 67 +#define RTE_SCT_IN_3_MUX 7 +#define RTE_SCT_IN_3_PAD 25 +#elif(RTE_SCT_IN_3_PORT_ID == 2) +#define RTE_SCT_IN_3_PORT 0 +#define RTE_SCT_IN_3_PIN 71 +#define RTE_SCT_IN_3_MUX 9 +#define RTE_SCT_IN_3_PAD 29 +#else + #error "Invalid RTE_SCT_IN_0_PIN Pin Configuration!" +#endif + +// SCT_OUT_0 <0=>GPIO_29 <1=>GPIO_68 +#define RTE_SCT_OUT_0_PORT_ID 0 +#if(RTE_SCT_OUT_0_PORT_ID == 0) +#define RTE_SCT_OUT_0_PORT 0 +#define RTE_SCT_OUT_0_PIN 29 +#define RTE_SCT_OUT_0_MUX 9 +#define RTE_SCT_OUT_0_PAD 0//no pad +#elif(RTE_SCT_OUT_0_PORT_ID ==1) +#define RTE_SCT_OUT_0_PORT 0 +#define RTE_SCT_OUT_0_PIN 68 +#define RTE_SCT_OUT_0_MUX 7 +#define RTE_SCT_OUT_0_PAD 26 +#else + #error "Invalid RTE_SCT_OUT_0_PIN Pin Configuration!" +#endif + +// SCT_OUT_1 <0=>GPIO_30 <1=>GPIO_69 +#define RTE_SCT_OUT_1_PORT_ID 0 +#if(RTE_SCT_OUT_1_PORT_ID == 0) +#define RTE_SCT_OUT_1_PORT 0 +#define RTE_SCT_OUT_1_PIN 30 +#define RTE_SCT_OUT_1_MUX 9 +#define RTE_SCT_OUT_1_PAD 0//no pad +#elif(RTE_SCT_OUT_1_PORT_ID == 1) +#define RTE_SCT_OUT_1_PORT 0 +#define RTE_SCT_OUT_1_PIN 69 +#define RTE_SCT_OUT_1_MUX 7 +#define RTE_SCT_OUT_1_PAD 27 +#else + #error "Invalid RTE_SCT_OUT_1_PIN Pin Configuration!" +#endif + +/// SCT_OUT_2 <0=>GPIO_70 <1=>GPIO_8 +#define RTE_SCT_OUT_2_PORT_ID 0 +#ifndef CHIP_917_6x6 +#if((RTE_SCT_OUT_2_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_2_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_2_PORT_ID == 0) +#define RTE_SCT_OUT_2_PORT 0 +#define RTE_SCT_OUT_2_PIN 70 +#define RTE_SCT_OUT_2_MUX 7 +#define RTE_SCT_OUT_2_PAD 28 +#elif(RTE_SCT_OUT_2_PORT_ID == 1) +#define RTE_SCT_OUT_2_PORT 0 +#define RTE_SCT_OUT_2_PIN 8 +#define RTE_SCT_OUT_2_MUX 12 +#define RTE_SCT_OUT_2_PAD 3 +#else + #error "Invalid RTE_SCT_OUT_2_PIN Pin Configuration!" +#endif +/**/ +//SCT_OUT_3 <0=>GPIO_71 <1=>GPIO_9 +#define RTE_SCT_OUT_3_PORT_ID 0 +#ifndef CHIP_917_6x6 +#if((RTE_SCT_OUT_3_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_3_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_3_PORT_ID == 0) +#define RTE_SCT_OUT_3_PORT 0 +#define RTE_SCT_OUT_3_PIN 71 +#define RTE_SCT_OUT_3_MUX 7 +#define RTE_SCT_OUT_3_PAD 29 +#elif(RTE_SCT_OUT_3_PORT_ID == 1) +#define RTE_SCT_OUT_3_PORT 0 +#define RTE_SCT_OUT_3_PIN 9 +#define RTE_SCT_OUT_3_MUX 12 +#define RTE_SCT_OUT_3_PAD 4 +#else + #error "Invalid RTE_SCT_OUT_3_PIN Pin Configuration!" +#endif + +//SCT_OUT_4 <0=>GPIO_72 <1=>GPIO_68 + +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_4_PORT_ID 0 +#if((RTE_SCT_OUT_4_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_4_PORT_ID 1 +#if((RTE_SCT_OUT_4_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_4_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_4_PORT_ID == 0) +/**/ +#define RTE_SCT_OUT_4_PORT 0 +#define RTE_SCT_OUT_4_PIN 72 +#define RTE_SCT_OUT_4_MUX 7 +#define RTE_SCT_OUT_4_PAD 30 +#elif(RTE_SCT_OUT_4_PORT_ID == 1) +#define RTE_SCT_OUT_4_PORT 0 +#define RTE_SCT_OUT_4_PIN 68 +#define RTE_SCT_OUT_4_MUX 13 +#define RTE_SCT_OUT_4_PAD 26 +#else + #error "Invalid RTE_SCT_OUT_4_PIN Pin Configuration!" +#endif +//SCT_OUT_5 <0=>GPIO_73 <1=>GPIO_69 +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_5_PORT_ID 0 +#if((RTE_SCT_OUT_5_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_5_PORT_ID 1 +#if((RTE_SCT_OUT_5_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_5_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_5_PORT_ID == 0) +#define RTE_SCT_OUT_5_PORT 2 +#define RTE_SCT_OUT_5_PIN 73 +#define RTE_SCT_OUT_5_MUX 7 +#define RTE_SCT_OUT_5_PAD 31 +#elif(RTE_SCT_OUT_5_PORT_ID == 1) +#define RTE_SCT_OUT_5_PORT 0 +#define RTE_SCT_OUT_5_PIN 69 +#define RTE_SCT_OUT_5_MUX 13 +#define RTE_SCT_OUT_5_PAD 27 +#else + #error "Invalid RTE_SCT_OUT_5_PIN Pin Configuration!" +#endif + +//SCT_OUT_6 <0=>GPIO_74 <1=>GPIO_70 +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_6_PORT_ID 0 +#if((RTE_SCT_OUT_6_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_6_PORT_ID 1 +#if((RTE_SCT_OUT_6_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_6_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_6_PORT_ID == 0) +#define RTE_SCT_OUT_6_PORT 0 +#define RTE_SCT_OUT_6_PIN 74 +#define RTE_SCT_OUT_6_MUX 7 +#define RTE_SCT_OUT_6_PAD 32 +#elif(RTE_SCT_OUT_6_PORT_ID == 1) +#define RTE_SCT_OUT_6_PORT 0 +#define RTE_SCT_OUT_6_PIN 70 +#define RTE_SCT_OUT_6_MUX 13 +#define RTE_SCT_OUT_6_PAD 28 +#else + #error "Invalid RTE_SCT_OUT_6_PIN Pin Configuration!" +#endif + +// SCT_OUT_7 <0=>GPIO_75 <1=>GPIO_71 + +#ifndef CHIP_917_6x6 +#define RTE_SCT_OUT_7_PORT_ID 0 +#if((RTE_SCT_OUT_7_PORT_ID == 1)) + #error "Invalid RTE_SCT_OUT_7_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SCT_OUT_7_PORT_ID 1 +#if((RTE_SCT_OUT_7_PORT_ID == 0)) + #error "Invalid RTE_SCT_OUT_7_PIN pin Configuration!" +#endif +#endif +#if(RTE_SCT_OUT_7_PORT_ID == 0) +#define RTE_SCT_OUT_7_PORT 0 +#define RTE_SCT_OUT_7_PIN 75 +#define RTE_SCT_OUT_7_MUX 7 +#define RTE_SCT_OUT_7_PAD 33 +#elif(RTE_SCT_OUT_7_PORT_ID == 1) +#define RTE_SCT_OUT_7_PORT 0 +#define RTE_SCT_OUT_7_PIN 71 +#define RTE_SCT_OUT_7_MUX 13 +#define RTE_SCT_OUT_7_PAD 29 +#else + #error "Invalid RTE_SCT_OUT_7_PIN Pin Configuration!" +#endif + +// SIO // +//<> Serial Input Output +//SIO_0 <0=>GPIO_6 <1=>GPIO_25 <2=>GPIO_64 <3=>GPIO_72 +#ifndef CHIP_917_6x6 +#define RTE_SIO_0_PORT_ID 0 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_0_PORT_ID 0 +#if((RTE_SIO_0_PORT_ID == 2)||(RTE_SIO_0_PORT_ID == 3)) + #error "Invalid RTE_SIO_0_PIN pin Configuration!" +#endif +#endif +#if(RTE_SIO_0_PORT_ID == 0) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 6 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 1 +#elif(RTE_SIO_0_PORT_ID == 1) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 25 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 0//no pad +#elif(RTE_SIO_0_PORT_ID == 2) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 64 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 22 +#elif(RTE_SIO_0_PORT_ID == 3) +#define RTE_SIO_0_PORT 0 +#define RTE_SIO_0_PIN 72 +#define RTE_SIO_0_MUX 1 +#define RTE_SIO_0_PAD 30 +#else + #error "Invalid RTE_SIO_0_PIN Pin Configuration!" +#endif + +//SIO_1 <0=>GPIO_7 <1=>GPIO_26 <2=>GPIO_65 <3=>GPIO_73 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_1_PORT_ID 1 +#else +#define RTE_SIO_1_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_1_PORT_ID 1 +#if((RTE_SIO_1_PORT_ID == 2)||(RTE_SIO_1_PORT_ID == 3)) + #error "Invalid RTE_SIO_1_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_1_PORT_ID == 0) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 7 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 2 +#elif(RTE_SIO_1_PORT_ID == 1) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 26 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 0// no pad +#elif(RTE_SIO_1_PORT_ID == 2) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 65 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 23 +#elif(RTE_SIO_1_PORT_ID == 3) +#define RTE_SIO_1_PORT 0 +#define RTE_SIO_1_PIN 73 +#define RTE_SIO_1_MUX 1 +#define RTE_SIO_1_PAD 31 +#else + #error "Invalid RTE_SIO_1_PIN Pin Configuration!" +#endif + + +// SIO_2 <0=>GPIO_8 <1=>GPIO_27 <2=>GPIO_66 <3=>GPIO_74 +#ifndef CHIP_917_6x6 +#define RTE_SIO_2_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_2_PORT_ID 0 +#if((RTE_SIO_2_PORT_ID == 2)||(RTE_SIO_2_PORT_ID == 3)) + #error "Invalid RTE_SIO_2_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_2_PORT_ID == 0) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 8 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 3 +#elif(RTE_SIO_2_PORT_ID == 1) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 27 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 0//no pad +#elif(RTE_SIO_2_PORT_ID == 2) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 66 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 24 +#elif(RTE_SIO_2_PORT_ID == 3) +#define RTE_SIO_2_PORT 0 +#define RTE_SIO_2_PIN 74 +#define RTE_SIO_2_MUX 1 +#define RTE_SIO_2_PAD 32 +#else + #error "Invalid RTE_SIO_2_PIN Pin Configuration!" +#endif + + + +//SIO_3 <0=>GPIO_9 <1=>GPIO_28 <2=>GPIO_67 <3=>GPIO_75 +#ifndef CHIP_917_6x6 +#define RTE_SIO_3_PORT_ID 1 +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_3_PORT_ID 0 +#if((RTE_SIO_3_PORT_ID == 2)||(RTE_SIO_3_PORT_ID == 3)) + #error "Invalid RTE_SIO_3_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_3_PORT_ID == 0) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 9 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 4 +#elif(RTE_SIO_3_PORT_ID == 1) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 28 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 0//no pad +#elif(RTE_SIO_3_PORT_ID == 2) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 67 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 25 +#elif(RTE_SIO_3_PORT_ID == 3) +#define RTE_SIO_3_PORT 0 +#define RTE_SIO_3_PIN 75 +#define RTE_SIO_3_MUX 1 +#define RTE_SIO_3_PAD 33 +#else + #error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif + + +//SIO_4 <0=>GPIO_10 <1=>GPIO_29 <2=>GPIO_68 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_4_PORT_ID 1 +#else +#define RTE_SIO_4_PORT_ID 0 +#endif +#if(RTE_SIO_4_PORT_ID == 0) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 10 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 5 +#elif(RTE_SIO_4_PORT_ID == 1) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 29 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 0//NO PAD +#elif(RTE_SIO_4_PORT_ID == 2) +#define RTE_SIO_4_PORT 0 +#define RTE_SIO_4_PIN 68 +#define RTE_SIO_4_MUX 1 +#define RTE_SIO_4_PAD 26 +#else + #error "Invalid RTE_SIO_3_PIN Pin Configuration!" +#endif + +// SIO_5 <0=>GPIO_11 <1=>GPIO_30 <2=>GPIO_69 +#define RTE_SIO_5_PORT_ID 0 +#if(RTE_SIO_5_PORT_ID == 0) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 11 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 6 +#elif(RTE_SIO_5_PORT_ID == 1) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 30 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 0//no pad +#elif(RTE_SIO_5_PORT_ID == 2) +#define RTE_SIO_5_PORT 0 +#define RTE_SIO_5_PIN 69 +#define RTE_SIO_5_MUX 1 +#define RTE_SIO_5_PAD 27 +#else + #error "Invalid RTE_SIO_5_PIN Pin Configuration!" +#endif + +// SIO_6 GPIO_70 +#define RTE_SIO_6_PORT 0 +#define RTE_SIO_6_PIN 70 +#define RTE_SIO_6_MUX 1 +#define RTE_SIO_6_PAD 28 + +// SIO_7 <0=>GPIO_15 <1=>GPIO_71 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_SIO_7_PORT_ID 1 +#else +#define RTE_SIO_7_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_SIO_7_PORT_ID 1 +#if((RTE_SIO_7_PORT_ID == 0)) + #error "Invalid RTE_SIO_7_PIN Configuration!" +#endif +#endif +#if(RTE_SIO_7_PORT_ID == 0) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 15 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 8 +#elif(RTE_SIO_7_PORT_ID == 1) +#define RTE_SIO_7_PORT 0 +#define RTE_SIO_7_PIN 71 +#define RTE_SIO_7_MUX 1 +#define RTE_SIO_7_PAD 29 +#else + #error "Invalid RTE_SIO_7_PIN Pin Configuration!" +#endif + + +//<> Pulse Width Modulation +//PWM_1H <0=>GPIO_7 <1=>GPIO_64 <2=>GPIO_65 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1H_PORT_ID 0 +#else +#define RTE_PWM_1H_PORT_ID 1 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_1H_PORT_ID 0 +#if((RTE_PWM_1H_PORT_ID == 1)) + #error "Invalid RTE_PWM_1H_PIN Configuration!" +#endif +#endif +#if(RTE_PWM_1H_PORT_ID == 0) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 7 +#define RTE_PWM_1H_MUX 10 +#define RTE_PWM_1H_PAD 2 +#elif(RTE_PWM_1H_PORT_ID == 1) +#define RTE_PWM_1H_PORT 0 +#define RTE_PWM_1H_PIN 65 +#define RTE_PWM_1H_MUX 8 +#define RTE_PWM_1H_PAD 22 +#else + #error "Invalid RTE_PWM_1H_PIN Pin Configuration!" +#endif + + +// PWM_1L <0=>GPIO_6 <1=>GPIO_64 <2=>GPIO_64 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_1L_PORT_ID 1 +#else +#define RTE_PWM_1L_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_1L_PORT_ID 0 +#if((RTE_PWM_1L_PORT_ID == 1)) + #error "Invalid RTE_PWM_1L_PIN Configuration!" +#endif +#endif +#if(RTE_PWM_1L_PORT_ID == 0) +#define RTE_PWM_1L_PORT 0 +#define RTE_PWM_1L_PIN 6 +#define RTE_PWM_1L_MUX 10 +#define RTE_PWM_1L_PAD 1 +#elif(RTE_PWM_1L_PORT_ID == 1) +#define RTE_PWM_1L_PORT 0 +#define RTE_PWM_1L_PIN 64 +#define RTE_PWM_1L_MUX 8 +#define RTE_PWM_1L_PAD 22 +#else + #error "Invalid RTE_PWM_1L_PIN Pin Configuration!" +#endif + +//PWM_2H <0=>GPIO_9 <1=>GPIO_67 <2=>GPIO_69 +#ifndef CHIP_917_6x6 +#define RTE_PWM_2H_PORT_ID 0 +#if((RTE_PWM_2H_PORT_ID == 2)) + #error "Invalid RTE_PWM_2H_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_2H_PORT_ID 0 +#if((RTE_PWM_2H_PORT_ID == 1)) + #error "Invalid RTE_PWM_2H_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_2H_PORT_ID == 0) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 9 +#define RTE_PWM_2H_MUX 10 +#define RTE_PWM_2H_PAD 4 +#elif(RTE_PWM_2H_PORT_ID == 1) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 67 +#define RTE_PWM_2H_MUX 8 +#define RTE_PWM_2H_PAD 25 +#elif(RTE_PWM_2H_PORT_ID == 2) +#define RTE_PWM_2H_PORT 0 +#define RTE_PWM_2H_PIN 69 +#define RTE_PWM_2H_MUX 12 +#define RTE_PWM_2H_PAD 27 +#else + #error "Invalid RTE_PWM_2H_PIN Pin Configuration!" +#endif + + +// PWM_2L <0=>GPIO_8 <1=>GPIO_66 <2=>GPIO_68 +#ifndef CHIP_917_6x6 +#define RTE_PWM_2L_PORT_ID 0 +#if((RTE_PWM_2L_PORT_ID == 2)) + #error "Invalid RTE_PWM_2L_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_2L_PORT_ID 0 +#if((RTE_PWM_2L_PORT_ID == 1)) + #error "Invalid RTE_PWM_2L_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_2L_PORT_ID == 0) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 8 +#define RTE_PWM_2L_MUX 10 +#define RTE_PWM_2L_PAD 3 +#elif(RTE_PWM_2L_PORT_ID == 1) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 66 +#define RTE_PWM_2L_MUX 8 +#define RTE_PWM_2L_PAD 24 +#elif(RTE_PWM_2L_PORT_ID == 2) +#define RTE_PWM_2L_PORT 0 +#define RTE_PWM_2L_PIN 68 +#define RTE_PWM_2L_MUX 12 +#define RTE_PWM_2L_PAD 26 +#else + #error "Invalid RTE_PWM_2L_PIN Pin Configuration!" +#endif + +// PWM_3H <0=>GPIO_11 <1=>GPIO_69 +#define RTE_PWM_3H_PORT_ID 0 +#if(RTE_PWM_3H_PORT_ID == 0) +#define RTE_PWM_3H_PORT 0 +#define RTE_PWM_3H_PIN 11 +#define RTE_PWM_3H_MUX 10 +#define RTE_PWM_3H_PAD 6 +#elif(RTE_PWM_3H_PORT_ID == 1) +#define RTE_PWM_3H_PORT 0 +#define RTE_PWM_3H_PIN 69 +#define RTE_PWM_3H_MUX 8 +#define RTE_PWM_3H_PAD 27 +#else + #error "Invalid RTE_PWM_3H_PIN Pin Configuration!" +#endif + +// PWM_3L <0=>GPIO_10 <1=>GPIO_68 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_3L_PORT_ID 1 +#else +#define RTE_PWM_3L_PORT_ID 0 +#endif +#if(RTE_PWM_3L_PORT_ID == 0) +#define RTE_PWM_3L_PORT 0 +#define RTE_PWM_3L_PIN 10 +#define RTE_PWM_3L_MUX 10 +#define RTE_PWM_3L_PAD 5 +#elif(RTE_PWM_3L_PORT_ID == 1) +#define RTE_PWM_3L_PORT 0 +#define RTE_PWM_3L_PIN 68 +#define RTE_PWM_3L_MUX 8 +#define RTE_PWM_3L_PAD 26 +#else + #error "Invalid RTE_PWM_3L_PIN Pin Configuration!" +#endif + + +// PWM_4H <0=>GPIO_15 <1=>GPIO_71 + +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4H_PORT_ID 1 +#else +#define RTE_PWM_4H_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_4H_PORT_ID 1 +#if((RTE_PWM_4H_PORT_ID == 0)) + #error "Invalid RTE_PWM_4H_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_4H_PORT_ID == 0) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 15 +#define RTE_PWM_4H_MUX 10 +#define RTE_PWM_4H_PAD 8 +#elif(RTE_PWM_4H_PORT_ID == 1) +#define RTE_PWM_4H_PORT 0 +#define RTE_PWM_4H_PIN 71 +#define RTE_PWM_4H_MUX 8 +#define RTE_PWM_4H_PAD 29 +#else + #error "Invalid RTE_PWM_4H_PIN Pin Configuration!" +#endif + + +// PWM_4H <0=>GPIO_12 <1=>GPIO_70 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_PWM_4L_PORT_ID 1 +#else +#define RTE_PWM_4L_PORT_ID 0 +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_PWM_4L_PORT_ID 1 +#if(RTE_PWM_4L_PORT_ID == 0) + #error "Invalid RTE_PWM_4L_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_4L_PORT_ID == 0) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 12 +#define RTE_PWM_4L_MUX 10 +#define RTE_PWM_4L_PAD 7 +#elif(RTE_PWM_4L_PORT_ID == 1) +#define RTE_PWM_4L_PORT 0 +#define RTE_PWM_4L_PIN 70 +#define RTE_PWM_4L_MUX 8 +#define RTE_PWM_4L_PAD 28 +#else + #error "Invalid RTE_PWM_4L_PIN Pin Configuration!" +#endif + + +// PWM_FAULTA <0=>GPIO_25 <1=>GPIO_68 <1=>GPIO_73 +#define RTE_PWM_FAULTA_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_FAULTA_PORT_ID == 2)) + #error "Invalid RTE_PWM_FAULTA_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_FAULTA_PORT_ID == 0) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 25 +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 0//no pad +#elif(RTE_PWM_FAULTA_PORT_ID == 1) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 68 +#define RTE_PWM_FAULTA_MUX 10 +#define RTE_PWM_FAULTA_PAD 26 +#elif(RTE_PWM_FAULTA_PORT_ID == 2) +#define RTE_PWM_FAULTA_PORT 0 +#define RTE_PWM_FAULTA_PIN 73 +#define RTE_PWM_FAULTA_MUX 8 +#define RTE_PWM_FAULTA_PAD 31 +#else + #error "Invalid RTE_PWM_FAULTA_PIN Pin Configuration!" +#endif + +// PWM_FAULTB <0=>GPIO_26 <1=>GPIO_69 <1=>GPIO_74 +#define RTE_PWM_FAULTB_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_FAULTB_PORT_ID == 2)) + #error "Invalid RTE_PWM_FAULTB_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_FAULTB_PORT_ID == 0) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 26 +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 0//no pad +#elif(RTE_PWM_FAULTB_PORT_ID == 1) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 69 +#define RTE_PWM_FAULTB_MUX 10 +#define RTE_PWM_FAULTB_PAD 27 +#elif(RTE_PWM_FAULTB_PORT_ID == 2) +#define RTE_PWM_FAULTB_PORT 0 +#define RTE_PWM_FAULTB_PIN 74 +#define RTE_PWM_FAULTB_MUX 8 +#define RTE_PWM_FAULTB_PAD 32 +#else + #error "Invalid RTE_PWM_FAULTB_PIN Pin Configuration!" +#endif +//PWM_SLP_EVENT_TRIG GPIO_72 +#define RTE_PWM_SLP_EVENT_TRIG_PORT 0 +#define RTE_PWM_SLP_EVENT_TRIG_PIN 72 +#define RTE_PWM_SLP_EVENT_TRIG_MUX 8 +#define RTE_PWM_SLP_EVENT_TRIG_PAD 30 + +//PWM_TMR_EXT_TRIG_1 <0=>GPIO_27 <1=>GPIO_51 <2=>GPIO_70 <3=>GPIO_75 +#define RTE_PWM_TMR_EXT_TRIG_1_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1)||(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3)) + #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 27 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 0//no pad +#elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 51 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 15 +#elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 70 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 28 +#elif(RTE_PWM_TMR_EXT_TRIG_1_PORT_ID == 3) +#define RTE_PWM_TMR_EXT_TRIG_1_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_1_PIN 75 +#define RTE_PWM_TMR_EXT_TRIG_1_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_1_PAD 33 +#else + #error "Invalid RTE_PWM_TMR_EXT_TRIG_1_PIN Pin Configuration!" +#endif + + +//PWM_TMR_EXT_TRIG_2 <0=>GPIO_28 <1=>GPIO_54 <2=>GPIO_71 +#define RTE_PWM_TMR_EXT_TRIG_2_PORT_ID 0 +#ifdef CHIP_917_6x6 +#if((RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1)) + #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN pin Configuration!" +#endif +#endif +#if(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 0) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 28 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 0//no pad +#elif(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 1) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 54 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 8 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 18 +#elif(RTE_PWM_TMR_EXT_TRIG_2_PORT_ID == 2) +#define RTE_PWM_TMR_EXT_TRIG_2_PORT 0 +#define RTE_PWM_TMR_EXT_TRIG_2_PIN 71 +#define RTE_PWM_TMR_EXT_TRIG_2_MUX 10 +#define RTE_PWM_TMR_EXT_TRIG_2_PAD 29 +#else + #error "Invalid RTE_PWM_TMR_EXT_TRIG_2_PIN Pin Configuration!" +#endif + + +//<> QEI (Quadrature Encode Interface) + +//QEI_DIR <0=>GPIO_28 <1=>GPIO_49 <2=>GPIO_57 <3=>GPIO_67 <4=>GPIO_71 <5=>GPIO_73 <6=>GPIO_11 <7=>GPIO_34 +#ifndef CHIP_917_6x6 +#define RTE_QEI_DIR_PORT_ID 4 +#if((RTE_QEI_DIR_PORT_ID == 7)||(RTE_QEI_DIR_PORT_ID == 6)) + #error "Invalid RTE_QEI_DIR_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_DIR_PORT_ID 6 +#if((RTE_QEI_DIR_PORT_ID == 1)||(RTE_QEI_DIR_PORT_ID == 2)|| (RTE_QEI_DIR_PORT_ID == 3)||(RTE_QEI_DIR_PORT_ID == 5)) + #error "Invalid RTE_QEI_DIR_PIN pin Configuration!" +#endif +#endif +#if(RTE_QEI_DIR_PORT_ID == 0) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 28 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 0//no pad +#elif(RTE_QEI_DIR_PORT_ID == 1) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 49 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 13 +#elif(RTE_QEI_DIR_PORT_ID == 2) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 57 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 21 +#elif(RTE_QEI_DIR_PORT_ID == 3) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 67 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 25 +#elif(RTE_QEI_DIR_PORT_ID == 4) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 71 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 29 +#elif(RTE_QEI_DIR_PORT_ID == 5) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 73 +#define RTE_QEI_DIR_MUX 3 +#define RTE_QEI_DIR_PAD 31 +#elif(RTE_QEI_DIR_PORT_ID == 6) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 11 +#define RTE_QEI_DIR_MUX 5 +#define RTE_QEI_DIR_PAD 6 +#elif(RTE_QEI_DIR_PORT_ID == 7) +#define RTE_QEI_DIR_PORT 0 +#define RTE_QEI_DIR_PIN 34 +#define RTE_QEI_DIR_MUX 13 +#define RTE_QEI_DIR_PAD 9 +#else + #error "Invalid RTE_QEI_DIR_PIN Pin Configuration!" +#endif + + +//QEI_IDX <0=>GPIO_25 <1=>GPIO_46 <2=>GPIO_52 <3=>GPIO_64 <4=>GPIO_68 <5=>GPIO_72 <6=>GPIO_8 <7=>GPIO_13 +#ifndef CHIP_917_6x6 +#define RTE_QEI_IDX_PORT_ID 4 +#if((RTE_QEI_IDX_PORT_ID == 7)||(RTE_QEI_IDX_PORT_ID == 6)) + #error "Invalid RTE_QEI_IDX_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_IDX_PORT_ID 6 +#if((RTE_QEI_IDX_PORT_ID == 1) || (RTE_QEI_IDX_PORT_ID == 2)||(RTE_QEI_IDX_PORT_ID == 3)||(RTE_QEI_IDX_PORT_ID == 5)) + #error "Invalid RTE_QEI_IDX_PIN pin Configuration!" +#endif +#endif +#if(RTE_QEI_IDX_PORT_ID == 0) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 25 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 0//no pad +#elif(RTE_QEI_IDX_PORT_ID == 1) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 46 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 10 +#elif(RTE_QEI_IDX_PORT_ID == 2) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 52 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 16 +#elif(RTE_QEI_IDX_PORT_ID == 3) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 64 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 22 +#elif(RTE_QEI_IDX_PORT_ID == 4) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 68 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 26 +#elif(RTE_QEI_IDX_PORT_ID == 5) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 72 +#define RTE_QEI_IDX_MUX 3 +#define RTE_QEI_IDX_PAD 30 +#elif(RTE_QEI_IDX_PORT_ID == 6) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 8 +#define RTE_QEI_IDX_MUX 5 +#define RTE_QEI_IDX_PAD 3 +#elif(RTE_QEI_IDX_PORT_ID == 7) +#define RTE_QEI_IDX_PORT 0 +#define RTE_QEI_IDX_PIN 31 +#define RTE_QEI_IDX_MUX 13 +#define RTE_QEI_IDX_PAD 9 +#else + #error "Invalid RTE_QEI_IDX_PIN Pin Configuration!" +#endif + + +//QEI_PHA <0=>GPIO_26 <1=>GPIO_47 <2=>GPIO_53 <3=>GPIO_65 <4=>GPIO_69 <5=>GPIO_73 <6=>GPIO_9 <7=>GPIO_32 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHA_PORT_ID 4 +#else +#define RTE_QEI_PHA_PORT_ID 5 +#endif +#if((RTE_QEI_PHA_PORT_ID == 7)||(RTE_QEI_PHA_PORT_ID == 6)) + #error "Invalid RTE_QEI_PHA_PIN pin Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_PHA_PORT_ID 6 +#if((RTE_QEI_PHA_PORT_ID == 1)||(RTE_QEI_PHA_PORT_ID == 2)||(RTE_QEI_PHA_PORT_ID == 3)||(RTE_QEI_PHA_PORT_ID == 5)) + #error "Invalid RTE_QEI_PHA_PIN pin Configuration!" +#endif +#endif +#if(RTE_QEI_PHA_PORT_ID == 0) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 26 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 0//no pad +#elif(RTE_QEI_PHA_PORT_ID == 1) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 47 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 11 +#elif(RTE_QEI_PHA_PORT_ID == 2) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 53 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 17 +#elif(RTE_QEI_PHA_PORT_ID == 3) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 65 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 23 +#elif(RTE_QEI_PHA_PORT_ID == 4) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 69 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 27 +#elif(RTE_QEI_PHA_PORT_ID == 5) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 73 +#define RTE_QEI_PHA_MUX 3 +#define RTE_QEI_PHA_PAD 31 +#elif(RTE_QEI_PHA_PORT_ID == 6) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 9 +#define RTE_QEI_PHA_MUX 5 +#define RTE_QEI_PHA_PAD 4 +#elif(RTE_QEI_PHA_PORT_ID == 7) +#define RTE_QEI_PHA_PORT 0 +#define RTE_QEI_PHA_PIN 32 +#define RTE_QEI_PHA_MUX 13 +#define RTE_QEI_PHA_PAD 9 +#else + #error "Invalid RTE_QEI_PHA_PIN Pin Configuration!" +#endif + +//QEI_PHB <0=>GPIO_27 <1=>GPIO_48 <1=>GPIO_56 <1=>GPIO_66 <1=>GPIO_70 <1=>GPIO_74 <7=>GPIO_33 +#ifndef CHIP_917_6x6 +#ifdef SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER +#define RTE_QEI_PHB_PORT_ID 5 +#else +#define RTE_QEI_PHB_PORT_ID 4 +#endif +#if((RTE_QEI_PHB_PORT_ID == 6) || (RTE_QEI_PHB_PORT_ID == 7)) + #error "Invalid RTE_QEI_PHB_PIN Configuration!" +#endif +#endif +#ifdef CHIP_917_6x6 +#define RTE_QEI_PHB_PORT_ID 6 +#if((RTE_QEI_PHB_PORT_ID == 1) || (RTE_QEI_PHB_PORT_ID == 2)||(RTE_QEI_PHB_PORT_ID == 3)||(RTE_QEI_PHB_PORT_ID == 5) ) + #error "Invalid RTE_QEI_PHB_PIN Configuration!" +#endif +#endif +#if(RTE_QEI_PHB_PORT_ID == 0) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 27 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 0//no pad +#elif(RTE_QEI_PHB_PORT_ID == 1) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 48 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 12 +#elif(RTE_QEI_PHB_PORT_ID == 2) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 56 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 20 +#elif(RTE_QEI_PHB_PORT_ID == 3) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 66 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 24 +#elif(RTE_QEI_PHB_PORT_ID == 4) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 70 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 28 +#elif(RTE_QEI_PHB_PORT_ID == 5) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 74 +#define RTE_QEI_PHB_MUX 3 +#define RTE_QEI_PHB_PAD 32 +#elif(RTE_QEI_PHB_PORT_ID == 6) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 10 +#define RTE_QEI_PHB_MUX 5 +#define RTE_QEI_PHB_PAD 5 +#elif(RTE_QEI_PHB_PORT_ID == 7) +#define RTE_QEI_PHB_PORT 0 +#define RTE_QEI_PHB_PIN 33 +#define RTE_QEI_PHB_MUX 13 +#define RTE_QEI_PHB_PAD 9 +#else + #error "Invalid RTE_QEI_PHB_PIN Pin Configuration!" +#endif + + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/clock_update.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/clock_update.h new file mode 100644 index 000000000..8b4f47339 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/clock_update.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* @file clock_update.h +* @brief +******************************************************************************* +* # License +* Copyright 2022 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +// Includes Files + +#include "base_types.h" + +#ifndef RSI_CLOCK_UPDATE_H +#define RSI_CLOCK_UPDATE_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum PERI_CLKS { + M4_USART0, // Enables or Disables USART1 Peripheral clock when it is passed + M4_UART1, // Enables or Disables USART2 Master Peripheral clock when it is passed + M4_SSI_MST, // Enables or Disables SSI Master Peripheral clock when it is passed + M4_CT, // Enables or Disables CT Peripheral clock when it is passed +#ifndef SLI_SI917 + M4_SD_MEM, // Enables or Disables SD_MEM Peripheral clock when it is passed + M4_CCI, // Enables or Disables CCI Peripheral clock when it is passed +#endif + M4_QSPI, // Enables or Disables QSPI Peripheral clock when it is passed + M4_QSPI2, + M4_GSPI, // Enables or Disables GSPI Peripheral clock when it is passed + M4_ETHERNET, // Enables or Disables ETHERNET Peripheral clock when it is passed + M4_I2SM, // Enables or Disables I2SM Peripheral clock when it is passed + ULPSS_SSI, + ULPSS_I2S, + ULPSS_UART, + ULPSS_TIMER, + ULPSS_AUX, + //ULPSS_VAD, + ULPSS_TOUCH, +} PERI_CLKS_T; + +uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src); +uint32_t GetTickCount(void); +void SysTick_Handler(void); + +#ifdef __SYSTICK +void rsi_delay_ms(uint32_t val); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // RSI_CLOCK_UPDATE_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h new file mode 100644 index 000000000..6818bcae8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_crc.h @@ -0,0 +1,101 @@ +/***************************************************************************/ /** +* @file rsi_crc.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef RSI_CRC_H +#define RSI_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define DIN_WIDTH_32 31 +#define DIN_WIDTH_16 15 +#define DIN_WIDTH_8 7 + +// brief: Structure of CRC Calculation +typedef struct { + uint32_t crc; //Calculated CRC Value + uint32_t polynomial; //Polynomial Value for CRC Calculation + unsigned int + polyWidth : 5; //Number of bits/width of the polynomial has to be written here for the computation of final CRC + uint32_t lfsrVal; //lfsr Initialization value for CRC Calculation + unsigned int widthType : 3; //Data Width taken Variable. + //When width_type - 0 :Take the data width from either reg programmed or from cnt + //width_type -1 :Take the data width from Reg. + //width_type-2 : Take the data width from CNT. + unsigned int dinWidth : 5; //Valid number of bits in the input data in din_width_from_reg set mode + uint32_t numBytes; //Input data number of bytes + unsigned int aempty : 4; //Almost empty Threshold value. Max value is 15 + unsigned int afull : 4; //Almost Full Threshold value. Max value is 15 + uint32_t InputData; + uint32_t swapLfsr; + uint32_t swapDin; + uint32_t useUdma; + uint32_t inputSize; + uint32_t dataIn; + uint32_t bitWidth; + uint32_t lfsrState; +} RSI_CRC_PARAMS_T; + +// CRC FUNCTION PROTOTYPES +void crc_set_gen_control(CRC_Type *pCRC); + +uint32_t crc_get_gen_status(CRC_Type *pCRC); + +void crc_polynomial(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_polynomial_width(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +void crc_lfsr_init(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_use_swapped_init(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_set_data_width_type(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_set_fifo_thresholds(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +uint32_t crc_write_data(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams, uint32_t data); + +uint32_t monitor_crc_calc(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +void crc_lfsr_dynamic_write(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + +void crc_reset_fifo(CRC_Type *pCRC); + +uint32_t crc_get_fifo_status(CRC_Type *pCRC); +#ifdef __cplusplus +} +#endif + +#endif // RSI_CRC_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h new file mode 100644 index 000000000..e335926b8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_ct.h @@ -0,0 +1,1087 @@ +/***************************************************************************/ /** +* @file rsi_ct.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" + +#ifndef RSI_CT_H +#define RSI_CT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_CT_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1 +#define RSI_CT_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1 + +#define CLK_ENABLE_SET_3_REG (*((uint32_t volatile *)(0x46000000 + 0x10))) +#define M4SS_CT_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x10))) + +#define ENABLE 1 +#define DISABLE 0 + +#define LOW 0 +#define HIGH 1 + +#define INPUT_CNT 4 +#define OUTPUT_CNT 8 +#define COUNTERS_CNT 2 +#define EVENT_CNT 38 +#define DMA_MODE 1 + +//CT Interrupt Flags +#define RSI_CT_EVENT_INTR_0_l (1UL << 0) // Counter 0 Interrupt event interrupt flag +#define RSI_CT_EVENT_FIFO_0_FULL_l (1UL << 1) // FIFO full signal of Counter 0 interrupt flag +#define RSI_CT_EVENT_COUNTER_0_IS_ZERO_l (1UL << 2) // Counter 0 hit zero in active mode interrupt flag +#define RSI_CT_EVENT_COUNTER_0_IS_PEAK_l (1UL << 3) // Counter 0 hit peak (MATCH) in active mode interrupt flag +#define RSI_CT_EVENT_INTR_1_l (1UL << 16) // Counter 1 Interrupt event interrupt flag +#define RSI_CT_EVENT_FIFO_1_FULL_l (1UL << 17) // FIFO full signal of Counter 1 interrupt flag +#define RSI_CT_EVENT_COUNTER_1_IS_ZERO_l (1UL << 18) // Counter 1 hit zero in active mode interrupt flag +#define RSI_CT_EVENT_COUNTER_1_IS_PEAK_l (1UL << 19) // Counter 1 hit peak (MATCH) in active mode interrupt flag + +#define COUNTER_0 0 +#define COUNTER_1 1 +#define COUNTER_0_1 2 + +// CT Control Set Register Bits +#define COUNTER0_UP (0x1 << 4) +#define COUNTER0_DOWN (0x2 << 4) +#define COUNTER0_UP_DOWN (0x3 << 4) + +#define COUNTER1_UP (0x1 << 20) +#define COUNTER1_DOWN (0x2 << 20) +#define COUNTER1_UP_DOWN (0x3 << 20) + +#define COUNTER32_BITMODE (1UL << 0) // 32 bit Counter mode +#define SOFTRESET_COUNTER_0 (1UL << 1) // soft reset counter 0 +#define PERIODIC_ENCOUNTER_0 (1UL << 2) // Periodic/One shot counter 0 +#define COUNTER0_TRIG (1UL << 3) // trigger Counter 0 +#define COUNTER0_SYNC_TRIG (1UL << 6) // Sync trigger for counter 0 +#define BUF_REG0EN (1UL << 7) // Buffer enable for counter 0 +#define SOFTRESET_COUNTER_1 (1UL << 17) // soft reset counter 1 +#define PERIODIC_ENCOUNTER_1 (1UL << 18) // Periodic/One shot counter 1 +#define COUNTER1_TRIG (1UL << 19) // trigger Counter 1 +#define COUNTER1_SYNC_TRIG (1UL << 22) // Sync trigger for counter 1 +#define BUF_REG1EN (1UL << 23) // Buffer enable for counter 1 + +#define RISE_EDGE_MASK0 (1UL << 0) +#define RISE_EDGE_MASK1 (1UL << 1) +#define RISE_EDGE_MASK2 (1UL << 2) +#define RISE_EDGE_MASK3 (1UL << 3) + +#define FALL_EDGE_MASK0 (1UL << 4) +#define FALL_EDGE_MASK1 (1UL << 5) +#define FALL_EDGE_MASK2 (1UL << 6) +#define FALL_EDGE_MASK3 (1UL << 7) + +#define RFE_EDGE_MASK0 (1UL << 8) +#define RFE_EDGE_MASK1 (1UL << 9) +#define RFE_EDGE_MASK2 (1UL << 10) +#define RFE_EDGE_MASK3 (1UL << 11) + +#define LEVEL_LOW_MASK0 (1UL << 12) +#define LEVEL_LOW_MASK1 (1UL << 13) +#define LEVEL_LOW_MASK2 (1UL << 14) +#define LEVEL_LOW_MASK3 (1UL << 15) + +#define LEVEL_HIGH_MASK0 (1UL << 16) +#define LEVEL_HIGH_MASK1 (1UL << 17) +#define LEVEL_HIGH_MASK2 (1UL << 18) +#define LEVEL_HIGH_MASK3 (1UL << 19) + +// CT example defines +#define OUTPUT_OCU_0 (1UL << 0) // Counter 0 output OCU +#define OCU_DMA_0 (1UL << 4) // Counter 0 OCU DMA enable +#define OCU_8_MODE_0 (1UL << 5) // OCU using 16 bit mode +#define OUTPUT_OCU_1 (1UL << 16) // Counter 1output OCU +#define OCU_DMA_1 (1UL << 20) // Counter 1 OCU DMA enable +#define OCU_8_MODE_1 (1UL << 21) // OCU using 16 bit mode +#define MAKE_OUTPUT_0_HIGH_SEL_0 (0x2 << 6) +#define MAKE_OUTPUT_0_LOW_SEL_0 (0x3 << 9) +#define MAKE_OUTPUT_1_HIGH_SEL_1 (0x3 << 22) +#define MAKE_OUTPUT_1_LOW_SEL_1 (0x2 << 25) +#define OCU_SYNC_WITH_0 (0x1 << 1) +#define OCU_SYNC_WITH_1 (0x1 << 17) + +#define OUTPUT_0_TGL_0_MAX 7 // Counter 0 output OCU +#define OUTPUT_0_TGL_1_MAX 7 // Counter 0 OCU DMA enable +#define TGL_CNT_0_PEAK 0xFF // OCU using 16 bit mode +#define OUTPUT_1_TGL_0_MAX 7 // Counter 0 output OCU +#define OUTPUT_1_TGL_1_MAX 7 // Counter 0 OCU DMA enable +#define TGL_CNT_1_PEAK 0xFF + +#define MAX_PEAK_VALUE_0 0x1000 +#define MAX_PEAK_VLAUE_1 0x2000 + +#define UDMA_CHNL_0 0 +#define UDMA_CHNL_1 1 +#define UDMA_CHNL_2 2 +#define UDMA_CHNL_3 3 +#define UDMA_CHNL_4 4 +#define UDMA_CHNL_5 5 +#define UDMA_CHNL_6 6 +#define UDMA_CHNL_7 7 + +#define UDMA_CONTROL_TABLE_BASE_CHNL0 0x00000000 +#define UDMA_CONTROL_TABLE_BASE_CHNL1 0x00000010 +#define WFG_ON_PERIOD 0xFF + +#define USE_DMA 1 +#define NO_DMA 0 + +#define PERIODIC_EN_COUNTER_0_FRM_REG (1UL << 2) +#define PERIODIC_EN_COUNTER_1_FRM_REG (1UL << 18) +#define COUNTER_0_TRIG (1UL << 3) +#define COUNTER_1_TRIG (1UL << 19) +#define COUNTER_0_UP (0x1 << 4) +#define COUNTER_1_UP (0x1 << 20) + +#define MAKE_OUTPUT_0_TGL_SEL_1 1 + +#define AND_COUNTER0(valid, event) ((event << 0) | (valid << 8)) +#define AND_COUNTER1(valid, event) ((event << 16) | (valid << 24)) + +#define OR_COUNTER0(valid, event) ((event << 0) | (valid << 8)) +#define OR_COUNTER1(valid, event) ((event << 16) | (valid << 24)) + +typedef CT0_Type RSI_CT_T; +typedef CT_MUX_REG_Type RSI_CT_MUX_REG_T; + +/**============================================================================ + * @brief CT Driver Capabilities. + ============================================================================**/ + +typedef struct { + unsigned int NoOfInputs : 3; /*!< Number of Input signals */ + unsigned int NoOfOutputs : 4; /*!< Number of Output signlas */ + unsigned int NumOfCounters : 4; /*!< Number of Counters present in CT module */ + unsigned int NoOfEvents : 6; /*!< Number of Events can be generated by input events */ + unsigned int DMAIntf : 1; /*!< Supports DMA interface or not */ +} RSI_CT_CAPABILITIES_T; +/****** CT Events ******/ +#define CT_EVT_0 1 +#define CT_EVT_1 2 +#define CT_EVT_2 3 +#define CT_EVT_3 4 +#define CT_EVT_4 5 +#define CT_EVT_5 6 +#define CT_EVT_6 7 +#define CT_EVT_7 8 +#define CT_EVT_8 9 +#define CT_EVT_9 10 +#define CT_EVT_10 11 +#define CT_EVT_11 12 +#define CT_EVT_12 13 +#define CT_EVT_13 14 +#define CT_EVT_14 15 +#define CT_EVT_15 16 +#define CT_EVT_16 17 +#define CT_EVT_17 18 +#define CT_EVT_18 19 +#define CT_EVT_19 20 +#define CT_EVT_20 21 +#define CT_EVT_21 22 +#define CT_EVT_22 23 +#define CT_EVT_23 24 +#define CT_EVT_24 25 +#define CT_EVT_25 26 +#define CT_EVT_26 27 +#define CT_EVT_27 28 +#define CT_EVT_28 29 +#define CT_EVT_29 30 +#define CT_EVT_30 31 +#define CT_EVT_31 32 +#define CT_EVT_32 33 +#define CT_EVT_33 34 +#define CT_EVT_34 35 +#define CT_EVT_35 36 +#define CT_EVT_36 37 +#define CT_EVT_37 38 + +// CT Callback Flags +#define CT_INTR_0_l_CB 0x01 // Callback ID for Counter 0 Interrupt event +#define CT_FIFO_0_FULL_l_CB 0x02 // Callback ID for FIFO full signal of Counter 0 +#define CT_COUNTER_0_IS_ZERO_l_CB 0x03 // Callback ID for Counter 0 hit zero in active mode +#define CT_COUNTER_0_IS_PEAK_l_CB 0x04 // Callback ID for Counter 0 hit peak (MATCH) in active mode +#define CT_INTR_1_l_CB 0x05 // Callback ID for Counter 1 Interrupt event +#define CT_FIFO_1_FULL_l_CB 0x06 // Callback ID for FIFO full signal of Counter 1 +#define CT_COUNTER_1_IS_ZERO_l_CB 0x07 // Callback ID for Counter 1 hit zero in active mode +#define CT_COUNTER_1_IS_PEAK_l_CB 0x08 // Callback ID for Counter 1 hit peak (MATCH) in active mode +#define CT_OCU_DMA_EN_COUNTER0 0x09 // OCU DMA call back +#define CT_OCU_DMA_EN_COUNTER1 0x0A + +// OCU parameter structure +typedef struct OCU_PARAMS { + uint16_t CompareVal1_0; /*!< two thresholds for counter 0 */ + uint16_t CompareVal2_0; + uint16_t CompareVal1_1; + uint16_t CompareVal2_1; + uint16_t CompareNextVal1_0; /*!< two next thresholds for counter 0 */ + uint16_t CompareNextVal2_0; + uint16_t CompareNextVal1_1; // next threshold for counter 1 + uint16_t CompareNextVal2_1; // next threshold for counter 1 + uint16_t SyncWith0; // Sync Value + uint16_t SyncWith1; +} OCU_PARAMS_T; + +// WFG control parameters structure +typedef struct WFG_PARAMS { + uint32_t output0_tgl0_sel; + uint32_t output0_tgl1_sel; + uint32_t tgl_cnt0_peak; + uint32_t output1_tgl0_sel; + uint32_t output1_tgl1_sel; + uint32_t tgl_cnt1_peak; +} WFG_PARAMS_T; + +// brief MCPWM Callback structure +typedef struct { + void (*cbFunc)(uint8_t event, uint8_t counterNum); // Call back function pointer +} RSI_CT_CALLBACK_T; + +// brief CT handle type +typedef void *RSI_CT_HANDLE_T; + +/*===================================================*/ +/** + * @fn void RSI_CT_Config(RSI_CT_T *pCT, boolean_t cfg) + * @brief This API is used to set the 32bit/ 16bit coutners + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] cfg : if cfg = 0 32bit Counter, cfg = 1 16bit counter + * @return none + */ +STATIC INLINE void RSI_CT_Config(RSI_CT_T *pCT, boolean_t cfg) +{ + // 32bit/16bit Counters + if (cfg == 1) { + pCT->CT_GEN_CTRL_SET_REG = (1 << 0); + } else { + pCT->CT_GEN_CTRL_RESET_REG = (1 << 0); + } +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetControl(RSI_CT_T *pCT, uint32_t value) + * @brief Programs General control register bit fields + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : This parameter can be the logical OR of the below parameters + - \ref COUNTER32_BITMODE : sets 32bit mode + - \ref SOFTRESET_COUNTER_0 : Resets coutner 0 + - \ref PERIODIC_ENCOUNTER_0 : sets periodic mode + - \ref COUNTER0_TRIG : starts counter 0 + - \ref COUNTER0_UP_DOWN : Counter 0 direction (0,1,2,3) + - \ref COUNTER0_SYNC_TRIG : This enables the counter 0 to run/active when sync is found. + - \ref BUF_REG0EN : Buffer will be enabled and in path for Counter 0 + - \ref SOFTRESET_COUNTER_1 : Resets Counter 1 + - \ref PERIODIC_ENCOUNTER_1 : sets periodic mode + - \ref COUNTER1_TRIG : starts counter 1 + - \ref COUNTER1_UP_DOWN : Counter 1 direction (0,1,2,3) + - \ref COUNTER1_SYNC_TRIG : This enables the counter 1 to run/active when sync is found. + - \ref BUF_REG1EN : Buffer will be enabled and in path for counter 1. + * @return none +*/ +STATIC INLINE void RSI_CT_SetControl(RSI_CT_T *pCT, uint32_t value) +{ + // Sets required control bits + pCT->CT_GEN_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ClearControl(RSI_CT_T *pCT, uint32_t value) + * @brief This API is used to Reset the required control bits in general control set register + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : This parameter can be the logical OR of the required bit ,fields in CT Reset Control register as below. + - \ref COUNTER32_BITMODE : Sets 16bit mode + - \ref PERIODIC_ENCOUNTER_0 : Sets Counter_0 will be in single count mode. + - \ref COUNTER0_UP_DOWN : counter 0 to run in up/down/up-down/down-up directions (0,1,2,3) + - \ref BUF_REG0EN : Buffer will be disabled and in path and in path for Counter 0 + - \ref PERIODIC_ENCOUNTER_1 : sets Counter 1 will be in single count mode + - \ref COUNTER1_UP_DOWN : Counter 1 to run in up/down/up-down/down-up directions(0,1,2,3) + - \ref BUF_REG1EN : Buffer will be disabled and in path for counter 1. + * @return none + */ +STATIC INLINE void RSI_CT_ClearControl(RSI_CT_T *pCT, uint32_t value) +{ + // Resets required control bits + pCT->CT_GEN_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_StartEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to start any counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : ORed value of Events for counter0 and counter1 + \n This parameter can be the logical OR of the event number for counter 0 and counter 1 + \n possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_StartEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + pCT->CT_START_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_StartEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for start counter operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : This parameter can be the logical OR of the below parameters. + - START_COUNTER_0_AND_EVENT : AND expression for AND event in start Counter_0 event, + possible values are 0x0 to 0xF. + - START_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_AND_EVENT : AND expression for AND event in start Counter_1 event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF. + * @param[in] orValue : This parameter can be the logical OR of the below parameters + - START_COUNTER_0_OR_EVENT : OR expression for OR event in start Counter_0 event, + possible values are 0x0 to 0xF. + - START_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_OR_EVENT : OR expression for OR event in start Counter_1 event, + possible values are 0x0 to 0xF. + - START_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF. + * @return none + */ +STATIC INLINE void RSI_CT_StartEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter start + pCT->CT_START_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter start + pCT->CT_START_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_StopEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for stop counter operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Stop Counter AND Event register value, this parameter can be the logical OR of the + - STOP_COUNTER_0_AND_EVENT : AND expression for AND event in stop Counter_0 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - STOP_COUNTER_1_AND_EVENT : AND expression for AND event in stop Counter_1 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Stop Counter OR Event register value,this parameter can be the logical OR of the + - STOP_COUNTER_0_OR_EVENT : OR expression for OR event in stop Counter_0 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - STOP_COUNTER_1_OR_EVENT : OR expression for OR event in stop Counter_1 event, + possible values are 0x0 to 0xF, + - STOP_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_StopEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter stop + pCT->CT_STOP_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter stop + pCT->CT_STOP_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ContinueEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for Continue operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Continue Counter AND Event register value,this parameter can be the logical OR of the + - CONTINUE_COUNTER_0_AND_EVENT : AND expression for AND event in continue Counter_0 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - CONTINUE_COUNTER_1_AND_EVENT : AND expression for AND event in continue Counter_1 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Continue Counter OR Event register value,this parameter can be the logical OR of the + - CONTINUE_COUNTER_0_OR_EVENT : OR expression for OR event in continue Counter_0 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - CONTINUE_COUNTER_1_OR_EVENT : OR expression for OR event in continue Counter_1 event, + possible values are 0x0 to 0xF, + - CONTINUE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_ContinueEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter continue + pCT->CT_CONTINUE_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter continue + pCT->CT_CONTINUE_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_HaltEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for Halt operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Halt Counter AND Event register value,This parameter can be the logical OR of the + - HALT_COUNTER_0_AND_EVENT : AND expression for AND event in halt Counter_0 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - HALT_COUNTER_1_AND_EVENT : AND expression for AND event in halt Counter_1 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Halt Counter OR Event register value + \n This parameter can be the logical OR of the + - HALT_COUNTER_0_OR_EVENT : OR expression for OR event in halt Counter_0 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - HALT_COUNTER_1_OR_EVENT : OR expression for OR event in halt Counter_1 event, + possible values are 0x0 to 0xF, + - HALT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_HaltEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Halt + pCT->CT_HALT_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter Halt + pCT->CT_HALT_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_IncrementEventConfig(RSI_CT_T *pCT,uint32_t andValue, uint32_t orValue) + * @brief This API is used to Configure AND/OR event for increment operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Increment Counter AND Event register value,this parameter can be the logical OR of the + - INCREMENT_COUNTER_0_AND_EVENT : AND expression for AND event in increment Counter_0 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - INCREMENT_COUNTER_1_AND_EVENT : AND expression for AND event in increment Counter_1 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Increment Counter OR Event register value,this parameter can be the logical OR of the + - INCREMENT_COUNTER_0_OR_EVENT : OR expression for OR event in increment Counter_0 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - INCREMENT_COUNTER_1_OR_EVENT : OR expression for OR event in increment Counter_1 event, + possible values are 0x0 to 0xF, + - INCREMENT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF, + * @return none + */ +STATIC INLINE void RSI_CT_IncrementEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Increment + pCT->CT_INCREMENT_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter Increment + pCT->CT_INCREMENT_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_CaptureEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for capture operation + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Capture Counter AND Event register value,This parameter can be the logical OR of the + - CAPTURE_COUNTER_0_AND_EVENT : AND expression for AND event in capture Counter_0 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - CAPTURE_COUNTER_1_AND_EVENT : AND expression for AND event in capture Counter_1 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Capture Counter OR Event register value,This parameter can be the logical OR of the + - CAPTURE_COUNTER_0_OR_EVENT : OR expression for OR event in capture Counter_0 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - CAPTURE_COUNTER_1_OR_EVENT : OR expression for OR event in capture Counter_1 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none +*/ +STATIC INLINE void RSI_CT_CaptureEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + + // AND Event configuration for counter Capture + pCT->CT_CAPTURE_COUNTER_AND_EVENT |= andValue; + // OR Event configuration for counter Capture + pCT->CT_CAPTURE_COUNTER_OR_EVENT |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptEventConfig(RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for interrupt operation. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] andValue : Interrupt Counter AND Event register value,this parameter can be the logical OR of the + - INTR_COUNTER_0_AND_EVENT : AND expression for AND event in interrupt Counter_0 event, + possible values are 0x0 to 0xF, + - INTR_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - INTR_COUNTER_1_AND_EVENT : AND expression for AND event in capture Counter_1 event, + possible values are 0x0 to 0xF, + - INTR_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Capture Counter OR Event register value,this parameter can be the logical OR of the + - CAPTURE_COUNTER_0_OR_EVENT : OR expression for OR event in interrupt Counter_0 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - CAPTURE_COUNTER_1_OR_EVENT : OR expression for OR event in interrupt Counter_1 event, + possible values are 0x0 to 0xF, + - CAPTURE_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_InterruptEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Interrupt + pCT->CT_INTR_AND_EVENT |= andValue; + // OR Event configuration for counter Interrupt + pCT->CT_INTR_OR_EVENT_REG |= orValue; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OutputEventConfig( RSI_CT_T *pCT,uint32_t andValue,uint32_t orValue) + * @brief This API is used to Configure AND/OR event for output operation. + * @param[in] pCT Pointer to the CT instance register area + * @param[in] andValue : Output Counter AND Event register value,this parameter can be the logical OR of the + - OUTPUT_COUNTER_0_AND_EVENT : AND expression for AND event in output Counter_0 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_0_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + - OUTPUT_COUNTER_1_AND_EVENT : AND expression for AND event in output Counter_1 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_1_AND_VLD : Indicates which bits valid for considering AND event, + possible values are 0x0 to 0xF + * @param[in] orValue : Output Counter OR Event register value,this parameter can be the logical OR of the + - OUTPUT_COUNTER_0_OR_EVENT : OR expression for OR event in output Counter_0 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_0_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + - OUTPUT_COUNTER_1_OR_EVENT : OR expression for OR event in output Counter_1 event, + possible values are 0x0 to 0xF, + - OUTPUT_COUNTER_1_OR_VLD : Indicates which bits valid for considering OR event, + possible values are 0x0 to 0xF + * @return none + */ +STATIC INLINE void RSI_CT_OutputEventConfig(RSI_CT_T *pCT, uint32_t andValue, uint32_t orValue) +{ + // AND Event configuration for counter Output + pCT->CT_OUTPUT_AND_EVENT_REG |= andValue; + // OR Event configuration for counter Output + pCT->CT_OUTPUT_OR_EVENT |= orValue; +} +/*===================================================*/ +/** + * @fn void RSI_CT_StopEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to stop counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Stop Event select register value,this parameter can be the logical OR of the + - STOP_EVENT_SEL_0 :event number for counter 0 + - STOP_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_StopEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to stop + pCT->CT_STOP_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ContinueEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief Configures event for Continue operation of Counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Continue Event select register value,this parameter can be the logical OR of the + - CONTINUE_EVENT_SEL_0 :event number for counter 0 + - CONTINUE_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_ContinueEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to continue + pCT->CT_CONTINUE_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_HaltEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief Configures event for HALT operation of Counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Halt Event select register value,this parameter can be the logical OR of the + - HALT_EVENT_SEL_0 :event number for counter 0 + - HALT_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_HaltEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to Halt + pCT->CT_HALT_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_IncrementEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief Configures event for Increment operation of Counter + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Increment Event select register value,this parameter can be the logical OR of the + - INCREMENT_EVENT_SEL_0 :event number for counter 0 + - INCREMENT_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_IncrementEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to Increment + pCT->CT_INCREMENT_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_CaptureEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to capture counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Capture Event select register value,this parameter can be the logical OR of the + - CAPTURE_EVENT_SEL_0 :event number for counter 0 + - CAPTURE_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_CaptureEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to capture + pCT->CT_CAPTURE_COUNTER_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OutputEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event to output counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Output Event select register value,this parameter can be the logical OR of the + - OUTPUT_EVENT_SEL_0 :event number for counter 0 + - OUTPUT_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_OutputEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to output event + pCT->CT_OUTPUT_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptEventSelect(RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to select the input event for interrupt + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : Output Event select register value,this parameter can be the logical OR of the + - INTR_EVENT_SEL_0 :event number for counter 0 + - INTR_EVENT_SEL_1 :event number for counter 1 + - possible event numbers are 1 to 38 if 0 : No event is selected + * @return none + */ +STATIC INLINE void RSI_CT_InterruptEventSelect(RSI_CT_T *pCT, uint32_t value) +{ + // Event number to interrupt + pCT->CT_INTR_EVENT_SEL |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OutputEventADCTrigger(RSI_CT_MUX_REG_T *pCTmux,uint8_t output1,uint8_t output2) + * @brief This API is used to select one of the ADC trigger output + * @param[in] pCTmux : Pointer to the CT instance register area + * @param[in] output1 : output event for ADC trigger (0 to 31) + * @param[in] output2 : output event for ADC trigger (0 to 31) + * @return none + */ +STATIC INLINE void RSI_CT_OutputEventADCTrigger(RSI_CT_MUX_REG_T *pCTmux, uint8_t output1, uint8_t output2) +{ + // Sets the output pin number for ADC + pCTmux->CT_OUTPUT_EVENT1_ADC_SEL_b.OUTPUT_EVENT_ADC_SEL = (unsigned int)(output1 & 0x0F); + // Sets the output pin number for ADC + pCTmux->CT_OUTPUT_EVENT2_ADC_SEL_b.OUTPUT_EVENT_ADC_SEL = (unsigned int)(output2 & 0x0F); +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetCount(RSI_CT_T *pCT, uint32_t count) + * @brief Sets the Counter Initial value. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] count : 32 bit Counter initial value,this parameter can be the logical OR of the + - \ref COUNTER_0 : Counter 0 load value ( 0x0 to 0xFFFF) + - \ref COUNTER_1 : Counter 1 load value ( 0x0 to 0xFFFF) + - possible values are 0x0 to 0xFFFFFFFF + * @return none + */ +STATIC INLINE void RSI_CT_SetCount(RSI_CT_T *pCT, uint32_t count) +{ + // Sets the Coutner start value + pCT->CT_COUNTER_REG = count; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OCUConfigSet(RSI_CT_T *pCT, uint32_t value) + * @brief This API is used to set OCU control parameters + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : OCU control register value,this parameter can be the logical OR of the below parameters + - OUTPUT_IS_OCU_0 : sets Counter 0 output in OCU mode + - SYNC_WITH_0 : Indicates whether the other channel is in sync with this counter(0,1,2,3) + - OCU_DMA_MODE_0 : OCU DMA mode is active or not for counter-0 + - OCU_8_16_MODE_0 : 16 bits or only 8-bits of the counter-0 are used in OCU mode + - OUTPUT_IS_OCU_1 : sets Counter 1 output in OCU mode + - SYNC_WITH_1 : Indicates whether the other channel is in sync with this counter(0,1,2,3) + - OCU_DMA_MODE_1 : OCU DMA mode is active or not for counter-1 + - OCU_8_16_MODE_1 : 16 bits or only 8-bits of the counter-1 are used in OCU mode + * @return none + */ +STATIC INLINE void RSI_CT_OCUConfigSet(RSI_CT_T *pCT, uint32_t value) +{ + // OCU control parameters + pCT->CT_OCU_CTRL_REG |= value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_OCUConfigReset(RSI_CT_T *pCT, uint32_t value) + * @brief This API is used to set OCU control parameters + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] value : OCU control register value,this parameter can be the logical OR required bit. + * @return none + */ +STATIC INLINE void RSI_CT_OCUConfigReset(RSI_CT_T *pCT, uint32_t value) +{ + // OCU control parameters + pCT->CT_OCU_CTRL_REG &= ~value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptEnable(RSI_CT_T *pCT, uint32_t unmaskFlags) + * @brief Enable the interrupts in State Configurable Timer. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] unmaskFlags : CT Interrupt unmask register value,this parameter can be the logical OR of the + - INTR_0_l : interrupt event flag for counter 0 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0 + - INTR_1_L : interrupt event flag for counter 1 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1 + * @return none + */ +STATIC INLINE void RSI_CT_InterruptEnable(RSI_CT_T *pCT, uint32_t unmaskFlags) +{ + // multi channel VIC enable + M4SS_CT_INTR_SEL = 0xFFFFFFFF; + + // unmasks required interrupt flags + pCT->CT_INTER_UNMASK = unmaskFlags; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptDisable(RSI_CT_T *pCT, uint32_t maskFlags) + * @brief Disable the interrupts in State Configurable Timer + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] maskFlags : CT Interrupt mask register value,this parameter can be the logical OR of the + - INTR_0_l : interrupt event flag for counter 0 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0 + - INTR_1_L : interrupt event flag for counter 1 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1 + * @return none + */ +STATIC INLINE void RSI_CT_InterruptDisable(RSI_CT_T *pCT, uint32_t maskFlags) +{ + // unmasks required interrupt flags + pCT->CT_INTR_MASK = maskFlags; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_InterruptClear(RSI_CT_T *pCT,uint32_t clr_flags) + * @brief Clear the specified interrupt flag in State Configurable Timer + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] clr_flags : CT Interrupt Ack register value,this parameter can be the logical OR of the + - INTR_0_l : interrupt event flag for counter 0 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 0 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 0 + - INTR_1_L : interrupt event flag for counter 1 + - COUNTER_0_IS_ZERO_L : counter hit zero for counter 1 + - COUNTER_0_IS_PEAK_L : counter hit peak for counter 1 + * @return none + */ +STATIC INLINE void RSI_CT_InterruptClear(RSI_CT_T *pCT, uint32_t clrFlags) +{ + // Clears required interrupt flags + pCT->CT_INTR_ACK = clrFlags; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_CT_GetInterruptStatus(const RSI_CT_T *pCT) + * @brief Clear the specified interrupt flag in State Configurable Timer + * @param[in] pCT : Pointer to the CT instance register area + * @return CT Interrupt status value + */ +STATIC INLINE uint32_t RSI_CT_GetInterruptStatus(const RSI_CT_T *pCT) +{ + return (pCT->CT_INTR_STS); +} + +/*===================================================*/ +/** + * @fn void RSI_CT_EdgeLevelEventControl(const RSI_CT_T *pCT,uint32_t value) + * @brief This API is used to control the input event generation to CT + * @param[in] pSCT : Pointer to the SCT instance register area + * @param[in] value : Mask value + * @return none + */ +STATIC INLINE void RSI_CT_EdgeLevelEventControl(const RSI_CT_T *pCT, uint32_t value) +{ + //pCT ->RE_FE_RFE_LEV0_LEV1_EVENT_ENABLE_REG = value; + (void)pCT; + (void)value; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetTimerMuxSelect( RSI_CT_MUX_REG_T *pCTMux,uint8_t timerIns ) + * @brief To Select Timer using mux. + * @param[in] pCTMux : Pointer to the CT Mux instance register area + * @param[in] timerIns : If 0 - Timer0 instance,if 1 - Timer1 instance + * @return none + */ +STATIC INLINE void RSI_CT_SetTimerMuxSelect(RSI_CT_MUX_REG_T *pCTMux, uint8_t timerIns) +{ + pCTMux->CT_MUX_SEL_0_REG = timerIns; + pCTMux->CT_MUX_SEL_1_REG = timerIns; +} + +/*===================================================*/ +/** + * @fn void RSI_CT_ResumeHaltEvent(RSI_CT_T *pCT,boolean_t counterNum) + * @brief To Resume the HALT operation of counter with I/O events + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_ResumeHaltEvent(RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + pCT->CT_HALT_COUNTER_EVENT_SEL_b.RESUME_FROM_HALT_COUNTER_1 = 0x1; + } else { + pCT->CT_HALT_COUNTER_EVENT_SEL_b.RESUME_FROM_HALT_COUNTER_0 = 0x1; + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_CT_PeripheralReset(RSI_CT_T *pCT,boolean_t counterNum) + * @brief This API is used to Reset any counter. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_PeripheralReset(RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + // Counter 1 reset + pCT->CT_GEN_CTRL_SET_REG = (1 << 17); + } else { + // Counter 0 reset + pCT->CT_GEN_CTRL_SET_REG = (1 << 1); + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_CT_StartSoftwareTrig(RSI_CT_T *pCT,boolean_t counterNum) + * @brief Starts the Counter form software register + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Coutner 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_StartSoftwareTrig(RSI_CT_T *pCT, boolean_t counterNum) +{ + // starts the required counter */ + if (counterNum) { + pCT->CT_GEN_CTRL_SET_REG = (1 << 19); + } else { + pCT->CT_GEN_CTRL_SET_REG = (1 << 3); + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_CT_OCUModeSet(RSI_CT_T *pCT, boolean_t counterNum) + * @brief OCU mode configuration setting + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Coutner 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_OCUModeSet(RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + // set the output in OCU mode for counter 1 + pCT->CT_OCU_CTRL_REG_b.OUTPUT_1_IS_OCU = 1; + } else { + // set the output in OCU mode for counter 0 + pCT->CT_OCU_CTRL_REG_b.OUTPUT_IS_OCU_0 = 1; + } +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetMatchCount(RSI_CT_T *pCT, uint32_t value,boolean_t counterMode, boolean_t counterNum) + * @brief Sets the Match load value for counter 0 and counter 1 + * @param[in] pCT : Pointer to the SCT instance register area + * @param[in] value : Match register or match buffer register value,this parameter + \n can be the logical OR of the + - COUNTER_0_MATCH : Counter 0 match value ( 0x0 to 0xFFFF) + - COUNTER_1_MATCH : Counter 1 match value ( 0x0 to 0xFFFF) + * @param[in] counterMode : counterMode 0/1 + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_SetMatchCount(RSI_CT_T *pCT, uint32_t value, boolean_t counterMode, boolean_t counterNum) +{ + if (counterMode == 0) { + if (counterNum) { + pCT->CT_MATCH_REG_b.COUNTER_1_MATCH = (uint16_t)value; + } else { + pCT->CT_MATCH_REG_b.COUNTER_0_MATCH = (uint16_t)value; + } + } else { + pCT->CT_MATCH_REG = (uint16_t)value; + } +} + +/*===================================================*/ +/** + * @fn uint16_t RSI_CT_CaptureRead(const RSI_CT_T *pCT, boolean_t counterNum) + * @brief Gets the captured counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @return Return counter value at the time of capture event occurs + */ +STATIC INLINE uint16_t RSI_CT_CaptureRead(const RSI_CT_T *pCT, boolean_t counterNum) +{ + if (counterNum) { + return (pCT->CT_CAPTURE_REG_b.COUNTER_1_CAPTURE); + } else { + return (pCT->CT_CAPTURE_REG_b.COUNTER_0_CAPTURE); + } +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_CT_GetCounter(const RSI_CT_T *pCT,boolean_t counterNum,boolean_t mode ) + * @brief Gets the captured counter value + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] counterNum : Counter 0/1 + * @param[in] mode : mode 0/1 + * @return Return the counter value + */ +STATIC INLINE uint32_t RSI_CT_GetCounter(const RSI_CT_T *pCT, boolean_t counterNum, boolean_t mode) +{ + if (mode) { + return (pCT->CT_COUNTER_REG); + } else { + if (counterNum) { + return (pCT->CT_COUNTER_REG_b.COUNTER1); + } else { + return (pCT->CT_COUNTER_REG_b.COUNTER0); + } + } +} + +/*===================================================*/ +/** + * @fn void RSI_CT_SetCounerSync( RSI_CT_T *pCT, uint8_t syncCounter,boolean_t counterNum) + * @brief Sets the captured counter value. + * @param[in] pCT : Pointer to the CT instance register area + * @param[in] syncCounter : set the counter number to be in sync + * @param[in] counterNum : Counter 0/1 + * @return none + */ +STATIC INLINE void RSI_CT_SetCounerSync(RSI_CT_T *pCT, uint8_t syncCounter, boolean_t counterNum) +{ + if (counterNum) { + pCT->CT_OCU_CTRL_REG_b.SYNC_WITH_1 = (unsigned int)(syncCounter & 0x07); + } else { + pCT->CT_OCU_CTRL_REG_b.SYNC_WITH_0 = (unsigned int)(syncCounter & 0x07); + } +} + +// CT FUNCTION PROTOTYPES +void RSI_CT_Init(void); +void ct_ocu_high_Low_toggle_select(RSI_CT_T *pCT, boolean_t lowHigh, boolean_t counterNum, uint8_t outputSel); + +rsi_error_t ct_ocu_control(RSI_CT_T *pCT, + boolean_t counterNum, + boolean_t dmaEn, + OCU_PARAMS_T *pOCUparams, + RSI_CT_CALLBACK_T *pCB); + +rsi_error_t ct_wfg_control_config(RSI_CT_T *pCT, WFG_PARAMS_T ctrlReg); + +rsi_error_t ct_wfg_comapre_value_set(RSI_CT_T *pCT, boolean_t counterNum, OCU_PARAMS_T *pOCUparams); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_CT_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h new file mode 100644 index 000000000..48d84323b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_efuse.h @@ -0,0 +1,132 @@ +/****************************************************************************** +* @file rsi_efuse.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" + +#ifndef RSI_EFUSE_H +#define RSI_EFUSE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define TA_EFUSE_BASE_ADDR 0x40010000 +#define M4_EFUSE_BASE_ADDR 0x4600C000 + +#define TA_EFUSE_IO_BASE_ADDR (TA_EFUSE_BASE_ADDR + 0x2000) +#define M4_EFUSE_IO_BASE_ADDR (M4_EFUSE_BASE_ADDR + 0x2000) + +#define EFUSE_DA_ADDR_REG_OFFSET 0x00 +#define EFUSE_DA_CTRL_SET_REG_OFFSET 0x04 +#define EFUSE_DA_CTRL_CLEAR_REG_OFFSET 0x08 +#define EFUSE_CTRL_REG_OFFSET 0x0C +#define EFUSE_READ_ADDR_REG_OFFSET 0x10 +#define EFUSE_READ_DATA_REG_OFFSET 0x14 +#define EFUSE_STATUS_REG_OFFSET 0x18 +#define EFUSE_RD_TMNG_PARAM_REG_OFFSET 0x1C +#define EFUSE_DA_ADDR_REG_DEFAULT_OFFSET 0x2C +#define EFUSE_MEM_MAP_LENGTH_OFFSET 0x24 +#define EFUSE_DA_CLR_STROBE_REG_OFFSET 0x34 +#define EFUSE_CLK_ENABLE_SET_REG2_OFFSET 0x38 +#define EFUSE_CLK_ENABLE_CLEAR_REG2_OFFSET 0x3C + +#define TA_EFUSE_DA_ADDR_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_OFFSET))) +#define TA_EFUSE_DA_CTRL_SET_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_SET_REG_OFFSET))) +#define TA_EFUSE_DA_CTRL_CLEAR_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_CLEAR_REG_OFFSET))) +#define TA_EFUSE_CTRL_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_CTRL_REG_OFFSET))) +#define TA_EFUSE_READ_ADDR_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_READ_ADDR_REG_OFFSET))) +#define TA_EFUSE_READ_DATA_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_READ_DATA_REG_OFFSET))) +#define TA_EFUSE_STATUS_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_STATUS_REG_OFFSET))) +#define TA_EFUSE_RD_TMNG_PARAM_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_RD_TMNG_PARAM_REG_OFFSET))) +#define TA_EFUSE_DA_ADDR_REG_DEFAULT (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_DEFAULT_OFFSET))) +#define TA_EFUSE_MEM_MAP_LENGTH (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_MEM_MAP_LENGTH_OFFSET))) +#define TA_EFUSE_DA_CLR_STROBE_REG (*((uint16_t volatile *)(TA_EFUSE_BASE_ADDR + EFUSE_DA_CLR_STROBE_REG_OFFSET))) + +#define M4_EFUSE_DA_ADDR_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_OFFSET))) +#define M4_EFUSE_DA_CTRL_SET_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_SET_REG_OFFSET))) +#define M4_EFUSE_DA_CTRL_CLEAR_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CTRL_CLEAR_REG_OFFSET))) +#define M4_EFUSE_CTRL_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_CTRL_REG_OFFSET))) +#define M4_EFUSE_READ_ADDR_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_READ_ADDR_REG_OFFSET))) +#define M4_EFUSE_READ_DATA_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_READ_DATA_REG_OFFSET))) +#define M4_EFUSE_STATUS_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_STATUS_REG_OFFSET))) +#define M4_EFUSE_RD_TMNG_PARAM_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_RD_TMNG_PARAM_REG_OFFSET))) +#define M4_EFUSE_DA_ADDR_REG_DEFAULT (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_ADDR_REG_DEFAULT_OFFSET))) +#define M4_EFUSE_MEM_MAP_LENGTH (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_MEM_MAP_LENGTH_OFFSET))) +#define M4_EFUSE_DA_CLR_STROBE_REG (*((uint16_t volatile *)(M4_EFUSE_BASE_ADDR + EFUSE_DA_CLR_STROBE_REG_OFFSET))) + +#define EFUSE_CLK_BIT BIT(5) +#define EFUSE_PCLK_BIT BIT(19) +#define M4SS_CLK_ENABLE_SET_3_REG (*((volatile uint32_t *)(M4SS_CLK_PWR_CTRL_BASE_ADDR + 0x10))) + +// EFUSE_DA_CTRL_SET_REG +#define SET_LOAD_ENABLE BIT(3) +#define SET_CHIP_ENABLE BIT(1) +#define SET_PROGRAM_ENABLE BIT(0) + +#define READ_FSM_DONE BIT(15) + +// Address range for 32x8 eFUSE for M4SS +#define ADDRESS_MIN 0x00 // Start address +#define ADDRESS_MAX 0x31 // End address + +// Bit Positions range +#define BIT_POS_MIN 0x00 // Min Bit position +#define BIT_POS_MAX 0x07 // Max bit position + +void efuse_enable(EFUSE_Type *pstcEfuse); + +void efuse_Disable(EFUSE_Type *pstcEfuse); + +uint8_t efuse_read_data(EFUSE_Type *pstcEfuse); + +void efuse_write_addr(EFUSE_Type *pstcEfuse, uint16_t u16Addr); + +rsi_error_t efuse_get_addr(EFUSE_Type *pstcEfuse, uint16_t *u16AddrVal); + +rsi_error_t efuse_write_bit(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t u8BitPos, uint32_t hold_time); + +rsi_error_t efuse_fsm_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + +rsi_error_t efuse_mem_map_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + +rsi_error_t efuse_mem_map_read_word(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint16_t *pu16Word, uint32_t SocClk); + +rsi_error_t efuse_direct_read_byte(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t hold_time); + +void efuse_write_address(EFUSE_Type *pstcEfuse, uint16_t u16Addr); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_EFUSE_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h new file mode 100644 index 000000000..c624c36b8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_egpio.h @@ -0,0 +1,320 @@ +/***************************************************************************/ /** +* @file rsi_egpio.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef RSI_EGPIO_H +#define RSI_EGPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +// EGPIO numbers +#define GPIO0 0 // EGPIO number 0 +#define GPIO1 1 // EGPIO number 1 +#define GPIO2 2 // EGPIO number 2 +#define GPIO3 3 // EGPIO number 3 +#define GPIO4 4 // EGPIO number 4 +#define GPIO5 5 // EGPIO number 5 +#define GPIO6 6 // EGPIO number 6 +#define GPIO7 7 // EGPIO number 7 +#define GPIO8 8 // EGPIO number 8 +#define GPIO9 9 // EGPIO number 9 +#define GPIO10 10 // EGPIO number 10 +#define GPIO11 11 // EGPIO number 11 +#define GPIO12 12 // EGPIO number 12 +#define GPIO13 13 // EGPIO number 13 +#define GPIO14 14 // EGPIO number 14 +#define GPIO15 15 // EGPIO number 14 + +// EGPIO Ports(NOTE : Each ports consists of 16 GPIO pins numbered from (0 - 15)) +#define EGPIO_PORT0 0 // EGPIO port number 0 +#define EGPIO_PORT1 1 // EGPIO port number 1 +#define EGPIO_PORT2 2 // EGPIO port number 2 + +// EGPIO PIN INTERRUPTS +// NOTE : Total 8 pin interrupts are supported , these interrupts can be mapped to any of the GPIO ports +#define EGPIO_PIN_INTERRUPT0 0 // Select interrupt channel 0 +#define EGPIO_PIN_INTERRUPT1 1 // Select interrupt channel 1 +#define EGPIO_PIN_INTERRUPT2 2 // Select interrupt channel 2 +#define EGPIO_PIN_INTERRUPT3 3 // Select interrupt channel 3 +#define EGPIO_PIN_INTERRUPT4 4 // Select interrupt channel 4 +#define EGPIO_PIN_INTERRUPT5 5 // Select interrupt channel 5 +#define EGPIO_PIN_INTERRUPT6 6 // Select interrupt channel 6 +#define EGPIO_PIN_INTERRUPT7 7 // Select interrupt channel 7 + +// EGPIO GROUP INTERUPTS +// NOTE : Total 2 group interrupts are supported +#define EGPIO_GROUP_INTERRUPT0 0 // Select EGPIO Group interrupt channel 0 +#define EGPIO_GROUP_INTERRUPT1 1 // Select EGPIO Group interrupt channel 1 + +// Pin multiplexing +// NOTE : Each GPIO supports up to 8 multiplexing functions those can be selected by passing following macros into the pin mux function +#define EGPIO_PIN_MUX_MODE0 0U // Select pin mode 0 +#define EGPIO_PIN_MUX_MODE1 1U // Select pin mode 1 +#define EGPIO_PIN_MUX_MODE2 2U // Select pin mode 2 +#define EGPIO_PIN_MUX_MODE3 3U // Select pin mode 3 +#define EGPIO_PIN_MUX_MODE4 4U // Select pin mode 4 +#define EGPIO_PIN_MUX_MODE5 5U // Select pin mode 5 +#define EGPIO_PIN_MUX_MODE6 6U // Select pin mode 6 +#define EGPIO_PIN_MUX_MODE7 7U // Select pin mode 7 +#define EGPIO_PIN_MUX_MODE8 8U // Select pin mode 8 +#define EGPIO_PIN_MUX_MODE9 9U // Select pin mode 9 +#define EGPIO_PIN_MUX_MODE10 10U // Select pin mode 10 +#define EGPIO_PIN_MUX_MODE11 11U // Select pin mode 11 +#define EGPIO_PIN_MUX_MODE12 12U // Select pin function 12 +#define EGPIO_PIN_MUX_MODE13 13U // Select pin function 13 +#define EGPIO_PIN_MUX_MODE14 14U // Select pin function 14 +#define EGPIO_PIN_MUX_MODE15 15U // Select pin function 15 + +// interrupt clear flags +#define EGPIO_PIN_INT_CLR_FALLING BIT(2) // Falling edge interrupt clear +#define EGPIO_PIN_INT_CLR_RISING BIT(1) // Raising edge interrupt clear +#define INTERRUPT_STATUS_CLR BIT(0) // interrupts are cleared +#define WAKEUP_INTERRUPT BIT(1) + +// GPIO directions +#define EGPIO_CONFIG_DIR_INPUT 1U // Configure EGPIO as input mode +#define EGPIO_CONFIG_DIR_OUTPUT 0U // Configure EGPIO as output mode +#define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR (0x41300000 + 0x004) + +// MISC host +#define MISC_HOST (*(volatile uint32_t *)(0x46008000 + 0x0C)) + +// m4 PAD configuration defines + +#define PAD_CONFIG_REG(x) (*(volatile uint32_t *)(0x46004000 + 4 * x)) // REN enable bit(this should be enable) +#define PADSELECTION \ + (*(volatile uint32_t *)(0x41300000 + 0x610)) // PAD selection (0 t0 21) A value of 1 on this gives control to M4SS + +#if defined(SLI_SI917) || defined(SLI_SI915) +#define PADSELECTION_1 \ + (*(volatile uint32_t *)(0x41300000 + 0x618)) // PAD selection (22 to 33) A value of 1 on this gives control to M4SS +#endif +#define SDIO_CNTD_TO_TASS \ + (*(volatile uint32_t *)NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR) // sdio connected to tass (0 for M4SS and 1 for TASS) + +// Ulp pad configuration defines +#define ULP_PAD_CONFIG_REG_0 (*(volatile uint32_t *)(0x2404A000 + 0x0)) +#define ULP_PAD_CONFIG_REG_1 (*(volatile uint32_t *)(0x2404A000 + 0x4)) +#define ULP_PAD_CONFIG_REG_2 (*(volatile uint32_t *)(0x2404A000 + 0x8)) + +// ulp_socgpio_n_mode +#define ULP_SOC_GPIO_MODE(x) (*(volatile uint32_t *)(0x24041400 + 4 * x)) // x= 0 to 15 + +// MISC host + +#define HOST_PADS_GPIO_MODE (*(volatile uint32_t *)(0x46008000 + 0x44)) + +// Ulp Ren enable +#define CLOCK_ENABLE (*(uint32_t *)(0x24041400 + 0x00)) + +typedef enum en_driver_state { + HiZ = 0, // 0 for HiZ (P1=0,P2=0) + Pullup = 1, // 1 for Pullup (P1=0,P2=1) + Pulldown = 2, // 2 for Pulldown (P1=1,P2=0) + Repeater = 3 // 3 for Repeater (P1=1,P2=1) +} en_driver_state_t; +typedef enum en_driver_strength_select { + two_milli_amps = 0, // 0 for two_milli_amps (E1=0,E2=0) + four_milli_amps = 1, // 1 for four_milli_amps (E1=0,E2=1) + eight_milli_amps = 2, // 2 for eight_milli_amps (E1=1,E2=0) + twelve_milli_amps = 3 // 3 for twelve_milli_amps(E1=1,E2=1) +} en_driver_strength_select_t; + +#define DDS_MASK 0xC0 // driver disabled state +#define DSS_MASK 0x3 // driver strength select +#define POS_MASK 0x4 // power on start +#define ST_MASK 0x8 // active high schmitt trigger +#define RE_MASK 0x10 // receiver enable +#define SR_MASK 0x20 // slew rate + +#define ULP_DDS_MASK_SET_1_AND_3 0xC0 // driver disabled state +#define ULP_DDS_MASK_SET_2_AND_4 0xC000 // driver disabled state +#define ULP_DSS_MASK_SET_1_AND_3 0x3 // driver strength select +#define ULP_DSS_MASK_SET_2_AND_4 0x300 // driver strength select +#define ULP_POS_MASK_SET_1_AND_3 0x4 // power on start +#define ULP_POS_MASK_SET_2_AND_4 0x400 // power on start +#define ULP_ST_MASK_SET_1_AND_3 0x8 // active high schmitt trigger +#define ULP_ST_MASK_SET_2_AND_4 0x800 // active high schmitt trigger +#define ULP_SR_MASK_SET_1_AND_3 0x20 // slew rate +#define ULP_SR_MASK_SET_2_AND_4 0x2000 // slew rate + +typedef enum en_ulp_driver_disable_state { + ulp_HiZ = 0, // 0 for HiZ (P1=0,P2=0) + ulp_Pullup = 1, // 1 for Pullup (P1=0,P2=1) + ulp_Pulldown = 2, // 2 for Pulldown (P1=1,P2=0) + ulp_Repeater = 3 // 3 for Repeater (P1=1,P2=1) +} en_ulp_driver_disable_state_t; +typedef enum en_ulp_driver_strength_select { + ulp_two_milli_amps = 0, // 0 for two_milli_amps (E1=0,E2=0) + ulp_four_milli_amps = 1, // 1 for four_milli_amps (E1=0,E2=1) + ulp_eight_milli_amps = 2, // 2 for eight_milli_amps (E1=1,E2=0) + ulp_twelve_milli_amps = 3 // 3 for twelve_milli_amps(E1=1,E2=1) +} en_ulp_driver_strength_select_t; + +void egpio_set_dir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir); + +void egpio_set_pin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); + +boolean_t egpio_get_pin(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +boolean_t egpio_get_dir(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_pin_int_sel(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); + +void egpio_set_int_fall_edge_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_fall_edge_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_rise_edge_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_rise_edge_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_low_level_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_int_mask(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_int_un_mask(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_low_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_high_level_enable(EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_set_int_high_level_disable(EGPIO_Type *pEGPIO, uint8_t intCh); + +uint8_t egpio_get_int_stat(const EGPIO_Type *pEGPIO, uint8_t intCh); + +void egpio_int_clr(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); + +void egpio_set_pin_mux(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t u8Mux); + +void egpio_ulp_soc_gpio_mode(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode); + +void egpio_set_port_mask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_set_port_un_mask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_port_masked_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t u16Val); + +void egpio_set_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +void egpio_port_load(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +void egpio_word_load(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val); + +void egpio_clr_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +void egpio_toggle_port(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + +uint16_t egpio_get_port(const EGPIO_Type *pEGPIO, uint8_t port); + +void egpio_group_int_one_enable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_group_int_one_disable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_group_int_two_enable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_group_int_mask(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_un_Mask(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_enable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_disable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_level(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_edge(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_and(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_or(EGPIO_Type *pEGPIO, uint8_t grpInt); + +uint32_t egpio_group_int_stat(const EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_wkeup_Enable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_wkeup_disable(EGPIO_Type *pEGPIO, uint8_t grpInt); + +void egpio_group_int_clr(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t u8ClrFlags); + +void egpio_group_int_two_disable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + +void egpio_set_group_int_one_pol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + +void egpio_set_group_int_two_pol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + +void egpio_host_pads_gpio_mode_enable(uint8_t u8GpioNum); + +void egpio_host_pads_gpio_mode_disable(uint8_t u8GpioNum); + +void egpio_pad_selection_enable(uint8_t padNum); + +void egpio_pad_selection_disable(uint8_t padNum); + +void egpio_pad_receiver_enable(uint8_t u8GpioNum); + +void egpio_pad_receiver_disable(uint8_t u8GpioNum); + +void egpio_pad_sdio_connected(void); + +void egpio_pad_driver_disable_state(uint8_t u8GpioNum, en_driver_state_t endstate); + +void egpio_pad_driver_strength_select(uint8_t u8GpioNum, en_driver_strength_select_t strength); + +void egpio_pad_power_on_start_enable(uint8_t u8GpioNum, uint8_t val); + +void egpio_pad_active_high_schmitt_trigger(uint8_t u8GpioNum, uint8_t val); + +void egpio_pad_slew_rate_controll(uint8_t u8GpioNum, uint8_t val); + +void egpio_ulp_pad_receiver_enable(uint8_t gpio); + +void egpio_ulp_pad_receiver_disable(uint8_t u8GpioNum); + +void egpio_ulp_pad_driver_disable_state(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate); + +void egpio_ulp_pad_driver_strength_select(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength); + +void egpio_ulp_pad_power_on_start_enable(uint8_t u8GpioNum, uint8_t val); + +void egpio_ulp_pad_active_high_schmitt_trigger(uint8_t u8GpioNum, uint8_t val); + +void egpio_ulp_pad_slew_rate_controll(uint8_t u8GpioNum, uint8_t val); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_EGPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h new file mode 100644 index 000000000..81285db90 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_gpdma.h @@ -0,0 +1,502 @@ +/***************************************************************************/ /** +* @file rsi_gpdma.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" +#include "rsi_packing.h" + +#ifndef RSI_GPDMA_H +#define RSI_GPDMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_GPDMA_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(02, 00) // API version +#define RSI_GPDMA_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version + +#define GPDMA_CHANNEL_NUM 7 + +// GPDMA Status Flags +#define GPDMA_STAT_HRESP_ERROR0 (1UL << 0) // Channel0 dma error +#define GPDMA_STAT_LINK_LIST_DONE0 (1UL << 1) // Channel0 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER0 (1UL << 2) // Channel0 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR0 (1UL << 3) // Channel0 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR1 (1UL << 4) // Channel1 dma error +#define GPDMA_STAT_LINK_LIST_DONE1 (1UL << 5) // Channel1 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER1 (1UL << 6) // Channel1 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR1 (1UL << 7) // Channel1 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR2 (1UL << 8) // Channel2 dma error +#define GPDMA_STAT_LINK_LIST_DONE2 (1UL << 9) // Channel2 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER2 (1UL << 10) // Channel2 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR2 (1UL << 11) // Channel2 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR3 (1UL << 12) // Channel3 dma error +#define GPDMA_STAT_LINK_LIST_DONE3 (1UL << 13) // Channel3 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER3 (1UL << 14) // Channel3 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR3 (1UL << 15) // Channel3 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR4 (1UL << 16) // Channel4 dma error +#define GPDMA_STAT_LINK_LIST_DONE4 (1UL << 17) // Channel4 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER4 (1UL << 18) // Channel4 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR4 (1UL << 19) // Channel4 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR5 (1UL << 20) // Channel5 dma error +#define GPDMA_STAT_LINK_LIST_DONE5 (1UL << 21) // Channel5 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER5 (1UL << 22) // Channel5 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR5 (1UL << 23) // Channel5 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR6 (1UL << 24) // Channel6 dma error +#define GPDMA_STAT_LINK_LIST_DONE6 (1UL << 25) // Channel6 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER6 (1UL << 26) // Channel6 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR6 (1UL << 27) // Channel6 Transfer size/burst size /h size mismatch/flow ctrl err status +#define GPDMA_STAT_HRESP_ERROR7 (1UL << 28) // Channel7 dma error +#define GPDMA_STAT_LINK_LIST_DONE7 (1UL << 29) // Channel7 link list fetch done status +#define GPDMA_STAT_PHRL_END_OF_XFER7 (1UL << 30) // Channel7 transfer done status +#define GPDMA_STAT_GPDMAC_ERROR7 (1UL << 31) // Channel7 Transfer size/burst size /h size mismatch/flow ctrl err status + +// GPDMA Event Flags +#define RSI_GPDMA_EVENT_HRESP_ERROR0 1 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE0 2 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER0 3 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR0 4 +#define RSI_GPDMA_EVENT_HRESP_ERROR1 5 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE1 6 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER1 7 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR1 8 +#define RSI_GPDMA_EVENT_HRESP_ERROR2 9 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE2 10 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER2 11 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR2 12 +#define RSI_GPDMA_EVENT_HRESP_ERROR3 13 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE3 14 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER3 15 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR3 16 +#define RSI_GPDMA_EVENT_HRESP_ERROR4 17 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE4 18 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER4 19 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR4 20 +#define RSI_GPDMA_EVENT_HRESP_ERROR5 21 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE5 22 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER5 23 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR5 24 +#define RSI_GPDMA_EVENT_HRESP_ERROR6 25 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE6 26 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER6 27 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR6 28 +#define RSI_GPDMA_EVENT_HRESP_ERROR7 29 +#define RSI_GPDMA_EVENT_GPDMAC_LINK_LIST_DONE7 30 +#define RSI_GPDMA_EVENT_GPDMAC_PHRL_END_OF_XFER7 31 +#define RSI_GPDMA_EVENT_GPDMAC_ERROR7 32 + +#define MEMORY_MEMORY 0x0 +#define MEMORY_PERIPHERAL 0x1 +#define PERIPHERAL_MEMORY 0x2 +#define PERIPHERAL_PERIPHERAL 0x3 + +#define DMA_FLW_CTRL 0x0 +#define SRC_PERI_CTRL 0x1 +#define DST_PERI_CTRL 0x2 +#define SRC_DST_PERI_CTRL 0x3 + +#define MASTER0_FETCH_IFSEL 0x0 +#define MASTER1_FETCH_IFSEL 0x1 + +#define MASTER0_SEND_IFSEL 0x0 +#define MASTER1_SEND_IFSEL 0x1 + +#define SRC_8_DATA_WIDTH 0x0 +#define SRC_16_DATA_WIDTH 0x1 +#define SRC_32_DATA_WIDTH 0x2 + +#define DST_8_DATA_WIDTH 0x0 +#define DST_16_DATA_WIDTH 0x1 +#define DST_32_DATA_WIDTH 0x2 + +#define LINK_LIST_EN 0x1 +#define LINK_LIST_DIS 0x0 +#define LINK_MASTER_0_FTCH 0x0 +#define LINK_MASTER_1_FTCH 0x1 + +#define SRC_ADR_CONTIG_EN 0x1 +#define SRC_ADR_CONTIG_DIS 0x0 +#define DST_ADR_CONTIG_EN 0x1 +#define DST_ADR_CONTIG_DIS 0x0 + +#define RETRY_ON_ERR_EN 0x1 +#define RETRY_ON_ERR_DIS 0x0 + +#define SRC_FIFO_EN 0x1 +#define SRC_FIFO_DIS 0x0 + +#define DST_FIFO_EN 0x1 +#define DST_FIFO_DIS 0x0 + +#define MAX_TRANS_SIZE 4096 + +#define AHBBURST_SIZE_1 0x0 +#define AHBBURST_SIZE_4 0x1 +#define AHBBURST_SIZE_8 0x2 +#define AHBBURST_SIZE_16 0x3 +#define AHBBURST_SIZE_20 0x4 +#define AHBBURST_SIZE_24 0x5 +#define AHBBURST_SIZE_28 0x6 +#define AHBBURST_SIZE_32 0x7 + +#define AHBBURST_SIZE_MAX 0x7 +#define AHBBURST_SIZE_MIN 0x0 + +#define DST_BURST_SIZE_64 0x0 +#define DST_BURST_SIZE_1 0x1 +#define DST_BURST_SIZE_2 0x2 +#define DST_BURST_SIZE_3 0x3 +#define DST_BURST_SIZE_4 0x4 +#define DST_BURST_SIZE_5 0x5 +#define DST_BURST_SIZE_6 0x6 +#define DST_BURST_SIZE_7 0x7 +#define DST_BURST_SIZE_8 0x8 +#define DST_BURST_SIZE_9 0x9 +#define DST_BURST_SIZE_10 0x10 +#define DST_BURST_SIZE_11 0x11 +#define DST_BURST_SIZE_12 0x12 +#define DST_BURST_SIZE_13 0x13 +#define DST_BURST_SIZE_14 0x14 +#define DST_BURST_SIZE_15 0x15 +#define DST_BURST_SIZE_16 0x16 +#define DST_BURST_SIZE_17 0x17 +#define DST_BURST_SIZE_18 0x18 +#define DST_BURST_SIZE_MIN 0x0 +#define DST_BURST_SIZE_MAX 63 + +#define SRC_BURST_SIZE_64 0x0 +#define SRC_BURST_SIZE_1 0x1 +#define SRC_BURST_SIZE_2 0x2 +#define SRC_BURST_SIZE_3 0x3 +#define SRC_BURST_SIZE_4 0x4 +#define SRC_BURST_SIZE_5 0x5 +#define SRC_BURST_SIZE_6 0x6 +#define SRC_BURST_SIZE_7 0x7 +#define SRC_BURST_SIZE_8 0x8 +#define SRC_BURST_SIZE_9 0x9 +#define SRC_BURST_SIZE_10 0x10 +#define SRC_BURST_SIZE_11 0x11 +#define SRC_BURST_SIZE_12 0x12 +#define SRC_BURST_SIZE_13 0x13 +#define SRC_BURST_SIZE_14 0x14 +#define SRC_BURST_SIZE_15 0x15 +#define SRC_BURST_SIZE_16 0x16 +#define SRC_BURST_SIZE_17 0x17 +#define SRC_BURST_SIZE_18 0x18 +#define SRC_BURST_SIZE_MIN 0x0 +#define SRC_BURST_SIZE_MAX 63 + +#define DST_CHNL_ID_MIN 0x0 +#define DST_CHNL_ID_MAX 47 +#define SRC_CHNL_ID_MIN 0x0 +#define SRC_CHNL_ID_MAX 47 +#define DMA_PROT_EN 0x1 +#define DMA_PROT_DIS 0x0 +#define MEM_FILL_EN 0x1 +#define MEM_FILL_DIS 0x0 +#define MEM_FILL_ONE 0x1 +#define MEM_FILL_ZERO 0x0 +#define SRC_ALIGN_DIS 0x0 +#define SRC_ALIGN_EN 0x1 + +#define LINK_INTR_DIS 0x0 +#define LINK_INTR_ON 0x1 +#define DESC_FETCH_DONE_INTR 0 +#define TRANS_DONE_INTR 1 + +#define UNMASK_DESC_FETCH_INTR 0x0000FF +#define GPDMA_CHNL0 0 +#define GPDMA_CHNL1 1 +#define GPDMA_CHNL7 7 + +#define GPDMA_CHNL_0 0 +#define GPDMA_CHNL_1 1 +#define GPDMA_CHNL_2 2 +#define GPDMA_CHNL_3 3 + +#define XFER_SIZE_4K 4096 + +#define AHB_BURST_1 0x0 +#define AHB_BURST_4 0x1 +#define AHB_BURST_8 0x2 +#define AHB_BURST_16 0x3 +#define AHB_BURST_20 0x4 +#define AHB_BURST_24 0x5 +#define AHB_BURST_28 0x6 +#define AHB_BURST_32 0x7 + +#define SRC_BURST_64 0x00 +#define SRC_BURST_1 0x01 +#define SRC_BURST_16 0x10 +#define SRC_BURST_63 0x3F + +#define DST_BURST_64 0x00 +#define DST_BURST_1 0x01 +#define DST_BURST_16 0x10 +#define DST_BURST_63 0x3F + +#define FILL_ZEROS 0x0 +#define FILL_ONES 0x1 + +#define PRIO_LEVEL_4 0x3 +#define PRIO_LEVEL_3 0x2 +#define PRIO_LEVEL_2 0x1 +#define PRIO_LEVEL_1 0x0 + +#define MAX_CHANNELS 0x8 + +#define DESC_COUNT 4 +#define DESC_INDEX0 0 +#define DESC_INDEX1 1 +#define DESC_INDEX2 2 +#define DESC_INDEX3 3 + +#define FIFO_SIZE_MAX 512 + +#define NO_DST_CHNL_ID 0x0 +#define NO_SRC_CHNL_ID 0x0 + +#define HRESP_ERR 0 +#define GPDMAC_ERR 1 + +#define M4SS_GPDMA_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x04))) +#define CLOCK_BASE 0x46000000 +#define CLK_ENABLE_SET_2_REG (*((uint32_t volatile *)(CLOCK_BASE + 0x08))) +#define CLK_ENABLE_SET_1_REG (*((uint32_t volatile *)(CLOCK_BASE + 0x00))) + +typedef GPDMA_G_Type RSI_GPDMAG_T; +typedef GPDMA_C_Type RSI_GPDMAC_T; + +// GPDMA Error flags +#define HRESP_ERR0 (1UL << 0) +#define HRESP_ERR1 (1UL << 4) +#define HRESP_ERR2 (1UL << 8) +#define HRESP_ERR3 (1UL << 12) +#define HRESP_ERR4 (1UL << 16) +#define HRESP_ERR5 (1UL << 20) +#define HRESP_ERR6 (1UL << 24) +#define HRESP_ERR7 (1UL << 28) +#define GPDMAC_ERR0 (1UL << 3) +#define GPDMAC_ERR1 (1UL << 7) +#define GPDMAC_ERR2 (1UL << 11) +#define GPDMAC_ERR3 (1UL << 15) +#define GPDMAC_ERR4 (1UL << 19) +#define GPDMAC_ERR5 (1UL << 23) +#define GPDMAC_ERR6 (1UL << 27) +#define GPDMAC_ERR7 (1UL << 31) + +// GPDMA transfer status flags +#define LINK_LIST_DONE0 (1UL << 1) +#define PHRL_END_OF_TFR0 (1UL << 2) +#define LINK_LIST_DONE1 (1UL << 5) +#define PHRL_END_OF_TFR1 (1UL << 6) +#define LINK_LIST_DONE2 (1UL << 9) +#define PHRL_END_OF_TFR2 (1UL << 10) +#define LINK_LIST_DONE3 (1UL << 13) +#define PHRL_END_OF_TFR3 (1UL << 14) +#define LINK_LIST_DONE04 (1UL << 17) +#define PHRL_END_OF_TFR4 (1UL << 18) +#define LINK_LIST_DONE5 (1UL << 21) +#define PHRL_END_OF_TFR5 (1UL << 22) +#define LINK_LIST_DONE6 (1UL << 25) +#define PHRL_END_OF_TFR6 (1UL << 26) +#define LINK_LIST_DONE7 (1UL << 29) +#define PHRL_END_OF_TFR7 (1UL << 30) + +// brief GPDMA Driver Capabilities. +typedef struct { + unsigned int noOfChannels : 4; // Total supporting channels + unsigned int noOfMasterInterfaces : 2; // No of master interfaces supported + unsigned int noOfPeriSupport : 7; // total supporting peripherals + unsigned int noOfPriorityLevels : 3; // No of priority levels + +} RSI_GPDMA_CAPABILITIES_T; + +// brief GPDMA Descriptor parameters. + +// brief chnl_ctrl_info +typedef PRE_PACK struct POST_PACK { + unsigned int transSize : 12; // Transfer lenght in bytes + unsigned int transType : 2; // Type of DMA transfer + unsigned int dmaFlwCtrl : 2; // Flow control type + unsigned int mastrIfFetchSel : 1; // Master controller select to fetch data + unsigned int mastrIfSendSel : 1; // Master controller select to send data + unsigned int destDataWidth : 2; // Destination data width + unsigned int srcDataWidth : 2; // Source data width + unsigned int srcAlign : 1; // Source Alignment + unsigned int linkListOn : 1; // Linked transfer on + unsigned int linkListMstrSel : 1; // Master controller select for link transfers + unsigned int srcAddContiguous : 1; // Source address contiguous + unsigned int dstAddContiguous : 1; // Destination address contiguous + unsigned int retryOnErr : 1; // Retry on error + unsigned int linkInterrupt : 1; // Link interrupt enable + unsigned int srcFifoMode : 1; // Source FIFO mode + unsigned int dstFifoMode : 1; // Destination FIFO mode + unsigned int reserved : 1; +} RSI_GPDMA_CHA_CONTROL_T; + +//brief Misc_chnl_ctrl_info +typedef PRE_PACK struct POST_PACK { + unsigned int ahbBurstSize : 3; // AHB Burst size + unsigned int destDataBurst : 6; // Destination data Burst size + unsigned int srcDataBurst : 6; // source data Burst size + unsigned int destChannelId : 6; // Dest channel ID + unsigned int srcChannelId : 6; // Source channel ID + unsigned int dmaProt : 3; + unsigned int memoryFillEn : 1; // Memory fill enable + unsigned int memoryOneFill : 1; // Memory fill with 1 or 0 +} RSI_GPDMA_MISC_CHA_CONTROL_T; + +//brief GPDMA controller handle type +typedef void *RSI_GPDMA_HANDLE_T; + +typedef PRE_PACK struct POST_PACK { + uint32_t *pNextLink; // Pointer to next descriptor link in a chain, NULL to end + void *src; // source address + void *dest; // destination address + RSI_GPDMA_CHA_CONTROL_T chnlCtrlConfig; // Channel control register paramter + RSI_GPDMA_MISC_CHA_CONTROL_T miscChnlCtrlConfig; // Channel control register paramter +} RSI_GPDMA_DESC_T; + +typedef void (*gpdmaTransferCompleteCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); +typedef void (*gpdmaTransferDescFetchCompleteCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, + RSI_GPDMA_DESC_T *pTranDesc, + uint32_t dmaCh); +typedef void (*gpdmaTransferHrespErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); +typedef void (*gpdmaTransferRpdmacErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); +typedef void (*gpdmaTransferErrorCB)(RSI_GPDMA_HANDLE_T gpdmaHandle, RSI_GPDMA_DESC_T *pTranDesc, uint32_t dmaCh); + +// @brief GPDMA controller callback IDs +typedef enum { + RSI_GPDMA_XFERCOMPLETE_CB = 0, // Callback ID for GPDMA transfer descriptor chain complete + RSI_GPDMA_XFERDESCFETCHCOMPLETE_CB, // Callback ID for GPDMA transfer descriptor complete + RSI_GPDMA_XFERHRESPERROR_CB, // Callback ID for GPDMA transfer error occurance + RSI_GPDMA_XFERGPDMACERROR_CB +} RSI_GPDMA_CALLBACK_T; + +// Private data structure used for the GPDMA controller driver, holds the driver and peripheral context +typedef struct { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + RSI_GPDMAG_T *baseG; // GPDMA global registers base + RSI_GPDMAC_T *baseC; // GPDMA channel specific registers base + RSI_GPDMA_DESC_T *sramBase; // SRAM descriptor table (all channels) + gpdmaTransferCompleteCB gpdmaCompCB; // Transfer descriptor chain completion callback + gpdmaTransferDescFetchCompleteCB gpdmaDescFetchCompCB; // Transfer descriptor fetch completion callback + gpdmaTransferHrespErrorCB gpdmaHrespErrorCB; // Transfer error callback + gpdmaTransferRpdmacErrorCB gpdmaRpdmacErrorCB; // Transfer error callback + uint32_t dmaCh; // GPDMA channel +} GPDMA_DATACONTEXT_T; + +// GPDMA Init structure +typedef PRE_PACK struct POST_PACK { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + uint32_t baseG; // Pointer to GPDMA global register instance + uint32_t baseC; // Pointer to GPDMA channel specific register instance + uint32_t sramBase; // Pointer to memory used for GPDMA descriptor storage, must be 512 byte aligned +} RSI_GPDMA_INIT_T; + +// brief GPDMA transfer channel setup structure (use this structure as const if possible) +typedef PRE_PACK struct POST_PACK { + uint32_t channelPrio; // Channel priority level + uint32_t descFetchDoneIntr; // Desc fetch done interrupt flag + uint32_t xferDoneIntr; // Transfer done interrupt flag + uint32_t hrespErr; // dma error flag + uint32_t gpdmacErr; // Transfer size/burst size /h size mismatch/flow ctrl err + uint32_t dmaCh; // Channel number +} RSI_GPDMA_CHA_CFG_T; + +/*===================================================*/ +/** + * @fn void RSI_GPDMA_FIFOConfig( RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, + uint32_t startAdr, uint32_t size ) + * @brief Set fifo configuration for data transmission. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : DMA channel number(0-7) + * @param[in] startAdr : starting address for data transfer. + * @param[in] size : size of data transfer. + * @return none. + */ +STATIC INLINE void RSI_GPDMA_FIFOConfig(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, uint32_t startAdr, uint32_t size) +{ + GPDMA_DATACONTEXT_T *pDrv = (GPDMA_DATACONTEXT_T *)pHandle; + pDrv->baseC->CHANNEL_CONFIG[dmaCh].FIFO_CONFIG_REGS_b.FIFO_STRT_ADDR = (unsigned int)(startAdr & 0x3F); + pDrv->baseC->CHANNEL_CONFIG[dmaCh].FIFO_CONFIG_REGS_b.FIFO_SIZE = (unsigned int)(size & 0x3F); +} + +// FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_GPDMA_GetVersion(void); + +RSI_GPDMA_CAPABILITIES_T RSI_GPDMA_GetCapabilities(void); + +uint32_t gpdma_get_mem_size(void); + +RSI_GPDMA_HANDLE_T gpdma_init(void *mem, const RSI_GPDMA_INIT_T *pInit); + +void gpdma_register_callback(RSI_GPDMA_HANDLE_T pHandle, uint32_t cbIndex, gpdmaTransferCompleteCB pCB); + +rsi_error_t gpdma_abort_channel(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +rsi_error_t gpdma_setup_channel(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_build_descriptors(RSI_GPDMA_HANDLE_T pHandle, + RSI_GPDMA_DESC_T *pXferCfg, + RSI_GPDMA_DESC_T *pDesc, + RSI_GPDMA_DESC_T *pDescPrev); + +rsi_error_t gpdma_setup_channelTransfer(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, RSI_GPDMA_DESC_T *pDesc); + +void gpdma_interrupt_handler(RSI_GPDMA_HANDLE_T pHandle); + +void gpdma_deInit(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_dma_channel_trigger(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +uint32_t gpdma_channel_is_enabled(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +rsi_error_t gpdma_interrupt_disable(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_interrupt_enable(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_error_status_clear(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +uint32_t gpdma_get_error_status(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +rsi_error_t gpdma_interrupt_clear(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +uint32_t gpdma_interrupt_status(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +uint8_t RSI_GPDMA_GetChannelActivity(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + +#ifdef __cplusplus +} +#endif +#endif //RSI_GPDMA_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h new file mode 100644 index 000000000..97fc2264b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_pwm.h @@ -0,0 +1,977 @@ +/***************************************************************************/ /** +* @file rsi_pwm.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Includes Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_error.h" + +#ifndef RSI_PWM_H +#define RSI_PWM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_MCPWM_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1 +#define RSI_MCPWM_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1 + +// MCPWM Interrupt Flags +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH0 \ + (1UL << 0) // Time base match for 0th channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH0 (1UL << 1) // Time base match for 0th channel which considering postscaler +#define RSI_MCPWM_EVENT_FAULT_A (1UL << 2) // Fault A pin match +#define RSI_MCPWM_EVENT_FAULT_B (1UL << 3) // Fault B pin match +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH1 \ + (1UL << 4) // Time base match for 1st channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH1 \ + (1UL << 5) // Time base match for 1st channel which considering postscaler +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH2 \ + (1UL << 6) // Time base match for 2nd channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH2 (1UL << 7) // Time base match for 2nd channel which considering postscaler +#define RSI_MCPWM_EVENT_RISE_TIME_PERIOD_MATCH_CH3 \ + (1UL << 8) // Time base match for 3rd channel without considering postscaler +#define RSI_MCPWM_EVENT_TIME_PERIOD_MATCH_CH3 \ + (1UL << 9) // Time base match for 3rd channel without considering postscaler + +#define FLTA_MODE (1UL << 0) +#define FLTB_MODE (1UL << 1) +#define FLTA_ENABLE (1UL << 4) +#define FLTB_ENABLE (1UL << 8) + +// MCPWM Events +#define RISE_TIME_PERIOD_MATCH_CH0 0x0 // Event for 0th channel without considering postscaler +#define TIME_PERIOD_MATCH_CH0 0x1 // Event for 0th channel which considering postscaler +#define FAULT_A 0x2 // Fault A pin Event +#define FAULT_B 0x3 // Fault B pin Event +#define RISE_TIME_PERIOD_MATCH_CH1 0x4 // Event for 1st channel without considering postscaler +#define TIME_PERIOD_MATCH_CH1 0x5 // Event for 1st channel which considering postscaler +#define RISE_TIME_PERIOD_MATCH_CH2 0x6 // Event for 2nd channel without considering postscaler +#define TIME_PERIOD_MATCH_CH2 0x7 // Event for 2nd channel which considering postscaler +#define RISE_TIME_PERIOD_MATCH_CH3 0x8 // Event for 3rd channel without considering postscaler +#define TIME_PERIOD_MATCH_CH3 0x9 // Event for 3rd channel which considering postscaler + +#define COUNTER_A 0 +#define COUNTER_B 1 + +// PWM Example defines +#define PWM_CHNL_0 0 +#define PWM_CHNL_1 1 +#define PWM_CHNL_2 2 +#define PWM_CHNL_3 3 + +#define TMR_FREE_RUN_MODE 0x0 +#define TMR_SINGLE_EVENT_MODE 0x1 +#define TMR_DOWN_COUNT_MODE 0x2 +#define TMR_UP_DOWN_MODE 0x3 +#define TMR_UP_DOWN_DOUBLE_UPDATE 0x4 + +#define ONE_TIMER_FOR_EACH_CHNL 0 +#define ONE_TIMER_FOR_ALL_CHNL 1 + +#define TIME_PERIOD_PRESCALE_1 0x0 +#define TIME_PERIOD_PRESCALE_2 0x1 +#define TIME_PERIOD_PRESCALE_4 0x2 +#define TIME_PERIOD_PRESCALE_8 0x3 +#define TIME_PERIOD_PRESCALE_16 0x4 +#define TIME_PERIOD_PRESCALE_32 0x5 +#define TIME_PERIOD_PRESCALE_64 0x6 + +#define TIME_PERIOD_POSTSCALE_1_1 0x0 +#define TIME_PERIOD_POSTSCALE_1_2 0x1 +#define TIME_PERIOD_POSTSCALE_1_3 0x2 +#define TIME_PERIOD_POSTSCALE_1_4 0x3 +#define TIME_PERIOD_POSTSCALE_1_5 0x4 +#define TIME_PERIOD_POSTSCALE_1_6 0x5 +#define TIME_PERIOD_POSTSCALE_1_7 0x6 +#define TIME_PERIOD_POSTSCALE_1_8 0x7 +#define TIME_PERIOD_POSTSCALE_1_9 0x8 +#define TIME_PERIOD_POSTSCALE_1_10 0x9 +#define TIME_PERIOD_POSTSCALE_1_11 0xA +#define TIME_PERIOD_POSTSCALE_1_12 0xB +#define TIME_PERIOD_POSTSCALE_1_13 0xC +#define TIME_PERIOD_POSTSCALE_1_14 0xD +#define TIME_PERIOD_POSTSCALE_1_15 0xE +#define TIME_PERIOD_POSTSCALE_1_16 0xF + +#define TMR0_PERIOD 0x1500 +#define TMR1_PERIOD 0x1500 +#define TMR2_PERIOD 0x1500 +#define TMR3_PERIOD 0x1500 + +#define COUNTER_INIT_VAL 0 + +#define DUTYCYCLE_UPDATE_DIS0 (1 << 4) +#define DUTYCYCLE_UPDATE_DIS1 (1 << 5) +#define DUTYCYCLE_UPDATE_DIS2 (1 << 6) +#define DUTYCYCLE_UPDATE_DIS3 (1 << 7) + +#define IMD_UPDATE_EN0 (1 << 0) +#define IMD_UPDATE_EN1 (1 << 1) +#define IMD_UPDATE_EN2 (1 << 2) +#define IMD_UPDATE_EN3 (1 << 3) + +#define DUTYCYCLE_UPDATE_EN0 (1 << 4) +#define DUTYCYCLE_UPDATE_EN1 (1 << 5) +#define DUTYCYCLE_UPDATE_EN2 (1 << 6) +#define DUTYCYCLE_UPDATE_EN3 (1 << 7) + +#define IMD_UPDATE_DIS0 (1 << 0) +#define IMD_UPDATE_DIS1 (1 << 1) +#define IMD_UPDATE_DIS2 (1 << 2) +#define IMD_UPDATE_DIS3 (1 << 3) + +#define TMR0_DUTYCYCLE 0xA80 +#define TMR1_DUTYCYCLE 0xA80 +#define TMR2_DUTYCYCLE 0xA80 +#define TMR3_DUTYCYCLE 0xA80 + +#define COMPLEMENT 1 +#define INDEPENDENT 0 + +#define OUT_POL_H_HIGH (1 << 2) +#define OUT_POL_H_LOW (0 << 2) + +#define OUT_POL_L_HIGH (1 << 3) +#define OUT_POL_L_LOW (0 << 3) + +#define DT_SELECT_INACTIVE_CH0 (1 << 4) +#define DT_SELECT_INACTIVE_CH1 (1 << 5) +#define DT_SELECT_INACTIVE_CH2 (1 << 6) +#define DT_SELECT_INACTIVE_CH3 (1 << 7) + +#define DT_SELECT_ACTIVE_CH0 (1 << 0) +#define DT_SELECT_ACTIVE_CH1 (1 << 1) +#define DT_SELECT_ACTIVE_CH2 (1 << 2) +#define DT_SELECT_ACTIVE_CH3 (1 << 3) + +#define COUNTUP 0 +#define COUNTDOWN 1 +#define PWM_OUTPUT_L0 0 +#define PWM_OUTPUT_L1 1 +#define PWM_OUTPUT_L2 2 +#define PWM_OUTPUT_L3 3 +#define PWM_OUTPUT_H0 4 +#define PWM_OUTPUT_H1 5 +#define PWM_OUTPUT_H2 6 +#define PWM_OUTPUT_H3 7 + +#define PWM_OUTPUT_MIN 0 +#define PWM_OUTPUT_MAX 7 + +#define OVERRIDE_SYNC_EN 1 +#define OVERRIDE_SYNC_DIS 0 + +#define OV_VALUE_0 1 +#define OV_VALUE_1 0 + +#define DT_EN_CH0 (1 << 8) +#define DT_EN_CH1 (1 << 9) +#define DT_EN_CH2 (1 << 10) +#define DT_EN_CH3 (1 << 11) + +#define DT_DIS_CH0 (1 << 8) +#define DT_DIS_CH1 (1 << 9) +#define DT_DIS_CH2 (1 << 10) +#define DT_DIS_CH3 (1 << 11) + +typedef MCPWM_Type RSI_MCPWM_T; + +// brief MCPWM Status +typedef struct { + uint32_t counterDir; // Current Counter direction + uint32_t counterVal; // Counter current value +} RSI_MCPWM_STATUS_T; + +// brief MCPWM Driver Capabilities. +typedef struct { + uint32_t pwmOutputs : 4; // Number of PWM outputs + uint32_t faultPins : 2; // Number of fault input pins +} RSI_MCPWM_CAPABILITIES_T; + +// brief MCPWM Callback structure +typedef struct { + void (*cbFunc)(uint16_t flag); // Call back function pointer + +} RSI_MCPWM_CALLBACK_T; + +// brief MCPWM Special Event trigger configuration parameters. +typedef struct { + uint16_t svtPostscalar; // SVT PostScalar value + uint16_t svtCompareVal; // SVT compare value to generate trigger for A/D + uint8_t svtChannel; // channel to generate SVT +} RSI_MCPWM_SVT_CONFIG_T; + +// brief MCPWM DeadTime Configuration parameters. +typedef struct { + uint8_t counterSelect; // Selects coutner A/B for deadtime insertion + int8_t preScaleA; // PreScale for counter A + int8_t preScaleB; // PreScale for counter B + int8_t deadTimeA; // Deadtime for counter A + int8_t deadTimeB; // Deadtime for counter B +} RSI_MCPWM_DT_CONFIG_T; + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_ReadCounter(RSI_MCPWM_T *pMCPWM,uint16_t *counterVal, + uint8_t chnlNum) + * @brief This API is used to read the counter current value + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] counterVal : counter value + * @param[in] chnlNum : Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel is invalid. + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_ReadCounter(RSI_MCPWM_T *pMCPWM, uint16_t *counterVal, uint8_t chnlNum) +{ + // Gets Time period counter current value + switch (chnlNum) { + case PWM_CHNL_0: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH0); + break; + case PWM_CHNL_1: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH1); + break; + case PWM_CHNL_2: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH2); + break; + case PWM_CHNL_3: + *counterVal = (uint16_t)(pMCPWM->PWM_TIME_PRD_CNTR_VALUE_CH3); + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_GetCounterDir(RSI_MCPWM_T *pMCPWM,uint8_t *counterDir, + uint8_t chnlNum) + * @brief This API is used to get time period counter direction status of required MCPWM channel + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] chnlNum : Channel number(0 to 3) + * @param[out] counterDir : Counter direction as up/down counter. + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid. + \n \ref RSI_OK(0) : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_GetCounterDir(RSI_MCPWM_T *pMCPWM, uint8_t *counterDir, uint8_t chnlNum) +{ + // Gets the counter direction + switch (chnlNum) { + case PWM_CHNL_0: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH0); + break; + case PWM_CHNL_1: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH1); + break; + case PWM_CHNL_2: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH2); + break; + case PWM_CHNL_3: + *counterDir = (uint8_t)(pMCPWM->PWM_TIME_PRD_STS_REG_CH3); + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeEnable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief Enables dead time insertion at rise edge or fall edge of any four channels + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_EN_CH0 + - DT_EN_CH1 + - DT_EN_CH2 + - DT_EN_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeEnable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeDisable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief This API is used to disable the dead time mode for the specified MCPWM generator. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_DIS_CH0 + - DT_DIS_CH1 + - DT_DIS_CH2 + - DT_DIS_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeDisable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_SET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_Dead_Time_Enable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief Enables dead time insertion at rise edge or fall edge of any four channels + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_EN_CH0 + - DT_EN_CH1 + - DT_EN_CH2 + - DT_EN_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_Dead_Time_Enable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_SET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_Dead_Time_Disable(RSI_MCPWM_T *pMCPWM ,uint32_t flag) + * @brief This API is used to disable the dead time mode for the specified MCPWM generator. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : This can be ORing of below values + - DT_DIS_CH0 + - DT_DIS_CH1 + - DT_DIS_CH2 + - DT_DIS_CH3 + * @return none + */ +STATIC INLINE void RSI_MCPWM_Dead_Time_Disable(RSI_MCPWM_T *pMCPWM, uint32_t flag) +{ + pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_InterruptClear(RSI_MCPWM_T *pMCPWM, uint32_t clrFlag) + * @brief This API is used to clear the interrupts of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] clrFlag : This can be logical OR of the below parameters + - RISE_PWM_TIME_PERIOD_MATCH_CH0_ACK : Time base interrupt for 0th channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 0th channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH0_ACK : Time base interrupt for 0th channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 0th channel will + be cleared if bit zero then no effect. + - FLT_A_INTR_ACK : Fault A pin interrupt + \n if bit is set pwm faultA interrupt will be cleared,if zero then ,no effect. + - FLT_A_INTR_ACK : Fault B pin interrupt + \n if bit is set pwm faultB interrupt will be cleared,if zero then ,no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH1_ACK : Time base interrupt for + 1th channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 1th channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH1_ACK : Time base interrupt for 1th channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 1th channel will + be cleared if bit zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH2_ACK : Time base interrupt for + 2nd channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 1th channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH2_ACK : Time base interrupt for 2nd channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 2nd channel will + be cleared if bit zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH3_ACK : Time base interrupt for + 3rd channel without considering postscaler + \n if bit is one then pwm time period match interrupt for 3rd channel will + be cleared if bit zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH3_ACK : Time base interrupt for 3rd channel which + considering postscaler + \n if bit is one then pwm time period match interrupt for 3rd channel will + be cleared if bit zero then no effect. + + * @return none + */ +STATIC INLINE void RSI_MCPWM_InterruptClear(RSI_MCPWM_T *pMCPWM, uint32_t clrFlag) +{ + pMCPWM->PWM_INTR_ACK = clrFlag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_InterruptEnable(RSI_MCPWM_T *pMCPWM, uint16_t flag) + * @brief This API is used to enable the interrupts of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : flag value can be logical OR of the below parameters + - RISE_PWM_TIME_PERIOD_MATCH_CH0 : Time base interrupt for 0th channel without + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared,if zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH0 : Time base interrupt for 0th channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared if zero then no effect. + - FLT_A_INTR : Fault A pin interrupt + \n if bit is one then pwm faultA interrupt will be cleared if zero + then no effect. + - FLT_B_INTR : Fault B pin interrupt + \n if bit is one pwm faultB interrupt will be cleared if zero + then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH1 : Time base interrupt for 1st channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 1st channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH1 : Time base interrupt for 1st channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 1st channel + will be cleared if zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH2 : Time base interrupt for 2nd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH2 : Time base interrupt for 2nd channel which + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - RISE_PWM_TIME_PERIOD_MATCH_CH3 : Time base interrupt for 3rd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH3 : Time base interrupt for 3rd channel which considering + postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + * @return none + */ +STATIC INLINE void RSI_MCPWM_InterruptEnable(RSI_MCPWM_T *pMCPWM, uint16_t flag) +{ + pMCPWM->PWM_INTR_UNMASK = flag; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_InterruptDisable(RSI_MCPWM_T *pMCPWM, uint16_t flag) + * @brief This API is used to disable the interrupts of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : flag value can be logical OR of the below parameters + - RISE_PWM_TIME_PERIOD_MATCH_CH0 : Time base interrupt for 0th channel without + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared,if zero then no effect. + - PWM_TIME_PRD_MATCH_INTR_CH0 : Time base interrupt for 0th channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared if zero then no effect. + - FLT_A_INTR : Fault A pin interrupt + \n if bit is one then pwm faultA interrupt will be cleared if zero + then no effect. + - FLT_B_INTR : Fault B pin interrupt + \n if bit is one pwm faultB interrupt will be cleared if zero + then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH1 : Time base interrupt for 1st channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 1st channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH1 : Time base interrupt for 1st channel which + considering postscaler + \n if bit is 1 then pwm time period match interrupt for 0th channel + will be cleared if zero then no effect. + - RISE_PWM_TIME_PERIOD_MATCH_CH2 : Time base interrupt for 2nd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH2 : Time base interrupt for 2nd channel which + considering postscaler + \n if bit is one pwm time period match interrupt for 2nd channel + will be cleared if bit is zero no effect + - RISE_PWM_TIME_PERIOD_MATCH_CH3 : Time base interrupt for 3rd channel without + considering postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + - PWM_TIME_PRD_MATCH_INTR_CH3 : Time base interrupt for 3rd channel which considering + postscaler + \n if bit is one pwm time period match interrupt for 3rd channel + will be cleared if bit is zero no effect + * @return none + */ +STATIC INLINE void RSI_MCPWM_InterruptDisable(RSI_MCPWM_T *pMCPWM, uint16_t flag) +{ + pMCPWM->PWM_INTR_MASK = flag; +} + +/*===================================================*/ +/** + * @fn uint16_t RSI_PWM_GetInterruptStatus(RSI_MCPWM_T *pMCPWM, uint16_t flag) + * @brief This API is used to get the interrupt status of interrupt flags of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] flag : Flag value + * @return Interrupt status of required interrupt flag + */ +STATIC INLINE uint16_t RSI_PWM_GetInterruptStatus(RSI_MCPWM_T *pMCPWM, uint16_t flag) +{ + return (uint16_t)(pMCPWM->PWM_INTR_STS & flag); +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_DutyCycleControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value,uint8_t chnlNum) + * @brief This API is used to set duty cycle control parameters for the required MCPWM channel + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately + - DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable + * @param[in] chnlNum : Channel number(0 to 3) + * @return ERROR_PWM_INVALID_CHNLNUM : If channel is invalid. + \n RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_DutyCycleControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value, uint8_t chnlNum) +{ + if (chnlNum <= PWM_CHNL_3) { + pMCPWM->PWM_DUTYCYCLE_CTRL_SET_REG = value; + } else { + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_DutyCycleControlReset(RSI_MCPWM_T *pMCPWM,uint32_t value, uint8_t chnlNum) + * @brief This API is used to reset the duty cycle control parameters of required MCPWM channel + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - IMDT_DUTYCYCLE_UPDATE_EN : Enable to update the duty cycle immediately + - DUTYCYCLE_UPDATE_DISABLE : Duty cycle register updation disable + * @param[in] chnlNum Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_DutyCycleControlReset(RSI_MCPWM_T *pMCPWM, uint32_t value, uint8_t chnlNum) +{ + if (chnlNum <= PWM_CHNL_3) { + pMCPWM->PWM_DUTYCYCLE_CTRL_RESET_REG = value; + } else { + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_OutputOverrideEnable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput) + * @brief This API is used to enable the output override operation of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : Pwm output over ride,possible values are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + * \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_OutputOverrideEnable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_ENABLE_SET_REG = (1 << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_OutputOverrideDisable(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput) + * @brief This API is used to disable the output override operation of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : Pwm output over ride enable,possible values are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + * \n \ref RSI_OK : If process is done successfully. +*/ +STATIC INLINE rsi_error_t RSI_MCPWM_OutputOverrideDisable(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_ENABLE_RESET_REG = (1 << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_OverrideControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value) + * @brief This API is used to set the override control parameter,output is synced with pwm time period depending on operating mode + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : if value is 1 then Output override is synced with pwm time period depending + \n on operating mode, if 0 then no effect. + * @return none + */ +STATIC INLINE void RSI_MCPWM_OverrideControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_OP_OVERRIDE_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_OverrideControlReSet(RSI_MCPWM_T *pMCPWM,uint32_t value) + * @brief This API is used to reset the output override sync control parameter. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : if value is 1 then Output override is synced with pwm time period depending + \n on operating mode, if 0 then no effect. + * @return none + */ +STATIC INLINE void RSI_MCPWM_OverrideControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_OP_OVERRIDE_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_OverrideValueSet(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput,uint8_t value) + * @brief This API is used to set override value for the required output of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : PWM outputs are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @param[in] value : override value can be 0 or 1 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + * \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_OverrideValueSet(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_VALUE_SET_REG = (value << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_OverrideValueReSet(RSI_MCPWM_T *pMCPWM,uint8_t pwmOutput,uint8_t value) + * @brief This API is used to reset override value for the required output of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] pwmOutput : PWM outputs are as below + - 0 : L0 + - 1 : L1 + - 2 : L2 + - 3 : L3 + - 4 : H0 + - 5 : H1 + - 6 : H2 + - 7 : H3 + * @param[in] value : override value can be 0 or 1 + * @return \ref ERROR_PWM_INVALID_ARG : If pwmOutput value is invalid + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_OverrideValueReSet(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value) +{ + if (pwmOutput <= PWM_OUTPUT_MAX) { + pMCPWM->PWM_OP_OVERRIDE_VALUE_RESET_REG = (value << pwmOutput); + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_FaultControlSet(RSI_MCPWM_T *pMCPWM,uint32_t value) + * @brief This API is used to set output fault override control parameters for required PWM output + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - FLT_A_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - FLT_B_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - FLT_A_ENABLE : enable fault A + - FLT_B_ENABLE : enable fault B + - COMPLEMENT_MODE : PWM I/O pair mode + \n if bit is 1 then PWM I/O pin pair is in the complementary output mode + \n if bit is 0 then PWM I/O pin pair is in the independent output mode + * @return none + */ +STATIC INLINE void RSI_MCPWM_FaultControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_FLT_OVERRIDE_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_FaultControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) + * @brief This API is used to reset output fault override control parameters for required PWM output. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - FLT_A_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - FLT_B_MODE : if bit one then cycle by cycle by mode and zero then latched mode + - OP_POLARITY_H Ouput polarity for high (H3, H2, H1, H0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - OP_POLARITY_L Ouput polarity for low (L3, L2, L1, L0) side signals. + \n if bit 0 then in active low mode and 1 then active high mode. + - FLT_A_ENABLE : enable fault A + - FLT_B_ENABLE : enable fault B + - COMPLEMENT_MODE : PWM I/O pair mode + \n if bit is 1 then PWM I/O pin pair is in the complementary output mode + \n if bit is 0 then PWM I/O pin pair is in the independent output mode + * @return none + */ +STATIC INLINE void RSI_MCPWM_FaultControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_FLT_OVERRIDE_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_SpecialEventTriggerEnable(RSI_MCPWM_T *pMCPWM ) + * @brief This API is used to enable generation of special event trigger for required channel of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @return none + */ +STATIC INLINE void RSI_MCPWM_SpecialEventTriggerEnable(RSI_MCPWM_T *pMCPWM) +{ + pMCPWM->PWM_SVT_CTRL_SET_REG = (1 << 0); +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_SpecialEventTriggerDisable(RSI_MCPWM_T *pMCPWM ) + * @brief This API is used to disable generation of special event trigger for required channel of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @return none + */ +STATIC INLINE void RSI_MCPWM_SpecialEventTriggerDisable(RSI_MCPWM_T *pMCPWM) +{ + pMCPWM->PWM_SVT_CTRL_RESET_REG = (1 << 0); +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value ) + * @brief This API is used to set dead time control parameters for the reqired channel. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - DEADTIME_SELECT_ACTIVE : Deadtime select bits for PWM going active + Possible values are as below if bit zero then use counter A , if one then use counter B + - DEADTIME_SELECT_INACTIVE : Deadtime select bits for PWM going inactive + Possible values are as below if bit zero then use counter A , if one then use counter B + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeControlSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_DEADTIME_CTRL_SET_REG = value; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_DeadTimeControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value ) + * @brief This API is used to reset dead time control for the MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] value : This can be logical OR of below parameters + - DEADTIME_SELECT_ACTIVE : Deadtime select bits for PWM going active + Possible values are as below if bit zero then use counter A , if one then use counter B + - DEADTIME_SELECT_INACTIVE : Deadtime select bits for PWM going inactive + Possible values are as below if bit zero then use counter A , if one then use counter B + * @return none + */ +STATIC INLINE void RSI_MCPWM_DeadTimeControlReSet(RSI_MCPWM_T *pMCPWM, uint32_t value) +{ + pMCPWM->PWM_DEADTIME_CTRL_RESET_REG = value; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_MCPWM_SetDutyCycle(RSI_MCPWM_T *pMCPWM, uint16_t dutyCycle, uint8_t chnlNum) + * @brief This API is used to set duty cycle for the required MCPWM channel. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] dutyCycle : Duty cycle value + * @param[in] chnlNum : channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_ARG : If channel number is invalid + \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_MCPWM_SetDutyCycle(RSI_MCPWM_T *pMCPWM, uint16_t dutyCycle, uint8_t chnlNum) +{ + if (chnlNum <= PWM_CHNL_3) { + pMCPWM->PWM_DUTYCYCLE_REG_WR_VALUE_b[chnlNum].PWM_DUTYCYCLE_REG_WR_VALUE_CH = dutyCycle; + } else { + return ERROR_PWM_INVALID_ARG; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_ExternalTriggerControl(RSI_MCPWM_T *pMCPWM,boolean_t enable) + * @brief This API is used to enable to use external trigger for base time counter increment or decrement of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] enable : If 0 then disable external trigger + \n If 1 then enable external trigger. + * @return none + */ +STATIC INLINE void RSI_MCPWM_ExternalTriggerControl(RSI_MCPWM_T *pMCPWM, boolean_t enable) +{ + pMCPWM->PWM_TIME_PRD_COMMON_REG_b.USE_EXT_TIMER_TRIG_FRM_REG = (unsigned int)(enable & 0x01); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_PWM_Channel_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) + * @brief This API is used to disable the reset for required channel of MCPWM. + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] chnlNum : Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel is invalid + * \n \ref RSI_OK : If process is done successfully. + */ +STATIC INLINE rsi_error_t RSI_PWM_Channel_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) +{ + // Resets operation of MCPWM channel + switch (chnlNum) { + case PWM_CHNL_0: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH0_b.PWM_SFT_RST = DISABLE; + break; + case PWM_CHNL_1: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH1_b.PWM_SFT_RST = DISABLE; + break; + case PWM_CHNL_2: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH2_b.PWM_SFT_RST = DISABLE; + break; + case PWM_CHNL_3: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH3_b.PWM_SFT_RST = DISABLE; + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_PWM_Counter_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) + * @brief This API is used to disable the counter reset for required channel of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] chnlNum : Channel number(0 to 3) + * @return \ref ERROR_PWM_INVALID_CHNLNUM : If channel number is invalid + * \n \ref RSI_OK : If process is done successfully + */ +STATIC INLINE rsi_error_t RSI_PWM_Counter_Reset_Disable(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum) +{ + // resets counter operations + switch (chnlNum) { + case PWM_CHNL_0: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH0_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + case PWM_CHNL_1: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH1_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + case PWM_CHNL_2: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH2_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + case PWM_CHNL_3: + pMCPWM->PWM_TIME_PRD_CTRL_REG_CH3_b.PWM_TIME_PRD_CNTR_RST_FRM_REG = DISABLE; + break; + default: + return ERROR_PWM_INVALID_CHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn void RSI_MCPWM_BaseTimerSelect(RSI_MCPWM_T *pMCPWM,uint8_t baseTime) + * @brief This API is used to select number of base timers as four base timers for four channels or one base timer for all channels of MCPWM + * @param[in] pMCPWM : Pointer to the MCPWM instance register area + * @param[in] baseTime : if 0 then one base timer for each channel + \n if 1 then only one base timer for all channels + * @return none + */ +STATIC INLINE void RSI_MCPWM_BaseTimerSelect(RSI_MCPWM_T *pMCPWM, uint8_t baseTime) +{ + pMCPWM->PWM_TIME_PRD_COMMON_REG_b.PWM_TIME_PRD_USE_0TH_TIMER_ONLY = (unsigned int)(baseTime & 0x01); +} +// PWM FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_MCPWM_GetVersion(void); + +RSI_MCPWM_CAPABILITIES_T RSI_MCPWM_GetCapabilities(void); + +rsi_error_t mcpwm_counter_reset(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_channel_reset(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_start(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_stop(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + +rsi_error_t mcpwm_set_time_period(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum, uint16_t period, uint16_t initVal); + +void mcpwm_special_event_trigger_config(RSI_MCPWM_T *pMCPWM, boolean_t svtDir, RSI_MCPWM_SVT_CONFIG_T *pMCPWMSVTConfig); + +rsi_error_t mcpwm_dead_time_value_set(RSI_MCPWM_T *pMCPWM, + RSI_MCPWM_DT_CONFIG_T *pMCPWMDeadTimeConfig, + uint8_t chnlNum); +rsi_error_t mcpwm_fault_avalue_set(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + +rsi_error_t mcpwm_fault_bvalue_set(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + +rsi_error_t mcpwm_set_base_timer_mode(RSI_MCPWM_T *pMCPWM, uint8_t mode, uint8_t chnlNum); + +rsi_error_t mcpwm_set_output_mode(RSI_MCPWM_T *pMCPWM, boolean_t mode, uint8_t chnlNum); + +void mcpwm_set_output_polarity(RSI_MCPWM_T *pMCPWM, boolean_t polL, boolean_t polH); + +void mcpwm_interrupt_handler(RSI_MCPWM_T *pMCPWM, RSI_MCPWM_CALLBACK_T *pCallBack); + +rsi_error_t mcpwm_period_control_config(RSI_MCPWM_T *pMCPWM, uint32_t postScale, uint32_t preScale, uint8_t chnlNum); +void SysTick_Handler(void); +uint32_t MCPWM_PercentageToTicks(uint8_t percent, uint8_t chnl_num); +void MCPWM_SetChannelPeriod(uint32_t freq); +void RSI_MCPWM_PinMux(); + +#ifdef __cplusplus +} +#endif +#endif // RSI_PWM_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h new file mode 100644 index 000000000..1c2ee3b03 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi.h @@ -0,0 +1,688 @@ +/***************************************************************************/ /** +* @file rsi_qspi.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "stdint.h" +#include "rsi_qspi_proto.h" + +#ifndef RSI_QSPI_H +#define RSI_QSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// QSPI defines +#define TA_QSPI_BASE_ADDRESS 0x10000000 +#define M4_QSPI_BASE_ADDRESS 0x12000000 +#define M4_QSPI_2_BASE_ADDRESS 0x12040000 +#define TA_QSPI_AUTOM_CHIP0_ADDRESS 0x04000000 +#define M4_QSPI_AUTOM_CHIP0_ADDRESS 0x08000000 + +#define NWP_FSM_BASE_ADDR 0x41300000 +#define MCU_NPSS_BASE_ADDR 0x24048000 +#define MCU_FSM_BASE_ADDR MCU_NPSS_BASE_ADDR + 0x100 +#define M4_BBFF_STORAGE1 *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x0580) +#define M4_BBFF_STORAGE2 *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x0584) +#define MCURET_BOOTSTATUS_REG *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x604) +#define TA_BBFF_STORAGE1 *(volatile uint32_t *)(NWP_FSM_BASE_ADDR + 0x580) +#define TA_BBFF_STORAGE2 *(volatile uint32_t *)(NWP_FSM_BASE_ADDR + 0x584) + +// This structure contains qspi registers +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +struct qspi_reg_s { + volatile uint32_t QSPI_CLK_CONFIG_REG; // qspi reg + volatile uint32_t QSPI_BUS_MODE_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_1_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_2_REG; // qspi reg + volatile uint32_t QSPI_MANUAL_CONFIG_REG; // qspi reg + volatile uint32_t QSPI_MANUAL_CONFIG_2_REG; // qspi reg + + volatile uint32_t RESERVED_1; // qspi reg + volatile uint32_t QSPI_FIFO_THRESHOLD_REG; // qspi reg + volatile uint32_t QSPI_STATUS_REG; // qspi reg + volatile uint32_t QSPI_INTR_MASK_REG; // qspi reg + volatile uint32_t QSPI_INTR_UNMASK_REG; // qspi reg + volatile uint32_t QSPI_INTR_STS_REG; // qspi reg + volatile uint32_t QSPI_INTR_ACK_REG; // qspi reg + volatile uint32_t QSPI_STS_MC_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CONFIG_1_CSN1_REG; // qspi reg + volatile uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; // qspi reg + volatile uint32_t QSPI_MANUAL_RD_WR_DATA_REG; // qspi reg + volatile uint32_t RESERVED_2[15]; // qspi reg + volatile uint32_t QSPI_MANUAL_WRITE_DATA_2_REG; // qspi reg + volatile uint32_t RESERVED_3[3]; // qspi reg + volatile uint32_t QSPI_AUTO_CONFIG3; + volatile uint32_t QSPI_AUTO_CONFIG3_CSN1; + volatile uint32_t RESERVED_4[6]; // qspi reg + volatile uint32_t OCTA_SPI_BUS_CONTROLLER; // qspi reg :2c + volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; + volatile uint32_t RESERVED_7[3]; // qspi reg + volatile uint32_t OCTA_SPI_BUS_CONTROLLER2; // qspi reg:31 +#if defined(SLI_SI917) || defined(SLI_SI915) + volatile uint32_t QSPI_AES_CONFIG; // qspi reg + volatile uint32_t QSPI_AES_KEY_IV_VALID; // qspi reg + volatile uint32_t QSPI_AES_IV1_0_3; // qspi reg + volatile uint32_t QSPI_AES_IV1_4_7; // qspi reg + volatile uint32_t QSPI_AES_IV1_8_B; // qspi reg + volatile uint32_t QSPI_AES_IV1_C_F; // qspi reg + volatile uint32_t RESERVED_8; // qspi reg +#else + volatile uint32_t QSPI_AES_KEY_0_3; // qspi reg + volatile uint32_t QSPI_AES_KEY_4_7; // qspi reg + volatile uint32_t QSPI_AES_KEY_8_B; // qspi reg + volatile uint32_t QSPI_AES_KEY_C_F; // qspi reg + volatile uint32_t QSPI_AES_NONCE_0_3; // qspi reg + volatile uint32_t QSPI_AES_NONCE_4_7; // qspi reg + volatile uint32_t QSPI_AES_NONCE_8_B; // qspi reg +#endif + volatile uint32_t QSPI_AES_SEC_SEG_ADDR[4 * 2]; // qspi reg + volatile uint32_t RESERVED_6[6]; // qspi reg + volatile uint32_t QSPI_SEMI_AUTO_ADDR_REG; + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG_REG; + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG2_REG; + volatile uint32_t QSPI_BUS_MODE2_REG; + volatile uint32_t QSPI_AES_SEC_KEY_FRM_KH; + volatile uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; // qspi reg +#if defined(SLI_SI917) || defined(SLI_SI915) + volatile uint32_t QSPI_AES_KEY1_0_3; // qspi reg + volatile uint32_t QSPI_AES_KEY1_4_7; // qspi reg + volatile uint32_t QSPI_AES_KEY1_8_B; // qspi reg + volatile uint32_t QSPI_AES_KEY1_C_F; // qspi reg + volatile uint32_t QSPI_AES_KEY1_10_13; // qspi reg + volatile uint32_t QSPI_AES_KEY1_14_17; // qspi reg + volatile uint32_t QSPI_AES_KEY1_18_1B; // qspi reg + volatile uint32_t QSPI_AES_KEY1_1C_1F; // qspi reg + volatile uint32_t QSPI_AES_KEY2_0_3; // qspi reg + volatile uint32_t QSPI_AES_KEY2_4_7; // qspi reg + volatile uint32_t QSPI_AES_KEY2_8_B; // qspi reg + volatile uint32_t QSPI_AES_KEY2_C_F; // qspi reg + volatile uint32_t QSPI_AES_KEY2_10_13; // qspi reg + volatile uint32_t QSPI_AES_KEY2_14_17; // qspi reg + volatile uint32_t QSPI_AES_KEY2_18_1B; // qspi reg + volatile uint32_t QSPI_AES_KEY2_1C_1F; // qspi reg + volatile uint32_t QSPI_AES_IV2_0_3; // qspi reg + volatile uint32_t QSPI_AES_IV2_4_7; // qspi reg + volatile uint32_t QSPI_AES_IV2_8_B; // qspi reg + volatile uint32_t QSPI_AES_IV2_C_F; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_0_3; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_4_7; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_8_B; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV1_C_F; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_0_3; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_4_7; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_8_B; // qspi reg + volatile uint32_t QSPI_AES_CTXOUT_IV2_C_F; // qspi reg +#endif +}; + +#else +struct qspi_reg_s { + volatile uint32_t QSPI_CLK_CONFIG_REG; // qspi reg 0x00 + volatile uint32_t QSPI_BUS_MODE_REG; // qspi reg 0x04 + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_1_REG; // qspi reg 0x08 + volatile uint32_t QSPI_AUTO_CTRL_CONFIG_2_REG; // qspi reg 0x0C + volatile uint32_t QSPI_MANUAL_CONFIG_REG; // qspi reg 0x10 + volatile uint32_t QSPI_MANUAL_CONFIG_2_REG; // qspi reg 0x14 + + volatile uint32_t RESERVED_1; // qspi reg 0x18 + volatile uint32_t QSPI_FIFO_THRESHOLD_REG; // qspi reg 0x1c + volatile uint32_t QSPI_STATUS_REG; // qspi reg 0x20 + volatile uint32_t QSPI_INTR_MASK_REG; // qspi reg 0x24 + volatile uint32_t QSPI_INTR_UNMASK_REG; // qspi reg 0x28 + volatile uint32_t QSPI_INTR_STS_REG; // qspi reg 0x2C + volatile uint32_t QSPI_INTR_ACK_REG; // qspi reg 0x30 + volatile uint32_t QSPI_STS_MC_REG; // qspi reg 0x34 + volatile uint32_t QSPI_AUTO_CONFIG_1_CSN1_REG; // qspi reg 0x38 + volatile uint32_t QSPI_AUTO_CONFIG_2_CSN1_REG; // qspi reg 0x3C + volatile uint32_t QSPI_MANUAL_RD_WR_DATA_REG; // qspi reg 0x40 + volatile uint32_t RESERVED_2[15]; // qspi reg -0x7c + volatile uint32_t QSPI_MANUAL_WRITE_DATA_2_REG; // qspi reg 0x80 + volatile uint32_t RESERVED_3[3]; // qspi reg -0x8C + volatile uint32_t QSPI_AUTO_CONFIG3; // qspi reg 0x90 + volatile uint32_t QSPI_AUTO_CONFIG3_CSN1; // qspi reg 0x94 + volatile uint32_t RESERVED_4[2]; // qspi reg -0x9C + + volatile uint32_t QSPI_AUTO_BASE_ADDR_CSN0; // qspi reg 0xA0 + volatile uint32_t QSPI_AUTO_BASE_ADDR_CSN1; // qspi reg 0xA4 + + volatile uint32_t RESERVED_5[2]; // qspi reg -0xAC + + volatile uint32_t OCTA_SPI_BUS_CONTROLLER; // qspi reg 0xB0 + volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN0; // qspi reg 0xB4 + + volatile uint32_t QSPI_AUTO_BASE_ADDR_UNMASK_CSN1; // qspi reg 0xB8 + + volatile uint32_t RESERVED_6[2]; // qspi reg -0xC0 + volatile uint32_t OCTA_SPI_BUS_CONTROLLER2; // qspi reg 0xC4 + + volatile uint32_t QSPI_AES_CONFIG; // qspi reg 0xC8 + volatile uint32_t QSPI_AES_KEY_IV_VALID; // qspi reg 0xCC + + volatile uint32_t QSPI_CMNFLASH_STS; // qspi reg 0xD0 + + volatile uint32_t QSPI_AES_LB_DATA_0_3; // qspi reg 0xD4 + volatile uint32_t QSPI_AES_LB_DATA_4_7; // qspi reg 0xD8 + volatile uint32_t QSPI_AES_LB_DATA_8_B; // qspi reg 0xDC + volatile uint32_t QSPI_AES_LB_DATA_C_F; // qspi reg 0xE0 + + volatile uint32_t QSPI_AES_SEC_SEG_ADDR[4 * 2]; // qspi reg -0x100 + + volatile uint32_t QSPI_SRAM_CTRL_CSN0_REG; // qspi reg 0x104 + volatile uint32_t QSPI_SRAM_CTRL_CSN1_REG; // qspi reg 0x108 + volatile uint32_t QSPI_SRAM_CTRL_CSN2_REG; // qspi reg 0x10C + volatile uint32_t QSPI_SRAM_CTRL_CSN3_REG; // qspi reg 0x110 + + volatile uint32_t CCMP_LBK_CTRL_REG; // qspi reg 0x114 + volatile uint32_t RESERVED_7; // qspi reg -0x118 + + volatile uint32_t QSPI_SEMI_AUTO_ADDR_REG; // qspi reg 0x11C + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG_REG; // qspi reg 0x120 + volatile uint32_t QSPI_SEMI_AUTO_MODE_CONFIG2_REG; // qspi reg 0x124 + volatile uint32_t QSPI_BUS_MODE2_REG; // qspi reg 0x128 + volatile uint32_t QSPI_AES_SEC_KEY_FRM_KH; // qspi reg 0x12C + volatile uint32_t QSPI_AUTO_CONITNUE_FETCH_CTRL_REG; // qspi reg 0x130 + + volatile uint32_t QSPI_AES_KEY1_0_3; // qspi reg 0x134 + volatile uint32_t QSPI_AES_KEY1_4_7; // qspi reg 0x138 + volatile uint32_t QSPI_AES_KEY1_8_B; // qspi reg 0x13C + volatile uint32_t QSPI_AES_KEY1_C_F; // qspi reg 0x140 + volatile uint32_t QSPI_AES_KEY1_10_13; // qspi reg 0x144 + volatile uint32_t QSPI_AES_KEY1_14_17; // qspi reg 0x148 + volatile uint32_t QSPI_AES_KEY1_18_1B; // qspi reg 0x14C + volatile uint32_t QSPI_AES_KEY1_1C_1F; // qspi reg 0x150 + volatile uint32_t QSPI_AES_KEY2_0_3; // qspi reg 0x154 + volatile uint32_t QSPI_AES_KEY2_4_7; // qspi reg 0x158 + volatile uint32_t QSPI_AES_KEY2_8_B; // qspi reg 0x15C + volatile uint32_t QSPI_AES_KEY2_C_F; // qspi reg 0x160 + volatile uint32_t QSPI_AES_KEY2_10_13; // qspi reg 0x164 + volatile uint32_t QSPI_AES_KEY2_14_17; // qspi reg 0x168 + volatile uint32_t QSPI_AES_KEY2_18_1B; // qspi reg 0x16C + volatile uint32_t QSPI_AES_KEY2_1C_1F; // qspi reg 0x170 + volatile uint32_t QSPI_AES_IV1_0_3; // qspi reg 0x174 + volatile uint32_t QSPI_AES_IV1_4_7; // qspi reg 0x178 + volatile uint32_t QSPI_AES_IV1_8_B; // qspi reg 0x17C + volatile uint32_t QSPI_AES_IV1_C_F; // qspi reg 0x180 + volatile uint32_t QSPI_LB_STATUS; // qspi reg 0x184 +}; +#endif + +#define XMAX(x, y) (((x) > (y)) ? (x) : (y)) +#define XMIN(x, y) (((x) < (y)) ? (x) : (y)) + +#define QSPI_BASE_ADDRESS 0x12000000 +#define QSPI_AUTOM_CHIP0_ADDRESS 0x08000000 +#define QSPI_AUTOM_CHIP1_ADDRESS 0x09000000 +#define PAD_CONFIGURATION_BASE_ADDR 0x41380000 +#define TASS_CLK_PWR_CTRL_BASE_ADDR 0x41400000 +#define GPIO_BASE_ADDR 0x40200000 +#define DMA_BASE_ADDR 0x21000000 +#define M4SS_CLK_PWR_CTRL_BASE_ADDR 0x46000000 +#define M4GPIO_BASE_ADDR 0x46130000 +#define M4PAD_CONFIGURATION_BASE_ADDR 0x46004000 +#define M4PAD_SELECTION_BASE_ADDR 0x41300000 + +#define MISC_CONFIGURATION_REG 0x46008000 +#define M4SS_QSPI_OCTA_MODE_CTRL *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1B4) +#define M4SS_QSPI_RX_DLL_TEST_REG *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1C0) +#define M4SS_QSPI_TX_DLL_TEST_REG *(volatile uint32_t *)(MISC_CONFIGURATION_REG + 0x1BC) + +#define qspi_ddr_data_0 0 +#define qspi_ddr_data_1 1 +#define qspi_ddr_data_2 2 +#define qspi_ddr_data_3 3 +#define qspi_ddr_data_4 4 +#define qspi_ddr_data_5 5 +#define qspi_ddr_data_6 6 +#define qspi_ddr_data_7 7 +#define qspi_ddr_csn 8 +#define qspi_ddr_clk 9 +#define qspi_ddr_dqs 10 +#define smih_wp 11 + +#define CHNL_21 21 +#define CHNL_20 20 + +// Qspi register defines + +// cmd len will be 8 bits +#define CMD_LEN 8 +// reg bit +#define RD_FIFO_EMPTY BIT(7) +// reg bit +#define Q_QSPI_BUSY BIT(0) +// QSPI_MANUAL_CONFIG_REG bits +#define FULL_DUPLEX_EN BIT(22) +#define TAKE_LEN_FRM_REG BIT(21) +#define HW_CTRL_MODE BIT(25) +#define READ_TRIGGER BIT(2) +#define WRITE_TRIGGER BIT(1) +#define CSN_ACTIVE BIT(0) + +// QSPI_MANUAL_CONFIG_2_REG bits +#define QSPI_LOOP_BACK_MODE_EN BIT(14) +#define QSPI_MANUAL_DDR_PHASSE BIT(15) +#define QSPI_DDR_CLK_EN BIT(16) + +// QSPI_CLK_CONFIG_REG bits +#define QSPI_DLL_CALIB BIT(28) +#define QSPI_DLL_TX_EN BIT(21) +#define QSPI_DLL_RX_EN BIT(19) + +// QSPI_AUTO_CTRL_CONFIG_1_REG bits +#define EXTRA_BYTE_EN BIT(18) + +// QSPI_AUTO_CTRL_CONFIG_2_REG bits +#define AUTO_RD_SWAP BIT(0) + +// QSPI_SEMI_AUTO_MODE_CONFIG2_REG +#define SEMI_AUTO_MODE_EN BIT(12) +#define QSPI_SEMI_AUTO_RD_BUSY BIT(13) + +#define _1BYTE 0 +#define _2BYTE 1 +#define _4BYTE 3 + +// QSPI_STATUS_REG bits +#define HW_CTRLD_QSPI_MODE_CTRL_SCLK BIT(14) +#define AUTO_MODE_ENABLED BIT(12) +#define QSPI_AUTO_MODE BIT(11) +#define AUTO_MODE_FSM_IDLE_SCLK BIT(10) +#define QSPI_MANUAL_RD_CNT BIT(9) +#define QSPI_FIFO_AEMPTY_RFIFO_S BIT(8) +#define QSPI_FIFO_EMPTY_RFIFO_S BIT(7) +#define QSPI_FIFO_AFULL_RFIFO BIT(6) +#define QSPI_FIFO_FULL_RFIFO BIT(5) +#define QSPI_FIFO_AEMPTY_WFIFO BIT(4) +#define QSPI_FIFO_EMPTY_WFIFO BIT(3) +#define QSPI_FIFO_AFULL_WFIFO_S BIT(2) +#define QSPI_FIFO_FULL_WFIFO_S BIT(1) +#define BUSY BIT(0) + +#define QSPI_FIFO_DEPTH 16 +#define QSPI_FIFO_AFULL_TH 3 +#define QSPI_FIFO_AEMPTY_TH 3 + +// QSPI_BUS_MODE_REG bits +#define AUTO_CSN_BASED_ADDR_ENABLE BIT(7) +#define AUTO_MODE BIT(6) +#define QSPI_WRAP_EN BIT(5) +#define QSPI_PREFETCH_EN BIT(4) +#define QSPI_ULTRA_HIGH_SPEED_MODE_EN BIT(0) + +// QSPI_AUTO_CONFIG3 bits +#define QSPI_RD_INST_CSN0_MSB 24 +#define QSPI_CMD_SIZE_16BIT_CSN0 BIT(18) +#define QSPI_ADR_SIZE_32BIT_AUTO_MODE BIT(19) + +// QSPI_MANUAL_WRITE_DATA_2_REG bits +#define USE_PREV_LEN BIT(7) + +// OCTA_SPI_BUS_CONTRLLER_2 bits +#define DUAL_FLASH_MODE BIT(3) + +// FLASH CMDS + +// Write enable cmd +#define WREN 0x06 +#define WREN2 0xF9 +// Write disable cmd +#define WRDI 0x04 +#define WRDI2 0xFB +// Read status reg cmd +#define RDSR 0x05 +#define RDSR2 0xFA +// chip erase cmd +#define CHIP_ERASE 0xC7 +// block erase cmd +#define BLOCK_ERASE 0xD8 +// sector erase cmd +#define SECTOR_ERASE 0x20 +// high speed rd cmd +#define HISPEED_READ 0x0B +// rd cmd +#define READ 0x03 +//write config2 +#define WCFG2 0x72 + +// SST25 specific cmds + +// Write status reg cmd +#define WRSR 0x01 +#define WRSR2 0xFE +// Enable Write status reg cmd +#define EWSR 0x50 +// Auto address incremental rd cmd +#define AAI 0xAF +// Byte program cmd +#define BYTE_PROGRAM 0x02 + +// SST26 specific cmds + +// Enable quad IO +#define EQIO 0x38 +// Reset quad IO +#define RSTQIO 0xFF +// Enable STR octa +#define OPI_ENABLE 0X01 +// Enable DDR octa +#define DOPI_ENABLE 0x02 +// wrap : set burst +#define SET_BURST 0xC0 +// wrap : read cmd +#define READ_BURST 0x0C +// Jump : page index read +#define READ_PI 0x08 +// Jump : Index read +#define READ_I 0x09 +// Jump : Block Index read +#define READ_BI 0x10 +// Page program cmd +#define PAGE_PROGRAM 0x02 +// write suspend cmd +#define Write_Suspend 0xB0 +// write resume cmd +#define Write_Resume 0x30 +// read block protection reg +#define RBPR 0x72 +// Write block protection reg +#define WBPR 0x42 +// Lockdown block protection reg +#define LBPR 0x8D + +// WINBOND + AT + MACRONIX specific cmds + +// fast read dual output +#define FREAD_DUAL_O 0x3B +// fast read quad output +#define FREAD_QUAD_O 0x6B + +#define FREAD_QUAD_O_EB 0xEB + +// WINBOND + MACRONIX specific cmds + +// fast read dual IO +#define FREAD_DUAL_IO 0xBB +// fast read quad IO +#define FREAD_QUAD_IO 0xEB + +// WINBOND specific cmds + +// Octal word read (A7-A0 must be 00) +#define OCTAL_WREAD 0xE3 +// Enable high performance cmd +#define HI_PERFMNC 0xA3 + +// ATMEL specific cmds + +// write config reg +#define WCON 0x3E +// read config reg +#define RCON 0x3F +// supported upto 100MHz +#define HI_FREQ_SPI_READ 0x1B + +#define ATMEL_QEN BIT(7) + +// MACRONIX specific write cmds + +// Address and data in quad +#define QUAD_PAGE_PROGRAM 0x38 +#define DDR_DATA 16 +#define DDR_EXTRA_BYTE 15 +#define DDR_DUMMY 14 +#define DDR_ADDR 13 +#define DDR_CMD 17 + +#define OCTA_DDR_READ 0xEE +#define OCTA_DDR_READ_CMD2 0x11 + +#define OCTA_SDR_READ 0xEC +#define OCTA_SDR_READ_CMD2 0x13 + +// ATMEL + WINBOND specific write cmds + +// Only data in quad mode +#define QUAD_IN_PAGE_PROGRAM 0x32 + +// ATMEL specific write cmds + +// Data in dual +#define DUAL_IN_PAGE_PROGRAM 0xA2 + +// MICRON specific cmds +#define RD_LOCK_REG 0xE8 +#define WR_LOCK_REG 0xE5 +#define RD_FLAG_STS_REG 0x70 +#define CLR_FLAG_STS_REG 0x50 +#define RD_NONVOL_CON_REG 0xB5 +#define WR_NONVOL_CON_REG 0xB1 +#define RD_VOL_CON_REG 0x85 +#define WR_VOL_CON_REG 0x81 +#define RD_ENHN_VOL_CON_REG 0x65 +#define WR_ENHN_VOL_CON_REG 0x61 +#define DIS_XIP BIT(3) +#define XIP_MODE 0 + +// ADESTO specific cmds + +#define STS_BYT2 0x31 +#define STS_CTRL 0x71 + +#define ADEST_PROTECT_CMD 0x36 +#define ADEST_UNPROTECT_CMD 0x39 + +// Defines for arguments + +// disable hw ctrl +#define DIS_HW_CTRL 1 +// donot disable hw ctrl +#define DNT_DIS_HW_CTRL 0 + +// 32bit hsize +#define _32BIT 3 +// 24bit hsize is not supported, so reserved +// reserved 2 +// 16bit hsize +#define _16BIT 1 +// 8bit hsize +#define _8BIT 0 + +// cmd len will be 8 bits +#define QSPI_8BIT_LEN 8 +// cmd + 1 byte len +#define QSPI_16BIT_LEN 16 +// cmd + 24bit addr len +#define QSPI_32BIT_LEN 0 + +// OCTA_SPI_BUS_CONTROLLER2 bits +// initialises NONCE +#define NONCE_INIT BIT(1) +// enables global security +#define EN_SECURITY BIT(2) +// enables of sec per segment +#define EN_SEG_SEC 12 +// enable qspi to use key from kh +#define EN_KH_KEY BIT(18) + +// QSPI AES SEC KEY FROM KH bits +// secure key loading interval +#define LOAD_SEC_KEY_FRM_KH BIT(0) + +// LIST OF MACRO USED + +// Macro to Deassert CS +#define DEASSERT_CSN qspi_reg->QSPI_MANUAL_CONFIG_REG = ((qspi_reg->QSPI_MANUAL_CONFIG_REG & (~0x1FFFU)) | 0x1) + +// Macro to check Quad mode +#define CHK_QUAD_MODE (spi_config->spi_config_1.data_mode == QUAD_MODE) +// Macro to check DUAL mode +#define CHK_DUAL_MODE (spi_config->spi_config_1.data_mode == DUAL_MODE) +#define CHK_OCTA_MODE (spi_config->spi_config_1.data_mode == OCTA_MODE) + +// Macro to provide protection byte for SST +#define SST_PROTECTION ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0xFF : 0) +// Macro to provide protection byte for WB +#define WB_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0x1C00 : 0) +// Macro to provide protection byte for MX +#define MX_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0x3C : 0) +// Macro to provide protection byte for AT +#define AT_PROT ((spi_config->spi_config_2.protection == EN_WR_PROT) ? 0xC : 0) +// Macro to get the position for D2 line data +#define GET_POS \ + ((spi_config->spi_config_2.cs_no == CHIP_THREE) ? 30 \ + : (spi_config->spi_config_2.cs_no == CHIP_TWO) ? 26 \ + : (spi_config->spi_config_2.cs_no == CHIP_ONE) ? 14 \ + : 10) + +#define GET_POS_D7_D4 \ + ((spi_config->spi_config_2.cs_no == CHIP_THREE) ? 24 \ + : (spi_config->spi_config_2.cs_no == CHIP_TWO) ? 16 \ + : (spi_config->spi_config_2.cs_no == CHIP_ONE) ? 8 \ + : 0) +// Macro to mask the d3 and d2 data bits +#define MASK_D3_D2(_POS) ~(0x3 << _POS) +#define MASK_D7_D4(_POS) ~(0xf << _POS) +// for 0xEB 0xE3 and 0xBB, 7th bit will be high so check for it +#define HI_PERFORMANCE_REQ (spi_config->spi_config_1.read_cmd & BIT(7)) + +// Macro to trigger QSPI to read from flash +#ifdef CHIP_9118 +#define READ_4M_FLASH(_NUM_BYTES, _CS_NO, Hsize) \ + qspi_reg->QSPI_MANUAL_CONFIG_REG = (qspi_reg->QSPI_MANUAL_CONFIG_REG & ~0xF8387FFF) | READ_TRIGGER | (_CS_NO << 13) \ + | ((_NUM_BYTES & 0x3FF) << 3) | (((_NUM_BYTES >> 10) & 0x1F) << 27) \ + | ((spi_config->spi_config_3.ddr_mode_en == 1) ? (BIT(21) | (Hsize << 19)) : 0) +#else +#define READ_4M_FLASH(_NUM_BYTES, _CS_NO, Hsize) \ + qspi_reg->QSPI_MANUAL_CONFIG_REG = (qspi_reg->QSPI_MANUAL_CONFIG_REG & ~0xF8387FFF) | READ_TRIGGER | (_CS_NO << 13) \ + | ((_NUM_BYTES & 0x3FF) << 3) | (((_NUM_BYTES >> 10) & 0x1F) << 27) \ + | (Hsize << 19) + +#endif +// Macro to return A8 bit in case 9bit addressing is required +#define A8_BIT ((spi_config->spi_config_2.addr_width == _9BIT_ADDR) ? ((addr & BIT(8)) << 3) : 0) + +// Macro to RETURN QSPI_BUS_SIZE from manual regs +#define QSPI_MANUAL_BUS_SIZE(_CHIP_SELECT) \ + (_CHIP_SELECT == CHIP_ZERO) ? ((qspi_reg->QSPI_BUS_MODE_REG & 0x6) >> 1) \ + : ((qspi_reg->QSPI_MANUAL_CONFIG_2_REG >> (8 + ((_CHIP_SELECT - 1) * 2))) & 0x3) +#ifdef CHIP_9118 +#define QSPI_CMD_DDR_MODE \ + (spi_config->spi_config_2.cs_no ? (qspi_reg->QSPI_AUTO_CONFIG3_CSN1 & BIT(DDR_CMD)) \ + : (qspi_reg->QSPI_AUTO_CONFIG3 & BIT(DDR_CMD))) +#define QSPI_DATA_DDR_MODE \ + (spi_config->spi_config_2.cs_no ? (qspi_reg->QSPI_AUTO_CONFIG3_CSN1 & BIT(DDR_CMD)) \ + : (qspi_reg->QSPI_AUTO_CONFIG3 & BIT(DDR_DATA))) +#define QSPI_DUAL_FLASH_MODE (qspi_reg->OCTA_SPI_BUS_CONTROLLER2 & DUAL_FLASH_MODE) +#else +#define QSPI_CMD_DDR_MODE 0 +#define QSPI_DATA_DDR_MODE 0 +#define QSPI_DUAL_FLASH_MODE 0 +#endif +// Macro to compute address width for manual mode based upon the addressing specified +#define ADDR_LEN (spi_config->spi_config_2.addr_width ? (spi_config->spi_config_2.addr_width * 8) : 8) +#define QSPI_32BIT_ADDR 32 +#define QSPI_8BIT_ADDR 8 +// Macro to compute address width for auto mode based upon addressing specified +#define AUTO_ADDR_WIDTH (((spi_config->spi_config_2.addr_width + 1) & 0x1) << 1) + +// Macro to check whether the addr violates page boundary +#define ODD_PAGE_BOUNDARY (addr & (page_size - 1)) + +// EXTRA_BYTE is currently hardcoded to 0xA0 +#define EXTRA_BYTE ((spi_config->spi_config_1.continuous) ? 0xA0 : 0x00) + +// number of dummy bytes required by the flash during a wrap/burst read command +#define NUM_DUMMY_BYTES_WRAP 1 +#define PROT_FROM_TOP BIT(3) + +#define HIGH_PERF_MODE BIT(1) +#define HSIZE_IN_BITS ((hsize + 1) * 8) + +// QSPI AES Decryption Defines +#define KEY_LEN_128 16 +#define KEY_LEN_256 32 +#if defined(SLI_SI917) || defined(SLI_SI915) +#define CTR_MODE 0x04 +#define XTS_MODE 0x80 +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +#define IV_VALID (0xf << 16) +#define KEY1_VALID (0xf << 0) +#define KEY2_VALID (0xf << 8) +#else +#define LB_IV_VALID (0xf << 8) +#define KEY1_VALID_128 (0xf0 << 0) //128-bit +#define KEY2_VALID_128 (0xf0 << 12) //128-bit +#define KEY1_VALID_256 (0xff << 0) //256-bit +#define KEY2_VALID_256 (0xff << 12) //256-bit +#endif +#define DECRYPT_KEY_CAL BIT(9) +#define KEY_FLIP_FOR_REG_INTF BIT(10) +#define KEY_FLIP_FOR_KH_INTF BIT(11) +#define SR2_READ 0x35 +#define QUAD_EN BIT(1) +#define EN_STANDALONE_AES BIT(15) +#define FLIP_IN_LB BIT(13) +#define QSPI_AES_DIN_READY BIT(2) +#define QSPI_AES_DOUT_VALID BIT(1) +#if defined(SLI_SI917B0) || defined(SLI_SI915) +#define KEY_SIZE_MASK (0x40000) +#define KEY_SIZE_256 BIT(16) +#define QSPI_KEY_SIZE_256 BIT(16) + +#define DEFAULT_AES_CONFIG (0x80) +#define DEFAULT_AES_SEC_KEY_FRM_KH (0x9 << 1) +#define DEFAULT_AES_KEY_IV_VALID (0x00) +#endif + +//XMC Flash +#define SR3_READ 0x15 +#define SR1_WRITE 0x1 +#define SR2_WRITE 0x31 +#define SR3_WRITE 0x11 +#endif + +#ifdef __cplusplus +} +#endif +void initialise_m4_efuse_in_io_mode(); +void rsi_cmemcpy(uint8_t *dst, uint8_t *src, uint32_t len); +void RSI_QSPI_GPDMA_Init(uint32_t hsize, uint32_t ch_no, uint32_t mode); +void RSI_QSPI_GPDMA_ReadFromFifo(uint32_t src, uint32_t dst, uint32_t len, uint32_t ch_no); +void RSI_QSPI_ReadFromFifo(uint32_t udma_read, void *udmaHandle, void *gpdmaHandle, uint32_t ch_no); +void RSI_QSPI_AutoModeEn(qspi_reg_t *qspi_reg); +void RSI_QSPI_ConfigQspiDll(spi_config_t *spi_config, qspi_reg_t *qspi_reg); +void RSI_QSPI_TIMER_Config(void); +void qspi_semi_auto_mode_config(qspi_reg_t *qspi_reg, uint32_t addr, uint32_t hsize, uint32_t bsize, uint32_t length); +void RSI_QSPI_ProtectAdesto(spi_config_t *spi_config, qspi_reg_t *qspi_reg, uint32_t protection, uint32_t cs_no); + +#endif // RSI_QSPI_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h new file mode 100644 index 000000000..9824f60f2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_qspi_proto.h @@ -0,0 +1,686 @@ +/***************************************************************************/ /** +* @file rsi_qspi_proto.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef QSPI_PROTO_H +#define QSPI_PROTO_H + +#ifdef __cplusplus +extern "C" { +#endif + +// GPIO register bit position related defines +#define GPIO_0_TO_5 0 +#define GPIO_6_TO_11 1 +#define GPIO_46_TO_51 2 +#define GPIO_52_TO_57 3 +#define GPIO_58_TO_63 4 +// NWP OCTA/DUAL combinations +#define GPIO_0_AND_58 5 +#define GPIO_6_AND_58 6 +#define GPIO_46_AND_58 7 +// M4 OCTA/DUAL combinations +#define GPIO_0_AND_52 8 +#define GPIO_6_AND_52 9 +#define GPIO_46_AND_52 10 +#define NOT_USING 11 // Not applicable +#define GPIO_58_AND_52 12 +#define GPIO_DDR_PADS 13 + +#define M4SS_PAD_CONFIG_REG(x) *(volatile uint32_t *)(0x46004000 + 4 * (x)) // REN enable bit(this should be enable) +#define M4_DDR_PAD_CONFIG(x) *(volatile uint32_t *)(0x46006000 + ((x)*4)) +// Pad config(P2 P1) +// 00 - Hi-Z, 01 - Pullup, 10 - PullDown, 11 - Repeater +#define PAD_CONFIG_P2 BIT(7) +#define PAD_CONFIG_P1 BIT(6) + +#define PADSELECTION \ + (*(volatile uint32_t *)(0x41300000 + 0x610)) // PAD selection (0 t0 21) A value of 1 on this gives control to M4SS +// Note BIT(0) to BIT(7) are reserved for channel no +#define DEFAULT_DESC_MODE BIT(8) +#define USE_UDMA_MODE BIT(9) + +typedef enum qspi_mode_e { NONE = 0, READ_MODE, WRITE_MODE } qspi_mode_t; + +// Structure to qspi standalone encrypt/decrypt configs +typedef struct qspi_standalone_config_s { + uint8_t aes_mode; // AES mode + bool encrypt; // 0 = Encrypt, 1 = Decrypt + bool kh_enable; // 1 = Pick the key from keyholder, 0 = pass the key + uint32_t *iv; // flash offset where data stored + uint32_t *key1; // Pass key1 if kh_enable = 0 + uint32_t *key2; // Pass key1 if kh_enable = 0 and 32 byte key + uint32_t key_len; // Key len i.e 16 or 32 bytes + uint32_t flip_data; // writing 1 to this Flips the 32-bit endian for data in standalone mode +} qspi_standalone_config_t; + +extern qspi_mode_t qspi_mode_g; + +typedef struct qspi_reg_s qspi_reg_t; +// This structure members are used to configure qspi +typedef struct spi_config_1_s { + // QSPI operation modes, all modes are single, dual or quad + + unsigned int inst_mode : 2; // instruction will be sent in this mode + unsigned int addr_mode : 2; // addr will be sent in this mode + unsigned int data_mode : 2; // data will be sent/received in this mode + unsigned int dummy_mode : 2; // dummy bytes will be sent/received in this mode + unsigned int extra_byte_mode : 2; // extra bytes will be sent in this mode + // SPI mode +#define SINGLE_MODE 0 + // dual mode +#define DUAL_MODE 1 + // quad mode +#define QUAD_MODE 2 +#define OCTA_MODE 3 + + unsigned int prefetch_en : 1; // prefetch enable +// prefetch will be enabled +#define EN_PREFETCH 1 +// prefetch will be disabled +#define DIS_PREFETCH 0 + + unsigned int dummy_W_or_R : 1; // dummy writes or read select +// dummy's are read +#define DUMMY_READS 0 +// dummy's are written +#define DUMMY_WRITES 1 + + unsigned int extra_byte_en : 1; // Enable extra byte + // Extra byte will be enabled +#define EN_EXTRA_BYTE + // Extra byte will be disabled +#define DIS_EXTRA_BYTE + + unsigned int d3d2_data : 2; // Data on D3 and D2 line in SPI or DUAL mode + + unsigned int continuous : 1; // continuous mode select + // continuous mode is selected +#define CONTINUOUS 1 + // discontinuous mode is selected +#define DIS_CONTINUOUS 0 + + unsigned int read_cmd : 8; // read cmd to be used + + unsigned int flash_type : 4; // flash defines + // sst spi flash +#define FREAD_QUAD_O 0x6B + +#define FREAD_QUAD_O_EB 0xEB + +// WINBOND + MACRONIX specific cmds + +// fast read dual IO +#define FREAD_DUAL_IO 0xBB +// fast read quad IO +#define FREAD_QUAD_IO 0xEB +#define SST_SPI_FLASH 0 + // sst dual flash +#define SST_DUAL_FLASH 1 + // sst quad flash +#define SST_QUAD_FLASH 2 + // Winbond quad flash +#define WBOND_QUAD_FLASH 3 + // Atmel quad flash +#define AT_QUAD_FLASH 4 + // macronix quad flash +#define MX_QUAD_FLASH 5 + // cFeon quad flash +#define EON_QUAD_FLASH 6 + // Micron quad flash +#define MICRON_QUAD_FLASH 7 + // Giga Device flash +#define GIGA_DEVICE_FLASH 8 + // macronix octa flash +#define MX_OCTA_FLASH 9 + // Adesto octa flash +#define ADESTO_OCTA_FLASH 10 + +#if defined(SLI_SI917) || defined(SLI_SI915) + // Adesto quad flash +#define ADESTO_QUAD_FLASH 11 + //ISSI flash +#define ISSI_FLASH 12 + + //XMC fash +#define XMC_FLASH 13 + +#endif + unsigned int no_of_dummy_bytes : 4; // no_of_dummy_bytes to be used for read operations +} spi_config_1_t; + +// This structure members are used to configure qspi +typedef struct spi_config_2_s { + + unsigned int auto_mode : 1; // mode select +// Auto mode selection +#define EN_AUTO_MODE 1 + // Manual mode selection +#define EN_MANUAL_MODE 0 + + unsigned int cs_no : 2; // QSPI chip_select +// cs-0 +#define CHIP_ZERO 0 +// cs-1 +#define CHIP_ONE 1 +// cs-2 +#define CHIP_TWO 2 +// cs-3 +#define CHIP_THREE 3 + + unsigned int reserved1 : 1; // Jump Enable +// Enables jump +#define EN_JUMP 1 +// Disables jump +#define DIS_JUMP 0 + + unsigned int neg_edge_sampling : 1; // For High speed mode, sample at neg edge +// enables neg edge sampling +#define NEG_EDGE_SAMPLING 1 +// enables pos edge sampling +#define POS_EDGE_SAMPLING 0 + + unsigned int qspi_clk_en : 1; // qspi clk select +// full time clk will be provided +#define QSPI_FULL_TIME_CLK 1 +// dynamic clk gating will be enabled +#define QSPI_DYNAMIC_CLK 0 + + unsigned int protection : 2; // flash protection select +// enable write protection +#define EN_WR_PROT 2 +// remove write protection +#define REM_WR_PROT 1 +// no change to wr protection +#define DNT_REM_WR_PROT 0 + + unsigned int dma_mode : 1; // dma mode enable +// use dma only in manaul mode +#define DMA_MODE 1 +// dma will not be used +#define NO_DMA 0 + + unsigned int swap_en : 1; // swap enable for w/r +// swap will be enabled +#define SWAP 1 +// swap will be disabled +#define NO_SWAP 0 + + unsigned int full_duplex : 2; // full duplex mode select +// do nothing for full duplex +#define IGNORE_FULL_DUPLEX 2 +// enable full duplex +#define EN_FULL_DUPLEX 1 +// disable full duplex +#define DIS_FULL_DUPLEX 0 + + unsigned int wrap_len_in_bytes : 3; // wrap len to be used +// wrap is diabled +#define NO_WRAP 7 +// 8 byte wrap will be used +#define SST_8BYTE_WRAP 0 +// 16 byte wrap will be used +#define SST_16BYTE_WRAP 1 +// 32 byte wrap will be used +#define SST_32BYTE_WRAP 2 +// 64 byte wrap will be used +#define SST_64BYTE_WRAP 3 + +// 16 byte wrap will be used +#define MICRON_16BYTE_WRAP 0 +// 32 byte wrap will be used +#define MICRON_32BYTE_WRAP 1 +// 64 byte wrap will be used +#define MICRON_64BYTE_WRAP 2 + + unsigned int addr_width_valid : 1; + // mode 3 clk will be used + // mode 0 clk will be used + + unsigned int addr_width : 3; // addr width to used +// 32 bit addr is configured +#define _32BIT_ADDR 4 +// 24 bit addr is configured +#define _24BIT_ADDR 3 +// 16 bit addr is configured +#define _16BIT_ADDR 2 +// 9 bit addr is configured +#define _9BIT_ADDR 1 +// 8 bit addr is configured +#define _8BIT_ADDR 0 + +#define MANUAL_DUMMY_BYTE_OR_BIT_MODE BIT(25) +#define DUMMY_BYTE_OR_BIT_MODE BIT(0) + unsigned int dummy_cycles_for_controller : 2; + + unsigned int reserved2 : 6; + // uint32 jump_inst : 8; // Instruction to be used in case of jump + + unsigned int pinset_valid : 1; + + unsigned int flash_pinset : 4; // width of memory protection reg for sst flashes + +} spi_config_2_t; + +// This structure members are used to configure qspi +typedef struct spi_config_3_s { +#define CONTINUE_FETCH_EN BIT(12) +#define WORD_SWAP_EN 20 + unsigned int en_word_swap : 1; + unsigned int _16bit_cmd_valid : 1; + unsigned int _16bit_rd_cmd_msb : 8; + unsigned int xip_mode : 1; + unsigned int no_of_dummy_bytes_wrap : 4; // no_of_dummy_bytes to be used for wrap operations +#ifdef CHIP_9118 + unsigned int ddr_mode_en : 1; +#else + unsigned int reserved : 1; +#endif + unsigned int wr_cmd : 8; + unsigned int wr_inst_mode : 2; + unsigned int wr_addr_mode : 2; + unsigned int wr_data_mode : 2; + unsigned int dummys_4_jump : 2; // no_of_dummy_bytes in case of jump instruction +} spi_config_3_t; + +typedef struct spi_config_4_s { + unsigned int _16bit_wr_cmd_msb : 8; + unsigned int high_perf_mode_en : 1; //used for high performance mode not ddr + unsigned int qspi_loop_back_mode_en : 1; +#ifdef CHIP_9118 + unsigned int qspi_manual_ddr_phasse : 1; + unsigned int ddr_data_mode : 1; + unsigned int ddr_inst_mode : 1; + unsigned int ddr_addr_mode : 1; + unsigned int ddr_dummy_mode : 1; + unsigned int ddr_extra_byte : 1; +#else + unsigned int reserved : 1; + unsigned int reserved1 : 1; + unsigned int reserved2 : 1; + unsigned int reserved3 : 1; + unsigned int reserved4 : 1; + unsigned int reserved5 : 1; +#endif + unsigned int dual_flash_mode : 1; + unsigned int secondary_csn : 1; + unsigned int polarity_mode : 1; + unsigned int valid_prot_bits : 4; + unsigned int no_of_ms_dummy_bytes : 4; +#ifdef CHIP_9118 + unsigned int ddr_dll_en : 1; +#else + unsigned int reserved6 : 1; +#endif + unsigned int continue_fetch_en : 1; + unsigned int dma_write : 1; + unsigned int prot_top_bottom : 1; + unsigned int auto_csn_based_addr_en : 1; +} spi_config_4_t; +typedef struct spi_config_5_s { + unsigned int block_erase_cmd : 16; + unsigned int busy_bit_pos : 3; + unsigned int d7_d4_data : 4; + unsigned int dummy_bytes_for_rdsr : 4; + unsigned int reset_type : 5; +} spi_config_5_t; + +typedef struct spi_config_6_s { + unsigned int chip_erase_cmd : 16; + unsigned int sector_erase_cmd : 16; +} spi_config_6_t; + +typedef struct spi_config_7_s { + unsigned int status_reg_write_cmd : 16; + unsigned int status_reg_read_cmd : 16; +} spi_config_7_t; + +// This structure has two daughter structures to configure qspi +typedef struct spi_config_s { + spi_config_1_t spi_config_1; // daughter structure 1 + spi_config_2_t spi_config_2; // daughter structure 2 + spi_config_3_t spi_config_3; // daughter structure 3 + spi_config_4_t spi_config_4; // daughter structure 4 + spi_config_5_t spi_config_5; // daughter structure 5 + spi_config_6_t spi_config_6; // daughter structure 5 + spi_config_7_t spi_config_7; // daughter structure 5 +} spi_config_t; + +typedef const struct qspi_func_s qspi_func_t; + +struct qspi_func_s { + + void (*qspi_write_to_flash)(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); + + void (*qspi_switch_qspi2)(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); + + uint32_t (*qspi_wait_flash_status_Idle)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + + void (*qspi_enable_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t flash_type, + spi_config_t *spi_config, + uint32_t cs_no); + + void (*qspi_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t write_value, + spi_config_t *spi_config, + uint32_t wr_reg_delay_ms); + + uint32_t (*qspi_flash_reg_read)(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); + + void (*qspi_flash_reg_write)(qspi_reg_t *qspi_reg, + uint32_t reg_write_cmd, + uint32_t reg_write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + + void (*qspi_set_flash_mode)(qspi_reg_t *qspi_reg, + uint32_t data_mode, + uint32_t cs_no, + uint32_t ddr_en, + uint32_t flash_type); + + void (*qspi_config_qflash4_read)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); + + void (*qspi_manual_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + + void (*qspi_auto_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config); + + void (*qspi_auto_read)(uint32_t cs_no, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + spi_config_t *spi_config, + uint32_t dma_flags); + + void (*qspi_flash_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + + void (*qspi_spi_init)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t RSI_QSPI_FlashInit_req, + uint32_t wr_reg_delay_ms, + uint8_t fifo_thrsld); + + void (*qspi_spi_erase)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t erase_cmd, + uint32_t blk_sec_addr, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms); + + uint32_t (*qspi_spi_write)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t write_cmd, + uint32_t addr, + uint8_t *data, + uint32_t len_in_bytes, + uint16_t page_size, + uint32_t hsize, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms, + uint32_t check_en, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + + void (*qspi_spi_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + void (*RSI_QSPI_ConfigureQspiRead)(spi_config_t *spi_config, qspi_func_t *qspi_func); + + void (*RSI_QSPI_ConfigureQspiWrite)(spi_config_t *spi_config, qspi_func_t *qspi_func); + void (*qspi_usleep)(uint32_t delay_us); // function ptr for halting processor for delay (us) specified + + void (*qspi_write_block_protect)(qspi_reg_t *qspi_reg, + uint32_t protect, + uint32_t cs_no, + uint32_t num_prot_bytes, + uint32_t wr_reg_delay_ms); + +#if defined(SLI_SI917) || defined(SLI_SI915) +#if defined(SLI_SI917B0) || defined(SLI_SI915) + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, + uint8_t mode, + uint32_t *key1, + uint32_t *key2, + uint32_t key_len, + uint32_t kh_enable); +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); +#endif +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); +#endif + void (*qspi_qspiload_nonce)(qspi_reg_t *qspi_reg, uint32_t *nonce); + void (*qspi_seg_sec_en)(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); + void (*qspi_status_control_reg_write)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint16_t write_command, + uint32_t addr, + uint16_t write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + void (*qspi_flash_protection)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint32_t protection, + uint32_t wr_reg_delay_ms); + + void (*RSI_QSPI_ConfigQspiDll)(spi_config_t *spi_config, qspi_reg_t *qspi_reg); + + void (*RSI_QSPI_ResetFlash)(qspi_reg_t *qspi_reg, uint32_t cs_no); + + void (*RSI_QSPI_UpdateOperatingMode_and_ResetType)(qspi_reg_t *qspi_reg, uint32_t operating_mode); +}; + +// SPI API LIST + +uint32_t qspi_flash_reg_read(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); + +void qspi_status_reg_write(qspi_reg_t *qspi_reg, + uint32_t write_value, + spi_config_t *spi_config, + uint32_t wr_reg_delay_ms); + +void qspi_enable_status_reg_write(qspi_reg_t *qspi_reg, uint32_t flash_type, spi_config_t *spi_config, uint32_t cs_no); + +uint32_t qspi_wait_flash_status_Idle(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + +void qspi_spi_init(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t flash_init_req, + uint32_t wr_reg_delay_ms, + uint8_t fifo_thrsld); +#define FLASH_INIT_REQ 1 +#define SKIP_FLASH_INIT 0 + +void qspi_spi_erase(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t erase_cmd, + uint32_t blk_sec_addr, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms); +// chip erase cmd +#define CHIP_ERASE 0xC7 +// block erase cmd +#define BLOCK_ERASE 0xD8 +// sector erase cmd +#define SECTOR_ERASE 0x20 + +// disable hw ctrl +#define DIS_HW_CTRL 1 +// donot disable hw ctrl +#define DNT_DIS_HW_CTRL 0 + +// 32bit hsize +#define _32BIT 3 +// 24bit hsize is not supported, so reserved +// reserved 2 +// 16bit hsize +#define _16BIT 1 +// 8bit hsize +#define _8BIT 0 + +uint32_t qspi_spi_write(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t write_cmd, + uint32_t addr, + uint8_t *data, + uint32_t len_in_bytes, + uint16_t page_size, + uint32_t hsize, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms, + uint32_t check_en, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + +void qspi_spi_read(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + +uint32_t RSI_QSPI_Aes_Encrypt_Decrypt_Standalone(qspi_reg_t *qspi_reg, + qspi_standalone_config_t *configs, + uint32_t *in_data, + uint32_t *out_data, + uint32_t data_length); + +// ROM API Fuctions + +void qspi_write_block_protect(qspi_reg_t *qspi_reg, + uint32_t protect, + uint32_t cs_no, + uint32_t num_prot_bytes, + uint32_t wr_reg_delay_ms); +void qspi_usleep(uint32_t delay_us); // function ptr for halting processor for delay (us) specified +void qspi_auto_init(qspi_reg_t *qspi_reg, spi_config_t *spi_config); +void qspi_set_flash_mode(qspi_reg_t *qspi_reg, + uint32_t data_mode, + uint32_t cs_no, + uint32_t ddr_en, + uint32_t flash_type); + +void qspi_write_to_flash(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); + +void qspi_switch_qspi2(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); + +void qspi_flash_reg_write(qspi_reg_t *qspi_reg, + uint32_t reg_write_cmd, + uint32_t reg_write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + +void qspi_config_qflash4_read(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); + +void qspi_manual_read(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t dma_flags, + void *udmaHandle, + void *rpdmaHandle); + +void qspi_auto_read(uint32_t cs_no, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + spi_config_t *spi_config, + uint32_t dma_flags); + +void qspi_flash_init(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + +#if defined(SLI_SI917) || defined(SLI_SI915) +#if defined(SLI_SI917B0) || defined(SLI_SI915) +void qspi_qspiload_key(qspi_reg_t *qspi_reg, + uint8_t mode, + uint32_t *key1, + uint32_t *key2, + uint32_t key_len, + uint32_t kh_enable); +#else +void qspi_qspiload_key(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); +#endif +#else +void qspi_qspiload_key(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); +#endif + +void qspi_qspiload_nonce(qspi_reg_t *qspi_reg, uint32_t *nonce); + +void qspi_seg_sec_en(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); +void qspi_status_control_reg_write(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint16_t write_command, + uint32_t addr, + uint16_t write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); +void qspi_flash_protection(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint32_t protection, + uint32_t wr_reg_delay_ms); + +void RSI_QSPI_ResetFlash(qspi_reg_t *qspi_reg, uint32_t cs_no); + +void RSI_QSPI_UpdateOperatingMode_and_ResetType(qspi_reg_t *qspi_reg, uint32_t operating_mode); + +extern spi_config_t spi_default_config; + +#ifdef __cplusplus +} +#endif + +#endif // QSPI_PROTO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h new file mode 100644 index 000000000..8f00f89a4 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_rng.h @@ -0,0 +1,60 @@ +/***************************************************************************/ /** +* @file rsi_rng.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +//Include Files + +#include "rsi_ccp_common.h" +#include "base_types.h" + +#ifndef RSI_RNG_H +#define RSI_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define RSI_RNG_TRUE_RANDOM 0 ///< Define for true random number generation mode. +#define RSI_RNG_PSEUDO_RANDOM 1 ///< Define for pseudo-random number generation mode. +#define RSI_RNG_LFSR_32_BIT_INPUT_VALID \ + 0x10 ///< Define for 32-bit input valid in LFSR (Linear Feedback Shift Register) mode. +#define HWRNG_CLK_ENABLE 0x400000 ///< Define to enable the clock for the hardware random number generator. + +typedef enum rng_lfsr_config { RNG_LFSR_DISABLE = 0, RNG_LFSR_ENABLE = 1 } rng_lfsr_config_t; + +uint32_t rng_start(HWRNG_Type *pRNG, uint8_t rng_mode); +void rng_stop(HWRNG_Type *pRNG); +void rng_get_bytes(HWRNG_Type *pRNG, uint32_t *random_bytes, uint32_t number_of_bytes); +uint32_t rng_read_lfsr_input(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes); +void rng_config_lfsr(HWRNG_Type *pRNG, rng_lfsr_config_t lfsr_config_param); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_RNG_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h new file mode 100644 index 000000000..56dbc6a05 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_timers.h @@ -0,0 +1,369 @@ +/******************************************************************************* +* @file rsi_timers.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +//Include Files + +#include "rsi_ccp_common.h" +#include "rsi_error.h" + +#ifndef RSI_TIMERS_H +#define RSI_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// LOCAL OR GLOBAL DEFINES + +#define RSI_TIMERS_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(2, 00) // API version 0.1 +#define RSI_TIMERS_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // driver version 0.1 + +#define MICRO_SEC_MODE 1 +#define _256_MICRO_SEC_MODE 2 +#define COUNTER_DOWN_MODE 0 + +// TIMERS Events +#define RSI_TIMERS_EVENT_TIMER0_TIMEOUT (1UL << 0) // Timer0 timeout interrupt +#define RSI_TIMERS_EVENT_TIMER1_TIMEOUT (1UL << 1) // Timer1 timeout interrupt +#define RSI_TIMERS_EVENT_TIMER2_TIMEOUT (1UL << 2) // Timer2 timeout interrupt +#define RSI_TIMERS_EVENT_TIMER3_TIMEOUT (1UL << 3) // Timer3 timeout interrupt + +#define TIMER_MODE 0x18 + +// Example defines +#define TIMER_0 0 +#define TIMER_1 1 +#define TIMER_2 2 +#define TIMER_3 3 + +#define ULP_TIMER_RF_REF_CLK 0 +#define ULP_TIMER_ULP_32KHZ_RO_CLK 1 +#define ULP_TIMER_ULP_32KHZ_RC_CLK 2 +#define ULP_TIMER_ULP_32KHZ_XTAL_CLK 3 +#define ULP_TIMER_ULP_MHZ_RC_CLK 4 +#define ULP_TIMER_ULP_20MHZ_RO_CLK 5 +#define ULP_TIMER_SOC_CLK 6 + +#define ULP_TIMER_CLK_DIV_FACT 0 + +#define PERIODIC_TIMER 1 +#define ONESHOT_TIMER 0 + +typedef TIMERS_Type RSI_TIMERS_T; + +// brief TIMERS Driver Capabilities. +typedef struct { + unsigned int timerCount : 4; // Number of Timers + unsigned int microSecMode : 1; // supports Micro second mode +} RSI_TIMERS_CAPABILITIES_T; + +/// @brief Enumeration to represent ulp-timer direction +typedef enum { + DOWN_COUNTER, ///< For ULP Timer up-counting direction + UP_COUNTER, ///< For ULP Timer down-counting direction + LAST_DIRECTION, ///< Last member of enum for validation +} ulp_timer_dir_t; + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum, boolean_t countDir) + * @brief This API is used to set direction of the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @param[in] countDir : counter direction + * - \ref UP_COUNTER + * - \ref DOWN_COUNTER + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetDirection(RSI_TIMERS_T *pTIMER, uint8_t timerNum, ulp_timer_dir_t countDir) +{ + if (timerNum <= TIMER_3) { + if (countDir == UP_COUNTER) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.COUNTER_UP = ENABLE; + } else if (countDir == DOWN_COUNTER) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.COUNTER_UP = DISABLE; + } else { + return ERROR_INVAL_COUNTER_DIR; + } + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_TIMERS_getDirection(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to get direction of the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * + * @return countDir : counter direction + * - 1 for UP_COUNTER + * - 0 for DOWN_COUNTER + */ +STATIC INLINE uint32_t RSI_TIMERS_getDirection(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + uint8_t counterDir; + if (timerNum <= TIMER_3) { + counterDir = pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.COUNTER_UP; + return counterDir; + } else { + return ERROR_INVAL_TIMER_NUM; + } +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_TIMERS_GetTimerMode(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to get the mode of timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the type of timer if valid timer else error code + */ +STATIC INLINE uint32_t RSI_TIMERS_GetTimerMode(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + return (pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_MODE); + } else { + return ERROR_INVAL_TIMER_NUM; + } +} +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_TimerStart(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to start the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_TimerStart(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_START = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_TimerStop(RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to stop the timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_TimerStop(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_STOP = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptEnable(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to enable the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_InterruptEnable(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_INTR_ENABLE = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptDisable(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to disable the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_InterruptDisable(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_INTR_ENABLE = DISABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptClear(RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to clear the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_InterruptClear(RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_INTR_CLR = ENABLE; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetMatch( RSI_TIMERS_T *pTIMER, uint8_t timerNum, uint32_t match) + * @brief This API is used to disable the timer interrupt + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @param[in] match : delay time + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetMatch(RSI_TIMERS_T *pTIMER, uint8_t timerNum, uint32_t match) +{ + if (timerNum <= TIMER_3) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_MATCH = match; + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_InterruptStatus(const RSI_TIMERS_T *pTIMER , uint8_t timerNum) + * @brief This API is used to get the timer interrupt status + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer interrupt status if valid timer else 0. + */ +STATIC INLINE uint8_t RSI_TIMERS_InterruptStatus(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + return (uint8_t)(pTIMER->MCUULP_TMR_INTR_STAT & (1 << timerNum)); + } else { + return 0; + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetTimerType( RSI_TIMERS_T *pTIMER, uint8_t timerType, uint8_t timerNum) + * @brief This API is used to set the timer type + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerType : timer type + * - \ref MICRO_SEC_MODE + * - \ref _256_MICRO_SEC_MODE + * - \ref COUNTER_DOWN_MODE + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetTimerType(RSI_TIMERS_T *pTIMER, uint8_t timerType, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + if ((timerType == MICRO_SEC_MODE) || (timerType == _256_MICRO_SEC_MODE) || (timerType == COUNTER_DOWN_MODE)) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_TYPE = (unsigned int)(timerType & 0x03); + } else { + return ERROR_INVAL_TIMERTYPE; + } + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_TIMERS_SetTimerMode(RSI_TIMERS_T *pTIMER, boolean_t mode,uint8_t timerNum) + * @brief This API is used to set the timer mode + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] mode : in which mode timer run + * - \ref PERIODIC_TIMER + * - \ref ONESHOT_TIMER + * @param[in] timerNum : Timer number(0 to 3) + * @return return the timer error code + */ +STATIC INLINE rsi_error_t RSI_TIMERS_SetTimerMode(RSI_TIMERS_T *pTIMER, boolean_t mode, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + if ((mode == PERIODIC_TIMER) || (mode == ONESHOT_TIMER)) { + pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_MODE = (unsigned int)(mode & 0x01); + } else { + return ERROR_INVAL_TIMER_MODE; + } + } else { + return ERROR_INVAL_TIMER_NUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_TIMERS_GetTimerType(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) + * @brief This API is used to get the type of timer + * @param[in] pTIMER : Pointer to the TIMERS instance register area + * @param[in] timerNum : Timer number(0 to 3) + * @return return the type of timer if valid timer else error code + */ +STATIC INLINE uint32_t RSI_TIMERS_GetTimerType(const RSI_TIMERS_T *pTIMER, uint8_t timerNum) +{ + if (timerNum <= TIMER_3) { + return (pTIMER->MATCH_CTRL[timerNum].MCUULP_TMR_CNTRL_b.TMR_TYPE); + } else { + return ERROR_INVAL_TIMER_NUM; + } +} + +// TIMERS FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_TIMERS_GetVersion(void); + +RSI_TIMERS_CAPABILITIES_T RSI_TIMERS_GetCapabilities(void); + +rsi_error_t timers_microsec_timer_config(RSI_TIMERS_T *pTIMER, + uint8_t timerNum, + uint16_t integer, + uint8_t fractional, + uint8_t mode); +uint32_t timers_read_timer(RSI_TIMERS_T *pTIMER, uint8_t timerNum, boolean_t countDir); +void IRQ002_Handler(); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_TIMERS_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h new file mode 100644 index 000000000..872da676d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma.h @@ -0,0 +1,578 @@ +/******************************************************************************* +* @file rsi_udma.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +//Include Files + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_packing.h" + +#ifndef RSI_UDMA_H +#define RSI_UDMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +#define RSI_UDMA_DRV_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(02, 00) // driver version +#define RSI_UDMA_API_VERSION RSI_DRIVER_VERSION_MAJOR_MINOR(00, 01) // API version +#define UDMA_CHANNEL_NUM 32 + +#define M4SS_UDMA_INTR_SEL (*((uint32_t volatile *)(0x46110000 + 0x0C))) +#define ULP_DYN_CLK_CTRL_DIS_REG (*((uint32_t volatile *)(0x24041400 + 0xA0))) +#define ULP_UDMA_STATIC_CLK_EN (1UL << 17) +#define PERIPHERAL_UDMA_DMA_SEL (*((uint32_t volatile *)(0x46008000UL + 0x58))) + +#define UDMA_ATTR_USEBURST 0x1 +#define UDMA_ATTR_ALTSELECT 0x2 +#define UDMA_ATTR_HIGH_PRIORITY 0x4 +#define UDMA_ATTR_REQMASK 0x8 +#define UDMA_ATTR_ALL 0xF + +// DMA control modes + +#define CHNL0_INTR (1UL << 0) // Channel0 interrupt flag +#define CHNL1_INTR (1UL << 1) // Channel1 interrupt flag +#define CHNL2_INTR (1UL << 2) // Channel2 interrupt flag +#define CHNL3_INTR (1UL << 3) // Channel3 interrupt flag +#define CHNL4_INTR (1UL << 4) // Channel4 interrupt flag +#define CHNL5_INTR (1UL << 5) // Channel5 interrupt flag +#define CHNL6_INTR (1UL << 6) // Channel6 interrupt flag +#define CHNL7_INTR (1UL << 7) // Channel7 interrupt flag +#define CHNL8_INTR (1UL << 8) // Channel8 interrupt flag +#define CHNL9_INTR (1UL << 9) // Channel9 interrupt flag +#define CHNL10_INTR (1UL << 10) // Channel10 interrupt flag +#define CHNL11_INTR (1UL << 11) // Channel11 interrupt flag +#define CHNL12_INTR (1UL << 12) // Channel12 interrupt flag +#define CHNL13_INTR (1UL << 13) // Channel13 interrupt flag +#define CHNL14_INTR (1UL << 14) // Channel14 interrupt flag +#define CHNL15_INTR (1UL << 15) // Channel15 interrupt flag +#define CHNL16_INTR (1UL << 16) // Channel16 interrupt flag +#define CHNL17_INTR (1UL << 17) // Channel17 interrupt flag +#define CHNL18_INTR (1UL << 18) // Channel18 interrupt flag +#define CHNL19_INTR (1UL << 19) // Channel19 interrupt flag +#define CHNL20_INTR (1UL << 20) // Channel20 interrupt flag +#define CHNL21_INTR (1UL << 21) // Channel21 interrupt flag +#define CHNL22_INTR (1UL << 22) // Channel22 interrupt flag +#define CHNL23_INTR (1UL << 23) // Channel23 interrupt flag +#define CHNL24_INTR (1UL << 24) // Channel24 interrupt flag +#define CHNL25_INTR (1UL << 25) // Channel25 interrupt flag +#define CHNL26_INTR (1UL << 26) // Channel26 interrupt flag +#define CHNL27_INTR (1UL << 27) // Channel27 interrupt flag +#define CHNL28_INTR (1UL << 28) // Channel28 interrupt flag +#define CHNL29_INTR (1UL << 29) // Channel29 interrupt flag +#define CHNL30_INTR (1UL << 30) // Channel30 interrupt flag +#define CHNL31_INTR (1UL << 31) // Channel31 interrupt flag + +#define UDMA_MODE_STOP 0x0 +#define UDMA_MODE_BASIC 0x1 +#define UDMA_MODE_AUTO 0x2 +#define UDMA_MODE_PINGPONG 0x3 +#define UDMA_MODE_MEM_SCATTER_GATHER 0x4 +#define UDMA_MODE_MEM_ALT_SCATTER_GATHER 0x5 +#define UDMA_MODE_PER_SCATTER_GATHER 0x6 +#define UDMA_MODE_ALT_SELECT 0x1 +#define UDMA_SOFTWARE_TRIGG 0X2 + +#define UDMA_DST_INC_NONE 0x3 +#define UDMA_SRC_INC_NONE 0x3 + +#define UDMA_PRI_SELECT 0x00 +#define UDMA_ALT_SELECT 0x20 +#define UDMA_ULPALT_SELECT 0x10 + +#define UDMA_CHCTL_XFERSIZE_M 0x3FF +#define UDMA_CHCTL_XFERMODE_M 0x07 +#define UDMA_CHCTL_XFERSIZE_S 0x04 + +#define SRC_SIZE_32 0x2 +#define SRC_SIZE_16 0x1 +#define SRC_SIZE_8 0x0 + +#define DST_SIZE_32 0x2 +#define DST_SIZE_16 0x1 +#define DST_SIZE_8 0x0 + +#define SRC_INC_NONE 0x3 +#define SRC_INC_32 0x2 +#define SRC_INC_16 0x1 +#define SRC_INC_8 0x0 + +#define DST_INC_NONE 0x3 +#define DST_INC_32 0x2 +#define DST_INC_16 0x1 +#define DST_INC_8 0x0 + +#define ARBSIZE_1 0x00 +#define ARBSIZE_2 0x01 +#define ARBSIZE_4 0x02 +#define ARBSIZE_8 0x03 +#define ARBSIZE_16 0x04 +#define ARBSIZE_32 0x05 +#define ARBSIZE_64 0x06 +#define ARBSIZE_128 0x07 +#define ARBSIZE_256 0x08 +#define ARBSIZE_512 0x09 +#define ARBSIZE_1024 0x0A + +#define DMA_XFERS_1 0x0 +#define DMA_XFERS_2 0x1 +#define DMA_XFERS_3 0x2 +#define DMA_XFERS_4 0x3 +#define DMA_XFERS_5 0x4 +#define DMA_XFERS_6 0x5 +#define DMA_XFERS_7 0x6 +#define DMA_XFERS_8 0x7 +#define DMA_XFERS_9 0x8 +#define DMA_XFERS_10 0x9 +#define DMA_XFERS_11 0xA +#define DMA_XFERS_16 0xF +#define DMA_XFERS_31 0x1F +#define DMA_XFERS_101 0x64 +#define DMA_XFERS_256 0xFF +#define DMA_XFERS_1024 0x3FF + +#define USART0_ACK 0x1 +#define UART1_ACK 0x2 +#define UART3_ACK 0x3 +#define SSISLAVE_ACK 0x4 +#define SSIMASTER_ACK 0x5 +#define SSISLAVE1_ACK 0x6 +#define I2C_ACK 0x7 +#define CHNL_0 0 +#define CHNL_31 31 + +#define PRIMARY 0 +#define ALTERNATE 1 +#define CHNL_0 0 +#define CHNL_1 1 + +#define SRC_SIZE_32 0x2 +#define SRC_SIZE_16 0x1 +#define SRC_SIZE_8 0x0 + +#define DST_SIZE_32 0x2 +#define DST_SIZE_16 0x1 +#define DST_SIZE_8 0x0 + +#define SRC_INC_32 0x2 +#define SRC_INC_16 0x1 +#define SRC_INC_8 0x0 + +#define DST_INC_32 0x2 +#define DST_INC_16 0x1 +#define DST_INC_8 0x0 + +#define SRC_DST_SIZE_32 2 +#define SRC_DST_SIZE_16 1 +#define SRC_DTS_SIZE_8 0 + +#define MEM_SG 0 +#define PERI_SG 1 + +typedef UDMA0_Type RSI_UDMA_T; + +// brief RPDMA handle type +typedef void *RSI_UDMA_HANDLE_T; + +// brief UDMA Driver Capabilities. +typedef struct { + uint32_t noOfChannels; // Number of DMA channels + uint32_t maxNoOfTxferPerCycle; // Maximum number of transfers per DMA cycle +} RSI_UDMA_CAPABILITIES_T; + +// brief UDMA Channel Config structure +typedef struct { + unsigned int transferType : 3; // The operating mode of the DMA cycle + unsigned int + nextBurst : 1; // Used to force the channel to only respond to burst requests at the tail end of a scatter-gather transfer + unsigned int totalNumOfDMATrans : 10; // total number of DMA transfers that the DMA cycle contains + unsigned int rPower : 4; // Number of DMA transfers can occur before the controller rearbitrates + unsigned int srcProtCtrl : 3; // Performs control operation when the controller reads the source data + unsigned int dstProtCtrl : 3; // Performs control operation when the controller writes the destination data + unsigned int srcSize : 2; // Source data size + unsigned int srcInc : 2; // Source address increment + unsigned int dstSize : 2; // Destination data size + unsigned int dstInc : 2; // Destination address increment +} RSI_UDMA_CHA_CONFIG_DATA_T; + +// brief UDMA Control Structure. +typedef struct { + volatile void *pSrcEndAddr; // The ending source address of the data transfer + volatile void *pDstEndAddr; // The ending destination address of the data transfer + volatile RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData1; // The Channel Config Structure + volatile uint32_t Spare; // An unused location +} RSI_UDMA_DESC_T; + +typedef void (*udmaTransferCompleteCB)(RSI_UDMA_HANDLE_T udmaHandle, RSI_UDMA_DESC_T *pTranDesc, uint32_t dmaCh); + +// brief RPDMA controller callback IDs +typedef enum { + ROM_UDMA_XFERCOMPLETE_CB = 0, // Callback ID for UDMA transfer descriptor chain complete +} ROM_UDMA_CALLBACK_T; + +// Private data structure used for the RPDMA controller driver, holds the driver and peripheral context +typedef struct { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + RSI_UDMA_T *base; // UDMA base address + RSI_UDMA_DESC_T *sramBase; // SRAM descriptor table (all channels) + RSI_UDMA_DESC_T *desc; // descriptor structure + udmaTransferCompleteCB udmaCompCB; // Transfer complete callback + uint32_t dmaCh; +} RSI_UDMA_DATACONTEXT_T; + +// RPDMA Init structure +typedef PRE_PACK struct POST_PACK { + void *pUserData; // Pointer to user data used by driver instance, use NULL if not used + uint32_t base; // Pointer to RPDMA global register instance + uint32_t sramBase; // Pointer to memory used for RPDMA descriptor storage, must be 512 byte aligned +} RSI_UDMA_INIT_T; + +// brief RPDMA transfer channel setup structure (use this structure as const if possible) +typedef PRE_PACK struct POST_PACK { + uint32_t channelPrioHigh; // Channel priority level + uint32_t altStruct; // Primary or alternate control structure + uint32_t burstReq; // Burst request + uint32_t reqMask; // Mask channel request + uint32_t periphReq; // Peripheral request + uint32_t periAck; // dma ACK for peripheral + uint32_t dmaCh; +} RSI_UDMA_CHA_CFG_T; +/** @addtogroup SOC18 +* @{ +*/ + +/*===================================================*/ +/** + * @fn uint32_t RSI_UDMA_GetMemSize(void) + * @brief This API is used to Get memory size in bytes needed for UDMA controller driver context + * @return Size in bytes needed for the ROM driver + */ +STATIC INLINE uint32_t RSI_UDMA_GetMemSize(void) +{ + return sizeof(RSI_UDMA_DATACONTEXT_T); +} + +/*===================================================*/ +/** + * @fn void RSI_UDMA_RegisterCallback(RSI_UDMA_HANDLE_T pHandle, void *pCB) + * @brief Registers an DMA controller callback for a queue + * @param[in] pHandle : Pointer to driver context handle + * @param[in] pCB : Pointer to callback function + * @return none + */ +STATIC INLINE void RSI_UDMA_RegisterCallback(RSI_UDMA_HANDLE_T pHandle, udmaTransferCompleteCB pCB) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + + pDrv->udmaCompCB = pCB; +} + +/*===================================================*/ +/** + * @fn void RSI_UDMA_UDMAEnable(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to enable the UDMA interface + * @param[in] pHandle : Pointer to driver context handle + * @return none + */ +STATIC INLINE void RSI_UDMA_UDMAEnable(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + pDrv->base->DMA_CFG_b.MASTER_ENABLE = ENABLE; +} + +/*===================================================*/ +/** + * @fn void RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to disable the UDMA interface + * @param[in] pHandle : Pointer to driver context handle + * @return none + */ + +STATIC INLINE void RSI_UDMA_UDMADisable(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + + pDrv->base->DMA_CFG_b.MASTER_ENABLE = DISABLE; +} + +/*===================================================*/ +/** + * @fn uint8_t RSI_UDMA_ErrorStatusGet(const RSI_UDMA_T *pUDMA) + * @brief This API is used to get the error status/sets the signal low of UDMA. + * @param[in] pUDMA : Pointer to the UDMA instance register area + * @return Returns error status as below + * - 0 : Error is LOW + * - 1 : Error is HIGH + */ +STATIC INLINE uint8_t RSI_UDMA_ErrorStatusGet(const RSI_UDMA_T *pUDMA) +{ + return (pUDMA->ERR_CLR_b.ERR_CLR); +} +/*===================================================*/ +/** + * @fn void RSI_UDMA_ErrorStatusClear(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to clear the errors of UDMA + * @param[in] pHandle : Pointer to driver context handle + * @return none + */ +STATIC INLINE void RSI_UDMA_ErrorStatusClear(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + pDrv->base->ERR_CLR_b.ERR_CLR = 0x1; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelEnable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh) + * @brief This API is used to enable the required channel of UDMA + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(1 to 32) + * @return RSI_OK if no errors occured, or an error code + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelEnable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + // Enables required channel + pDrv->base->CHNL_ENABLE_SET = SET_BIT(dmaCh); + return RSI_OK; + } else { + return ERROR_UDMA_INVALIDCHNLNUM; + } +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelDisable(RSI_UDMA_HANDLE_T pHandle,uint8_t dmaCh) + * @brief This API is used to disable the required channel of UDMA + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(1 to 32) + * @return RSI_OK if no errors occured, or an error code + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelDisable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + // Disables required channel + pDrv->base->CHNL_ENABLE_CLR = SET_BIT(dmaCh); + return RSI_OK; + } else + return ERROR_UDMA_INVALIDCHNLNUM; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelIsEnabled(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief This API is used to check the required UDMA channel is enabled or not + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(0 to 31) + * @return If process is successful then return RSI_OK else RSI_FAIL If requied channel is not enabled + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelIsEnabled(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + const RSI_UDMA_DATACONTEXT_T *pDrv = (const RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + if (((pDrv->base->CHNL_ENABLE_SET) & SET_BIT(dmaCh)) != 0) { + return RSI_OK; + } else { + return RSI_FAIL; + } + } else { + return ERROR_UDMA_INVALIDCHNLNUM; + } +} + +/*===================================================*/ +/** + * @fn void *RSI_UDMA_GetControlBaseAddress(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the UDMA control base address + * @param[in] pHandle : Pointer to driver context handle + * @return Control structure base pointer + */ +STATIC INLINE void *RSI_UDMA_GetControlBaseAddress(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + return ((void *)pDrv->base->CTRL_BASE_PTR); +} + +/*===================================================*/ +/** + * @fn void *RSI_UDMA_GetControlAlternateBase(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the required UDMA channel alternate control base + * @param[in] pHandle : Pointer to driver context handle + * @return Alternate control structure base pointer + */ +STATIC INLINE void *RSI_UDMA_GetControlAlternateBase(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + return ((void *)pDrv->base->ALT_CTRL_BASE_PTR); +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_ChannelSoftwareTrigger(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief This API is used to to generate a software UDMA request on the corresponding UDMA channel + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : channel number (0 to 31). + * @return return ERROR_UDMA_INVALID_ARG if channel is greater than 31 or channel is invalid , and on success return RSI_OK(0). + */ +STATIC INLINE rsi_error_t RSI_UDMA_ChannelSoftwareTrigger(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + pDrv->base->CHNL_SW_REQUEST |= SET_BIT(dmaCh); + return RSI_OK; + } else + return ERROR_UDMA_INVALIDCHNLNUM; +} + +/*===================================================*/ +/** + * @fn rsi_error_t RSI_UDMA_InterruptClear(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief This API is used to to generate a UDMA interrupt clear. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : channel number (0 to 31). + * @return return ERROR_UDMA_INVALID_ARG if channel is greater than 31 or channel is invalid , + * and on success return RSI_OK(0). + */ +STATIC INLINE rsi_error_t RSI_UDMA_InterruptClear(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + if (dmaCh <= CHNL_31) { + pDrv->base->UDMA_DONE_STATUS_REG = SET_BIT(dmaCh); + } else { + return ERROR_UDMA_INVALIDCHNLNUM; + } + return RSI_OK; +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_UDMA_InterruptStatus(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief Gets interrupt status of required channel. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(0 to 31),Possible values are as below + - \b 0 : Channel disable + - \b 1 : Channel enable + * @return Interrupt status of required channel + */ +STATIC INLINE uint32_t RSI_UDMA_InterruptStatus(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ + uint32_t intr_stat = 0; + const RSI_UDMA_DATACONTEXT_T *pDrv = (const RSI_UDMA_DATACONTEXT_T *)pHandle; + + intr_stat = pDrv->base->UDMA_DONE_STATUS_REG; + return (intr_stat & SET_BIT(dmaCh)); +} + +/*===================================================*/ +/** + * @fn uint8_t RSI_UDMA_GetControllerEnableStatus(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the enable status of controller + * @param[in] pHandle : Pointer to driver context handle + * @return If 1 controller is enabled ,if 0 controller is disabled + */ +STATIC INLINE uint8_t RSI_UDMA_GetControllerEnableStatus(RSI_UDMA_HANDLE_T pHandle) +{ + RSI_UDMA_DATACONTEXT_T *pDrv = (RSI_UDMA_DATACONTEXT_T *)pHandle; + return (pDrv->base->DMA_STATUS_b.MASTER_ENABLE); +} + +/*===================================================*/ +/** + * @fn uint32_t RSI_UDMA_GetControlState(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to get the current state of the control state machine + * @param[in] pHandle : Pointer to driver context handle + * @return returns state of the control state machine + possible values are as below + - 0000 = idle + - 0001 = reading channel controller data + - 0010 = reading source data end pointer + - 0011 = reading destination data end pointer + - 0100 = reading source data + - 0101 = writing destination data + - 0110 = waiting for DMA request to clear + - 0111 = writing channel controller data + - 1000 = stalled + - 1001 = done + - 1010 = peripheral scatter-gather transition + - 1011-1111 = undefined. + */ +STATIC INLINE uint32_t RSI_UDMA_GetControlState(RSI_UDMA_HANDLE_T pHandle) +{ + const RSI_UDMA_DATACONTEXT_T *pDrv = (const RSI_UDMA_DATACONTEXT_T *)pHandle; + return (pDrv->base->DMA_STATUS_b.STATE); +} + +// FUNCTION PROTOTYPES +RSI_DRIVER_VERSION_M4 RSI_UDMA_GetVersion(void); + +RSI_UDMA_CAPABILITIES_T RSI_UDMA_GetCapabilities(void); + +RSI_UDMA_HANDLE_T udma_init(void *mem, const RSI_UDMA_INIT_T *pInit); + +uint32_t udma_get_channel_transfer_mode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + +rsi_error_t udma_setup_channel_transfer(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, + void *pSrcAddr, + volatile void *pDstAddr); + +rsi_error_t udma_set_channel_scatter_gather_transfer(RSI_UDMA_HANDLE_T pHandle, + uint8_t dmaCh, + uint32_t taskCount, + void *pTaskList, + uint32_t transferType); + +uint32_t udma_get_channel_transfer_length(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); + +rsi_error_t udma_setup_channel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + +void udma_deInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + +void udma_interrupt_handler(RSI_UDMA_HANDLE_T pHandle); + +rsi_error_t udma_interrupt_enable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh); +rsi_error_t RSI_UDMA_ChannelControlsDisable(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); +void RSI_UDMA_SetSingleRequest(RSI_UDMA_HANDLE_T pHandle); +void RSI_UDMA_AckEnable(const void *pHandle, uint32_t peripheral); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_UDMA_H +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h new file mode 100644 index 000000000..1a5287d7d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc/rsi_udma_wrapper.h @@ -0,0 +1,90 @@ +/******************************************************************************* +* @file rsi_udma_wrapper.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +/**=========================================================================== + * @brief This files contains functions prototypes releated to UDMA peripheral + * @section Description : + * This file contains the list of function prototypes for the UDMA and low level function definations + * Following are list of API's which need to be defined in this file. +============================================================================**/ +// Include Files + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_packing.h" +#include "UDMA.h" + +#ifndef RSI_UDMA_WRAPPER_H +#define RSI_UDMA_WRAPPER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +typedef struct { + uint32_t SrcAddr; + uint32_t DestAddr; + uint32_t Size; + uint32_t Cnt; + UDMA_SignalEvent_t cb_event; +} UDMA_Channel_Info; + +RSI_UDMA_HANDLE_T uDMAx_Initialize(const UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T udmaHandle, + uint32_t *mem); +int32_t uDMAx_Uninitialize(const UDMA_RESOURCES *udma); +int32_t uDMAx_ChannelConfigure(const UDMA_RESOURCES *udma, + uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + RSI_UDMA_CHA_CONFIG_DATA_T control, + const RSI_UDMA_CHA_CFG_T *config, + UDMA_SignalEvent_t cb_event, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_ChannelEnable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_DMAEnable(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +int32_t uDMAx_ChannelDisable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); +uint32_t uDMAx_ChannelGetCount(uint8_t ch, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T config, + const UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); +void uDMAx_IRQHandler(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info); + +#ifdef __cplusplus +} +#endif + +#endif // RSI_UDMA_WRAPPER_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c new file mode 100644 index 000000000..cd88facee --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c @@ -0,0 +1,785 @@ +/****************************************************************************** +* @file clock_update.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +// Include Files + +#include "clock_update.h" +#include "rsi_pll.h" +#include "rsi_power_save.h" +#include "rsi_ulpss_clk.h" + +#ifdef __SYSTICK +volatile uint32_t _dwTickCount = 0; + +/** @addtogroup SOC2 +* @{ +*/ +/*==============================================*/ +/** + * @fn void SysTick_Handler(void) + * @brief Systic handler use for generation delay for XTAL clock enable + * @return None + */ +void SysTick_Handler(void) +{ + _dwTickCount++; +} + +/*==============================================*/ +/** + * @fn uint32_t GetTickCount(void) + * @brief Get tick count. + * @return return the count of tick. + */ +uint32_t GetTickCount(void) +{ + /*gets the tick count from systic ISR */ + return _dwTickCount; +} + +/*==============================================*/ +/** + * @fn void rsi_delay_ms(uint32_t val) + * @brief This callback function for generation delay for XTAL clock. + * @param[in] Number of delay in us. + * @return None. + */ +void rsi_delay_ms(uint32_t val) +{ + uint32_t start = 0; + + start = GetTickCount(); + do { + } while (GetTickCount() - start < val); + + return; +} +#endif +// It will gets the clock of each peripheral + +/*==============================================*/ +/** + * @fn uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) + * @brief gets the clock of each peripheral + * @param[in] peri_src + * @return src_clk + */ +uint32_t RSI_CLK_GetBaseClock(PERI_CLKS_T peri_src) +{ + uint32_t src_clk_mux = 0; + uint32_t src_clk = 0; + uint32_t div_fac = 0; + uint32_t swallow_val = 0; + uint32_t odd_div = 0; + switch (peri_src) { + case M4_USART0: + // Read the ULP UART clock mux + src_clk_mux = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL; + switch (src_clk_mux) { + case USART_ULPREFCLK: + switch (system_clocks.m4_ref_clock_source) { + case ULPSS_REF_BYP_CLK: + src_clk = system_clocks.byp_rc_ref_clock; + break; + case ULPSS_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_40MHZ_CLK: + src_clk = system_clocks.rf_ref_clock; + break; + case ULPSS_MEMS_REF_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_ULP_20MHZ_RINGOSC_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULPSS_ULP_DOUBLER_CLK: + src_clk = system_clocks.doubler_clock; + break; + default: + break; + } + break; + case USART_MODELPLLCLK2: + src_clk = system_clocks.modem_pll_clock2; + break; + case USART_INTFPLLCLK: + src_clk = system_clocks.intf_pll_clock; + break; + case USART_SOCPLLCLK: + src_clk = system_clocks.soc_pll_clock; + break; + case M4_SOCCLKFOROTHERCLOCKS: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + div_fac = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC; + swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL; + if (swallow_val) { + if (div_fac == 0) { + break; // Clock is gated + } else { + src_clk = (uint32_t)(src_clk / (div_fac + 0.5)); + } + } else { + if (div_fac == 0) { + return src_clk; //divider bypassed + } else { + src_clk = src_clk / div_fac; + } + } + break; + + case M4_UART1: + src_clk_mux = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL; + switch (src_clk_mux) { + case USART_ULPREFCLK: + switch (system_clocks.m4_ref_clock_source) { + case ULPSS_REF_BYP_CLK: + src_clk = system_clocks.byp_rc_ref_clock; + break; + case ULPSS_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_40MHZ_CLK: + src_clk = system_clocks.rf_ref_clock; + break; + case ULPSS_MEMS_REF_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_ULP_20MHZ_RINGOSC_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULPSS_ULP_DOUBLER_CLK: + src_clk = system_clocks.doubler_clock; + break; + default: + break; + } + break; + case USART_MODELPLLCLK2: + src_clk = system_clocks.modem_pll_clock2; + break; + case USART_INTFPLLCLK: + src_clk = system_clocks.intf_pll_clock; + break; + case USART_SOCPLLCLK: + src_clk = system_clocks.soc_pll_clock; + break; + case M4_SOCCLKFOROTHERCLOCKS: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + div_fac = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC; + swallow_val = M4CLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL; + if (swallow_val) { + if (div_fac == 0) { + break; // Clock is gated + } else { + src_clk = (uint32_t)(src_clk / (div_fac + 0.5)); + } + } else { + if (div_fac == 0) { + return src_clk; //divider bypassed + } else { + src_clk = src_clk / div_fac; + } + } + break; + + case M4_SSI_MST: + src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL; + switch (src_clk_mux) { + case SSI_ULPREFCLK: + switch (system_clocks.m4_ref_clock_source) { + case ULPSS_REF_BYP_CLK: + src_clk = system_clocks.byp_rc_ref_clock; + break; + case ULPSS_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_40MHZ_CLK: + src_clk = system_clocks.rf_ref_clock; + break; + case ULPSS_MEMS_REF_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_ULP_20MHZ_RINGOSC_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULPSS_ULP_DOUBLER_CLK: + src_clk = system_clocks.doubler_clock; + break; + default: + break; + } + break; + case SSI_SOCPLLCLK: + src_clk = system_clocks.soc_pll_clock; + break; + case SSI_MODEMPLLCLK1: + src_clk = system_clocks.modem_pll_clock; + break; + case SSI_INTFPLLCLK: + src_clk = system_clocks.intf_pll_clock; + break; + case SSI_MODELPLLCLK2: + src_clk = system_clocks.modem_pll_clock2; + break; + case M4_SOCCLKFOROTHERCLKS: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + div_fac = (M4CLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + break; + + case M4_CT: + src_clk_mux = M4CLK->CLK_CONFIG_REG5_b.CT_CLK_SEL; + switch (src_clk_mux) { + case CT_ULPREFCLK: + switch (system_clocks.m4_ref_clock_source) { + case ULPSS_REF_BYP_CLK: + src_clk = system_clocks.byp_rc_ref_clock; + break; + case ULPSS_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_40MHZ_CLK: + src_clk = system_clocks.rf_ref_clock; + break; + case ULPSS_MEMS_REF_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_ULP_20MHZ_RINGOSC_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULPSS_ULP_DOUBLER_CLK: + src_clk = system_clocks.doubler_clock; + break; + default: + break; + } + break; + case CT_INTFPLLCLK: + src_clk = system_clocks.intf_pll_clock; + break; + case CT_SOCPLLCLK: + src_clk = system_clocks.soc_pll_clock; + break; + case M4_SOCCLKFOROTHERCLKSCT: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + div_fac = (M4CLK->CLK_CONFIG_REG5_b.CT_CLK_DIV_FAC); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / (2 * div_fac)); + } + break; +#if !defined(SLI_SI917) && !defined(SLI_SI915) + case M4_SD_MEM: + src_clk_mux = M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL; + switch (src_clk_mux) { + case SDMEM_SOCPLLCLK: + src_clk = system_clocks.soc_pll_clock; + break; + case SDMEM_MODEMPLLCLK1: + src_clk = system_clocks.modem_pll_clock2; + break; + case SDMEM_INTFPLLCLK: + src_clk = system_clocks.intf_pll_clock; + break; + case M4_SOCCLKFOROTHERCLKSSDMEM: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + swallow_val = M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL; + div_fac = (M4CLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_DIV_FAC); + if (swallow_val) { + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + } else { + if (div_fac == 0) { + src_clk = (src_clk / 2); //divider bypassed + } else { + src_clk = (src_clk / (2 * div_fac)); + } + } + break; + + case M4_CCI: + src_clk_mux = M4CLK->CLK_CONFIG_REG4_b.CCI_CLK_SEL; + switch (src_clk_mux) { + case CCI_M4_SOC_CLK_FOR_OTHER_CLKS: + src_clk = system_clocks.soc_clock; + break; + case CCI_INTF_PLL_CLK: + src_clk = system_clocks.intf_pll_clock; + break; + default: + break; + } + div_fac = (M4CLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / (2 * div_fac)); + } + break; +#endif + case M4_QSPI: + src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL; + switch (src_clk_mux) { + case QSPI_ULPREFCLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case QSPI_MODELPLLCLK2: + src_clk = system_clocks.modem_pll_clock2; + break; + case QSPI_INTFPLLCLK: + src_clk = system_clocks.intf_pll_clock; + break; + case QSPI_SOCPLLCLK: + src_clk = system_clocks.soc_pll_clock; + break; + case M4_SOCCLKNOSWLSYNCCLKTREEGATED: + break; + default: + break; + } + swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); + div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); + odd_div = (M4CLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL); + if (swallow_val) { + if (odd_div == 0) { + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + } else { + if ((div_fac % 2 != 0) && (div_fac >= 3)) { + src_clk = (src_clk / div_fac); + } else { + break; //clock gated + } + } + } else { + if (odd_div == 0) { + if (div_fac == 0) { + src_clk = (src_clk / 2); + } else { + src_clk = (src_clk / (2 * div_fac)); + } + } else { + if ((div_fac % 2 != 0) && (div_fac >= 3)) { + src_clk = (src_clk / div_fac); + } else { + break; //clock gated + } + } + } + break; + + case M4_QSPI2: + src_clk_mux = M4CLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL; + switch (src_clk_mux) { + case QSPI_ULPREFCLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case QSPI_MODELPLLCLK2: + src_clk = system_clocks.modem_pll_clock2; + break; + case QSPI_INTFPLLCLK: + src_clk = system_clocks.intf_pll_clock; + break; + case QSPI_SOCPLLCLK: + src_clk = system_clocks.soc_pll_clock; + break; + case M4_SOCCLKNOSWLSYNCCLKTREEGATED: + break; + default: + break; + } + swallow_val = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL); + div_fac = (M4CLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC); + odd_div = (M4CLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL); + if (swallow_val) { + if (odd_div == 0) { + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + } else { + if ((div_fac % 2 != 0) && (div_fac >= 3)) { + src_clk = (src_clk / div_fac); + } else { + break; //clock gated + } + } + } else { + if (odd_div == 0) { + if (div_fac == 0) { + src_clk = (src_clk / 2); + } else { + src_clk = (src_clk / (2 * div_fac)); + } + } else { + if ((div_fac % 2 != 0) && (div_fac >= 3)) { + src_clk = (src_clk / div_fac); + } else { + break; //clock gated + } + } + } + break; + + case M4_GSPI: + src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL; + switch (src_clk_mux) { + case GSPI_M4_SOC_CLK_FOR_OTHER_CLKS: + src_clk = system_clocks.soc_clock; + break; + case GSPI_ULP_REF_CLK: + switch (system_clocks.m4_ref_clock_source) { + case ULPSS_REF_BYP_CLK: + src_clk = system_clocks.byp_rc_ref_clock; + break; + case ULPSS_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_40MHZ_CLK: + src_clk = system_clocks.rf_ref_clock; + break; + case ULPSS_MEMS_REF_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULPSS_ULP_20MHZ_RINGOSC_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULPSS_ULP_DOUBLER_CLK: + src_clk = system_clocks.doubler_clock; + break; + default: + break; + } + break; + case GSPI_SOC_PLL_CLK: + src_clk = system_clocks.soc_pll_clock; + break; + case GSPI_MODEM_PLL_CLK2: + src_clk = system_clocks.modem_pll_clock2; + break; + case GSPI_INTF_PLL_CLK: + src_clk = system_clocks.intf_pll_clock; + break; + default: + break; + } + break; + + case M4_ETHERNET: + src_clk_mux = M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SEL; + switch (src_clk_mux) { + case ETH_INTF_PLL_CLK: + src_clk = system_clocks.intf_pll_clock; + break; + case ETH_SOC_PLL_CLK: + src_clk = system_clocks.soc_pll_clock; + break; + default: + break; + } + + div_fac = (M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_DIV_FAC); + swallow_val = (M4CLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SWALLOW_SEL); + if (swallow_val) { + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + } else { + if (div_fac == 0) { + src_clk = (src_clk / 2); //divider bypassed + } else { + src_clk = (src_clk / (2 * div_fac)); + } + } + break; + + case M4_I2SM: + src_clk_mux = M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL; + switch (src_clk_mux) { + case I2S_PLLCLK: + src_clk = system_clocks.i2s_pll_clock; + break; + case I2S_M4SOCCLKFOROTHERS: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + div_fac = (M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_DIV_FAC); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / (2 * div_fac)); + } + break; + + case ULPSS_SSI: + src_clk_mux = ULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL; + switch (src_clk_mux) { + case ULP_SSI_REF_CLK: + src_clk = system_clocks.ulpss_ref_clk; + break; + case ULP_SSI_ULP_32KHZ_RO_CLK: + src_clk = system_clocks.ro_32khz_clock; + break; + case ULP_SSI_ULP_32KHZ_RC_CLK: + src_clk = system_clocks.rc_32khz_clock; + break; + case ULP_SSI_ULP_32KHZ_XTAL_CLK: + src_clk = system_clocks.xtal_32khz_clock; + break; + case ULP_SSI_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULP_SSI_ULP_20MHZ_RO_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULP_SSI_SOC_CLK: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + div_fac = (ULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_DIV_FACTOR); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + break; + + case ULPSS_I2S: + src_clk_mux = ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b; + switch (src_clk_mux) { + case ULP_I2S_REF_CLK: + src_clk = system_clocks.ulpss_ref_clk; + break; + case ULP_I2S_ULP_32KHZ_RO_CLK: + src_clk = system_clocks.ro_32khz_clock; + break; + case ULP_I2S_ULP_32KHZ_RC_CLK: + src_clk = system_clocks.rc_32khz_clock; + break; + case ULP_I2S_ULP_32KHZ_XTAL_CLK: + src_clk = system_clocks.xtal_32khz_clock; + break; + case ULP_I2S_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULP_I2S_ULP_20MHZ_RO_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + default: + break; + } + div_fac = (ULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLKDIV_FACTOR); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / (2 * div_fac)); + } + break; + + case ULPSS_UART: + src_clk_mux = ULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL; + switch (src_clk_mux) { + case ULP_UART_REF_CLK: + src_clk = system_clocks.ulpss_ref_clk; + break; + case ULP_UART_ULP_32KHZ_RO_CLK: + src_clk = system_clocks.ro_32khz_clock; + break; + case ULP_UART_ULP_32KHZ_RC_CLK: + src_clk = system_clocks.rc_32khz_clock; + break; + case ULP_UART_ULP_32KHZ_XTAL_CLK: + src_clk = system_clocks.xtal_32khz_clock; + break; + case ULP_UART_ULP_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULP_UART_ULP_20MHZ_RO_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULP_UART_SOC_CLK: + src_clk = system_clocks.soc_clock; + break; + case ULP_UART_ULP_DOUBLER_CLK: + src_clk = system_clocks.doubler_clock; + break; + default: + break; + } + div_fac = (ULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLKDIV_FACTOR); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + break; + + case ULPSS_TIMER: + src_clk_mux = ULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL; + switch (src_clk_mux) { + case ULP_TIMER_REF_CLK: + src_clk = system_clocks.ulpss_ref_clk; + break; + case ULP_TIMER_32KHZ_RO_CLK: + src_clk = system_clocks.ro_32khz_clock; + break; + case ULP_TIMER_32KHZ_RC_CLK: + src_clk = system_clocks.rc_32khz_clock; + break; + case ULP_TIMER_32KHZ_XTAL_CLK: + src_clk = system_clocks.xtal_32khz_clock; + break; + case ULP_TIMER_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULP_TIMER_20MHZ_RO_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULP_TIMER_ULP_SOC_CLK: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + //no division factor + break; + + case ULPSS_AUX: + src_clk_mux = ULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL; + switch (src_clk_mux) { + case ULP_AUX_REF_CLK: + src_clk = system_clocks.ulpss_ref_clk; + break; + case ULP_AUX_32KHZ_RO_CLK: + src_clk = system_clocks.ro_32khz_clock; + break; + case ULP_AUX_32KHZ_RC_CLK: + src_clk = system_clocks.rc_32khz_clock; + break; + case ULP_AUX_32KHZ_XTAL_CLK: + src_clk = system_clocks.xtal_32khz_clock; + break; + case ULP_AUX_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULP_AUX_20MHZ_RO_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULP_AUX_ULP_SOC_CLK: + src_clk = system_clocks.soc_clock; + break; + case ULP_AUX_ULP_DOUBLER_CLK: + src_clk = system_clocks.doubler_clock; + break; + case ULP_AUX_I2S_PLL_CLK: + src_clk = system_clocks.i2s_pll_clock; + break; + default: + break; + } + //no division factor + break; + + case ULPSS_TOUCH: + src_clk_mux = ULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL; + switch (src_clk_mux) { + case ULP_TOUCH_REF_CLK: + src_clk = system_clocks.ulpss_ref_clk; + break; + case ULP_TOUCH_32KHZ_RO_CLK: + src_clk = system_clocks.ro_32khz_clock; + break; + case ULP_TOUCH_32KHZ_RC_CLK: + src_clk = system_clocks.rc_32khz_clock; + break; + case ULP_TOUCH_32KHZ_XTAL_CLK: + src_clk = system_clocks.xtal_32khz_clock; + break; + case ULP_TOUCH_MHZ_RC_CLK: + src_clk = system_clocks.rc_mhz_clock; + break; + case ULP_TOUCH_20MHZ_RO_CLK: + src_clk = system_clocks.ro_20mhz_clock; + break; + case ULP_TOUCH_ULP_SOC_CLK: + src_clk = system_clocks.soc_clock; + break; + default: + break; + } + div_fac = (ULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLKDIV_FACTOR); + if (div_fac == 0) { + return src_clk; + } else { + src_clk = (src_clk / div_fac); + } + break; + } + return src_clk; +} +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_rng.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_rng.c new file mode 100644 index 000000000..d4ebf5975 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_rng.c @@ -0,0 +1,133 @@ +/****************************************************************************** +* @file rsi_rng.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +// Include Files + +#include "rsi_rom_rng.h" + +/*==============================================*/ +/** + * @fn uint32_t rng_start(HWRNG_Type *pRNG, uint8_t rngMode) + * @brief This API is used to start the Random Number Generation + * @param[in] pRNG : pointer to the control register + * @param[in] rngMode : mode of random number generation + * @return return RSI_OK if successful execution + */ +uint32_t rng_start(HWRNG_Type *pRNG, uint8_t rngMode) +{ + if (rngMode == 0 || rngMode == 1) { + if (rngMode == RSI_RNG_TRUE_RANDOM) { + pRNG->HWRNG_CTRL_REG_b.HWRNG_RNG_ST = 1; + pRNG->HWRNG_CTRL_REG_b.HWRNG_PRBS_ST = 0; + } else { + pRNG->HWRNG_CTRL_REG_b.HWRNG_PRBS_ST = 1; + pRNG->HWRNG_CTRL_REG_b.HWRNG_RNG_ST = 0; + } + } else { + return ERROR_RNG_INVALID_ARG; + } + return RSI_OK; +} + +void rng_config_lfsr(HWRNG_Type *pRNG, rng_lfsr_config_t lfsr_config_param) +{ + pRNG->HWRNG_CTRL_REG_b.TAP_LFSR_INPUT = lfsr_config_param; +} + +/*==============================================*/ +/** + * @fn void rng_stop(HWRNG_Type *pRNG) + * @brief This API is used to stop the Random Number Generation + * @param[in] pRNG : pointer to the control register + * @return none + */ +void rng_stop(HWRNG_Type *pRNG) +{ + //Disabling pseudo random number and true number generation bit. + pRNG->HWRNG_CTRL_REG_b.HWRNG_PRBS_ST = 0; + pRNG->HWRNG_CTRL_REG_b.HWRNG_RNG_ST = 0; +} + +/***************************************************************************/ +/** + * @brief + * Read random data from the HRNG using the LFSR input latch. + * + * @details + * This function reads random data from the HRNG using the LFSR input latch register. + * The data is valid only when the LFSR_32_BIT_INPUT_VALID bit is set. After reading + * the data from the LFSR_INPUT_LATCH_REG, the LFSR_32_BIT_INPUT_VALID bit will be + * cleared by hardware. + * + * @param[in] pRNG : Pointer to the control register of the hardware random number generator. + * @param[out] randomBytes : Pointer to an array where the random data will be stored. + * @param[in] numberOfBytes : Number of bytes of random data to read. + * + * @return + * - RSI_OK on success. + * - RSI_FAIL if the LFSR_32_BIT_INPUT_VALID bit is not set or if the TAP_LFSR_INPUT bit is not set. + ******************************************************************************/ +uint32_t rng_read_lfsr_input(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes) +{ + uint32_t status = RSI_FAIL, i; + if (pRNG->HWRNG_CTRL_REG_b.TAP_LFSR_INPUT == 1) { + for (i = 0; i < numberOfBytes; i++) { + // Check if LFSR input data is valid + if (pRNG->HWRNG_CTRL_REG_b.LFSR_32_BIT_INPUT_VALID != 0) { + // Read from HWRNG_LFSR_INPUT_LATCH_REG + randomBytes[i] = pRNG->HWRNG_LFSR_INPUT_LATCH_REG_REG_b.HWRNG_LFSR_INPUT_LATCH_REG; + status = RSI_OK; + } else { + status = RSI_FAIL; + return status; + } + } + } else { + status = RSI_FAIL; + } + return status; +} +/*==============================================*/ +/** + * @fn void rng_get_bytes(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes) + * @brief This API is used to get the random number bytes + * @param[in] pRNG : pointer to the control register + * @param[in] randomBytes : random number register + * @param[in] numberOfBytes : number of bytes + * @return none + */ +void rng_get_bytes(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes) +{ + uint32_t i; + + for (i = 0; i < numberOfBytes; i++) { + randomBytes[i] = pRNG->HWRNG_RAND_NUM_REG; + } +} +const ROM_RNG_API_T rng_api = { &rng_start, &rng_stop, &rng_get_bytes }; diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h new file mode 100644 index 000000000..7a6e628b1 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_packing.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* @file rsi_packing.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#ifndef __PACKING_H_ +#define __PACKING_H_ + +#define PRE_PACK /* Nothing */ +#define POST_PACK /* Nothing */ +#ifndef ALIGNED +#define ALIGNED(n) /* Nothing */ +#endif + +#endif /* __PACKING_H_ */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h new file mode 100644 index 000000000..09e964e65 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_clks.h @@ -0,0 +1,1709 @@ +/****************************************************************************** +* @file rsi_rom_clks.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +//Includes + +/** + * @defgroup RSI_SPECIFIC_DRIVERS SoC Device-Specific Drivers + * @ingroup SOC + * @section Description + * RSI specific drivers are unique to a specific device. RSI specific drivers may use an IP driver as it's base driver or a custom implementation if that + * peripheral or IP on the chip is unique (ie, clocking) + */ + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + */ + +/** + * \defgroup RSI_CHIP_CLOCK_DRIVERS + * @{ + * + */ + +/** + * \defgroup RSI_M4SS_CLOCK_DRIVERS M4SS CLOCK + * @{ + * + */ + +#ifndef __RSI_ROM_CLK_H_ +#define __RSI_ROM_CLK_H_ + +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif + +#if SL_WIFI_COMPONENT_INCLUDED +#include "sl_rsi_utility.h" +#include "rsi_m4.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @fn STATIC INLINE boolean_t RSI_CLK_CheckPllLock(PLL_TYPE_T pllType) + * @brief This API is used to check the lock status of pll + * @param[in] pllType : To select the soc_pll, intf_pll and i2s_pll. See # PLL_TYPE_T for more info + * \n structure member is below. + * - SOC_PLL : soc_pll clk + * - INTF_PLL : intf_pll clk + * - I2S_PLL : i2s_pll clk + * @return return 1 then for lock status high(enable) and return 0 then for lock status low(disable) + * + */ +STATIC INLINE boolean_t RSI_CLK_CheckPllLock(PLL_TYPE_T pllType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_check_pll_lock(pllType); +#else + return clk_check_pll_lock(pllType); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable) + * @brief This API is used to enable the SoC-PLL output clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable : Enables clock + * - Disable : Disables clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_enable(clkEnable); +#else + return clk_soc_pll_clk_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() + * @brief This API is used to TurnOn the SOC_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOn() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_on(); +#else + return clk_soc_pll_turn_on(); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(const M4CLK_Type *pCLK,uint32_t socPllFreq,uint32_t pllRefClk) + * @brief This API is used to set the Soc PLL clock to particular frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] socPllFreq : Frequency value in Mhz for Soc_Pll_Clk . + * @param[in] pllRefClk : Frequency value in Mhz for Reference clk. Please refer # NOTE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported + */ +STATIC INLINE rsi_error_t RSI_CLK_SetSocPllFreq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) +{ + rsi_error_t ret = (rsi_error_t)0; + system_clocks.soc_pll_clock = socPllFreq; + + /* TurnON the SOC_PLL */ + RSI_CLK_SocPllTurnOn(); + if (pllRefClk == XTAL_CLK_FREQ) //avoid if XTAL req is already done + { +#if SL_WIFI_COMPONENT_INCLUDED + /* Notify NWP that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); +#endif + PLL_REF_CLK_CONFIG_REG &= SELECT_XTAL_MHZ_CLOCK; // Selecting the XTAL as PLL reference clock + } + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = 0xD900; +#if defined(CLOCK_ROMDRIVER_PRESENT) + ret = ROMAPI_M4SS_CLK_API->clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk); +#else + + ret = clk_set_soc_pll_freq(pCLK, socPllFreq, pllRefClk); +#endif + if (ret != RSI_OK) { + return ret; + } else { + socPllFreq /= 1000000; + /*if SOC PLL frequency is greater than 90Mhz */ + if (socPllFreq < 90) { + /* Change the power state from PS4 to PS3 */ + RSI_PS_PowerStateChangePs4toPs3(); + /* Configure DCDC to give lower output voltage */ + RSI_PS_SetDcDcToLowerVoltage(); + } + if ((socPllFreq > 90) && (!(BATT_FF->MCU_PMU_LDO_CTRL_CLEAR & MCU_SOC_LDO_LVL))) { + /* Change the power state from PS3 to PS4 */ + RSI_PS_SetDcDcToHigerVoltage(); + /* Configure DCDC to give higher output voltage.*/ + RSI_PS_PowerStateChangePs3toPs4(); + } + } + return RSI_OK; +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type *pCLK , boolean_t clk_en,uint16_t + * divFactor,uint16_t nFactor,uint16_t mFactor,uint16_t fCwf, + * uint16_t dcofixsel,uint16_t ldoprog) + * @brief This API is used to configure the SOC PLL clock frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clk_en : To enable the soc_pll_clk output enable + * @param[in] divFactor : PLL post division factor + * @param[in] nFactor : N factor of PLL + * @param[in] mFactor : M factor of PLL + * @param[in] fCwf : Fractional Frequency Control Word. For below 200MHz fcwF is 0 and above 200Mhz if the frequency is odd program FCW_F as 8192 + * @param[in] dcofixsel : Dco Fixed Ring select. Please refer # Note + * @param[in] ldoprog : SOCPLL LDO output voltage select. Please refer # Note + * @return returns zero \ref RSI_OK (0) on success ,on failure return error code. + * @note For <= 200Mhz ---> ldo_prog =4 and dco_fix_sel=1 + * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0 + * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2 + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllSetFreqDiv(const M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fCwf, + uint16_t dcofixsel, + uint16_t ldoprog) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API + ->clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog); +#else + return clk_soc_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fCwf, dcofixsel, ldoprog); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(const M4CLK_Type *pCLK) + * @brief This API is used to Enables the SoC-PLL + * @param[in] pCLK : Pointer to the pll register instance + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkSet(const M4CLK_Type *pCLK) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_set(pCLK); +#else + return clk_soc_pll_clk_set(pCLK); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkBypassEnable(boolean_t clkEnable) + * @brief This API is used to enable bypass clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable (1) : Enables bypass clock + * - Disable (0) : Disables bypass clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkBypassEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_bypass_enable(clkEnable); +#else + return clk_soc_pll_clk_bypass_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllClkReset() + * @brief This API is used to Reset the Soc_pll_clk + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllClkReset() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_clk_reset(); +#else + return clk_soc_pll_clk_reset(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllPdEnable(boolean_t en) + * @brief This API is used to enable the PdEnable(power down) + * @param[in] en : Enable or disable the PdEnable + * - Enable : Enables bypass clock + * - Disable : Disables bypass clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllPdEnable(boolean_t en) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_pd_enable(en); +#else + return clk_soc_pll_pd_enable(en); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOff() + * @brief This API is used to TurnOff the SOC_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SocPllTurnOff() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_soc_pll_turn_off(); +#else + return clk_soc_pll_turn_off(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkEnable(boolean_t clkEnable) + * @brief This API is used to enable the I2s_PLL output clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable(1) : Enables clock for i2s + * - Disable(0) : Disables clock for i2s + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_enable(clkEnable); +#else + return clk_i2s_pll_clk_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkBypassEnable(boolean_t clkEnable) + * @brief This API is used to enable bypass clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable : Enables bypass clock for i2s + * - Disable : Disables bypass clock for i2s + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkBypassEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_bypass_enable(clkEnable); +#else + return clk_i2s_pll_clk_bypass_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllPdEnable(boolean_t en) + * @brief This API is used to enable the PdEnable(power down) + * @param[in] en : Enable or disable the PdEnable + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllPdEnable(boolean_t en) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_pd_enable(en); +#else + return clk_i2s_pll_pd_enable(en); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOff() + * @brief This API is used to TurnOff the I2s_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOff() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_turn_off(); +#else + return clk_i2s_pll_turn_off(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOn() + * @brief This API is used to TurnOn the I2s_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllTurnOn() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_turn_on(); +#else + return clk_i2s_pll_turn_on(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(const M4CLK_Type *pCLK,uint32_t i2sPllFreq, uint32_t fXtal) + * @brief This API is used to set the I2s_pll clock to particular frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] i2sPllFreq : Frequency value in Mhz for I2S_PLL Clk . + * @param[in] fXtal : Frequency value in Mhz for crystal oscillator frequency. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SetI2sPllFreq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) +{ + system_clocks.i2s_pll_clock = i2sPllFreq; + /* TurnON the I2S_PLL */ + RSI_CLK_I2sPllTurnOn(); +#if SL_WIFI_COMPONENT_INCLUDED + /* Notify NWP that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); +#endif + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG9) = 0xD900; +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_set_i2s_pll_freq(pCLK, i2sPllFreq, fXtal); +#else + return clk_set_i2s_pll_freq(pCLK, i2sPllFreq, fXtal); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(const M4CLK_Type *pCLK,uint16_t u16DivFactor1, + * uint16_t u16DivFactor2,uint16_t nFactor,uint16_t mFactor, + * uint16_t fcwF) + * @brief This API is used to divide I2s_PLL Clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] u16DivFactor1 : Post Division factor1. See user manual for more info. + * @param[in] u16DivFactor2 : Post Division factor2. See user manual for more info. + * @param[in] nFactor : N factor for PLL. See user manual for more info. + * @param[in] mFactor : M factor for PLL. See user manual for more info. + * @param[in] fcwF : Fractional Frequency Control Word. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllSetFreqDiv(const M4CLK_Type *pCLK, + uint16_t u16DivFactor1, + uint16_t u16DivFactor2, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_set_freq_div(pCLK, u16DivFactor1, u16DivFactor2, nFactor, mFactor, fcwF); +#else + return clk_i2s_pll_set_freq_div(pCLK, u16DivFactor1, u16DivFactor2, nFactor, mFactor, fcwF); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(const M4CLK_Type *pCLK) + * @brief This API is used to set the I2s_pll_clk + * @param[in] pCLK : Pointer to the pll register instance + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkSet(const M4CLK_Type *pCLK) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_set(pCLK); +#else + return clk_i2s_pll_clk_set(pCLK); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkReset() + * @brief This API is used to reset the I2s_pll_clk + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sPllClkReset() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_pll_clk_reset(); +#else + return clk_i2s_pll_clk_reset(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkEnable(boolean_t clkEnable) + * @brief This API is used to enable the Intf_PLL output clock + * @param[in] clkEnable : Enum value to enable or disable the clock + * - Enable(1) : Enables clock + * - Disable(0) : Disables clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_enable(clkEnable); +#else + return clk_intf_pll_clk_enable(clkEnable); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllPdEnable(boolean_t en) + * @brief This API is used to enable the PdEnable(power down) + * @param[in] en : Enable or disable the PdEnable + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllPdEnable(boolean_t en) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_pd_enable(en); +#else + return clk_intf_pll_pd_enable(en); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff() + * @brief This API is used to TurnOff the Intf_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOff() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_turn_off(); +#else + return clk_intf_pll_turn_off(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOn() + * @brief This API is used to TurnOn the Intf_PLL + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPLLTurnOn() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_turn_on(); +#else + return clk_intf_pll_turn_on(); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(const M4CLK_Type *pCLK,uint32_t intfPllFreq,uint32_t pllRefClk) + * @brief This API is used to set the INTFPLL clock to particular frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] intfPllFreq : Frequency value in Mhz for INTFPLL Clk . + * @param[in] pllRefClk : Frequency value in Mhz for Reference clk. Please refer # NOTE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note Only 1Mhz steps applicable to the this API, 0.96Mhz steps are not supported + */ +STATIC INLINE rsi_error_t RSI_CLK_SetIntfPllFreq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) +{ + rsi_error_t error = (rsi_error_t)0; + system_clocks.intf_pll_clock = intfPllFreq; + /* TurnON the INTF_PLL */ + RSI_CLK_IntfPLLTurnOn(); + +#if SL_WIFI_COMPONENT_INCLUDED + if (pllRefClk == XTAL_CLK_FREQ) //avoid if XTAL req is already done + { + /* Notify NWP that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); + PLL_REF_CLK_CONFIG_REG &= SELECT_XTAL_MHZ_CLOCK; // Selecting the XTAL as PLL reference clock + } +#endif + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG9) = 0xD900; +#if defined(CLOCK_ROMDRIVER_PRESENT) + error = ROMAPI_M4SS_CLK_API->clk_set_intf_pll_freq(pCLK, intfPllFreq, pllRefClk); +#else + error = clk_set_intf_pll_freq(pCLK, intfPllFreq, pllRefClk); +#endif + if (error != RSI_OK) { + return error; + } else { + /*if SOC PLL frequency is greater than 90Mhz */ + if (intfPllFreq < 90) { + /* Change the power state from PS4 to PS3 */ + RSI_PS_PowerStateChangePs4toPs3(); + /* Configure DCDC to give lower output voltage */ + RSI_PS_SetDcDcToLowerVoltage(); + } + if ((intfPllFreq > 90) && (!(BATT_FF->MCU_PMU_LDO_CTRL_CLEAR & MCU_SOC_LDO_LVL))) { + /* Change the power state from PS3 to PS4 */ + RSI_PS_SetDcDcToHigerVoltage(); + /* Configure DCDC to give higher output voltage.*/ + RSI_PS_PowerStateChangePs3toPs4(); + } + } + return RSI_OK; +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(const M4CLK_Type *pCLK , boolean_t clk_en, + * uint16_t divFactor,uint16_t nFactor,uint16_t mFactor, + * uint16_t fcwF,uint16_t dcoFixSel,uint16_t ldoProg) + * @brief This API is used to divide the Intf PLL clock frequency + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clk_en : Enble the intf_pll_clk output enale + * @param[in] divFactor : PLL post division factor ,see user for more info + * @param[in] nFactor : N factor of PLL , see user manual for more info + * @param[in] mFactor : M factor of PLL , see user manual for more info + * @param[in] fcwF : Fractional Frequency Control Word. For below 200MHz fcwF is 0 and above 200Mhz if the frequency is odd program FCW_F as 8192 + * @param[in] dcoFixSel : Dco Fixed Ring select. Please refer # Note + * @param[in] ldoProg : INTFPLL LDO output voltage select. Please refer # Note + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For <= 200Mhz ---> ldo_prog =4 and dco_fix_sel=1 + * - For 201-250Mhz ---> ldo_prog =5 and dco_fix_sel=0 + * - For >=251Mhz ---> ldo_prog =5 and dco_fix_sel=2 + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllSetFreqDiv(const M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API + ->clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoProg); +#else + return clk_intf_pll_set_freq_div(pCLK, clk_en, divFactor, nFactor, mFactor, fcwF, dcoFixSel, ldoProg); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPLLClkBypassEnable(boolean_t clkEnable) + * @brief This API is used to enable bypass clock + * @param[in] clkEnable : is enum value to enable or disable the clock + * - Enable : Enables bypass clock + * - Disable : Disables bypass clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPLLClkBypassEnable(boolean_t clkEnable) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_bypass_enable(clkEnable); +#else + return clk_intf_pll_clk_bypass_enable(clkEnable); +#endif +} + +/** + + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkReset() + * @brief This API is used to Reset the Intf_pll_clk + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkReset() +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_reset(); +#else + return clk_intf_pll_clk_reset(); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(const M4CLK_Type *pCLK) + * @brief This API is used to Enables the Intf-PLL + * @param[in] pCLK : Pointer to the pll register instance + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_IntfPllClkSet(const M4CLK_Type *pCLK) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_intf_pll_clk_set(pCLK); +#else + return clk_intf_pll_clk_set(pCLK); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable1(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the peripheral clocks for SET1 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enbled. + * - \ref USART1_PCLK_ENABLE + * - \ref USART1_SCLK_ENABLE + * - \ref USART2_PCLK_ENABLE + * - \ref USART2_SCLK_ENABLE + * - \ref CT_CLK_ENABLE + * - \ref CT_PCLK_ENABLE + * - \ref ICACHE_CLK_ENABLE + * - \ref ICACHE_CLK_2X_ENABLE + * - \ref GPDMA_HCLK_ENABLE + * - \ref SOC_PLL_SPI_CLK_ENABLE + * - \ref IID_CLK_ENABLE + * - \ref SDIO_SYS_HCLK_ENABLE + * - \ref CRC_CLK_ENABLE_M4 + * - \ref M4SS_UM_CLK_STATIC_EN + * - \ref ETH_HCLK_ENABLE + * - \ref HWRNG_PCLK_ENABLE + * - \ref GNSS_MEM_CLK_ENABLE + * - \ref CCI_PCLK_ENABLE + * - \ref CCI_HCLK_ENABLE + * - \ref CCI_CLK_ENABLE + * - \ref MASK_HOST_CLK_WAIT_FIX + * - \ref MASK31_HOST_CLK_CNT + * - \ref SD_MEM_INTF_CLK_ENABLE + * - \ref MASK_HOST_CLK_AVAILABLE_FIX + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkEnable1(&M4CLK ,(USART1_PCLK_ENABLE | USART1_SCLK_ENABLE )); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable1(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable1(pCLK, flags); +#else + return clk_peripheral_clk_enable1(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable1(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the peripheral clocks for CLR1 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enbled. + * - \ref USART1_PCLK_ENABLE + * - \ref USART1_SCLK_ENABLE + * - \ref USART2_PCLK_ENABLE + * - \ref USART2_SCLK_ENABLE + * - \ref CT_CLK_ENABLE + * - \ref CT_PCLK_ENABLE + * - \ref ICACHE_CLK_ENABLE + * - \ref ICACHE_CLK_2X_ENABLE + * - \ref GPDMA_HCLK_ENABLE + * - \ref SOC_PLL_SPI_CLK_ENABLE + * - \ref IID_CLK_ENABLE + * - \ref SDIO_SYS_HCLK_ENABLE + * - \ref CRC_CLK_ENABLE_M4 + * - \ref M4SS_UM_CLK_STATIC_EN + * - \ref ETH_HCLK_ENABLE + * - \ref HWRNG_PCLK_ENABLE + * - \ref GNSS_MEM_CLK_ENABLE + * - \ref CCI_PCLK_ENABLE + * - \ref CCI_HCLK_ENABLE + * - \ref CCI_CLK_ENABLE + * - \ref MASK_HOST_CLK_WAIT_FIX + * - \ref MASK31_HOST_CLK_CNT + * - \ref SD_MEM_INTF_CLK_ENABLE + * - \ref MASK_HOST_CLK_AVAILABLE_FIX + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkDisable1(&M4CLK ,(USART1_PCLK_ENABLE | USART1_SCLK_ENABLE )); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable1(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable1(pCLK, flags); +#else + return clk_peripheral_clk_disable1(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the peripheral clocks for SET2 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enabled. + * - \ref GEN_SPI_MST1_HCLK_ENABLE + * - \ref CAN1_PCLK_ENABLE + * - \ref CAN1_CLK_ENABLE + * - \ref UDMA_HCLK_ENABLE + * - \ref I2C_BUS_CLK_ENABLE + * - \ref I2C_2_BUS_CLK_ENABLE + * - \ref SSI_SLV_PCLK_ENABLE + * - \ref SSI_SLV_SCLK_ENABLE + * - \ref QSPI_CLK_ENABLE + * - \ref QSPI_HCLK_ENABLE + * - \ref I2SM_INTF_SCLK_ENABLE + * - \ref I2SM_PCLK_ENABLE + * - \ref QE_PCLK_ENABLE + * - \ref MCPWM_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_ENABLE + * - \ref ARM_CLK_ENABLE + * - \ref SSI_MST_PCLK_ENABLE + * - \ref SSI_MST_SCLK_ENABLE + * - \ref MEM2_CLK_ENABLE + * - \ref MEM_CLK_ULP_ENABLE + * - \ref ROM_CLK_ENABLE + * - \ref PLL_INTF_CLK_ENABLE + * - \ref SEMAPHORE_CLK_ENABLE + * - \ref TOT_CLK_ENABLE + * - \ref RMII_SOFT_RESET + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkEnable2(M4CLK ,(GEN_SPI_MST1_HCLK_ENABLE | SSI_MST_PCLK_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable2(pCLK, flags); +#else + return clk_peripheral_clk_enable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the peripheral clocks for CLR2 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enabled. + * - \ref GEN_SPI_MST1_HCLK_ENABLE + * - \ref CAN1_PCLK_ENABLE + * - \ref CAN1_CLK_ENABLE + * - \ref UDMA_HCLK_ENABLE + * - \ref I2C_BUS_CLK_ENABLE + * - \ref I2C_2_BUS_CLK_ENABLE + * - \ref SSI_SLV_PCLK_ENABLE + * - \ref SSI_SLV_SCLK_ENABLE + * - \ref QSPI_CLK_ENABLE + * - \ref QSPI_HCLK_ENABLE + * - \ref I2SM_INTF_SCLK_ENABLE + * - \ref I2SM_PCLK_ENABLE + * - \ref QE_PCLK_ENABLE + * - \ref MCPWM_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_ENABLE + * - \ref ARM_CLK_ENABLE + * - \ref SSI_MST_PCLK_ENABLE + * - \ref SSI_MST_SCLK_ENABLE + * - \ref MEM2_CLK_ENABLE + * - \ref MEM_CLK_ULP_ENABLE + * - \ref ROM_CLK_ENABLE + * - \ref PLL_INTF_CLK_ENABLE + * - \ref SEMAPHORE_CLK_ENABLE + * - \ref TOT_CLK_ENABLE + * - \ref RMII_SOFT_RESET + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkDisable2(M4CLK ,(GEN_SPI_MST1_HCLK_ENABLE | SSI_MST_PCLK_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable2(pCLK, flags); +#else + return clk_peripheral_clk_disable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable3(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the peripheral clocks for SET3 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enabled. + * - \ref BUS_CLK_ENABLE + * - \ref M4_CORE_CLK_ENABLE + * - \ref CM_BUS_CLK_ENABLE + * - \ref MISC_CONFIG_PCLK_ENABLE + * - \ref EFUSE_CLK_ENABLE + * - \ref ICM_CLK_ENABLE + * - \ref MEM1_CLK_ENABLE + * - \ref MEM3_CLK_ENABLE + * - \ref USB_PHY_CLK_IN_ENABLE + * - \ref QSPI_CLK_ONEHOT_ENABLE + * - \ref QSPI_M4_SOC_SYNC + * - \ref EGPIO_CLK_ENABLE + * - \ref I2C_CLK_ENABLE + * - \ref I2C_2_CLK_ENABLE + * - \ref EFUSE_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref TASS_M4SS_64K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_128K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_SDIO_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_USB_SWITCH_CLK_ENABLE + * - \ref ROM_MISC_STATIC_ENABLE + * - \ref M4_SOC_CLK_FOR_OTHER_ENABLE + * - \ref ICACHE_ENABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkEnable3(M4CLK ,(M4_SOC_CLK_FOR_OTHER_ENABLE | ROM_MISC_STATIC_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable3(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable3(pCLK, flags); +#else + return clk_peripheral_clk_enable3(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable3(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the peripheral clocks for CLR3 register + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed values of peripheral bits to be enbled. + * - \ref BUS_CLK_ENABLE + * - \ref M4_CORE_CLK_ENABLE + * - \ref CM_BUS_CLK_ENABLE + * - \ref MISC_CONFIG_PCLK_ENABLE + * - \ref EFUSE_CLK_ENABLE + * - \ref ICM_CLK_ENABLE + * - \ref MEM1_CLK_ENABLE + * - \ref MEM3_CLK_ENABLE + * - \ref USB_PHY_CLK_IN_ENABLE + * - \ref QSPI_CLK_ONEHOT_ENABLE + * - \ref QSPI_M4_SOC_SYNC + * - \ref EGPIO_CLK_ENABLE + * - \ref I2C_CLK_ENABLE + * - \ref I2C_2_CLK_ENABLE + * - \ref EFUSE_PCLK_ENABLE + * - \ref SGPIO_PCLK_ENABLE + * - \ref TASS_M4SS_64K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_128K_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_SDIO_SWITCH_CLK_ENABLE + * - \ref TASS_M4SS_USB_SWITCH_CLK_ENABLE + * - \ref ROM_MISC_STATIC_ENABLE + * - \ref M4_SOC_CLK_FOR_OTHER_ENABLE + * - \ref ICACHE_ENABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_PeripheralClkDisable3(M4CLK ,(M4_SOC_CLK_FOR_OTHER_ENABLE | ROM_MISC_STATIC_ENABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable3(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable3(pCLK, flags); +#else + return clk_peripheral_clk_disable3(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SDIO_SYS_HCLK_DYN_CTRL_DISABLE + * - \ref BUS_CLK_DYN_CTRL_DISABLE + * - \ref GPDMA_HCLK_DYN_CTRL_DISABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref SGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref TOT_CLK_DYN_CTRL_DISABLE + * - \ref HWRNG_PCLK_DYN_CTRL_DISABLE + * - \ref USART1_SCLK_DYN_CTRL_DISABLE + * - \ref USART1_PCLK_DYN_CTRL_DISABLE + * - \ref USART2_SCLK_DYN_CTRL_DISABLE + * - \ref USART2_PCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_SCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_PCLK_DYN_CTRL_DISABLE + * - \ref I2SM_INTF_SCLK_DYN_CTRL_DISABLE + * - \ref SEMAPHORE_CLK_DYN_CTRL_DISABLE + * - \ref ARM_CLK_DYN_CTRL_DISABLE + * - \ref SSI_MST_SCLK_DYN_CTRL_DISABLE + * - \ref MEM1_CLK_DYN_CTRL_DISABLE + * - \ref MEM2_CLK_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref SSI_MST_PCLK_DYN_CTRL_DISABLE + * - \ref ICACHE_DYN_GATING_DISABLE + * - \ref CCI_PCLK_DYN_CTRL_DISABLE + * - \ref MISC_CONFIG_PCLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_DynamicClkGateDisable(M4CLK , (SDIO_SYS_HCLK_DYN_CTRL_DISABLE | BUS_CLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_disable(pCLK, flags); +#else + return clk_dynamic_clk_gate_disable(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE + * - \ref I2C_BUS_DYN_CTRL_DISABLE + * - \ref I2C_2_BUS_CLK_DYN_CTRL_DISABLE + * - \ref CT_PCLK_DYN_CTRL_DISABLE + * - \ref CAN1_PCLK_DYN_CTRL_DISABLE + * - \ref EFUSE_CLK_DYN_CTRL_DISABLE + * - \ref EFUSE_PCLK_DYN_CTRL_DISABLE + * - \ref PWR_CTRL_CLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_CLK_DynamicClkGateDisable2(M4CLK , (EFUSE_CLK_DYN_CTRL_DISABLE | EFUSE_PCLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateDisable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_disable2(pCLK, flags); +#else + return clk_dynamic_clk_gate_disable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SDIO_SYS_HCLK_DYN_CTRL_DISABLE + * - \ref BUS_CLK_DYN_CTRL_DISABLE + * - \ref GPDMA_HCLK_DYN_CTRL_DISABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref SGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref TOT_CLK_DYN_CTRL_DISABLE + * - \ref HWRNG_PCLK_DYN_CTRL_DISABLE + * - \ref USART1_SCLK_DYN_CTRL_DISABLE + * - \ref USART1_PCLK_DYN_CTRL_DISABLE + * - \ref USART2_SCLK_DYN_CTRL_DISABLE + * - \ref USART2_PCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_SCLK_DYN_CTRL_DISABLE + * - \ref SSI_SLV_PCLK_DYN_CTRL_DISABLE + * - \ref I2SM_INTF_SCLK_DYN_CTRL_DISABLE + * - \ref SEMAPHORE_CLK_DYN_CTRL_DISABLE + * - \ref ARM_CLK_DYN_CTRL_DISABLE + * - \ref SSI_MST_SCLK_DYN_CTRL_DISABLE + * - \ref MEM1_CLK_DYN_CTRL_DISABLE + * - \ref MEM2_CLK_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref MEM_CLK_ULP_DYN_CTRL_DISABLE + * - \ref SSI_MST_PCLK_DYN_CTRL_DISABLE + * - \ref ICACHE_DYN_GATING_DISABLE + * - \ref CCI_PCLK_DYN_CTRL_DISABLE + * - \ref MISC_CONFIG_PCLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_DynamicClkGateEnable(M4CLK , (SDIO_SYS_HCLK_DYN_CTRL_DISABLE | BUS_CLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_enable(pCLK, flags); +#else + return clk_dynamic_clk_gate_enable(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable2(M4CLK_Type *pCLK ,uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] flags : ORed value of the register bits + * - \ref SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE + * - \ref I2C_BUS_DYN_CTRL_DISABLE + * - \ref I2C_2_BUS_CLK_DYN_CTRL_DISABLE + * - \ref CT_PCLK_DYN_CTRL_DISABLE + * - \ref CAN1_PCLK_DYN_CTRL_DISABLE + * - \ref EFUSE_CLK_DYN_CTRL_DISABLE + * - \ref EFUSE_PCLK_DYN_CTRL_DISABLE + * - \ref PWR_CTRL_CLK_DYN_CTRL_DISABLE + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * + * @b Example + * - RSI_Clk_DynamicClkGateEnable2(M4CLK , (EFUSE_CLK_DYN_CTRL_DISABLE | EFUSE_PCLK_DYN_CTRL_DISABLE)); + */ +STATIC INLINE rsi_error_t RSI_CLK_DynamicClkGateEnable2(M4CLK_Type *pCLK, uint32_t flags) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_dynamic_clk_gate_enable2(pCLK, flags); +#else + return clk_dynamic_clk_gate_enable2(pCLK, flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_EnableRefClks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType,cdDelay delayFn) + * @brief This API is used to enable the ULP reference clocks and provide delay for clock starting + * @param[in] enable : To enable the particular reference clock. See \ref REF_CLK_ENABLE_T for more info + * @param[in] srcType : To select the pheripheral clock or processor clk. See \ref SRC_TYPE_T for more info + * @param[in] delayFn : Call back fuction used to create delay by using loops or timers in application code + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_ULPSS_EnableRefClks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->ulpss_enable_ref_clks(enable, srcType, delayFn); +#else + return ulpss_enable_ref_clks(enable, srcType, delayFn); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type) + * @brief This API is used to disable the ULP reference clocks + * @param[in] clk_type : To enable the particular reference clock. See \ref REF_CLK_ENABLE_T for more info + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_ULPSS_DisableRefClks(REF_CLK_ENABLE_T clk_type) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->ulpss_disable_ref_clks(clk_type); +#else + return ulpss_disable_ref_clks(clk_type); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(const M4CLK_Type *pCLK ,M4SS_REF_CLK_SEL_T clkSource) + * @brief This API is used to configure the m4ss_ref clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values of different M4 ref source clocks \ref M4SS_REF_CLK_SEL_T + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_M4ssRefClkConfig(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) +{ +#if SL_WIFI_COMPONENT_INCLUDED + if (clkSource == EXT_40MHZ_CLK) { + /* Notify NWP that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); + } +#endif + return clk_m4ss_ref_clk_config(pCLK, clkSource); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_M4SocClkConfig(M4CLK_Type *pCLK ,M4_SOC_CLK_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the m4_soc clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values of different SOC source clocks.See #M4_SOC_CLK_SRC_SEL_T and NOTE for more info + * @param[in] divFactor : division value for M4SOC clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + * - For using SocPllCLK clksource need to configure SocPll frequency. For that need to call \ref RSI_CLK_SetSocPllFreq Api first + * - For using IntfPllCLK clksource need to configure IntfPll frequency. For that need to call \ref RSI_CLK_SetIntfPllFreq Api first + * - For using Sleep clksource need to configure Sleep Clock. For that need to call \ref RSI_CLK_SlpClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_M4SocClkConfig(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ + return clk_m4_soc_clk_config(pCLK, clkSource, divFactor); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_QspiClkConfig(M4CLK_Type *pCLK ,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn, + boolean_t OddDivEn,uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum valuse for Qspi clock sources to be selected. + see possible Qspi clock sources at \ref QSPI_CLK_SRC_SEL_T + * @param[in] swalloEn : To enable or disable the swallo functionality. See user manual for more info + * - 1 : swalloEn enabled + * - 0 : swalloEn disabled + * @param[in] OddDivEn : To enable or disable the odd div functionality. See user manual for more info + * - 1 : OddDivEn enabled + * - 0 : OddDivEn disabled + * @param[in] divFactor : Division value for Qspi Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. + \n For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_QspiClkConfig(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_qspi_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#else + return clk_qspi_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#endif +} +#if defined(SLI_SI917B0) || defined(SLI_SI915) + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_Qspi2ClkConfig(M4CLK_Type *pCLK ,QSPI_CLK_SRC_SEL_T clkSource,boolean_t swalloEn, + boolean_t OddDivEn,uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum valuse for Qspi clock sources to be selected. + see possible Qspi clock sources at \ref QSPI_CLK_SRC_SEL_T + * @param[in] swalloEn : To enable or disable the swallo functionality. See user manual for more info + * - 1 : swalloEn enabled + * - 0 : swalloEn disabled + * @param[in] OddDivEn : To enable or disable the odd div functionality. See user manual for more info + * - 1 : OddDivEn enabled + * - 0 : OddDivEn disabled + * @param[in] divFactor : Division value for Qspi Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. + \n For that need to call \ref RSI_CLK_M4ssRefClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_Qspi2ClkConfig(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_qspi_2_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#else + return clk_qspi_2_clk_config(pCLK, clkSource, swalloEn, OddDivEn, divFactor); +#endif +} +#endif +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_UsartClkConfig(M4CLK_Type *pCLK ,CLK_ENABLE_T clkType,boolean_t FracDivEn, + EN_USART_T enUsart,USART_CLK_SRC_SEL_T clkSource,uint32_t divFactor) + * @brief This API is used to configure the Usart clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkType : Boolean value to enable or disable clock mode + * - 1 Enable : Enables the Usart clock + * - 0 Disable: Disables the Usart clock + * @param[in] FracDivEn : To enable or disable Fractional Division functionality + * - 1 : FracDivEn enabled + * - 0 : FracDivEn disabled + * @param[in] enUsart : Enum values for different Usart instances see possible bypass clock sources at \ref EN_USART_T + * @param[in] clkSource : Enum values for Usart clock sources to be selected. see possible Usart clock sources at #USART_CLK_SRC_SEL_T + * @param[in] divFactor is the division value for Usart Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + * @note For using UlpRefClk clksource need to configure M4ssRefClk frequency. For that need to call #ROM_CLK_M4ssRefClkConfig Api first + */ +STATIC INLINE rsi_error_t RSI_CLK_UsartClkConfig(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + boolean_t FracDivEn, + EN_USART_T enUsart, + USART_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_usart_clk_config(pCLK, clkType, FracDivEn, enUsart, clkSource, divFactor); +#else + return clk_usart_clk_config(pCLK, clkType, FracDivEn, enUsart, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkConfig(M4CLK_Type *pCLK ,CLK_ENABLE_T clkType , + SSI_MST_CLK_SRC_SEL_T clkSource ,uint32_t divFactor) + * @brief This API is used to configure the SSI clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info. + * @param[in] clkSource : Enum values for SSI clock sources to be selected. see possible SSI clock sources at #SSI_MST_CLK_SRC_SEL_T + * @param[in] divFactor : is the division value for SSI Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkConfig(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + SSI_MST_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ssi_mst_clk_config(pCLK, clkType, clkSource, divFactor); +#else + return clk_ssi_mst_clk_config(pCLK, clkType, clkSource, divFactor); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SdMemClkConfig(M4CLK_Type *pCLK ,boolean_t swalloEn ,SDMEM_CLK_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the SdMem clocks + * @param[in] pCLK : Pointer to pll register instance + * @param[in] swalloEn : Enable or disable the swallo functionality + * - 1 : swalloEn enabled + * - 0 : swalloEn disabled + * @param[in] clkSource : Enum values for SdMem clock sources to be selected. see possible SdMem clock sources at #SDMEM_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for SdMem Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SdMemClkConfig(M4CLK_Type *pCLK, + boolean_t swalloEn, + SDMEM_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_sd_mem_clk_config(pCLK, swalloEn, clkSource, divFactor); +#else + return clk_sd_mem_clk_config(pCLK, swalloEn, clkSource, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CtClkConfig(M4CLK_Type *pCLK ,CT_CLK_SRC_SEL_T clkSource ,uint32_t divFactor, + CLK_ENABLE_T clkType) + * @brief This API is used to configure the CT clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values for CT clock sources to be selected. see possible CT clock + sources at \ref CT_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for CT Clock + * @param[in] clkType : Enum value to select static clock or dynamic clock. See \ref CLK_ENABLE_T for more info. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CtClkConfig(M4CLK_Type *pCLK, + CT_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ct_clk_config(pCLK, clkSource, divFactor, clkType); +#else + return clk_ct_clk_config(pCLK, clkSource, divFactor, clkType); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CciClkConfig(M4CLK_Type *pCLK ,CCI_CLK_SRC_SEL_T clkSource ,uint32_t divFactor, + CLK_ENABLE_T clkType) + * @brief This API is used to configure the CCI clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values for CCI clock sources to be selected. see possible CCI clock sources at #CCI_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for CCI Clock + * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CciClkConfig(M4CLK_Type *pCLK, + CCI_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_cci_clk_config(pCLK, clkSource, divFactor, clkType); +#else + return clk_cci_clk_config(pCLK, clkSource, divFactor, clkType); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sClkConfig(M4CLK_Type *pCLK ,I2S_CLK_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the I2S clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum valuse for I2S clock sources to be selected. see possible I2S clock sources at #I2S_CLK_SRC_SEL_T + * @param[in] divFactor : Division value for I2S Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sClkConfig(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_clk_config(pCLK, clkSource, divFactor); +#else + return clk_i2s_clk_config(pCLK, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_McuClkOutConfig(M4CLK_Type *pCLK ,MCU_CLKOUT_SRC_SEL_T clkSource , + uint32_t divFactor) + * @brief This API is used to configure the McuClkOut clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Enum values of MCU_CLKOUT. See possible mcu_clk sources at #MCU_CLKOUT_SRC_SEL_T + * @param[in] divFactor : Division value for McuClkOut Clock + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_McuClkOutConfig(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_mcu_clk_cut_config(pCLK, clkSource, divFactor); +#else + return clk_mcu_clk_cut_config(pCLK, clkSource, divFactor); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CanClkConfig(M4CLK_Type *pCLK , uint32_t divFactor,CLK_ENABLE_T clkType) + * @brief This API is used to configure the Can clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : Division value for Can Clock + * @param[in] clkType : Enum value to select static clock or dynamic clock. See #CLK_ENABLE_T for more info. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CanClkConfig(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_can_clk_config(pCLK, divFactor, clkType); +#else + return clk_can_clk_config(pCLK, divFactor, clkType); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_EthernetClkConfig(M4CLK_Type *pCLK ,boolean_t swalloEn ,ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) + * @brief This API is used to configure the PLL_INTF clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] swalloEn : Enable or disable the swallo functionality + * - 1 : Swallo enabled + * - 0 : Swallo disabled + * @param[in] clkSource : Enum values for PLL_Intf clock sources to be selected. see possible PLl clock sources at #ETHERNET_CLK_SRC_SEL_T + * @param[in] divFactor : PLL_INTF clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_EthernetClkConfig(M4CLK_Type *pCLK, + boolean_t swalloEn, + ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ethernet_clk_config(pCLK, swalloEn, clkSource, divFactor); +#else + return clk_ethernet_clk_config(pCLK, swalloEn, clkSource, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_M4SocClkDiv(M4CLK_Type *pCLK ,uint32_t divFactor) + * @brief This API is used to divide the M4soc clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : M4Soc clock division value + * @return returns 0 on success + * \n Error code on failure + */ +STATIC INLINE rsi_error_t RSI_CLK_M4SocClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_m4_soc_clk_div(pCLK, divFactor); +#else + return clk_m4_soc_clk_div(pCLK, divFactor); +#endif +} + +/** + * @fn RSI_CLK_QspiClkDiv(M4CLK_Type *pCLK , boolean_t u8SwallowEn , + boolean_t u8OddDivEn , uint32_t divFactor ) + * @brief This API is used to divide the QSPI clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] u8SwallowEn : To enable or disable the swallo functionality + * - 1 : Swallo enabled + * - 0 : Swallo disabled + * @param[in] u8OddDivEn : To enable or disable the odd division functionality + * - 1 : Odd division enabled + * - 0 : Odd division disabled + * @param[in] divFactor : QSPI clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_QspiClkDiv(M4CLK_Type *pCLK, + boolean_t u8SwallowEn, + boolean_t u8OddDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_qspi_clk_div(pCLK, u8SwallowEn, u8OddDivEn, divFactor); +#else + return clk_qspi_clk_div(pCLK, u8SwallowEn, u8OddDivEn, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CtClkDiv(M4CLK_Type *pCLK , uint32_t divFactor) + * @brief This API is used to divide the CT clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : CT clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CtClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ct_clk_div(pCLK, divFactor); +#else + return clk_ct_clk_div(pCLK, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkDiv(M4CLK_Type *pCLK , uint32_t divFactor ) + * @brief This API is used to divide the SSI clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : SSI clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SsiMstClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_ssi_mst_clk_div(pCLK, divFactor); +#else + return clk_ssi_mst_clk_div(pCLK, divFactor); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_CciClkDiv(M4CLK_Type *pCLK , uint32_t divFactor ) + * @brief This API is used to divide the CCI clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : CCI clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_CciClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_cci_clk_div(pCLK, divFactor); +#else + return clk_cci_clk_div(pCLK, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2sClkDiv(M4CLK_Type *pCLK , uint32_t divFactor ) + * @brief This API is used to divide the I2S clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] divFactor : I2S clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2sClkDiv(M4CLK_Type *pCLK, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2s_clk_div(pCLK, divFactor); +#else + return clk_i2s_clk_div(pCLK, divFactor); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SdmemClkDiv(M4CLK_Type *pCLK , boolean_t u8SwallowEn , uint32_t divFactor) + * @brief This API is used to divide the SDMEM clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] u8SwallowEn : To enable or disable the swallo functionality + * - 1 : Swallo enabled + * - 0 : Swallo disabled + * @param[in] divFactor : SDMEM clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SdmemClkDiv(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_sd_mem_clk_div(pCLK, u8SwallowEn, divFactor); +#else + return clk_sd_mem_clk_div(pCLK, u8SwallowEn, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_UsartClkDiv(M4CLK_Type *pCLK , EN_USART_T EN_USART_T , + uint8_t u8FracDivEn, uint32_t divFactor) + * @brief This API is used to divide the USART/UART clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] EN_USART_T : Enum of uart numbers. See #EN_USART_T for more info + * @param[in] u8FracDivEn : To enable or disable fractional division feature + * - 1 : Clock Swallo type divider is selected + * - 0 : Fractional Divider typed is selected + * @param[in] divFactor : USART/UART clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_UsartClkDiv(M4CLK_Type *pCLK, + EN_USART_T EN_USART, + uint8_t u8FracDivEn, + uint32_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_usart_clk_div(pCLK, EN_USART, u8FracDivEn, divFactor); +#else + return clk_usart_clk_div(pCLK, EN_USART, u8FracDivEn, divFactor); +#endif +} + +/** + * @fn uint32_t RSI_CLK_SlpClkCalibConfig(M4CLK_Type *pCLK , uint8_t clkCycles) + * @brief This API is used to calibrate the sleep clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkCycles : These bits are used to program the number of clock cycles over which + clock calibration is to be done. + * - 00 => 1 Cycle + * - 01 => 2 Cycles + * - 10 => 3 Cycles + * - 11 => 4 Cycles + * @return Returns the calibration duration. + */ +STATIC INLINE uint32_t RSI_CLK_SlpClkCalibConfig(M4CLK_Type *pCLK, uint8_t clkCycles) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_slp_clk_calib_config(pCLK, clkCycles); +#else + return clk_slp_clk_calib_config(pCLK, clkCycles); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_GspiClkConfig(M4CLK_Type *pCLK ,GSPI_CLK_SRC_SEL_T clkSel ) + * @brief This API is used to configure the GSPI Clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSel : Enum values to select the clock sources. See possible values at \ref GSPI_CLK_SRC_SEL_T + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_GspiClkConfig(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_gspi_clk_config(pCLK, clkSel); +#else + return clk_gspi_clk_config(pCLK, clkSel); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_SlpClkConfig(M4CLK_Type *pCLK , SLEEP_CLK_SRC_SEL_T clkSrc) + * @brief This API is used to configure the SLEEP Clocks + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSrc : Enum values to select the clock sources for sleep clock. See \ref SLEEP_CLK_SRC_SEL_T for more info + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_SlpClkConfig(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_slp_clk_config(pCLK, clkSrc); +#else + return clk_slp_clk_config(pCLK, clkSrc); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_I2CClkConfig(M4CLK_Type *pCLK , boolean_t clkEnable,EN_I2C_T enI2C) + * @brief This API is used to configure the I2C clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkEnable : Boolean value to enable or disable clock mode + * - 1 clkEnable : Enables the I2C clock + * - 0 Disable : Disables the I2C clock + * @param[in] enI2C : Enum values. See \ref EN_I2C_T for more infomation + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_I2CClkConfig(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_i2c_clk_config(pCLK, clkEnable, enI2C); +#else + return clk_i2c_clk_config(pCLK, clkEnable, enI2C); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_XtalClkConfig(uint8_t xtalPin) + * @brief This API is used to configure the Xtal clock + * @param[in] xtalPin : Pin number of NPSS_GPIO. Possible values are 0,1,2,3,4 + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_XtalClkConfig(uint8_t xtalPin) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_xtal_clk_config(xtalPin); +#else + return clk_xtal_clk_config(xtalPin); +#endif +} + +#ifdef CHIP_9118 +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_USBClkConfig(M4CLK_Type *pCLK ,USB_CLK_SRC_SEL_T clkSource ,uint16_t divFactor) + * @brief This API is used to configure the USB clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkSource : Different clock sources for USB_PHY_CLK. See #USB_CLK_SRC_SEL_T for more info + * @param[in] divFactor : USB clock division value + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_USBClkConfig(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_usb_clk_config(pCLK, clkSource, divFactor); +#else + return clk_usb_clk_config(pCLK, clkSource, divFactor); +#endif +} +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable(M4CLK_Type *pCLK ,PERIPHERALS_CLK_T module,CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] module : To select particular pheripheral. + * @param[in] clkType : To select the clock as dynamic or static clock. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkEnable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_enable(pCLK, module, clkType); +#else + return clk_peripheral_clk_enable(pCLK, module, clkType); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable(M4CLK_Type *pCLK ,PERIPHERALS_CLK_T module) + * @brief This API is used to disable the particular clock + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] module : To select particular peripheral. + * @return returns zero \ref RSI_OK on success ,on failure return error code. + */ +STATIC INLINE rsi_error_t RSI_CLK_PeripheralClkDisable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module) +{ +#if defined(CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_M4SS_CLK_API->clk_peripheral_clk_disable(pCLK, module); +#else + return clk_peripheral_clk_disable(pCLK, module); +#endif +} + +/** + *@fn void RSI_CLK_SocPllLockConfig(boolean_t manual_lock , boolean_t bypass_manual_lock , uint8_t mm_count_limit) + *@brief This API is used to configure the SOC-PLL lock settings + *@param[in] manual_lock : Enable for manual mode phase lock generation + *@param[in] bypass_manual_lock : Bypass signal for phase detector logic + *@param[in] mm_count_limit : Lock count limit in manual mode phase lock generation + */ +STATIC INLINE void RSI_CLK_SocPllLockConfig(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + ROMAPI_M4SS_CLK_API->clk_config_pll_lock(manual_lock, bypass_manual_lock, mm_count_limit); +#else + clk_config_pll_lock(manual_lock, bypass_manual_lock, mm_count_limit); +#endif +} + +/** + *@fn STATIC INLINE void RSI_CLK_SocPllRefClkConfig(uint8_t ref_clk_src) + *@brief This API is used to configure SOC-PLL config + *@param[in] ref_clk_src : Reference clock to be programmed. + */ +STATIC INLINE void RSI_CLK_SocPllRefClkConfig(uint8_t ref_clk_src) +{ +#if defined(A11_ROM) && defined(CLOCK_ROMDRIVER_PRESENT) + ROMAPI_M4SS_CLK_API->clk_config_pll_ref_clk(ref_clk_src); +#else + clk_config_pll_ref_clk(ref_clk_src); +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif //__RSI_ROM_CLK_H_ + +/*@} end of RSI_M4SS_CLOCK_DRIVERS */ + +/* @} end of RSI_CHIP_CLOCK_DRIVERS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h new file mode 100644 index 000000000..9359c638a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_egpio.h @@ -0,0 +1,1213 @@ +/******************************************************************************* +* @file rsi_rom_egpio.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +//Includes + +#ifndef __RSI_ROM_EGPIO_H__ +#define __RSI_ROM_EGPIO_H__ + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup EGPIO_DRIVER + * @{ + * + */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#include "rsi_egpio.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif +/** @addtogroup SOC11 +* @{ +*/ + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetDir(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin, boolean_t dir) + * @brief This API is used to set the EGPIO direction(Direction of the GPIO pin. '1' for INPUT, '0' for OUTPUT) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @param[in] dir : boolean type pin direction + * \n '0' : Output + * \n '1' : Input + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetDir(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_dir(pEGPIO, port, pin, dir); +#else + egpio_set_dir(pEGPIO, port, pin, dir); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPin(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin , uint8_t val) + * @brief This API is used to set the GPIO pin value.It Loads 0th bit on to the pin on write & + * reads the value on pin on read into 0th bit + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @param[in] val : value to be set for the pin + * \n '0' : Logic on Pin + * \n '1' : Logic on Pin + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPin(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_pin(pEGPIO, port, pin, val); +#else + egpio_set_pin(pEGPIO, port, pin, val); +#endif +} + +/** + * @fn STATIC INLINE boolean_t RSI_EGPIO_GetPin(const EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) + * @brief This API is used get the GPIO pin status. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return returns Pin status + */ +STATIC INLINE boolean_t RSI_EGPIO_GetPin(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_pin(pEGPIO, port, pin); +#else + return egpio_get_pin(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE boolean_t RSI_EGPIO_GetDir(const EGPIO_Type *pEGPIO,uint8_t port ,uint8_t pin) + * @brief This API is used to Get the Direction GPIO(Direction of the GPIO pin. '1' for INPUT,and '0'for OUTPUT) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return returns the GPIO direction value + */ +STATIC INLINE boolean_t RSI_EGPIO_GetDir(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_dir(pEGPIO, port, pin); +#else + return egpio_get_dir(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PinIntSel(EGPIO_Type *pEGPIO ,uint8_t intCh ,uint8_t port , uint8_t pin) + * @brief This API is used to select the pin for interrupt generation + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_PinIntSel(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pin_int_sel(pEGPIO, intCh, port, pin); +#else + egpio_pin_int_sel(pEGPIO, intCh, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntFallEdgeEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n(enables interrupt generation when falling edge is detected on pin '1' for intr enabled and '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntFallEdgeEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_fall_edge_enable(pEGPIO, intCh); +#else + egpio_set_int_fall_edge_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntFallEdgeDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API to used to set the pin interrupt mode configuration + * \n(enables interrupt generation when falling edge is detected on pin '1' for intr enabled and '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntFallEdgeDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_fall_edge_disable(pEGPIO, intCh); +#else + egpio_set_int_fall_edge_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API to used to set the pin interrupt mode configuration + * \n(enables interrupt generation when rising edge is detected on pin '1' for intr enabled and '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_rise_edge_enable(pEGPIO, intCh); +#else + egpio_set_int_rise_edge_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API to used to set the pin interrupt mode configuration + * \n(enables interrupt generation when rising edge is detected on pin '1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntRiseEdgeDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_rise_edge_disable(pEGPIO, intCh); +#else + egpio_set_int_rise_edge_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntLowLevelEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n (enables interrupt generation when pin level is 0, '1' for intr enabled, '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntLowLevelEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_low_level_enable(pEGPIO, intCh); +#else + egpio_set_int_low_level_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_IntMask(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n(Masks the interrupt. Interrupt will still be seen in status register when enabled + * '1' for intr masked '0' for intr unmasked) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_IntMask(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_int_mask(pEGPIO, intCh); +#else + egpio_int_mask(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_IntUnMask(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to used to set the pin interrupt mode configuration + * \n(UnMasks the interrupt. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_IntUnMask(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_int_un_mask(pEGPIO, intCh); +#else + egpio_int_un_mask(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntLowLevelDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to set the pin interrupt mode configuration + * \n(enables interrupt generation when pin level is 0 ,'1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntLowLevelDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_low_level_disable(pEGPIO, intCh); +#else + egpio_set_int_low_level_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntHighLevelEnable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API used to set the pin interrupt mode configuration + * \n(enables interrupt generation when pin level is 1, '1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntHighLevelEnable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_high_level_enable(pEGPIO, intCh); +#else + egpio_set_int_high_level_enable(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetIntHighLevelDisable(EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to used to set the pin interrupt mode configuration + \n(disables interrupt generation when pin level is 1 ,'1' for intr enabled '0' for disabled) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetIntHighLevelDisable(EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_int_high_level_disable(pEGPIO, intCh); +#else + egpio_set_int_high_level_disable(pEGPIO, intCh); +#endif +} + +/** + * @fn uint8_t RSI_EGPIO_GetIntStat(const EGPIO_Type *pEGPIO ,uint8_t intCh) + * @brief This API is used to get the pin interrupt status register + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @return returns the interrupt status register + */ +STATIC INLINE uint8_t RSI_EGPIO_GetIntStat(const EGPIO_Type *pEGPIO, uint8_t intCh) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_int_stat(pEGPIO, intCh); +#else + return egpio_get_int_stat(pEGPIO, intCh); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_IntClr(EGPIO_Type *pEGPIO ,uint8_t intCh , uint8_t flags) + * @brief This API is used to clear the pin interrupt in status register + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] intCh : GPIO pin interrupt channel number (0 to 7) + * @param[in] flags : GPIO pin interrupt channel number (0 to 7) + \n 2- \ref EGPIO_PIN_INT_CLR_FALLING + \n 1- \ref EGPIO_PIN_INT_CLR_RISING + \n 0- \ref INTERRUPT_STATUS_CLR + * @return None + */ +STATIC INLINE void RSI_EGPIO_IntClr(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_int_clr(pEGPIO, intCh, flags); +#else + egpio_int_clr(pEGPIO, intCh, flags); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPinMux(EGPIO_Type *pEGPIO ,uint8_t port , uint8_t pin , uint8_t mux) + * @brief This API to used to set pin multiplexing + * \n(GPIO Pin Mode. Ranges 000 -> Mode 0 to 111 -> Mode 7 Used for GPIO Pin Muxing) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @param[in] mux : pin function value + * \n possible values for this parameter are the following + * - \ref EGPIO_PIN_MUX_MODE0 : Select pin mode 0 + * - \ref EGPIO_PIN_MUX_MODE1 : Select pin mode 1 + * - \ref EGPIO_PIN_MUX_MODE2 : Select pin mode 2 + * - \ref EGPIO_PIN_MUX_MODE3 : Select pin mode 3 + * - \ref EGPIO_PIN_MUX_MODE4 : Select pin mode 4 + * - \ref EGPIO_PIN_MUX_MODE5 : Select pin mode 5 + * - \ref EGPIO_PIN_MUX_MODE6 : Select pin mode 6 + * - \ref EGPIO_PIN_MUX_MODE7 : Select pin mode 7 + * - \ref EGPIO_PIN_MUX_MODE8 : Select pin mode 8 + * - \ref EGPIO_PIN_MUX_MODE9 : Select pin mode 9 + * - \ref EGPIO_PIN_MUX_MODE10 : Select pin mode 10 + * - \ref EGPIO_PIN_MUX_MODE11 : Select pin mode 11 + * - \ref EGPIO_PIN_MUX_MODE12 : Select pin mode 12 + * - \ref EGPIO_PIN_MUX_MODE13 : Select pin mode 13 + * - \ref EGPIO_PIN_MUX_MODE14 : Select pin mode 14 + * - \ref EGPIO_PIN_MUX_MODE15 : Select pin mode 15 + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPinMux(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t mux) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_pin_mux(pEGPIO, port, pin, mux); +#else + egpio_set_pin_mux(pEGPIO, port, pin, mux); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpSocGpioMode(ULPCLK_Type *pULPCLK,uint8_t gpio,uint8_t mode) + * @brief This API is used set ulp soc gpio mode + * \n(Gpio pin mode,ranges 000 -> Mode 0 to 111 -> Mode 7 Used for GPIO Pin Muxing ) + * @param[in] pULPCLK : Pointer to the ULP register instance + * @param[in] gpio : Gpio number + * @param[in] mode : GPIO mode + * \n possible values for this parameter are the following + * - \ref EGPIO_PIN_MUX_MODE0 : Select pin mode 0 + * - \ref EGPIO_PIN_MUX_MODE1 : Select pin mode 1 + * - \ref EGPIO_PIN_MUX_MODE2 : Select pin mode 2 + * - \ref EGPIO_PIN_MUX_MODE3 : Select pin mode 3 + * - \ref EGPIO_PIN_MUX_MODE4 : Select pin mode 4 + * - \ref EGPIO_PIN_MUX_MODE5 : Select pin mode 5 + * - \ref EGPIO_PIN_MUX_MODE6 : Select pin mode 6 + * - \ref EGPIO_PIN_MUX_MODE7 : Select pin mode 7 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpSocGpioMode(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_soc_gpio_mode(pULPCLK, gpio, mode); +#else + egpio_ulp_soc_gpio_mode(pULPCLK, gpio, mode); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPortMask(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) + * @brief This API is used to set the EGPIO port mask. When set, pin is masked when written/read through PORT MASK REG. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPortMask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_port_mask(pEGPIO, port, pin); +#else + egpio_set_port_mask(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPortUnMask(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin) + * @brief This API is used to set the EGPIO port unmask. When set, pin is masked when written/read through PORT MASK REG. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPortUnMask(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_port_un_mask(pEGPIO, port, pin); +#else + egpio_set_port_un_mask(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PortMaskedLoad(EGPIO_Type *pEGPIO ,uint8_t port, uint16_t val) + * @brief This API is used to set the EGPIO port mask load. When set, pin is masked when written/read through PORT MASK REG. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_PortMaskedLoad(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_port_masked_load(pEGPIO, port, val); +#else + egpio_port_masked_load(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetPort(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to set the port value. + * Sets the pin when corresponding bit is high. Writing zero has no effect + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number to the EGPIO register instance + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetPort(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_port(pEGPIO, port, val); +#else + egpio_set_port(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PortLoad(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to load the port value. + * Loads the value on to pin on write. And reads the value of load register on read + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number to the EGPIO register instance + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_PortLoad(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_port_load(pEGPIO, port, val); +#else + egpio_port_load(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_WordLoad(EGPIO_Type *pEGPIO ,uint8_t pin , uint16_t val) + * @brief This API is used to load the port value. + * Loads 1 on the pin when any of the bit in load value is 1. On read pass the bit status into all bits. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] pin : pin number to the EGPIO register instance + * @param[in] val : Port value to be set + * @return None + */ +STATIC INLINE void RSI_EGPIO_WordLoad(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_word_load(pEGPIO, pin, val); +#else + egpio_word_load(pEGPIO, pin, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_ClrPort(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to clear the port value. + * Clears the pin when corresponding bit is high. Writing zero has no effect. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number + * @param[in] val : Port value to be clear + * @return None + */ +STATIC INLINE void RSI_EGPIO_ClrPort(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_clr_port(pEGPIO, port, val); +#else + egpio_clr_port(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_TogglePort(EGPIO_Type *pEGPIO ,uint8_t port , uint16_t val) + * @brief This API is used to toggle the port. + * Toggles the pin when corresponding bit is high. Writing zero has not effect. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number + * @param[in] val : Port value to be toggle + * @return None + */ +STATIC INLINE void RSI_EGPIO_TogglePort(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_toggle_port(pEGPIO, port, val); +#else + egpio_toggle_port(pEGPIO, port, val); +#endif +} + +/** + * @fn STATIC INLINE uint16_t RSI_EGPIO_GetPort(const EGPIO_Type *pEGPIO ,uint8_t port) + * @brief This API is used to used to get the EGPIO port value. + * Reads the value on GPIO pins irrespective of the pin mode. + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : Port number to be read + * @return port value + */ +STATIC INLINE uint16_t RSI_EGPIO_GetPort(const EGPIO_Type *pEGPIO, uint8_t port) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_get_port(pEGPIO, port); +#else + return egpio_get_port(pEGPIO, port); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntOneEnable(EGPIO_Type *pEGPIO,uint8_t port,uint8_t pin) + * @brief This API is used to enable the group interrupt one , When set, + * the corresponding GPIO pin is selected for group interrupt 1 generation + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntOneEnable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_one_enable(pEGPIO, port, pin); +#else + egpio_group_int_one_enable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntOneDisable(EGPIO_Type *pEGPIO,uint8_t port,uint8_t pin) + * @brief This API is used to disable the group interrupt one + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntOneDisable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_one_disable(pEGPIO, port, pin); +#else + egpio_group_int_one_disable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntTwoEnable(EGPIO_Type *pEGPIO,uint8_t port,uint8_t pin) + * @brief This API is used to enable the group interrupt Two , When set, + * the corresponding GPIO pin is selected for group interrupt 2 generation + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : GPIO port number + * @param[in] pin : GPIO pin number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntTwoEnable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_two_enable(pEGPIO, port, pin); +#else + egpio_group_int_two_enable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntMask(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-mask,0-unmask) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntMask(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_mask(pEGPIO, grpInt); +#else + egpio_group_int_mask(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntUnMask(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-mask,0-unmask) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntUnMask(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_un_Mask(pEGPIO, grpInt); +#else + egpio_group_int_un_Mask(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntEnable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-enable, 0-disable) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntEnable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_enable(pEGPIO, grpInt); +#else + egpio_group_int_enable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntDisable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(1-enable, 0-disable) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntDisable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_disable(pEGPIO, grpInt); +#else + egpio_group_int_disable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntLevel(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0-level,1-edge) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntLevel(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_level(pEGPIO, grpInt); +#else + egpio_group_int_level(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntEdge(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0-level,1-edge) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntEdge(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_edge(pEGPIO, grpInt); +#else + egpio_group_int_edge(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntAnd(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0-AND ,1-Or) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntAnd(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_and(pEGPIO, grpInt); +#else + egpio_group_int_and(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntOr(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API is used to configure the group interrupts(0- AND , 1-Or) + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntOr(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_or(pEGPIO, grpInt); +#else + egpio_group_int_or(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(const EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API to used to get the group interrupt status + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return returns the group interrupt status register + */ +STATIC INLINE uint32_t RSI_EGPIO_GroupIntStat(const EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + return ROMAPI_EGPIO_API->egpio_group_int_stat(pEGPIO, grpInt); +#else + return egpio_group_int_stat(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntWkeUpEnable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API to used to Enable the group interrupt wakeup interrupt + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntWkeUpEnable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_wkeup_Enable(pEGPIO, grpInt); +#else + egpio_group_int_wkeup_Enable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntWkeUpDisable(EGPIO_Type *pEGPIO ,uint8_t grpInt) + * @brief This API to used to Disable the group interrupt wakeup interrupt + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntWkeUpDisable(EGPIO_Type *pEGPIO, uint8_t grpInt) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_wkeup_disable(pEGPIO, grpInt); +#else + egpio_group_int_wkeup_disable(pEGPIO, grpInt); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntClr(EGPIO_Type *pEGPIO ,uint8_t grpInt , uint8_t flags) + * @brief This API is used to used to clear the group interrupt status + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] grpInt : Group interrupt number + * @param[in] flags : clear flags + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntClr(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t flags) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_clr(pEGPIO, grpInt, flags); +#else + egpio_group_int_clr(pEGPIO, grpInt, flags); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_GroupIntTwoDisable(EGPIO_Type *pEGPIO ,uint8_t port ,uint8_t pin) + * @brief This API is used to used to disable the group interrupt two + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : PORT number + * @param[in] pin : PIN number + * @return None + */ +STATIC INLINE void RSI_EGPIO_GroupIntTwoDisable(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_group_int_two_disable(pEGPIO, port, pin); +#else + egpio_group_int_two_disable(pEGPIO, port, pin); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetGroupIntOnePol(EGPIO_Type *pEGPIO ,uint8_t port , uint8_t pin , uint8_t pol) + * @brief This API is used to set the group polarity of interrupt one. + * Decides the active value of the pin to be considered for group interrupt 1 generation when enabled + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : PORT number + * @param[in] pin : PIN number + * @param[in] pol : Polarity of interrupt + * \n '0' : group interrupt gets generated when GPIO input pin status is '0'. + * \n '1' : group interrupt gets generated when GPIO input pin status is '1' + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetGroupIntOnePol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_group_int_one_pol(pEGPIO, port, pin, pol); +#else + egpio_set_group_int_one_pol(pEGPIO, port, pin, pol); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_SetGroupIntTwoPol(EGPIO_Type *pEGPIO ,uint8_t port,uint8_t pin , uint8_t pol) + * @brief This API is used to set the group polarity of interrupt two. + * Decides the active value of the pin to be considered for group interrupt 2 generation when enabled + * @param[in] pEGPIO : Pointer to the EGPIO register instance + * @param[in] port : PORT number + * @param[in] pin : PIN number + * @param[in] pol : Polarity of interrupt + * \n '0' : group interrupt gets generated when GPIO input pin status is '0'. + * \n '1' : group interrupt gets generated when GPIO input pin status is '1'. + * @return None + */ +STATIC INLINE void RSI_EGPIO_SetGroupIntTwoPol(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_set_group_int_two_pol(pEGPIO, port, pin, pol); +#else + egpio_set_group_int_two_pol(pEGPIO, port, pin, pol); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_HostPadsGpioModeEnable(uint8_t u8GpioNum) + * @brief This API is used to select the host pad gpios(25 to 30) + * @param[in] u8GpioNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_HostPadsGpioModeEnable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_host_pads_gpio_mode_enable(u8GpioNum); +#else + egpio_host_pads_gpio_mode_enable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_HostPadsGpioModeDisable(uint8_t u8GpioNum) + * @brief This API is used to deselect the host pad gpios(25 to 30) + * @param[in] u8GpioNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_HostPadsGpioModeDisable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_host_pads_gpio_mode_disable(u8GpioNum); +#else + egpio_host_pads_gpio_mode_disable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSelectionEnable(uint8_t padNum) + * @brief This API is used to select the pad(0 to 21) + * @param[in] padNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSelectionEnable(uint8_t padNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_selection_enable(padNum); +#else + egpio_pad_selection_enable(padNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSelectionDisable(uint8_t padNum) + * @brief This API is used to deselect the pad(0 to 21) + * @param[in] padNum : PAD number to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSelectionDisable(uint8_t padNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_selection_disable(padNum); +#else + egpio_pad_selection_disable(padNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadReceiverEnable(uint8_t u8GpioNum) + * @brief This API is used to enable the receiver enable bit(REN) + * @param[in] u8GpioNum : GPIO num to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadReceiverEnable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_receiver_enable(u8GpioNum); +#else + egpio_pad_receiver_enable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadReceiverDisable(uint8_t u8GpioNum) + * @brief This API is used to Disable the receiver enable bit(REN) + * @param[in] u8GpioNum : GPIO num to be use + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadReceiverDisable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_receiver_disable(u8GpioNum); +#else + egpio_pad_receiver_disable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSdioConnected(void) + * @brief This API is used to use the SDIO pins(25 to 30) in M4 or NWP (0 for M4SS and 1 for TASS) + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSdioConnected(void) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_sdio_connected(); +#else + egpio_pad_sdio_connected(); +#endif +} + +/** + * @fn void RSI_EGPIO_PadDriverDisableState(uint8_t u8GpioNum , en_driver_state_t endstate) + * @brief This API is used to control the Driver disabled state control + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] endstate : the value to be passed + * \n possible values are + * \n - 0 for \ref HiZ (P1=0,P2=0) + * \n - 1 for \ref Pullup (P1=0,P2=1) + * \n - 2 for \ref Pulldown (P1=1,P2=0) + * \n - 3 for \ref Repeater (P1=1,P2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadDriverDisableState(uint8_t u8GpioNum, en_driver_state_t endstate) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_driver_disable_state(u8GpioNum, endstate); +#else + egpio_pad_driver_disable_state(u8GpioNum, endstate); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadDriverStrengthSelect(uint8_t u8GpioNum , en_driver_strength_select_t strength) + * @brief This API is used to select Drive strength + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] strength : Drive strength selector(E1,E2) + * \n possible values are + * \n - 0 for \ref two_milli_amps (E1=0,E2=0) + * \n - 1 for \ref four_milli_amps (E1=0,E2=1) + * \n - 2 for \ref eight_milli_amps (E1=1,E2=0) + * \n - 3 for \ref twelve_milli_amps(E1=1,E2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadDriverStrengthSelect(uint8_t u8GpioNum, en_driver_strength_select_t strength) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_driver_strength_select(u8GpioNum, strength); +#else + egpio_pad_driver_strength_select(u8GpioNum, strength); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadPowerOnStartEnable(uint8_t u8GpioNum ,uint8_t val) + * @brief This API is used to select Power on Start enable + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : POS = 1 : Enables active pull down for invalid power; + * \n : POS = 0 : Active pull down capability disabled . + * \n When one of the power supplies is invalid and active high POS is set to 1, + * \n AD is pulled to weak 0. When POS is set to 0, PAD remains in a high-Z state. : Default 0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadPowerOnStartEnable(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_power_on_start_enable(u8GpioNum, val); +#else + egpio_pad_power_on_start_enable(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadActiveHighSchmittTrigger(uint8_t u8GpioNum ,uint8_t val) + * @brief Active high Schmitt trigger (Hysteresis) select; + * \n SMT=0 for No hysteresis; Default value for reset is 1'b1 and others is 1'b0 + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : SMT=0 : No hysteresis; Default value for reset is 1'b1 and others is 1'b0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadActiveHighSchmittTrigger(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_active_high_schmitt_trigger(u8GpioNum, val); +#else + egpio_pad_active_high_schmitt_trigger(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_PadSlewRateControll(uint8_t u8GpioNum ,uint8_t val) + * @brief this API is used to control the slew rate + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : slew rate + * \n - SR = 0 : Slow (half frequency) + \n - SR = 1 : Fast ,Default 1 + * @return None + */ +STATIC INLINE void RSI_EGPIO_PadSlewRateControll(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_pad_slew_rate_controll(u8GpioNum, val); +#else + egpio_pad_slew_rate_controll(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadReceiverEnable(uint8_t u8GpioNum) + * @brief This API is used to enable the REN for ULP + * @param[in] u8GpioNum : GPIO number to be used + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadReceiverEnable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_receiver_enable(u8GpioNum); +#else + egpio_ulp_pad_receiver_enable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadReceiverDisable(uint8_t u8GpioNum) + * @brief This API is used to enable the REN for ULP + * @param[in] u8GpioNum : GPIO number to be used + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadReceiverDisable(uint8_t u8GpioNum) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_receiver_disable(u8GpioNum); +#else + egpio_ulp_pad_receiver_disable(u8GpioNum); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadDriverDisableState(uint8_t u8GpioNum , en_ulp_driver_disable_state_t disablestate) + * @brief This API is used to control the Driver disabled state control + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] disablestate : the value to be passed + * \n possible values are + * \n - 0 for \ref HiZ (P1=0,P2=0) + * \n - 1 for \ref Pullup (P1=0,P2=1) + * \n - 2 for \ref Pulldown (P1=1,P2=0) + * \n - 3 for \ref Repeater (P1=1,P2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadDriverDisableState(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_driver_disable_state(u8GpioNum, disablestate); +#else + egpio_ulp_pad_driver_disable_state(u8GpioNum, disablestate); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadDriverStrengthSelect(uint8_t u8GpioNum , en_ulp_driver_strength_select_t strength) + * @brief this API is used to select Drive strength + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] strength : Drive strength selector(E1,E2) + * \n possible values are + * \n - 0 for \ref two_milli_amps (E1=0,E2=0) + * \n - 1 for \ref four_milli_amps (E1=0,E2=1) + * \n - 2 for \ref eight_milli_amps (E1=1,E2=0) + * \n - 3 for \ref twelve_milli_amps(E1=1,E2=1) + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadDriverStrengthSelect(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_driver_strength_select(u8GpioNum, strength); +#else + egpio_ulp_pad_driver_strength_select(u8GpioNum, strength); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadPowerOnStartEnable(uint8_t u8GpioNum ,uint8_t val ) + * @brief Power-on-Start enable; + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : POS = 1 : Enables active pull down for invalid power; + * \n : POS = 0 : Active pull down capability disabled . + * \n When one of the power supplies is invalid and active high POS is set to 1, + *PAD is pulled to weak 0. When POS is set to 0, PAD remains in a high Z state. : Default 0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadPowerOnStartEnable(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_power_on_start_enable(u8GpioNum, val); +#else + egpio_ulp_pad_power_on_start_enable(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadActiveHighSchmittTrigger(uint8_t u8GpioNum ,uint8_t val ) + * @brief Active high Schmitt trigger (Hysteresis) select; + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : SMT=0 : No hysteresis; Default value for reset is 1'b1 and others is 1'b0 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadActiveHighSchmittTrigger(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_active_high_schmitt_trigger(u8GpioNum, val); +#else + egpio_ulp_pad_active_high_schmitt_trigger(u8GpioNum, val); +#endif +} + +/** + * @fn STATIC INLINE void RSI_EGPIO_UlpPadSlewRateControll(uint8_t u8GpioNum ,uint8_t val ) + * @brief Slew Rate Control + * @param[in] u8GpioNum : GPIO number to be use + * @param[in] val : slew rate + * \n - SR = 0 : Slow (half frequency); SR = 1 for Fast , Default 1 + * @return None + */ +STATIC INLINE void RSI_EGPIO_UlpPadSlewRateControll(uint8_t u8GpioNum, uint8_t val) +{ +#if defined(ROMDRIVER_PRESENT) + ROMAPI_EGPIO_API->egpio_ulp_pad_slew_rate_controll(u8GpioNum, val); +#else + egpio_ulp_pad_slew_rate_controll(u8GpioNum, val); +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_ROM_EGPIO_H__*/ +/** @} */ +/* @}end of RSI_EGPIO_DRIVERS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h new file mode 100644 index 000000000..047b86484 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_power_save.h @@ -0,0 +1,331 @@ +/****************************************************************************** +* @file rsi_rom_power_save.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +// Includes + +#ifndef __RSI_ROM_POWER_SAVE_H__ +#define __RSI_ROM_POWER_SAVE_H__ + +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup POWER_SAVE + * @{ + * + */ +/** + * @fn STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs4toPs2(ULP_MODE_T enCtxSel , + * uint8_t PwrMuxSelUlpssRam , + * uint8_t pwrMuxSelM4UlpRam , + * uint8_t pwrMuxSelM4UlpRam16K , + * uint8_t pwrMuxSelM4Ulp , + * uint8_t pwrMuxSelUlpss , + * uint8_t bgSampleEnable , + * uint8_t dcDcEnable , + * uint8_t socLdoEnable , + * uint8_t standByDc + * ) + * @brief This API is used to used to change the power transition state from Power save state 4/3 to power save state 2 + * @param[in] enCtxSel : is Select enum for the context top ULP mode + * \n 00, 10 - \ref HP-MCU/LP-MCU Mode + * \n 01 - \ref ULP-MCU Mode + * \n 11 - \ref UULP-MCU Mode + * \n (1st 16K of M4 RAM is dedicated to IM, + * \n 2nd 16K of M4 RAM is dedicated to DM) + * @param[in] pwrMuxSelM4UlpRam : Select value for M4 ULP RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] PwrMuxSelUlpssRam :Select value for ULPSS RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4UlpRam16K : is Select value for M4 ULP RAM 16K Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4Ulp : is Select value for M4 ULP (Peripherals + CORTEX Core )Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelUlpss : is Select value for ULPSS(Peripherals) Power MUX + * \n 1 \ref SOC LDO + * \n 0 \ref SCDCDC 0.9 + * @param[in] bgSampleEnable : Value to enable or disable the bg Sample + * \n 0 :Disable + * \n 1 :Enale + * @param[in] dcDcEnable : Value to enable or disable the dcDcEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] socLdoEnable : Value to enable or disable the socLdoEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] standByDc : Value to enable or disable the standByDc + * \n 0 :Disable + * \n 1 :Enale + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs4toPs2(ULP_MODE_T enCtxSel, + uint8_t PwrMuxSelUlpssRam, + uint8_t pwrMuxSelM4UlpRam, + uint8_t pwrMuxSelM4UlpRam16K, + uint8_t pwrMuxSelM4Ulp, + uint8_t pwrMuxSelUlpss, + uint8_t bgSampleEnable, + uint8_t dcDcEnable, + uint8_t socLdoEnable, + uint8_t standByDc, + uint8_t taRamRetEnable, + uint8_t M4RamRetEnable) +{ + // TODO: Check silicon rev from flash/efuse offset; for 1.4V do this programming + if (SiliconRev >= 0x14) { + if (taRamRetEnable) { + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= HPSRAM_RET_ULP_MODE_EN; + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= TA_RAM_RETENTION_MODE_EN; + } + if (M4RamRetEnable) { + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= HPSRAM_RET_ULP_MODE_EN; + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= M4SS_RAM_RETENTION_MODE_EN; +#if !defined(SLI_SI917) && !defined(SLI_SI915) + M4CLK->CLK_ENABLE_SET_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + for (uint8_t x = 0; x < 10; x++) { + __ASM("NOP"); + } +#if !defined(SLI_SI917) && !defined(SLI_SI915) + M4CLK->CLK_ENABLE_CLR_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + } + } + // Moved this API from ROM to appication memmory + return ps_power_state_change_ps4tops2(enCtxSel, + PwrMuxSelUlpssRam, + pwrMuxSelM4UlpRam, + pwrMuxSelM4UlpRam16K, + pwrMuxSelM4Ulp, + pwrMuxSelUlpss, + bgSampleEnable, + dcDcEnable, + socLdoEnable, + standByDc); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs2toPs4(uint32_t PmuBuckTurnOnWaitTime , uint32_t SocLdoTurnOnWaitTime) + * @brief This API is used to change the power state from PS2 to PS4 + * @param[in] PmuBuckTurnOnWaitTime : PMU buck time + * @param[in] SocLdoTurnOnWaitTime : soc ldo turn on time + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t RSI_PS_PowerStateChangePs2toPs4(uint32_t PmuBuckTurnOnWaitTime, uint32_t SocLdoTurnOnWaitTime) +{ + // Moved this API from ROM to appication memmory + return ps_power_state_change_ps2_to_Ps4(PmuBuckTurnOnWaitTime, SocLdoTurnOnWaitTime); +} + +/** + * @fn void RSI_PS_ClrWkpUpStatus(uint32_t wakeUpIntrClear) + * @brief This API is used clear the NPSS/wake up interrupts. + * @param wakeUpIntrClear : OR'ed value of register bits of NPSS interrupt register + * @return none + */ +STATIC INLINE void RSI_PS_ClrWkpUpStatus(uint32_t wakeUpIntrClear) +{ +#if defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_clr_wkp_up_status(wakeUpIntrClear); +#else + ps_clr_wkp_up_status(wakeUpIntrClear); +#endif +} + +#if defined(SLI_SI917B0) || defined(SLI_SI915) + +STATIC INLINE void RSI_PS_RetentionSleepConfig_bypass(uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode) +{ + UNUSED_PARAMETER(vector_offset); + qspi_reg_t *qspi_reg2 = (qspi_reg_t *)M4SS_PSRAM_QSPI_BASE_ADDRESS; + if (mode == RSI_WAKEUP_WITH_RETENTION) { + *(uint32 *)RSI_WAKE_FROM_FLASH_JUMP_ADDR = jump_cb_address; + } else { + if (MCURET_BOOTSTATUS_REG & BIT(13) || (M4_BBFF_STORAGE1 & PSRAM_SEC_EN)) { + if (((((qspi_reg_t *)QSPI)->QSPI_AES_CONFIG) & QSPI_KEY_SIZE_256) + || ((qspi_reg2->QSPI_AES_CONFIG) & QSPI_KEY_SIZE_256)) { + M4_BBFF_STORAGE1 |= KEY_LENGTH; + } + } + M4_BBFF_STORAGE1 &= ~(0xffUL << STACK_AND_CB_ADDR_BIT_NO); + //! Keeping stack address with 2k granularity. + M4_BBFF_STORAGE1 |= (((stack_address >> 11) & 0xFF) << STACK_AND_CB_ADDR_BIT_NO); + + M4_BBFF_STORAGE1 |= STACK_AND_CB_ADDR_PRESENT_IN_BBFF; + } +} +#endif + +/** + * @fn STATIC INLINE void RSI_PS_RetentionSleepConfig(uint32_t stack_address, uint32_t jump_cb_address, uint32_t vector_offset,uint32_t mode) + * @brief This API is used configure the wake up parameter for retention sleep + * @param stack_address : + * @param jump_cb_address : + * @param stack_address : + * @param vector_offset : + * @param mode : Following are the possible parameters for this parameter + * \n \ref RSI_WAKEUP_FROM_FLASH_MODE : Wakes from flash with retention. Upon wake up control jumps to wake up handler in flash. + * In this mode ULPSS RAMs are used to store the stack pointer and wake up handler address. + * \n \ref RSI_WAKEUP_WITH_OUT_RETENTION : Without retention sleep common for both FLASH/RAM based execution. + * In this mode ULPSS RAMs are used to store the stack pointer and control block address. + * if stack_addr and jump_cb_addr are not valid then 0x2404_0C00 and 0x2404_0000 are used + * for stack and control block address respectively. + * + * \n \ref RSI_WAKEUP_WITH_RETENTION : With retention branches to wake up handler in RAM. + * In this mode ULPSS RAMs are used to store the wake up handler address. + * \n \ref RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM : In this mode ULPSS RAMs are not used by boot-loader instead it uses the NPSS battery flip flops. + * \n \ref RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM :In this mode ULPSS RAMs are not used by boot-loader. + * Instead it uses the NPSS battery flip flops to store the stack and derives the control block address by adding 0XC00 + * to the stack address stored in battery flops. + * @return none + */ +STATIC INLINE void RSI_PS_RetentionSleepConfig(uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode) +{ + +#if defined(SLI_SI917B0) || defined(SLI_SI915) + //!write magic numbers in retention ram content ulp memory start ,end addresses (work around for jtag mode powersave) + RETEN_RAM_CONTENT_START_LOCATION = 0xBEAFBEAF; + RETEN_RAM_CONTENT_END_LOCATION = 0xBEADBEAD; + + //!remove wakeup flash bit in ulpss ram if flash is not required upon wakuep + if (mode == SL_SI91X_MCU_WAKEUP_PSRAM_MODE) { + RETEN_RAM_CONTENT_WAKEUP_FLASH_BIT_LOCATION = 0x0; + } + + if ((mode == RSI_WAKEUP_WITH_RETENTION) || (mode == RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM)) { + RSI_PS_RetentionSleepConfig_bypass(stack_address, jump_cb_address, vector_offset, mode); + } else { + ROMAPI_PWR_API->RSI_GotoSleepWithRetention(stack_address, jump_cb_address, vector_offset, mode); + } +#else + ROMAPI_PWR_API->RSI_GotoSleepWithRetention(stack_address, jump_cb_address, vector_offset, mode); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_BgLdoConfig(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode) + * @brief This API is used configure the LP low power mode and vref for DCDC1p1_lp_500uA + * @param ldo_0p6_ctrl : vref for DCDC1p1_lp_500uA + * - 0 - 0.8V + * - 1 - 0.75V + * - 2 - 0.7V + * - 3 - 0.65V + * - 4 - 0.6V + * - 5 - 0.55V + * @param ldo_0p6_lp_mode : 1:enable low power mode, 0:otherwise in high power mode + * @return none + */ +STATIC INLINE void RSI_PS_BgLdoConfig(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode) +{ +#if defined(CHIP_9118) && defined(A11_ROM) && defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_bg_ldo_config(ldo_0p6_ctrl, ldo_0p6_lp_mode); +#else + ps_bg_ldo_config(ldo_0p6_ctrl, ldo_0p6_lp_mode); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_ConfigurTrimValues(uint16_t lf_ro_trim ,uint16_t lf_rc_trim , uint16_t hf_ro_trim ,uint16_t hf_rc_trim ,uint16_t bg_ptat_trim , uint16_t bg_trim) + * @brief This API is used configure the clock and bg trim values + * @param[in] lf_ro_trim : trim value for low frequency RO clock + * @param[in] lf_rc_trim : trim value for low frequency RC clock + * @param[in] hf_ro_trim : trim value for high frequency RO clock + * @param[in] hf_rc_trim : trim value for high frequency RC clock + * @param[in] bg_ptat_trim : trim value for bg ptat + * @param[in] bg_trim : trim value for bg(Band Gap) + * @return none + */ +STATIC INLINE void RSI_PS_ConfigurTrimValues(uint16_t lf_ro_trim, + uint16_t lf_rc_trim, + uint16_t hf_ro_trim, + uint16_t hf_rc_trim, + uint16_t bg_ptat_trim, + uint16_t bg_trim) +{ +#if defined(CHIP_9118) && defined(A11_ROM) && defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_configure_trim_values(lf_ro_trim, lf_rc_trim, hf_ro_trim, hf_rc_trim, bg_ptat_trim, bg_trim); +#else + ps_configure_trim_values(lf_ro_trim, lf_rc_trim, hf_ro_trim, hf_rc_trim, bg_ptat_trim, bg_trim); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_WirelessShutdown(void) + * @brief This API is used shut-down the wireless + * @return none + */ +STATIC INLINE void RSI_PS_WirelessShutdown(void) +{ + // Wireless shutdown should be called only on First/Reset boot + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.FIRST_BOOTUP_MCU_N_b == 0) { +#if defined(CHIP_9118) && defined(A11_ROM) && defined(PS_ROMDRIVER_PRESENT) + ROMAPI_PWR_API->ps_wireless_shutdown(); +#else + ps_wireless_shutdown(); +#endif + } +} + +/*end of file*/ + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_ROM_POWER_SAVE_H__*/ + +/* @}end of RSI_POWER_SAVE */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_rng.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_rng.h new file mode 100644 index 000000000..0f69311ef --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_rng.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* @file rsi_rom_rng.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#ifndef __RSI_ROM_RNG_H__ +#define __RSI_ROM_RNG_H__ + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RNG_DRIVERS + * @{ + * + */ +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @fn STATIC INLINE uint32_t RSI_RNG_Start(HWRNG_Type *pRNG, uint8_t rngMode) + * @brief This API is used to start the Random Number Generation + * @param[in] pRNG : Random Number Generator handler + * @param[in] rngMode : mode of the Random Number Generator + * - \ref RNG_TRUE_RANDOM - For True RNG + * - \ref RNG_PSEUDO_RANDOM - For Psudo RNG + * @return returns 0 \ref RSI_OK on success ,non zero on failure + * + */ +STATIC INLINE uint32_t RSI_RNG_Start(HWRNG_Type *pRNG, uint8_t rngMode) +{ +#if defined(RNG_ROMDRIVER_PRESENT) + return ROMAPI_RNG_API->rng_start(pRNG, rngMode); +#else + return rng_start(pRNG, rngMode); +#endif +} + +/** + * @fn STATIC INLINE void RSI_RNG_Stop(HWRNG_Type *pRNG) + * @brief This API is used to stop the Random Number Generation + * @param[in] pRNG : Random Number Generator handler + * @return none + */ +STATIC INLINE void RSI_RNG_Stop(HWRNG_Type *pRNG) +{ +#if defined(RNG_ROMDRIVER_PRESENT) + ROMAPI_RNG_API->rng_stop(pRNG); +#else + rng_stop(pRNG); +#endif +} + +/** + * @fn STATIC INLINE void RSI_RNG_GetBytes(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes) + * @brief This API is used to get the random number bytes + * @param[in] pRNG : Random Number Generator handler + * @param[in] numberOfBytes : Number of bytes to generate + * @param[out] randomBytes : variable or array to store generated random bytes + * @return none + */ +STATIC INLINE void RSI_RNG_GetBytes(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes) +{ +#if defined(RNG_ROMDRIVER_PRESENT) + ROMAPI_RNG_API->rng_get_bytes(pRNG, randomBytes, numberOfBytes); +#else + rng_get_bytes(pRNG, randomBytes, numberOfBytes); +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif + +/* @} end of RSI_RNG_DRIVERS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h new file mode 100644 index 000000000..e7a380622 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_table_si91x.h @@ -0,0 +1,1112 @@ +/****************************************************************************** +* @file rsi_rom_table_si91x.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_ROM_TABLE_RS9116_H__ +#define __RSI_ROM_TABLE_RS9116_H__ +#include "rsi_ccp_user_config.h" +#if defined(A11_ROM) +#include +#include "rsi_error.h" +#include "rsi_timers.h" +#include "rsi_ulpss_clk.h" +#include "rsi_pll.h" +#include "rsi_power_save.h" +#include "rsi_egpio.h" +#include "rsi_crc.h" +#include "rsi_ulpss_clk.h" +#include "rsi_qspi_proto.h" +#include "rsi_qspi.h" +#include "rsi_rng.h" +#include "rsi_gpdma.h" +#include "rsi_ct.h" +#include "rsi_timers.h" +#include "rsi_udma.h" +#include "rsi_reg_spi.h" +#include "rsi_processor_sensor.h" +#include "rsi_retention.h" +#include "rsi_temp_sensor.h" +#include "rsi_time_period.h" +#include "rsi_wwdt.h" +#include "rsi_ipmu.h" +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +#include "rsi_efuse.h" +#include "rsi_pwm.h" +#endif +#include "rsi_udma_wrapper.h" +#include "UDMA.h" +#include "USART.h" +#include "GSPI.h" +#include "SAI.h" +#include "I2C.h" +#include "SPI.h" +#ifdef __cplusplus +extern "C" { +#endif +/* @brief ROM indirect function structure */ + +///////////////////EGPIO////////////////////////// +typedef struct { + void (*egpio_set_dir)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, boolean_t dir); + void (*egpio_set_pin)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t val); + boolean_t (*egpio_get_pin)(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + boolean_t (*egpio_get_dir)(const EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_pin_int_sel)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t port, uint8_t pin); + void (*egpio_set_int_fall_edge_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_fall_edge_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_rise_edge_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_rise_edge_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_low_level_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_int_mask)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_int_un_mask)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_low_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_high_level_enable)(EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_set_int_high_level_disable)(EGPIO_Type *pEGPIO, uint8_t intCh); + uint8_t (*egpio_get_int_stat)(const EGPIO_Type *pEGPIO, uint8_t intCh); + void (*egpio_int_clr)(EGPIO_Type *pEGPIO, uint8_t intCh, uint8_t flags); + void (*egpio_set_pin_mux)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t mux); + void (*egpio_ulp_soc_gpio_mode)(ULPCLK_Type *pULPCLK, uint8_t gpio, uint8_t mode); + void (*egpio_set_port_mask)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_set_port_un_mask)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_port_masked_load)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_set_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_port_load)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_word_load)(EGPIO_Type *pEGPIO, uint8_t pin, uint16_t val); + void (*egpio_clr_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + void (*egpio_toggle_port)(EGPIO_Type *pEGPIO, uint8_t port, uint16_t val); + uint16_t (*egpio_get_port)(const EGPIO_Type *pEGPIO, uint8_t port); + void (*egpio_group_int_one_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_group_int_one_disable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_group_int_two_enable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_group_int_mask)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_un_Mask)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_enable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_disable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_level)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_edge)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_and)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_or)(EGPIO_Type *pEGPIO, uint8_t grpInt); + uint32_t (*egpio_group_int_stat)(const EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_wkeup_Enable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_wkeup_disable)(EGPIO_Type *pEGPIO, uint8_t grpInt); + void (*egpio_group_int_clr)(EGPIO_Type *pEGPIO, uint8_t grpInt, uint8_t flags); + void (*egpio_group_int_two_disable)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin); + void (*egpio_set_group_int_one_pol)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + void (*egpio_set_group_int_two_pol)(EGPIO_Type *pEGPIO, uint8_t port, uint8_t pin, uint8_t pol); + void (*egpio_host_pads_gpio_mode_enable)(uint8_t u8GpioNum); + void (*egpio_host_pads_gpio_mode_disable)(uint8_t u8GpioNum); + void (*egpio_pad_selection_enable)(uint8_t padNum); + void (*egpio_pad_selection_disable)(uint8_t padNum); + void (*egpio_pad_receiver_enable)(uint8_t u8GpioNum); + void (*egpio_pad_receiver_disable)(uint8_t u8GpioNum); + void (*egpio_pad_sdio_connected)(void); + void (*egpio_pad_driver_disable_state)(uint8_t u8GpioNum, en_driver_state_t endstate); + void (*egpio_pad_driver_strength_select)(uint8_t u8GpioNum, en_driver_strength_select_t strength); + void (*egpio_pad_power_on_start_enable)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_pad_active_high_schmitt_trigger)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_pad_slew_rate_controll)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_ulp_pad_receiver_enable)(uint8_t u8GpioNum); + void (*egpio_ulp_pad_receiver_disable)(uint8_t u8GpioNum); + void (*egpio_ulp_pad_driver_disable_state)(uint8_t u8GpioNum, en_ulp_driver_disable_state_t disablestate); + void (*egpio_ulp_pad_driver_strength_select)(uint8_t u8GpioNum, en_ulp_driver_strength_select_t strength); + void (*egpio_ulp_pad_power_on_start_enable)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_ulp_pad_active_high_schmitt_trigger)(uint8_t u8GpioNum, uint8_t val); + void (*egpio_ulp_pad_slew_rate_controll)(uint8_t u8GpioNum, uint8_t val); +} ROM_EGPIO_API_T; +///////////////////EGPIO END////////////////////////// + +/** @brief CRC ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + void (*crc_set_gen_control)(CRC_Type *pCRC); + uint32_t (*crc_get_gen_status)(CRC_Type *pCRC); + void (*crc_polynomial)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_polynomial_width)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + void (*crc_lfsr_init)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_use_swapped_init)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_set_data_width_type)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_set_fifo_thresholds)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + uint32_t (*crc_write_data)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams, uint32_t data); + uint32_t (*monitor_crc_calc)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRC_Params); + void (*crc_lfsr_dynamic_write)(CRC_Type *pCRC, RSI_CRC_PARAMS_T *pCRCParams); + void (*crc_reset_fifo)(CRC_Type *pCRC); + uint32_t (*crc_get_fifo_status)(CRC_Type *pCRC); +} ROM_CRC_API_T; +//////////////CRC END///////////////////////////// + +/** @brief RNG ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + uint32_t (*rng_start)(HWRNG_Type *pRNG, uint8_t rngMode); + void (*rng_stop)(HWRNG_Type *pRNG); + void (*rng_get_bytes)(HWRNG_Type *pRNG, uint32_t *randomBytes, uint32_t numberOfBytes); +} ROM_RNG_API_T; +///////////////RNG END////////////////// +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +/* @brief ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + void (*efuse_enable)(EFUSE_Type *pstcEfuse); + void (*efuse_Disable)(EFUSE_Type *pstcEfuse); + uint8_t (*efuse_read_data)(EFUSE_Type *pstcEfuse); + void (*efuse_write_addr)(EFUSE_Type *pstcEfuse, uint16_t u16Addr); + rsi_error_t (*efuse_write_bit)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t u8BitPos, uint32_t hold_time); + rsi_error_t (*efuse_fsm_read_byte)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + rsi_error_t (*efuse_mem_map_read_byte)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint8_t *pu8Byte, uint32_t SocClk); + rsi_error_t (*efuse_mem_map_read_word)(EFUSE_Type *pstcEfuse, uint16_t u16Addr, uint16_t *pu16Word, uint32_t SocClk); +} ROM_EFUSE_API_T; +///////////////EFUSE END////////////////// +#endif +typedef PRE_PACK struct POST_PACK { + void (*qspi_write_to_flash)(qspi_reg_t *qspi_reg, uint32_t len_in_bits, uint32_t cmd_addr_data, uint32_t cs_no); + void (*qspi_switch_qspi2)(qspi_reg_t *qspi_reg, uint32_t mode, uint32_t cs_no); + uint32_t (*qspi_wait_flash_status_Idle)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + void (*qspi_enable_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t flash_type, + spi_config_t *spi_config, + uint32_t cs_no); + void (*qspi_status_reg_write)(qspi_reg_t *qspi_reg, + uint32_t write_value, + spi_config_t *spi_config, + uint32_t wr_reg_delay_ms); + uint32_t (*qspi_flash_reg_read)(qspi_reg_t *qspi_reg, uint8_t reg_read_cmd, uint32_t cs_no, spi_config_t *spi_config); + void (*qspi_flash_reg_write)(qspi_reg_t *qspi_reg, + uint32_t reg_write_cmd, + uint32_t reg_write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + void (*qspi_set_flash_mode)(qspi_reg_t *qspi_reg, + uint32_t data_mode, + uint32_t cs_no, + uint32_t ddr_en, + uint32_t flash_type); + void (*qspi_config_qflash4_read)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t addr); + void (*qspi_manual_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t manual_udma_read, + void *udmaHandle, + void *gpdmaHandle); + void (*qspi_auto_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config); + void (*qspi_auto_read)(uint32_t cs_no, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + spi_config_t *spi_config, + uint32_t dma_flags); + void (*qspi_flash_init)(qspi_reg_t *qspi_reg, spi_config_t *spi_config, uint32_t wr_reg_delay_ms); + void (*qspi_spi_init)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t flash_init_req, + uint32_t wr_reg_delay_ms, + uint8_t fifo_thrsld); + void (*qspi_spi_erase)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t erase_cmd, + uint32_t blk_sec_addr, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms); + uint32_t (*qspi_spi_write)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t write_cmd, + uint32_t addr, + uint8_t *data, + uint32_t len_in_bytes, + uint16_t page_size, + uint32_t hsize, + uint32_t dis_hw_ctrl, + uint32_t wr_reg_delay_ms, + uint32_t check_en, + uint32_t udma_enable, + void *udmaHandle, + void *gpdmaHandle); + void (*qspi_spi_read)(qspi_reg_t *qspi_reg, + spi_config_t *spi_config, + uint32_t addr, + uint8_t *data, + uint32_t hsize, + uint32_t len_in_bytes, + uint32_t manual_udma_read, + void *udmaHandle, + void *gpdmaHandle); + void (*qspi_usleep)(uint32_t delay_us); //!< function ptr for halting processor for delay (us) specified + void (*qspi_write_block_protect)(qspi_reg_t *qspi_reg, + uint32_t protect, + uint32_t cs_no, + uint32_t num_prot_bytes, + uint32_t wr_reg_delay_ms); +#if defined(SLI_SI917) || defined(SLI_SI915) +#if defined(SLI_SI917B0) || defined(SLI_SI915) + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, + uint8_t mode, + uint32_t *key1, + uint32_t *key2, + uint32_t key_len, + uint32_t kh_enable); +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint8_t mode, uint32_t *key, uint32_t kh_enable); +#endif +#else + void (*qspi_qspiload_key)(qspi_reg_t *qspi_reg, uint32_t *key, uint32_t kh_enable); +#endif + void (*qspi_qspiload_nonce)(qspi_reg_t *qspi_reg, uint32_t *nonce); + void (*qspi_seg_sec_en)(qspi_reg_t *qspi_reg, uint32_t seg_no, uint32_t start_addr, uint32_t end_addr); + void (*qspi_status_control_reg_write)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint16_t write_command, + uint32_t addr, + uint16_t write_value, + uint32_t cs_no, + uint32_t wr_reg_delay_ms); + void (*qspi_flash_protection)(spi_config_t *spi_config, + qspi_reg_t *qspi_reg, + uint32_t protection, + uint32_t wr_reg_delay_ms); + void (*RSI_QSPI_ConfigQspiDll)(spi_config_t *spi_config, qspi_reg_t *qspi_reg); + void (*RSI_QSPI_ResetFlash)(qspi_reg_t *qspi_reg, uint32_t cs_no); + void (*RSI_QSPI_UpdateOperatingMode_and_ResetType)(qspi_reg_t *qspi_reg, uint32_t operating_mode); +} ROM_QSPI_API_T; +//////////////////////////QSPI END////////////////////////// + +/** @brief TIMERS ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + RSI_UDMA_HANDLE_T (*udma_init)(void *mem, const RSI_UDMA_INIT_T *pInit); + + uint32_t (*udma_get_channel_transfer_mode)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + rsi_error_t (*udma_setup_channel_transfer)(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, + void *pSrcAddr, + void *pDstAddr); + + rsi_error_t (*udma_set_channel_scatter_gather_transfer)(RSI_UDMA_HANDLE_T pHandle, + uint8_t dmaCh, + uint32_t taskCount, + void *pTaskList, + uint32_t transferType); + + uint32_t (*udma_get_channel_transfer_length)(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); + + rsi_error_t (*udma_setup_channel)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + + void (*udma_deInit)(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + + void (*udma_interrupt_handler)(RSI_UDMA_HANDLE_T pHandle); + + rsi_error_t (*udma_interrupt_enable)(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh); + +} ROM_UDMA_API_T; + +//////////////////////////UDMA END////////////////////////// + +//////////////////////////UDMA WRAPPERS ////////////////////////// +typedef PRE_PACK struct POST_PACK { + RSI_UDMA_HANDLE_T(*uDMAx_Initialize) + (const UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, RSI_UDMA_HANDLE_T udmaHandle, uint32_t *mem); + int32_t (*uDMAx_Uninitialize)(const UDMA_RESOURCES *udma); + int32_t (*uDMAx_ChannelConfigure)(const UDMA_RESOURCES *udma, + uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + RSI_UDMA_CHA_CONFIG_DATA_T control, + const RSI_UDMA_CHA_CFG_T *config, + UDMA_SignalEvent_t cb_event, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_ChannelEnable)(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_DMAEnable)(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*uDMAx_ChannelDisable)(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*uDMAx_ChannelGetCount)(uint8_t ch, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T config, + const UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + void (*uDMAx_IRQHandler)(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info); + +} ROM_UDMA_WRAPPER_API_T; +//////////////////////////UDMA WRAPPERS END////////////////////////// +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +typedef PRE_PACK struct POST_PACK { + rsi_error_t (*mcpwm_counter_reset)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_channel_reset)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_start)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_stop)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum); + + rsi_error_t (*mcpwm_set_time_period)(RSI_MCPWM_T *pMCPWM, uint8_t chnlNum, uint16_t period, uint16_t initVal); + + void (*mcpwm_special_event_trigger_config)(RSI_MCPWM_T *pMCPWM, + boolean_t svtDir, + RSI_MCPWM_SVT_CONFIG_T *pMCPWMSVTConfig); + + rsi_error_t (*mcpwm_dead_time_value_set)(RSI_MCPWM_T *pMCPWM, + RSI_MCPWM_DT_CONFIG_T *pMCPWMDeadTimeConfig, + uint8_t chnlNum); + + rsi_error_t (*mcpwm_period_control_config)(RSI_MCPWM_T *pMCPWM, + uint32_t postScale, + uint32_t preScale, + uint8_t chnlNum); + + rsi_error_t (*mcpwm_fault_avalue_set)(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + + rsi_error_t (*mcpwm_fault_bvalue_set)(RSI_MCPWM_T *pMCPWM, uint8_t pwmOutput, uint8_t value); + + rsi_error_t (*mcpwm_set_base_timer_mode)(RSI_MCPWM_T *pMCPWM, uint8_t mode, uint8_t chnlNum); + + rsi_error_t (*mcpwm_set_output_mode)(RSI_MCPWM_T *pMCPWM, boolean_t mode, uint8_t chnlNum); + + void (*mcpwm_set_output_polarity)(RSI_MCPWM_T *pMCPWM, boolean_t polL, boolean_t polH); + + void (*mcpwm_interrupt_handler)(RSI_MCPWM_T *pMCPWM, RSI_MCPWM_CALLBACK_T *pCallBack); + +} ROM_MCPWM_API_T; +#endif +////////////MCPWM END/////////////////////// + +/* RPDMA Function Pointer Table */ +typedef PRE_PACK struct POST_PACK { + uint32_t (*gpdma_get_mem_size)(void); + + RSI_GPDMA_HANDLE_T (*gpdma_init)(void *mem, const RSI_GPDMA_INIT_T *pInit); + + void (*gpdma_register_callback)(RSI_GPDMA_HANDLE_T pHandle, uint32_t cbIndex, gpdmaTransferCompleteCB pCB); + + rsi_error_t (*gpdma_abort_channel)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + + rsi_error_t (*gpdma_setup_channel)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_build_descriptors)(RSI_GPDMA_HANDLE_T pHandle, + RSI_GPDMA_DESC_T *pXferCfg, + RSI_GPDMA_DESC_T *pDesc, + RSI_GPDMA_DESC_T *pDescPrev); + + rsi_error_t (*gpdma_setup_channelTransfer)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh, RSI_GPDMA_DESC_T *pDesc); + + void (*gpdma_interrupt_handler)(RSI_GPDMA_HANDLE_T pHandle); + + void (*gpdma_deInit)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_dma_channel_trigger)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + + uint32_t (*gpdma_channel_is_enabled)(RSI_GPDMA_HANDLE_T pHandle, uint8_t dmaCh); + + rsi_error_t (*gpdma_interrupt_disable)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_interrupt_enable)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_error_status_clear)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + uint32_t (*gpdma_get_error_status)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + rsi_error_t (*gpdma_interrupt_clear)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + + uint32_t (*gpdma_interrupt_status)(RSI_GPDMA_HANDLE_T pHandle, RSI_GPDMA_CHA_CFG_T *pCfg); + +} ROM_RPDMA_API_T; +///////////////////////////GPDMA END///////////////////// + +/** @brief TIMERS ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + rsi_error_t (*timers_microsec_timer_config)(RSI_TIMERS_T *pTIMER, + uint8_t timerNum, + uint16_t integer, + uint8_t fractional, + uint8_t mode); + uint32_t (*timers_read_timer)(RSI_TIMERS_T *pTIMER, uint8_t timerNum, boolean_t countDir); +} ROM_TIMERS_API_T; + +////////////////////////////TIMERS END/////////////////////// + +//USART +typedef PRE_PACK struct POST_PACK { + int32_t (*USART_Initialize)(ARM_USART_SignalEvent_t cb_event, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*USART_Uninitialize)(USART_RESOURCES *usart, UDMA_RESOURCES *udma); + int32_t (*USART_PowerControl)(ARM_POWER_STATE state, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*USART_SetBaudrate)(uint32_t baudrate, uint32_t baseClk, USART_RESOURCES *usart); + int32_t (*USART_Send_Data)(const void *data, + uint32_t num, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*USART_Receive_Data)(const void *data, + uint32_t num, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*USART_Transfer)(const void *data_out, + void *data_in, + uint32_t num, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*USART_GetTxCount)(USART_RESOURCES *usart); + uint32_t (*USART_GetRxCount)(USART_RESOURCES *usart); + int32_t (*USART_Control)(uint32_t control, + uint32_t arg, + uint32_t baseClk, + USART_RESOURCES *usart, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + ARM_USART_STATUS (*USART_GetStatus)(USART_RESOURCES *usart); + int32_t (*USART_SetModemControl)(ARM_USART_MODEM_CONTROL control, USART_RESOURCES *usart); + ARM_USART_MODEM_STATUS (*USART_GetModemStatus)(USART_RESOURCES *usart); + void (*UartIrqHandler)(USART_RESOURCES *usart); + void (*USART_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, USART_RESOURCES *usart); + void (*USART_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, USART_RESOURCES *usart); +} ROM_USART_API_T; +//////////////////////USART END//////////////////// + +//GPSI +typedef PRE_PACK struct POST_PACK { + int32_t (*GSPI_Initialize)(ARM_SPI_SignalEvent_t cb_event, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*GSPI_Uninitialize)(const GSPI_RESOURCES *gspi, UDMA_RESOURCES *udma); + int32_t (*GSPI_PowerControl)(ARM_POWER_STATE state, const GSPI_RESOURCES *gspi); +#if defined(SLI_SI917B0) || defined(SLI_SI915) + int32_t (*GSPI_Control)(uint32_t control, + uint32_t arg, + const GSPI_RESOURCES *gspi, + uint32_t base_clock, + uint8_t spi_slavenumber); +#else + int32_t (*GSPI_Control)(uint32_t control, uint32_t arg, const GSPI_RESOURCES *gspi, uint32_t base_clock); +#endif + int32_t (*GSPI_Send)(const void *data, + uint32_t num, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*GSPI_Receive)(void *data, + uint32_t num, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*GSPI_Transfer)(const void *data_out, + void *data_in, + uint32_t num, + const GSPI_RESOURCES *gspi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*GSPI_GetDataCount)(const GSPI_RESOURCES *gspi); + void (*GSPI_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, GSPI_RESOURCES *gspi); + void (*GSPI_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, GSPI_RESOURCES *gspi); + void (*GSPI_IRQHandler)(const GSPI_RESOURCES *gspi); +} ROM_GSPI_API_T; +////////////////////////////GSPI END////////////////////////// + +//i2s +typedef PRE_PACK struct POST_PACK { + int32_t (*I2S_Initialize)(ARM_SAI_SignalEvent_t cb_event, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*I2S_Uninitialize)(I2S_RESOURCES *i2s, UDMA_RESOURCES *udma); + int32_t (*I2S_PowerControl)(ARM_POWER_STATE state, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*I2S_Send)(const void *data, + uint32_t num, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*I2S_Receive)(void *data, + uint32_t num, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*I2S_GetTxCount)(I2S_RESOURCES *i2s); + uint32_t (*I2S_GetRxCount)(I2S_RESOURCES *i2s); + int32_t (*I2S_Control)(uint32_t control, + uint32_t arg1, + uint32_t arg2, + I2S_RESOURCES *i2s, + UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle); + ARM_SAI_STATUS (*I2S_GetStatus)(I2S_RESOURCES *i2s); + void (*I2S_IRQHandler)(I2S_RESOURCES *i2s); + void (*I2S_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, I2S_RESOURCES *i2s); + void (*I2S_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, I2S_RESOURCES *i2s); +} ROM_I2S_API_T; +////////////////////////////I2S END//////////////////////// + +//I2C +typedef PRE_PACK struct POST_PACK { + int32_t (*I2Cx_Initialize)(ARM_I2C_SignalEvent_t cb_event, I2C_RESOURCES *i2c); + int32_t (*I2Cx_Uninitialize)(I2C_RESOURCES *i2c); + int32_t (*I2Cx_PowerControl)(ARM_POWER_STATE state, I2C_RESOURCES *i2c); + int32_t ( + *I2Cx_MasterTransmit)(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c); + int32_t (*I2Cx_MasterReceive)(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, I2C_RESOURCES *i2c); + int32_t (*I2Cx_SlaveTransmit)(const uint8_t *data, uint32_t num, I2C_RESOURCES *i2c); + int32_t (*I2Cx_SlaveReceive)(uint8_t *data, uint32_t num, I2C_RESOURCES *i2c); + int32_t (*I2Cx_GetDataCount)(I2C_RESOURCES *i2c); + int32_t (*I2Cx_Control)(uint32_t control, uint32_t arg, I2C_RESOURCES *i2c, uint32_t clock); + ARM_I2C_STATUS (*I2Cx_GetStatus)(I2C_RESOURCES *i2c); + uint32_t (*I2Cx_MasterHandler)(I2C_RESOURCES *i2c); + uint32_t (*I2Cx_SlaveHandler)(I2C_RESOURCES *i2c); + void (*I2Cx_IRQHandler)(I2C_RESOURCES *i2c); +} ROM_I2C_API_T; +///////////////////I2C END///////////////// +#if 0 +typedef PRE_PACK struct POST_PACK + { + void (* rsi_arm_offset_f32_opt)(int32_t *pSrc, int32_t scale, int32_t *pDst,uint32_t length,uint16_t inBank, uint16_t outBank ); + + void (* rsi_arm_offset_q7_opt)( q7_t *pSrc, q7_t scale, q7_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_offset_q15_opt)( q15_t *pSrc, q15_t scale, q15_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_offset_q31_opt)( q31_t *pSrc, q31_t scale, q31_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_sub_q7)(q7_t *pSrc,q7_t scale,q7_t *pDst, uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_sub_q31)(q31_t *pSrc,q31_t scale,q31_t *pDst, uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_sub_f32)( int32_t *pSrc, int32_t scale,int32_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_f32_opt)( int32_t *pSrc,int32_t scale,int32_t *pDst, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_q7_opt)( q7_t *pSrc,q7_t scaleFract,int8_t shift,q7_t *pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_q15_opt)( q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_arm_scale_q31_opt)( q31_t * pSrc,q31_t scaleFract, int8_t shift,q31_t * pDst,uint32_t blockSize,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_scalar_mul_q15)(q15_t *pSrc,q15_t *scale,uint32_t blockSize, typ_data_t typ_data,uint16_t inBank, uint16_t outBank ); + + void (* rsi_arm_add_f32_opt)( int32_t *pSrcA, int32_t *pSrcB,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_add_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_add_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_add_q31_opt)( q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_vector_add_q15)(q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize, typ_data_t typ_data,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_sub_f32_opt)(int32_t *pSrcA, int32_t *pSrcB,int32_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_sub_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_sub_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (*rsi_arm_sub_q31_opt)( q31_t *pSrcA, q31_t *pSrcB,q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_read_data)( uint32_t bank,uint32_t length,volatile void *pDst, uint8_t data_type,typ_data_t type_data); + + void (* rsi_fim_vector_sub_q15)( q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize,typ_data_t typ_data,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_f32_opt)( int32_t *pIn1,int32_t *pIn2, uint32_t SatTruncRound,uint32_t length,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_q7_opt)( q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_q15_opt)( q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_mult_q31_opt)(q31_t *pSrcA,q31_t *pSrcB,q31_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_vector_mul_q15)( q15_t *pIn1, q15_t *pIn2,q15_t *pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_cmplx_mult_real_q15_opt)(q15_t *pSrcCmplx,q15_t *pSrcReal,q15_t *pDst,uint32_t numSamples,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_cmplx_mult_cmplx_q15_opt)(q15_t * pSrcA,q15_t * pSrcB,q15_t *pDst,uint32_t numSamples,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_cmplx_mag_squared_q15_opt)(q15_t *pSrc,q15_t *pDst,uint32_t numSamples,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_q7)( q7_t *pSrc,uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_q15)( q15_t *pSrc, uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_q31)( q31_t *pSrc,uint32_t length,uint16_t inBank, uint16_t outBank); + + void (* rsi_fim_absSqr_f32)(int32_t *pSrc, uint32_t length,uint16_t inBank, uint16_t outBank); + + rsi_error_t (* rsi_arm_mat_mult_f32_opt)( const arm_matrix_instance_f32_opt *pSrcA, + const arm_matrix_instance_f32_opt *pSrcB,arm_matrix_instance_f32_opt *pDst,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + rsi_error_t (* rsi_arm_mat_mult_q31_opt)( const arm_matrix_instance_q31_opt * pSrcA,const arm_matrix_instance_q31_opt * pSrcB, + arm_matrix_instance_q31_opt * pDst,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + rsi_error_t (* rsi_arm_mat_mult_q15_opt)( const arm_matrix_instance_q15_opt * pSrcA, + const arm_matrix_instance_q15_opt * pSrcB,arm_matrix_instance_q15_opt * pDst,q15_t * pState + ,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_f32_opt)( arm_fir_instance_f32_opt *S, uint16_t numTaps,int32_t *pCoeffs, int32_t *pState, + uint32_t blockSize); + + void (* rsi_arm_fir_f32_opt)( arm_fir_instance_f32_opt *S, int32_t *pSrc, int32_t *pDst, + uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_q31_opt)( arm_fir_instance_q31_opt *S,uint16_t numTaps,q31_t *pCoeffs, + q31_t *pState, uint32_t blockSize); + + void (* rsi_arm_fir_q31_opt)( arm_fir_instance_q31_opt *S, q31_t *pSrc,q31_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_q15_opt)( arm_fir_instance_q15_opt *S,uint16_t numTaps,q15_t *pCoeffs, + q15_t *pState, uint32_t blockSize); + + void (* rsi_arm_fir_q15_opt)( arm_fir_instance_q15_opt *S, q15_t *pSrc,q15_t *pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_arm_fir_init_q7_opt)( arm_fir_instance_q7_opt *S,uint16_t numTaps,q7_t *pCoeffs, + q7_t *pState, uint32_t blockSize); + + void (* rsi_arm_fir_q7_opt)( arm_fir_instance_q7_opt *S, q7_t *pSrc,q7_t *pDst, + uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + void (* rsi_fim_interrupt_handler)(volatile FIM_Type *ptFim); + + void (* rsi_arm_fir_interpolate_f32_opt)( const arm_fir_interpolate_instance_f32_opt * S, int32_t * pSrc, + int32_t * pDst,uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + arm_status (* rsi_arm_fir_interpolate_init_f32_opt)( arm_fir_interpolate_instance_f32_opt * S, + uint8_t L, uint16_t numTaps, int32_t * pCoeffs, + int32_t * pState,uint32_t blockSize ); + + arm_status (* rsi_arm_fir_interpolate_init_q15_opt)( arm_fir_interpolate_instance_q15_opt * S,uint8_t L, + uint16_t numTaps,q15_t * pCoeffs,q15_t * pState, + uint32_t blockSize ); + + arm_status (* rsi_arm_fir_interpolate_init_q31_opt)( arm_fir_interpolate_instance_q31_opt *S, uint8_t L, + uint16_t numTaps,q31_t * pCoeffs, q31_t * pState, + uint32_t blockSize ); + + void (* rsi_arm_fir_interpolate_q15_opt)( arm_fir_interpolate_instance_q15_opt * S,q15_t * pSrc,q15_t *pDst, + uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + + + void (* rsi_arm_fir_interpolate_q31_opt)( const arm_fir_interpolate_instance_q31_opt * S, q31_t * pSrc, + q31_t * pDst, uint32_t blockSize,uint16_t inBank1, uint16_t inBank2, uint16_t outBank); + }ROM_FIM_API_T; + +/////////////////////FIM END////////////////////// +#endif +typedef PRE_PACK struct POST_PACK { + void (*ct_ocu_high_Low_toggle_select)(RSI_CT_T *pCT, boolean_t lowHigh, boolean_t counterNum, uint8_t outputSel); + rsi_error_t (*ct_wfg_control_config)(RSI_CT_T *pCT, WFG_PARAMS_T ctrlReg); + rsi_error_t (*ct_ocu_control)(RSI_CT_T *pCT, + boolean_t counterNum, + boolean_t dmaEn, + OCU_PARAMS_T *pOCUparams, + RSI_CT_CALLBACK_T *pCB); + + rsi_error_t (*ct_wfg_comapre_value_set)(RSI_CT_T *pCT, boolean_t counterNum, OCU_PARAMS_T *pOCUparams); +} ROM_CT_API_T; + +///////////////////////CT END/////////////////////////////////// +/** @brief SPI master ROM indirect function structure */ +typedef PRE_PACK struct POST_PACK { + void (*ps_clr_wkp_up_status)(uint32_t wakeUpIntrClear); + void (*ps_bg_ldo_config)(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode); + void (*ps_configure_trim_values)(uint16_t lf_ro_trim, + uint16_t lf_rc_trim, + uint16_t hf_ro_trim, + uint16_t hf_rc_trim, + uint16_t bg_ptat_trim, + uint16_t bg_trim); + void (*ps_wireless_shutdown)(void); + uint32_t (*RSI_SelectTaBootOption)(uint32_t option); + void (*RSI_GotoSleepWithRetention)(uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode); + void (*RSI_WakeupWirelessProcessor)(void); +} ROM_PWR_API_T; +///////////////////////POWERSAVE END/////////////////////////// + +typedef PRE_PACK struct POST_PACK { + rsi_error_t (*ulpss_clock_config)(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); + + rsi_error_t (*ulpss_ulp_peri_clk_enable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_peri_clk_disable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_dyn_clk_enable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_dyn_clk_disable)(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + + rsi_error_t (*ulpss_ulp_ssi_clk_config)(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor); + + rsi_error_t (*ulpss_ulp_i2s_clk_config)(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); + + rsi_error_t (*ulpss_ulp_uar_clk_config)(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor); + + rsi_error_t (*ulpss_time_clk_disable)(ULPCLK_Type *pULPCLK); + rsi_error_t (*ulpss_time_clk_config)(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime); + + rsi_error_t (*ulpss_aux_clk_config)(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); + + rsi_error_t (*ulpss_vad_clk_config)(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor); + + rsi_error_t (*ulpss_touch_clk_config)(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); + + rsi_error_t (*ulpss_slp_sensor_clk_config)(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); + + rsi_error_t (*ulpss_peripheral_enable)(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + + rsi_error_t (*ulpss_peripheral_disable)(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); + +} ROM_ULPSS_CLK_API_T; + +////////////////////////////ULPSS CLOCKS END///////////////////////////////// + +typedef PRE_PACK struct POST_PACK { + boolean_t (*clk_check_pll_lock)(PLL_TYPE_T pllType); + rsi_error_t (*clk_soc_pll_clk_enable)(boolean_t clkEnable); + rsi_error_t (*clk_set_soc_pll_freq)(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk); + rsi_error_t (*clk_soc_pll_set_freq_div)(const M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg); + rsi_error_t (*clk_soc_pll_clk_set)(const M4CLK_Type *pCLK); + rsi_error_t (*clk_soc_pll_clk_bypass_enable)(boolean_t clkEnable); + rsi_error_t (*clk_soc_pll_clk_reset)(void); + rsi_error_t (*clk_soc_pll_pd_enable)(boolean_t en); + rsi_error_t (*clk_soc_pll_turn_off)(void); + rsi_error_t (*clk_soc_pll_turn_on)(void); + rsi_error_t (*clk_i2s_pll_clk_enable)(boolean_t clkEnable); + rsi_error_t (*clk_i2s_pll_clk_bypass_enable)(boolean_t clkEnable); + rsi_error_t (*clk_i2s_pll_pd_enable)(boolean_t en); + rsi_error_t (*clk_i2s_pll_turn_off)(void); + rsi_error_t (*clk_i2s_pll_turn_on)(void); + rsi_error_t (*clk_set_i2s_pll_freq)(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal); + rsi_error_t (*clk_i2s_pll_set_freq_div)(const M4CLK_Type *pCLK, + uint16_t u16DivFactor1, + uint16_t u16DivFactor2, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF); + rsi_error_t (*clk_i2s_pll_clk_set)(const M4CLK_Type *pCLK); + rsi_error_t (*clk_i2s_pll_clk_reset)(void); + rsi_error_t (*clk_intf_pll_clk_enable)(boolean_t clkEnable); + rsi_error_t (*clk_intf_pll_pd_enable)(boolean_t en); + rsi_error_t (*clk_intf_pll_turn_off)(void); + rsi_error_t (*clk_set_intf_pll_freq)(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk); + rsi_error_t (*clk_intf_pll_set_freq_div)(const M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg); + rsi_error_t (*clk_intf_pll_clk_bypass_enable)(boolean_t clkEnable); + rsi_error_t (*clk_intf_pll_turn_on)(void); + rsi_error_t (*clk_intf_pll_clk_reset)(void); + rsi_error_t (*clk_intf_pll_clk_set)(const M4CLK_Type *pCLK); + rsi_error_t (*clk_peripheral_clk_enable1)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_disable1)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_enable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_disable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_enable3)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_peripheral_clk_disable3)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_disable)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_disable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_enable)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*clk_dynamic_clk_gate_enable2)(M4CLK_Type *pCLK, uint32_t flags); + rsi_error_t (*ulpss_enable_ref_clks)(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn); + rsi_error_t (*ulpss_disable_ref_clks)(REF_CLK_ENABLE_T clk_type); + rsi_error_t (*clk_qspi_clk_config)(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor); + rsi_error_t (*clk_usart_clk_config)(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + boolean_t FracDivEn, + EN_USART_T EN_USART_T, + USART_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); + rsi_error_t (*clk_ssi_mst_clk_config)(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + SSI_MST_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); +#if !defined(SLI_SI917) && !defined(SLI_SI915) + rsi_error_t (*clk_sd_mem_clk_config)(M4CLK_Type *pCLK, + boolean_t swalloEn, + SDMEM_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); +#endif + rsi_error_t (*clk_ct_clk_config)(M4CLK_Type *pCLK, + CT_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType); +#if !defined(SLI_SI917) && !defined(SLI_SI915) + rsi_error_t (*clk_cci_clk_config)(M4CLK_Type *pCLK, + CCI_CLK_SRC_SEL_T clkSource, + uint32_t divFactor, + CLK_ENABLE_T clkType); +#endif + rsi_error_t (*clk_i2s_clk_config)(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor); + rsi_error_t (*clk_mcu_clk_cut_config)(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor); +#if !defined(SLI_SI917) && !defined(SLI_SI915) + rsi_error_t (*clk_can_clk_config)(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType); + rsi_error_t (*clk_ethernet_clk_config)(M4CLK_Type *pCLK, + boolean_t swalloEn, + ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor); +#endif + rsi_error_t (*clk_m4_soc_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); + rsi_error_t (*clk_qspi_clk_div)(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor); + rsi_error_t (*clk_ct_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); + rsi_error_t (*clk_ssi_mst_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); +#if !defined(SLI_SI917) && !defined(SLI_SI915) + rsi_error_t (*clk_cci_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); +#endif + rsi_error_t (*clk_i2s_clk_div)(M4CLK_Type *pCLK, uint32_t divFactor); +#if !defined(SLI_SI917) && !defined(SLI_SI915) + rsi_error_t (*clk_sd_mem_clk_div)(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor); +#endif + rsi_error_t (*clk_usart_clk_div)(M4CLK_Type *pCLK, EN_USART_T EN_USART_T, uint8_t u8FracDivEn, uint32_t divFactor); + uint32_t (*clk_slp_clk_calib_config)(M4CLK_Type *pCLK, uint8_t clkCycles); + rsi_error_t (*clk_gspi_clk_config)(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel); + rsi_error_t (*clk_slp_clk_config)(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc); + rsi_error_t (*clk_i2c_clk_config)(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C); + rsi_error_t (*clk_xtal_clk_config)(uint8_t xtalPin); +#if !defined(SLI_SI917) && !defined(SLI_SI915) + rsi_error_t (*clk_usb_clk_config)(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor); +#endif + rsi_error_t (*clk_peripheral_clk_enable)(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + rsi_error_t (*clk_peripheral_clk_disable)(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module); + void (*clk_config_pll_lock)(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit); + void (*clk_config_pll_ref_clk)(uint8_t ref_clk_src); +#if defined(SLI_SI917B0) || defined(SLI_SI915) + rsi_error_t (*clk_qspi_2_clk_config)(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor); +#endif +} ROM_M4SS_CLK_API_T; + +//////////////////////////M4 CLOCKS END/////////////////////// + +///////////////SSI///////////////////////////////// +typedef PRE_PACK struct POST_PACK { + int32_t (*SPI_Initialize)(ARM_SPI_SignalEvent_t cb_event, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T *udmaHandle, + uint32_t *mem); + int32_t (*SPI_Uninitialize)(const SPI_RESOURCES *spi, UDMA_RESOURCES *udma); + int32_t (*SPI_PowerControl)(ARM_POWER_STATE state, const SPI_RESOURCES *spi); + int32_t (*SPI_Send)(const void *data, + uint32_t num, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*SPI_Receive)(void *data, + uint32_t num, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + int32_t (*SPI_Transfer)(const void *data_out, + void *data_in, + uint32_t num, + const SPI_RESOURCES *spi, + UDMA_RESOURCES *udma, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle); + uint32_t (*SPI_GetDataCount)(const SPI_RESOURCES *spi); +#if defined(SLI_SI917B0) || defined(SLI_SI915) + int32_t (*SPI_Control)(uint32_t control, + uint32_t arg, + const SPI_RESOURCES *spi, + uint32_t base_clock, + uint8_t spi_slavenumber); +#else + int32_t (*SPI_Control)(uint32_t control, uint32_t arg, const SPI_RESOURCES *spi, uint32_t base_clock); +#endif + ARM_SPI_STATUS (*SPI_GetStatus)(const SPI_RESOURCES *spi); + void (*SPI_UDMA_Tx_Event)(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi); + void (*SPI_UDMA_Rx_Event)(uint32_t event, uint8_t dmaCh, SPI_RESOURCES *spi); + void (*SPI_IRQHandler)(const SPI_RESOURCES *spi); +} ROM_SSI_API_T; +//////////////////SSI END////////////////////////// + +typedef struct { + const ROM_EGPIO_API_T *pEGPIOROM; /*!< EGPIO driver API function table base address */ + const ROM_TIMERS_API_T *pTIMERSROM; /*!< TIMERS driver API function table base address */ + const ROM_UDMA_API_T *pUDMAROM; /*!< UDMA driver API function table base address */ + const ROM_UDMA_WRAPPER_API_T *pUDMAWRAPPERROM; + const ROM_CT_API_T *pCTROM; /*!< SCT driver API function table base address */ + const ROM_RPDMA_API_T *pRPDMAROM; + const ROM_PWR_API_T *pPWR; + const ROM_M4SS_CLK_API_T *pM4SSCLK; + const ROM_ULPSS_CLK_API_T *pULPSSCLK; + const ROM_QSPI_API_T *pQSPIROM; +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + const ROM_EFUSE_API_T *pEFUSEROM; +#endif + const ROM_CRC_API_T *pCRCROM; + const ROM_RNG_API_T *pRNGROM; +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + const ROM_MCPWM_API_T *pMCPWMROM; +#endif + const ROM_USART_API_T *pUSARTROM; + const ROM_GSPI_API_T *pGSPIROM; + const ROM_I2S_API_T *pI2SROM; + const ROM_I2C_API_T *pI2CROM; +#ifdef CHIP_9118 + const struct ROM_WL_API_S *pWLROM; +#endif +#if defined(SLI_SI917) || defined(SLI_SI915) + const ROM_SSI_API_T *pSSIROM; +#endif +} RSI_ROM_API_T; + +/*ROM base address */ +#define RSI_ROM_API_BASE_LOC (0x00300100) + +#define RSI_ROM_API ((RSI_ROM_API_T *)RSI_ROM_API_BASE_LOC) +/* Pointer to EGPIO peripheral driver functions in ROM */ +#define ROMAPI_EGPIO_API ((RSI_ROM_API)->pEGPIOROM) + +/* Pointer to Timers peripheral driver functions in ROM */ +#define ROMAPI_TIMER_API ((RSI_ROM_API)->pTIMERSROM) + +/* Pointer to UDMA peripheral driver functions in ROM */ +#define ROMAPI_UDMA_API ((RSI_ROM_API)->pUDMAROM) + +#define ROMAPI_UDMA_WRAPPER_API ((RSI_ROM_API)->pUDMAWRAPPERROM) + +/* Pointer to SCT peripheral driver functions in ROM */ +#define ROMAPI_CT_API ((RSI_ROM_API)->pCTROM) + +/* Pointer to RPDMA peripheral driver functions in ROM */ +#define ROMAPI_GPDMA_API ((RSI_ROM_API)->pRPDMAROM) + +/* Pointer to POWER driver functions in ROM */ +#define ROMAPI_PWR_API ((RSI_ROM_API)->pPWR) + +/* Pointer to M4SS CLOCKS driver functions in ROM */ +#define ROMAPI_M4SS_CLK_API ((RSI_ROM_API)->pM4SSCLK) + +/*ULP clocks*/ +#define ROMAPI_ULPSS_CLK_API ((RSI_ROM_API)->pULPSSCLK) + +/* Pointer to QSPI peripheral driver functions in ROM */ +#define ROMAPI_QSPI_API ((RSI_ROM_API)->pQSPIROM) + +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +/* Pointer to EFUSE driver functions in ROM */ +#define ROMAPI_EFUSE_API ((RSI_ROM_API)->pEFUSEROM) +#endif + +/* Pointer to CRC peripheral driver functions in ROM */ +#define ROMAPI_CRC_API ((RSI_ROM_API)->pCRCROM) + +/* Pointer to RNG peripheral driver functions in ROM */ +#define ROMAPI_RNG_API ((RSI_ROM_API)->pRNGROM) + +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +/* Pointer to MCPWM peripheral driver functions in ROM */ +#define ROMAPI_MCPWM_API ((RSI_ROM_API)->pMCPWMROM) +#endif + +/* Pointer to USART peripheral driver functions in ROM */ +#define ROMAPI_USART_API ((RSI_ROM_API)->pUSARTROM) + +/* Pointer to GSPI peripheral driver functions in ROM */ +#define ROMAPI_GSPI_API ((RSI_ROM_API)->pGSPIROM) + +/* Pointer to I2S peripheral driver functions in ROM */ +#define ROMAPI_I2S_API ((RSI_ROM_API)->pI2SROM) + +/* Pointer to I2C peripheral driver functions in ROM */ +#define ROMAPI_I2C_API ((RSI_ROM_API)->pI2CROM) + +#ifdef CHIP_9118 +/* Pointer to WIRELESS driver functions in ROM */ +#define ROMAPI_WL ((RSI_ROM_API)->pWLROM) +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) +/* Pointer to SSI driver functions in ROM */ +#define ROMAPI_SSI_API ((RSI_ROM_API)->pSSIROM) +#endif + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /* __RSI_ROM_TABLE_RS9116_H__ */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h new file mode 100644 index 000000000..3c0da1528 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma.h @@ -0,0 +1,345 @@ +/****************************************************************************** +* @file rsi_rom_udma.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#ifndef __RSI_ROM_UDMA_H__ +#define __RSI_ROM_UDMA_H__ + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_UDMA_DRIVER + * @{ + * + */ +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_UDMA_SetupChannelTransfer( RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, + void *pSrcAddr, void *pDstAddr ) + * @brief This API is used to control parameters for a UDMA channel control structure. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] pCfg : Pointer to channel configuration structure \ref RSI_UDMA_CHA_CFG_T + * @param[in] vsUdmaChaConfigData :structure variable of type RSI_UDMA_CHA_CONFIG_DATA ,structure has below members + to configure and possible values + - transferType : The operating mode of the DMA cycle + - \ref UDMA_MODE_STOP + - \ref UDMA_MODE_BASIC + - \ref UDMA_MODE_AUTO + - \ref UDMA_MODE_PINGPONG + - \ref UDMA_MODE_MEM_SCATTER_GATHER + - \ref UDMA_MODE_PER_SCATTER_GATHER + - nextBurst : Controls if the chnl_useburst_set[0] bit is set to a 1 + when the controller is performing a peripheral scatter-gather + and is completing a DMA cycle that uses the alternate data + structure + - 0 : the controller does not change the value of the + chnl_useburst_set[0]bit + - 1 : the controller sets the chnl_useburst_set [0] bit + to a 1 + - totalNumOfDMATrans : Represent the total number of DMA transfers that + the DMA cycle contains + \n possible values are 0x00 to 0x1FF for + 1 to 1024 transfers + - rPower : The arbitration size determines how many items are + transferred before the uDMA controller re-arbitrates for + the bus. Choose the arbitration size from one of + - \ref ARBSIZE_1 + - \ref ARBSIZE_2 + - \ref ARBSIZE_4 + - \ref ARBSIZE_16 + - \ref ARBSIZE_64 + - \ref ARBSIZE_128 + - \ref ARBSIZE_256 + - \ref ARBSIZE_512 + - \ref ARBSIZE_1024 + \n to select the arbitration size from 1 to 1024 items, + in powers of 2 + - srcProtCtrl : Set the bits to control the state of HPROT[3:1] + when the controller reads the source data. + - dstProtCtrl : Set the bits to control the state of HPROT[3:1] when + the controller writes the destination data. + - srcSize : Choose the source data size from one of + - \ref SRC_SIZE_8 + - \ref SRC_SIZE_16 + - \ref SRC_SIZE_32 + \n to select a data size of 8, 16, or 32 bits + - dstSize : Choose the destination data size from one of + - \ref DST_SIZE_8 + - \ref DST_SIZE_16 + - \ref DST_SIZE_32 + \n to select a data size of 8, 16, or 32 bits + - srcInc : Choose the source address increment from one of + - \ref SRC_INC_8 + - \ref SRC_INC_16 + - \ref SRC_INC_32 + - \ref SRC_INC_NONE + \n to select a data size of 8, 16, or 32 bits + half-words, 32-bit words, or to select non-incrementing. + - dstInc : Choose the destination address increment from one of + - \ref DST_INC_8 + - \ref DST_INC_8 + - \ref DST_INC_8 + - \ref DST_INC_NONE + \n to select a data size of 8, 16, or 32 bits + half-words, 32-bit words, or to select non-incrementing. + * @param[in] pSrcAddr : Pointer to source address + * @param[in] pDstAddr : Pointer to destination address + * @return \ref RSI_OK if no errors occurred, or an error code + */ +STATIC INLINE rsi_error_t RSI_UDMA_SetupChannelTransfer(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, + void *pSrcAddr, + void *pDstAddr) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + return ROMAPI_UDMA_API->udma_setup_channel_transfer(pHandle, pCfg, vsUdmaChaConfigData, pSrcAddr, pDstAddr); +#else + return udma_setup_channel_transfer(pHandle, pCfg, vsUdmaChaConfigData, pSrcAddr, pDstAddr); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_UDMA_SetChannelScatterGatherTransfer(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh, + uint8_t taskCount, + void *pTaskList, uint32_t transferType) + * @brief This API is used to configures a UDMA channel for scatter-gather mode + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(0 to 31) + * @param[in] taskCount : Number of scatter-gather tasks to execute + * @param[in] pTaskList : pointer to the beginning of the scatter-gather task list + * @param[in] transferType : Transfer type + * @return return \ref ERROR_UDMA_INVALID_ARG if channel is greater than 31, and on success return \ref RSI_OK + */ +STATIC INLINE rsi_error_t RSI_UDMA_SetChannelScatterGatherTransfer(RSI_UDMA_HANDLE_T pHandle, + uint8_t dmaCh, + uint8_t taskCount, + void *pTaskList, + uint32_t transferType) + +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + return ROMAPI_UDMA_API->udma_set_channel_scatter_gather_transfer(pHandle, dmaCh, taskCount, pTaskList, transferType); + +#else + return udma_set_channel_scatter_gather_transfer(pHandle, dmaCh, taskCount, pTaskList, transferType); +#endif +} + +/** + * @fn STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferLength(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData) + + * @brief Gets the current transfer size for a UDMA channel control structure + * @param[in] pHandle : Pointer to driver context handle + * @param[in] pCfg : Pointer to channel configuration structure \ref RSI_UDMA_CHA_CFG_T + * @param[in] vsUDMAChaConfigData : structure variable of type \ref RSI_UDMA_CHA_CONFIG_DATA + * @return Number of items remaining to transfer and all transmission is complete then return RSI_OK(0) + * @note This function is used to get the UDMA transfer size for a channel. + The transfer size is the number of items to transfer, where the size of an item + might be 8, 16, or 32 bits. If a partial transfer has already occurred, + then the number of remaining items is returned. If the transfer is + complete, then 0 is returned. + */ +STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferLength(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + return ROMAPI_UDMA_API->udma_get_channel_transfer_length(pHandle, pCfg, vsUDMAChaConfigData); +#else + return udma_get_channel_transfer_length(pHandle, pCfg, vsUDMAChaConfigData); +#endif +} +/** + + * @fn STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) + * @brief Gets the transfer mode for a UDMA channel control structure. + * @param[in] pHandle : Pointer to driver context handle + * @param[in] pCfg : Pointer to DMA channel configuration structure \RSI_UDMA_CHA_CFG_T required parameter below + - \ref channelPrioHigh : channel priority level. + - \ref altStruct : alternate structure if 1 then enable alternate structure + if 0 then primary structure + - \ref burstReq : Burst request + - \ref reqMask : mask the specific channel. + - \ref periphReq : peripheral request like i2c ,i2s etc + - \ref periAck : peripheral ack like i2c ,i2s etc + - \ref dmaCh :dma channel number(0-31) + * @return Returns the transfer mode of the specified channel and control structure,possible value is below + - \ref UDMA_MODE_STOP + - \ref UDMA_MODE_BASIC + - \ref UDMA_MODE_AUTO + - \ref UDMA_MODE_PINGPONG + - \ref UDMA_MODE_MEM_SCATTER_GATHER + - \ref UDMA_MODE_PER_SCATTER_GATHER + */ + +STATIC INLINE uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + return ROMAPI_UDMA_API->udma_get_channel_transfer_mode(pHandle, pCfg); +#else + return udma_get_channel_transfer_mode(pHandle, pCfg); +#endif +} +/** + * @fn RSI_UDMA_HANDLE_T RSI_UDMA_Init(void *mem, const RSI_UDMA_INIT_T *pInit) + + * @brief This API is used to initialize driver context parameters + * @param[in] pInit : Pointer to DMA controller init data + * @param[in] mem : Pointer to memory area used to driver context + * @return NULL on error, or a pointer to the device context handle + */ +STATIC INLINE RSI_UDMA_HANDLE_T RSI_UDMA_Init(void *mem, const RSI_UDMA_INIT_T *pInit) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + return ROMAPI_UDMA_API->udma_init(mem, pInit); +#else + return udma_init(mem, pInit); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, RSI_UDMA_CHA_CFG_T *pCfg) + + * @brief This API is used to configures required parameters for a channel + * @param[in] pHandle : Pointer to driver context handle + * @param[in] pCfg : Pointer to DMA channel configuration structure \RSI_UDMA_CHA_CFG_T required parameter below + - \ref channelPrioHigh : channel priority level. + - \ref altStruct : alternate structure if 1 then enable alternate structure + if 0 then primary structure + - \ref burstReq : Burst request + - \ref reqMask : mask the specific channel. + - \ref periphReq : peripheral request like i2c ,i2s etc + - \ref periAck : peripheral ack like i2c ,i2s etc + - \ref dmaCh :dma channel number(0-31) + * @return - \ref RSI_OK if no errors occurred, or an error code + */ +STATIC INLINE rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + return ROMAPI_UDMA_API->udma_setup_channel(pHandle, pCfg); +#else + return udma_setup_channel(pHandle, pCfg); +#endif +} +/** + * @fn STATIC INLINE void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) + * @brief This API is used to Uninitialized driver context parameters + * @param[in] pHandle : Pointer to driver context handle + * @param[in] pCfg : Pointer to DMA channel configuration structure + * @return none + */ +STATIC INLINE void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + ROMAPI_UDMA_API->udma_deInit(pHandle, pCfg); +#else + udma_deInit(pHandle, pCfg); +#endif +} +/** + * @fn STATIC INLINE void RSI_UDMA_Interrupthandler(RSI_UDMA_HANDLE_T pHandle) + * @brief This API is used to handle all interrupt and error flags in interrupt context + * @param[in] pHandle : Pointer to driver context handle + * @return none + * @note(s) This function should be called from the DMA interrupt handler + */ + +STATIC INLINE void RSI_UDMA_Interrupthandler(RSI_UDMA_HANDLE_T pHandle) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + ROMAPI_UDMA_API->udma_interrupt_handler(pHandle); +#else + udma_interrupt_handler(pHandle); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_UDMA_InterruptEnable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) + * @brief This API is used to enable the done interrupt to processor + * @param[in] pHandle : Pointer to driver context handle + * @param[in] dmaCh : Channel number(0 to 31) + * @return return \ref ERROR_UDMA_INVALID_ARG if channel is greater than 31, and on success return \ref RSI_OK + */ +STATIC INLINE rsi_error_t RSI_UDMA_InterruptEnable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) + return ROMAPI_UDMA_API->udma_interrupt_enable(pHandle, dmaCh); +#else + return udma_interrupt_enable(pHandle, dmaCh); +#endif +} +/* @} end of RSI_UDMA_DRIVERS */ +/************************************************************************************** + UDMA ROM FUNCTION PROTOTYPES + **************************************************************************************/ +rsi_error_t RSI_UDMA_SetupChannelTransfer(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUdmaChaConfigData, + void *pSrcAddr, + void *pDstAddr); + +rsi_error_t RSI_UDMA_SetChannelScatterGatherTransfer(RSI_UDMA_HANDLE_T pHandle, + uint8_t dmaCh, + uint8_t taskCount, + void *pTaskList, + uint32_t transferType); + +uint32_t RSI_UDMA_GetChannelTransferLength(RSI_UDMA_HANDLE_T pHandle, + const RSI_UDMA_CHA_CFG_T *pCfg, + RSI_UDMA_CHA_CONFIG_DATA_T vsUDMAChaConfigData); + +uint32_t RSI_UDMA_GetChannelTransferMode(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + +RSI_UDMA_HANDLE_T RSI_UDMA_Init(void *mem, const RSI_UDMA_INIT_T *pInit); + +rsi_error_t RSI_UDMA_SetupChannel(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + +static void RSI_UDMA_DeInit(RSI_UDMA_HANDLE_T pHandle, const RSI_UDMA_CHA_CFG_T *pCfg); + +void RSI_UDMA_Interrupthandler(RSI_UDMA_HANDLE_T pHandle); + +rsi_error_t RSI_UDMA_InterruptEnable(RSI_UDMA_HANDLE_T pHandle, uint8_t dmaCh); + +#ifdef __cplusplus +} +#endif + +#endif /* __RSI_ROM_UDMA_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h new file mode 100644 index 000000000..6f13e6c00 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_udma_wrapper.h @@ -0,0 +1,150 @@ +/****************************************************************************** +* @file rsi_rom_udma_wrapper.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#ifndef __RSI_ROM_UDMA_WRAPPER_H__ +#define __RSI_ROM_UDMA_WRAPPER_H__ + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_UDMA_DRIVER UDMA WRAPPER + * @{ + * + */ +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#include "rsi_udma_wrapper.h" +#include "UDMA.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#endif +#ifdef __cplusplus +extern "C" { +#endif + +STATIC INLINE RSI_UDMA_HANDLE_T UDMAx_Initialize(const UDMA_RESOURCES *udma, + RSI_UDMA_DESC_T *UDMA_Table, + RSI_UDMA_HANDLE_T udmaHandle, + uint32_t *mem) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + return udmaHandle = ROMAPI_UDMA_WRAPPER_API->uDMAx_Initialize(udma, UDMA_Table, udmaHandle, mem); +#else + return udmaHandle = uDMAx_Initialize(udma, UDMA_Table, udmaHandle, mem); +#endif +} + +STATIC INLINE int32_t UDMAx_Uninitialize(const UDMA_RESOURCES *udma) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + return ROMAPI_UDMA_WRAPPER_API->uDMAx_Uninitialize(udma); +#else + return uDMAx_Uninitialize(udma); +#endif +} + +STATIC INLINE int32_t UDMAx_ChannelConfigure(const UDMA_RESOURCES *udma, + uint8_t ch, + uint32_t src_addr, + uint32_t dest_addr, + uint32_t size, + RSI_UDMA_CHA_CONFIG_DATA_T control, + const RSI_UDMA_CHA_CFG_T *config, + UDMA_SignalEvent_t cb_event, + UDMA_Channel_Info *chnl_info, + RSI_UDMA_HANDLE_T udmaHandle) +{ + if (control.transferType == UDMA_SOFTWARE_TRIGG) { + udma->desc->vsUDMAChaConfigData1.transferType = UDMA_SOFTWARE_TRIGG; + } + if ((control.totalNumOfDMATrans + 1UL) > size) { + control.totalNumOfDMATrans = (unsigned int)((size - 1) & 0x03FF); + } + +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + return ROMAPI_UDMA_WRAPPER_API + ->uDMAx_ChannelConfigure(udma, ch, src_addr, dest_addr, size, control, config, cb_event, chnl_info, udmaHandle); +#else + return uDMAx_ChannelConfigure(udma, ch, src_addr, dest_addr, size, control, config, cb_event, chnl_info, udmaHandle); +#endif +} + +STATIC INLINE int32_t UDMAx_ChannelEnable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + + return ROMAPI_UDMA_WRAPPER_API->uDMAx_ChannelEnable(ch, udma, udmaHandle); +#else + return uDMAx_ChannelEnable(ch, udma, udmaHandle); +#endif +} + +STATIC INLINE int32_t UDMAx_DMAEnable(const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + return ROMAPI_UDMA_WRAPPER_API->uDMAx_DMAEnable(udma, udmaHandle); +#else + return uDMAx_DMAEnable(udma, udmaHandle); +#endif +} + +STATIC INLINE int32_t UDMAx_ChannelDisable(uint8_t ch, const UDMA_RESOURCES *udma, RSI_UDMA_HANDLE_T udmaHandle) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + return ROMAPI_UDMA_WRAPPER_API->uDMAx_ChannelDisable(ch, udma, udmaHandle); +#else + return uDMAx_ChannelDisable(ch, udma, udmaHandle); +#endif +} + +STATIC INLINE uint32_t UDMAx_ChannelGetCount(uint8_t ch, + RSI_UDMA_CHA_CONFIG_DATA_T control, + RSI_UDMA_CHA_CFG_T config, + const UDMA_RESOURCES *udma, + RSI_UDMA_HANDLE_T udmaHandle) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + return ROMAPI_UDMA_WRAPPER_API->uDMAx_ChannelGetCount(ch, control, config, udma, udmaHandle); +#else + return uDMAx_ChannelGetCount(ch, control, config, udma, udmaHandle); +#endif +} +STATIC INLINE void UDMAx_IRQHandler(UDMA_RESOURCES *udma, RSI_UDMA_DESC_T *UDMA_Table, UDMA_Channel_Info *chnl_info) +{ +#if defined(UDMA_ROMDRIVER_PRESENT) && defined(A11_ROM) + ROMAPI_UDMA_WRAPPER_API->uDMAx_IRQHandler(udma, UDMA_Table, chnl_info); +#else + uDMAx_IRQHandler(udma, UDMA_Table, chnl_info); +#endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* __RSI_ROM_UDMA_WRAPPER_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h new file mode 100644 index 000000000..904e2733a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/inc/rsi_rom_ulpss_clk.h @@ -0,0 +1,686 @@ +/******************************************************************************* +* @file rsi_rom_ulpss_clk.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Includes + +#ifndef __RSI_ROM_ULPSS_CLK_H__ +#define __RSI_ROM_ULPSS_CLK_H__ + +#include "rsi_rom_egpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + */ + +/** + * \defgroup RSI_CHIP_CLOCK_DRIVERS CLOCK + * @{ + * + */ + +/** + * \defgroup RSI_ULPSS_CLOCK_DRIVERS ULPSS CLOCK + * @{ + * + */ +#include "rsi_ccp_user_config.h" +#include "rsi_packing.h" +#include "rsi_ulpss_clk.h" +#if defined(A11_ROM) +#include "rsi_rom_table_si91x.h" +#else +#include "rsi_rom_table_RS1xxxx.h" +#endif +#if SL_WIFI_COMPONENT_INCLUDED +#include "sl_rsi_utility.h" +#include "rsi_m4.h" +#endif + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource) + * @brief This API is used to select the ULPSS processor ref clk configuration + * @param[in] clkSource : Enum values of clock source to select as ulp processor ref clock.Please refer #ULPSS_REF_CLK_SEL_T + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource) +{ +#if SL_WIFI_COMPONENT_INCLUDED + if (clkSource == ULPSS_40MHZ_CLK) { + /* Notify NWP that M4 requires XTAL clock source */ + sli_si91x_xtal_turn_on_request_from_m4_to_TA(); + } +#endif + return ulpss_ref_clk_config(clkSource); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor) + * @brief This API is used to select the ULPSS processor clock source when input is soc clk source which is greater than 100MHz + * @param[in] pCLK : Pointer to the pll register instance + * @param[in] clkEnable : is to enable or disable the ulpss_soc clock + * - Enable 1: Enables the clock + * - Disable 0: Disables the clock + * @param[in] divFactor : To divide the clock, ensure that oddDivFactor is 0 then divFactor must be even value or else odd value + * @param[in] oddDivFactor : Selects the type of divider for m4_soc_clk_2ulpss + * - 0 => Clock Divider(even) is selected + * - 1 => Odd Divider is selected + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, + boolean_t clkEnable, + uint16_t divFactor, + boolean_t oddDivFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); +#else + return ulpss_clock_config(pCLK, clkEnable, divFactor, oddDivFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK , + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor,cdDelay delayFn) + * @brief This API is used to configure the ULPSS processor clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Enum values of clock source to select as processor clock.Please refer #ULP_PROC_CLK_SELECT_T and refer NOTE + * @param[in] divFactor : To divide the clock + * @param[in] delayFn : delay enable parameter is 1 for enable 0 for not enable. + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note + * In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn) +{ + return ulpss_ulp_proc_clk_config(pULPCLK, clkSource, divFactor, delayFn); +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to enable different pheriheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags : Ored value of the clock enable bits of particular peripheral + * - \ref Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_peri_clk_enable(pULPCLK, u32Flags); +#else + return ulpss_ulp_peri_clk_enable(pULPCLK, u32Flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to disable different peripheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags is to Ored value of the clock enable bits of particular peripheral + * \n Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_peri_clk_disable(pULPCLK, u32Flags); +#else + return ulpss_ulp_peri_clk_disable(pULPCLK, u32Flags); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to enable different peripheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags : Ored value of the clock enable bits of particular peripheral + * \n Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_dyn_clk_enable(pULPCLK, u32Flags); +#else + return ulpss_ulp_dyn_clk_enable(pULPCLK, u32Flags); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK , uint32_t u32Flags) + * @brief This API is used to disable different peripheral clocks in ULPSS + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] u32Flags : is to Ored value of the clock enable bits of particular peripheral + * \n Possible values for this parameter are + * - \ref ULPSS_TASS_QUASI_SYNC + * - \ref ULPSS_M4SS_SLV_SEL + * - \ref AUX_SOC_EXT_TRIG_2_SEL + * - \ref AUX_SOC_EXT_TRIG_1_SEL + * - \ref AUX_ULP_EXT_TRIG_2_SEL + * - \ref AUX_ULP_EXT_TRIG_1_SEL + * - \ref TIMER_PCLK_EN + * - \ref EGPIO_PCLK_ENABLE + * - \ref EGPIO_PCLK_DYN_CTRL_DISABLE + * - \ref CLK_ENABLE_ULP_MEMORIES + * - \ref VAD_CLK_EN + * - \ref FIM_CLK_EN + * - \ref REG_ACCESS_SPI_CLK_EN + * - \ref EGPIO_CLK_EN + * - \ref CLK_ENABLE_TIMER + * - \ref VAD_PCLK_ENABLE + * - \ref FIM_PCLK_ENABLE + * - \ref SCLK_ENABLE_UART + * - \ref PCLK_ENABLE_UART + * - \ref SCLK_ENABLE_SSI_MASTER + * - \ref PCLK_ENABLE_SSI_MASTER + * - \ref CLK_ENABLE_I2S + * - \ref PCLK_ENABLE_I2C + * - \ref RELEASE_SOFT_RESET + * - \ref PCM_FSYNC_START + * - \ref PCM_ENABLE + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_dyn_clk_disable(pULPCLK, u32Flags); +#else + return ulpss_ulp_dyn_clk_disable(pULPCLK, u32Flags); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK ,CLK_ENABLE_T clkType , + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor) + * @brief This API is used to configure the SSI clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] clkSource : Value of clock source to select as Ulp SSI clock. Please refer #ULP_SSI_CLK_SELECT_T for more info + * - 0: \ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two \ref XTAL Clk sources one is Internal and external \ref XTAL clk source. In order to enable the external XTAL clk source need to configure the \ref NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer \ref RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ + +STATIC INLINE rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor); +#else + return ulpss_ulp_ssi_clk_config(pULPCLK, clkType, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK, + ULP_I2S_CLK_SELECT_T clkSource , + uint16_t divFactor) + * @brief This API is used to configure the I2S clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Value of clock source to select as I2S clock. Please refer #ULP_SSI_CLK_SELECT_T for more info + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * - 7: \ref ulp_doubler_clk + * - 8: \ref I2S PLL + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK, + ULP_I2S_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_i2s_clk_config(pULPCLK, clkSource, divFactor); +#else + return ulpss_ulp_i2s_clk_config(pULPCLK, clkSource, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK,CLK_ENABLE_T clkType, + boolean_t bFrClkSel,ULP_UART_CLK_SELECT_T clkSource , + uint16_t divFactor) + * @brief This API is used to configure the UART clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] bFrClkSel : To enable or disable ulp uart clk selection + * - 1: Fractional Divider output is selected + * - 0: Swallow Divider output is selected + * @param[in] clkSource : Value of clock source to select as processor clock + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_ulp_uar_clk_config(pULPCLK, clkType, bFrClkSel, clkSource, divFactor); +#else + return ulpss_ulp_uar_clk_config(pULPCLK, clkType, bFrClkSel, clkSource, divFactor); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK ,CLK_ENABLE_T clkType, + boolean_t bTmrSync ,ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime) + * @brief This API is used to configure the timer clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] bTmrSync : To enable Ulp timer in synchronous mode to ULPSS pclk + * - 1: Enables + * - 0: Disables + * @param[in] clkSource : Value of clock source to select as Timer clock. Please refer #ULP_TIMER_CLK_SELECT_T for possible values + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * - 7: \ref ulp_doubler_clk + * @param[in] skipSwitchTime : To skip the switching of timer clk. + * - 1 : Wait for switching timer clk + * - 0 : Skip waiting for switching timer clk + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_time_clk_config(pULPCLK, clkType, bTmrSync, clkSource, skipSwitchTime); +#else + return ulpss_time_clk_config(pULPCLK, clkType, bTmrSync, clkSource, skipSwitchTime); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkDisable(ULPCLK_Type *pULPCLK ) + * @brief This API is used to disable the timer clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_TimerClkDisable(ULPCLK_Type *pULPCLK) +{ +#if defined(CHIP_9118) && defined(A11_ROM) && defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_time_clk_disable(pULPCLK); +#else + return ulpss_time_clk_disable(pULPCLK); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK , + CLK_ENABLE_T clkType, + ULP_AUX_CLK_SELECT_T clkSource + ) + * @brief This API is used to configure the AUX clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkType : To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @param[in] clkSource : Value of clock source to select as AUX clock. Please refer #ULP_AUX_CLK_SELECT_T for more info + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * - 7: \ref ulp_doubler_clk + * - 8: \ref I2S PLL + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note - There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_AUX_CLK_SELECT_T clkSource) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_aux_clk_config(pULPCLK, clkType, clkSource); +#else + return ulpss_aux_clk_config(pULPCLK, clkType, clkSource); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK , + ULP_VAD_CLK_SELECT_T clkSource , + ULP_VAD_FCLK_SELECT_T FclkSource , + uint16_t divFactor) + * @brief This API is used to configure the VAD clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Value of clock source to select as vad clock. Please refer #ULP_VAD_CLK_SELECT_T for more info + * - 0: \ref ulp_32khz_ro_clk + * - 1: \ref ulp_32khz_rc_clk + * - 2: \ref ulp_32khz_xtal_clk #refer NOTE + * \n NOTE: In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins + * \n which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * @param[in] FclkSource : Ulp vad Fast clock select. Please refer #ULP_VAD_FCLK_SELECT_T for more info + * - 0: ulpss processor clock #refer NOTE + * - 1: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 2: \ref ulp_mhz_rc_clk + * - 3: \ref ulp_20mhz_ro_clk + * - 4: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note - There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + * - In order to enable the ulpss processor clock source need to configure the + * - RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK ,boolean_t clkEnable,uint8_t clkSource,uint16_t divFactor,delayMs cbDelay ) + */ +STATIC INLINE rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor); +#else + return ulpss_vad_clk_config(pULPCLK, clkSource, FclkSource, divFactor); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK ,ULP_TOUCH_CLK_SELECT_T clkSource , + uint16_t divFactor ) + * @brief This API is used to configure the Touch clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkSource : Value of clock source to select as Touch clock. Please refer #ULP_TOUCH_CLK_SELECT_T for more info. + * - 0: \ref ref_clk (output of dynamic clock mux for different possible ref_clk sources) + * - 1: \ref ulp_32khz_ro_clk + * - 2: \ref ulp_32khz_rc_clk + * - 3: \ref ulp_32khz_xtal_clk #refer NOTE + * - 4: \ref ulp_mhz_rc_clk + * - 5: \ref ulp_20mhz_ro_clk + * - 6: \ref soc_clk #refer NOTE + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note There are two XTAL Clk sources one is Internal and external XTAL clk source. In order to enable the external XTAL clk source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + * - In order to enable the soc CLK source need to configure the Ulpss soc Clk from M4 soc clk + * - please refer RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK,boolean_t clkEnable,uint16_t divFactor,boolean_t oddDivFactor); + */ +STATIC INLINE rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK, + ULP_TOUCH_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_touch_clk_config(pULPCLK, clkSource, divFactor); +#else + return ulpss_touch_clk_config(pULPCLK, clkSource, divFactor); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK , boolean_t clkEnable ,uint32_t divFactor) + * @brief This API is used to configure the sleep sensor clock source + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] clkEnable : To enable or disable the sleep sensor clock + * - Enable 1: Enables the clock + * - Disable 0: Disables the clock + * @param[in] divFactor : To divide the clock + * @return returns 0 \ref RSI_OK on success ,Error code on failure + * @note In order to enable the XTAL CLK source need to configure the NPSS_GPIO pins + * - which can be done through RSI_CLK_XtalClkConfig(uint8_t xtalPin) API i.e we need to call that API first + */ +STATIC INLINE rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_slp_sensor_clk_config(pULPCLK, clkEnable, divFactor); +#else + return ulpss_slp_sensor_clk_config(pULPCLK, clkEnable, divFactor); +#endif +} + +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK, + ULPPERIPHERALS_CLK_T module,CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular ULP peripherial Clock + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] module : To select particular ulp pheripheral. See \ref ULPPERIPHERALS_ENABLE_T for more info. + * @param[in] clkType :To select the clock as dynamic or static clock. See the #CLK_ENABLE_T for more info + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK, + ULPPERIPHERALS_CLK_T module, + CLK_ENABLE_T clkType) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_peripheral_enable(pULPCLK, module, clkType); +#else + return ulpss_peripheral_enable(pULPCLK, module, clkType); +#endif +} +/** + * @fn STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) + * @brief This API is used to Disable the particular ULP peripherial Clock + * @param[in] pULPCLK : Pointer to the ulp clock register instance + * @param[in] module : To select particular ulp pheripheral. \ref ULPPERIPHERALS_DISABLE_T for more info. + * @return returns 0 \ref RSI_OK on success ,Error code on failure + */ +STATIC INLINE rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) +{ +#if defined(ULPSS_CLOCK_ROMDRIVER_PRESENT) + return ROMAPI_ULPSS_CLK_API->ulpss_peripheral_disable(pULPCLK, module); +#else + return ulpss_peripheral_disable(pULPCLK, module); +#endif +} + +rsi_error_t RSI_ULPSS_RefClkConfig(ULPSS_REF_CLK_SEL_T clkSource); + +rsi_error_t RSI_ULPSS_ClockConfig(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); + +rsi_error_t RSI_ULPSS_UlpProcClkConfig(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn); + +rsi_error_t RSI_ULPSS_UlpPeriClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpPeriClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpDynClkEnable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpDynClkDisable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t RSI_ULPSS_UlpSsiClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t RSI_ULPSS_UlpI2sClkConfig(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t RSI_ULPSS_UlpUartClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t RSI_ULPSS_TimerClkConfig(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime); + +rsi_error_t RSI_ULPSS_AuxClkConfig(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); + +rsi_error_t RSI_ULPSS_VadClkConfig(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor); + +rsi_error_t RSI_ULPSS_TouchClkConfig(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t RSI_ULPSS_SlpSensorClkConfig(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); + +rsi_error_t RSI_ULPSS_PeripheralEnable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + +rsi_error_t RSI_ULPSS_PeripheralDisable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_ROM_ULPSS_CLK_H__*/ + +/*@} end of RSI_ULPSS_CLOCK_DRIVERS */ + +/* @} end ofRSI_CHIP_CLOCK_DRIVERS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/src/rsi_rom_table_si91x.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/src/rsi_rom_table_si91x.c new file mode 100644 index 000000000..d045529a2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/rom_driver/src/rsi_rom_table_si91x.c @@ -0,0 +1,107 @@ +/****************************************************************************** +* @file rsi_rom_table_si91x.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +/** + * Includes + */ +#include + +#include "rsi_ccp_user_config.h" +#include "rsi_rom_table_si91x.h" +#if defined(A11_ROM) +#ifdef __cplusplus +extern "C" { +#endif +extern const ROM_EGPIO_API_T egpio_api; +extern const ROM_TIMERS_API_T timer_api; +extern const ROM_UDMA_API_T udma_api; +extern const ROM_UDMA_WRAPPER_API_T udma_wrapper_api; +extern const ROM_CT_API_T ct_api; +extern const ROM_RPDMA_API_T gpdma_api; +extern const ROM_PWR_API_T pwr_api; +extern const ROM_M4SS_CLK_API_T m4ssclk_api; +extern const ROM_ULPSS_CLK_API_T ulpssclk_api; +extern const ROM_QSPI_API_T qspi_api; +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +extern const ROM_EFUSE_API_T efuse_api; +#endif +extern const ROM_CRC_API_T crc_api; +extern const ROM_RNG_API_T rng_api; +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +extern const ROM_MCPWM_API_T mcpwm_api; +#endif +extern const ROM_USART_API_T usart_api; +extern const ROM_GSPI_API_T gspi_api; +extern const ROM_I2S_API_T i2s_api; +extern const ROM_I2C_API_T i2c_api; +#if defined(SLI_SI917) || defined(SLI_SI915) +extern const ROM_SSI_API_T ssi_api; +#endif +#if defined(CHIP_9118) +extern const struct ROM_WL_API_S wl_api; +#endif +const RSI_ROM_API_T romEntry __attribute__((section(".rom_data_start"))) /* ((at(0x0801ACA8)))= */ += { + /*!< ROM TABLE FIXED ENTRY POINT*/ + &egpio_api, /*!< EGPIO driver API function table base address */ + &timer_api, /*!< FIM driver API function table base address */ + &udma_api, /*!< uDMA driver API function table base address */ + &udma_wrapper_api, /*!< udma wrapper driver API function table base address */ + &ct_api, /*!< CT driver API function table base address */ + &gpdma_api, /*!< RPDMA driver API function table base address */ + &pwr_api, /*!< POWER SAVE driver API function table base address */ + &m4ssclk_api, /*!< M4SS CLK driver API function table base address */ + &ulpssclk_api, /*!< ULPSS CLK driver API function table base address */ + &qspi_api, /*!< QSPI driver API function table base address */ +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + &efuse_api, /*!< EFUSE driver API function table base address */ +#endif + &crc_api, /*!< CRC driver API function table base address */ + &rng_api, /*!< RNG driver API function table base address */ +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + &mcpwm_api, /*!< MCPWM driver API function table base address */ +#endif + &usart_api, /*!< USARt driver API function table base address */ + &gspi_api, /*!< GSPI driver API function table base address */ + &i2s_api, /*!< I2S driver API function table base address */ + &i2c_api /*!< I2C driver API function table base address */ +#if defined(SLI_SI917) || defined(SLI_SI915) + , + &ssi_api +#endif +#ifdef CHIP_9118 + , + &wl_api /*!< Wireless driver API function table base address */ +#endif + }; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h new file mode 100644 index 000000000..29de4a21a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc/sl_si91x_clock_manager.h @@ -0,0 +1,207 @@ +/****************************************************************************** +* @file sl_si91x_clock_manager.h +* @brief Clock Manager Service API implementation +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#ifndef SL_SI91X_CLOCK_MANAGER_H +#define SL_SI91X_CLOCK_MANAGER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "rsi_pll.h" + +/***************************************************************************/ +/** + * @addtogroup CLOCK-MANAGER Clock Manager + * @ingroup SI91X_SERVICE_APIS + * @{ + * + ******************************************************************************/ +// ----------------------------------------------------------------------------------- +// GLOBAL DEFINES / MACROS +// Macros for defining supported PLL Ref Clock frequencies +#define PLL_REF_CLK_VAL_XTAL (40000000UL) ///< PLL reference clock frequency value of XTAL CLK +// ----------------------------------------------------------------------------------- + +/***************************************************************************/ +/** + * @typedef sl_si91x_m4_soc_clk_src_sel_t + * @brief Typedef to select the clock source for the M4 core in the Si91x SOC. + * + * @details This typedef maps to the M4_SOC_CLK_SRC_SEL_T type, which defines the possible clock source selections for the M4 core. + * The clock source selection impacts the operating frequency and performance characteristics of the M4 processor within the Si91x SOC. + * + * Users can configure the clock source to optimize power consumption or performance based on application requirements. + * + * @note Ensure that the selected clock source is properly configured and stable before switching to avoid system instability. + ******************************************************************************/ +typedef M4_SOC_CLK_SRC_SEL_T sl_si91x_m4_soc_clk_src_sel_t; +// ----------------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------------- +// GLOBAL FUNCTION PROTOTYPES + +/***************************************************************************/ +/** + * @brief Initializes the M4_SOC and other required clocks. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_init(void); + +/***************************************************************************/ +/** + * @brief To configure the M4 core clock source and configure the PLL frequency if selected as source. + * + * @param[in] clk_source Enum value representing different core clock sources. + * @param[in] pll_freq Desired M4 core frequency in MHz. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_m4_set_core_clk(M4_SOC_CLK_SRC_SEL_T clk_source, uint32_t pll_freq); + +/***************************************************************************/ +/** + * @brief To set the selected PLL (Phase-Locked Loop) clock to the desired frequency. + * + * @param[in] pll_type Enum specifying the type of PLL to configure. + * @param[in] pll_freq Desired frequency for the PLL clock (in MHz). + * @param[in] pll_ref_clk Reference clock frequency for the PLL configuration. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_set_pll_freq(PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk); + +/***************************************************************************/ +/** + * @brief To read the currently active M4 core clock source and its frequency. + * + * @param[out] m4_core_clk_freq Pointer to a variable where the current core clock frequency will be stored (in MHz). + * + * @return sl_si91x_m4_soc_clk_src_sel_t The currently active core clock source: + * - 0: M4_ULPREFCLK + * - 2: M4_SOCPLLCLK + * - 3: M4_MODEMPLLCLK1 + * - 4: M4_INTFPLLCLK + * - 5: M4_SLEEPCLK + * + ******************************************************************************/ +sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq(uint32_t *m4_core_clk_freq); + +/***************************************************************************/ +/** + * @brief Gets the selected PLL (Phase-Locked Loop) clock to the desired frequency. + * + * @param[in] pll_type Enum specifying the type of PLL to configure. + * + * @return uint32_t PLL frequency value in MHz. + ******************************************************************************/ +uint32_t sl_si91x_clock_manager_get_pll_freq(PLL_TYPE_T pll_type); + +/***************************************************************************/ +/** + * @brief Controls the selected PLL (Phase-Locked Loop) clock. + * + * @param[in] pll_type Enum specifying the type of PLL to control. + * @param[in] enable Boolean value to enable (true) or disable (false) the PLL. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_control_pll(PLL_TYPE_T pll_type, bool enable); +// ----------------------------------------------------------------------------------- + +/// @} end addtogroup CLOCK-MANAGER ******************************************************/ + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY! *********************** +/***************************************************************************/ +/***************************************************************************/ +/** + * @addtogroup CLOCK-MANAGER Clock Manager + * @{ + * + * @details + * + * @section Clock_Manager_Intro Introduction + * + * The Clock Manager module is responsible for configuring the clock tree in the Si91x system. + * It enhances the clock management features provided by the GSDK's emlib and device_init services, + * offering additional functionality for selecting clock sources and setting dividers. + * This module ensures optimized performance and power efficiency across various system components + * by managing clock configurations according to application requirements. + * + * @section Clock_Manager_Config Configuration + * + * The Clock Manager supports a variety of configurations: + * - **Clock Source Selection**: Allows specific clock sources to be chosen for different branches. + * - **Divider Configuration**: Modifies clock frequencies by setting divider values. + * + * Configuration is typically performed during device initialization using configuration files and source code. + * + * @section Clock_Manager_Usage Usage + * + * The following steps outline typical usage of the Clock Manager: + * 1. Initialize the Clock Manager with desired configuration settings. + * 2. Set up oscillator sources and configure clock dividers. + * 3. Use runtime APIs to manage dynamic clock changes. + * 4. Maintain stable clock configurations to ensure system reliability. + * + * @section Clock_Manager_Benefits Benefits + * + * - Manages complex clock trees efficiently. + * - Enhances system stability and performance. + * - Supports a wide range of Si91x devices. + * - Optimizes power consumption through efficient clock management. + * + * @} (end addtogroup CLOCK-MANAGER) + */ +/***************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_SI91X_CLOCK_MANAGER_H */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c new file mode 100644 index 000000000..96078d698 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c @@ -0,0 +1,384 @@ +/****************************************************************************** +* @file sl_si91x_clock_manager.c +* @brief Clock Manager Service API implementation +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ + +#include "sl_si91x_clock_manager.h" +#include "rsi_rom_clks.h" +#include "rsi_rom_ulpss_clk.h" +/************************************************************************************ + ************************* DEFINES / MACROS *************************************** + ************************************************************************************/ +#define MANUAL_LOCK 1 // Manual lock enable +#define BYPASS_MANUAL_LOCK 1 // Bypass manual lock enable +#define SOC_PLL_MM_COUNT_LIMIT 0xA4 // Soc pll count limit +#define DIVISION_FACTOR 0 // Division factor +#define QSPI_ODD_DIV_EN 0 // Odd division enable for QSPI clock +#define QSPI_SWALLO_EN 0 // Swallo enable for QSPI clock +#define QSPI_DIV_FACTOR 2 // Division factor for QSPI clock +#define QSPI2_DIV_FACTOR 2 // Division factor for QSPI2 clock +#define PLL_PREFETCH_LIMIT (120000000UL) // 120MHz Limit for pll clock +#define SOC_PLL_FREQ (180000000UL) // 180MHz default SoC PLL Clock as source to Processor +#define INTF_PLL_FREQ (180000000UL) // 180MHz default Interface PLL Clock as source to all peripherals +/************************************************************************************ + ************************* LOCAL VARIABLES **************************************** + ************************************************************************************/ + +/************************************************************************************ + ************************* LOCAL TYPE DEFINITIONS ********************************* + ************************************************************************************/ + +/************************************************************************************ + ************************* LOCAL FUNCTION PROTOTYPES ****************************** + ************************************************************************************/ +static sl_status_t convert_rsi_to_sl_error_code(rsi_error_t error); +/************************************************************************************ + ************************* GLOBAL FUNCTION DEFINITIONS **************************** + ************************************************************************************/ +/***************************************************************************/ +/** + * @brief Initializes the M4_SOC and other required clocks. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_init(void) +{ +#ifdef SL_SI91X_REQUIRES_INTF_PLL + M4CLK_Type *pCLK = M4CLK; +#endif + sl_status_t status = SL_STATUS_OK; + +#ifdef SL_SI91X_ULP_STATE_ENABLE + //Trimming the RC_32MHz clock down to 20MHz, which is utilized in the PS2 state + RSI_IPMU_M20rcOsc_TrimEfuse(); + // Sets FSM HF frequency to 20MHz + RSI_PS_FsmHfFreqConfig(20); + // Updated the clock global variables + RSI_PS_PS2UpdateClockVariable(); +#endif + // Configure FSM Low Frequency Clock + // FSM based on XTAL or EXT_OSC has been done in SystemCoreClockUpdate + + /* Configure Ref clock to 40Mhz crystal */ + RSI_CLK_M4ssRefClkConfig(M4CLK, EXT_40MHZ_CLK); + RSI_ULPSS_RefClkConfig(ULPSS_40MHZ_CLK); + + // Core Clock runs at 180MHz SOC PLL Clock + sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK, SOC_PLL_FREQ); + +#ifdef SL_SI91X_REQUIRES_INTF_PLL + // Configuring the interface PLL clock to 180MHz used by the peripherals whose source clock in INTF_PLL + sl_si91x_clock_manager_set_pll_freq(INTF_PLL, INTF_PLL_FREQ, PLL_REF_CLK_VAL_XTAL); + +// Configure QSPI clock with INTF PLL as input source +#if defined(CLOCK_ROMDRIVER_PRESENT) + ROMAPI_M4SS_CLK_API->clk_qspi_clk_config(pCLK, QSPI_INTFPLLCLK, QSPI_SWALLO_EN, QSPI_ODD_DIV_EN, QSPI_DIV_FACTOR); +#endif + +#ifdef SLI_SI91X_MCU_PSRAM_PRESENT + // Configure QSPI2 clock with INTF PLL as input source +#if defined(CLOCK_ROMDRIVER_PRESENT) + ROMAPI_M4SS_CLK_API->clk_qspi_2_clk_config(pCLK, QSPI_INTFPLLCLK, QSPI_SWALLO_EN, QSPI_ODD_DIV_EN, QSPI2_DIV_FACTOR); +#endif +#endif +#endif /* SL_SI91X_REQUIRES_INTF_PLL */ + + return status; +} +/***************************************************************************/ +/** + * @brief To configure the M4 core clock source and configure the PLL frequency if selected as source. + * + * @param[in] clk_source Enum value representing different core clock sources. + * @param[in] pll_freq Desired M4 core frequency in MHz. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_m4_set_core_clk(M4_SOC_CLK_SRC_SEL_T clk_source, uint32_t pll_freq) +{ + M4CLK_Type *pCLK = M4CLK; + uint32_t div_factor = DIVISION_FACTOR; + rsi_error_t error_status = RSI_OK; + sl_status_t status; + + // PLL reference clock set to XTAL_CLK for PLL configuration + uint32_t pll_ref_clk = PLL_REF_CLK_VAL_XTAL; + + // Validating for correct Clock Source input + if (clk_source > M4_SLEEPCLK) { + status = SL_STATUS_INVALID_PARAMETER; + return status; + } + + // Configure the registers for clock less than 120MHz + if (pll_freq < PLL_PREFETCH_LIMIT) { + RSI_PS_PS4ClearRegisters(); + } + // Changing M4 SOC clock to M4_ULPREFCLK + error_status = RSI_CLK_M4SocClkConfig(pCLK, M4_ULPREFCLK, 0); + status = convert_rsi_to_sl_error_code(error_status); + if (status != SL_STATUS_OK) { + return status; + } + + // Configure the required PLL Clocks with desired frequency before configuring it to M4 Core + if (clk_source == M4_ULPREFCLK) { + // ULP REF clock has already been set as M4 SoC source by now + UNUSED_PARAMETER(pll_freq); + return status; + } else if (clk_source == M4_INTFPLLCLK) { + // RSI API to set INTF PLL clock frequency + error_status = sl_si91x_clock_manager_set_pll_freq(INTF_PLL, pll_freq, pll_ref_clk); + } else if (clk_source == M4_SOCPLLCLK) { + // RSI API to set SOC PLL clock frequency + error_status = sl_si91x_clock_manager_set_pll_freq(SOC_PLL, pll_freq, pll_ref_clk); + } + + // The error status is converted to the SL error code + status = convert_rsi_to_sl_error_code(error_status); + if (status != SL_STATUS_OK) { + return status; + } + + // RSI API to set M4 SOC clock is called and the status is converted to the SL error code. + error_status = RSI_CLK_M4SocClkConfig(pCLK, clk_source, div_factor); + status = convert_rsi_to_sl_error_code(error_status); + if (status != SL_STATUS_OK) { + return status; + } + + return status; +} + +/***************************************************************************/ +/** + * @brief To set the selected PLL (Phase-Locked Loop) clock to the desired frequency. + * + * @param[in] pll_type Enum specifying the type of PLL to configure. + * @param[in] pll_freq Desired frequency for the PLL clock (in MHz). + * @param[in] pll_ref_clk Reference clock frequency for the PLL configuration. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_set_pll_freq(PLL_TYPE_T pll_type, uint32_t pll_freq, uint32_t pll_ref_clk) +{ + M4CLK_Type *pCLK = M4CLK; + rsi_error_t error_status = RSI_OK; + sl_status_t status; + + // Configure the registers for clock more than 120MHz in PS4 + if (pll_freq >= PLL_PREFETCH_LIMIT) { + RSI_PS_PS4SetRegisters(); + } + + switch (pll_type) { + case SOC_PLL: + // Configure SOC-PLL lock settings before configuring SOC PLL clock + RSI_CLK_SocPllLockConfig(MANUAL_LOCK, BYPASS_MANUAL_LOCK, SOC_PLL_MM_COUNT_LIMIT); + + // RSI API to set SOC PLL clock frequency + error_status = RSI_CLK_SetSocPllFreq(pCLK, pll_freq, pll_ref_clk); + break; + + case INTF_PLL: + // RSI API to set INTF PLL clock frequency + error_status = RSI_CLK_SetIntfPllFreq(pCLK, pll_freq, pll_ref_clk); + break; + + case I2S_PLL: + // RSI API to set I2S PLL clock frequency + error_status = RSI_CLK_SetI2sPllFreq(pCLK, pll_freq, pll_ref_clk); + break; + + default: + break; + } + + status = convert_rsi_to_sl_error_code(error_status); + return status; +} + +/***************************************************************************/ +/** + * @brief To read the currently active M4 core clock source and its frequency. + * + * @param[out] core_clock Pointer to a variable where the current core clock frequency will be stored (in MHz). + * + * @return sl_si91x_m4_soc_clk_src_sel_t The currently active core clock source: + * - 0: M4_ULPREFCLK + * - 2: M4_SOCPLLCLK + * - 3: M4_MODEMPLLCLK1 + * - 4: M4_INTFPLLCLK + * - 5: M4_SLEEPCLK + * + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_si91x_m4_soc_clk_src_sel_t sl_si91x_clock_manager_m4_get_core_clk_src_freq(uint32_t *m4_core_clk_freq) +{ + M4CLK_Type *pCLK = M4CLK; + sl_si91x_m4_soc_clk_src_sel_t m4_core_clk_src; + + // return currently active core clock frequency via the pointer by reference + *m4_core_clk_freq = system_clocks.soc_clock; + + // read currently active core clock source + m4_core_clk_src = pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL; + + return m4_core_clk_src; +} + +/***************************************************************************/ +/** + * @brief Gets the selected PLL (Phase-Locked Loop) clock to the desired frequency. + * + * @param[in] pll_type Enum specifying the type of PLL to configure. + * + * @return uint32_t PLL frequency value in MHz. + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +uint32_t sl_si91x_clock_manager_get_pll_freq(PLL_TYPE_T pll_type) +{ + uint32_t pll_freq = 0; + + switch (pll_type) { + case SOC_PLL: + // return currently configured SOC PLL frequency + pll_freq = system_clocks.soc_clock; + break; + + case INTF_PLL: + // return currently configured INTF PLL frequency + pll_freq = system_clocks.intf_pll_clock; + break; + + case I2S_PLL: + // return currently configured I2S PLL frequency + pll_freq = system_clocks.i2s_pll_clock; + break; + + default: + break; + } + + return pll_freq; +} +/***************************************************************************/ +/** + * @brief Controls the selected PLL (Phase-Locked Loop) clock. + * + * @param[in] pll_type Enum specifying the type of PLL to control. + * @param[in] enable Boolean value to enable (true) or disable (false) the PLL. + * + * @return sl_status_t Status code indicating the result: + * - SL_STATUS_OK - Success. + * - Corresponding error code on failure. + * + * For more information on status codes, see [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_clock_manager_control_pll(PLL_TYPE_T pll_type, bool enable) +{ + sl_status_t status = SL_STATUS_OK; + + switch (pll_type) { + case SOC_PLL: + // Turn On/Off the SOC PLL + enable ? RSI_CLK_SocPllTurnOn() : RSI_CLK_SocPllTurnOff(); + break; + + case INTF_PLL: + // Turn On/Off the INTF PLL + enable ? RSI_CLK_IntfPLLTurnOn() : RSI_CLK_IntfPLLTurnOff(); + break; + + case I2S_PLL: + // Turn On/Off the I2S PLL + enable ? RSI_CLK_I2sPllTurnOn() : RSI_CLK_I2sPllTurnOff(); + break; + + default: + status = SL_STATUS_INVALID_PARAMETER; + break; + } + + return status; +} +/******************************************************************************* + * To validate the RSI error code + * While calling the RSI APIs, it returns the RSI Error codes. + * This function converts the RSI error codes into SL error codes. + * It takes argument as RSI error type and returns the SL error type. + * It has a single switch statement which is mapped with the SL error code and + * after successful conversion it breaks the switch statement. + * If the error code is not listed, by default is SL_STATUS_FAIL. + ******************************************************************************/ +static sl_status_t convert_rsi_to_sl_error_code(rsi_error_t error) +{ + sl_status_t status; + switch (error) { + case RSI_OK: + status = SL_STATUS_OK; + break; + case INVALID_PARAMETERS: + status = SL_STATUS_INVALID_PARAMETER; + break; + case ERROR_INVALID_INPUT_FREQUENCY: + status = SL_STATUS_INVALID_PARAMETER; + break; + case ERROR_CLOCK_NOT_ENABLED: + status = SL_STATUS_NOT_INITIALIZED; + break; + case INVALID_SAMPLING_RATE: + status = SL_STATUS_INVALID_RANGE; + break; + case INVALID_SAMPLE_LENGTH: + status = SL_STATUS_INVALID_COUNT; + break; + case ERROR_ADC_INVALID_ARG: + status = SL_STATUS_INVALID_PARAMETER; + break; + case ERROR_PS_INVALID_STATE: + status = SL_STATUS_INVALID_PARAMETER; + break; + default: + status = SL_STATUS_FAIL; + break; + } + return status; +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h new file mode 100644 index 000000000..5e98b03f5 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ipmu.h @@ -0,0 +1,829 @@ +/******************************************************************************* +* @file rsi_ipmu.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_IPMU_H__ +#define __RSI_IPMU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AT_EFUSE_DATA_1P19 +#include "rsi_ccp_common.h" +#include "rsi_error.h" + +/****************************************************** + * * Macros + * ******************************************************/ +#define RET_LDO_VOL_DECREASE 1 +#define RET_LDO_TRIM_VALUE_CHECK 2 + +#define REG_GSPI_BASE 0x24050000 +#define NPSS_BASE_ADDR 0x24048000 +#define NPSS_NWP_BASE_ADDR 0x41300000 +#define MCURET_BOOTSTATUS (volatile uint32_t *)(NPSS_BASE_ADDR + 0x604) +#define MCU_BBFF_STORAGE1_ADDR (volatile uint32_t *)(NPSS_NWP_BASE_ADDR + 0x580) +#define TA_MANF_DATA_BASE_ADDR 0x04000000 +#define MCU_MANF_DATA_BASE_ADDR 0x08000000 +#define TA_FLASH 1 + +/*IPMU power gates */ +#define CMP_NPSS_PG_ENB BIT(16) /*Power gate enable for BOD CORE*/ +#define ULP_ANG_CLKS_PG_ENB BIT(15) /*Power gate enable for CLKS CORE*/ +#define ULP_ANG_PWRSUPPLY_PG_ENB BIT(14) /*Power gate enable for BG SPI*/ +#define WURX_PG_ENB BIT(13) /*Power gate enable for WURX*/ +#define WURX_CORR_PG_ENB BIT(12) /*Power gate enable for WURX CORRELATION BLOCK*/ +#define AUXADC_PG_ENB BIT(11) /*Power gate enable for AUXADC*/ +#define AUXADC_BYPASS_ISO_GEN BIT(10) /*power gate bypass for AUXADC*/ +#define AUXADC_ISOLATION_ENABLE BIT(9) /*power gate isolation for AUXADC*/ +#define AUXDAC_PG_ENB BIT(8) /*Power gate enable for AUXDAC*/ +#define AUXDAC_BYPASS_ISO_GEN BIT(7) /*power gate bypass for AUXDAC*/ +#define AUXDAC_ISOLATION_ENABLE BIT(6) /*power gate isolation for AUXDAC*/ +#define AUX_SUPPLY_ISOLATION_ENABLE BIT(5) /*Given to analog peripherals indicating the supply state*/ +#define PMU_ANA_BYPASS_PWRGATE_EN_N BIT(4) /*To ON or OFF analog blocks in PMU when pwr manager is bypassed*/ +#define PMU_SPI_BYPASS_ISO_GEN BIT(3) /*Bypass power manager for PMU_SPI*/ +#define PMU_SPI_ISOLATION_ENABLE BIT(2) /*Bypass isoaltion enable signal for PMU_SPI isoaltion cells*/ +#define PMU_BUCK_BYPASS_ISO_GEN BIT(1) /*Bypass power manager for PMU BUCK*/ +#define PMU_BUCK_BYPASS_ISOLATION_ENABLE BIT(0) /*Bypass isoaltion enable signal for PMU_BUCK isoaltion cells*/ + +/*IPMU configuration defines*/ +#define LATCH_TOP_SPI BIT(4) +#define LATCH_TRANSPARENT_HF BIT(3) +#define LATCH_TRANSPARENT_LF BIT(2) + +/*BG_SCDC_PROG_REG_1 defines*/ +#define REF_SEL_LP_DCDC 0xFFFFFC7F + +/*Registers */ +#define BG_SCDC_PROG_REG_1 0x127 +#define SELECT_BG_CLK 0x144 +#define BG_SCDC_PROG_REG_2 0x128 +//#define WURX_CORR_CALIB_REG 0x088 +#define POWERGATE_REG_WRITE 0x142 +//#define ULPCLKS_REFCLK_REG 0x106 +//#define WURX_CORR_CALIB_REG 0x088 + +#define GSPI_CTRL_REG1 *(volatile uint32_t *)(REG_GSPI_BASE + 0x02) +#define SPI_ACTIVE BIT(8) + +#define POSITION_BITS_MASK 0x1F +#define LSB_POSITION 22 +#define MSB_POSITION 27 +#define MAX_BIT_LEN 22 + +#define ULPCLKS_32KRC_CLK_REG_ADDR 0x103 + +#define ENABLE_CALIB_DOMAIN 0x005200 +#define SELECT_RO_CALIB 0x002310 +#define TRIM_VALUE_BITS 0x0003f800 +#define MASK_TRIM_VALUE_WRITE_BITS 0x1FC000 +#define ULPCLKS_TRIM_SEL_REG_DEFAULT 0x005a14 + +#define MAX_RESP_BUF_FOR_IAP 3 + +#define BASE_OFFSET_BB_RF_IN_FLASH 424 + +#define PMU_SPI_BASE_ADDR 0x24050000 + +//! PMU +#define PMU_SPI_DIRECT_ACCESS(_x) *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0x8000 + ((_x) << 2)) +//! IPMU +#define PMU_DIRECT_ACCESS(_x) *(volatile uint32_t *)(PMU_SPI_BASE_ADDR + 0xA000 + ((_x) << 2)) +#define PMU_SPI 1 + +#define RC_CLK_MODE 1 + +#define XTAL_SEL 1 + +#define TS_SLOPE_SET_OFFSET 0x04 +#define PMU_1P3_CTRL_REG_OFFSET 0x1D0 +#define PMU_PFM_REG_OFFSET 0x1D1 +#define PMU_ADC_REG_OFFSET 0x1D2 +#define PMU_PID_REG1_OFFSET 0x1D3 +#define PMU_PTAT_REG_OFFSET 0x1D5 +#define PMU_LDO_REG_OFFSET 0x1D6 +#define PMU_PWRTRAIN_REG_OFFSET 0x1D8 +#define PMU_TESTMUX_REG1_OFFSET 0x1D9 +#define PMU_TEST_MODES_OFFSET 0x1DA +#define SPARE_REG_1_OFFSET 0x1DC +#define SPARE_REG_2_OFFSET 0x1DD +#define BYPASS_CURR_CTRL_REG_OFFSET 0x1DE +#define SPARE_REG_3_OFFSET 0x1DF + +#ifdef CHIP_9118 +//FLASH OFFSET +#define __CALIB_DATA_OFFSET_ 1024 +#define IPMU_VALUES_OFFSET (__CALIB_DATA_OFFSET_ + 168) +#define DUAL_FLASH_IPMU_VALUES_OFFSET MCU_MANF_DATA_BASE_ADDR +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) +#if (((defined SLI_SI917 || defined SLI_SI915) && (defined SLI_SI917B0 || defined SLI_SI915)) \ + || (defined CHIP_917_6x6 && (defined SLI_SI917B0 || defined SLI_SI915))) +#ifdef SLI_SI91X_MCU_4MB_LITE_IMAGE +#define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x8160292 +#define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x8160293 +#define COMMON_FLASH_IPMU_VALUES_OFFSET 0x8160258 +#else +#define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x81F0292 +#define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x81F0293 +#define COMMON_FLASH_IPMU_VALUES_OFFSET 0x81F0258 +#endif +#define PACKAGE_TYPE_VALUES_OFFSET_DUAL_FLASH 0x800059B +#define SILICON_REV_VALUES_OFFSET_DUAL_FLASH 0x800059C +#define DUAL_FLASH_IPMU_VALUES_OFFSET 0x8000561 +#endif +#if ((defined SLI_SI917) && (!(defined SLI_SI917B0))) +#define PACKAGE_TYPE_VALUES_OFFSET_COMMON_FLASH 0x82001DE +#define SILICON_REV_VALUES_OFFSET_COMMON_FLASH 0x82001DF +#define COMMON_FLASH_IPMU_VALUES_OFFSET 0x82001A4 +#define COMMON_FLASH_IPMU_VALUES ((efuse_ipmu_t *)(COMMON_FLASH_IPMU_VALUES_OFFSET)) + +#define PACKAGE_TYPE_VALUES_OFFSET_DUAL_FLASH 0x80004E0 +#define SILICON_REV_VALUES_OFFSET_DUAL_FLASH 0x80004E1 +#define DUAL_FLASH_IPMU_VALUES_OFFSET 0x80004A6 +#define DUAL_FLASH_IPMU_VALUES ((efuse_ipmu_t *)(DUAL_FLASH_IPMU_VALUES_OFFSET)) +#endif +#define IPMU_VALUES_OFFSET 0 +#endif +#define HP_LDO_MODE 1 +#define SCDC_MODE 0 +#ifdef ENABLE_1P8V +#define IPMU_MODE_VALUE HP_LDO_MODE +#else +#define IPMU_MODE_VALUE SCDC_MODE +#endif + +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE +#define MANF_DATA_BASE_ADDR COMMON_FLASH_IPMU_VALUES_OFFSET +#else +#define MANF_DATA_BASE_ADDR DUAL_FLASH_IPMU_VALUES_OFFSET +#endif + +/* After changes */ +#define MAGIC_WORD 0x5a + +#define NWP_AHB_ADDR 0x41300000 +#define ULP_TASS_MISC_CONFIG_REG 0x24041400 +#define AUX_BASE_ADDR 0x24043800 +#define TEMP_SENSOR_BASE_ADDRESS 0x24048500 +#define TS_NOMINAL_SETTINGS_OFFSET 0x08 +#define DIRECT 2 + +#define MASK_BITS(A, B) (((1U << A) - 1) << B) +#define ULP_SPI 0 +#define ULPCLKS_DOUBLER_XTAL_REG_OFFSET 0x101 +#define ULPCLKS_32KRO_CLK_REG_OFFSET 0x102 +#define ULPCLKS_32KRC_CLK_REG_OFFSET 0x103 +#define ULPCLKS_MRC_CLK_REG_OFFSET 0x104 +#define ULPCLKS_HF_RO_CLK_REG_OFFSET 0x105 +#define ULPCLKS_REFCLK_REG_ADDR 0x106 +#define ULPCLKS_TRIM_SEL_REG_ADDR 0x107 +#define ULPCLKS_CALIB_REG_ADDR 0x10A +#define ULPCLKS_CALIB_REF_REG 0x10B +#define ULPCLKS_CALIB_DONE_REG_ADDR 0x10C +#define ULPCLKS_32KXTAL_CLK_REG_OFFSET 0x10E +#define BG_SCDC_PROG_REG_1_OFFSET 0x127 +#define iPMU_SPARE_REG1_OFFSET 0x140 +#if defined(SLI_SI917) || defined(SLI_SI915) +#define BG_SCDC_PROG_REG_3_ADDR 0x12B +#endif + +#define HF_RC_CLK_MODE 1 +#define MCU_PWR_CTRL_BASE_ADDR 0x24048400 +#define MCU_PMU_LDO_CTRL_CLEAR_REG_1 *(volatile uint32 *)(MCU_PWR_CTRL_BASE_ADDR + 0x6C) +#define TEMP_SENSOR_BASE_ADDRESS 0x24048500 +#define MCU_FSM_BASE_ADDRESS 0x24048100 + +//! ULP SPI (0x2405A000) +#define ULPCLKS_ADAPTIVE_REG_OFFSET 0x100 +#define ULPCLKS_DOUBLER_XTAL_REG_OFFSET 0x101 +#define ULPCLKS_32KRO_CLK_REG_OFFSET 0x102 +#define ULPCLKS_32KRC_CLK_REG_OFFSET 0x103 +#define ULPCLKS_MRC_CLK_REG_OFFSET 0x104 +#define ULPCLKS_HF_RO_CLK_REG_OFFSET 0x105 +#define ULPCLKS_REF_CLK_REG_OFFSET 0x106 +#define ULPCLKS_TRIM_SEL_REG_OFFSET 0x107 +#define ULPCLKS_32KXTAL_CLK_REG_OFFSET 0x10E +#define BG_SLEEP_TIMER_REG_OFFSET 0x125 +#define SCDC_CTRL_REG_0_OFFSET 0x126 +#define BG_SCDC_PROG_REG_1_OFFSET 0x127 +#define BG_SCDC_PROG_REG_2_OFFSET 0x128 +#define BG_LDO_REG_OFFSET 0x129 +#define BG_SCDC_READ_BACK_OFFSET 0x12A +#define BG_BLACKOUT_REG_OFFSET 0x12B +#define iPMU_SPARE_REG1_OFFSET 0x140 +#define iPMU_SPARE_REG2_OFFSET 0x141 +#define POWERGATE_REG_WRITE_OFFSET 0x142 +#define SELECT_BG_CLK_OFFSET 0x144 +#define BOD_TEST_PG_VBATT_STATUS_REG_OFFSET 0x1E3 +#define POWERGATE_REG_READ_OFFSET 0x342 + +//! PMU SPI (0x24058000) +#define PMU_1P3_CTRL_REG_OFFSET 0x1D0 +#define PMU_PFM_REG_OFFSET 0x1D1 +#define PMU_ADC_REG_OFFSET 0x1D2 +#define PMU_PID_REG1_OFFSET 0x1D3 +#define PMU_PTAT_REG_OFFSET 0x1D5 +#define PMU_LDO_REG_OFFSET 0x1D6 +#define PMU_PWRTRAIN_REG_OFFSET 0x1D8 +#define PMU_TESTMUX_REG1_OFFSET 0x1D9 +#define PMU_TEST_MODES_OFFSET 0x1DA +#define SPARE_REG_1_OFFSET 0x1DC +#define SPARE_REG_2_OFFSET 0x1DD +#define BYPASS_CURR_CTRL_REG_OFFSET 0x1DE +#define SPARE_REG_3_OFFSET 0x1DF +#define PMU_FREQ_MODE_REG 0x1CE +#define LOW_FREQ_PWM BIT(2) +#define MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_OFFSET 0x20 +#define MCU_FSM_PMU_STATUS_REG_OFFSET 0x40 + +//! NWP_PMU_CTRLS defines +#define scdcdc_lp_mode_en BIT(0) +#define bgpmu_sleep_en BIT(1) +#define standby_dc1p3 BIT(19) + +#define MCU_AON_BASE_ADDR 0x24048000 +#define MCU_FSM_PMU_CTRL *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x140) +#define MCUAON_GEN_CTRLS_REG *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x14) +#define MCUAON_SHELF_MODE *(volatile uint32 *)(MCU_AON_BASE_ADDR + 0x10) + +//! MCUAON_GEN_CTRLS register defines +#define NPSS_SUPPLY_0P9_BIT BIT(17) +#define ENABLE_PDO_BIT BIT(16) + +#define NWP_AHB_ADDR 0x41300000 +#define ULP_DIRECT_ACCESS(_x) *(uint32 *)(NWP_AHB_ADDR + (_x)) +#define NWPAON_POR_CTRL_BITS_REG 0x3C +#define NWP_FSM_FIRST_BOOTUP 0x0120 + +//! NWP_FSM_FIRST_BOOTUP defines +#define nwp_ulp_32khz_xtal_clk_en BIT(18) +#define nwp_ulp_mhz_rc_clk_en BIT(19) +#define nwp_ulp_20mhz_ring_osc_clk_en BIT(20) +#define nwp_ulp_doubler_clk_en BIT(21) + +#define TASS_PWR_CTRL_BASE_ADDR 0x41300400 +#define TASS_FSM_CTRL_BYPASS *(volatile uint32 *)(TASS_PWR_CTRL_BASE_ADDR + 0x1C) +//! TASS_FSM_CTRL_BYPASS defines +#define ta_xtal_en_40MHz_bypass_cntrl BIT(0) +#define ta_xtal_en_40MHz_bypass BIT(1) +#define ta_pmu_shut_down_bypass_cntrl BIT(2) +#define ta_pmu_shut_down_bypass BIT(3) +#define ta_buck_boost_enable_bypass_cntrl BIT(4) +#define ta_buck_boost_enable_bypass BIT(5) + +//! ULPCLKS_ADAPTIVE_REG defines +#define adapt_powergate_en BIT(3) + +//! ULPCLKS_DOUBLER_XTAL_REG defines +#define doubler_en BIT(21) + +//! ULPCLKS_32MRC_CLK_REG defines +#define rc_mhz_en BIT(21) + +//! ULPCLKS_HF_RO_CLK_REG defines +#define ro_hf_en BIT(21) + +//! ULPCLKS_TRIM_SEL_REG defines +#define calib_powergate_en BIT(9) + +//! ULPCLKS_32KXTAL_CLK_REG defines +#define xtal_32khz_en BIT(21) + +#define pass_clk_40m_buffer_enable BIT(15) + +//! iPMU_SPARE_REG2 defines +#define wurx_lvl_shift_en BIT(20) +#define wurx_pg_en_1 BIT(21) + +//! POWERGATE_REG_WRITE defines +#define auxdac_pg_enb BIT(8) +#define auxadc_pg_enb BIT(11) +#define wurx_corr_pg_enb BIT(12) +#define wurx_pg_enb BIT(13) +#define ulp_ang_pwrsupply_pg_enb BIT(14) +#define ulp_ang_clks_pg_enb BIT(15) +#define cmp_npss_pg_enb BIT(16) + +#define IPMU_HIGH_POWER_MODE 0 +#define IPMU_LOW_POWER_MODE 1 + +//! SELECT_BG_CLK defines +#define latch_transparent_lf BIT(2) +#define latch_transparent_hf BIT(3) +#define latch_top_spi BIT(4) + +//! PMU_PFM_REG defines +#define ext_pfm_en1p3 BIT(17) + +//! PMU_PTAT_REG defines +#define test_pfm_mode1p3 BIT(4) + +//! PMU_LDO_REG defines +#define LDOSOC_DEFAULT_MODE_EN BIT(5) + +//! PMU_PWRTRAIN_REG defines +#define BYPASS_LDORF_CTRL BIT(2) + +//! BOD_TEST_PG_VBATT_STATUS_REG defines +#define bod_pwrgate_en_n_ulp_button_calib BIT(15) + +//! MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP defines +#define mcu_ulp_32khz_xtal_clk_en BIT(18) +#define mcu_ulp_mhz_rc_clk_en BIT(19) +#define mcu_ulp_20mhz_ring_osc_clk_en BIT(20) +#define mcu_ulp_doubler_clk_en BIT(21) + +//! NWPAON_POR_CTRL_BITS defines +#define poc_cntrl_reg_0 BIT(0) + +#define MCU_FSM_DIRECT_ACCESS(_x) *(volatile uint32 *)(MCU_FSM_BASE_ADDRESS + (_x)) + +#define TEMP_SENSOR_BJT *(volatile uint32 *)(0x240439E0) +#define temp_sens_en BIT(0) + +#define TS_SLOPE_SET_OFFSET 0x04 +#define TS_NOMINAL_SETTINGS_OFFSET 0x08 + +//! BG_SCDC_PROG_REG_2 defines +#define scdcdc_sel BIT(21) +#define testmode_0_en BIT(20) + +//! SCDC_CTRL_REG_0 defines +#define ext_cap_en BIT(21) + +//! PMU_LDO_REG defines +#define LDORF_DEFAULT_MODE_EN BIT(11) + +#define LS_SHIFT 22 +#define MS_SHIFT 27 +#define IPMU_DATAMASK 0x3fffff + +#define mcu_dcdc_lvl BIT(18) +#define mcu_soc_ldo_lvl BIT(17) + +/*32khz rc clock define */ +#define RC_TRIM_VALUE_LF 0x7F0 +#define RO_TRIM_VALUE_LF 0x1F0 +#define MASK32KRO_TRIM_VALUE_WRITE_BITS 0x1F0000 +#define MASK32KRC_TRIM_VALUE_WRITE_BITS 0x1FC000 +#define TRIM_MSB_MHZ 20 +#define TRIM_LSB_MHZ 14 +#define PARTICULAR_FREQ_MIN 10 +#define PARTICULAR_FREQ_MAX 100 +#define MIN_DIFF_FREQ 3 + +/* 64khz rc clock define */ +#define ENABLE_32KHZ_CLOCK_TRIM 0x40F03000 +#define NPSS_REF_CLOCK_40MSOC 0x41A48000 +#define NUMBER_HIGH_FRQ_CLOCK 0x42C4E390 +#define LOW_FREQ_CLOCK_CAL 0x42B24210 +#define ORIGINAL_REF_VALUE_AFTER_CAL 0x42C9C590 + +/****************************************************** + * * Structures + * ******************************************************/ + +//! This structure contains format for retention_boot_status_word_0 +typedef struct retention_boot_status_word_s { +#define SDIO_USB_WITH_TA 3 +#define SDIO_WITH_TA_USB_WITH_M4 2 +#define SDIO_WITH_M4_USB_WITH_TA 1 +#define SDIO_USB_WITH_M4 0 + unsigned int m4_present : 1; + unsigned int m4_flash_present : 1; + unsigned int m4_flash_pinset : 4; + unsigned int m4_flash_address_width_valid : 1; + unsigned int m4_flash_address_width : 2; + unsigned int select_host_inf_with_m4_valid : 1; + unsigned int select_host_inf_with_m4 : 2; + unsigned int m4_secure_boot_enable : 1; + unsigned int m4_encrypt_firmware : 1; + unsigned int host_if_with_ta : 1; + unsigned int mcu_wdt_hw_timer : 1; +#ifdef CHIP_9118 +#define NONE_MODE 0 +#define NLINK 1 +#define WISECONNECT 2 +#define WCPLUS 3 +#define MCU 4 +#define WISEMCU 5 +#define ACCELARATOR 6 +#define WC_SIMULATANEOUS 7 +#endif +#if defined(SLI_SI917) || defined(SLI_SI915) +//! Product modes +#define WISEMCU 0 +#define WCPLUS 3 +#define ACCELARATOR 4 +#define WISECONNECT 6 +#define NLINK 7 +#define MCU 0xF // not supported +#endif + unsigned int product_mode : 4; + unsigned int m4_flash_type : 4; + unsigned int m4_dual_flash : 1; + unsigned int m4_csum : 1; + unsigned int wise_aoc_mode : 1; + unsigned int wise_aoc_from_m4_rom : 1; + unsigned int m4_image_format : 1; + unsigned int clean_ulp_wakeup : 1; +#define M4_IMAGE_VALID_IND BIT(30) + unsigned int m4_image_valid : 1; + unsigned int reserved : 1; /* one bit is reserved for hardware */ +} retention_boot_status_word_t; + +/* This structure contains format for efuse_dword0 */ +typedef struct npss_boot_status_word_0_s { + //! Data from EFUSE + unsigned int usb_fsel_valid : 1; + unsigned int mems_ref_clk_as_usb_phy_clk : 1; + unsigned int modem_pll_as_usb_phy_clk : 1; + unsigned int usb_phy_clk_fsel_external : 1; + unsigned int usb_fsel : 3; + unsigned int bypass_usb_detection : 1; + //! Data derived by bootloder + unsigned int host_sel_valid : 1; + unsigned int host_sel : 3; + unsigned int ta_flash_present : 1; + unsigned int ta_flash_pinset : 4; + unsigned int ta_flash_address_width_valid : 1; + unsigned int ta_flash_address_width : 2; + unsigned int ta_flash_type : 4; + unsigned int fips_enable : 1; + unsigned int usb_fclk_div_factor : 2; +#define BBFF_DATA_VALID BIT(27) + unsigned int bbff_data_valid : 1; + //! Bits configured by FW +#define NWP_SOFT_RESET BIT(28) + unsigned int soft_reset : 1; +#define FACTORY_RESET BIT(29) + unsigned int factory_reset : 1; +#define TAMPER_RECOVERY BIT(30) + unsigned int tamper_recovery : 1; + unsigned int reserved : 1; +} npss_boot_status_word0_t; + +#ifdef CHIP_9118 +typedef struct efuse_ipmu_s { + unsigned int trim_0p5na1 : 1; + unsigned int trim_0p5na2 : 1; + unsigned int bg_r_vdd_ulp : 4; + unsigned int bg_r_ptat_vdd_ulp : 3; + unsigned int resbank_trim : 2; + unsigned int trim_sel : 7; + unsigned int del_2x_sel : 6; + unsigned int freq_trim : 5; + unsigned int coarse_trim_16k : 2; + unsigned int fine_trim_16k : 7; + unsigned int coarse_trim_64k : 2; + unsigned int fine_trim_64k : 7; + unsigned int coarse_trim_32k : 2; + unsigned int fine_trim_32k : 7; + unsigned int xtal1_trim_32k : 4; + unsigned int xtal2_trim_32k : 4; + unsigned int trim_ring_osc : 7; + unsigned int vbatt_status_1 : 6; + unsigned int str_temp_slope : 10; + unsigned int f2_nominal : 10; + unsigned int str_nominal_temp : 7; + unsigned int str_bjt_temp_sense_off : 16; + unsigned int str_bjt_temp_sense_slope : 16; +#ifndef AT_EFUSE_DATA_1P19 + unsigned int reserved1 : 20; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + unsigned int trim_sel_20Mhz : 7; // Trim value for 20mzh rc + unsigned int ro_32khz_00_trim : 5; + unsigned int scdc_dcdc_trim : 3; + unsigned int scdc_hpldo_trim : 3; + unsigned int reserved1 : 2; +#endif + unsigned int ldo_ctrl : 4; +#ifndef AT_EFUSE_DATA_1P19 + unsigned int reserved2 : 16; +#endif +#ifdef AT_EFUSE_DATA_1P19 + unsigned int vbg_tsbjt_efuse : 12; + unsigned int retn_ldo_lptrim : 3; + unsigned int reserved2 : 1; +#endif + unsigned int auxadc_offset_diff : 12; + unsigned int auxadc_invgain_diff : 16; + unsigned int auxadc_offset_single : 12; + unsigned int auxadc_invgain_single : 16; + unsigned int set_vref1p3 : 4; + +#ifndef AT_EFUSE_DATA_1P19 + unsigned int set_vref_isense1p3 : 2; + unsigned int set_vref_adc : 2; + unsigned int vtrim_ldosoc : 2; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + unsigned int reserved13 : 6; +#endif + + unsigned int trim_r1_resistorladder : 4; +#ifndef AT_EFUSE_DATA_1P19 + unsigned int enable_undershoot_reduction : 1; + unsigned int select_vref_comp : 2; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + unsigned int retn_ldo_hptrim : 3; +#endif + +#ifndef AT_EFUSE_DATA_1P19 + unsigned int pwr_gd_threshold_sel : 1; + unsigned int sel_overshoot_control : 1; + unsigned int ptat_load_ctrl : 3; + unsigned int ctrl_soc : 4; + unsigned int pt_gate_ctrl : 3; + unsigned int default_mode_ctrl : 1; + unsigned int ptat_load_enable : 1; + unsigned int ldosoc_outputpulldown_sel : 1; + unsigned int ldosoc_outputpulldown : 1; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + unsigned int reserved12 : 16; +#endif + + unsigned int scale_soc_ldo_vref : 1; + +#ifndef AT_EFUSE_DATA_1P19 + unsigned int ctrl_rf : 4; + unsigned int default_mode : 1; + unsigned int test_ldopulldown_sel : 1; + unsigned int test_ldopulldown : 1; + unsigned int drive_n : 2; + unsigned int drive_p : 2; + unsigned int deadtime_ctrl_n2p : 4; + unsigned int deadtime_ctrl_p2n : 4; + unsigned int revi_offset_prog : 3; + unsigned int tran_lo_ctr : 2; + unsigned int tran_hi_ctr : 2; + unsigned int tran_und_shoot_ctr : 3; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + unsigned int reserved11 : 7; + unsigned int reserved10 : 12; + unsigned int reserved9 : 10; +#endif + + unsigned int dpwm_freq_trim : 4; + +#ifndef AT_EFUSE_DATA_1P19 + unsigned int pfmro_freq_trim : 3; + unsigned int test_revi_delay : 1; + unsigned int sel_sleep_nmos_ctrl : 1; + unsigned int p_1p3 : 13; + unsigned int i_steady_state1p3 : 13; + unsigned int d_1p3 : 15; + unsigned int i_soft_start1p3 : 13; + unsigned int dither_en1p3 : 1; + unsigned int auto_mode_tran_disable : 1; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + unsigned int reserved73 : 1; + unsigned int reserved74 : 13; + unsigned int reserved75 : 13; + unsigned int reserved76 : 15; + unsigned int reserved77 : 13; + unsigned int reserved78 : 1; + unsigned int reserved79 : 1; +#endif + + unsigned int pfm_pon_time_sel : 4; + +#ifndef AT_EFUSE_DATA_1P19 + unsigned int pfm_non_time_sel : 3; + unsigned int pwm_cont_prog : 3; + unsigned int pfm_clk_up_del_sel : 3; + unsigned int pwm_to_pfm_pulse_count_prog : 2; + unsigned int pfm_to_pwm_pulse_count_prog : 2; + unsigned int pfm_to_pwm_cur_prog : 3; + unsigned int pwm_to_pfm_cur_prog : 3; + unsigned int max_duty_cycle_threshold : 3; + unsigned int min_duty_cycle_threshold : 3; + unsigned int bypass_pfm_to_pwm_counter_1 : 1; + unsigned int no_of_pfm_clk : 4; + unsigned int adc_op_thresh_sel : 2; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + unsigned int reserved6; + unsigned int reserved31 : 3; + unsigned int reserved32 : 3; + unsigned int reserved33 : 3; + unsigned int reserved34 : 2; + unsigned int reserved35 : 2; + unsigned int reserved36 : 3; + unsigned int reserved37 : 3; + unsigned int reserved38 : 3; + unsigned int reserved39 : 3; + unsigned int reserved40 : 1; + unsigned int reserved41 : 4; + unsigned int reserved42 : 2; +#endif + unsigned int reserved3 : 4; + unsigned int reserved4[2]; + uint16_t reserved5; + +} __attribute__((__packed__)) efuse_ipmu_t; +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) +typedef struct efuse_ipmu_s { + unsigned int trim_0p5na1 : 1; + unsigned int bg_r_vdd_ulp : 5; + unsigned int bg_r_ptat_vdd_ulp : 3; + unsigned int reserved20 : 2; //Removed in RS9117 + unsigned int trim_sel : 7; + unsigned int del_2x_sel : 6; + unsigned int freq_trim : 5; + unsigned int coarse_trim_16k : 2; + unsigned int fine_trim_16k : 7; + unsigned int coarse_trim_64k : 2; + unsigned int fine_trim_64k : 7; + unsigned int coarse_trim_32k : 2; + unsigned int fine_trim_32k : 7; + unsigned int xtal1_trim_32k : 4; + unsigned int xtal2_trim_32k : 4; + unsigned int trim_ring_osc : 7; + unsigned int vbatt_status_1 : 6; + unsigned int str_temp_slope : 10; + unsigned int f2_nominal : 10; + unsigned int str_nominal_temp : 7; + unsigned int str_bjt_temp_sense_off : 16; + unsigned int str_bjt_temp_sense_slope : 16; + unsigned int trim_sel_20Mhz : 7; // Trim value for 20mzh rc + unsigned int ro_32khz_00_trim : 5; + unsigned int scdc_dcdc_trim : 3; + unsigned int scdc_hpldo_trim : 3; + unsigned int reserved1 : 2; + unsigned int ldo_ctrl : 4; + unsigned int vbg_tsbjt_efuse : 12; + unsigned int retn_ldo_lptrim : 3; + unsigned int reserved2 : 1; + unsigned int auxadc_offset_diff : 12; + unsigned int auxadc_invgain_diff : 16; + unsigned int auxadc_offset_single : 12; + unsigned int auxadc_invgain_single : 16; + unsigned int set_vref1p3 : 4; + unsigned int reserved13 : 6; + unsigned int trim_r1_resistorladder : 4; + unsigned int retn_ldo_hptrim : 3; + unsigned int reserved12 : 16; + unsigned int scale_soc_ldo_vref : 1; + unsigned int reserved11 : 7; + unsigned int reserved10 : 12; + unsigned int reserved9 : 10; + unsigned int dpwm_freq_trim : 4; + unsigned int reserved73 : 32; // 73 and 74 togther as 50 + unsigned int reserved74 : 18; // + unsigned int scdc_clk_freq : 5; + unsigned int reserved7 : 6; + unsigned int buck_ind_efuse : 4; + unsigned int reserved31 : 32; // 31,32 and 33 togther as 80 + unsigned int reserved32 : 32; + unsigned int reserved33 : 16; +} __attribute__((__packed__)) efuse_ipmu_t; +#endif + +/* Clock trim APL structure */ +typedef enum INPUT_CLOCK { + ulp_ref_clk = 0, + ulp_20mhz_ringosc_clk = 2, + sleep_clk = 8, + soc_pll_clk = 6 + +} INPUT_CLOCK_T; + +typedef enum SLEEP_CLOCK { khz_rc_clk = 0x0, khz_xtal_clk = 0x1, khz_ro_clk = 0x3, none = 0x233 } SLEEP_CLOCK_T; + +/****************************************************** + * * Global Variables + * ******************************************************/ + +/****************************************************** + * * Function Declarations + * ******************************************************/ +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_IPMU_DRIVERS RSI:RS1xxxx IPMU + * @{ + * + */ +rsi_error_t RSI_IPMU_Xtal2bias_Efuse(void); +rsi_error_t RSI_IPMU_Xtal1bias_Efuse(void); +uint32_t RSI_IPMU_Delvbe_Tsbjt_Efuse(void); +rsi_error_t RSI_IPMU_Dpwmfreq_TrimEfuse(void); +rsi_error_t RSI_IPMU_Ldosoc_TrimEfuse(void); +rsi_error_t RSI_IPMU_Buck_TrimEfuse(void); +rsi_error_t RSI_IPMU_POCbias_Efuse(void); +rsi_error_t RSI_IPMU_Blackout_TrimEfuse(void); +rsi_error_t RSI_IPMU_Bg_TrimEfuse(void); +uint32_t RSI_IPMU_Auxadcgain_SeEfuse(void); +uint32_t RSI_IPMU_Auxadcoff_SeEfuse(void); +uint32_t RSI_IPMU_Auxadcoff_DiffEfuse(void); +uint32_t RSI_IPMU_Auxadcgain_DiffEfuse(void); +uint32_t RSI_IPMU_Vbg_Tsbjt_Efuse(void); +uint32_t RSI_IPMU_RO_TsEfuse(void); +rsi_error_t RSI_IPMU_Vbattstatus_TrimEfuse(void); +rsi_error_t RSI_IPMU_RC32khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_RC64khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_RC16khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_RO32khz_TrimEfuse(void); +rsi_error_t RSI_IPMU_M20roOsc_TrimEfuse(void); +rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void); +rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void); +rsi_error_t RSI_IPMU_PMUCommonConfig(void); +rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void); +void RSI_IPMU_PowerGateSet(uint32_t mask_vlaue); +void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue); +rsi_error_t RSI_IPMU_CommonConfig(void); +void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk); +uint32_t RSI_IPMU_32MHzClkClib(void); +rsi_error_t RSI_IPMU_ProgramConfigData(const uint32_t *config); +void RSI_IPMU_InitCalibData(void); +void RSI_IPMU_UpdateIpmuCalibData_efuse(const efuse_ipmu_t *ipmu_calib_data); +uint32_t RSI_APB_ProgramConfigData(const uint32_t *config); +uint32_t RSI_IPMU_RO_TsConfig(void); +void RSI_Configure_DCDC_LowerVoltage(void); +void RSI_IPMU_32KHzRCClkClib(void); +void RSI_IPMU_32KHzROClkClib(void); +rsi_error_t RSI_IPMU_PocbiasCurrent11(void); +rsi_error_t RSI_IPMU_RO32khzTrim00Efuse(void); +rsi_error_t RSI_IPMU_RetnHP_Volttrim_Efuse(void); +rsi_error_t RSI_IPMU_PocbiasCurrent(void); +void RSI_IPMU_RetnLdoHpmode(void); +void RSI_IPMU_RetnLdoLpmode(void); +void RSI_IPMU_Retn_Voltage_Reduction(void); +void RSI_IPMU_Retn_Voltage_To_Default(void); +void RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(void); +rsi_error_t RSI_IPMU_RetnLdo0p75(void); +rsi_error_t RSI_IPMU_RetnLdoVoltsel(void); +void RSI_IPMU_64KHZ_RCClktrim(void); +void RSI_IPMU_20M_ROClktrim(uint8_t clkfreq); +uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_type); +uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq); +void RSI_IPMU_SCDC_Enable(void); +void RSI_IPMU_HP_LDO_Enable(void); +void RSI_Ipmu_Init(void); +void RSI_Configure_Ipmu_Mode(void); +void ipmu_init(void); +void configure_ipmu_mode(uint32_t mode); +uint32_t init_ipmu_calib_data(uint32_t m4_present); +void update_ipmu_data(uint32_t reg_addr, uint32_t reg_type, uint32_t data, uint32_t mask); +void update_efuse_system_configs(int data, uint32_t config_ptr[]); +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig1(void); +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig2(void); +rsi_error_t RSI_IPMU_Hpldo_volt_trim_efuse(void); +rsi_error_t RSI_IPMU_Scdc_volt_trim_efuse(void); +void RSI_IPMU_Reconfig_to_SCDCDC(void); +rsi_error_t RSI_IPMU_Lp_scdc_extcapmode(void); +rsi_error_t RSI_IPMU_BOD_Cmphyst(void); +/** + * @} end of RSI_IPMU_DRIVERS + */ +/* @} end of RSI_IPMU_DRIVERS */ + +#ifdef __cplusplus +} +#endif +#endif // RSI_IPMU_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h new file mode 100644 index 000000000..4e9d3e0b9 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_pll.h @@ -0,0 +1,854 @@ +/******************************************************************************* +* @file rsi_pll.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_PLL_H__ +#define __RSI_PLL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_ipmu.h" +#include "rsi_reg_spi.h" + +#define MISC_CFG_MISC_CTRL (*((uint32_t volatile *)(MISC_CONFIG_BASE + 0x14))) + +typedef void (*cdDelay)(uint32_t delay); + +#define CCI_SYNC_MODE BIT(16) /* Enables CCI_SYNC_MODE */ +/*M4 Clock configuration base address */ + +/*SET Reg 1 SET / CLR*/ +#define USART1_PCLK_ENABLE BIT(0) /* Enables USART1_PCLK_ENABLE */ +#define USART1_SCLK_ENABLE BIT(1) /* Enables USART1_SCLK_ENABLE */ +#define USART2_PCLK_ENABLE BIT(2) /* Enables USART2_PCLK_ENABLE */ +#define USART2_SCLK_ENABLE BIT(3) /* Enables USART2_SCLK_ENABLE */ +#if defined(SLI_SI917B0) || defined(SLI_SI915) +#define QSPI_2_CLK_ENABLE BIT(4) /* Enables QSPI_CLK_ENABLE */ +#define QSPI_2_HCLK_ENABLE BIT(5) /* Enables QSPI_HCLK_ENABLE */ +#define QSPI_2_M4_SOC_SYNC BIT(6) /* Enables QSPI_M4_SOC_SYNC */ +#define QSPI_2_CLK_ONEHOT_ENABLE BIT(7) /* Enables QSPI_CLK_ONEHOT_ENABLE */ +#endif +#define CT_CLK_ENABLE BIT(9) /* Enables CT_CLK_ENABLE */ +#define CT_PCLK_ENABLE BIT(10) /* Enables CT_PCLK_ENABLE */ +#define ICACHE_CLK_ENABLE BIT(11) /* Enables ICACHE_CLK_ENABLE */ +#define ICACHE_CLK_2X_ENABLE BIT(12) /* Enables ICACHE_CLK_2X_ENABLE */ +#define RPDMA_HCLK_ENABLE BIT(13) /* Enables RPDMA_HCLK_ENABLE */ +#define SOC_PLL_SPI_CLK_ENABLE BIT(14) /* Enables SOC_PLL_SPI_CLK_ENABLE */ +#define IID_CLK_ENABLE BIT(16) /* Enables IID_CLK_ENABLE */ +#define SDIO_SYS_HCLK_ENABLE BIT(17) /* Enables SDIO_SYS_HCLK_ENABLE */ +#define CRC_CLK_ENABLE_M4 BIT(18) /* Enables CRC_CLK_ENABLE_M4 */ +#define M4SS_UM_CLK_STATIC_EN BIT(19) /* Enables M4SS_UM_CLK_STATIC_EN */ +#define ETH_HCLK_ENABLE BIT(21) /* Enables ETH_HCLK_ENABLE */ +#define HWRNG_PCLK_ENABLE BIT(22) /* Enables HWRNG_PCLK_ENABLE */ +#define GNSS_MEM_CLK_ENABLE BIT(23) /* Enables GNSS_MEM_CLK_ENABLE */ +#define CCI_PCLK_ENABLE BIT(24) /* Enables CCI_PCLK_ENABLE */ +#define CCI_HCLK_ENABLE BIT(25) /* Enables CCI_HCLK_ENABLE */ +#define CCI_CLK_ENABLE BIT(26) /* Enables CCI_CLK_ENABLE */ +#define MASK_HOST_CLK_WAIT_FIX BIT(27) /* Enables MASK_HOST_CLK_WAIT_FIX */ +#define MASK31_HOST_CLK_CNT BIT(28) /* Enables MASK31_HOST_CLK_CNT */ +#define SD_MEM_INTF_CLK_ENABLE \ + BIT(29) /* Static Clock gating Enable for sd_mem_intf clk1'b1 => Clock is enabled1'b0 => Invalid*/ +#define MASK_HOST_CLK_AVAILABLE_FIX BIT(30) /* Enables MASK_HOST_CLK_AVAILABLE_FIX */ +#define ULPSS_CLK_ENABLE BIT(31) /* Enables ULPSS_CLK_ENABLE */ + +/*SER Reg2 SET / CLR*/ +#define GEN_SPI_MST1_HCLK_ENABLE BIT(0) /* Enables GEN_SPI_MST1_HCLK_ENABLE */ +#define CAN1_PCLK_ENABLE BIT(2) /* Enables CAN1_PCLK_ENABLE */ +#define CAN1_CLK_ENABLE BIT(3) /* Enables CAN1_CLK_ENABLE */ +#define UDMA_HCLK_ENABLE BIT(6) /* Enables UDMA_HCLK_ENABLE */ +#define I2C_BUS_CLK_ENABLE BIT(7) /* Enables I2C_1_BUS_CLK_ENABLE */ +#define I2C_2_BUS_CLK_ENABLE BIT(8) /* Enables I2C_2_BUS_CLK_ENABLE */ +#define SSI_SLV_PCLK_ENABLE BIT(9) /* Enables SSI_SLV_PCLK_ENABLE */ +#define SSI_SLV_SCLK_ENABLE BIT(10) /* Enables SSI_SLV_SCLK_ENABLE */ +#define QSPI_CLK_ENABLE BIT(11) /* Enables QSPI_CLK_ENABLE */ +#define QSPI_HCLK_ENABLE BIT(12) /* Enables QSPI_HCLK_ENABLE */ +#define I2SM_SCLK_ENABLE BIT(13) /* Enables I2SM_SCLK_ENABLE */ +#define I2SM_INTF_SCLK_ENABLE BIT(14) /* Enables I2SM_INTF_SCLK_ENABLE */ +#define I2SM_PCLK_ENABLE BIT(15) /* Enables I2SM_PCLK_ENABLE */ +#define QE_PCLK_ENABLE BIT(17) /* Enables QE_PCLK_ENABLE */ +#define MCPWM_PCLK_ENABLE BIT(18) /* Enables MCPWM_PCLK_ENABLE */ +#define SGPIO_PCLK_ENABLE BIT(20) /* Enables SGPIO_PCLK_ENABLE */ +#define EGPIO_PCLK_ENABLE BIT(21) /* Enables EGPIO_PCLK_ENABLE */ +#define ARM_CLK_ENABLE BIT(22) /* Enables ARM_CLK_ENABLE */ +#define SSI_MST_PCLK_ENABLE BIT(23) /* Enables SSI_MST_PCLK_ENABLE */ +#define SSI_MST_SCLK_ENABLE BIT(24) /* Enables SSI_MST_SCLK_ENABLE */ +#define MEM2_CLK_ENABLE BIT(25) /* Enables MEM2_CLK_ENABLE */ +#define MEM_CLK_ULP_ENABLE BIT(26) /* Enables MEM_CLK_ULP_ENABLE */ +#define ROM_CLK_ENABLE BIT(27) /* Enables ROM_CLK_ENABLE */ +#define PLL_INTF_CLK_ENABLE BIT(28) /* Enables PLL_INTF_CLK_ENABLE */ +#define SEMAPHORE_CLK_ENABLE BIT(29) /* Enables SEMAPHORE_CLK_ENABLE */ +#define TOT_CLK_ENABLE BIT(30) /* Enables TOT_CLK_ENABLE */ +#define RMII_SOFT_RESET BIT(31) /* Enables RMII_SOFT_RESET */ + +/*SET Reg 3 SET / CLR*/ +#define BUS_CLK_ENABLE BIT(0) /* Enables BUS_CLK_ENABLE */ +#define M4_CORE_CLK_ENABLE BIT(1) /* Enables M4_CORE_CLK_ENABLE */ +#define CM_BUS_CLK_ENABLE BIT(2) /* Enables CM_BUS_CLK_ENABLE */ +#define MISC_CONFIG_PCLK_ENABLE BIT(4) /* Enables MISC_CONFIG_PCLK_ENABLE */ +#define EFUSE_CLK_ENABLE BIT(5) /* Enables EFUSE_CLK_ENABLE */ +#define ICM_CLK_ENABLE BIT(6) /* Enables ICM_CLK_ENABLE */ +#define MEM1_CLK_ENABLE BIT(7) /* Enables MEM1_CLK_ENABLE */ +#define MEM3_CLK_ENABLE BIT(8) /* Enables MEM3_CLK_ENABLE */ +#define USB_PHY_CLK_IN_ENABLE BIT(12) /* Enables USB_PHY_CLK_IN_ENABLE */ +#define QSPI_CLK_ONEHOT_ENABLE BIT(13) /* Enables QSPI_CLK_ONEHOT_ENABLE */ +#define QSPI_M4_SOC_SYNC BIT(14) /* Enables QSPI_M4_SOC_SYNC */ +#define EGPIO_CLK_ENABLE BIT(16) /* Enables EGPIO_CLK_ENABLE */ +#define I2C_CLK_ENABLE BIT(17) /* Enables I2C_CLK_ENABLE */ +#define I2C_2_CLK_ENABLE BIT(18) /* Enables I2C_2_CLK_ENABLE */ +#define EFUSE_PCLK_ENABLE BIT(19) /* Enables EFUSE_PCLK_ENABLE */ +#define SGPIO_CLK_ENABLE BIT(20) /* Enables SGPIO_CLK_ENABLE */ +#define TASS_M4SS_64K_SWITCH_CLK_ENABLE BIT(21) /* Enables TASS_M4SS_64K_SWITCH_CLK_ENABLE */ +#define TASS_M4SS_128K_SWITCH_CLK_ENABLE BIT(22) /* Enables TASS_M4SS_128K_SWITCH_CLK_ENABLE */ +#define TASS_M4SS_SDIO_SWITCH_CLK_ENABLE BIT(23) /* Enables TASS_M4SS_SDIO_SWITCH_CLK_ENABLE */ +#define TASS_M4SS_USB_SWITCH_CLK_ENABLE BIT(24) /* Enables TASS_M4SS_USB_SWITCH_CLK_ENABLE */ +#define ROM_MISC_STATIC_ENABLE BIT(25) /* Enables ROM_MISC_STATIC_ENABLE */ +#define M4_SOC_CLK_FOR_OTHER_ENABLE BIT(26) /* Enables M4_SOC_CLK_FOR_OTHER_ENABLE */ +#define ICACHE_ENABLE BIT(27) /* Enables ICACHE_ENABLE */ + +/*DYN_CLK_GATE_DISABLE_REG */ + +#define SDIO_SYS_HCLK_DYN_CTRL_DISABLE BIT(0) /* Enables SDIO_SYS_HCLK_DYN_CTRL_DISABLE */ +#define BUS_CLK_DYN_CTRL_DISABLE BIT(1) /* Enables BUS_CLK_DYN_CTRL_DISABLE */ +#define GPDMA_HCLK_DYN_CTRL_DISABLE BIT(4) /* Enables GPDMA_HCLK_DYN_CTRL_DISABLE */ +#define EGPIO_PCLK_DYN_CTRL_DISABLE BIT(5) /* Enables EGPIO_PCLK_DYN_CTRL_DISABLE */ +#define SGPIO_PCLK_DYN_CTRL_DISABLE BIT(6) /* Enables SGPIO_PCLK_DYN_CTRL_DISABLE */ +#define TOT_CLK_DYN_CTRL_DISABLE BIT(7) /* Enables TOT_CLK_DYN_CTRL_DISABLE */ +#define HWRNG_PCLK_DYN_CTRL_DISABLE BIT(8) /* Enables HWRNG_PCLK_DYN_CTRL_DISABLE */ +#define USART1_SCLK_DYN_CTRL_DISABLE BIT(9) /* Enables USART1_SCLK_DYN_CTRL_DISABLE */ +#define USART1_PCLK_DYN_CTRL_DISABLE BIT(10) /* Enables USART1_PCLK_DYN_CTRL_DISABLE */ +#define USART2_SCLK_DYN_CTRL_DISABLE BIT(11) /* Enables USART2_SCLK_DYN_CTRL_DISABLE */ +#define USART2_PCLK_DYN_CTRL_DISABLE BIT(12) /* Enables USART2_PCLK_DYN_CTRL_DISABLE */ +#define SSI_SLV_SCLK_DYN_CTRL_DISABLE BIT(15) /* Enables SSI_SLV_SCLK_DYN_CTRL_DISABLE */ +#define SSI_SLV_PCLK_DYN_CTRL_DISABLE BIT(16) /* Enables SSI_SLV_PCLK_DYN_CTRL_DISABLE */ +#define I2SM_INTF_SCLK_DYN_CTRL_DISABLE BIT(18) /* Enables I2SM_INTF_SCLK_DYN_CTRL_DISABLE */ +#define SEMAPHORE_CLK_DYN_CTRL_DISABLE BIT(19) /* Enables SEMAPHORE_CLK_DYN_CTRL_DISABLE */ +#define ARM_CLK_DYN_CTRL_DISABLE BIT(20) /* Enables ARM_CLK_DYN_CTRL_DISABLE */ +#define SSI_MST_SCLK_DYN_CTRL_DISABLE BIT(21) /* Enables SSI_MST_SCLK_DYN_CTRL_DISABLE */ +#define MEM1_CLK_DYN_CTRL_DISABLE BIT(22) /* Enables MEM1_CLK_DYN_CTRL_DISABLE */ +#define MEM2_CLK_DYN_CTRL_DISABLE BIT(23) /* Enables MEM2_CLK_DYN_CTRL_DISABLE */ +#define MEM_CLK_ULP_DYN_CTRL_DISABLE BIT(24) /* Enables MEM_CLK_ULP_DYN_CTRL_DISABLE */ +#define MEM3_CLK_DYN_CTRL_DISABLE BIT(25) /* Enables MEM3_CLK_DYN_CTRL_DISABLE */ +#define SSI_MST_PCLK_DYN_CTRL_DISABLE BIT(28) /* Enables SSI_MST_PCLK_DYN_CTRL_DISABLE */ +#define ICACHE_DYN_GATING_DISABLE BIT(29) /* Enables ICACHE_DYN_GATING_DISABLE */ +#define CCI_PCLK_DYN_CTRL_DISABLE BIT(30) /* Enables CCI_PCLK_DYN_CTRL_DISABLE */ +#define MISC_CONFIG_PCLK_DYN_CTRL_DISABLE BIT(31) /* Enables MISC_CONFIG_PCLK_DYN_CTRL_DISABLE */ + +/*DYN_CLK_GATE_DISABLE_REG2 */ +#define SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE BIT(0) /* Enables SOC_PLL_SPI_CLK_DYN_CTRL_DISABLE */ +#define I2C_BUS_DYN_CTRL_DISABLE BIT(1) /* Enables I2C_BUS_DYN_CTRL_DISABLE */ +#define I2C_2_BUS_CLK_DYN_CTRL_DISABLE BIT(2) /* Enables I2C_2_BUS_CLK_DYN_CTRL_DISABLE */ +#define CT_PCLK_DYN_CTRL_DISABLE BIT(3) /* Enables SCT_PCLK_DYN_CTRL_DISABLE */ +#define CAN1_PCLK_DYN_CTRL_DISABLE BIT(4) /* Enables CAN1_PCLK_DYN_CTRL_DISABLE */ +#define I2SM_PCLK_DYN_CTRL_DISABLE BIT(5) /* Enables I2SM_PCLK_DYN_CTRL_DISABLE */ +#define EFUSE_CLK_DYN_CTRL_DISABLE BIT(6) /* Enables EFUSE_CLK_DYN_CTRL_DISABLE */ +#define EFUSE_PCLK_DYN_CTRL_DISABLE BIT(7) /* Enables EFUSE_PCLK_DYN_CTRL_DISABLE */ +#define PWR_CTRL_CLK_DYN_CTRL_DISABLE BIT(8) /* Enables PWR_CTRL_CLK_DYN_CTRL_DISABLE */ + +/*SOC_Pll Clock frequency checks */ +#define SOC_PLL_MIN_FREQUECY 1000000 /* Minimum frequency for SOC_PLL*/ +#define SOC_PLL_MAX_FREQUECY 300000000 /* Maximum frequency for SOC_PLL*/ + +/*SOC_Pll Clock frequency checks */ +#define INTF_PLL_MIN_FREQUECY 1000000 /* Minimum frequency for SOC_PLL*/ +#define INTF_PLL_MAX_FREQUECY 300000000 /* Maximum frequency for SOC_PLL*/ + +#define I2S_DCO_FREQ1 73728000 /* i2s_dco_freq1*/ +#define I2S_DCO_FREQ2 67737600 /* i2s_dco_freq2*/ + +/*SOCPLL_MACRO_REG_ACCESS*/ +#define SOCPLLMACROREG1 0x00 /* Address for SOCPLLMACROREG1 register Access*/ +#define SOCPLLMACROREG2 0x01 /* Address for SOCPLLMACROREG2 register Access*/ +#define SOCPLLMACROREG3 0x02 /* Address for SOCPLLMACROREG3 register Access*/ +#define SOCPLLMACROREG4 0x03 /* Address for SOCPLLMACROREG4 register Access*/ +#define SOCPLLMACROREG5 0x04 /* Address for SOCPLLMACROREG5 register Access*/ + +/*SOCPLLMACROREG*/ +#define LDO_PROG_SOCPLL (0xE000) /* Mask value for LDO_PROG_SOCPLL*/ +#define LDO_PROG_INTFPLL (0x1C00) /* Mask value for LDO_PROG_INTFPLL*/ +#define LDO_PROG_I2SPLL (0x0380) /* Mask value for LDO_PROG_I2SPLL*/ + +/* SOC_PLL_REG_ACCESS */ +#define SOC_PLL_500_CTRL_REG1 0x10 /* Address for SOC_PLL_500_CTRL_REG1 register Access*/ +#define SOC_PLL_500_CTRL_REG2 0x11 /* Address for SOC_PLL_500_CTRL_REG2 register Access*/ +#define SOC_PLL_500_CTRL_REG3 0x12 /* Address for SOC_PLL_500_CTRL_REG3 register Access*/ +#define SOC_PLL_500_CTRL_REG4 0x13 /* Address for SOC_PLL_500_CTRL_REG4 register Access*/ +#define SOC_PLL_500_CTRL_REG5 0x14 /* Address for SOC_PLL_500_CTRL_REG5 register Access*/ +#define SOC_PLL_500_CTRL_REG6 0x15 /* Address for SOC_PLL_500_CTRL_REG6 register Access*/ +#define SOC_PLL_500_CTRL_REG7 0x16 /* Address for SOC_PLL_500_CTRL_REG7 register Access*/ +#define SOC_PLL_500_CTRL_REG8 0x17 /* Address for SOC_PLL_500_CTRL_REG8 register Access*/ +#define SOC_PLL_500_CTRL_REG9 0x18 /* Address for SOC_PLL_500_CTRL_REG9 register Access*/ +#define SOC_PLL_500_CTRL_REG10 0x19 /* Address for SOC_PLL_500_CTRL_REG10 register Access*/ +#define SOC_PLL_500_CTRL_REG11 0x1A /* Address for SOC_PLL_500_CTRL_REG11 register Access*/ +#define SOC_PLL_500_CTRL_REG12 0x1B /* Address for SOC_PLL_500_CTRL_REG12 register Access*/ +#define SOC_PLL_500_CTRL_REG13 0x1C /* Address for SOC_PLL_500_CTRL_REG13 register Access*/ + +/* INTF_PLL_REG_ACCESS */ +#define INTF_PLL_500_CTRL_REG1 0x20 /* Address for INTF_PLL_500_CTRL_REG1 register Access*/ +#define INTF_PLL_500_CTRL_REG2 0x21 /* Address for INTF_PLL_500_CTRL_REG2 register Access*/ +#define INTF_PLL_500_CTRL_REG3 0x22 /* Address for INTF_PLL_500_CTRL_REG3 register Access*/ +#define INTF_PLL_500_CTRL_REG4 0x23 /* Address for INTF_PLL_500_CTRL_REG4 register Access*/ +#define INTF_PLL_500_CTRL_REG5 0x24 /* Address for INTF_PLL_500_CTRL_REG5 register Access*/ +#define INTF_PLL_500_CTRL_REG6 0x25 /* Address for INTF_PLL_500_CTRL_REG6 register Access*/ +#define INTF_PLL_500_CTRL_REG7 0x26 /* Address for INTF_PLL_500_CTRL_REG7 register Access*/ +#define INTF_PLL_500_CTRL_REG8 0x27 /* Address for INTF_PLL_500_CTRL_REG8 register Access*/ +#define INTF_PLL_500_CTRL_REG9 0x28 /* Address for INTF_PLL_500_CTRL_REG9 register Access*/ +#define INTF_PLL_500_CTRL_REG10 0x29 /* Address for INTF_PLL_500_CTRL_REG10 register Access*/ +#define INTF_PLL_500_CTRL_REG11 0x2A /* Address for INTF_PLL_500_CTRL_REG11 register Access*/ +#define INTF_PLL_500_CTRL_REG12 0x2B /* Address for INTF_PLL_500_CTRL_REG12 register Access*/ +#define INTF_PLL_500_CTRL_REG13 0x2C /* Address for INTF_PLL_500_CTRL_REG13 register Access*/ + +/* I2S_PLL_REG_ACCESS */ +#define I2S_PLL_CTRL_REG1 0x30 /* Address for I2S_PLL_CTRL_REG1 register Access*/ +#define I2S_PLL_CTRL_REG2 0x31 /* Address for I2S_PLL_CTRL_REG2 register Access*/ +#define I2S_PLL_CTRL_REG3 0x32 /* Address for I2S_PLL_CTRL_REG3 register Access*/ +#define I2S_PLL_CTRL_REG4 0x33 /* Address for I2S_PLL_CTRL_REG4 register Access*/ +#define I2S_PLL_CTRL_REG5 0x34 /* Address for I2S_PLL_CTRL_REG5 register Access*/ +#define I2S_PLL_CTRL_REG6 0x35 /* Address for I2S_PLL_CTRL_REG6 register Access*/ +#define I2S_PLL_CTRL_REG7 0x36 /* Address for I2S_PLL_CTRL_REG7 register Access*/ +#define I2S_PLL_CTRL_REG8 0x37 /* Address for I2S_PLL_CTRL_REG8 register Access*/ +#define I2S_PLL_CTRL_REG9 0x38 /* Address for I2S_PLL_CTRL_REG9 register Access*/ +#define I2S_PLL_CTRL_REG10 0x39 /* Address for I2S_PLL_CTRL_REG10 register Access*/ +#define I2S_PLL_CTRL_REG11 0x3A /* Address for I2S_PLL_CTRL_REG11 register Access*/ +#define I2S_PLL_CTRL_REG12 0x3B /* Address for I2S_PLL_CTRL_REG12 register Access*/ +#define I2S_PLL_CTRL_REG13 0x3C /* Address for I2S_PLL_CTRL_REG13 register Access*/ + +/* AFE_PLL_CTRL_REG_REG_ACCESS */ +#define AFEPLLCTRLREG1 0x07 /* Address for AFEPLLCTRLREG1 register Access*/ +#define AFEPLLCTRLREG2 0x08 /* Address for AFEPLLCTRLREG1 register Access*/ + +#define MEMS_REF_CLK_ENABLE BIT(6) + +/*SOC_PLL_500_CTRL_REG1/INTF_PLL_500_CTRL_REG1/I2S_PLL_CTRL_REG_1 */ +#define DCO_FIX_SEL_MASK (0x0003) /* Mask value for DCO_FIX_SEL_MASK*/ +#define PLL_500_BYPASS BIT(2) /* Enables PLL_500_BYPASS */ +#define PLL_500_CLK_ENABLE BIT(3) /* Enables PLL_500_CLK_ENABLE */ +#define PLL_500_PD BIT(4) /* Enables PLL_500_PD */ +#define PLL_500_RST BIT(5) /* Enables PLL_500_RST */ +#define PLL_500_M_MASK (0xFFC0) /* Mask value for PLL_500_M_MASK*/ +/*I2S_PLL_CTRL_REG_1*/ +#define I2S_PLL_CLK_ENABLE BIT(2) /* Enables I2S_PLL_CLK_ENABLE */ +#define I2S_PLL_BYPASS BIT(3) /* Enables I2S_PLL_BYPASS */ + +/*SOC_PLL_500_CTRL_REG2/INTF_PLL_500_CTRL_REG 2 */ +#define PLL_500_N_MASK (0x01F8) /* Mask value for PLL_500_N_MASK*/ +#define PLL_500_P_MASK (0xFE00) /* Mask value for PLL_500_P_MASK*/ + +/*I2S_PLL_CTRL_REG_2*/ +#define N_DIV_MASK (0x00FE) /* Mask value for N_DIV_MASK*/ +#define P_DIV2_MASK (0x0700) /* Mask value for P_DIV2_MASK*/ +#define P_DIV1_MASK (0xF800) /* Mask value for P_DIV1_MASK*/ + +/*SOC_PLL_500_CTRL_REG3/INTF_PLL_500_CTRL_REG_3/ I2S_PLL_CTRL_REG_3 */ +#define FCW_F_MASK (0xFFFC) /* Mask value for FCW_F_MASK*/ + +/*SOC_PLL_500_CTRL_REG_4/INTF_PLL_500_CTRL_REG_4 */ +#define LDO_BY_PASS BIT(1) /* Enables LDO_BY_PASS */ +#define SD_CLK_SEL_MASK (0x000C) /* Mask value for SD_CLK_SEL_MASK*/ +#define SD_LEN BIT(4) /* Enables SD_LEN */ +#define FILTER_TYPE BIT(5) /* Enables FILTER_TYPE */ +#define BETA_MASK (0x07C0) /* Mask value for BETA_MASK*/ +#define ALPHA_MASK (0xF800) /* Mask value for ALPHA_MASK*/ +/*SOC_PLL_500_CTRL_REG_5/INTF_PLL_500_CTRL_REG_5/ I2S_PLL_CTRL_REG_5 */ +#define LOCK_LIMIT_MASK (0x3FFF) /* Mask value for LOCK_LIMIT_MASK*/ +#define ENABLE_PHASE_LOCK_DETECT BIT(14) /* Enables ENABLE_PHASE_LOCK_DETECT */ +#define ENABLE_FREQ_LOCK_DETECT BIT(15) /* Enables ENABLE_FREQ_LOCK_DETECT */ +/*SOC_PLL_500_CTRL_REG_6/INTF_PLL_500_CTRL_REG_6/ I2S_PLL_CTRL_REG_6 */ +#define RETIMER_COUNT_MASK (0x00F0) /* Mask value for RETIMER_COUNT_MASK*/ +#define TDC_PWRSAV_COUNT_MASK (0x7F00) /* Mask value for TDC_PWRSAV_COUNT_MASK*/ +#define TDC_PWRSAV_EN BIT(15) /* Enables TDC_PWRSAV_EN */ + +/*SOC_PLL_500_CTRL_REG_7/INTF_PLL_500_CTRL_REG_7/ I2S_PLL_CTRL_REG_7*/ +#define SPI_INP_RD_EN BIT(4) /* Enables SPI_INP_RD_EN */ +#define OCW_MANUAL_MASK (0xFFE0) /* Mask value for OCW_MANUAL_MASK */ +#define DCO_TESTMODE BIT(15) /* Enables DCO_TESTMODE */ + +/*SOC_PLL_500_CTRL_REG_8/INTF_PLL_500_CTRL_REG_8/I2S_PLL_CTRL_REG_8 */ +#define ISOLATION_ENABLE BIT(0) /* Enables ISOLATION_ENABLE */ +#define BYPASS_ISO_GEN BIT(1) /* Enables BYPASS_ISO_GEN */ +#define BYPASS_LOCK_FLAG BIT(2) /* Enables BYPASS_LOCK_FLAG */ +#define BYPASS_PWR_GOOD BIT(3) /* Enables BYPASS_PWR_GOOD */ +#define LOCK_COUNT_LIMIT_FREQ_MASK (0x00F0) /* Mask value for LOCK_COUNT_LIMIT_FREQ_MASK */ +#define LOCK_COUNT_LIMIT_PHASE_MASK (0xFF00) /* Mask value for LOCK_COUNT_LIMIT_PHASE_MASK*/ + +/*SOC_PLL_500_CTRL_REG_9/INTF_PLL_500_CTRL_REG_9/ I2S_PLL_CTRL_REG_9 */ +#define MM_COUNT_LIMIT_MASK (0x3FC0) /* Mask value for MM_COUNT_LIMIT_MASK */ +#define BYPASS_LOCK_PLL BIT(14) /* Enables BYPASS_LOCK_PLL */ +#define MANUAL_LOCK_ENABLE BIT(15) /* Enables MANUAL_LOCK_ENABLE */ + +/*SOC_PLL_500_CTRL_REG_10/INTF_PLL_500_CTRL_REG_10/ I2S_PLL_CTRL_REG_10 */ +#define CKR_TEST_EN BIT(3) /* Enables CKR_TEST_EN */ +#define SELOUT_SA_RETIMER BIT(4) /* Enables SELOUT_SA_RETIMER */ +#define EN_STD_RETIMER BIT(5) /* Enables EN_STD_RETIMER */ +#define EN_SA_RETIMER BIT(6) /* Enables EN_SA_RETIMER */ +#define RETIMER_PWRSAV_COUNT2_MASK (0x0780) /* Mask value for RETIMER_PWRSAV_COUNT2_MASK */ +#define RETIMER_PWRSAV_COUNT1_MASK (0x7800) /* Mask value for RETIMER_PWRSAV_COUNT1_MASK */ +#define RETIMER_PWRSAV_EN BIT(15) /* Enables RETIMER_PWRSAV_EN */ + +/*SOC_PLL_500_CTRL_REG_11/INTF_PLL_500_CTRL_REG_11/ I2S_PLL_CTRL_REG_11 */ +#define PU_SD_DIV BIT(1) /* Enables PU_SD_DIV */ +#define PU_POST_DIV BIT(2) /* Enables PU_POST_DIV */ +#define PU_INP_DIV BIT(3) /* Enables PU_INP_DIV */ +#define PU_INDO BIT(4) /* Enables PU_INDO */ +#define PU_RETIMER BIT(5) /* Enables PU_RETIMER */ +#define PU_TDC BIT(6) /* Enables PU_TDC */ +#define PU_DCO BIT(7) /* Enables PU_DCO */ +#define PU_DIGITAL_TOP BIT(8) /* Enables PU_DIGITAL_TOP */ +#define RESETN_SD_DIV BIT(9) /* Enables RESETN_SD_DIV */ +#define RESETN_INP_DIV BIT(10) /* Enables RESETN_INP_DIV */ +#define RESETN_POST_DIV BIT(11) /* Enables RESETN_POST_DIV */ +#define RESETN_RETIMER BIT(12) /* Enables RESETN_RETIMER */ +#define RESETN_LOCK_DETECT BIT(13) /* Enables RESETN_LOCK_DETECT */ +#define RESETN_LOOP BIT(14) /* Enables RESETN_LOOP */ +#define RESETN_TDC BIT(15) /* Enables RESETN_TDC */ + +/*SOC_PLL_500_CTRL_REG_12/INTF_PLL_500_CTRL_REG_12/ I2S_PLL_CTRL_REG_12 */ +#define DELTF_MASK (0x003E) /* Mask value for DELTF_MASK */ +#define DELTR_MASK (0x07C0) /* Mask value for DELTR_MASK */ +#define TV_MASK (0XF800) /* Mask value for TV_MASK */ + +/*SOC_PLL_500_CTRL_REG_13/INTF_PLL_500_CTRL_REG_13/ I2S_PLL_CTRL_REG_13*/ +#define OCW_MASK (0x3FF0) /* Mask value for OCW_MASK */ +#define LOCK_FLAG_PHASE BIT(14) /* Enables LOCK_FLAG_PHASE */ +#define LOCK_FLAG_FREQ BIT(15) /* Enables LOCK_FLAG_FREQ */ + +/*SOC Clock division factor checks */ +#define SOC_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for SOC clock*/ +#define SOC_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SOC clock*/ + +/*SDMEM Clock division factor checks */ +#define SDMEM_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for SD_MEM clock*/ +#define SDMEM_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SD_MEM clock*/ + +/*CT Clock division factor checks */ +#define CT_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for CT clock*/ +#define CT_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CT clock*/ + +/*I2S Clock division factor checks */ +#define I2S_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for I2S clock*/ +#define I2S_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for I2S clock*/ + +/*USB Clock division factor checks */ +#define USB_MAX_CLK_DIVISION_FACTOR 3 /* Maximum division factor value for USB clock*/ +#define USB_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for USB clock*/ + +/*CAN Clock division factor checks */ +#define CAN_MAX_CLK_DIVISION_FACTOR 255 /* Maximum division factor value for CAN clock*/ +#define CAN_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CAN clock*/ + +/*I2S Clock division factor checks */ +#define MCU_CLKOUT_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for MCU_CLKOUT clock*/ +#define MCU_CLKOUT_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for MCU_CLKOUT clock*/ +#define MCU_CLKOUT_SEL_MAX 15 /* Maximum Seletion value for MCU_CLKOUT clock source*/ + +/*QSPI Clock Division factor checks */ +#define QSPI_MAX_CLK_DIVISION_FACTOR 63 /* Maximum division factor value for QSPI clock*/ +#define QSPI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for QSPI clock*/ + +/*USART Clock Division factor checks */ +#define USART_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for USART clock*/ +#define USART_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for USART clock*/ + +/*SSI Clock Division factor checks */ +#define SSI_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for SSI clock*/ +#define SSI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for SSI clock*/ + +/*CCI Clock Division factor checks */ +#define CCI_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for CCI clock*/ +#define CCI_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for CCI clock*/ + +/*PLL_INTF Clock Division factor checks */ +#define PLL_INTF_MAX_CLK_DIVISION_FACTOR 15 /* Maximum division factor value for PLL_INTF clock*/ +#define PLL_INTF_MIN_CLK_DIVISION_FACTOR 0 /* Minimum division factor value for PLL_INTF clock*/ + +/*Sleep Clock selection checks */ +#define SLP_MAX_SEL 3 /* Maximum Seletion value for Sleep clock source*/ +#define SLP_MIN_SEL 0 /* Minimum Seletion value for Sleep clock source*/ + +#define MAX_SLP_CYCLES 3 /* Maximum Cycles for Sleep clock*/ +#define MIN_SLP_CYCLES 0 /* Minimum Cycles for Sleep clock*/ + +#define MISC_CFG_MISC_CTRL1 (*((uint32_t volatile *)(MISC_CONFIG_BASE + 0x44))) /* address of MISC_CFG_MISC_CTRL1 */ +#define I2S_MASTER_SLAVE_MODE (1 << 23) /* Sets I2S/I2S PCM master mode */ + +#define MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 40MHZ CLK*/ +#define MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP DOUBLER CLK*/ +#define MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 20MHZ_RING_OSC CLK*/ +#define MCU_ULP_MHZ_RC_CLK_EN_TRUN_ON_DELAY 2 /* delay to enable the ULP MHZ_RC CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1 500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2 1500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY 250 /* delay to enable the ULP 32KHZ_RO CLK*/ +#define MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY 150 /* delay to enable the ULP 32KHZ_RC CLK*/ + +/** + *@brief Reference clock selection + **/ +typedef enum REF_CLK_ENABLE { + MCU_ULP_40MHZ_CLK_EN, /*!< Enables ULP_40MHZ_CLK when it is passed */ + MCU_ULP_DOUBLER_CLK_EN, /*!< Enables ULP_DOUBLER_CLK when it is passed */ + MCU_ULP_20MHZ_RING_OSC_CLK_EN, /*!< Enables ULP_20MHZ_RING_OSC_CLK when it is passed */ + MCU_ULP_MHZ_RC_CLK_EN, /*!< Enables ULP_MHZ_RC_CLK when it is passed */ + MCU_ULP_32KHZ_XTAL_CLK_EN, /*!< Enables ULP_32KHZ_XTAL_CLK when it is passed */ + MCU_ULP_32KHZ_RO_CLK_EN, /*!< Enables ULP_32KHZ_RO_CLK when it is passed */ + MCU_ULP_32KHZ_RC_CLK_EN /*!< Enables ULP_32KHZ_RC_CLK when it is passed */ +} REF_CLK_ENABLE_T; +/** + *@brief list of peripherals, particular clock that to be enabled + **/ +typedef enum PERIPHERALS_CLK { + USART1_CLK, /*!< Enables or Disables USART1 Peripheral clock when it is passed */ + USART2_CLK, /*!< Enables or Disables USART2 Master Peripheral clock when it is passed */ + SSIMST_CLK, /*!< Enables or Disables SSI Master Peripheral clock when it is passed */ + SSISLAVE_CLK, /*!< Enables or Disables SSI Slave Peripheral clock when it is passed */ + CT_CLK, /*!< Enables or Disables CT Peripheral clock when it is passed */ + SD_MEM_CLK, /*!< Enables or Disables SD_MEM Peripheral clock when it is passed */ + CCI_CLK, /*!< Enables or Disables CCI Peripheral clock when it is passed */ + QSPI_CLK, /*!< Enables or Disables QSPI Peripheral clock when it is passed */ + RPDMA_CLK, /*!< Enables or Disables RPDMA Peripheral clock when it is passed */ + UDMA_CLK, /*!< Enables or Disables UDMA Peripheral clock when it is passed */ + PWM_CLK, /*!< Enables or Disables PWM Peripheral clock when it is passed */ + CAN_CLK, /*!< Enables or Disables CAN Peripheral clock when it is passed */ + GSPI_CLK, /*!< Enables or Disables GSPI Peripheral clock when it is passed */ + EGPIO_CLK, /*!< Enables or Disables EGPIO Peripheral clock when it is passed */ + ETHERNET_CLK, /*!< Enables or Disables ETHERNET Peripheral clock when it is passed */ + MCUCLKOUT_CLK, /*!< Enables or Disables MCUCLKOUT Peripheral clock when it is passed */ + HWRNG_CLK, /*!< Enables or Disables HWRNG Peripheral clock when it is passed */ + I2SM_CLK, /*!< Enables or Disables I2SM Peripheral clock when it is passed */ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + QSPI_2_CLK, /*!< Enables or Disables QSPI 2 Peripheral clock when it is passed */ +#endif +} PERIPHERALS_CLK_T; + +/** + *@brief PLL selection types + **/ +typedef enum PLL_TYPE { + SOC_PLL, /*!Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_POWER_SAVE_H__ +#define __RSI_POWER_SAVE_H__ + +#include "rsi_error.h" +#include "base_types.h" +#include "rsi_ccp_common.h" +#include "rsi_reg_spi.h" +#include "rsi_ipmu.h" +#include "rsi_system_config.h" +#include "rsi_ccp_user_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*M4SS peripheral power gates */ +/* M4SS_PWRCTRL_SET_REG Bits ((NPSS MCU(MCU DM POWER CTRL FF's Domain))*/ +#define M4SS_PWRGATE_ULP_EXT_ROM BIT(22) +#define M4SS_PWRGATE_ULP_M4_CORE BIT(18) +#define M4SS_PWRGATE_ULP_IID BIT(14) +#define M4SS_PWRGATE_ULP_SDIO_SPI BIT(11) +#define M4SS_PWRGATE_ULP_RPDMA BIT(9) +#if defined(SLI_SI917) || defined(SLI_SI915) +#define M4SS_PWRGATE_ULP_EFUSE_PERI BIT(4) +#define M4SS_PWRGATE_ULP_QSPI_ICACHE BIT(13) +#define M4SS_PWRGATE_ULP_M4_DEBUG_FPU BIT(17) +#else +#define M4SS_PWRGATE_ULP_EFUSE BIT(4) +#define M4SS_PWRGATE_ULP_QSPI BIT(13) +#define M4SS_PWRGATE_ULP_M4_DEBUG BIT(17) +#endif +#if defined(CHIP_9118) +#define M4SS_PWRGATE_ULP_M4_FPU BIT(16) +#define M4SS_PWRGATE_ULP_ICACHE BIT(15) +#define M4SS_PWRGATE_ULP_ETHERNET BIT(12) +#define M4SS_PWRGATE_ULP_USB BIT(10) +#define M4SS_PWRGATE_ULP_PERI1 BIT(8) +#define M4SS_PWRGATE_ULP_PERI2 BIT(7) +#define M4SS_PWRGATE_ULP_PERI3 BIT(6) +#define M4SS_PWRGATE_ULP_CCI BIT(5) +#define M4SS_PWRGATE_ULP_SD_MEM BIT(2) +#endif + +/*ULPSS Peripheral power gate */ +/* ULPSS_PWRCTRL_SET_REG bits (NPSS MCU(MCU DM POWER CTRL FF's Domain))*/ +#define ULPSS_PWRGATE_ULP_MISC BIT(18) +#define ULPSS_PWRGATE_ULP_CAP BIT(19) +#if defined(CHIP_9118) +#define ULPSS_PWRGATE_ULP_VAD BIT(20) +#endif +#define ULPSS_PWRGATE_ULP_UART BIT(21) +#define ULPSS_PWRGATE_ULP_SSI BIT(22) +#define ULPSS_PWRGATE_ULP_I2S BIT(23) +#define ULPSS_PWRGATE_ULP_I2C BIT(24) +#define ULPSS_PWRGATE_ULP_AUX BIT(25) +#define ULPSS_PWRGATE_ULP_IR BIT(26) +#define ULPSS_PWRGATE_ULP_UDMA BIT(27) +#define ULPSS_PWRGATE_ULP_FIM BIT(28) + +/*NPSS Peripheral power gates */ +/*MCUAON_NPSS_PWRCTRL_SET_REG Bits (MCU AON Domain)*/ +#define SLPSS_PWRGATE_ULP_NWPAPB_MCU_CTRL BIT(16) +#define SLPSS_PWRGATE_ULP_TIMEPERIOD BIT(10) +#define SLPSS_PWRGATE_ULP_MCUSTORE3 BIT(9) +#define SLPSS_PWRGATE_ULP_MCUSTORE2 BIT(8) +#define SLPSS_PWRGATE_ULP_MCUSTORE1 BIT(7) +#define SLPSS_PWRGATE_ULP_MCUTS BIT(6) +#define SLPSS_PWRGATE_ULP_MCUPS BIT(5) +#define SLPSS_PWRGATE_ULP_MCUWDT BIT(4) +#define SLPSS_PWRGATE_ULP_MCURTC BIT(3) +#define SLPSS_PWRGATE_ULP_MCUFSM BIT(2) +#define SLPSS_PWRGATE_ULP_MCUBFFS BIT(1) + +/*Power supply controls*/ +/*MCU_FSM_CRTL_PDM_AND_ENABLES_b(0x24) Reg Bits (MCU FSM )*/ +#define ENABLE_WDT_IN_SLEEP BIT(0) +#define ENABLE_WURX_DETECTION BIT(1) +#define RESET_MCU_BBF_DM_EN BIT(2) +#define DISABLE_TURNOFF_SRAM_PERI BIT(3) +#define ENABLE_SRAM_DS_CTRL BIT(4) +#define POWER_ENABLE_FSM_PERI BIT(16) +#define POWER_ENABLE_TIMESTAMPING BIT(17) +#define POWER_ENABLE_DEEPSLEEP_TIMER BIT(18) +#define POWER_ENABLE_RETENTION_DM BIT(19) + +/*Wake up sources configuration*/ +/*MCU_FSM_CRTL_PDM_AND_ENABLES_b(0x24) Reg Bits (MCU FSM )*/ +#define WDT_INTR_BASED_WAKEUP BIT(29) +#define MSEC_BASED_WAKEUP BIT(28) +#define SEC_BASED_WAKEUP BIT(27) +#define ALARM_BASED_WAKEUP BIT(26) +#define SDCSS_BASED_WAKEUP BIT(25) +#define ULPSS_BASED_WAKEUP BIT(24) +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) +#define WAKEIF_BASED_WAKEUP BIT(22) +#else +#define SYSRTC_BASED_WAKEUP BIT(22) +#endif +#define COMPR_BASED_WAKEUP BIT(21) +#define GPIO_BASED_WAKEUP BIT(20) +#define M4_PROCS_BASED_WAKEUP BIT(19) +#define WIRELESS_BASED_WAKEUP BIT(18) +#define HOST_BASED_WAKEUP BIT(17) +#define DST_BASED_WAKEUP BIT(16) +#define WIC_BASED_WAKEUP BIT(23) + +/*RAM retention controls */ +/*MCU FSM SLEEP CTRLS AND WAKEUP MODE Reg(0x0) (MCU FSM)*/ +#define M4ULP_RAM16K_RETENTION_MODE_EN BIT(7) +#define ULPSS_RAM_RETENTION_MODE_EN BIT(6) +#define TA_RAM_RETENTION_MODE_EN BIT(5) +#define M4ULP_RAM_RETENTION_MODE_EN BIT(4) +#define M4SS_RAM_RETENTION_MODE_EN BIT(3) /* reserved in 917 */ +#define HPSRAM_RET_ULP_MODE_EN BIT(2) + +/*RAM banks power gate controls*/ +/* M4_SRAM_PWRCTRL_SET_REG1 reg bits((NPSS MCU(MCU DM POWER CTRL FF's Domain)) */ +#if defined(CHIP_9118) +/*These banks typically used in M4SS high power mode */ +#define RAM_BANK_0 BIT(0) /*!< RAM BANK 0 SIZE : 16K*/ +#define RAM_BANK_1 BIT(1) /*!< RAM BANK 1 SIZE : 32K*/ +#define RAM_BANK_2 BIT(2) /*!< RAM BANK 2 SIZE : 16K*/ +/*Typically used in M4 ULP mode*/ +/*m4ulp_ram16k_retention_mode_en*/ +#define RAM_BANK_3 BIT(3) /*!< RAM BANK 3 SIZE : 4K*/ +#define RAM_BANK_4 BIT(4) /*!< RAM BANK 4 SIZE : 4K*/ +#define RAM_BANK_5 BIT(5) /*!< RAM BANK 4 SIZE : 4K*/ +#define RAM_BANK_6 BIT(6) /*!< RAM BANK 4 SIZE : 4K*/ +#define RAM_BANK_7 BIT(7) /*!< RAM BANK 4 SIZE : 32K*/ +#define RAM_BANK_8 BIT(8) /*!< RAM BANK 4 SIZE : 64K*/ +#define RAM_BANK_9 BIT(9) /*!< RAM BANK 4 SIZE : 16K*/ +/*typically these banks are used in TASS */ +#define RAM_BANK_10 BIT(16) /*!< RAM BANK 4 SIZE : 16K*/ +#define RAM_BANK_11 BIT(17) /*!< RAM BANK 4 SIZE : 32K*/ +#define RAM_BANK_12 BIT(18) /*!< RAM BANK 4 SIZE : 80K*/ +#define RAM_BANK_13 BIT(19) /*!< RAM BANK 4 SIZE : 64K*/ +#else +/*These banks typically used in M4SS high power mode */ +#define RAM_BANK_0 BIT(0) /*!< 4KB (Bank1 of first 192k chunk)*/ +#define RAM_BANK_1 BIT(1) /*!< 4KB (Bank2 of first 192k chunk)*/ +#define RAM_BANK_2 BIT(2) /*!< 4KB (Bank3 of first 192k chunk)*/ +#define RAM_BANK_3 BIT(3) /*!< 4KB (Bank4 of first 192k chunk)*/ +#define RAM_BANK_4 BIT(4) /*!< 16KB (Bank 5 of first 192k chunk)*/ +#define RAM_BANK_5 BIT(5) /*!< 32KB (Bank 6-7 of first 192k chunk*/ +#define RAM_BANK_6 BIT(6) /*!< 64KB (Bank 8-11 of first 192k chunk)*/ +#define RAM_BANK_7 BIT(7) /*!< 64KB (Bank 12-15 of first 192k chunk)*/ +#define RAM_BANK_8 BIT(8) /*!< 64KB (Bank 1-4 of second 64k chunk)*/ +#define RAM_BANK_9 BIT(9) /*!< 64KB (Bank 1-4 of third 64k chunk)*/ +#endif + +/*ULPSS RAM banks power gates */ +/*ULPSS _RAM_PWRCTRL_SET_REG1 bits (NPSS MCU(MCU DM POWER CTRL FF's Domain)*/ +#define ULPSS_2K_BANK_0 BIT(0) +#define ULPSS_2K_BANK_1 BIT(1) +#define ULPSS_2K_BANK_2 BIT(2) +#define ULPSS_2K_BANK_3 BIT(3) +#if defined(CHIP_9118) +#define ULPSS_2K_BANK_4 BIT(4) +#define ULPSS_2K_BANK_5 BIT(5) +#define ULPSS_2K_BANK_6 BIT(6) +#define ULPSS_2K_BANK_7 BIT(7) +#endif + +/*Controls the PMU off delay time*/ +#define PMU_LDO_OFF_DELAY 31U + +/*LP control reg */ +#define M4LP_CTRL_REG *((volatile uint32_t *)(0x24041424)) +#define ULP_M4_CORE_CLK_ENABLE BIT(2) + +/*NPSS INTERRUPT */ +#ifndef NPSS_INTR_BASE +#define NPSS_INTR_BASE 0x12080000 +#endif // NPSS_INTR_BASE +#ifndef NPSS_INTR_MASK_SET_REG +#define NPSS_INTR_MASK_SET_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x00)) +#endif // NPSS_INTR_MASK_SET_REG +#ifndef NPSS_INTR_MASK_CLR_REG +#define NPSS_INTR_MASK_CLR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x04)) +#endif // NPSS_INTR_MASK_CLR_REG +#ifndef NPSS_INTR_CLEAR_REG +#define NPSS_INTR_CLEAR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x08)) +#endif // NPSS_INTR_CLEAR_REG +#ifndef NPSS_INTR_STATUS_REG +#define NPSS_INTR_STATUS_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x0C)) +#endif // NPSS_INTR_STATUS_REG +#define M4_ULP_SLP_STATUS_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x1C)) +#define MCU_ULP_WAKEUP BIT(0) /* To check whether it is first boot up or Wake up */ +#define NWPAON_POR_CTRL_BITS *(volatile uint32_t *)(0x41300000 + 0x3C) +#define POC_CNTRL_REG_0 BIT(0) + +/*NPSS interrupt numbers*/ +#define NPSS_TO_MCU_WDT_INTR BIT(0) +#define NPSS_TO_MCU_GPIO_INTR_0 BIT(1) +#define NPSS_TO_MCU_GPIO_INTR_1 BIT(2) +#define NPSS_TO_MCU_GPIO_INTR_2 BIT(3) +#define NPSS_TO_MCU_GPIO_INTR_3 BIT(4) +#define NPSS_TO_MCU_GPIO_INTR_4 BIT(5) + +#define NPSS_TO_MCU_CMP_INTR_1 BIT(6) +#define NPSS_TO_MCU_CMP_INTR_2 BIT(7) +#define NPSS_TO_MCU_CMP_INTR_3 BIT(8) +#define NPSS_TO_MCU_CMP_INTR_4 BIT(9) + +#define NPSS_TO_MCU_RFWAKEUP_INTR BIT(10) + +#define NPSS_TO_MCU_BOD_INTR BIT(11) +#define NPSS_TO_MCU_BUTTON_INTR BIT(12) + +#define NPSS_TO_MCU_SDC_INTR BIT(13) +#define NPSS_TO_MCU_WIRELESS_INTR BIT(14) +#define NPSS_TO_MCU_WAKEUP_INTR BIT(15) +#define NPSS_TO_MCU_ALARM_INTR BIT(16) +#define NPSS_TO_MCU_SEC_INTR BIT(17) +#define NPSS_TO_MCU_MSEC_INTR BIT(18) +#define NPSS_TO_MCU_PROCESSOR_INTR BIT(19) +#define NPSS_TO_MCU_HOST_INTR BIT(20) +#define NPSS_TO_MCU_DST_INTR BIT(21) + +#define ENABLE_NEGEDGE_ULP BIT(1) +#define ULP_MODE_SWITCHED_NPSS BIT(3) +#define ULP_MODE_AFTR_CLK_SW BIT(2) + +/*wake up status register */ +/*MCU_FSM_WAKEUP_STATUS_REG Reg(0x38) (MCU FSM)*/ +#define CDBG_POWER_UP_REQUEST_WAKEUP BIT(6) +#define WATCH_DOG_WINDOW_RESET_INTERRUPT BIT(5) +#define WWD_RESET_LOOKUP_WAKEUP BIT(4) +#define WATCHDOG_RESET_INTERRUPT BIT(3) +#define HOST_BASED_WAKEUP_S BIT(2) +#define TIMEOUT_WAKEUP BIT(1) +#define WAKEUP_INDICATION BIT(0) + +/*wake up status clear register */ +/*MCU_FSM_WAKEUP_STATUS_CLEAR Reg(0x3C) (MCU FSM)*/ +#define MCU_WAKEUP_INTERRUPT BIT(11) +#define RF_WAKEUP_CLEAR BIT(10) +#define COMP6_BASED_WAKEUP_STATUS_CLEAR BIT(9) +#define COMP5_BASED_WAKEUP_STATUS_CLEAR BIT(8) +#define COMP4_BASED_WAKEUP_STATUS_CLEAR BIT(7) +#define COMP3_BASED_WAKEUP_STATUS_CLEAR BIT(6) +#define COMP2_BASED_WAKEUP_STATUS_CLEAR BIT(5) +#define COMP1_BASED_WAKEUP_STATUS_CLEAR BIT(4) +#define RTC_ALARM_BASED_WAKEUP_STATUS_CLEAR BIT(3) +#define RTC_SEC_BASED_STATUS_CLEAR BIT(2) +#define MILLI_SEC_BASED_STATUS_CLEAR BIT(1) +#define WWD_INTERRUPT_STATUS_CLEAR BIT(0) + +/*PMU status configuration bits */ +/* MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE Reg bits (0x0)(MCU FSM)*/ +#define PMU_STS_DCDC_ON BIT(10) +#define PMU_STS_FLASH_LDO_ON BIT(9) +#define PMU_STS_SOC_LDO_ON BIT(8) + +/*PMU */ +#define STANDBY_LDOSOC_R BIT(18) +#define STANDBY_LDORF_R BIT(17) +#define BGPMU_SLEEP_EN_R BIT(16) + +/*Retention sleep configurations*/ +#if defined(SLI_SI917B0) || defined(SLI_SI915) + +//!PSRAM only initialized upon wakeup and it branches to PSRAM +#define SL_SI91X_MCU_WAKEUP_PSRAM_MODE 1 + +//!PSRAM and FLASH both will be initialized upon wake up,BIT4 refers to program flash upon wakeup +#define RSI_WAKEUP_FROM_FLASH_MODE (0x1 | (BIT(4))) +#else +#define RSI_WAKEUP_FROM_FLASH_MODE 1 +#endif +#define RSI_WAKEUP_WITH_OUT_RETENTION 2 +#define RSI_WAKEUP_WITH_RETENTION 3 +#define RSI_WAKEUP_WITH_RETENTION_WO_ULPSS_RAM 4 +#define RSI_WAKEUP_WO_RETENTION_WO_ULPSS_RAM 5 + +//!Retention ram content ulp memory start ,end addresses for power save retention sleep cases +#define RETEN_RAM_CONTENT_START_LOCATION (*(volatile uint32_t *)(0x24061F00)) +#define RETEN_RAM_CONTENT_END_LOCATION (*(volatile uint32_t *)(0x24061FCC)) +#define RETEN_RAM_CONTENT_WAKEUP_FLASH_BIT_LOCATION (*(volatile uint32_t *)(0x24061FC8)) + +#define ICACHE2_ADDR_TRANSLATE_1_REG *(volatile uint32_t *)(0x20280000 + 0x24) // ICACHE address register +#ifndef MISC_CFG_SRAM_REDUNDANCY_CTRL +#define MISC_CFG_SRAM_REDUNDANCY_CTRL *(volatile uint32_t *)(0x46008000 + 0x18) // Misc config register +#endif +#ifndef MISC_CONFIG_MISC_CTRL1 +#define MISC_CONFIG_MISC_CTRL1 *(volatile uint32_t *)(0x46008000 + 0x44) // Misc control register +#endif +#define P2P_STATUS_REGISTER *(volatile uint32_t *)(0x46008000 + 0x174) // P2P status register +#define M4SS_P2P_INTR_SET_REGISTER *(volatile uint32_t *)(0x46008000 + 0x16C) // P2P interrupt set register + +typedef enum FSM_CLK { FSM_NO_CLOCK = 0, FSM_20MHZ_RO = 1, FSM_MHZ_RC = 2, FSM_40MHZ_XTAL = 4 } FSM_CLK_T; + +typedef enum AON_CLK { KHZ_RO_CLK_SEL = 1, KHZ_RC_CLK_SEL = 2, KHZ_XTAL_CLK_SEL = 4 } AON_CLK_T; + +/*Ship modes*/ +typedef enum SHUT_DOWN_WKP_MODE { + NPSS_GPIO_2_BASED = 0, + NPSS_GPIO_1_BASED = 1, + NPSS_GPIO_2_AND_3_BASED = 2, + NPSS_GPIO_2_OR_3_BASED = 3, +} SHUT_DOWN_WKP_MODE_T; + +/// @brief Peri efuse power state +typedef enum { POWER_DOWN, POWER_UP } peri_efuse_power_state_t; + +/*m4ss context switch top ULP mode selection */ +typedef enum ULP_MODE { ULP_MCU_MODE = 1, UULP_MCU_MODE = 3 } ULP_MODE_T; + +/*NPSS Comparator selection*/ +typedef enum NPSS_COMPARATOR { + NPSS_CMP_1, + NPSS_CMP_2, + NPSS_CMP_3, + NPSS_CMP_4, + NPSS_CMP_5, +} NPSS_COMPARATOR_T; + +#define _SOC_LDO 3 +#define MCU_SOC_LDO_LVL BIT(17) +#define MCU_DCDC_LVL BIT(18) + +/*Select value for ULPSS RAM Power MUX*/ +#define PWR_MUX_SEL_ULPSSRAM_SOC_LDO 3 +#define PWR_MUX_SEL_ULPSSRAM_SCDC_0_9 1 +#define PWR_MUX_SEL_ULPSSRAM_SCDC_0_6 0 + +/*Select value for M4 ULP RAM Power MUX*/ +#define PWR_MUX_SEL_M4_ULP_RAM_SOC_LDO 3 +#define PWR_MUX_SEL_M4_ULP_RAM_SCDC_0_9 1 +#define PWR_MUX_SEL_M4_ULP_RAM_SCDC_0_6 0 + +/*Select value for M4 ULP RAM 16K Power MUX*/ +#define PWR_MUX_SEL_M4_ULP_RAM16K_SOC_LDO 3 +#define PWR_MUX_SEL_M4_ULP_RAM16K_SCDC_0_9 1 +#define PWR_MUX_SEL_M4_ULP_RAM16K_SCDC_0_6 0 + +/*Select value for M4 ULP (Cortex Core)Power MUX*/ +#define PWR_MUX_SEL_M4ULP_SOC_LDO 3 +#define PWR_MUX_SEL_M4ULP_SCDC_0_9 1 +#define PWR_MUX_SEL_M4ULP_SCDC_0_6 0 + +/*Select value for ULPSS (Peripherals)Power MUX*/ +#define PWR_MUX_SEL_ULPSS_SOC_LDO 1 +#define PWR_MUX_SEL_ULPSS_SCDC_0_9 0 + +/*BG SAMPLE ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_BG_SAMPLE_ENABLE 1 +#define DISABLE_BG_SAMPLE_ENABLE 0 + +/*DC DC ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_DC_DC_ENABLE 1 +#define DISABLE_DC_DC_ENABLE 0 + +/*SOC LDO ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_SOCLDO_ENABLE 1 +#define DISABLE_SOCLDO_ENABLE 0 + +/*STAND BY ENABLE AND DISABLE /ENABLE MACROS*/ +#define ENABLE_STANDBYDC 1 +#define DISABLE_STANDBYDC 0 + +/* NWP 192K RAM RETENTION MODE ENABLE in PS2 */ +#define ENABLE_TA192K_RAM_RET 1 +#define DISABLE_TA192K_RAM_RET 0 + +/* M4 64K RAM RETENTION MODE ENABLE in PS2 */ +#define ENABLE_M464K_RAM_RET 1 +#define DISABLE_M464K_RAM_RET 0 + +#define NWP_FSM_CLOCKS_SELECT *(volatile uint32_t *)0x41300114 +#define ENABLE_RO_32KHz_N_RO_20MHz 0x9 + +#define NWP_FSM_CLK_EN_AND_FIRST_BOOTUP *(volatile uint32_t *)0x41300120 +#define DISABLE_ULP_CLKS 0x790000 + +#define NWPAON_NPSS_PWRCTRL_CLEAR_REG *(volatile uint32_t *)0x4130000C +#define PWRGATE_EN_N_ULP_NWPDOMAINS 0x78 + +#define STANDBY_DC1P3 BIT(19) +#define BGPMU_SLEEP_EN BIT(1) +#define SCDCDC_LP_MODE_EN BIT(0) +#define NWP_PMU_CTRLS *(volatile uint32_t *)0x41300140 + +#define TASS_REF_CLOCK_SELECT *(volatile uint32_t *)0x41300110 +#define TASS_REF_CLK_CLEANER_OFF BIT(22) +#define TASS_REF_CLK_CLEANER_ON BIT(23) + +#define TASS_PMU_LDO_CTRL_CLEAR *(volatile uint32_t *)0x41300424 +#define TASS_SOC_LDO_LVL BIT(17) +#define TASS_DCDC_LVL BIT(18) + +#define RF_AFE_PWR_CTRL_REG *(volatile uint32_t *)0x41300480 +#define RF2G_SHUTDOWN BIT(5) + +#define RF_AFE_PWR_CTRL_REG *(volatile uint32_t *)0x41300480 +#define RF2G_PG_EN BIT(7) +#define AFE_PG_EN BIT(1) + +#define TASS_M4SS_CRTL_SET_REG *(volatile uint32_t *)0x41300470 +#define TASS_CTRL_SOCPLL_SPI_PG_EN BIT(20) + +#define MODEM_BAND1_PWRCTRL_CLEAR_REG *(volatile uint32_t *)0x41300408 +#define MODEM_EXT_PWRGATE_EN_N_ULP_BBP_WLAN_GAINLUT BIT(28) +#define MODEM_EXT_PWRGATE_EN_N_ULP_BBP_TXPPLUT BIT(24) +#define MODEM_EXT_PWRGATE_EN_N_ULP_PPE_SHARED BIT(20) +#define MODEM_EXT_PWRGATE_EN_N_ULP_PPE_IMDM BIT(16) + +#define MODEM_ZBBT_PWRCTRL_CLEAR_REG *(volatile uint32_t *)0x41300418 +#define MODEM_EXT_PWRGATE_EN_N_ULP_BBP_ZBBT_GAINLUT BIT(4) + +#define NWP_RTC_TIMER_CLOCK_PERIOD_SOC *(volatile uint32_t *)(0x41300204) +#define RTC_TIMER_CLK_PERIOD_VALUE 0x003E7FFF + +#define SPI_RTC_TIMER_CLK_PERIOD_APPLIED BIT(31) + +#define NWP_FSM_SLEEP_WAKEUP_MODES *(volatile uint32_t *)0x41300100 +#define COUNT_TICK_ENABLE 0x1 +#if defined(SLI_SI917B0) || defined(SLI_SI915) +#define MCURET_BOOTSTATUS_REG *(volatile uint32_t *)(MCU_NPSS_BASE_ADDR + 0x604) +#define KEY_SIZE_IN_DWORDS 8 + +#define RSI_WAKE_FROM_FLASH_CB_START_ADDR 0x24061F00 + +#define STACK_AND_CB_ADDR_PRESENT_IN_BBFF BIT(20) + +#define RSI_WAKE_FROM_FLASH_JUMP_ADDR 0x24061F28 + +#define STACK_AND_CB_ADDR_BIT_NO 12 +#define QSPI_KEY_SIZE_256 BIT(16) +#define PSRAM_SEC_EN BIT(23) +#define KEY_LENGTH BIT(11) +#define PSRAM_SEC_EN BIT(23) +#define M4SS_PSRAM_QSPI_BASE_ADDRESS 0x12040000 +#endif + +#define MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_REG *(volatile uint32 *)(0x24048100 + 0x0) +#define LDO_FLASH_ON BIT(9) +#define PMU_DCDC_ON BIT(10) + +/** @addtogroup SOC2 +* @{ +*/ +/** + * @fn STATIC INLINE rsi_error_t ps_power_state_change_ps4tops2( ULP_MODE_T enCtxSel , + * uint8_t PwrMuxSelUlpssRam , + * uint8_t pwrMuxSelM4UlpRam , + * uint8_t pwrMuxSelM4UlpRam16K , + * uint8_t pwrMuxSelM4Ulp , + * uint8_t pwrMuxSelUlpss , + * uint8_t bgSampleEnable , + * uint8_t dcDcEnable , + * uint8_t socLdoEnable , + * uint8_t standByDc + * ) + * @brief This API is used to used to change the power transition state from Power save state 4/3 to power save state 2 + * @param[in] enCtxSel : is Select enum for the context top ULP mode + * \n 00, 10 - \ref HP-MCU/LP-MCU Mode + * \n 01 - \ref ULP-MCU Mode + * \n 11 - \ref UULP-MCU Mode + * \n (1st 16K of M4 RAM is dedicated to IM, + * \n 2nd 16K of M4 RAM is dedicated to DM) + * @param[in] pwrMuxSelM4UlpRam : Select value for M4 ULP RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] PwrMuxSelUlpssRam :Select value for ULPSS RAM Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4UlpRam16K : is Select value for M4 ULP RAM 16K Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelM4Ulp : is Select value for M4 ULP (Peripherals + CORTEX Core )Power MUX + * \n 3 \ref SOC LDO + * \n 1 \ref SCDCDC 0.9 + * \n 0 \ref SCDCDC 0.6 + * @param[in] pwrMuxSelUlpss : is Select value for ULPSS(Peripherals) Power MUX + * \n 1 \ref SOC LDO + * \n 0 \ref SCDCDC 0.9 + * @param[in] bgSampleEnable : Value to enable or disable the bg Sample + * \n 0 :Disable + * \n 1 :Enale + * @param[in] dcDcEnable : Value to enable or disable the dcDcEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] socLdoEnable : Value to enable or disable the socLdoEnable + * \n 0 :Disable + * \n 1 :Enale + * @param[in] standByDc : Value to enable or disable the standByDc + * \n 0 :Disable + * \n 1 :Enale + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t ps_power_state_change_ps4tops2(ULP_MODE_T enCtxSel, + uint8_t PwrMuxSelUlpssRam, + uint8_t pwrMuxSelM4UlpRam, + uint8_t pwrMuxSelM4UlpRam16K, + uint8_t pwrMuxSelM4Ulp, + uint8_t pwrMuxSelUlpss, + uint8_t bgSampleEnable, + uint8_t dcDcEnable, + uint8_t socLdoEnable, + uint8_t standByDc) +{ + volatile int x = 0; + + /*return error if this function is called from PS2*/ + if (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) { + return ERROR_PS_INVALID_STATE; + } + + /*Static clock enable m4 core in ULP mode*/ + M4LP_CTRL_REG |= ULP_M4_CORE_CLK_ENABLE; + + /*flushes the transactions in the Bridge before transition to PS2 state*/ + x = (int)ULPCLK->ULP_TA_CLK_GEN_REG; + /*Select the MCU mode*/ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.M4SS_CONTEXT_SWITCH_TOP_ULP_MODE = enCtxSel; + + /*Avoid the junk system bus access*/ + for (x = 0; x < 10; x++) { + __ASM("NOP"); + } + /* + Indicates the status of functional switching to ULP Mode operation + 0 - PS4 state + 1 - PS2 state + */ + do { + /*wait for status of functional switching to ULP Mode operation*/ + x++; + } while ((M4_ULP_SLP_STATUS_REG & ULP_MODE_AFTR_CLK_SW) != ULP_MODE_AFTR_CLK_SW); + + /*Select value for ULPSS RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS_RAM = (unsigned int)(PwrMuxSelUlpssRam & 0x3); + /*Select value for M4 ULP RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM = (unsigned int)(pwrMuxSelM4UlpRam & 0x3); + /*Select value for M4 ULP RAM 16K Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM_16K = (unsigned int)(pwrMuxSelM4UlpRam16K & 0x3); + /*Select value for M4 ULP (Peripherals + Cortex Core )Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP = (unsigned int)(pwrMuxSelM4Ulp & 0x3); + /*Select value for ULPSS(Peripherals) Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS = (unsigned int)(pwrMuxSelUlpss & 0x1); + + /*update the SOC LDO*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_SOC_LDO_EN = (unsigned int)(socLdoEnable & 0x1); + + if (socLdoEnable == 1) { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = 1; + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.BGPMU_SAMPLING_EN_R = 0; + } + + else { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = (unsigned int)(socLdoEnable & 0x1); + } + + if (dcDcEnable == 1) { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = (unsigned int)(dcDcEnable & 0x1); + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.BGPMU_SAMPLING_EN_R = 0; + } else { + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.FSM_PERI_DCDC_EN = (unsigned int)(dcDcEnable & 0x1); + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.BGPMU_SAMPLING_EN_R = (unsigned int)(bgSampleEnable & 0x1); + } + + if ((socLdoEnable == 0) && (dcDcEnable == 1)) { + MCU_FSM->MCU_FSM_PMU_STATUS_REG_b.STANDBY_DC1P3_R = (unsigned int)(standByDc & 0x1); + } + /*Set the LDO turn off delay*/ + + /*PMU off delay */ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS2_PMU_LDO_OFF_DELAY = PMU_LDO_OFF_DELAY; + +#if !defined(SLI_SI917) && !defined(SLI_SI915) + /*Bridge clock disable*/ + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 0; +#endif + + /*Set ulp mode isolation */ + BATT_FF->M4_ULP_MODE_CONFIG = (BATT_FF->M4_ULP_MODE_CONFIG | 0x3F); + + /* Setting RETN_LDO voltage to 0.75V */ + RSI_IPMU_RetnLdo0p75(); + + /* enabling the RETN_LDO HP MODE */ + RSI_IPMU_RetnLdoHpmode(); + + /*Enable the ULP mode */ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.ULP_MCU_MODE_EN = 1; + + /* Wait for Status bit indicating Physical transition from PS2 to PS4*/ + do { + /*wait for status of Physical switching to ULP Mode operation*/ + x++; + } while ((M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) != ULP_MODE_SWITCHED_NPSS); + + return RSI_OK; +} + +/** + * @fn STATIC INLINE rsi_error_t ps_power_state_change_ps2_to_Ps4(uint32_t PmuBuckTurnOnWaitTime , uint32_t SocLdoTurnOnWaitTime) + * @brief This API is used to change the power state from PS2 to PS4 + * @param[in] PmuBuckTurnOnWaitTime : PMU buck time + * @param[in] SocLdoTurnOnWaitTime : soc ldo turn on time + * @return returns 0 \ref RSI_OK on success,return error code on error + */ +STATIC INLINE rsi_error_t ps_power_state_change_ps2_to_Ps4(uint32_t PmuBuckTurnOnWaitTime, + uint32_t SocLdoTurnOnWaitTime) +{ + uint8_t x; + /*Return if this is issues in PS4 state */ + if (!(M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS)) { + return ERROR_PS_INVALID_STATE; + } +#ifdef CHIP_9118 + /*Disables clock to ULP-M4SS AHB-AHB Bridge since the MCU is in PS2 state logically*/ + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 0; +#endif + /*Select value for ULPSS RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS_RAM = _SOC_LDO; + /*Select value for M4 ULP RAM Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM = _SOC_LDO; + /*Select value for M4 ULP RAM 16K Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP_RAM_16K = _SOC_LDO; + /*Select value for M4 ULP (Peripherals + Cortex Core )Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_M4_ULP = _SOC_LDO; + /*Select value for ULPSS(Peripherals) Power Mux*/ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.POWER_MUX_SEL_ULPSS = 0x01; + + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PG4_BUCK_ON_DELAY = (unsigned int)(PmuBuckTurnOnWaitTime & 0xF); + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS4_SOCLDO_ON_DELAY = (unsigned int)(SocLdoTurnOnWaitTime & 0xF); + + MCU_FSM->MCU_FSM_PMU_STATUS_REG_b.STANDBY_DC1P3_R = 0; + + /*Disable the ULP mode */ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.ULP_MCU_MODE_EN = 0; + // NOTE : nopes issue issue is fixed by adding this bit + /* Wait for Status bit indicating Physical transition from PS2 to PS4*/ + /*Avoid the junk system bus access*/ + for (x = 0; x < 10; x++) { + __ASM("NOP"); + } + + while (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS) + ; + + /*Disable ulp mode isolation */ + BATT_FF->M4_ULP_MODE_CONFIG &= ~(0x3F); + +#if !defined(SLI_SI917) && !defined(SLI_SI915) + /*Disables clock to ULP-M4SS AHB-AHB Bridge since the MCU is in PS2 state logically*/ + ULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 1; +#endif + + /*Select the MCU mode*/ + MCU_FSM->MCU_FSM_PERI_CONFIG_REG_b.M4SS_CONTEXT_SWITCH_TOP_ULP_MODE = 0; + // NOTE : nopes issue issue is fixed by adding this bit + /* Wait for Status bit indicating Functional transition from PS4 to PS2*/ + while (M4_ULP_SLP_STATUS_REG & ULP_MODE_AFTR_CLK_SW) + ; + + /* Setting RETN_LDO voltage to 0.7V */ + RSI_IPMU_RetnLdoVoltsel(); + + /* enabling the RETN_LDO LP MODE */ + RSI_IPMU_RetnLdoLpmode(); +#if !defined(SLI_SI917) && !defined(SLI_SI915) + M4CLK->CLK_ENABLE_SET_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + for (x = 0; x < 200; x++) { + __ASM("NOP"); + } +#if !defined(SLI_SI917) && !defined(SLI_SI915) + M4CLK->CLK_ENABLE_CLR_REG1_b.M4SS_UM_CLK_STATIC_EN_b = 0x1; +#endif + return RSI_OK; +} +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_POWER_SAVE + * @{ + * + */ +/** + * @fn STATIC INLINE void RSI_PS_PowerStateChangePs4toPs3(void) + * @brief This API is used to Change the power state from PS4 to PS3 + * \n + * \ref MCU_PMU_LDO_CTRL_CLEAR + */ +STATIC INLINE void RSI_PS_PowerStateChangePs4toPs3(void) +{ + /*Clear the MCU_SOC_LDO_LVL */ + BATT_FF->MCU_PMU_LDO_CTRL_CLEAR = MCU_SOC_LDO_LVL; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetDcDcToHigerVoltage(void) + * @brief This API is used configure DCDC to give higher output voltage. + * \n + * \ref MCU_PMU_LDO_CTRL_SET + */ +STATIC INLINE void RSI_PS_SetDcDcToHigerVoltage(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_SET = MCU_DCDC_LVL; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetDcDcToLowerVoltage(void) + * @brief This API is used configure DCDC to give lower output voltage. + * \n + * \ref MCU_PMU_LDO_CTRL_CLEAR + */ +STATIC INLINE void RSI_PS_SetDcDcToLowerVoltage(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_CLEAR = MCU_DCDC_LVL; +} + +/** + * @fn STATIC INLINE void RSI_PS_PowerStateChangePs3toPs4(void) + * @brief This API is used to Change the power state from PS3 to PS4 + * \n + * \ref MCU_PMU_LDO_CTRL_SET + */ +STATIC INLINE void RSI_PS_PowerStateChangePs3toPs4(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_SET = MCU_SOC_LDO_LVL; + return; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the M4SS peripherals + * @param[in] mask OR'ed value of the power gates + * \n + * \ref M4SS_PWRCTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_M4ssPeriPowerDown(uint32_t mask) +{ + BATT_FF->M4SS_PWRCTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssPeriPowerUp(uint32_t mask) + * @brief This API is used to un power gate the M4SS peripherals + * @param[in] mask OR'ed value of the power gates + * \n + * \ref M4SS_PWRCTRL_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_M4ssPeriPowerUp(uint32_t mask) +{ + BATT_FF->M4SS_PWRCTRL_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void sl_si91x_peri_efuse_power_control(bool power_up) + * @brief This API is used to power gate the PERI_EFUSE power domain, This power domain contains the different M4SS peripherals those are + * SPI/SSI Master, I2C, USART, Micro-DMA Controller, UART, SPI/SSI Slave, Generic-SPI Master, Config Timer, Random-Number Generator, + * CRC Accelerator, SIO, I2C, I2S Master/Slave, QEI, MCPWM ,EFUSE and MVP + * @param[in] power_up 1 - Power Up the EFUSE Peri Power domain + * 0 - Power Down the EFUSE Peri power domain + * @return none + */ +STATIC INLINE void sl_si91x_peri_efuse_power_state_control(peri_efuse_power_state_t power_up) +{ + if (power_up) { + RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI); + } else { + RSI_PS_M4ssPeriPowerDown(M4SS_PWRGATE_ULP_EFUSE_PERI); + } +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ss_Tass_Ctrl_Clear(uint32_t mask) + * @brief This API is used to clear the M4SS TASS controls + * @param[in] mask OR'ed value of the power gates + * \n + * \ref M4SS_TASS_CTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_M4ss_Tass_Ctrl_Clear(uint32_t mask) +{ + BATT_FF->M4SS_TASS_CTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the ULPSS peripherals + * @param[in] mask OR'ed value of the power gates + * \n + * \ref ULPSS_PWRCTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_UlpssPeriPowerDown(uint32_t mask) +{ + BATT_FF->ULPSS_PWRCTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssPeriPowerUp(uint32_t mask) + * @brief This API is used to un power gate the ULPSS peripherals + * @param[in] mask OR'ed value of the power domains + * \n + * \ref ULPSS_PWRCTRL_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_UlpssPeriPowerUp(uint32_t mask) +{ + BATT_FF->ULPSS_PWRCTRL_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssPeriPowerUp(uint32_t mask) + * @brief This API is used to un power gate the NPSS peripherals + * @param[in] mask OR'ed value of the power domains + * \n + * \ref MCUAON_NPSS_PWRCTRL_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssPeriPowerUp(uint32_t mask) +{ + MCU_AON->MCUAON_NPSS_PWRCTRL_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the NPSS peripherals + * @param[in] mask OR'ed value of the power domains + * \n + * \ref MCUAON_NPSS_PWRCTRL_CLEAR_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssPeriPowerDown(uint32_t mask) +{ + MCU_AON->MCUAON_NPSS_PWRCTRL_CLEAR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPowerDown(uint32_t mask) + * @brief This API is used to power gate the M4SS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPowerDown(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_CLEAR_REG1 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPowerUp(uint32_t mask) + * @brief This API is used to un power gate the M4SS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPowerUp(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_SET_REG1 = mask; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPowerSts(void) + * @brief This API is used to get the power gate status of M4SS RAM Banks + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return Ored bits of M4_SRAM_PWRCTRL_SET_REG1 reg + */ +STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPowerSts(void) +{ + return BATT_FF->M4_SRAM_PWRCTRL_SET_REG1; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the M4SS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerDown(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_CLEAR_REG2 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerUp(uint32_t mask) + * @brief This API is used to un-power gate the M4SS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_M4ssRamBanksPeriPowerUp(uint32_t mask) +{ + BATT_FF->M4_SRAM_PWRCTRL_SET_REG2 = mask; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPeriPowerSts(void) + * @brief This API is used to get the power gate status of M4SS RAM Banks periphery domain + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return Ored bits of M4_SRAM_PWRCTRL_SET_REG2 register. + */ +STATIC INLINE uint32_t RSI_PS_M4ssRamBanksGetPeriPowerSts(void) +{ + return BATT_FF->M4_SRAM_PWRCTRL_SET_REG2; +} +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerDown(uint32_t mask) + * @brief This API is used to power gate the ULPSS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerDown(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_CLEAR_REG3 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerUp(uint32_t mask) + * @brief This API is used to un-power gate the ULPSS RAM Banks periphery domain + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref M4_SRAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPeriPowerUp(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_SET_REG3 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetRamRetention(uint32_t ramRetention) + * @brief This API is used to set the RAM retention enable for the RAM during sleep + * @param[in] ramRetention OR'ed value of the RAM retention bits + * \n + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_SetRamRetention(uint32_t ramRetention) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= ramRetention; +} + +/** + * @fn STATIC INLINE void RSI_PS_ClrRamRetention(uint32_t ramRetention) + * @brief This API is used to clear the RAM retention enable for the RAM during sleep + * @param[in] ramRetention OR'ed value of the RAM retention bits + * \n + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_ClrRamRetention(uint32_t ramRetention) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE &= ~ramRetention; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPowerDown(uint32_t mask) + * @brief This API is used to power gate the ULPSS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref ULPSS_RAM_PWRCTRL_CLEAR_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPowerDown(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_CLEAR_REG1 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_UlpssRamBanksPowerUp(uint32_t mask) + * @brief This API is used to un power gate the ULPSS RAM Banks + * @param[in] mask OR'ed value of the RAM power gates + * \n + * \ref ULPSS_RAM_PWRCTRL_SET_REG1 + * @return none + */ +STATIC INLINE void RSI_PS_UlpssRamBanksPowerUp(uint32_t mask) +{ + BATT_FF->ULPSS_RAM_PWRCTRL_SET_REG1 = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_SetWkpSources(uint32_t wakeUpsrcMask) + * @brief This API is used to set the wake up source to wake up from deep sleep + * @param[in] wakeUpsrcMask OR'ed value of the wake up sources + * \n + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_SetWkpSources(uint32_t wakeUpsrcMask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= wakeUpsrcMask; +} + +/** + * @fn STATIC INLINE void RSI_PS_ClrWkpSources(uint32_t wakeUpsrcMask) + * @brief This API is used to clear the wake up source + * @param[in] wakeUpsrcMask OR'ed value of the wake up sources + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE + * @return none + */ +STATIC INLINE void RSI_PS_ClrWkpSources(uint32_t wakeUpsrcMask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE &= ~wakeUpsrcMask; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_GetWkpSources(void) + * @brief This API is used to get the wake up source + * @return register bits of wake up sources + */ +STATIC INLINE uint32_t RSI_PS_GetWkpSources(void) +{ + return MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE; +} + +/** + * @fn STATIC INLINE void RSI_PS_EnableFirstBootUp(boolean_t enable) + * @brief This API is used to SET and CLEAR the First boot up bit + * @param[in] enable : + * \ref MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b 0: disable the first boot , + * \ref MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b 1: enable the first boot up + * @return none + */ +STATIC INLINE void RSI_PS_EnableFirstBootUp(boolean_t enable) +{ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.FIRST_BOOTUP_MCU_N_b = (unsigned int)(enable & 0x01); +} + +/** + * @fn STATIC INLINE void RSI_PS_PowerSupplyEnable(uint32_t mask) + * @brief This API is used to enable the supply to some NPSS peripherals + * @param[in] mask 0: disable the first boot , 1: enable the first boot up + * @return none + */ +STATIC INLINE void RSI_PS_PowerSupplyEnable(uint32_t mask) +{ + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES |= mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_PowerSupplyDisable(uint32_t mask) + * @brief This API is used to disable the supply to some NPSS peripherals + * @param[in] mask 0: disable the first boot , 1: enable the first boot up + * \ref MCU_FSM_CRTL_PDM_AND_ENABLES + * @return none + */ +STATIC INLINE void RSI_PS_PowerSupplyDisable(uint32_t mask) +{ + MCU_FSM->MCU_FSM_CRTL_PDM_AND_ENABLES &= ~mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_FsmHfClkSel(FSM_CLK_T fsmHfClk) + * @brief This API is used to configure the FSM high frequency clock + * @param[in] fsmHfClk : enum value of the high frequency clock sources + * \ref MCU_FSM_CLKS_REG_b + * @return none + */ +STATIC INLINE void RSI_PS_FsmHfClkSel(FSM_CLK_T fsmHfClk) +{ + MCU_FSM->MCU_FSM_CLKS_REG_b.HF_FSM_CLK_SELECT = fsmHfClk; + while (MCU_FSM->MCU_FSM_CLKS_REG_b.HF_FSM_CLK_SWITCHED_SYNC != 1) + ; +} + +/** + * @fn STATIC INLINE void RSI_PS_FsmHfFreqConfig(uint32_t freq) + * @brief This API is used to configure the FSM high frequency clock range + * @param[in] freq : frequency in MHz pass 2 if it is 2MHz + * @return none + */ +STATIC INLINE void RSI_PS_FsmHfFreqConfig(uint32_t freq) +{ + MCU_FSM->MCU_FSM_CLKS_REG_b.HF_FSM_CLK_FREQ = (unsigned int)(freq & 0x3F); +} + +/** + * @fn STATIC INLINE void RSI_PS_FsmLfClkSel(AON_CLK_T fsmLfClk) + * @brief This API is used to configure the FSM low frequency clock + * @param[in] fsmLfClk enum value of the low frequency clock sources + * \ref MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b + * @return none + */ +STATIC INLINE void RSI_PS_FsmLfClkSel(AON_CLK_T fsmLfClk) +{ + MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.AON_KHZ_CLK_SEL = fsmLfClk; + while (MCU_AON->MCUAON_KHZ_CLK_SEL_POR_RESET_STATUS_b.AON_KHZ_CLK_SEL_CLOCK_SWITCHED != 1) + ; +} + +/** + * @fn STATIC INLINE void RSI_PS_PmuGoodTimeDurationConfig(uint8_t pmuDuration) + * @brief This API is used to configure the PMU good time. + * @param[in] pmuDuration (0 to 31) are possible value is applied in power of 2. + * @return none + */ +STATIC INLINE void RSI_PS_PmuGoodTimeDurationConfig(uint8_t pmuDuration) +{ +#ifdef CHIP_9118 + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_PMU_POWERGOOD_DURATION_COUNT = + (unsigned int)(pmuDuration & 0x1F); +#endif +#if defined(SLI_SI917) || defined(SLI_SI915) + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_PMU_POWERGOOD_DURATION_COUNT = + (unsigned int)(pmuDuration & 0x7F); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_XtalGoodTimeDurationConfig(uint8_t xtalDuration) + * @brief This API is used to configure the XTAL good time. + * @param[in] xtalDuration (0 to 31) are possible value is applied in power of 2. + * \ref MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b + * @return none + */ +STATIC INLINE void RSI_PS_XtalGoodTimeDurationConfig(uint8_t xtalDuration) +{ +#ifdef CHIP_9118 + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_XTAL_GOODTIME_DURATION_COUNT = + (unsigned int)(xtalDuration & 0x1F); +#endif +#if defined(SLI_SI917) || defined(SLI_SI915) + MCU_FSM->MCU_FSM_XTAL_AND_PMU_GOOD_COUNT_REG_b.MCUFSM_XTAL_GOODTIME_DURATION_COUNT = + (unsigned int)(xtalDuration & 0x7F); +#endif +} + +/** + * @fn STATIC INLINE void RSI_PS_Ps2PmuLdoOffDelayConfig(uint8_t ldoOffDelay) + * @brief This API is used to configure LDO off delay + * @param[in] ldoOffDelay (0 to 31) are possible value is applied in power of 2. + * @return none + */ +STATIC INLINE void RSI_PS_Ps2PmuLdoOffDelayConfig(uint8_t ldoOffDelay) +{ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS2_PMU_LDO_OFF_DELAY = (unsigned int)(ldoOffDelay & 0x1F); +} + +/** + * @fn STATIC INLINE void RSI_PS_Ps4PmuLdoOnDelayConfig(uint8_t ldoOnDelay) + * @brief This API is used to configure LDO on delay + * @param[in] ldoOnDelay (0 to 31) are possible value is applied in power of 2. + * \ref MCU_FSM_POWER_CTRL_AND_DELAY_b + * @return none + */ +STATIC INLINE void RSI_PS_Ps4PmuLdoOnDelayConfig(uint8_t ldoOnDelay) +{ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PS4_SOCLDO_ON_DELAY = (unsigned int)(ldoOnDelay & 0xF); +} + +/** + * @fn STATIC INLINE void RSI_PS_Ps4PmuBuckOnDelayConfig(uint8_t pmuBuckOnDelay) + * @brief This API is used to configure buck on delay + * @param[in] pmuBuckOnDelay (0 to 31) are possible value is applied in power of 2. + * \ref MCU_FSM_POWER_CTRL_AND_DELAY_b + * @return none + */ +STATIC INLINE void RSI_PS_Ps4PmuBuckOnDelayConfig(uint8_t pmuBuckOnDelay) +{ + MCU_FSM->MCU_FSM_POWER_CTRL_AND_DELAY_b.PG4_BUCK_ON_DELAY = (unsigned int)(pmuBuckOnDelay & 0xF); +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_GetWkpUpStatus(void) + * @brief This API is used to get the wake up/ NPSS interrupt status + * \ref NPSS_INTR_STATUS_REG + * @return register bits of NPSS interrupt status register + * @return wakeup/NPSS intr status + */ +STATIC INLINE uint32_t RSI_PS_GetWkpUpStatus(void) +{ + return NPSS_INTR_STATUS_REG; +} + +/** + * @fn STATIC INLINE uint32_t RSI_PS_GetComnIntrSts(void) + * @brief This API is used to get the wake up/ NPSS common interrupt status + * @return register bits of NPSS interrupt status register + * \ref MCU_FSM_WAKEUP_STATUS_REG + * @return wake up/NPSS common inrerrupt status + */ +STATIC INLINE uint32_t RSI_PS_GetComnIntrSts(void) +{ + return MCU_FSM->MCU_FSM_WAKEUP_STATUS_REG; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssIntrUnMask(uint32_t mask) + * @brief This API is used to un mask the NPSS interrupts + * @param[in] mask is OR'ed value of the NPSS interrupt bits + * \ref NPSS_INTR_MASK_CLR_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssIntrUnMask(uint32_t mask) +{ + NPSS_INTR_MASK_CLR_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_NpssIntrMask(uint32_t mask) + * @brief This API is used to mask the NPSS interrupts + * @param[in] mask is OR'ed value of the NPSS interrupt bits + * \ref NPSS_INTR_MASK_SET_REG + * @return none + */ +STATIC INLINE void RSI_PS_NpssIntrMask(uint32_t mask) +{ + NPSS_INTR_MASK_SET_REG = mask; +} + +/** + * @fn STATIC INLINE void RSI_PS_EnableLpSleep(boolean_t lpSleep) + * @brief This API is used to enable/disable the lp sleep mode + * @param[in] lpSleep 1:enable lp sleep , 0 : disable lp sleep + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b + * @return none + */ +STATIC INLINE void RSI_PS_EnableLpSleep(boolean_t lpSleep) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.LP_SLEEP_MODE_b = (unsigned int)(lpSleep & 0x1); +} + +/** + *@fn STATIC INLINE void RSI_PS_SkipXtalWaitTime(boolean_t val) + *@brief This API is used to skip the XTAL wait time + *@param[in] val 1: skip XTAL wait time + * 0 Do not skip XTAL wait time + * \ref MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b + * @return none + */ +STATIC INLINE void RSI_PS_SkipXtalWaitTime(boolean_t val) +{ + /*if package_type value is 5(M7DB) then don't skip xtal wait time */ + if (package_type != 0x5) { + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE_b.SKIP_XTAL_WAIT_TIME = (unsigned int)(val & 0x1); + } +} +/** + *@fn STATIC INLINE void RSI_PS_UlpToDcDcMode(void) + *@brief This API is configures SC-DCDC from LDO to DCDC Mode + * @return none + */ +STATIC INLINE void RSI_PS_UlpToDcDcMode(void) +{ + ULP_SPI_MEM_MAP(0x126) = 0x3E002F; + ULP_SPI_MEM_MAP(0x128) = 0x200020; +} + +/** + *@fn STATIC INLINE void RSI_PS_LatchCntrlSet(uint32_t val) + *@brief This API is used to set the latch configurations + * @return none + */ +STATIC INLINE void RSI_PS_LatchCntrlSet(uint32_t val) +{ + ULP_SPI_MEM_MAP(SELECT_BG_CLK) |= val; +} + +/** + *@fn STATIC INLINE void RSI_PS_LatchCntrlClr(uint32_t val) + *@brief This API is used to clear the latch configurations + * @return none + */ +STATIC INLINE void RSI_PS_LatchCntrlClr(uint32_t val) +{ + ULP_SPI_MEM_MAP(SELECT_BG_CLK) &= ~val; +} + +/** + *@fn STATIC INLINE void RSI_PS_BodPwrGateButtonCalibEnable(void) + *@brief This API is used to enable the power-gate enable signal for button calib and vbatt status checking block + * @return none + */ +STATIC INLINE void RSI_PS_BodPwrGateButtonCalibEnable(void) +{ + ULP_SPI_MEM_MAP(0x1E3) |= (BIT(15)); +} + +/** + *@fn STATIC INLINE void RSI_PS_BodPwrGateButtonCalibDisable(void) + *@brief This API is used to disable the power-gate enable signal for button calib and vbatt status checking block + * @return none + */ +STATIC INLINE void RSI_PS_BodPwrGateButtonCalibDisable(void) +{ + ULP_SPI_MEM_MAP(0x1E3) &= ~(BIT(15)); +} + +/** + *@fn STATIC INLINE void RSI_PS_XtalEnable(void) + *@brief This API is used to enable the XTAL + *@return none + */ +STATIC INLINE void RSI_PS_XtalEnable(void) +{ + *(volatile uint32_t *)0x41300480 |= (BIT(10)); +} + +/** + *@fn STATIC INLINE void RSI_PS_XtalDisable(void) + *@brief This API is used to disable the XTAL + *@return none + */ +STATIC INLINE void RSI_PS_XtalDisable(void) +{ + *(volatile uint32_t *)0x41300480 &= ~(BIT(10)); +} + +/** + *@fn STATIC INLINE void RSI_PS_QspiDllDomainEnable(void) + *@brief This API is used to enable the power to the QSPI-DLL module + *@return none + */ +STATIC INLINE void RSI_PS_QspiDllDomainEnable(void) +{ + *(volatile uint32_t *)0x24048484 |= (BIT(2) | BIT(6)); +} + +/** + *@fn STATIC INLINE void RSI_PS_QspiDllDomainDisable(void) + *@brief This API is used to disable the power to the QSPI-DLL module + *@return none + */ +STATIC INLINE void RSI_PS_QspiDllDomainDisable(void) +{ + *(volatile uint32_t *)0x24048484 &= ~(BIT(2) | BIT(6)); +} + +/** + *@fn STATIC INLINE void RSI_PS_LdoSocDefaultModeEnable(void) + *@brief This API is used to enable the SOC LDO default mode (Set high for 1.1 V (default mode)) + *@return none + */ +STATIC INLINE void RSI_PS_LdoSocDefaultModeEnable(void) +{ + PMU_SPI_MEM_MAP(0x1D6) |= (BIT(5)); +} + +/** + *@fn STATIC INLINE void RSI_PS_LdoSocDefaultModeDisable(void) + *@brief This API is used to disable the SOC LDO default mode + *@return none + */ +STATIC INLINE void RSI_PS_LdoSocDefaultModeDisable(void) +{ + PMU_SPI_MEM_MAP(0x1D6) &= ~(BIT(5)); +} + +/** + *@fn void RSI_PS_BypassLdoRfEnable(void) + *@brief This API is used to enable bypass of LDO-RF enable and control bits to control from outside + *@return none + */ +STATIC INLINE void RSI_PS_BypassLdoRfEnable(void) +{ + PMU_SPI_MEM_MAP(0x1D8) |= BIT(2); +} + +/** + *@fn STATIC INLINE void RSI_PS_FlashLdoEnable(void) + *@brief This API is used to flash LDO enable. + *@return none + */ +STATIC INLINE void RSI_PS_FlashLdoEnable(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_SET = BIT(0); +} + +/** + *@fn STATIC INLINE void RSI_PS_FlashLdoDisable(void) + *@brief This API is used to disable flash LDO. + *@return none + */ +STATIC INLINE void RSI_PS_FlashLdoDisable(void) +{ + BATT_FF->MCU_PMU_LDO_CTRL_CLEAR = BIT(0); +} + +/** + *@fn void RSI_PS_BypassLdoRfDisable(void) + *@brief This API is used to disable bypass of LDO-RF enable and control bits to control from outside(i.e internal logic) + *@return none + */ +STATIC INLINE void RSI_PS_BypassLdoRfDisable(void) +{ + PMU_SPI_MEM_MAP(0x1D8) &= ~BIT(2); +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllSpiDisable(void) + *@brief This API is used to disable the Soc-PLL SPI PG + *@return none + */ +STATIC INLINE void RSI_PS_SocPllSpiDisable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_SPI_PG_EN = 0U; +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllVddIsoEnable(void) + *@brief This API is used to enable the Soc-PLL ISO VDD + *@return none + */ +STATIC INLINE void RSI_PS_SocPllVddIsoEnable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_ISO_ENABLE = 1U; +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllVddIsoDiable(void) + *@brief This API is used to disable the Soc-PLL ISO VDD + *@return none + */ +STATIC INLINE void RSI_PS_SocPllVddIsoDiable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_ISO_ENABLE = 0U; +} + +/** + *@fn STATIC INLINE void RSI_PS_SocPllSpiEnable(void) + *@brief This API is used to enable the Soc-PLL SPI PG + *@return none + */ +STATIC INLINE void RSI_PS_SocPllSpiEnable(void) +{ + BATT_FF->PLLCCI_PWRCTRL_REG_b.SOCPLL_SPI_PG_EN = 1U; +} + +/** + *@fn STATIC INLINE void RSI_ConfigBuckBoost(uint8_t cntrl , uint8_t enable) + *@brief This API is used to control the buck boost + *@param[in] cntrl 0: Software controlled 1: Hardware controlled. + *@param[in] enable 0: Disabled if controlled by software(cntrl = 0) 1: Enabled if controlled by software(cntrl = 1) + *@return none + */ +STATIC INLINE void RSI_ConfigBuckBoost(uint8_t cntrl, uint8_t enable) +{ + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_BUCK_BOOST_ENABLE_BYPASS = (unsigned int)((enable & 0x1) & 0x01); + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_BUCK_BOOST_ENABLE_BYPASS_CTRL = (unsigned int)((cntrl & 0x1) & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_ConfigPmuShutDown(uint8_t cntrl , uint8_t enable) + *@brief This API is used to control the pmu shut down mode + *@param[in] cntrl 0: Software controlled 1: Hardware controlled. + *@param[in] enable 0: Disabled if controlled by software(cntrl = 0) 1: Enabled if controlled by software(cntrl = 1) + *@return none + */ +STATIC INLINE void RSI_ConfigPmuShutDown(uint8_t cntrl, uint8_t enable) +{ + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_PMU_SHUT_DOWN_BYPASS = (unsigned int)((enable & 0x1) & 0x01); + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_PMU_SHUT_DOWN_BYPASS_CTRL = (unsigned int)((cntrl & 0x1) & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_ChangeTassRefClock(void) + *@brief This API is used to change the TASS reference clock to MHz RC , This API is used only in MCU mode , should not be used in WiSeMCU mode. + *@return none + */ +STATIC INLINE void RSI_ChangeTassRefClock(void) +{ + *(volatile uint32_t *)0x41300110 = (1 << 23) | (1 << 16) | (1 << 4) | 1; +} + +/** + *@fn STATIC INLINE void RSI_SetRegSpiDivision(uint8_t div) + *@brief This API is used to change the reg access SPI clock division factor. + *@return none + */ +STATIC INLINE void RSI_SetRegSpiDivision(uint8_t div) +{ + *(volatile uint32_t *)(REG_SPI_BASE_ADDR_ULP + 0x00) &= ~0xF; + *(volatile uint32_t *)(REG_SPI_BASE_ADDR_ULP + 0x00) |= div; +} + +/** + *@fn STATIC INLINE void RSI_ConfigXtal(uint8_t cntrl , uint8_t enable) + *@brief This API is used to control the Xtal + *@param[in] cntrl 0: Software controlled 1: Hardware controlled. + *@param[in] enable 0: Disabled if controlled by software(cntrl = 0) 1: Enabled if controlled by software(cntrl = 1) + *@return none + */ +STATIC INLINE void RSI_ConfigXtal(uint8_t cntrl, uint8_t enable) +{ + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_XTAL_EN_40MHZ_BYPASS = (unsigned int)((enable & 0x1) & 0x01); + BATT_FF->MCU_FSM_CTRL_BYPASS_b.MCU_XTAL_EN_40MHZ_BYPASS_CTRL = (unsigned int)((cntrl & 0x1) & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_PS_PmuUltraSleepConfig(boolean_t en) + *@brief This API is used to enable the 'NPSS_PMU_STANDBY' + *@param[in] en 1: enable the 'NPSS_PMU_STANDBY' + * en 0: disable the 'NPSS_PMU_STANDBY' + *@return none + */ +STATIC INLINE void RSI_PS_PmuUltraSleepConfig(boolean_t en) +{ + MCU_FSM->MCU_FSM_PMU_STATUS_REG_b.STANDBY_DC1P3_R = (unsigned int)(en & 0x01); +} + +/** + *@fn STATIC INLINE void RSI_PS_PmuSetConfig(uint32_t mask) + *@brief This API is used to enable/set the PMU status + *@param[in] mask : Ored values of PMU status bits + * \n Following are the possible parameters for this parameter + * \n PMU_STS_DCDC_ON + * \n PMU_STS_FLASH_LDO_ON + * \n PMU_STS_SOC_LDO_ON + *@return none + */ +STATIC INLINE void RSI_PS_PmuSetConfig(uint32_t mask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE |= mask; +} + +/** + *@fn STATIC INLINE void RSI_PS_PmuClrConfig(uint32_t mask) + *@brief This API is used to disable/clear the PMU status + *@param[in] mask : Ored values of PMU status bits + * \n Following are the possible parameters for this parameter + * \n PMU_STS_DCDC_ON + * \n PMU_STS_FLASH_LDO_ON + * \n PMU_STS_SOC_LDO_ON + *@return none + */ +STATIC INLINE void RSI_PS_PmuClrConfig(uint32_t mask) +{ + MCU_FSM->MCU_FSM_SLEEP_CTRLS_AND_WAKEUP_MODE &= ~mask; +} + +/** + *@fn void RSI_PS_AnalogPeriPtatEnable(void) + *@brief This API is used to enable the ptat currents to analog peripherals + * @return execution status + */ +STATIC INLINE uint32_t RSI_PS_AnalogPeriPtatEnable(void) +{ + return RSI_IPMU_ProgramConfigData(ana_perif_ptat_common_config1); +} + +/** + *@fn void RSI_PS_AnalogPeriPtatDisable(void) + *@brief This API is used to disable the ptat currents to analog peripherals + *@return execution status + */ +STATIC INLINE uint32_t RSI_PS_AnalogPeriPtatDisable(void) +{ + return RSI_IPMU_ProgramConfigData(ana_perif_ptat_common_config2); +} + +/** + *@fn void RSI_PS_BodClksPtatEnable(void) + *@brief This API is used to enable the ptat currents to clocks and bod(cmp_npss) + *@return execution status + */ +STATIC INLINE uint32_t RSI_PS_BodClksPtatEnable(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config1); +} + +/** + *@fn void RSI_PS_BodClksPtatDisable(void) + *@brief This API is used to disable the ptat currents to clocks and bod(cmp_npss) + *@return execution status + */ +STATIC INLINE uint32_t RSI_PS_BodClksPtatDisable(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config2); +} + +/** + *@fn void RSI_PS_PS4SetRegisters(void) + *@brief This API is used configure the registers for clock more than 120 MHz in PS4 + *@return none + */ +STATIC INLINE void RSI_PS_PS4SetRegisters(void) +{ + // Configure the prefetch and registering when SOC clock is more than 120 MHz + ICACHE2_ADDR_TRANSLATE_1_REG = BIT(21); // Icache registering when clock frequency is more than 120 MHz + // When set, enables registering in M4-NWP AHB2AHB. This will have performance penalty. This has to be set above 100 MHz + MISC_CFG_SRAM_REDUNDANCY_CTRL = BIT(4); + MISC_CONFIG_MISC_CTRL1 |= BIT(4); // Enable Register ROM as clock frequency is 200 MHz +} + +/** + *@fn void RSI_PS_PS4ClearRegisters(void) + *@brief This API is used to clear the MISC registers for clock less than 120 MHz for core + *@return none + */ +STATIC INLINE void RSI_PS_PS4ClearRegisters(void) +{ + // Clears the prefetch and registering when SOC clock is less than 120 MHz + ICACHE2_ADDR_TRANSLATE_1_REG &= ~BIT(21); // Clearing Icache registering when clock frequency is less than 120 MHz + // When set, enables registering in M4-NWP AHB2AHB. This will have performance penalty. This has to be set above 100 MHz + MISC_CFG_SRAM_REDUNDANCY_CTRL &= ~BIT(4); + MISC_CONFIG_MISC_CTRL1 &= ~BIT(4); // Disable Register ROM as clock frequency is less than 120 MHz +} + +/** + *@fn void RSI_PS_PS2UpdateClockVariable(void) + *@brief This API is used update the global clock variable after clock setting in PS2 + *@return none + */ +STATIC INLINE void RSI_PS_PS2UpdateClockVariable(void) +{ + // Updates the system clock. + system_clocks.rc_mhz_clock = 20000000; + // Updating the systemcoreclock variable. + SystemCoreClock = 20000000; +} + +/** + *@fn void RSI_PS_WakeupTAandProgramFlash(void) + *@brief This API is used wakeup the NWP and program the flash + *@return none + */ +STATIC INLINE void RSI_PS_WakeupTAandProgramFlash(void) +{ + if (!(P2P_STATUS_REGISTER & BIT(3))) { + //!wakeup NWP + P2P_STATUS_REGISTER |= BIT(0); + //!wait for NWP active + while (!(P2P_STATUS_REGISTER & BIT(3))) + ; + } + //! Request NWP to program flash + //! raise an interrupt to NWP register + M4SS_P2P_INTR_SET_REGISTER = BIT(4); + P2P_STATUS_REGISTER = BIT(0); + + while (!(P2P_STATUS_REGISTER & BIT(3))) + ; +} + +/** + *@fn void RSI_PS_SetMCUActiveStatus(void) + *@brief This API is used set the active status of mcu after wakeup + *@return none + */ +STATIC INLINE void RSI_PS_SetMCUActiveStatus(void) +{ + P2P_STATUS_REGISTER = BIT(1); +} + +/** + *@fn void RSI_PS_IsPS2State(void) + *@brief This API is used to check is current state is PS2 or not + *@return true if PS2 state false if not + */ +STATIC INLINE boolean_t RSI_PS_IsPS2State(void) +{ + return (M4_ULP_SLP_STATUS_REG & ULP_MODE_SWITCHED_NPSS); +} + +/** @} */ + +/* @} end of RSI_POWER_SAVE */ + +void ps_clr_wkp_up_status(uint32_t wakeUpIntrClear); + +void ps_bg_ldo_config(uint8_t ldo_0p6_ctrl, uint8_t ldo_0p6_lp_mode); + +void ps_configure_trim_values(uint16_t lf_ro_trim, + uint16_t lf_rc_trim, + uint16_t hf_ro_trim, + uint16_t hf_rc_trim, + uint16_t bg_ptat_trim, + uint16_t bg_trim); + +void ps_wireless_shutdown(void); + +/*End of file not truncated*/ +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_POWER_SAVE_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h new file mode 100644 index 000000000..f4e3b048f --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_processor_sensor.h @@ -0,0 +1,63 @@ +/******************************************************************************* +* @file rsi_processor_sensor.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_PROCESSOR_SENSOR_H__ +#define __RSI_PROCESSOR_SENSOR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_PROCESSOR_SENSOR RSI:RS1xxxx PROCESSOR_SENSOR + * @{ + * + */ +#include "rsi_ccp_common.h" + +rsi_error_t RSI_ProSense_Enable(MCU_ProcessSensor_Type *pstcProcessSensor, boolean_t bEN); +uint32_t RSI_ProSense_Read(MCU_ProcessSensor_Type *pstcProcessSensor); +uint32_t RSI_ProSense_GetNumCycles(MCU_ProcessSensor_Type *pstcProcessSensor); +rsi_error_t RSI_ProSense_ClkEnable(MCU_ProcessSensor_Type *pstcProcessSensor, boolean_t bEN); +rsi_error_t RSI_ProSense_RingClkStart(MCU_ProcessSensor_Type *pstcProcessSensor, boolean_t bEN); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /*__RSI_PROCESSOR_SENSOR_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h new file mode 100644 index 000000000..0765a49c4 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_reg_spi.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* @file rsi_reg_spi.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_REG_SPI_H__ +#define __RSI_REG_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \cond HIDDEN_SYMBOLS + */ + +#define REG_SPI_BASE_ADDR_ULP 0x24050000 +#define REG_SPI_BASE_ADDR_PLL 0x46180000 +#define TASS_AFE_REG_ACC_MEM_MAP_BASE_ADDR 0x41138000 + +#include "rsi_ccp_common.h" + +/*Register memory mapped reg read write*/ + +/*REG ADDRESS : Address of a target register ULP*/ +#define ULP_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(REG_SPI_BASE_ADDR_ULP + (0xa000 + (REG_ADR * 4))))) + +/*REG ADDRESS : Address of a target register PMU*/ +#define PMU_SPI_MEM_MAP(REG_ADR) (*((uint32_t volatile *)(REG_SPI_BASE_ADDR_ULP + (0x00008000 + (REG_ADR * 4))))) + +/*Memory mapped SPI for M4 PLL configuration */ +#define SPI_MEM_MAP_PLL(REG_ADR) (*((uint16_t volatile *)(REG_SPI_BASE_ADDR_PLL + 0x00008000 + (REG_ADR << 2)))) + +/*Memory mapped SPI for PLL_480 configuration */ +#define TASS_PLL_CTRL_SET_REG(REG_ADR) (*((uint16_t volatile *)(TASS_AFE_REG_ACC_MEM_MAP_BASE_ADDR + (REG_ADR << 2)))) + +/*Configuration parameters*/ +#define GSPI_RF_N_ULP BIT(12) +#define GSPI_ACTIVE BIT(8) +#define GSPI_TRIG BIT(7) +#define GSPI_READ BIT(6) +#define GSPI_DATA_FIFO GSPI_DATA_REG0 +#define READ_INDICATION BIT(15) +#define ADDR_DATA_LEN 31 + +/*GSPI Configuration*/ +typedef struct stc_reg_spi_config { + uint16_t u16GspiClockRatio; + uint16_t u16GspiCsbSetupTime; + uint16_t u16GspiCsbHoldTime; + uint16_t u16GspiCsbHighTime; + boolean_t bGspiSpiMode; + boolean_t bGspiClockPhase; + boolean_t bGspiAfeIpmun; + boolean_t bDmaMode; + boolean_t bDma32_48Bitn; +} stc_reg_spi_config_t; + +/*Target selection*/ +typedef enum en_select_target { PmuBlock = 0, UlpBlock = 1 } en_select_target_t; + +/*Base address assignment */ +#define REG_SPI_ULP (*((REG_SPI_Type_T *)REG_SPI_BASE_ADDR_ULP)) /*Memory map for ULPSS Reg access SPI*/ +#define REG_SPI_PLL (*((REG_SPI_Type_T *)REG_SPI_BASE_ADDR_PLL)) /*Memory map for ULPSS Reg access SPI*/ + +/** + * \endcond + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__RSI_REG_SPI_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h new file mode 100644 index 000000000..f99ff2630 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_retention.h @@ -0,0 +1,326 @@ +/******************************************************************************* +* @file rsi_retention.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_RETENTION_H__ +#define __RSI_RETENTION_H__ +#include "rsi_ccp_common.h" +#include "rsi_power_save.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*NPSS GPIO PIN MUX VALEUS*/ +#define NPSS_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x14)) +#define NPSS_GPIO_CONFIG_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x10)) +#define NPSS_GPIO_CONFIG_CLR_REG (*(volatile uint32_t *)(NPSS_INTR_BASE + 0x8)) + +/*NPSS GPIO PIN MUX VALEUS*/ +#define NPSSGPIO_PIN_MUX_MODE0 0 +#define NPSSGPIO_PIN_MUX_MODE1 1 +#define NPSSGPIO_PIN_MUX_MODE2 2 +#define NPSSGPIO_PIN_MUX_MODE3 3 +#define NPSSGPIO_PIN_MUX_MODE4 4 +#define NPSSGPIO_PIN_MUX_MODE5 5 +#define NPSSGPIO_PIN_MUX_MODE6 6 +#define NPSSGPIO_PIN_MUX_MODE7 7 +/*@note : Please refer to pin MUX excel to configure in desired mode + * */ +/*EDGE INTERRUPT MODE */ +#define RISING_EDGE 0 +#define FALLING_EDGE 1 +#define BOTH_FALL_RISE_EDGE 3 + +/*NPSS GPIO pin interrupt edge configuration */ +#define NPSS_INTR_RISING_EDGE 1 +#define NPSS_INTR_FALLING_EDGE 0 + +/*NPSS GPIO pin direction */ +#define NPSS_GPIO_DIR_INPUT 1 +#define NPSS_GPIO_DIR_OUTPUT 0 + +/*NPSS GPIO pin interrupt levels*/ +#define NPSS_GPIO_INTR_HIGH 1 +#define NPSS_GPIO_INTR_LOW 0 + +/*NPSS GPIO pin defines */ +#define NPSS_GPIO_0 0 +#define NPSS_GPIO_1 1 +#define NPSS_GPIO_2 2 +#define NPSS_GPIO_3 3 +#define NPSS_GPIO_4 4 + +/*NPSS GPIO Interrupt defines */ +#define NPSS_GPIO_0_INTR BIT(0) +#define NPSS_GPIO_1_INTR BIT(1) +#define NPSS_GPIO_2_INTR BIT(2) +#define NPSS_GPIO_3_INTR BIT(3) +#define NPSS_GPIO_4_INTR BIT(4) + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_NPSSGPIO RSI:RS1xxxx NPSSGPIO + * @{ + * + */ + +/** +* @brief This API is used to set the NPSS GPIO pin MUX (mode) + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] mux : is NPSS GPIO MUX value + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_SetPinMux(uint8_t pin, uint8_t mux) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = (unsigned int)(mux & 0x07); +} + +/** + * @fn void RSI_NPSSGPIO_InputBufferEn(uint8_t pin , boolean_t enable) +* @brief This API is used to enable/disable NPSS GPIO input buffer + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] enable: is enable / disable NPSS GPIO input buffer + * 1- Enable + * 0- Disable + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_InputBufferEn(uint8_t pin, boolean_t enable) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = (unsigned int)(enable & 0x01); +} + +/** + * @brief This API is used to set the direction of the NPSS GPIO + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] dir: is direction value (Input / Output) + * 1- Input Direction + * 0- Output Direction + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_SetDir(uint8_t pin, boolean_t dir) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = (unsigned int)(dir & 0x01); +} + +/** + * @brief This API is used to Get the direction of the NPSS GPIO + *@param[in] pin: is NPSS GPIO pin number (0...4) + * @return : returns the GPIO pin direction + * */ +STATIC INLINE boolean_t RSI_NPSSGPIO_GetDir(uint8_t pin) +{ + return MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN; +} + +/** + * @brief This API is used to set the NPSS GPIO pin value + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] val: is NPSS GPIO pin value 0 or 1 + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetPin(uint8_t pin, boolean_t val) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = (unsigned int)(val & 0x01); +} + +/** + * @brief This API is used to Get the NPSS GPIO pin value + *@param[in] pin: is NPSS GPIO pin number (0...4) + * @return returns the pin logical state of pin + */ +STATIC INLINE boolean_t RSI_NPSSGPIO_GetPin(uint8_t pin) +{ + return (NPSS_GPIO_STATUS >> pin) & 0x01; +} + +/** +* @brief This API is used to select NPSS GPIO wake up detection when in sleep + *@param[in] pin: is NPSS GPIO pin number (0...4) + *@param[in] level :Gpio polarity to wake up from sleep + * 1 - When signal is High + * 0 - When signal is Low + *@return : none + * */ +STATIC INLINE void RSI_NPSSGPIO_SetPolarity(uint8_t pin, boolean_t level) +{ + MCU_RET->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = (unsigned int)(level & 0x01); +} + +/** + * @brief This API is used to set the GPIO to wake from deep sleep + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetWkpGpio(uint8_t npssGpioPinIntr) +{ + MCU_FSM->GPIO_WAKEUP_REGISTER |= npssGpioPinIntr; +} + +/** + * @brief This API is used to clear the GPIO to wake from deep sleep + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrWkpGpio(uint8_t npssGpioPinIntr) +{ + MCU_FSM->GPIO_WAKEUP_REGISTER &= ~npssGpioPinIntr; +} + +/** + * @brief This API is used to mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_IntrMask(uint8_t npssGpioPinIntr) +{ + NPSS_INTR_MASK_SET_REG = (npssGpioPinIntr << 1); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_IntrUnMask(uint8_t npssGpioPinIntr) +{ + NPSS_INTR_MASK_CLR_REG = (npssGpioPinIntr << 1); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntFallEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 8); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntFallEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 8)); +} + +/** + * @brief This API is used to Set the rise edge interrupt detection for NPSS GPIO + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntRiseEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 0); +} + +/** + * @brief This API is used to Enable rise edge interrupt detection for NPSS GPIO + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntRiseEdgeEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 0)); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntLevelHighEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 24); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntLevelHighEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 24)); +} + +/** + * @brief This API is used to un mask the NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_SetIntLevelLowEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG |= (npssGpioPinIntr << 16); +} + +/** + * @brief This API is used clear the interrupt low level enable + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntLevelLowEnable(uint8_t npssGpioPinIntr) +{ + NPSS_GPIO_CONFIG_REG &= (uint32_t)(~(npssGpioPinIntr << 16)); +} + +/** + * @brief This API is used to clear NPSS GPIO interrupt + * @param[in] npssGpioPinIntr: OR'ed values of the NPSS GPIO interrupts + * @return none + */ +STATIC INLINE void RSI_NPSSGPIO_ClrIntr(uint8_t npssGpioPinIntr) +{ + NPSS_INTR_CLEAR_REG = (npssGpioPinIntr << 1); +} + +/** + * @brief This API is used to get the NPSS GPIO interrupt status + * @return returns the GPIO status + */ +STATIC INLINE uint8_t RSI_NPSSGPIO_GetIntrStatus(void) +{ + return (NPSS_INTR_STATUS_REG >> 1) & 0x1F; +} +/* + *@} + */ + +#ifdef __cplusplus +} +#endif + +/*End of file not truncated*/ +#endif /*__RSI_RETENTION_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h new file mode 100644 index 000000000..8b5abc194 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_temp_sensor.h @@ -0,0 +1,81 @@ +/******************************************************************************* +* @file rsi_temp_sensor.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_TEMP_SENSOR_H__ +#define __RSI_TEMP_SENSOR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_TEMP_SENSORS RSI:RS1xxxx TS + * @brief + * @{ + * + */ +#include "rsi_ccp_common.h" + +void RSI_TS_SetCntFreez(MCU_TEMP_Type *pstcTempSens, uint32_t u32CountFreez); +void RSI_TS_RefClkSel(MCU_TEMP_Type *pstcTempSens, boolean_t bRefClk); +void RSI_TS_Enable(MCU_TEMP_Type *pstcTempSens, boolean_t bEn); + +/** + * @} + */ +void RSI_TS_Config(MCU_TEMP_Type *pstcTempSens, uint32_t u32Nomial); +/** + * \ingroup RSI_SPECIFIC_DRIVERS + * \defgroup RSI_TEMP_SENSORS RSI:RS1xxxx TEMPERARTURE SENSOR + * @brief + * @{ + * + */ +uint32_t RSI_TS_ReadTemp(const MCU_TEMP_Type *pstcTempSens); +uint32_t RSI_TS_GetRefClkCnt(const MCU_TEMP_Type *pstcTempSens); +uint32_t RSI_TS_GetPtatClkCnt(const MCU_TEMP_Type *pstcTempSens); +void RSI_TS_LoadBjt(MCU_TEMP_Type *pstcTempSens, uint8_t temp); +void RSI_TS_RoBjtEnable(MCU_TEMP_Type *pstcTempSens, boolean_t enable); +void RSI_Periodic_TempUpdate(TIME_PERIOD_Type *temp, uint8_t enable, uint8_t trigger_time); + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +/*End of file not truncated */ +#endif /**__RSI_TEMP_SENSOR_H__*/ + +/* @}end of group RSI_TEMP_SENSORS */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h new file mode 100644 index 000000000..6150aba57 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_time_period.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* @file rsi_time_period.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_TIME_PERIOD_H__ +#define __RSI_TIME_PERIOD_H__ +#include "rsi_ccp_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +rsi_error_t RSI_TIMEPERIOD_TimerClkSel(TIME_PERIOD_Type *pstcTimePeriod, uint32_t u32TimePeriod); +rsi_error_t RSI_TIMEPERIOD_RCCalibration(TIME_PERIOD_Type *pstcTimePeriod, + uint32_t u32TimePeriodRefClk, + uint32_t u32XtalSettle, + uint16_t u16RcClkCnt, + boolean_t bPeriodicCalibEn, + uint8_t u8PeriodicCalibRate, + boolean_t bTemperatureCalibEn, + uint8_t u8TemperatureVal, + uint8_t u8AverageFactor); +uint32_t RSI_TIMEPERIOD_RCCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod); +uint32_t RSI_TIMEPERIOD_ROCalibTimePeriodRead(const TIME_PERIOD_Type *pstcTimePeriod); +rsi_error_t RSI_TIMEPERIOD_XTAL32KHzCalibration(TIME_PERIOD_Type *pstcTimePeriod, + uint32_t u32TimePeriodRefClk, + uint32_t u32XtalSettle, + uint16_t u16RcClkCnt, + boolean_t bPeriodicCalibEn, + uint8_t u8PeriodicCalibRate, + boolean_t bTemperatureCalibEn, + uint8_t u8TemperatureVal, + uint8_t u8AverageFactor); +rsi_error_t RSI_TIMEPERIOD_ROCalibration(TIME_PERIOD_Type *pstcTimePeriod, + uint8_t u8RefClkSrc, + uint32_t u32XtalSettle, + uint16_t u16RoClkCnt, + boolean_t bPeriodicCalibEn, + uint8_t u8PeriodicCalibRate, + uint8_t u8AverageFactor + +); +rsi_error_t RSI_TIMEPERIOD_LowPwrTrigSelEn(TIME_PERIOD_Type *pstcTimePeriod, boolean_t bEn); +rsi_error_t RSI_TIMEPERIOD_VbatTrigSel(TIME_PERIOD_Type *pstcTimePeriod, uint8_t u8Time); + +#ifdef __cplusplus +} +#endif + +/*End of file not truncated*/ +#endif /*__RSI_TIME_PERIOD_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h new file mode 100644 index 000000000..8b24b1b41 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_ulpss_clk.h @@ -0,0 +1,359 @@ +/******************************************************************************* +* @file rsi_ulpss_clk.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ + +#ifndef __RSI_ULPSS_CLK_H__ +#define __RSI_ULPSS_CLK_H__ + +#include "rsi_ccp_common.h" +#include "rsi_error.h" +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" +#include "rsi_power_save.h" + +/*requied delays for turn on the clocks in micro seconds*/ +#define MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 40MHZ CLK*/ +#define MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP DOUBLER CLK*/ +#define MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY 10 /* delay to enable the ULP 20MHZ_RING_OSC CLK*/ +#define MCU_ULP_MHZ_RC_CLK_EN_TRUN_ON_DELAY 2 /* delay to enable the ULP MHZ_RC CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1 500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2 1500 /* delay to enable the ULP 32KHZ_XTAL CLK*/ +#define MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY 250 /* delay to enable the ULP 32KHZ_RO CLK*/ +#define MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY 150 /* delay to enable the ULP 32KHZ_RC CLK*/ + +/*Clock enable Bits */ +#define TOUCH_SENSOR_PCLK_ENABLE BIT(31) /* Enables TOUCH_SENSOR_PCLK_ENABLE */ +#define FIM_AHB_CLK_ENABLE BIT(30) /* Enables FIM_AHB_CLK_ENABLE */ +#define ULPSS_TASS_QUASI_SYNC BIT(27) /* Enables ULPSS_TASS_QUASI_SYNC */ +#define ULPSS_M4SS_SLV_SEL BIT(26) /* Enables ULPSS_M4SS_SLV_SEL */ +#define AUX_SOC_EXT_TRIG_2_SEL BIT(25) /* Enables TOUCH_SENSOR_PCLK_ENABLE */ +#define AUX_SOC_EXT_TRIG_1_SEL BIT(24) /* Enables AUX_SOC_EXT_TRIG_1_SEL */ +#define AUX_ULP_EXT_TRIG_2_SEL BIT(23) /* Enables AUX_ULP_EXT_TRIG_2_SEL */ +#define AUX_ULP_EXT_TRIG_1_SEL BIT(22) /* Enables AUX_ULP_EXT_TRIG_1_SEL */ +#define TIMER_PCLK_EN BIT(21) /* Enables TIMER_PCLK_EN */ +#define EGPIO_PCLK_EN BIT(20) /* Enables EGPIO_PCLK_EN */ +#define EGPIO_PCLK_DYN_CTRL_DISABLE_ULP BIT(19) /* Enables EGPIO_PCLK_DYN_CTRL_DISABLE_ULP */ +#define CLK_ENABLE_ULP_MEMORIES BIT(18) /* Enables CLK_ENABLE_ULP_MEMORIES */ +#define VAD_CLK_EN BIT(17) /* Enables VAD_CLK_EN */ +#define FIM_CLK_EN BIT(16) /* Enables FIM_CLK_EN */ +#define REG_ACCESS_SPI_CLK_EN BIT(15) /* Enables REG_ACCESS_SPI_CLK_EN */ +#define EGPIO_CLK_EN BIT(14) /* Enables EGPIO_CLK_EN */ +#define CLK_ENABLE_TIMER BIT(13) /* Enables CLK_ENABLE_TIMER */ +#define VAD_PCLK_ENABLE BIT(12) /* Enables VAD_PCLK_ENABLE */ +#define FIM_PCLK_ENABLE BIT(11) /* Enables FIM_PCLK_ENABLE */ +#define SCLK_ENABLE_UART BIT(10) /* Enables SCLK_ENABLE_UART */ +#define PCLK_ENABLE_UART BIT(9) /* Enables PCLK_ENABLE_UART */ +#define SCLK_ENABLE_SSI_MASTER BIT(8) /* Enables SCLK_ENABLE_SSI_MASTER */ +#define PCLK_ENABLE_SSI_MASTER BIT(7) /* Enables PCLK_ENABLE_SSI_MASTER */ +#define CLK_ENABLE_I2S BIT(6) /* Enables CLK_ENABLE_I2S */ +#define PCLK_ENABLE_I2C BIT(5) /* Enables PCLK_ENABLE_I2C */ +#define IR_PCLK_EN BIT(4) /* Enables IR_PCLK_EN */ +#define PCM_FSYNC_START BIT(1) /* Enables PCM_FSYNC_START */ +#define PCM_ENABLE BIT(0) /* Enables PCM_ENABLE */ + +#define I2C_PCLK_DYN_CTRL_DISABLE BIT(0) /* Enables PCM_ENABLE */ +#define I2S_CLK_DYN_CTRL_DISABLE BIT(1) +#define ULP_SSI_MST_PCLK_DYN_CTRL_DISABLE BIT(2) +#define ULP_SSI_MST_SCLK_DYN_CTRL_DISABLE BIT(3) +#define UART_CLK_DYN_CTRL_DISABLE BIT(4) +#define UART_SCLK_DYN_CTRL_DISABLE BIT(5) +#define ULP_TIMER_PCLK_DYN_CTRL_DISABLE BIT(6) +#define ULP_TIMER_SCLK_DYN_CTRL_DISABLE BIT(7) +#define REG_ACCESS_SPI_CLK_DYN_CTRL_DISABLE BIT(8) +#define FIM_CLK_DYN_CTRL_DISABLE BIT(9) +#define VAD_CLK_DYN_CTRL_DISABLE BIT(10) +#define AUX_PCLK_EN BIT(11) +#define AUX_CLK_EN BIT(12) +#define AUX_MEM_EN BIT(13) +#define AUX_PCLK_DYN_CTRL_DISABLE BIT(14) +#define AUX_CLK_DYN_CTRL_DISABLE BIT(15) +#define AUX_CLK_MEM_DYN_CTRL_DISABLE BIT(16) +#define UDMA_CLK_ENABLE BIT(17) +#define IR_CLK_ENABLE BIT(18) +#define IR_CLK_DYN_CTRL_DISABLE BIT(19) + +/*ULP PROCESSOR CLOCK */ +#define ULP_PROC_MAX_SEL 7 /* Maximum Seletion value for ulp processor clock source*/ +#define ULP_PROC_MIN_SEL 0 /* Minimum Seletion value for ulp processor clock source*/ +#define ULP_PROC_MAX_DIVISOIN_FACTOR 255 /* Maximum division factor value for ulp processor clock*/ +#define ULP_PROC_MIN_DIVISOIN_FACTOR 0 /* Minimum division factor value for ulp processor clock*/ + +/*ULP SSI CLOCK*/ +#define ULP_SSI_MAX_SEL 6 /* Maximum Seletion value for ulp SSI clock source*/ +#define ULP_SSI_MIN_SEL 0 /* Minimum Seletion value for ulp SSI clock source*/ +#define ULP_SSI_MAX_DIVISION_FACTOR 127 /* Maximum division factor value for ulp SSI clock*/ +#define ULP_SSI_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp SSI clock*/ + +/*ULP I2S CLOCK*/ +#define ULP_I2S_MAX_SEL 8 /* Maximum Seletion value for ulp I2S clock source*/ +#define ULP_I2S_MIN_SEL 0 /* Minimum Seletion value for ulp I2S clock source*/ +#define ULP_I2S_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp SSI clock*/ +#define ULP_I2S_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp SSI clock*/ + +/*ULP UART CLOCK*/ +#define ULP_UART_MAX_SEL 7 /* Maximum Seletion value for ulp Uart clock source*/ +#define ULP_UART_MIN_SEL 0 /* Minimum Seletion value for ulp Uart clock source*/ +#define ULP_UART_MAX_DIVISION_FACTOR 7 /* Maximum division factor value for ulp Uart clock*/ +#define ULP_UART_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Uart clock*/ + +/*ULP AUX CLOCK*/ +#define ULP_AUX_MAX_SEL 8 /* Maximum Seletion value for ulp Aux clock source*/ +#define ULP_AUX_MIN_SEL 0 /* Minimum Seletion value for ulp Aux clock source*/ +#define ULP_AUX_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Aux clock*/ +#define ULP_AUX_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Aux clock*/ + +/*ULP TIMER CLOCK*/ +#define ULP_TIMER_MAX_SEL 6 /* Maximum Seletion value for ulp Timer clock source*/ +#define ULP_TIMER_MIN_SEL 0 /* Minimum Seletion value for ulp Tiemer clock source*/ + +/*ULP VAD CLOCK*/ +#define ULP_VAD_MAX_SEL 8 /* Maximum Seletion value for ulp Vad clock source*/ +#define ULP_VAD_MIN_SEL 0 /* Minimum Seletion value for ulp Vad clock source*/ +#define ULP_VAD_FCLK_MAX_SEL 8 /* Maximum Seletion value for ulp Vad fclock source*/ +#define ULP_VAD_FCLK_MIN_SEL 0 /* Minimum Seletion value for ulp Vad fclock source*/ +#define ULP_VAD_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Vad clock*/ +#define ULP_VAD_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Vad clock*/ + +/*ULP TOUCH CLOCK*/ +#define ULP_TOUCH_MAX_SEL 6 /* Maximum Seletion value for ulp Touch clock source*/ +#define ULP_TOUCH_MIN_SEL 0 /* Minimum Seletion value for ulp Touch clock source*/ +#define ULP_TOUCH_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Touch clock*/ +#define ULP_TOUCH_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Touch clock*/ + +/*ULP SLEEP SENSOR */ +#define ULP_SLP_SENSOR_MAX_DIVISION_FACTOR 255 /* Maximum division factor value for ulp Sleep sensor clock*/ +#define ULP_SLP_SENSOR_MIN_DIVISION_FACTOR 0 /* Minimum division factor value for ulp Sleep sensor clock*/ +/** + *@brief ulpss Reference Input clock source selection + **/ +typedef enum ULPSS_REF_CLK_SEL { + ULPSS_REF_BYP_CLK = 1, /*!< REF_BYP_CLK selection*/ + ULPSS_ULP_MHZ_RC_CLK = 2, /*!< ULP_MHZ_RC_CLK selection*/ + ULPSS_40MHZ_CLK = 3, /*!< EXT_40MHZ_CLK selection*/ + ULPSS_MEMS_REF_CLK = 4, /*!< MEMS_REF_CLK selection*/ + ULPSS_ULP_20MHZ_RINGOSC_CLK = 5, /*!< ULP_20MHZ_RINGOSC_CLK selection*/ + ULPSS_ULP_DOUBLER_CLK = 6, /*!< ULP_DOUBLER_CLK selection*/ +} ULPSS_REF_CLK_SEL_T; +/** +*@brief Different possible ref_clk sources for Ulp_proc_clk +**/ +typedef enum ULP_PROC_CLK_SELECT { + ULP_PROC_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_PROC_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_PROC_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_PROC_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_PROC_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_PROC_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_PROC_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_PROC_ULP_DOUBLER_CLK /*!< ULP_DOUBLER_CLK selection*/ +} ULP_PROC_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_SSI_clk +**/ +typedef enum ULP_SSI_CLK_SELECT { + + ULP_SSI_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_SSI_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_SSI_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_SSI_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_SSI_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_SSI_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_SSI_SOC_CLK, /*!< SOC_CLK selection*/ +} ULP_SSI_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_I2S_clk +**/ +typedef enum ULP_I2S_CLK_SELECT { + + ULP_I2S_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_I2S_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_I2S_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_I2S_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_I2S_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_I2S_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_I2S_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_I2S_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ + ULP_I2S_PLL_CLK /*!< I2s_PLL_CLK selection*/ + +} ULP_I2S_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Uart_clk +**/ +typedef enum ULP_UART_CLK_SELECT { + + ULP_UART_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_UART_ULP_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_UART_ULP_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_UART_ULP_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_UART_ULP_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_UART_ULP_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_UART_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_UART_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ +} ULP_UART_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Timer_clk +**/ +typedef enum ULP_TIMER_CLK_SELECT { + + ULP_TIMER_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_TIMER_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_TIMER_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_TIMER_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_TIMER_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_TIMER_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_TIMER_ULP_SOC_CLK, /*!< SOC_CLK selection*/ +} ULP_TIMER_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_AUX_clk +**/ +typedef enum ULP_AUX_CLK_SELECT { + + ULP_AUX_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_AUX_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_AUX_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_AUX_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_AUX_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_AUX_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_AUX_ULP_SOC_CLK, /*!< SOC_CLK selection*/ + ULP_AUX_ULP_DOUBLER_CLK, /*!< ULP_DOUBLER_CLK selection*/ + ULP_AUX_I2S_PLL_CLK /*!< I2s_PLL_CLK selection*/ +} ULP_AUX_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Vad_clk +**/ +typedef enum ULP_VAD_CLK_SELECT { + + ULP_VAD_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_VAD_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_VAD_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ +} ULP_VAD_CLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Vad_fclk +**/ +typedef enum ULP_VAD_FCLK_SELECT { + + ULP_VAD_ULP_PROCESSOR_CLK, /*!< ULP_PROCESSOR_CLK selection*/ + ULP_VAD_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_VAD_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_VAD_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_VAD_ULP_SOC_CLK, /*!< SOC_CLK selection*/ +} ULP_VAD_FCLK_SELECT_T; +/** +*@brief Different possible input clk sources for Ulp_Touch_clk +**/ +typedef enum ULP_TOUCH_CLK_SELECT { + + ULP_TOUCH_REF_CLK, /*!< ULP_REF_CLK selection*/ + ULP_TOUCH_32KHZ_RO_CLK, /*!< ULP_32KHZ_RO_CLK selection*/ + ULP_TOUCH_32KHZ_RC_CLK, /*!< ULP_32KHZ_RC_CLK selection*/ + ULP_TOUCH_32KHZ_XTAL_CLK, /*!< ULP_32KHZ_XTAL_CLK selection*/ + ULP_TOUCH_MHZ_RC_CLK, /*!< ULP_MHZ_RC_CLK selection*/ + ULP_TOUCH_20MHZ_RO_CLK, /*!< ULP_20MHZ_RO_CLK selection*/ + ULP_TOUCH_ULP_SOC_CLK /*!< SOC_CLK selection*/ + +} ULP_TOUCH_CLK_SELECT_T; + +/** +*@brief list of peripherals, particular ulp clock that to be disabled +**/ +typedef enum ULPPERIPHERALS_CLK { + ULP_I2C_CLK, /*!< Enables or Disables ULP_I2C Peripheral clock when it is passed */ + ULP_EGPIO_CLK, /*!< Enables or Disables Ulp_Egpio Peripheral clock when it is passed */ + ULP_AUX_CLK, /*!< Enables or Disables Ulp_Aux Peripheral clock when it is passed */ + ULP_FIM_CLK, /*!< Enables or Disables Ulp_Fim Peripheral clock when it is passed */ + ULP_VAD_CLK, /*!< Enables or Disables Ulp_Vad Peripheral clock when it is passed */ + ULP_TIMER_CLK, /*!< Enables or Disables Ulp_Timer Peripheral clock when it is passed */ + ULP_UDMA_CLK, /*!< Enables or Disables Ulp_Udma Peripheral clock when it is passed */ + ULP_TOUCH_CLK, /*!< Enables or Disables Ulp_Touch Peripheral clock when it is passed */ + ULP_UART_CLK, /*!< Enables or Disables Ulp_Uart Peripheral clock when it is passed */ + ULP_SSI_CLK, /*!< Enables or Disables Ulp_SSI Peripheral clock when it is passed */ + ULP_I2S_CLK, /*!< Enables or Disables Ulp_I2S Peripheral clock when it is passed */ +} ULPPERIPHERALS_CLK_T; + +rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn); +rsi_error_t ulpss_ref_clk_config(ULPSS_REF_CLK_SEL_T clkSource); + +rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor); + +rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn); + +rsi_error_t ulpss_ulp_peri_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_peri_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_dyn_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_dyn_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags); + +rsi_error_t ulpss_ulp_ssi_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t ulpss_ulp_uar_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor); + +rsi_error_t ulpss_time_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime); + +rsi_error_t ulpss_aux_clk_config(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource); + +rsi_error_t ulpss_vad_clk_config(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor); + +rsi_error_t ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor); + +rsi_error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor); + +rsi_error_t ulpss_peripheral_enable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType); + +rsi_error_t ulpss_peripheral_disable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module); + +rsi_error_t ulpss_time_clk_disable(ULPCLK_Type *pULPCLK); + +#endif /*__RSI_ULPSS_CLK_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h new file mode 100644 index 000000000..bb347c58c --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/inc/rsi_wwdt.h @@ -0,0 +1,220 @@ +/******************************************************************************* +* @file rsi_wwdt.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ +#ifndef __RSI_WDT_H__ +#define __RSI_WDT_H__ + +#ifdef __cplusplus +extern "C" { +#endif +#include "rsi_ccp_common.h" +#include "base_types.h" +#include "rsi_power_save.h" + +#ifndef UNUSED_PARAMETER +#define UNUSED_PARAMETER(x) (void)(x) +#endif // UNUSED_PARAMETER + +#define WDT_SYSTEM_RESET_TIMER 0x3 +#define WDT_INTERRUPT_TIMER 0x1 +#define WDT_IRQHandler IRQ020_Handler /*!MCU_WWD_WINDOW_TIMER_b.WINDOW_TIMER = (unsigned int)(u8WindowTimerVal & 0x0F); +} + +/** + * @fn void RSI_WWDT_ConfigIntrTimer(MCU_WDT_Type *pstcWDT , uint16_t u16IntrTimerVal) + * @brief This API is used to configure the interrupt timer of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @param[in] u16IntrTimerVal : interrupt timer value + * @return None + */ +STATIC INLINE void RSI_WWDT_ConfigIntrTimer(MCU_WDT_Type *pstcWDT, uint16_t u16IntrTimerVal) +{ + pstcWDT->MCU_WWD_INTERRUPT_TIMER_b.WWD_INTERRUPT_TIMER = (unsigned int)(u16IntrTimerVal & 0x1F); +} + +/** + * @fn void RSI_WWDT_ConfigSysRstTimer(MCU_WDT_Type *pstcWDT , uint16_t u16SysRstVal) + * @brief This API is used to configure the system reset timer of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @param[in] u16SysRstVal : reset value + * @return NONE + */ +STATIC INLINE void RSI_WWDT_ConfigSysRstTimer(MCU_WDT_Type *pstcWDT, uint16_t u16SysRstVal) +{ + pstcWDT->MCU_WWD_SYSTEM_RESET_TIMER_b.WWD_SYSTEM_RESET_TIMER = (unsigned int)(u16SysRstVal & 0x1F); +} + +/** + * @fn void RSI_WWDT_Disable(MCU_WDT_Type *pstcWDT) + * @brief This API is used to Disable the Watch dog timer + * @param[in] pstcWDT :pointer to the WDT register instance + * @return None + */ +STATIC INLINE void RSI_WWDT_Disable(MCU_WDT_Type *pstcWDT) +{ + /*0xF0 to Disable the watch dog */ + pstcWDT->MCU_WWD_MODE_AND_RSTART_b.WWD_MODE_EN_STATUS = 0xF0; +} + +/** + * @fn void RSI_WWDT_ReStart(MCU_WDT_Type *pstcWDT) + * @brief This API is used to restart the Watch dog timer + * @param[in] pstcWDT :pointer to the WDT register instance + * @return None + */ +STATIC INLINE void RSI_WWDT_ReStart(MCU_WDT_Type *pstcWDT) +{ + pstcWDT->MCU_WWD_MODE_AND_RSTART_b.WWD_MODE_RSTART = 1U; +} + +/** + * @fn void RSI_WWDT_IntrUnMask(void) + * @brief This API is used to unmask the Watch dog timer + * @return None + */ +STATIC INLINE void RSI_WWDT_IntrUnMask(void) +{ + NPSS_INTR_MASK_CLR_REG = NPSS_TO_MCU_WDT_INTR; +} + +/** + * @fn void RSI_WWDT_IntrMask(void) + * @brief This API is used to mask the Watch dog timer + * @return None + */ +STATIC INLINE void RSI_WWDT_IntrMask(void) +{ + NPSS_INTR_MASK_SET_REG = NPSS_TO_MCU_WDT_INTR; +} + +/** + * @fn void RSI_WWDT_SysRstOnProcLockEnable(MCU_WDT_Type *pstcWDT) + * @brief This API is used to enable Watch dog timer to reset system on processor stuck + * @return None + */ +STATIC INLINE void RSI_WWDT_SysRstOnProcLockEnable(MCU_WDT_Type *pstcWDT) +{ + pstcWDT->MCU_WWD_ARM_STUCK_EN_b.PROCESSOR_STUCK_RESET_EN = ENABLE; +} + +/** + * @fn void RSI_WWDT_SysRstOnProcLockDisable(MCU_WDT_Type *pstcWDT) + * @brief This API is used to disable Watch dog timer to reset system on processor stuck + * @return None + */ +STATIC INLINE void RSI_WWDT_SysRstOnProcLockDisable(MCU_WDT_Type *pstcWDT) +{ + pstcWDT->MCU_WWD_ARM_STUCK_EN_b.PROCESSOR_STUCK_RESET_EN = DISABLE; +} + +/** + * @fn void RSI_WWDT_GetProcLockSignal(const MCU_WDT_Type *pstcWDT) + * @brief This API is used to read signal for processor stuck reset enable + * @return None + */ +STATIC INLINE uint8_t RSI_WWDT_GetProcLockRstEnableSignal(const MCU_WDT_Type *pstcWDT) +{ + if (pstcWDT->MCU_WWD_ARM_STUCK_EN_b.PROCESSOR_STUCK_RESET_EN_) { + return 1; + } else { + return 0; + } +} + +/** + * @fn uint16_t RSI_WWDT_GetIntrTime(const MCU_WDT_Type *pstcWDT) + * @brief This API is used to read the interrupt time of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @return uint8_t : interrupt timer value + */ +STATIC INLINE uint8_t RSI_WWDT_GetIntrTime(const MCU_WDT_Type *pstcWDT) +{ + uint8_t interrupt_time; + interrupt_time = pstcWDT->MCU_WWD_INTERRUPT_TIMER_b.WWD_INTERRUPT_TIMER; + return interrupt_time; +} + +/** + * @fn uint16_t RSI_WWDT_GetSysRstTime(const MCU_WDT_Type *pstcWDT) + * @brief This API is used to read the system reset time of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @return uint8_t : system reset timer value + */ +STATIC INLINE uint8_t RSI_WWDT_GetSysRstTime(const MCU_WDT_Type *pstcWDT) +{ + uint8_t system_reset_time; + system_reset_time = pstcWDT->MCU_WWD_SYSTEM_RESET_TIMER_b.WWD_SYSTEM_RESET_TIMER; + return system_reset_time; +} + +/** + * @fn uint8_t RSI_WWDT_GetWindowTime(const MCU_WDT_Type *pstcWDT) + * @brief This API is used to read the system reset time of the watch dog timer + * @param[in] pstcWDT : pointer to the WDT register instance + * @return uint8_t : system reset timer value + */ +STATIC INLINE uint8_t RSI_WWDT_GetWindowTime(const MCU_WDT_Type *pstcWDT) +{ + uint8_t window_time; + window_time = pstcWDT->MCU_WWD_WINDOW_TIMER_b.WINDOW_TIMER; + return window_time; +} +// Function prototypes +void RSI_WWDT_IntrClear(void); + +uint8_t RSI_WWDT_GetIntrStatus(void); + +void RSI_WWDT_DeInit(MCU_WDT_Type *pstcWDT); + +void RSI_WWDT_Start(MCU_WDT_Type *pstcWDT); + +void RSI_WWDT_Init(MCU_WDT_Type *pstcWDT); +void IRQ020_Handler(void); + +#ifdef __cplusplus +} +#endif + +/*End of file not truncated*/ +#endif /*__RSI_WDT_H__*/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c new file mode 100644 index 000000000..151eef584 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c @@ -0,0 +1,1707 @@ +/******************************************************************************* +* @file rsi_ipmu.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * Includes + */ +#include "rsi_system_config.h" +#include "rsi_ipmu.h" +#include "rsi_pll.h" +#include "rsi_ulpss_clk.h" + +/** + * Defines + */ +#define SYSTEM_CLK_VAL_20MHZ ((uint32_t)(20000000)) // macro for 20MHz +#define SYSTEM_CLK_VAL_MHZ ((uint32_t)(32000000)) // macro for 32MHz doubler + +/** + * @fn void RSI_IPMU_UpdateIpmuCalibData_efuse(const efuse_ipmu_t *ipmu_calib_data) + * @brief This function prepares the data from the ipmu calib structure content and writes to each specific register + * @param[in] ipmu_calib_data : pointer of calibrate data + * @return none + */ +void RSI_IPMU_UpdateIpmuCalibData_efuse(const efuse_ipmu_t *ipmu_calib_data) +{ + uint32_t data = 0; + uint32_t value = 0; + uint32_t mask = 0; + /* over writing the efuse arrays */ + +#ifdef CHIP_9118 + /* POC_BIAS_EFUSE */ + data = (ipmu_calib_data->trim_0p5na1 | ipmu_calib_data->trim_0p5na2 << 1); + mask = MASK_BITS(22, 0); + value = poc_bias_efuse[2]; + value &= ~mask; + value |= data; + poc_bias_efuse[2] = value; +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) + /* POC_BIAS_EFUSE */ + data = (ipmu_calib_data->trim_0p5na1); + mask = MASK_BITS(22, 0); + value = poc_bias_efuse[2]; + value &= ~mask; + value |= data; + poc_bias_efuse[2] = value; +#endif + +#ifdef CHIP_9118 + /* BG_TRIM_EFUSE */ + data = (ipmu_calib_data->bg_r_vdd_ulp | ipmu_calib_data->bg_r_ptat_vdd_ulp << 3); + mask = MASK_BITS(22, 0); + value = bg_trim_efuse[4]; + value &= ~mask; + value |= data; + bg_trim_efuse[4] = value; +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) + /* BG_TRIM_EFUSE */ + data = (ipmu_calib_data->bg_r_ptat_vdd_ulp); + mask = MASK_BITS(22, 0); + value = bg_trim_efuse[2]; + value &= ~mask; + value |= data; + bg_trim_efuse[2] = value; + + /* BG_TRIM_EFUSE */ + data = (ipmu_calib_data->bg_r_vdd_ulp); + mask = MASK_BITS(22, 0); + value = bg_trim_efuse[4]; + value &= ~mask; + value |= data; + bg_trim_efuse[4] = value; +#endif + +#ifdef CHIP_9118 + /* POC2 ( blackout_trim_efuse )*/ + data = (ipmu_calib_data->resbank_trim); + mask = MASK_BITS(22, 0); + value = blackout_trim_efuse[2]; + value &= ~mask; + value |= data; + blackout_trim_efuse[2] = value; +#endif + + /* M32RC_EFUSE */ + data = ipmu_calib_data->trim_sel; + mask = MASK_BITS(22, 0); + value = m32rc_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m32rc_osc_trim_efuse[2] = value; + + /* dblr_32m_trim_efuse */ + data = ipmu_calib_data->del_2x_sel; + mask = MASK_BITS(22, 0); + value = dblr_32m_trim_efuse[2]; + value &= ~mask; + value |= data; + dblr_32m_trim_efuse[2] = value; + + /* ro_32khz_trim_efuse */ + data = ipmu_calib_data->freq_trim; + mask = MASK_BITS(22, 0); + value = ro_32khz_trim_efuse[2]; + value &= ~mask; + value |= data; + ro_32khz_trim_efuse[2] = value; + + /* rc_16khz_trim_efuse */ + data = (uint32_t)(ipmu_calib_data->coarse_trim_16k | ipmu_calib_data->fine_trim_16k << 2); + mask = MASK_BITS(22, 0); + value = rc_16khz_trim_efuse[2]; + value &= ~mask; + value |= data; + rc_16khz_trim_efuse[2] = value; + + /* rc_64khz_trim_efuse */ + data = (uint32_t)(ipmu_calib_data->coarse_trim_64k | ipmu_calib_data->fine_trim_64k << 2); + mask = MASK_BITS(22, 0); + value = rc_64khz_trim_efuse[2]; + value &= ~mask; + value |= data; + rc_64khz_trim_efuse[2] = value; + + /* xtal1_bias_efuse */ + data = (ipmu_calib_data->xtal1_trim_32k); + mask = MASK_BITS(22, 0); + value = xtal1_bias_efuse[2]; + value &= ~mask; + value |= data; + xtal1_bias_efuse[2] = value; + + /* xtal2_bias_efuse */ + data = (ipmu_calib_data->xtal2_trim_32k); + mask = MASK_BITS(22, 0); + value = xtal2_bias_efuse[2]; + value &= ~mask; + value |= data; + xtal2_bias_efuse[2] = value; + +#ifndef AT_EFUSE_DATA_1P19 + /* m20rc_osc_trim_efuse */ + data = ((ipmu_calib_data->reserved1) & 0x7F); + mask = MASK_BITS(22, 0); + value = m20rc_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m20rc_osc_trim_efuse[2] = value; +#endif + +#ifdef AT_EFUSE_DATA_1P19 + /* m20rc_osc_trim_efuse */ + data = (ipmu_calib_data->trim_sel_20Mhz); + mask = MASK_BITS(22, 0); + value = m20rc_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m20rc_osc_trim_efuse[2] = value; +#endif + + /*m20ro_osc_trim_efuse */ + data = (ipmu_calib_data->trim_ring_osc); + mask = MASK_BITS(22, 0); + value = m20ro_osc_trim_efuse[2]; + value &= ~mask; + value |= data; + m20ro_osc_trim_efuse[2] = value; + + /* vbatt_status_trim_efuse */ + data = (ipmu_calib_data->vbatt_status_1); + mask = MASK_BITS(22, 0); + value = vbatt_status_trim_efuse[2]; + value &= ~mask; + value |= data; + vbatt_status_trim_efuse[2] = value; + + /* ro_ts_efuse */ + data = (ipmu_calib_data->f2_nominal); + mask = MASK_BITS(22, 0); + value = ro_ts_efuse[2]; + value &= ~mask; + value |= data; + ro_ts_efuse[2] = value; + + /* ro_tempsense_config */ + data = (ipmu_calib_data->str_temp_slope); + mask = MASK_BITS(22, 0); + value = ro_tempsense_config[2]; + value &= ~mask; + value |= data; + ro_tempsense_config[2] = value; + +#ifdef AT_EFUSE_DATA_1P19 + /*BJT temperature sensor efuse value update*/ + /* delvbe_ts_efuse*/ + data = (ipmu_calib_data->str_bjt_temp_sense_off); + mask = MASK_BITS(22, 0); + value = delvbe_tsbjt_efuse[2]; + value &= ~mask; + value |= data; + delvbe_tsbjt_efuse[2] = value; + + /* vbg_ts_efuse */ + data = (ipmu_calib_data->vbg_tsbjt_efuse); + mask = MASK_BITS(22, 0); + value = vbg_tsbjt_efuse[2]; + value &= ~mask; + value |= data; + vbg_tsbjt_efuse[2] = value; +#endif + + /* retn_ldo_lptrim */ + data = (ipmu_calib_data->retn_ldo_lptrim); + mask = MASK_BITS(22, 0); + value = retnLP_volt_trim_efuse[2]; + value &= ~mask; + value |= data; + retnLP_volt_trim_efuse[2] = value; + + /* auxadc_off_diff_efuse */ + data = (ipmu_calib_data->auxadc_offset_diff); + mask = MASK_BITS(22, 0); + value = auxadc_off_diff_efuse[2]; + value &= ~mask; + value |= data; + auxadc_off_diff_efuse[2] = value; + + /* auxadc_gain_diff_efuse */ + data = (ipmu_calib_data->auxadc_invgain_diff); + mask = MASK_BITS(22, 0); + value = auxadc_gain_diff_efuse[2]; + value &= ~mask; + value |= data; + auxadc_gain_diff_efuse[2] = value; + + /* auxadc_off_se_efuse */ + data = (ipmu_calib_data->auxadc_offset_single); + mask = MASK_BITS(22, 0); + value = auxadc_off_se_efuse[2]; + value &= ~mask; + value |= data; + auxadc_off_se_efuse[2] = value; + + /* auxadc_gain_se_efuse */ + data = (ipmu_calib_data->auxadc_invgain_single); + mask = MASK_BITS(22, 0); + value = auxadc_gain_se_efuse[2]; + value &= ~mask; + value |= data; + auxadc_gain_se_efuse[2] = value; + + /* rc_32khz_trim_efuse */ + data = (uint32_t)(ipmu_calib_data->coarse_trim_32k | ipmu_calib_data->fine_trim_32k << 2); + mask = MASK_BITS(22, 0); + value = rc_32khz_trim_efuse[2]; + value &= ~mask; + value |= data; + rc_32khz_trim_efuse[2] = value; + +#ifndef AT_EFUSE_DATA_1P19 + /*If the 13 bits of WuRx(i.e.reserved1) in E-Fuse are zeros, + then overwrite this structure with the contents from RO32K_EFUSE*/ + if (!((ipmu_calib_data->reserved1) >> 7)) { + ro_32khz_trim00_efuse[2] = ro_32khz_trim_efuse[2]; + } else { + /*then write the contents of the (reserved1) last 5 bits + allotted to RO32K_00 */ + data = ((ipmu_calib_data->reserved1) & (0xF80)); + mask = MASK_BITS(22, 0); + value = ro_32khz_trim00_efuse[2]; + value &= ~mask; + value |= data; + ro_32khz_trim00_efuse[2] = value; + } +#endif + +#ifdef AT_EFUSE_DATA_1P19 + + /*If the 13 bits of WuRx(i.e.reserved1) in E-Fuse are zeros, + then overwrite this structure with the contents from RO32K_EFUSE*/ + if (!(ipmu_calib_data->ro_32khz_00_trim)) { + ro_32khz_trim00_efuse[2] = ro_32khz_trim_efuse[2]; + } else { + /*then write the contents of the (reserved1) last 5 bits + allotted to RO32K_00 */ + data = (ipmu_calib_data->ro_32khz_00_trim); + mask = MASK_BITS(22, 0); + value = ro_32khz_trim00_efuse[2]; + value &= ~mask; + value |= data; + ro_32khz_trim00_efuse[2] = value; + } +#endif + + data = ipmu_calib_data->set_vref1p3; + mask = MASK_BITS(22, 0); + value = buck_trim_efuse[2]; + value &= ~mask; + value |= data; + buck_trim_efuse[2] = value; + + data = ipmu_calib_data->trim_r1_resistorladder; + mask = MASK_BITS(22, 0); + value = ldosoc_trim_efuse[2]; + value &= ~mask; + value |= data; + ldosoc_trim_efuse[2] = value; + + data = ipmu_calib_data->dpwm_freq_trim; + mask = MASK_BITS(22, 0); + value = dpwm_freq_trim_efuse[2]; + value &= ~mask; + value |= data; + dpwm_freq_trim_efuse[2] = value; + +#ifdef AT_EFUSE_DATA_1P19 + /* scdc_hpldo_trim */ + data = ipmu_calib_data->scdc_hpldo_trim; + mask = MASK_BITS(22, 0); + value = hpldo_volt_trim_efuse[2]; + value &= ~mask; + value |= data; + hpldo_volt_trim_efuse[2] = value; + + /* scdc_dcdc_trim */ + data = ipmu_calib_data->scdc_dcdc_trim; + mask = MASK_BITS(22, 0); + value = scdc_volt_trim_efuse[2]; + value &= ~mask; + value |= data; + scdc_volt_trim_efuse[2] = value; +#endif + + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_InitCalibData(void) + * @brief This function checks for magic byte in efuse/flash, copies the content if valid data present and calls to update the ipmu registers + * @return none + */ +void RSI_IPMU_InitCalibData(void) +{ + efuse_ipmu_t global_ipmu_calib_data; +#ifdef CHIP_9118 + uint8_t *calib_data_read_adr = NULL; + + /* Read the MCU boot status register */ + volatile retention_boot_status_word_t *retention_reg = (retention_boot_status_word_t *)MCURET_BOOTSTATUS; + /* Read the NWP BBFFs storage register */ + volatile npss_boot_status_word0_t *npss_boot_status = (npss_boot_status_word0_t *)MCU_BBFF_STORAGE1_ADDR; + + if (retention_reg->product_mode == MCU) { + calib_data_read_adr = (uint8_t *)(MCU_MANF_DATA_BASE_ADDR); + } + if (retention_reg->product_mode == WISEMCU) { + if (npss_boot_status->ta_flash_present) { + calib_data_read_adr = (uint8_t *)(TA_MANF_DATA_BASE_ADDR); + } else { + calib_data_read_adr = (uint8_t *)(MCU_MANF_DATA_BASE_ADDR); + } + } + + /* Checks the Calibration values are present at MCU flash */ + if ((*(uint32_t *)(calib_data_read_adr + IPMU_VALUES_OFFSET)) == 0x00) { + //NO CALIB DATA. Return + return; + } + /* Checks the `Calibration values are present at MCU flash */ + if ((*(uint32_t *)(calib_data_read_adr + IPMU_VALUES_OFFSET)) == 0xFFFFFFFF) { + //NO CALIB DATA. Return + return; + } + + memcpy((void *)&global_ipmu_calib_data, (void *)(calib_data_read_adr + IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); + //rsi_cmd_m4_ta_secure_handshake(2,0,NULL,sizeof(efuse_ipmu_t),(uint8_t *)&global_ipmu_calib_data); +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + /* Checks the Calibration values are present at MCU flash */ + if ((*(uint32_t *)(COMMON_FLASH_IPMU_VALUES_OFFSET)) == 0x00) { + //NO CALIB DATA. Return + return; + } + memcpy((void *)&global_ipmu_calib_data, (void *)(COMMON_FLASH_IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); +#else + /* Checks the Calibration values are present at MCU flash */ + if ((*(uint32_t *)(DUAL_FLASH_IPMU_VALUES_OFFSET)) == 0x00) { + //NO CALIB DATA. Return + return; + } + memcpy((void *)&global_ipmu_calib_data, (void *)(DUAL_FLASH_IPMU_VALUES_OFFSET), sizeof(efuse_ipmu_t)); +#endif +#endif + + //Dummy read + (void)PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); + + RSI_IPMU_UpdateIpmuCalibData_efuse(&global_ipmu_calib_data); + + //Dummy read + (void)PMU_SPI_DIRECT_ACCESS(PMU_PFM_REG_OFFSET); +} + +/*==============================================*/ +/** + * @brief This function Initialize IPMU and MCU FSM blocks + * @param void + * @return void + */ +void RSI_Ipmu_Init(void) +{ + ipmu_init(); +} + +/** + * @brief This function configures chip supply mode + * @param void + * @return void + */ +void RSI_Configure_Ipmu_Mode(void) +{ + double temperature = 0; + +#if defined(ENABLE_1P8V) || defined(SLI_SI915) + (void)temperature; + /*configures chip supply mode to HP-LDO */ + configure_ipmu_mode(HP_LDO_MODE); +#else + (void)temperature; + configure_ipmu_mode(SCDC_MODE); +#endif +} +void update_efuse_system_configs(int data, uint32_t config_ptr[]) +{ + uint32_t mask = 0; + uint32_t value = 0; + mask = MASK_BITS(22, 0); + value = config_ptr[2]; + value &= ~mask; + value |= (uint32_t)data; + config_ptr[2] = value; +} +/** + * @brief This function configures the Lower voltage level for DC-DC to 1.25V based on the DC-DC Trim value(for 1.35V) obtained from Calibration + * @return none + */ + +void RSI_Configure_DCDC_LowerVoltage(void) +{ + uint32_t pmu_1p2_ctrl_word; + uint32_t bypass_curr_ctrl_data; + + bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(PMU_1P3_CTRL_REG_OFFSET); + pmu_1p2_ctrl_word = ((bypass_curr_ctrl_data >> 17) & 0xF) - 2; + bypass_curr_ctrl_data = PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET); + bypass_curr_ctrl_data &= (uint32_t)(~(0xF << 5)); + PMU_SPI_DIRECT_ACCESS(BYPASS_CURR_CTRL_REG_OFFSET) = (bypass_curr_ctrl_data | (pmu_1p2_ctrl_word << 5)); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_PowerGateSet(uint32_t mask_vlaue) + * @brief This API is used to power-up the IPMU peripherals. + * @param[in] mask_vlaue : Ored value of peripheral power gate defines + * Possible values for this parameter are the following + * CMP_NPSS_PG_ENB + * ULP_ANG_CLKS_PG_ENB + * ULP_ANG_PWRSUPPLY_PG_ENB + * WURX_PG_ENB + * WURX_CORR_PG_ENB + * AUXADC_PG_ENB + * AUXADC_BYPASS_ISO_GEN + * AUXADC_ISOLATION_ENABLE + * AUXDAC_PG_ENB + * @return none + */ + +void RSI_IPMU_PowerGateSet(uint32_t mask_vlaue) +{ + uint32_t impuPowerGate = 0; + impuPowerGate = ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + impuPowerGate = (impuPowerGate >> 5); + impuPowerGate |= mask_vlaue; + ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE) = impuPowerGate; + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + /*Dummy read*/ + impuPowerGate = ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE); + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue) + * @brief This API is used to power-down the IPMU peripherals. + * @param[in] mask_vlaue : Ored value of peripheral power gate defines + * Possible values for this parameter are the following + * CMP_NPSS_PG_ENB + * ULP_ANG_CLKS_PG_ENB + * ULP_ANG_PWRSUPPLY_PG_ENB + * WURX_PG_ENB + * WURX_CORR_PG_ENB + * AUXADC_PG_ENB + * AUXADC_BYPASS_ISO_GEN + * AUXADC_ISOLATION_ENABLE + * AUXDAC_PG_ENB + * @return none + */ + +void RSI_IPMU_PowerGateClr(uint32_t mask_vlaue) +{ + uint32_t impuPowerGate = 0; + + if (mask_vlaue & (WURX_CORR_PG_ENB | WURX_PG_ENB)) { + ULP_SPI_MEM_MAP(0x141) &= ~BIT(20); + ULP_SPI_MEM_MAP(0x141) &= ~BIT(21); + } + + impuPowerGate = ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + impuPowerGate = (impuPowerGate >> 5); + impuPowerGate &= ~mask_vlaue; + ULP_SPI_MEM_MAP(POWERGATE_REG_WRITE) = impuPowerGate; + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk) + * @brief This API is used to select clock to the BG-PMU + * @param[in] bg_pmu_clk : Selects the clock source to the BG-PMU module + * 1: RO 32KHz clock + * 2: MCU FSM clock + * @return none + */ + +void RSI_IPMU_ClockMuxSel(uint8_t bg_pmu_clk) +{ + bg_pmu_clk = (bg_pmu_clk - 1); + ULP_SPI_MEM_MAP(SELECT_BG_CLK) &= ~(BIT(0) | BIT(1)); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + ULP_SPI_MEM_MAP(SELECT_BG_CLK) |= BIT(bg_pmu_clk); + while (GSPI_CTRL_REG1 & SPI_ACTIVE) + ; + return; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_32MHzClkClib(void) + * @brief This API is used to auto calibrate the 32MHz RC clock + * @return trim value on success + */ + +uint32_t RSI_IPMU_32MHzClkClib(void) +{ + volatile int i; + volatile int trim_value = 0; + /*Enables RC 32MHz clock and*/ + ULP_SPI_MEM_MAP(0x104) = (0x3FFFFF & 0x41368000); + /*Enable XTAL 40MHz clock through NPSS*/ + *(volatile uint32_t *)0x41300120 |= BIT(22); + i = 1000000; + while (i--) + ; + /*Selects NPSS reference clock to be CLK-40M_SOC*/ + ULP_SPI_MEM_MAP(0x106) = (0x3FFFFF & 0x41A48000); + /*Change spi trim select to 0*/ + ULP_SPI_MEM_MAP(0x107) = (0x3FFFFF & 0x41C04A14); + /*Pointing clks test out 1 to RC 32M clock*/ + ULP_SPI_MEM_MAP(0x10D) = (0x3FFFFF & 0x43600000); + /*Pointing clks test out to IPMU_TEST_OUT_0 = SOC[8] in mode 5*/ + ULP_SPI_MEM_MAP(0x143) = (0x3FFFFF & 0x50C00610); + /*Enable the high frequency clock calibration + * Enable the clock gate for npss ref clk + * Select the RC32M clock to calibrate + * */ + ULP_SPI_MEM_MAP(0x10A) = (0x3FFFFF & 0x42922290); + i = 100000; + while (i--) + ; + do { + /*wait for calibration done indication*/ + } while ((!(ULP_SPI_MEM_MAP(0x30C))) & BIT(20)); + /*Calibrated trim value*/ + trim_value = (int)ULP_SPI_MEM_MAP(0x30C); + trim_value = (trim_value >> 11); + trim_value = (trim_value & 0x7F); + /*Programming the calibrated trim to SPI register.*/ + ULP_SPI_MEM_MAP(0x104) |= (uint32_t)(trim_value << 14); + /*pointing the trim select to SPI*/ + ULP_SPI_MEM_MAP(0x107) = (0x3FFFFF & 0x41C05A14); + return (uint32_t)trim_value; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_ProgramConfigData(const uint32_t *config) + * @brief This API is used to program the any mcu configuration structure + * @param[in] config : pointer configuration + * @return RSI_OK on success + */ + +rsi_error_t RSI_IPMU_ProgramConfigData(const uint32_t *config) +{ + volatile uint32_t index = 0; + volatile uint32_t program_len = 0; + volatile uint32_t reg_addr = 0; + volatile uint32_t reg_write_data = 0; + volatile uint32_t clear_cnt = 0; + volatile uint32_t cnt = 0; + volatile uint32_t reg_read_data = 0; + volatile uint32_t write_mask = 0; + volatile uint32_t write_bit_pos = 0; + volatile uint8_t msb = 0; + volatile uint8_t lsb = 0; + + if (config == NULL) { + return INVALID_PARAMETERS; + } + /*Compute the number of entries in the array to program*/ + program_len = config[index]; + if (program_len == 0U) { + return INVALID_PARAMETERS; + } + for (index = 0; index < program_len; index++) { + reg_addr = config[(2U * index) + 1]; + reg_write_data = config[2U * (index + 1)]; + + lsb = ((reg_write_data >> LSB_POSITION) & POSITION_BITS_MASK); + msb = ((reg_write_data >> MSB_POSITION) & POSITION_BITS_MASK); + + clear_cnt = (msb - lsb) + 1U; + /*MSB and LSB position counts validation */ + if (clear_cnt > MAX_BIT_LEN) { + // Return error + return INVALID_PARAMETERS; + } + /*Read register*/ + reg_read_data = *(volatile uint32_t *)reg_addr; + cnt = lsb; + write_mask = 0; + write_bit_pos = 0; + do { + reg_read_data &= ~BIT(cnt); + write_mask |= BIT(write_bit_pos); + cnt++; + write_bit_pos++; + } while (cnt < (clear_cnt + lsb)); + reg_write_data &= write_mask; + /*Write to the hardware register*/ + reg_write_data = (reg_read_data | (reg_write_data << lsb)); + *(volatile uint32_t *)reg_addr = reg_write_data; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_APB_ProgramConfigData(const uint32_t *config) + * @brief This API is used to program the any mcu configuration structure + * @param[in] config : pointer configuration + * @return reg_write_data on success. + */ + +uint32_t RSI_APB_ProgramConfigData(const uint32_t *config) +{ + volatile uint32_t index = 0; + volatile uint32_t program_len = 0; + volatile uint32_t reg_addr = 0; + volatile uint32_t clear_cnt = 0; + volatile uint32_t cnt = 0; + volatile uint32_t reg_write_data = 0; + volatile uint32_t reg_read_data = 0; + volatile uint32_t write_mask = 0; + volatile uint32_t write_bit_pos = 0; + volatile uint8_t msb = 0; + volatile uint8_t lsb = 0; + (void)reg_addr; + + if (config == NULL) { + return INVALID_PARAMETERS; + } + /*Compute the number of entries in the array to program*/ + program_len = config[index]; + if (program_len == 0U) { + return INVALID_PARAMETERS; + } + for (index = 0; index < program_len; index++) { + + reg_write_data = config[2U * (index + 1)]; + + lsb = ((reg_write_data >> LSB_POSITION) & POSITION_BITS_MASK); + msb = ((reg_write_data >> MSB_POSITION) & POSITION_BITS_MASK); + + clear_cnt = (msb - lsb) + 1U; + /*MSB and LSB position counts validation */ + if (clear_cnt > MAX_BIT_LEN) { + // Return error + return INVALID_PARAMETERS; + } + cnt = lsb; + write_mask = 0; + write_bit_pos = 0; + do { + write_mask |= BIT(write_bit_pos); + cnt++; + write_bit_pos++; + } while (cnt < (clear_cnt + lsb)); + reg_write_data &= write_mask; + /*Write to the hardware register*/ + reg_write_data = (reg_read_data | (reg_write_data << lsb)); + } + return reg_write_data; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_CommonConfig(void) + * @brief This API is used to program the default system start-up IPMU hardware programming. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_CommonConfig(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_common_config); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_PMUCommonConfig(void) + * @brief This API is used to program the default system start-up PMU hardware programming. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_PMUCommonConfig(void) +{ + return RSI_IPMU_ProgramConfigData(pmu_common_config); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_PocbiasCurrent(void) + * @brief This API is used to Decreasing the bias current of RETN_LDO . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_PocbiasCurrent(void) +{ + return RSI_IPMU_ProgramConfigData(poc_bias_current); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_PocbiasCurrent11(void) + * @brief This API is used to increasing the bias current of RETN_LDO . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_PocbiasCurrent11(void) +{ + return RSI_IPMU_ProgramConfigData(poc_bias_current_11); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RO32khzTrim00Efuse(void) + * @brief This API is used to trim to 32Khz RO . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RO32khzTrim00Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(ro_32khz_trim00_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RetnLdoVoltsel(void) + * @brief This API is used to setting RETN_LDO voltage to 0.7V. + * @return RSI_IPMU_ProgramConfigData on success . + */ + +rsi_error_t RSI_IPMU_RetnLdoVoltsel(void) +{ + return RSI_IPMU_ProgramConfigData(retn_ldo_voltsel); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RetnLdo0p75(void) + * @brief This API is used to setting RETN_LDO voltage to 0.75V . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RetnLdo0p75(void) +{ + return RSI_IPMU_ProgramConfigData(retn_ldo_0p75); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_RetnLdoLpmode(void) + * @brief This API is used to program enabling the RETN_LDO LP MODE . + * @return none + */ + +void RSI_IPMU_RetnLdoLpmode(void) +{ + RSI_IPMU_ProgramConfigData(retn_ldo_lpmode); + RSI_IPMU_ProgramConfigData(retnLP_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Retn_Voltage_Reduction(void) + * @brief This API is used to reduce the RETN_LDO voltage by 0.05V. + * @return none + */ + +void RSI_IPMU_Retn_Voltage_Reduction(void) +{ + uint32_t value; + uint32_t mask; + value = retnLP_volt_trim_efuse[2]; + mask = MASK_BITS(3, 0); + value &= mask; + if (value < RET_LDO_TRIM_VALUE_CHECK) { + retnLP_volt_trim_efuse[2] += RET_LDO_VOL_DECREASE; + } +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Retn_Voltage_To_Default(void) + * @brief This API is used to change the RETN_LDO voltage to 0.8V. + * @return none + */ + +void RSI_IPMU_Retn_Voltage_To_Default(void) +{ + uint32_t mask; + mask = MASK_BITS(22, 0); + retnLP_volt_trim_efuse[2] &= ~mask; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(void) + * @brief This API is used to enable Higher Pwm Ro Frequency Mode for PMU. + * @return none + */ + +void RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(void) +{ + PMU_SPI_MEM_MAP(PMU_FREQ_MODE_REG) &= ~(LOW_FREQ_PWM); +} +/*==============================================*/ +/** + * @fn void RSI_IPMU_RetnLdoHpmode(void) + * @brief This API is used to program enabling the RETN_LDO HP MODE . + * @return none + */ + +void RSI_IPMU_RetnLdoHpmode(void) +{ + RSI_IPMU_ProgramConfigData(retn_ldo_hpmode); + RSI_IPMU_ProgramConfigData(retnHP_volt_trim_efuse); +} +/** + * @fn void RSI_IPMU_SCDC_Enable(void) + * @brief This API is used to enable SCDC mode . + * @return none + */ +void RSI_IPMU_SCDC_Enable(void) +{ + RSI_IPMU_ProgramConfigData(ipmu_scdc_enable); +} +/** + * @fn void RSI_IPMU_HP_LDO_Enable(void) + * @brief This API is used to enable LDO mode . + * @return none + */ +void RSI_IPMU_HP_LDO_Enable(void) +{ + RSI_IPMU_ProgramConfigData(hp_ldo_voltsel); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void) + * @brief This API is used to program the trim value for 32Mhz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_M32rc_OscTrimEfuse(void) +{ + system_clocks.rc_mhz_clock = DEFAULT_MHZ_RC_CLOCK; + + if (system_clocks.m4_ref_clock_source == ULP_MHZ_RC_CLK) { + system_clocks.m4ss_ref_clk = DEFAULT_MHZ_RC_CLOCK; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_MHZ_RC_CLK) { + system_clocks.ulpss_ref_clk = DEFAULT_MHZ_RC_CLOCK; + } + + return RSI_IPMU_ProgramConfigData(m32rc_osc_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) + * @brief This API is used to program the trim value for 20MHz RC oscillator + * @return RSI_IPMU_ProgramConfigData on success + */ + +rsi_error_t RSI_IPMU_M20rcOsc_TrimEfuse(void) +{ + rsi_error_t error_status; + + error_status = RSI_IPMU_ProgramConfigData(m20rc_osc_trim_efuse); + + if (error_status == RSI_OK) { + system_clocks.rc_mhz_clock = SYSTEM_CLK_VAL_20MHZ; + if (system_clocks.m4_ref_clock_source == ULP_MHZ_RC_CLK) { + system_clocks.m4ss_ref_clk = SYSTEM_CLK_VAL_20MHZ; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_MHZ_RC_CLK) { + system_clocks.ulpss_ref_clk = SYSTEM_CLK_VAL_20MHZ; + } + } + + return error_status; +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void) + * @brief This API is used to program DBLR 32MHz trim value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_DBLR32M_TrimEfuse(void) +{ + system_clocks.doubler_clock = SYSTEM_CLK_VAL_MHZ; + return RSI_IPMU_ProgramConfigData(dblr_32m_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_M20roOsc_TrimEfuse(void) + * @brief This API is used to program the trim value for 20Mhz RO oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_M20roOsc_TrimEfuse(void) +{ + system_clocks.ro_20mhz_clock = DEFAULT_20MHZ_RO_CLOCK; + if (system_clocks.m4_ref_clock_source == ULP_20MHZ_RINGOSC_CLK) { + system_clocks.m4ss_ref_clk = DEFAULT_20MHZ_RO_CLOCK; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_20MHZ_RINGOSC_CLK) { + system_clocks.ulpss_ref_clk = DEFAULT_20MHZ_RO_CLOCK; + } + return RSI_IPMU_ProgramConfigData(m20ro_osc_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RO32khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 32KHz RO oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RO32khz_TrimEfuse(void) +{ + system_clocks.ro_32khz_clock = DEFAULT_32KHZ_RO_CLOCK; + + return RSI_IPMU_ProgramConfigData(ro_32khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RC16khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 16KHz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RC16khz_TrimEfuse(void) +{ + system_clocks.rc_32khz_clock = 16000; + return RSI_IPMU_ProgramConfigData(rc_16khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RC64khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 64KHz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RC64khz_TrimEfuse(void) +{ + system_clocks.rc_32khz_clock = 64000; + return RSI_IPMU_ProgramConfigData(rc_64khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RC32khz_TrimEfuse(void) + * @brief This API is used to program the trim value for 32KHz RC oscillator . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RC32khz_TrimEfuse(void) +{ + system_clocks.rc_32khz_clock = 32000; + return RSI_IPMU_ProgramConfigData(rc_32khz_trim_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_RO_TsEfuse() + * @brief This API is used to program the nominal_count . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_RO_TsEfuse() +{ + return RSI_APB_ProgramConfigData(ro_ts_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_RO_TsConfig(void) + * @brief This API is used to program the RO Temp sensor slope . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_RO_TsConfig(void) +{ + return RSI_APB_ProgramConfigData(ro_tempsense_config); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Vbattstatus_TrimEfuse(void) + * @brief This API is used to program the trim value for Vbatt status . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Vbattstatus_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(vbatt_status_trim_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Vbg_Tsbjt_Efuse(void) + * @brief This API is used to program the BG voltage for BJT temperature sensor + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Vbg_Tsbjt_Efuse(void) +{ + return RSI_APB_ProgramConfigData(vbg_tsbjt_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcoff_DiffEfuse(void) + * @brief This API is used to program The offset value for AUX ADC differential mode . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Auxadcoff_DiffEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_off_diff_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcgain_DiffEfuse(void) + * @brief This API is used to program The gain value for AUX ADC differential mode . + * @return RSI_APB_ProgramConfigData on success. + */ +uint32_t RSI_IPMU_Auxadcgain_DiffEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_gain_diff_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcoff_SeEfuse(void) + * @brief This API is used to program The offset value for AUX ADC single ended mode . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Auxadcoff_SeEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_off_se_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Auxadcgain_SeEfuse(void) + * @brief This API is used to program The gain value for AUX ADC single mode . + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Auxadcgain_SeEfuse(void) +{ + return RSI_APB_ProgramConfigData(auxadc_gain_se_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Bg_TrimEfuse(void) + * @brief This API is used to program BG trim value. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Bg_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(bg_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Blackout_TrimEfuse(void) + * @brief This API is used to program BLACKOUT thresholds . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Blackout_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(blackout_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_POCbias_Efuse(void) + * @brief This API is used to program the poc bias. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_POCbias_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(poc_bias_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Buck_TrimEfuse(void) + * @brief This API is used to program BUCK value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Buck_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(buck_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Ldosoc_TrimEfuse(void) + * @brief This API is used to program LDO SOC value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Ldosoc_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(ldosoc_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Dpwmfreq_TrimEfuse(void) + * @brief This API is used to program DPWM frequency value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Dpwmfreq_TrimEfuse(void) +{ + return RSI_IPMU_ProgramConfigData(dpwm_freq_trim_efuse); +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_IPMU_Delvbe_Tsbjt_Efuse(void) + * @brief This API is used to program the offset voltage + * @return RSI_APB_ProgramConfigData on success. + */ + +uint32_t RSI_IPMU_Delvbe_Tsbjt_Efuse(void) +{ + return RSI_APB_ProgramConfigData(delvbe_tsbjt_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Xtal1bias_Efuse(void) + * @brief This API is used to program Xtal bias value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Xtal1bias_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(xtal1_bias_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Xtal2bias_Efuse(void) + * @brief This API is used to program Xtal2 bias value . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Xtal2bias_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(xtal2_bias_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_RetnHP_Volttrim_Efuse(void) + * @brief This API is used to program the HP retention voltage . + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_RetnHP_Volttrim_Efuse(void) +{ + return RSI_IPMU_ProgramConfigData(retnHP_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_BOD_ClksCommonconfig1(void) + * @brief This API is used to enable bias currents to BOD. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig1(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config1); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_BOD_ClksCommonconfig2(void) + * @brief This API is used to disable bias currents to BOD. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_BOD_ClksCommonconfig2(void) +{ + return RSI_IPMU_ProgramConfigData(ipmu_bod_clks_common_config2); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Hpldo_volt_trim_efuse(void) + * @brief This API is used to set the LDO to the correct voltage based on E-Fuse. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Hpldo_volt_trim_efuse(void) +{ + return RSI_IPMU_ProgramConfigData(hpldo_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Scdc_volt_trim_efuse(void)) + * @brief This API is used to set the SC-DCDC to the corrrect voltage based on E-Fuse. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Scdc_volt_trim_efuse(void) +{ + return RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_Reconfig_to_SCDCDC(void) + * @brief This API is used to the LDO has to be re-configured into SC-DCDC mode. + * @return none + */ + +void RSI_IPMU_Reconfig_to_SCDCDC(void) +{ + RSI_IPMU_ProgramConfigData(scdc_volt_sel1); + RSI_IPMU_ProgramConfigData(scdc_volt_trim_efuse); + RSI_IPMU_ProgramConfigData(scdc_volt_sel2); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_Lp_scdc_extcapmode(void) + * @brief This API is used to SCDC into the external CAP mode. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_Lp_scdc_extcapmode(void) +{ + return RSI_IPMU_ProgramConfigData(lp_scdc_extcapmode); +} + +/*==============================================*/ +/** + * @fn rsi_error_t RSI_IPMU_BOD_Cmphyst(void) + * @brief This API is used to set the comparator hysteresis. + * @return RSI_IPMU_ProgramConfigData on success. + */ + +rsi_error_t RSI_IPMU_BOD_Cmphyst(void) +{ + return RSI_IPMU_ProgramConfigData(bod_cmp_hyst); +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_32KHzROClkClib(void) + * @brief This API is used to calibrate the 32Khz RO clock to 32khz frequency . + * @return none + */ + +void RSI_IPMU_32KHzROClkClib(void) +{ + uint32_t ro32k_trim = 0; + uint32_t no_of_tst_clk_khz_ro = 0; + + /*Do until clock should be 32KHz */ + do { + /* CLK40M buffer circuit will be ON */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(21); + /* Off controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~BIT(16); + /* RO 32KHz clock enable */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) |= BIT(21); + /* calibrated trim goes to the block */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) &= ~(BIT(15)); + /* Enable the clock gate for npss ref clk &wait for 1us*/ + /* 32KHz RO clock calibration */ + /* Binary search calibration enable signal for low frequency clocks RO and RC */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) |= (BIT(4) | BIT(15) | BIT(21)); + /* wait till bit 21 becomes 1 Indicates calibration done indication*/ + while (!(ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & BIT(21))) + ; + /* Read calibrated trim value after low frequency calibration done */ + ro32k_trim = ((ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & RO_TRIM_VALUE_LF) >> 4); + /*Mask the bits where the trim value need to write */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) &= (uint32_t)(~(MASK32KRO_TRIM_VALUE_WRITE_BITS)); + /* Programming the calibrated trim to SPI register. */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) |= (ro32k_trim << 16); + /* trim given from spi goes to the block */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRO_CLK_REG_OFFSET) |= (BIT(15)); + /* Measures MHz RC clock Clock Frequency */ + no_of_tst_clk_khz_ro = RSI_Clks_Calibration(sleep_clk, khz_ro_clk); + no_of_tst_clk_khz_ro /= 1000; + /* Check if it is less than a particular value */ + if (no_of_tst_clk_khz_ro < PARTICULAR_FREQ_MIN) { + ULP_SPI_MEM_MAP(iPMU_SPARE_REG1_OFFSET) |= BIT(18) | BIT(19); + } + /* Check if it is greater than a particular value */ + if (no_of_tst_clk_khz_ro > PARTICULAR_FREQ_MAX) { + ULP_SPI_MEM_MAP(iPMU_SPARE_REG1_OFFSET) &= ~((BIT(18) | BIT(19))); + } + } while ((no_of_tst_clk_khz_ro < PARTICULAR_FREQ_MIN) || (no_of_tst_clk_khz_ro > PARTICULAR_FREQ_MAX)); + + return; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_32KHzRCClkClib(void) + * @brief This API is used to calibrate the 32Khz RC clock to 32khz frequency. + * @return none + */ + +void RSI_IPMU_32KHzRCClkClib(void) +{ + uint32_t rc32k_trim = 0; + uint32_t no_of_tst_clk_khz_rc = 0; + + /*Do until clock should be 32KHz */ + do { + /* CLK40M buffer circuit will be ON */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(21); + /* Off controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~(BIT(16)); + /* RC 32KHz clock enable */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= BIT(21); + /* calibrated trim goes to the block (changes spi_trim select to 0) */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) &= ~(BIT(11)); + /* Enable the clock gate for npss ref clk &wait for 1us*/ + /* 32KHz RC clock calibration */ + /* Binary search calibration enable signal for low frequency clocks RO and RC */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) |= (BIT(4) | BIT(14) | BIT(21)); + /* wait till bit 21 becomes 1 Indicates calibration done indication*/ + while (!(ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & BIT(21))) + ; + /* Read calibrated trim value after low frequency calibration done */ + rc32k_trim = ((ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & RC_TRIM_VALUE_LF) >> 4); + /*Mask the bits where the trim value need to write */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) &= (uint32_t)~MASK32KRC_TRIM_VALUE_WRITE_BITS; + /* Programming the calibrated trim to SPI register. */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= (rc32k_trim << 14); + /*pointing the trim select to SPI */ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= (BIT(11)); + /* Measures MHz RC clock Clock Frequency */ + no_of_tst_clk_khz_rc = RSI_Clks_Calibration(sleep_clk, khz_rc_clk); + no_of_tst_clk_khz_rc /= 1000; + /* Check if it is less than a particular value */ + if (no_of_tst_clk_khz_rc < PARTICULAR_FREQ_MIN) { + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) |= BIT(12) | BIT(13); + } + /* Check if it is greater than a particular value */ + if (no_of_tst_clk_khz_rc > PARTICULAR_FREQ_MAX) { + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_OFFSET) &= ~((BIT(12) | BIT(13))); + } + } while ((no_of_tst_clk_khz_rc < PARTICULAR_FREQ_MIN) || (no_of_tst_clk_khz_rc > PARTICULAR_FREQ_MAX)); + + return; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq) + * @brief This API is used to trim 32MHz RC clock to required frequency + * @param[in] freq : Input is to get required frequency from 13MHz to 32MHz. + * @return trim value for required MHz RC frequency which we can reserve for further usage . + */ + +uint32_t RSI_Clks_Trim32MHzRC(uint32_t freq) +{ + volatile uint32_t no_oftst_clk_f = 0; + volatile uint32_t no_oftst_clk = 0; + volatile uint32_t reg_read = 0; + volatile uint32_t trim_value = 0; + + system_clocks.rc_mhz_clock = freq; + + if (system_clocks.m4_ref_clock_source == ULP_MHZ_RC_CLK) { + system_clocks.m4ss_ref_clk = freq; + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_MHZ_RC_CLK) { + system_clocks.ulpss_ref_clk = freq; + } + + /*Multiple the input frequency value with 10 e.g:20MHz as 200 */ + freq *= 10; + + /* Measures MHz RC clock Clock Frequency */ + no_oftst_clk = RSI_Clks_Calibration(ulp_ref_clk, none); + no_oftst_clk = no_oftst_clk_f / 100000; + /* Trims MHz RC clock to required frequency */ + if (no_oftst_clk != freq) { + reg_read = ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET); + /* Clears Trim bits(14-20) for RC 32MHz clock */ + reg_read &= (uint32_t)(~(0x7F << TRIM_LSB_MHZ)); + ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET) = reg_read; + /* check's from 20 bit to 14 bit */ + for (volatile uint32_t i = TRIM_MSB_MHZ; i >= TRIM_LSB_MHZ; i--) { + /* Measures MHz RC clock Clock Frequency */ + no_oftst_clk_f = RSI_Clks_Calibration(ulp_ref_clk, none); + /*To get in three digit of Measured frequency value in MHz e.g:20MHz as 200 */ + no_oftst_clk = no_oftst_clk_f / 100000; + /* Halt the process for less than 0.3MHZ even */ + if (freq - no_oftst_clk < MIN_DIFF_FREQ) { + break; + } + /*Check whether the acquired frequency is higher than required frequency + If higher then clear the previous bit and set the present bit */ + if (no_oftst_clk >= freq) { + ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET) &= ~BIT(i + 1); + ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET) |= BIT(i); + } + /* If lesser set the present bit */ + else { + ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET) |= BIT(i); + } + } + } + /* Trim bits(14-20) value for RC 32MHz clock */ + trim_value = ULP_SPI_MEM_MAP(ULPCLKS_MRC_CLK_REG_OFFSET); + trim_value &= (0x7F << TRIM_LSB_MHZ); + trim_value = trim_value >> TRIM_LSB_MHZ; + + return trim_value; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_20M_ROClktrim(uint8_t clkfreq) + * @brief This API is used to trim the 20Mhz RO clock to required frequency. + * @param[in] clkfreq : Input is to get required frequency from 1MHz to 50MHz. + * @return none + */ + +void RSI_IPMU_20M_ROClktrim(uint8_t clkfreq) +{ + volatile uint32_t ro50m_trim = 0; + system_clocks.doubler_clock = (clkfreq * 1000000 * 2); + + system_clocks.ro_20mhz_clock = (clkfreq * 1000000); + + if (system_clocks.m4_ref_clock_source == ULP_20MHZ_RINGOSC_CLK) { + system_clocks.m4ss_ref_clk = (clkfreq * 1000000); + } + if (system_clocks.ulp_ref_clock_source == ULPSS_ULP_20MHZ_RINGOSC_CLK) { + system_clocks.ulpss_ref_clk = (clkfreq * 1000000); + } + /* CLK40M buffer circuit will be ON */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(21); + /* Off controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~BIT(16); + + if (clkfreq > 10) { + /* select input to High frequency RO */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) |= BIT(13); + } else { + /*select input to Low frequency RO */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= ~BIT(13); + } + /* Enable the 50MHZ RO clock */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) |= BIT(21) | BIT(12); + /* powergate enable for calibration domain */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) = ENABLE_CALIB_DOMAIN; + /* Mask the bits to write required frequency for High frequency RO clock */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) &= (uint32_t)~0x3F; + /*It writes that at what frequency the ROMhz need to be trim */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) |= clkfreq; + /* Select the RO50M clock to calibrate */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) = SELECT_RO_CALIB; + /* Waiting for calibration done indication */ + while (!(ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & BIT(20))) + ; + /* Reading calibrated trim value */ + ro50m_trim = ((ULP_SPI_MEM_MAP(ULPCLKS_CALIB_DONE_REG_ADDR) & TRIM_VALUE_BITS) >> 11); + /*Mask the bits where the trim value need to write */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= (uint32_t)~MASK_TRIM_VALUE_WRITE_BITS; + /* Programming the calibrated trim to SPI register. */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) |= (ro50m_trim << 14); + /* pointing the trim select to SPI i.e write default values to that register */ + ULP_SPI_MEM_MAP(ULPCLKS_TRIM_SEL_REG_ADDR) = ULPCLKS_TRIM_SEL_REG_DEFAULT; + /* CLK40M buffer circuit will be OFF */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) &= ~BIT(21); + /* ON controls for clock cleaner are taken from NPSS */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) |= BIT(16); + /* Disable the 50MHZ RO clock */ + ULP_SPI_MEM_MAP(ULPCLKS_HF_RO_CLK_REG_OFFSET) &= ~BIT(21); + + return; +} + +/*==============================================*/ +/** + * @fn uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_type) + * @brief This API is used for Clock Frequency measurement . + * @param[in] inputclk : Select the clock to be calibrated. + * - /ref INPUT_CLOCK_T + * @param[in] sleep_clk_type : Select the type of Khz clock(RO,RC, XTAL) if it is sleep clock. + * - /ref SLEEP_CLOCK_T + * @return Clock Frequency in Hz . + */ + +uint32_t RSI_Clks_Calibration(INPUT_CLOCK_T inputclk, SLEEP_CLOCK_T sleep_clk_type) +{ + volatile uint32_t no_oftst_clk = 0; + + if (inputclk > 10) { + return INVALID_PARAMETERS; + } + + if (inputclk == sleep_clk) { + if (sleep_clk_type == khz_rc_clk) { + M4CLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = khz_rc_clk; + } + if (sleep_clk_type == khz_ro_clk) { + M4CLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = khz_ro_clk; + } + if (sleep_clk_type == khz_xtal_clk) { + M4CLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = khz_xtal_clk; + } + } + /* Select the clock to be calibrated*/ + M4CLK->CLK_CALIB_CTRL_REG1_b.CC_CLKIN_SEL_b = inputclk; + /* number of ref clock cycles to be considered for calibrating */ + M4CLK->CLK_CALIB_CTRL_REG2_b.CC_NUM_REF_CLKS = 39062; + /* Start clock calibration */ + M4CLK->CLK_CALIB_CTRL_REG1_b.CC_START_b = 0x1; + /* Wait until the clock calibration done */ + while (!M4CLK->CLK_CALIB_STS_REG1_b.CC_DONE_b) + ; + + if ((M4CLK->CLK_CALIB_STS_REG1_b.CC_ERROR_b)) { + M4CLK->CLK_CALIB_CTRL_REG1_b.CC_SOFT_RST_b = 0x1; + } + + /*If cc_error is not set then the clock calibration is done. */ + if (!M4CLK->CLK_CALIB_STS_REG1_b.CC_ERROR_b) { + /* number of test clock cycles occurred for the specified number + of ref_clock cycles*/ + no_oftst_clk = M4CLK->CLK_CALIB_STS_REG2_b.CC_NUM_TEST_CLKS; + } + + return no_oftst_clk; +} + +/*==============================================*/ +/** + * @fn void RSI_IPMU_64KHZ_RCClktrim(void) + * @brief This API is used to trim the 64khz RC clock. + * @return none + */ + +void RSI_IPMU_64KHZ_RCClktrim(void) +{ + uint32_t i; + uint32_t status = 0; + + system_clocks.rc_32khz_clock = 64000; + + /*Enables RC clock and changes spi_trim select to 0*/ + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_ADDR) = ENABLE_32KHZ_CLOCK_TRIM; + + /* Enable XTAL clock from NPSS */ + *(volatile uint32_t *)0x41300120 |= BIT(22); + + // Wait for 1ms using a delay loop + for (i = 0; i < 10000; i++) { + // Intentional empty loop body + } + + /* Selects NPSS reference clock to be CLK-40M_SOC */ + ULP_SPI_MEM_MAP(ULPCLKS_REFCLK_REG_ADDR) = NPSS_REF_CLOCK_40MSOC; + + /* Select number of reference cycles to 625(No of clocks of high frequency clocks in 1 cycle of 16KHz clock Default value is 1250)*/ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REF_REG) = NUMBER_HIGH_FRQ_CLOCK; + + /* Pointing RC32KHz clock to NPSS_TESTMODE 0 */ + *(volatile uint32_t *)0x24048610 = BIT(25) | BIT(28); + + /*Configure NPSS_GPIO_0 in mode 6 */ + *(volatile uint32_t *)0x24048610 = 0x0000000E; + + /*Enable the low frequency clock calibration,enable the clock gate for npss ref clk and select the RC32K clock to calibrate */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REG_ADDR) = LOW_FREQ_CLOCK_CAL; + + // Wait for 1us using a delay loop + for (i = 0; i < 100; i++) { + // Intentional empty loop body + } + + /* wait till bit 21 becomes 1 Indicates calibration done indication*/ + while (!(ULP_SPI_MEM_MAP(0x30C) & BIT(21))) + ; + + /* Calibrated trim value and write the calibrated trim into EFUSE */ + status = (ULP_SPI_MEM_MAP(0x30C) >> 4) & 0x7F; + status = ((status << 14) | BIT(11)); + ULP_SPI_MEM_MAP(ULPCLKS_32KRC_CLK_REG_ADDR) |= status; + + /*Restore the original value of reference cycles once calibration is done */ + ULP_SPI_MEM_MAP(ULPCLKS_CALIB_REF_REG) = ORIGINAL_REF_VALUE_AFTER_CAL; +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c new file mode 100644 index 000000000..a4de118a1 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c @@ -0,0 +1,3360 @@ +/******************************************************************************* +* @file rsi_pll.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Includes + +#include "rsi_ccp_user_config.h" +#include +#include "rsi_rom_clks.h" +#ifndef PLL_ROMDRIVER_PRESENT +/** @addtogroup SOC3 +* @{ +*/ +/*==============================================*/ +/** + * @fn boolean_t clk_check_pll_lock(PLL_TYPE_T pllType) + * @brief This API is used to check the lock status of pll + * @param[in] pllType : PLL type + * @return Enable on success + * Disable on failure + */ + +boolean_t clk_check_pll_lock(PLL_TYPE_T pllType) +{ + uint16_t lock = 0; + + if (pllType == SOC_PLL) { + lock = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG13) >> 14; + } else if (pllType == INTF_PLL) { + lock = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG13) >> 14; + } else { + lock = SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG13) >> 14; + } + if (lock & 1) { + return Enable; + } else { + return Disable; + } +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable) + * @brief This API is used to enable SoC-PLL output clock + * @param[in] clkEnable : enable the clock for SoC-PLL output clock + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable SoC-PLL*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) |= PLL_500_CLK_ENABLE; + } else { + /*Disable SoC-PLL*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_CLK_ENABLE)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_set_soc_pll_freq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) + * @brief This API is used to set the Soc PLL clock to particular frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] socPllFreq : SoC PLL frequency for Soc PLL clock to particular frequency + * @param[in] pllRefClk : PLL reference clock for Soc PLL clock to particular frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_set_soc_pll_freq(const M4CLK_Type *pCLK, uint32_t socPllFreq, uint32_t pllRefClk) +{ + uint16_t shiftFac = 0; + uint16_t socPllMulFac = 0; + uint16_t dcoFreq = 0; + uint16_t reg = 0; + uint16_t socPllDivFac = 0; + uint16_t socreg1 = 0x31c9; + uint16_t socreg3 = 0; + uint16_t socPllTvRead = 0; + + /*parameter validation*/ + + if ((pCLK == NULL) || (socPllFreq < SOC_PLL_MIN_FREQUECY) || (socPllFreq > SOC_PLL_MAX_FREQUECY)) { + return INVALID_PARAMETERS; + } + socPllFreq = (socPllFreq / 1000000); + pllRefClk = (pllRefClk / 1000000); + + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (socPllFreq >= 201) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration. */ + clk_soc_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /* Derive the m,n,p values as per the newer table*/ + /* program PLL with derived values */ + /* Wait for PLL lock*/ + if (socPllFreq < 2) { + shiftFac = 7; + } else if (socPllFreq < 3) { + shiftFac = 6; + } else if (socPllFreq < 6) { + shiftFac = 5; + } else if (socPllFreq < 12) { + shiftFac = 4; + } else if (socPllFreq < 23) { + shiftFac = 3; + } else if (socPllFreq < 46) { + shiftFac = 2; + } else if (socPllFreq < 91) { + shiftFac = 1; + } else { + shiftFac = 0; + } + + socPllDivFac = (uint16_t)((1 << shiftFac) - 1); + + socPllMulFac = (uint16_t)(((socPllDivFac + 1) * socPllFreq) - 1); + + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)~LDO_PROG_SOCPLL; + reg |= 1 << 13; + + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + + socreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + /*writing the value into the dco_fix_sel=1*/ + socreg1 |= 1; + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(socPllDivFac << 9 | (pllRefClk - 1) << 3); + socreg1 &= (uint16_t)~PLL_500_M_MASK; + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + + /*Enable */ + clk_soc_pll_clk_set(pCLK); /* wait for lock */ + /* Set and clear(read modify write) PLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + + /* Read the TV value from PLL500CTRLREG12 BIT[15 : 11]*/ + socPllTvRead = (SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if (socPllTvRead <= (M4_BBFF_STORAGE1 & 0x001F)) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration. */ + clk_soc_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } + } else { + /*Older table*/ + if (socPllFreq < 2) { + shiftFac = 7; + } else if (socPllFreq < 4) { + shiftFac = 6; + } else if (socPllFreq < 8) { + shiftFac = 5; + } else if (socPllFreq < 16) { + shiftFac = 4; + } else if (socPllFreq < 32) { + shiftFac = 3; + } else if (socPllFreq < 64) { + shiftFac = 2; + } else if (socPllFreq < 127) { + shiftFac = 1; + } else { + shiftFac = 0; + } + dcoFreq = (uint16_t)(socPllFreq << shiftFac); + socPllMulFac = (uint16_t)((socPllFreq << shiftFac) - 1); + socPllDivFac = (uint16_t)((1 << shiftFac) - 1); + + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + + if (socPllFreq >= 201) { + if ((socPllFreq % 2) == 0) { + socreg3 &= (uint16_t)~FCW_F_MASK; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + } else { + socreg3 |= (8192 << 2); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + } + } + if (dcoFreq >= 251) { + /*clearing the two bits i.e dco_fix_sel*/ + socreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + /*writing the value into the dco_fix_sel=2*/ + socreg1 |= 2; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)~LDO_PROG_SOCPLL; + reg |= 5 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socPllMulFac = ((dcoFreq / 2) - 1); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(socPllDivFac << 9 | (pllRefClk - 1) << 3); + socreg1 &= (uint16_t)~PLL_500_M_MASK; + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else if ((dcoFreq >= 201) && (dcoFreq <= 250)) { + socreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)~LDO_PROG_SOCPLL; + reg |= 5 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socPllMulFac = ((dcoFreq / 2) - 1); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(socPllDivFac << 9 | (pllRefClk - 1) << 3); + socreg1 &= (uint16_t)~PLL_500_M_MASK; + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else { + socreg3 &= (uint16_t)~FCW_F_MASK; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + socreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + socreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)~LDO_PROG_SOCPLL; + reg |= 4 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(socPllDivFac << 9 | (pllRefClk - 1) << 3); + socreg1 &= (uint16_t)~PLL_500_M_MASK; + socreg1 |= (uint16_t)((socPllMulFac << 6) | PLL_500_CLK_ENABLE); // m factor + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } + /*Enable */ + clk_soc_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK, + * boolean_t clk_en, + * uint16_t divFactor, + * uint16_t nFactor, + * uint16_t mFactor, + * uint16_t fcwF, + * uint16_t dcoFixSel, + * uint16_t ldoProg) + * @brief This API is used to configure the SOC PLL clock frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clk_en : enable the clock for SOC PLL clock frequency + * @param[in] divFactor : division factor for SOC PLL clock frequency + * @param[in] nFactor : n number of factor for SOC PLL clock frequency + * @param[in] mFactor : m number of factor for SOC PLL clock frequency + * @param[in] fcwF : frequency for SOC PLL clock frequency + * @param[in] dcoFixSel : fixed select for SOC PLL clock frequency + * @param[in] ldoProg : ldo program for SOC PLL clock frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_set_freq_div(const M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg) +{ + uint16_t socreg1 = 0x31c9; + uint16_t socreg3 = 0; + uint16_t reg = 0; + uint16_t socPllTvRead = 0; + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (clk_en) { + socreg3 &= (uint16_t)~FCW_F_MASK; + socreg3 = (uint16_t)(fcwF << 2); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + socreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + socreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift*/ + reg &= (uint16_t)~LDO_PROG_SOCPLL; + reg |= 1 << 13; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socreg1 |= PLL_500_CLK_ENABLE; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(divFactor << 9 | nFactor << 3); + socreg1 &= (uint16_t)~PLL_500_M_MASK; + socreg1 |= (uint16_t)(mFactor << 6 | PLL_500_CLK_ENABLE); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else { + socreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); /*soc_pll_clk o/p disable */ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } + + /*wait for lock */ + clk_soc_pll_clk_set(pCLK); + /* Set and clear(read modify write) PLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + + /* Read the TV value from PLL500CTRLREG12 BIT[15 : 11]*/ + socPllTvRead = (SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if ((socPllTvRead <= (M4_BBFF_STORAGE1 & 0x001F)) && (divFactor == 0)) { + /*RESET PLL*/ + clk_soc_pll_clk_reset(); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } else { + if (clk_en) { + socreg3 &= (uint16_t)~FCW_F_MASK; + socreg3 = (uint16_t)(fcwF << 2); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG3) = socreg3; + socreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + socreg1 |= dcoFixSel; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); // according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift + reg &= (uint16_t)~LDO_PROG_SOCPLL; + reg |= (uint16_t)(ldoProg << 13); + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + socreg1 |= PLL_500_CLK_ENABLE; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG2) = (uint16_t)(divFactor << 9 | nFactor << 3); + socreg1 &= (uint16_t)~PLL_500_M_MASK; + socreg1 |= (uint16_t)((mFactor << 6) | PLL_500_CLK_ENABLE); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } else { + socreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); // soc_pll_clk o/p disable + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + } + + /*Enable */ + clk_soc_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_set(const M4CLK_Type *pCLK) + * @brief This API is used to Enables the SoC-PLL + * @param[in] pCLK : pointer to the processor clock source + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_set(const M4CLK_Type *pCLK) +{ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG11) = 0xFFFF; + /*Wait for lock*/ + while ((pCLK->PLL_STAT_REG_b.SOCPLL_LOCK) != 1) + ; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_bypass_enable(boolean_t clkEnable) + * @brief This API is used to Enable bypass clock + * @param[in] clkEnable : enable the clock + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_bypass_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable PLL clock*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) |= PLL_500_BYPASS; + } else { + /*Disable PLL clock*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_BYPASS)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_clk_reset(void) + * @brief This API is used to Reset the Soc_pll_clk + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_clk_reset(void) +{ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG11) = 0x01FF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_pd_enable(boolean_t en) + * @brief This API is used to Enable the PdEnable(power down) + * @param[in] en : enable + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_pd_enable(boolean_t en) +{ + if (en == Enable) { + /*Enable power down*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) |= PLL_500_PD; + } else { + /*Disable power down*/ + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_PD)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_turn_off(void) + * @brief This API is used to TurnOff the SOC_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_turn_off(void) +{ + uint16_t socreg1 = 0x31c9; + /*Set PLL PD Bit*/ + socreg1 |= PLL_500_PD; + socreg1 |= PLL_500_RST; + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_soc_pll_turn_on(void) + * @brief This API is used to TurnOn the SOC_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_soc_pll_turn_on(void) +{ + uint16_t socreg1 = 0x31c9; + /*Disable power down */ + socreg1 &= (uint16_t)(~(PLL_500_RST)); + socreg1 &= (uint16_t)(~(PLL_500_PD)); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG1) = socreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_enable(boolean_t clkEnable) + * @brief This API is used to Enable the I2s_PLL output clock + * @param[in] clkEnable : enable the clock for I2s_PLL output clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable SoC-PLL*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= PLL_500_CLK_ENABLE; + } else { + /*Disable SoC-PLL*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) &= (uint16_t)(~(PLL_500_CLK_ENABLE)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_bypass_enable(boolean_t clkEnable) + * @brief This API is used to Enable bypass clock + * @param[in] clkEnable : enable the clock for bypass clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_bypass_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable PLL clock*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= PLL_500_BYPASS; + } else { + /*Disable PLL clock*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) &= (uint16_t)(~(PLL_500_BYPASS)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_pd_enable(boolean_t en) + * @brief This API is used to Enable the PdEnable(power down) + * @param[in] en : enable + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_pd_enable(boolean_t en) +{ + if (en == Enable) { + /*Enable power down*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= PLL_500_PD; + } else { + /*Disable power down*/ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) &= (uint16_t)(~(PLL_500_PD)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_turn_off(void) + * @brief This API is used to TurnOff the I2s_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_turn_off(void) +{ + uint16_t i2sreg1 = 0x1244; + /*Set PLL PD Bit*/ + i2sreg1 |= PLL_500_PD; + i2sreg1 |= PLL_500_RST; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) |= i2sreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_turn_on(void) + * @brief This API is used to TurnOn the I2s_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_turn_on(void) +{ + uint16_t i2sreg1 = 0x1244; + i2sreg1 &= (uint16_t)(~(PLL_500_PD)); + i2sreg1 &= (uint16_t)(~(PLL_500_RST)); + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) = i2sreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_set_i2s_pll_freq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) + * @brief This API is used to set the I2s_pll clock to particular frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] i2sPllFreq : PLL clock of I2S for particular frequency + * @param[in] fXtal : frequency oscillator for particular frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_set_i2s_pll_freq(const M4CLK_Type *pCLK, uint32_t i2sPllFreq, uint32_t fXtal) +{ + uint16_t p_div = 0; + uint16_t u16DivFactor1 = 0; + uint16_t u16DivFactor2 = 0; + uint16_t N = 0; + uint16_t M = 0; + uint16_t FCW_F = 0; + uint32_t fref = 0; + uint32_t Fdco; + float g; + double FCW; + double frac; + uint16_t i2sreg1 = 0x1244; + uint16_t i2sreg2 = 0x5850; + uint16_t i2sreg3 = 0xba60; + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + + if (!((fXtal == 9600000) || (fXtal == 19200000) || (fXtal == 38400000))) { + fref = 1000000; /* One Mega herz steps*/ + } else { + fref = 960000; /* 0.96 Mega herz steps*/ + } + /*Calculating p_div value*/ + g = ((float)I2S_DCO_FREQ1 / (float)i2sPllFreq); + if (g - (float)(int)g == 0) /* checking if the value is an integer */ + { + p_div = (uint16_t)(g); + Fdco = I2S_DCO_FREQ1; + } else { + p_div = (uint16_t)(I2S_DCO_FREQ2 / i2sPllFreq); + Fdco = I2S_DCO_FREQ2; + } + N = (uint16_t)(fXtal / fref); /*calculating N value*/ + /*deriving M and FCW_F value*/ + FCW = (float)Fdco / (float)fref; + M = (uint16_t)FCW; + frac = (FCW - M); + FCW_F = (uint16_t)(frac * (1 << 14)); // (1 << 14) == pow(2, 14) + if (Fdco == I2S_DCO_FREQ1) { + FCW_F = (FCW_F + 1); + } + /*deriving the p_div1 and p_div2 values from p_div value*/ + /*From the refernce of PLL Programming table*/ + if (p_div >= 288) { + u16DivFactor2 = 4; + u16DivFactor1 = ((p_div >> 4) - 1); + } else if ((p_div >= 96) && (p_div <= 144)) { + u16DivFactor2 = 3; + u16DivFactor1 = ((p_div >> 3) - 1); + } else if (p_div == 72) { + u16DivFactor2 = 2; + u16DivFactor1 = ((p_div >> 2) - 1); + } else if ((p_div >= 36) && (p_div <= 48)) { + u16DivFactor2 = 1; + u16DivFactor1 = ((p_div >> 1) - 1); + } else { + u16DivFactor2 = 0; + u16DivFactor1 = (p_div - 1); + } + /*RESET PLL*/ + clk_i2s_pll_clk_reset(); + i2sreg2 &= (uint16_t)~N_DIV_MASK; + i2sreg2 |= (uint16_t)(N << 1); + i2sreg3 &= (uint16_t)~FCW_F_MASK; + i2sreg3 |= (uint16_t)(FCW_F << 2); + i2sreg1 &= (uint16_t)~PLL_500_M_MASK; + i2sreg1 |= (uint16_t)(M << 6); + i2sreg2 &= (uint16_t)~0xff00; + i2sreg2 |= (uint16_t)((u16DivFactor1 << 11) | (u16DivFactor2 << 8)); + i2sreg1 &= (uint16_t)(~PLL_500_PD); + i2sreg1 &= (uint16_t)(~PLL_500_RST); + i2sreg1 |= PLL_500_BYPASS; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) = i2sreg1; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG2) = i2sreg2; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG3) = i2sreg3; + clk_i2s_pll_clk_set(pCLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_set_freq_div(const M4CLK_Type *pCLK, + * uint16_t u16DivFactor1, + * uint16_t u16DivFactor2, + * uint16_t nFactor, + * uint16_t mFactor, + * uint16_t fcwF) + * @brief This API is used to divide I2s_PLL Clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] u16DivFactor1 : division factor of 1 + * @param[in] u16DivFactor2 : division factor of 2 + * @param[in] nFactor : n number of factor for I2s_PLL Clock + * @param[in] mFactor : m number of factor for I2s_PLL Clock + * @param[in] fcwF : frequency for for I2s_PLL Clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_set_freq_div(const M4CLK_Type *pCLK, + uint16_t u16DivFactor1, + uint16_t u16DivFactor2, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF) +{ + uint16_t i2sreg1 = 0x1244; + uint16_t i2sreg2 = 0x5850; + uint16_t i2sreg3 = 0xba60; + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + clk_i2s_pll_clk_reset(); + if (u16DivFactor1) { + i2sreg2 &= (uint16_t)~N_DIV_MASK; + i2sreg2 |= (uint16_t)(nFactor << 1); + i2sreg3 &= (uint16_t)~FCW_F_MASK; + i2sreg3 |= (uint16_t)(fcwF << 2); + i2sreg1 &= (uint16_t)~PLL_500_M_MASK; + i2sreg1 |= (uint16_t)(mFactor << 6); + i2sreg2 &= (uint16_t)~0xff00; + i2sreg2 |= (uint16_t)((u16DivFactor1 << 11) | (u16DivFactor2 << 8)); + i2sreg1 &= (uint16_t)~PLL_500_PD; + i2sreg1 &= (uint16_t)(~PLL_500_RST); + i2sreg1 |= PLL_500_BYPASS; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG1) = i2sreg1; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG2) = i2sreg2; + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG3) = i2sreg3; + } + clk_i2s_pll_clk_set(pCLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK) + * @brief This API is used to set the I2s_pll_clk + * @param[in] pCLK : pointer to the processor clock source + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_set(const M4CLK_Type *pCLK) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG11) = 0xFFFF; + while ((pCLK->PLL_STAT_REG_b.I2SPLL_LOCK) != 1) + ; /* checking for pll lck */ + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_pll_clk_reset(void) + * @brief This API is used to set the I2s_pll_clk + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_pll_clk_reset(void) +{ + SPI_MEM_MAP_PLL(I2S_PLL_CTRL_REG11) = 0x01FF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_enable(boolean_t clkEnable) + * @brief This API is used to Enable the Intf_PLL output clock + * @param[in] clkEnable : enable the clock + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable SoC-PLL*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) |= PLL_500_CLK_ENABLE; + } else { + /*Disable SoC-PLL*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_CLK_ENABLE)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_pd_enable(boolean_t en) + * @brief This API is used to Enable the PdEnable(power down) + * @param[in] en : enable + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_pd_enable(boolean_t en) +{ + if (en == Enable) { + /*Enable power down*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) |= PLL_500_PD; + } else { + /*Disable power down*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_PD)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_turn_off(void) + * @brief This API is used to TurnOff the Intf_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_turn_off(void) +{ + uint16_t intfreg1 = 0x31c9; + /*Set PLL PD Bit*/ + intfreg1 |= PLL_500_PD; + /* setting the bit reset */ + intfreg1 |= PLL_500_RST; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_set_intf_pll_freq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) + * @brief This API is used to set the INTFPLL clock to particular frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] intfPllFreq : input frequency of PLL frequency + * @param[in] pllRefClk : PLL reference clock + * @return RSI_OK on success + */ + +rsi_error_t clk_set_intf_pll_freq(const M4CLK_Type *pCLK, uint32_t intfPllFreq, uint32_t pllRefClk) +{ + uint16_t shiftFac = 0; + uint16_t intfPllMulFac = 0; + uint16_t intfPllDivFac = 0; + uint16_t reg = 0; + uint16_t dcoFreq = 0; + uint16_t intfreg1 = 0x31c9; + uint16_t intfreg3 = 0; + uint16_t intfPllTvRead = 0; + + /*Parameter validation */ + if ((pCLK == NULL) || (intfPllFreq < INTF_PLL_MIN_FREQUECY) || (intfPllFreq > INTF_PLL_MAX_FREQUECY)) { + return INVALID_PARAMETERS; + } + intfPllFreq = (intfPllFreq / 1000000); + pllRefClk = (pllRefClk / 1000000); + + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (intfPllFreq >= 201) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration. */ + clk_intf_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /* Derive the m,n,p values as per the newer table*/ + /* program PLL with derived values */ + /* Wait for PLL lock*/ + if (intfPllFreq < 2) { + shiftFac = 7; + } else if (intfPllFreq < 3) { + shiftFac = 6; + } else if (intfPllFreq < 6) { + shiftFac = 5; + } else if (intfPllFreq < 12) { + shiftFac = 4; + } else if (intfPllFreq < 23) { + shiftFac = 3; + } else if (intfPllFreq < 46) { + shiftFac = 2; + } else if (intfPllFreq < 91) { + shiftFac = 1; + } else { + shiftFac = 0; + } + + intfPllDivFac = (uint16_t)((1 << shiftFac) - 1); + + intfPllMulFac = (uint16_t)(((intfPllDivFac + 1) * intfPllFreq) - 1); + + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)~LDO_PROG_INTFPLL; + reg |= 1 << 10; + + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + + intfreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + /*writing the value into the dco_fix_sel=1*/ + intfreg1 |= 1; + + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)(intfPllDivFac << 9 | (pllRefClk - 1) << 3); + intfreg1 &= (uint16_t)~PLL_500_M_MASK; + intfreg1 |= (uint16_t)((intfPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + + /*Enable */ + clk_intf_pll_clk_set(pCLK); + /* Set and clear(read modify write) INTFPLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + /* Read the TV value from INTFPLL500CTRLREG12 BIT[15 : 11]*/ + intfPllTvRead = (SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if (intfPllTvRead <= ((M4_BBFF_STORAGE1 & 0x03E0) >> 5)) { + /*New table*/ + /* Program PLL to 200Mhz */ + /* Call low level API with m,n,p values for 200Mhz configuration.*/ + clk_intf_pll_set_freq_div(pCLK, 1, 0, 39, 199, 0, 1, 1); + return ERROR_INVALID_INPUT_FREQUENCY; + + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } + + } else { /* older table */ + if (intfPllFreq < 2) { + shiftFac = 7; + } else if (intfPllFreq < 4) { + shiftFac = 6; + } else if (intfPllFreq < 8) { + shiftFac = 5; + } else if (intfPllFreq < 16) { + shiftFac = 4; + } else if (intfPllFreq < 32) { + shiftFac = 3; + } else if (intfPllFreq < 64) { + shiftFac = 2; + } else if (intfPllFreq < 127) { + shiftFac = 1; + } else { + shiftFac = 0; + } + dcoFreq = (uint16_t)(intfPllFreq << shiftFac); + intfPllMulFac = (uint16_t)((intfPllFreq << shiftFac) - 1); + intfPllDivFac = (uint16_t)((1 << shiftFac) - 1); + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + if (intfPllFreq >= 201) { + if ((intfPllFreq % 2) == 0) { + intfreg3 &= (uint16_t)~FCW_F_MASK; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + } else { + intfreg3 |= (8192 << 2); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + } + } + + if (dcoFreq >= 251) { + + intfreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + /*writing the value into the dco_fix_sel=2*/ + intfreg1 |= 2; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); + reg &= (uint16_t)~LDO_PROG_INTFPLL; + reg |= 5 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfPllMulFac = ((dcoFreq / 2) - 1); + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((intfPllDivFac << 9) | ((pllRefClk - 1) << 3)); + intfreg1 &= (uint16_t)~PLL_500_M_MASK; + intfreg1 |= (uint16_t)((intfPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else if ((dcoFreq >= 201) && (dcoFreq <= 250)) { + intfreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)~LDO_PROG_INTFPLL; + reg |= 5 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfPllMulFac = ((dcoFreq / 2) - 1); + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((intfPllDivFac << 9) | ((pllRefClk - 1) << 3)); + intfreg1 &= (uint16_t)~PLL_500_M_MASK; + intfreg1 |= (uint16_t)((intfPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else { + intfreg3 &= (uint16_t)~FCW_F_MASK; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + intfreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + intfreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); + reg &= (uint16_t)~LDO_PROG_INTFPLL; + reg |= 4 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((intfPllDivFac << 9) | ((pllRefClk - 1) << 3)); + intfreg1 &= (uint16_t)~PLL_500_M_MASK; + intfreg1 |= (uint16_t)((intfPllMulFac << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } + /*Enable */ + + clk_intf_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_set_freq_div(const M4CLK_Type *pCLK, + * boolean_t clk_en, + * uint16_t divFactor, + * uint16_t nFactor, + * uint16_t mFactor, + * uint16_t fcwF, + * uint16_t dcoFixSel, + * uint16_t ldoProg) + * @brief This API is used to divide the Intf PLL clock frequency + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clk_en : enable the clock for Intf PLL clock frequency + * @param[in] divFactor : division factor for Intf PLL clock frequency + * @param[in] nFactor : n number of factor for Intf PLL clock frequency + * @param[in] mFactor : m number of factor for Intf PLL clock frequency + * @param[in] fcwF : frequency for Intf PLL clock frequency + * @param[in] dcoFixSel : fixed select for Intf PLL clock frequency + * @param[in] ldoProg : ldo program for Intf PLL clock frequency + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_set_freq_div(const M4CLK_Type *pCLK, + boolean_t clk_en, + uint16_t divFactor, + uint16_t nFactor, + uint16_t mFactor, + uint16_t fcwF, + uint16_t dcoFixSel, + uint16_t ldoProg) +{ + uint16_t intfreg1 = 0x31c9; + uint16_t intfreg3 = 0; + uint16_t reg = 0; + uint16_t intfPllTvRead = 0; + + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + if ((MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) || (M4_BBFF_STORAGE1 & BIT(10))) { + if (clk_en) { + intfreg3 &= (uint16_t)~FCW_F_MASK; + intfreg3 = (uint16_t)(fcwF << 2); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + intfreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + intfreg1 |= 1; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)~LDO_PROG_INTFPLL; + reg |= 1 << 10; + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((divFactor << 9) | (nFactor << 3)); + intfreg1 &= (uint16_t)~PLL_500_M_MASK; + intfreg1 |= (uint16_t)((mFactor << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else { + intfreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; /* soc_pll_clk o/p disable */ + } + /*Enable */ + clk_intf_pll_clk_set(pCLK); + /* Set and clear(read modify write) PLL500CTRLREG7 BIT[4] : TV value will be latched */ + + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) |= SPI_INP_RD_EN; + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG7) &= (uint16_t)(~(SPI_INP_RD_EN)); + + /* Read the TV value from PLL500CTRLREG12 BIT[15 : 11] */ + intfPllTvRead = (SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG12) & 0xF800) >> 11; + + if ((intfPllTvRead <= ((M4_BBFF_STORAGE1 & 0x03E0) >> 5)) && (divFactor == 0)) { + /*RESET PLL*/ + clk_intf_pll_clk_reset(); + return ERROR_INVALID_INPUT_FREQUENCY; + } else { + /*Program the required frequency by user*/ + return RSI_OK; + } + } else { + if (clk_en) { + intfreg3 &= (uint16_t)~FCW_F_MASK; + intfreg3 = (uint16_t)(fcwF << 2); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG3) = intfreg3; + intfreg1 &= (uint16_t)~DCO_FIX_SEL_MASK; + intfreg1 |= dcoFixSel; + reg = SPI_MEM_MAP_PLL(SOCPLLMACROREG3); + reg = (uint16_t)(reg << 1); /* according to RTL bug SOCPLLMACROREG3 (read issue) will shift to one left shift */ + reg &= (uint16_t)~LDO_PROG_INTFPLL; + reg |= (uint16_t)(ldoProg << 10); + SPI_MEM_MAP_PLL(SOCPLLMACROREG3) = reg; + intfreg1 |= PLL_500_CLK_ENABLE; /* soc_pll_clk o/p en */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG2) = (uint16_t)((divFactor << 9) | (nFactor << 3)); + intfreg1 &= (uint16_t)~PLL_500_M_MASK; + intfreg1 |= (uint16_t)((mFactor << 6) | PLL_500_CLK_ENABLE); /* m factor */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + } else { + intfreg1 &= (uint16_t)(~PLL_500_CLK_ENABLE); + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; /* soc_pll_clk o/p disable */ + } + /*Enable */ + clk_intf_pll_clk_set(pCLK); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_bypass_enable(boolean_t clkEnable) + * @brief This API is used to Enable bypass clock + * @param[in] clkEnable : enable the clock + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_bypass_enable(boolean_t clkEnable) +{ + if (clkEnable == Enable) { + /*Enable PLL clock*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) |= PLL_500_BYPASS; + } else { + /*Disable PLL clock*/ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) &= (uint16_t)(~(PLL_500_BYPASS)); + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_turn_on() + * @brief This API is used to TurnOn the Intf_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_turn_on() +{ + uint16_t intfreg1 = 0x31c9; + + intfreg1 &= (uint16_t)(~PLL_500_PD); /* clearing pd */ + intfreg1 &= (uint16_t)(~PLL_500_RST); /* clearing reset */ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG1) = intfreg1; + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_reset(void) + * @brief This API is used to Reset the Intf_PLL + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_reset(void) +{ + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG11) = 0x01FF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_intf_pll_clk_set(const M4CLK_Type *pCLK) + * @brief This API is used to Enable the Intf_PLL + * @param[in] pCLK : pointer to the processor clock source + * @return RSI_OK on success + */ + +rsi_error_t clk_intf_pll_clk_set(const M4CLK_Type *pCLK) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + SPI_MEM_MAP_PLL(INTF_PLL_500_CTRL_REG11) = 0xFFFF; + while ((pCLK->PLL_STAT_REG_b.INTFPLL_LOCK) != 1) + ; // checking for pll lck + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable1(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to Enable the peripheral cloks for SET1 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for SET1 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable1(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_SET_REG1 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable1(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the peripheral cloks for CLR1 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for CLR1 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable1(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_CLEAR_REG1 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to Enable the peripheral cloks for SET2 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for SET2 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_SET_REG2 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the peripheral cloks for CLR2 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for CLR2 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_CLEAR_REG2 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable3(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to Enable the peripheral cloks for SET3 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for SET3 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable3(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_SET_REG3 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable3(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the peripheral cloks for CLR3 register + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for CLR3 register + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable3(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_ENABLE_CLEAR_REG3 = flags; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_disable(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_disable(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG = (pCLK->DYN_CLK_GATE_DISABLE_REG) & (0xFFFFFFFF & ~flags); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_disable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to disable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_disable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG2 = (pCLK->DYN_CLK_GATE_DISABLE_REG2) & (0xFFFFFFFF & ~flags); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_enable(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_enable(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG = (pCLK->DYN_CLK_GATE_DISABLE_REG | flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_dynamic_clk_gate_enable2(M4CLK_Type *pCLK, uint32_t flags) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : pointer to the processor clock source + * @param[in] flags : flags for dynamic clock gate of peripherals + * @return RSI_OK on success + */ + +rsi_error_t clk_dynamic_clk_gate_enable2(M4CLK_Type *pCLK, uint32_t flags) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->DYN_CLK_GATE_DISABLE_REG2 = (pCLK->DYN_CLK_GATE_DISABLE_REG2 | flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_qspi_clk_config(M4CLK_Type *pCLK, + * QSPI_CLK_SRC_SEL_T clkSource, + * boolean_t swalloEn, + * boolean_t OddDivEn, + * uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : clock source for configure the Qspi clocks + * @param[in] swalloEn : enable for Qspi clocks + * @param[in] oddDivEn : enable for Qspi clocks + * @param[in] divFactor : division factor for Qspi clocks + * @return clock spi on success + */ + +rsi_error_t clk_qspi_clk_config(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ + rsi_error_t errorCode = RSI_OK; + + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > QSPI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*disabling the clocks*/ + clk_peripheral_clk_disable(pCLK, QSPI_CLK); + + /*Select clock MUX*/ + switch (clkSource) { + case QSPI_ULPREFCLK: + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = clkSource; + break; + + case QSPI_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x01; + break; + + case QSPI_MODELPLLCLK2: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = 0x02; + break; + + case QSPI_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SEL = clkSource; + break; + + case M4_SOCCLKNOSWLSYNCCLKTREEGATED: + /*incase of qspi in sync with soc*/ + pCLK->CLK_ENABLE_SET_REG3 = QSPI_M4_SOC_SYNC; + break; + + default: + errorCode = INVALID_PARAMETERS; + break; + } + + if (errorCode == RSI_OK) { + /*wait for QSPI clock switched */ + while ((pCLK->PLL_STAT_REG_b.QSPI_CLK_SWITCHED) != true) + ; + + /*update the division factor */ + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + /*Specifies whether QSPI clock is in sync with Soc clock. + Before enabling this make sure that qspi_clk_onehot_enable is 1\92b0 to enable glitch free switching*/ + /*Enable the QSPI clock*/ + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = swalloEn ? ENABLE : DISABLE; + pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = OddDivEn ? ENABLE : DISABLE; + } + clk_peripheral_clk_enable(pCLK, QSPI_CLK, ENABLE_STATIC_CLK); + + return errorCode; +} +#if defined(SLI_SI917B0) || defined(SLI_SI915) +/*==============================================*/ +/** + * @fn rsi_error_t clk_qspi_2_clk_config(M4CLK_Type *pCLK, + * QSPI_CLK_SRC_SEL_T clkSource, + * boolean_t swalloEn, + * boolean_t OddDivEn, + * uint32_t divFactor) + * @brief This API is used to configure the Qspi clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : clock source for configure the Qspi clocks + * @param[in] swalloEn : enable for Qspi clocks + * @param[in] oddDivEn : enable for Qspi clocks + * @param[in] divFactor : division factor for Qspi clocks + * @return clock spi on success + */ + +rsi_error_t clk_qspi_2_clk_config(M4CLK_Type *pCLK, + QSPI_CLK_SRC_SEL_T clkSource, + boolean_t swalloEn, + boolean_t OddDivEn, + uint32_t divFactor) +{ + + rsi_error_t errorCode = RSI_OK; + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > QSPI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*disabling the clocks*/ + clk_peripheral_clk_disable(pCLK, QSPI_2_CLK); + /*Select clock MUX*/ + switch (clkSource) { + case QSPI_ULPREFCLK: + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x00; + break; + + case QSPI_MODELPLLCLK2: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x02; + break; + + case QSPI_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x01; + break; + + case QSPI_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + errorCode = ERROR_CLOCK_NOT_ENABLED; + break; + } + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SEL = 0x03; + break; + + case M4_SOCCLKNOSWLSYNCCLKTREEGATED: + /*incase of qspi in sync with soc*/ + pCLK->CLK_ENABLE_SET_REG1 = QSPI_2_M4_SOC_SYNC; + break; + + default: + errorCode = INVALID_PARAMETERS; + break; + } + if (errorCode == RSI_OK) { + /*wait for QSPI clock switched */ + while ((pCLK->PLL_STAT_REG_b.QSPI_2_CLK_SWITCHED) != 1) + ; + + /*update the division factor */ + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + /*Specifies whether QSPI clock is in sync with Soc clock. + Before enabling this make sure that qspi_clk_onehot_enable is 1\92b0 to enable glitch free switching*/ + /*Enable the QSPI clock*/ + if (swalloEn) { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SWALLOW_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_CLK_SWALLOW_SEL = 0; + } + if (OddDivEn) { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_ODD_DIV_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG6_b.QSPI_2_ODD_DIV_SEL = 0; + } + } + clk_peripheral_clk_enable(pCLK, QSPI_2_CLK, ENABLE_STATIC_CLK); + return errorCode; +} +#endif +/*==============================================*/ +/** +* @fn rsi_error_t clk_ssi_mst_clk_config(M4CLK_Type *pCLK, +* CLK_ENABLE_T clkType, +* SSI_MST_CLK_SRC_SEL_T clkSource, +* uint32_t divFactor) +* @brief This API is used to configure the SSI clocks +* @param[in] pCLK : pointer to the processor clock source +* @param[in] clkType : clock type for SSI clocks +* @param[in] clkSource : cource clock for SSI clocks +* @param[in] divFactor : division factor for SSI clocks +* @return RSI_OK on success +*/ + +rsi_error_t clk_ssi_mst_clk_config(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + SSI_MST_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > SSI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Disable the clock */ + clk_peripheral_clk_disable(pCLK, SSIMST_CLK); + /*Master mode */ + switch (clkSource) { + case SSI_ULPREFCLK: + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x00; + break; + + case SSI_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x01; + break; + + case SSI_MODEMPLLCLK1: + + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x02; + break; + + case SSI_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x03; + break; + + case SSI_MODELPLLCLK2: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x04; + break; + + case M4_SOCCLKFOROTHERCLKS: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_SEL = 0x05; + break; + + default: + return INVALID_PARAMETERS; + } + /*wait for clock switch */ + while ((pCLK->PLL_STAT_REG_b.SSI_MST_SCLK_SWITCHED) != 1) + ; + /*division factor */ + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*Enable the SSI clock */ + clk_peripheral_clk_enable(pCLK, SSIMST_CLK, clkType); + return RSI_OK; +} +#if !defined(SLI_SI917) && !defined(SLI_SI915) + +/*==============================================*/ +/** + * @fn rsi_error_t clk_sd_mem_clk_config(M4CLK_Type *pCLK, boolean_t swalloEn, SDMEM_CLK_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the SdMem clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] swalloEn : enable for SdMem clocks + * @param[in] clkSource : clock source for SdMem clocks + * @param[in] divFactor : division factor for SdMem clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_sd_mem_clk_config(M4CLK_Type *pCLK, + boolean_t swalloEn, + SDMEM_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > SDMEM_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Disable the SDMEM clock*/ + clk_peripheral_clk_disable(pCLK, SD_MEM_CLK); + switch (clkSource) { + case SDMEM_SOCPLLCLK: + /*Check clock is present or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x00; + break; + + case SDMEM_MODEMPLLCLK1: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x01; + break; + + case SDMEM_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x02; + break; + + case M4_SOCCLKFOROTHERCLKSSDMEM: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SEL = 0x03; + break; + + default: + return INVALID_PARAMETERS; + } + /*wait for SD mem clock switch */ + while ((pCLK->PLL_STAT_REG_b.SD_MEM_INTF_CLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_DIV_FAC = divFactor; + if (swalloEn) { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 1; + } else { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 0; + } + /*Enable SD memory clock */ + clk_peripheral_clk_enable(pCLK, SD_MEM_CLK, ENABLE_STATIC_CLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_cci_clk_config(M4CLK_Type *pCLK, CCI_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) + * @brief This API is used to configure the CCI clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock for configure the CCI clocks + * @param[in] clkType : clock type for configure the CCI clocks + * @param[in] divFactor : division factor for configure the CCI clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_cci_clk_config(M4CLK_Type *pCLK, CCI_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > CCI_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Enable CCI clock */ + clk_peripheral_clk_disable(pCLK, CCI_CLK); + /*cci_sync_mode_enable_for_ams = 0 */ + MISC_CFG_MISC_CTRL &= ~CCI_SYNC_MODE; + switch (clkSource) { + case CCI_M4_SOC_CLK_FOR_OTHER_CLKS: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG4_b.CCI_CLK_SEL = 0x00; + break; + + case CCI_INTF_PLL_CLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG4_b.CCI_CLK_SEL = 0x01; + break; + + case CCI_M4_SOC_CLK_NO_SWL_SYNC_CLK_TREE: + /*cci_sync_mode_enable_for_ams = 1*/ + MISC_CFG_MISC_CTRL |= CCI_SYNC_MODE; + break; + default: + return INVALID_PARAMETERS; + } + /*update the division factor */ + pCLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC = divFactor; + /*Enable the CCI clock */ + clk_peripheral_clk_enable(pCLK, CCI_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_can_clk_config(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType) + * @brief This API is used to configure the Can clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor for configure the Can clocks + * @param[in] clkType : clock type for configure the Can clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_can_clk_config(M4CLK_Type *pCLK, uint32_t divFactor, CLK_ENABLE_T clkType) +{ + if ((pCLK == NULL) || (divFactor > CAN_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + clk_peripheral_clk_disable(pCLK, CAN_CLK); + + pCLK->CLK_CONFIG_REG3_b.CAN1_CLK_DIV_FAC = divFactor; + + /*Disable the clock*/ + clk_peripheral_clk_enable(pCLK, CAN_CLK, clkType); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ethernet_clk_config(M4CLK_Type *pCLK, + * boolean_t swalloEn, + * ETHERNET_CLK_SRC_SEL_T clkSource, + * uint32_t divFactor) + * @brief This API is used to configure the PLL_INTF clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] swalloEn : enable for PLL_INTF clock + * @param[in] clkSource : clock source for PLL_INTF clock + * @param[in] divFactor : division factor for PLL_INTF clock + * @return RSI_OK on success + */ + +rsi_error_t clk_ethernet_clk_config(M4CLK_Type *pCLK, + boolean_t swalloEn, + ETHERNET_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > PLL_INTF_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Disable Ethernet clock*/ + pCLK->CLK_ENABLE_CLEAR_REG2 = PLL_INTF_CLK_ENABLE; + if (clkSource == ETH_INTF_PLL_CLK) { + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SEL = 0; + } else { + /*Check clock is present or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SEL = 1; + } + while ((pCLK->PLL_STAT_REG_b.PLL_INTF_CLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_DIV_FAC = divFactor; + if (swalloEn) { + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SWALLOW_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG1_b.PLL_INTF_CLK_SWALLOW_SEL = 0; + } + pCLK->CLK_ENABLE_SET_REG2 = PLL_INTF_CLK_ENABLE; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_cci_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the CCI clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor for CCI clock + * @return RSI_OK on success + */ + +rsi_error_t clk_cci_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG2_b.CCI_CLK_DIV_FAC = divFactor; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_sd_mem_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor) + * @brief This API is used to divide the SDMEM clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] u8SwallowEn : enable for SDMEM clock + * @param[in] divFactor : division factor for SDMEM clock + * @return RSI_OK on success + */ + +rsi_error_t clk_sd_mem_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + + if (u8SwallowEn) { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 1; + } else { + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_SWALLOW_SEL = 0; + } + + /*SDMEM division selection */ + pCLK->SD_MEM_CLOCK_REG_b.SD_MEM_INTF_CLK_DIV_FAC = divFactor; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_usb_clk_config(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor) + * @brief This API is used to configure the USB clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_usb_clk_config(M4CLK_Type *pCLK, USB_CLK_SRC_SEL_T clkSource, uint16_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > USB_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*clock Disable */ + pCLK->CLK_ENABLE_CLEAR_REG3 = USB_PHY_CLK_IN_ENABLE; + switch (clkSource) { + case USB_MEMS_REF_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*mems_ref_clk from Modem PLL*/ + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) |= MEMS_REF_CLK_ENABLE; + pCLK->CLK_CONFIG_REG5_b.USB_CLK_SEL = 0x00; + break; + + case USB_REFERENCE_CLK: + /*Reference clock*/ + pCLK->CLK_CONFIG_REG5_b.USB_CLK_SEL = 0x01; + break; + case USB_PLL_CLK: + /* usb_pll_clk from Modem PLL */ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.USB_CLK_SEL = 0x02; + break; + default: + return INVALID_PARAMETERS; + } + /*Program the division factor */ + pCLK->CLK_CONFIG_REG6_b.USB_PHY_CLK_DIV_FAC = divFactor; + /*clock Enable */ + pCLK->CLK_ENABLE_SET_REG3 = USB_PHY_CLK_IN_ENABLE; + return RSI_OK; +} +#endif + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ct_clk_config(M4CLK_Type *pCLK, CT_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) + * @brief This API is used to configure the CT clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock for CT clocks + * @param[in] clkType : source clock for CT clocks + * @param[in] divFactor : division factor for CT clocks + * @return RSI_OK on success + */ + +rsi_error_t clk_ct_clk_config(M4CLK_Type *pCLK, CT_CLK_SRC_SEL_T clkSource, uint32_t divFactor, CLK_ENABLE_T clkType) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > CT_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Disable SCT clock*/ + clk_peripheral_clk_disable(pCLK, CT_CLK); + switch (clkSource) { + case CT_ULPREFCLK: + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x00; + break; + + case CT_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x01; + break; + + case CT_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x02; + break; + + case M4_SOCCLKFOROTHERCLKSCT: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG5_b.CT_CLK_SEL = 0x03; + break; + default: + return INVALID_PARAMETERS; + } + /*wait for SCT switched */ + while ((pCLK->PLL_STAT_REG_b.CT_CLK_SWITCHED) != 1) + ; + /*Program the division factor */ + pCLK->CLK_CONFIG_REG5_b.CT_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + clk_peripheral_clk_enable(pCLK, CT_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_clk_config(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the I2S clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_clk_config(M4CLK_Type *pCLK, I2S_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > I2S_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + /*Disable the I2S clock */ + clk_peripheral_clk_disable(pCLK, I2SM_CLK); + MISC_CFG_MISC_CTRL1 |= I2S_MASTER_SLAVE_MODE; + if (clkSource == I2S_PLLCLK) { + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, I2S_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 0; + } else { + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 1; + } + + /*Wait for I2S clock switch*/ + while ((pCLK->PLL_STAT_REG_b.I2S_CLK_SWITCHED) != 1) + ; + /*update the division factor */ + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + /*enable the clock*/ + clk_peripheral_clk_enable(pCLK, I2SM_CLK, ENABLE_STATIC_CLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_mcu_clk_cut_config(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the McuClkOut clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_mcu_clk_cut_config(M4CLK_Type *pCLK, MCU_CLKOUT_SRC_SEL_T clkSource, uint32_t divFactor) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor >= MCU_CLKOUT_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + clk_peripheral_clk_disable(pCLK, MCUCLKOUT_CLK); + /*clock out mux select */ + /*apply division factor */ + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_DIV_FAC = (unsigned int)(divFactor & 0x3F); + switch (clkSource) { + case MCUCLKOUT_ULP_MHZ_RC_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x01; + break; + + case MCUCLKOUT_RF_REF_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x02; + break; + + case MCUCLKOUT_MEMS_REF_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) |= MEMS_REF_CLK_ENABLE; + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x03; + break; + + case MCUCLKOUT_ULP_20MHZ_RINGOSC_CLK: + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x04; + break; + + case MCUCLKOUT_ULP_DOUBLER_CLK: + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x05; + break; + + case MCUCLKOUT_ULP_32KHZ_RC_CLK: + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x07; + break; + + case MCUCLKOUT_ULP_32KHZ_XTAL_CLK: + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x08; + break; + + case MCUCLKOUT_ULP_32KHZ_RO_CLK: + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x09; + break; + + case MCUCLKOUT_INTF_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0A; + break; + + case MCUCLKOUT_MODEM_PLL_CLK1: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0B; + break; + + case MCUCLKOUT_MODEM_PLL_CLK2: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0C; + break; + + case MCUCLKOUT_SOC_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0D; + break; + + case MCUCLKOUT_I2S_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, I2S_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0E; + break; + + case MCUCLKOUT_USB_PLL_CLK: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_SEL = 0x0F; + break; + + default: + return INVALID_PARAMETERS; + } + clk_peripheral_clk_enable(pCLK, MCUCLKOUT_CLK, ENABLE_STATIC_CLK); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_m4_soc_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the M4soc clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_m4_soc_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_qspi_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor) + * @brief This API is used to divide the QSPI clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] u8SwallowEn : enable + * @param[in] u8OddDivEn : odd division enable + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_qspi_clk_div(M4CLK_Type *pCLK, boolean_t u8SwallowEn, boolean_t u8OddDivEn, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (u8SwallowEn) { + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_SWALLOW_SEL = 0; + } + if (u8OddDivEn) { + pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG2_b.QSPI_ODD_DIV_SEL = 0; + } + pCLK->CLK_CONFIG_REG1_b.QSPI_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ct_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the CT clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_ct_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG5_b.CT_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_ssi_mst_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the SSI clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_ssi_mst_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG1_b.SSI_MST_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2s_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) + * @brief This API is used to divide the I2S clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_i2s_clk_div(M4CLK_Type *pCLK, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + pCLK->CLK_CONFIG_REG5_b.I2S_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_usart_clk_div(M4CLK_Type *pCLK, EN_USART_T enUsart, boolean_t u8FracDivEn, uint32_t divFactor) + * @brief This API is used to divide the USART/UART clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] enUsart : enable UART + * @param[in] u8FracDivEn : fractional divison enable + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_usart_clk_div(M4CLK_Type *pCLK, EN_USART_T enUsart, boolean_t u8FracDivEn, uint32_t divFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (enUsart == USART1) { + if (u8FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + } else { + if (u8FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + } + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_xtal_clk_config(uint8_t xtalPin) + * @brief This API is used to configure the Xtal clock + * @param[in] xtalPin : oscillator pin + * @return RSI_OK on success + */ + +rsi_error_t clk_xtal_clk_config(uint8_t xtalPin) +{ + if (xtalPin > 4) { + return INVALID_PARAMETERS; + } + switch (xtalPin) { + case 1: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 3; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + + case 2: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 4; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + + case 3: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 5; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + + case 4: + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = 6; + MCU_RET->NPSS_GPIO_CNTRL[xtalPin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = 1; + break; + + default: + // Handle unexpected xtalPin values + // You can log an error, set a default configuration, or take other appropriate actions + break; + } + // enables the XTAL clock + MCU_AON->MCUAON_GEN_CTRLS_b.XTAL_CLK_FROM_GPIO = 1; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_slp_clk_config(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc) + * @brief This API is used to calibrate the sleep clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkEnable : enable the clock + * @param[in] clkSrc : source clock + * @return RSI_OK on success + */ + +rsi_error_t clk_slp_clk_config(M4CLK_Type *pCLK, SLEEP_CLK_SRC_SEL_T clkSrc) +{ + /*Parameter validation */ + if ((pCLK == NULL) || (clkSrc > SLP_MAX_SEL)) { + return INVALID_PARAMETERS; + } + switch (clkSrc) { + case SLP_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b = 1; + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + case SLP_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + /*NOTE: In order to enable the Xtal clk source need to configure the NPSS_GPIO pins + which can be done through clk_xtal_clk_config(uint8_t xtalPin) API i.e we need to call that API first*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b = 1; + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + + case SLP_CLK_GATED: + /* default value i.e, clock is gated*/ + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + + case SLP_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b = 1; + pCLK->CLK_CONFIG_REG4_b.SLEEP_CLK_SEL = clkSrc; + break; + + default: + return INVALID_PARAMETERS; + } + while ((pCLK->PLL_STAT_REG_b.SLEEP_CLK_SWITCHED) != 1) + ; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn uint32_t clk_slp_clk_calib_config(M4CLK_Type *pCLK, uint8_t clkCycles) + * @brief This API is used to calibrate the sleep clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkCycles : clock cycle + * @return pCLK on success + */ + +uint32_t clk_slp_clk_calib_config(M4CLK_Type *pCLK, uint8_t clkCycles) +{ + if (pCLK == NULL || clkCycles > MAX_SLP_CYCLES) { + return INVALID_PARAMETERS; + } + pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_CYCLES = (unsigned int)(clkCycles & 0x03); + /* Start the sleep clock */ + pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_START_b = 1; + /* Wait for calib done */ + while (pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_DONE_b != 1) + ; + /* Return the value */ + return pCLK->SLEEP_CALIB_REG_b.SLP_CALIB_DURATION_b; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_gspi_clk_config(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel) + * @brief This API is used to configure the GSPI Clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSel : clock select + * @return RSI_OK on success + */ + +rsi_error_t clk_gspi_clk_config(M4CLK_Type *pCLK, GSPI_CLK_SRC_SEL_T clkSel) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + /*Disable the clocks*/ + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x07; + /*Without this clk enabled, div_fac and mux select for sclk cannot be programmed) */ + pCLK->CLK_ENABLE_SET_REG2 = GEN_SPI_MST1_HCLK_ENABLE; + + switch (clkSel) { + case GSPI_M4_SOC_CLK_FOR_OTHER_CLKS: + /*M4 SOC Clock for others enable*/ + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x00; + break; + + case GSPI_ULP_REF_CLK: + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x01; + break; + + case GSPI_SOC_PLL_CLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x02; + break; + + case GSPI_MODEM_PLL_CLK2: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x03; + break; + + case GSPI_INTF_PLL_CLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + pCLK->CLK_CONFIG_REG1_b.GEN_SPI_MST1_SCLK_SEL = 0x04; + break; + } + /*Wait for GSPI switched */ + while ((pCLK->PLL_STAT_REG_b.GEN_SPI_MST1_SCLK_SWITCHED) != 1) + ; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_i2c_clk_config(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C) + * @brief This API is used to configure the I2C clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkEnable : module for I2C clock + * @param[in] enI2C : enable I2C bus for I2C clock + * @return RSI_OK on success + */ + +rsi_error_t clk_i2c_clk_config(M4CLK_Type *pCLK, boolean_t clkEnable, EN_I2C_T enI2C) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (enI2C == I2C1_INSTAN) { + if (clkEnable) { + /*I2C 1 bus clock enable*/ + pCLK->CLK_ENABLE_SET_REG2 = I2C_BUS_CLK_ENABLE; + /*I2C clk enable */ + pCLK->CLK_ENABLE_SET_REG3 = I2C_CLK_ENABLE; + } else { + /*I2C bus clock disable*/ + pCLK->CLK_ENABLE_CLEAR_REG2 = I2C_BUS_CLK_ENABLE; + /*I2C clk disable */ + pCLK->CLK_ENABLE_CLEAR_REG3 = I2C_CLK_ENABLE; + } + } else { + if (clkEnable) { + /*I2C2 bus clock enable*/ + pCLK->CLK_ENABLE_SET_REG2 = I2C_2_BUS_CLK_ENABLE; + /*I2C2 clk enable */ + pCLK->CLK_ENABLE_SET_REG3 = I2C_2_CLK_ENABLE; + } else { + /*I2C2 bus clock disable*/ + pCLK->CLK_ENABLE_CLEAR_REG2 = I2C_2_BUS_CLK_ENABLE; + /*I2C2 clk disable */ + pCLK->CLK_ENABLE_CLEAR_REG3 = I2C_2_CLK_ENABLE; + } + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_enable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] module : module for particular clock + * @param[in] clkType : clock type for particular clock + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_enable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) +{ + /*valid parameter check*/ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case USART1_CLK: + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = (USART1_SCLK_ENABLE | USART1_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART1_SCLK_ENABLE | USART1_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case USART2_CLK: + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = (USART2_SCLK_ENABLE | USART2_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART2_SCLK_ENABLE | USART2_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case SSIMST_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG2 = (SSI_MST_SCLK_ENABLE | SSI_MST_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG2 = (SSI_MST_SCLK_ENABLE | SSI_MST_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_MST_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case SSISLAVE_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG2 = (SSI_SLV_SCLK_ENABLE | SSI_SLV_PCLK_ENABLE); + } else { + pCLK->CLK_ENABLE_CLEAR_REG2 = (SSI_SLV_SCLK_ENABLE | SSI_SLV_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_SCLK_DYN_CTRL_DISABLE_b = 0; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + + case CT_CLK: + pCLK->CLK_ENABLE_SET_REG1 = CT_CLK_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = CT_PCLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = CT_PCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG2_b.CT_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; +#if !defined(SLI_SI917) && !defined(SLI_SI915) + case SD_MEM_CLK: + pCLK->CLK_ENABLE_SET_REG1 = SD_MEM_INTF_CLK_ENABLE; + break; + + case CCI_CLK: + pCLK->CLK_ENABLE_SET_REG1 = (CCI_CLK_ENABLE | CCI_HCLK_ENABLE); + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG1 = CCI_PCLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = CCI_PCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.CCI_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case CAN_CLK: + /*Enable the clock */ + pCLK->CLK_ENABLE_SET_REG2 = CAN1_CLK_ENABLE; + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + if (clkType == ENABLE_STATIC_CLK) { + pCLK->CLK_ENABLE_SET_REG2 = CAN1_PCLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG2 = CAN1_PCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG2_b.CAN1_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; +#endif + case QSPI_CLK: + pCLK->CLK_ENABLE_SET_REG2 = (QSPI_CLK_ENABLE | QSPI_HCLK_ENABLE); + pCLK->CLK_ENABLE_SET_REG3 = QSPI_CLK_ONEHOT_ENABLE; + break; +#if defined(SLI_SI917B0) || defined(SLI_SI915) + case QSPI_2_CLK: + pCLK->CLK_ENABLE_SET_REG1 = (QSPI_2_CLK_ENABLE | QSPI_2_HCLK_ENABLE); + pCLK->CLK_ENABLE_SET_REG1 = QSPI_2_CLK_ONEHOT_ENABLE; + break; +#endif + case RPDMA_CLK: + pCLK->CLK_ENABLE_SET_REG1 = RPDMA_HCLK_ENABLE; + break; + case UDMA_CLK: + pCLK->CLK_ENABLE_SET_REG2 = UDMA_HCLK_ENABLE; + break; + case PWM_CLK: + pCLK->CLK_ENABLE_SET_REG2 = MCPWM_PCLK_ENABLE; + break; + case GSPI_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_ENABLE_SET_REG2 = GEN_SPI_MST1_HCLK_ENABLE; + break; + case EGPIO_CLK: + pCLK->CLK_ENABLE_SET_REG3 = EGPIO_CLK_ENABLE; + pCLK->CLK_ENABLE_SET_REG2 = EGPIO_PCLK_ENABLE; + break; + case ETHERNET_CLK: + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + pCLK->CLK_ENABLE_SET_REG1 = ETH_HCLK_ENABLE; + break; + case MCUCLKOUT_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_ENABLE = 1; + break; + case HWRNG_CLK: + pCLK->CLK_ENABLE_SET_REG1 = HWRNG_PCLK_ENABLE; + break; + case I2SM_CLK: + pCLK->CLK_ENABLE_SET_REG2 = (I2SM_INTF_SCLK_ENABLE | I2SM_SCLK_ENABLE | I2SM_PCLK_ENABLE | I2SM_SCLK_ENABLE); + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_peripheral_clk_disable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module) + * @brief This API is used to disable the particular clock + * @param[in] pCLK : pointer to the processor clock source + * @param[in] module : module + * @return RSI_OK on success + */ + +rsi_error_t clk_peripheral_clk_disable(M4CLK_Type *pCLK, PERIPHERALS_CLK_T module) +{ + /*valid parameter check*/ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case USART1_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART1_SCLK_ENABLE | USART1_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_SCLK_DYN_CTRL_DISABLE_b = 1; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART1_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case USART2_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = (USART2_SCLK_ENABLE | USART2_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_SCLK_DYN_CTRL_DISABLE_b = 1; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.USART2_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case SSIMST_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = SSI_MST_SCLK_ENABLE; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + case SSISLAVE_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = (SSI_SLV_SCLK_ENABLE | SSI_SLV_PCLK_ENABLE); + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_SCLK_DYN_CTRL_DISABLE_b = 1; + pCLK->DYN_CLK_GATE_DISABLE_REG_b.SSI_SLV_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case CT_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = CT_CLK_ENABLE; + break; + case SD_MEM_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = SD_MEM_INTF_CLK_ENABLE; + break; + case CCI_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = CCI_CLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + break; + case QSPI_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = QSPI_CLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG3 = (QSPI_CLK_ONEHOT_ENABLE | QSPI_M4_SOC_SYNC); + break; +#if defined(SLI_SI917B0) || defined(SLI_SI915) + case QSPI_2_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = QSPI_2_CLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG1 = (QSPI_2_CLK_ONEHOT_ENABLE | QSPI_2_M4_SOC_SYNC); + break; +#endif + case RPDMA_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = RPDMA_HCLK_ENABLE; + break; + case UDMA_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = UDMA_HCLK_ENABLE; + break; + case PWM_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = MCPWM_PCLK_ENABLE; + break; + case CAN_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = CAN1_CLK_ENABLE; + break; + case GSPI_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = GEN_SPI_MST1_HCLK_ENABLE; + break; + case EGPIO_CLK: + pCLK->CLK_ENABLE_CLEAR_REG2 = EGPIO_PCLK_ENABLE; + pCLK->CLK_ENABLE_CLEAR_REG3 = EGPIO_CLK_ENABLE; + break; + case ETHERNET_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = ETH_HCLK_ENABLE; + break; + case MCUCLKOUT_CLK: + pCLK->CLK_CONFIG_REG3_b.MCU_CLKOUT_ENABLE = 0; + break; + case HWRNG_CLK: + pCLK->CLK_ENABLE_CLEAR_REG1 = HWRNG_PCLK_ENABLE; + break; + case I2SM_CLK: +#if !defined(SLI_SI917) && !defined(SLI_SI915) + pCLK->DYN_CLK_GATE_DISABLE_REG_b.I2SM_INTF_SCLK_DYN_CTRL_DISABLE_b = 1; +#endif + pCLK->CLK_ENABLE_CLEAR_REG2 = (I2SM_INTF_SCLK_ENABLE | I2SM_SCLK_ENABLE); + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn void clk_config_pll_ref_clk(uint8_t ref_clk_src) + * @brief This API is used to Configures the PLL lock configurations + * @param[in] ref_clk_src : reference clock source + * @return none + */ + +void clk_config_pll_ref_clk(uint8_t ref_clk_src) +{ + uint32_t reg_read = 0; + reg_read = SPI_MEM_MAP_PLL(SOCPLLMACROREG2); + reg_read &= ~((uint16_t)(0x3 << 14)); + reg_read |= (ref_clk_src << 14U); + SPI_MEM_MAP_PLL(SOCPLLMACROREG2) = (uint16_t)reg_read; +} +#endif //PLL_ROMDRIVER_PRESENT + +#if !defined(CHIP_9118) || !defined(A11_ROM) || !defined(PLL_ROMDRIVER_PRESENT) + +/*==============================================*/ +/** + * @fn void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit) + * @brief This API is used to Configures the PLL lock configurations + * @param[in] manual_clock : manual clock + * @param[in] bypass_manual_clock : bypass manual clock + * @param[in] mm_count_limit : count limit + * @return none + */ + +void clk_config_pll_lock(boolean_t manual_lock, boolean_t bypass_manual_lock, uint8_t mm_count_limit) +{ + uint32_t reg_read = 0; + reg_read = SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9); + reg_read &= ~((0xFF << 6) | BIT(15) | BIT(14)); + reg_read |= (uint32_t)((manual_lock << 15U) | (bypass_manual_lock << 14U) | (mm_count_limit << 6U)); + SPI_MEM_MAP_PLL(SOC_PLL_500_CTRL_REG9) = (uint16_t)reg_read; +} +#endif + +/*==============================================*/ +/** + * @fn uint32_t RSI_CLK_CheckPresent(const M4CLK_Type *pCLK ,CLK_PRESENT_T clkPresent) + * @brief This API is used to enable the dynamic clock gate for peripherals + * @param[in] pCLK : Pointer to the pll register instance \ref M4CLK_Type + * @param[in] clkPresent : structure variable of CLK_PRESENT_T , \ref CLK_PRESENT_T + * @return zero on success + * RSI_OK on error error code + * ERROR_CLOCK_NOT_ENABLED + */ + +uint32_t RSI_CLK_CheckPresent(const M4CLK_Type *pCLK, CLK_PRESENT_T clkPresent) +{ + uint32_t errorReturn = 0; + switch (clkPresent) { + case SOC_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.SOCPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + case INTF_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.INTFPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + case I2S_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.I2SPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + case MODEM_PLL_CLK_PRESENT: + if (pCLK->PLL_STAT_REG_b.MODEMPLL_LOCK == 1) { + errorReturn = RSI_OK; + } else { + errorReturn = ERROR_CLOCK_NOT_ENABLED; + } + break; + } + return errorReturn; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_m4ss_ref_clk_config(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) + * @brief This API is used to configure the m4ss_ref clocks + * @param[in] pCLK is pointer to the processor clock source + * @param[in] clkSource is source clock + * @return RSI_OK on success + */ + +rsi_error_t clk_m4ss_ref_clk_config(const M4CLK_Type *pCLK, M4SS_REF_CLK_SEL_T clkSource) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + + switch (clkSource) { + case ULP_MHZ_RC_BYP_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = clkSource; + system_clocks.m4_ref_clock_source = clkSource; + system_clocks.m4ss_ref_clk = system_clocks.byp_rc_ref_clock; + break; + + case ULP_MHZ_RC_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = clkSource; + system_clocks.m4_ref_clock_source = clkSource; + system_clocks.m4ss_ref_clk = system_clocks.rc_mhz_clock; + break; + + case EXT_40MHZ_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = clkSource; + system_clocks.m4_ref_clock_source = clkSource; + system_clocks.m4ss_ref_clk = system_clocks.rf_ref_clock; + break; + + case MEMS_REF_CLK: + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) = MEMS_REF_CLK_ENABLE; + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = clkSource; + system_clocks.m4_ref_clock_source = clkSource; + system_clocks.m4ss_ref_clk = system_clocks.mems_ref_clock; + break; + + case ULP_20MHZ_RINGOSC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = clkSource; + system_clocks.m4_ref_clock_source = clkSource; + system_clocks.m4ss_ref_clk = system_clocks.ro_20mhz_clock; + break; + + case ULP_DOUBLER_CLK: + /*6: ulp_doubler_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.M4SS_REF_CLK_SEL = clkSource; + system_clocks.m4_ref_clock_source = clkSource; + system_clocks.m4ss_ref_clk = system_clocks.doubler_clock; + break; + + default: + return INVALID_PARAMETERS; + } + + /*wait for clock switched*/ + while ((pCLK->PLL_STAT_REG_b.ULP_REF_CLK_SWITCHED) != true) + ; + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type) + * @brief This API is used to enable the ULP reference clocks and provide delay for clock starting + * @param[in] clk_Type : clock type + * @return RSI_OK on success + */ + +rsi_error_t ulpss_disable_ref_clks(REF_CLK_ENABLE_T clk_type) +{ + /*Select clock source*/ + switch (clk_type) { + case MCU_ULP_40MHZ_CLK_EN: + /*Cleaners are disabled */ + *(volatile uint32_t *)0x2404811C |= (BIT(7) | BIT(23)); + *(volatile uint32_t *)0x2404811C &= ~(BIT(8) | BIT(24)); /////// API with XTAL Clock disabled /////// + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_40MHZ_CLK_EN_b = 0; + break; + + case MCU_ULP_DOUBLER_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_DOUBLER_CLK_EN_b = 0; + break; + + case MCU_ULP_20MHZ_RING_OSC_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b = 0; + break; + + case MCU_ULP_MHZ_RC_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_MHZ_RC_CLK_EN_b = 0; + break; + + case MCU_ULP_32KHZ_XTAL_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b = 0; + break; + case MCU_ULP_32KHZ_RO_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b = 0; + break; + + case MCU_ULP_32KHZ_RC_CLK_EN: + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b = 0; + break; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t clk_m4_soc_clk_config(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor) + * @brief This API is used to configure the m4_soc clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkSource : source clock + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_m4_soc_clk_config(M4CLK_Type *pCLK, M4_SOC_CLK_SRC_SEL_T clkSource, uint32_t divFactor) +{ + /*check valid parameters*/ + if ((pCLK == NULL) || (divFactor >= SOC_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Added for MCU 100 MHz variant mode setting + * Clock will be max/2 in this mode*/ + if (MCU_RET->CHIP_CONFIG_MCU_READ_b.LIMIT_M4_FREQ_110MHZ_b == 1) { + divFactor = divFactor / 2; + } + /*Selects one of the clock sources for M4 SoC clock*/ + switch (clkSource) { + case M4_ULPREFCLK: + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.m4ss_ref_clk; + break; + + case M4_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.soc_pll_clock; + break; + + case M4_MODEMPLLCLK1: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.modem_pll_clock; + break; + + case M4_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.intf_pll_clock; + break; + + case M4_SLEEPCLK: + /*Check clock is present is or not before switching*/ + if (ULPCLK->M4LP_CTRL_REG_b.ULP_M4_CORE_CLK_ENABLE_b == 1) { + /*Update the clock MUX*/ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_SEL = clkSource; + } else { + /*If clock is not presented return the error */ + return ERROR_CLOCK_NOT_ENABLED; + } + SystemCoreClock = system_clocks.sleep_clock; + break; + default: + return INVALID_PARAMETERS; + } + /*wait for clock switched*/ + while ((pCLK->PLL_STAT_REG_b.M4_SOC_CLK_SWITCHED) != 1) + ; + /*update the division factor */ + pCLK->CLK_CONFIG_REG5_b.M4_SOC_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + + if (divFactor) { + SystemCoreClock /= divFactor; + } + system_clocks.soc_clock = SystemCoreClock; + return RSI_OK; +} + +#if defined(CHIP_9118) || !defined(A11_ROM) || !defined(PLL_ROMDRIVER_PRESENT) + +/*==============================================*/ +/** + * @fn rsi_error_t clk_usart_clk_config(M4CLK_Type *pCLK, + * CLK_ENABLE_T clkType, + * boolean_t FracDivEn, + * EN_USART_T enUsart, + * USART_CLK_SRC_SEL_T clkSource, + * uint32_t divFactor) + * @brief This API is used to configure the Usart clocks + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkType : enable the clock + * @param[in] FracDivEn : fractional clock divider + * @param[in] enUsart : used for enable Usart + * @param[in] clkSource: clock source + * @param[in] divFactor : division factor + * @return RSI_OK on success + */ + +rsi_error_t clk_usart_clk_config(M4CLK_Type *pCLK, + CLK_ENABLE_T clkType, + boolean_t FracDivEn, + EN_USART_T enUsart, + USART_CLK_SRC_SEL_T clkSource, + uint32_t divFactor) +{ + + /*Parameter validation */ + if ((pCLK == NULL) || (divFactor > USART_MAX_CLK_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + + /*Disable the USART clock*/ + if (enUsart == USART1) { + RSI_CLK_PeripheralClkDisable(pCLK, USART1_CLK); + } else { + RSI_CLK_PeripheralClkDisable(pCLK, USART2_CLK); + } + /*Select clock MUX*/ + switch (clkSource) { + case USART_ULPREFCLK: + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x00; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x00; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*fractional clock divider select */ + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case USART_MODELPLLCLK2: + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, MODEM_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x02; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x02; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*fractional clock divider select */ + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case USART_INTFPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, INTF_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x03; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*fractional clock divider select */ + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x03; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case USART_SOCPLLCLK: + /*Check clock is present is or not before switching*/ + if (RSI_OK != RSI_CLK_CheckPresent(pCLK, SOC_PLL_CLK_PRESENT)) { + return ERROR_CLOCK_NOT_ENABLED; + } + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x01; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x01; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + + case M4_SOCCLKFOROTHERCLOCKS: + + if (enUsart == USART1) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_SEL = 0x04; + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART1_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART1_SCLK_FRAC_SEL = 1; + } + } else if (enUsart == USART2) { + /*select the MUX for the USART 1*/ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_SEL = 0x04; + pCLK->CLK_ENABLE_SET_REG3 = M4_SOC_CLK_FOR_OTHER_ENABLE; + /*Wait for the clock MUX switch status */ + while ((pCLK->PLL_STAT_REG_b.USART2_SCLK_SWITCHED) != 1) + ; + /*Update the division factor */ + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_DIV_FAC = (unsigned int)(divFactor & 0x0F); + /*fractional clock divider select */ + if (FracDivEn) { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 0; + } else { + pCLK->CLK_CONFIG_REG2_b.USART2_SCLK_FRAC_SEL = 1; + } + } + break; + default: + return INVALID_PARAMETERS; + } + /*Enable USART clock */ + if (enUsart == USART1) { + RSI_CLK_PeripheralClkEnable(pCLK, USART1_CLK, clkType); + } else { + RSI_CLK_PeripheralClkEnable(pCLK, USART2_CLK, clkType); + } + return RSI_OK; +} +#endif + +/*==============================================*/ +/** +* @fn rsi_error_t ulpss_enable_ref_clks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn) +* @brief This API is used to enable the ULP reference clocks and provide delay for clock starting +* @param[in] enable : enable +* @param[in] srcType : source type +* @param[in] delayFn : delay function +* @return RSI_OK on success +*/ + +rsi_error_t ulpss_enable_ref_clks(REF_CLK_ENABLE_T enable, SRC_TYPE_T srcType, cdDelay delayFn) +{ + /*Select clock source*/ + switch (enable) { + case MCU_ULP_40MHZ_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_40MHZ_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_40MHZ_CLK_EN_b = 1; + } + /*Wait for the time out only in case of ULP processor clock configuration */ + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_40MHZ_CLK_EN_TRUN_ON_DELAY, delayFn); + } + /*Cleaners are Enabled */ + *(volatile uint32_t *)0x2404811C &= ~(BIT(7) | BIT(23)); /////// API with XTAL Clock disabled /////// + *(volatile uint32_t *)0x2404811C |= (BIT(8) | BIT(24)); /////// API with XTAL Clock disabled /////// + break; + case MCU_ULP_DOUBLER_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_DOUBLER_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*NOTE : 320Mhz RC is interdependent on Doubler clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b = 1; + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_DOUBLER_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_DOUBLER_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + + case MCU_ULP_20MHZ_RING_OSC_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_20MHZ_RING_OSC_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_20MHZ_RING_OSC_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + case MCU_ULP_MHZ_RC_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_MHZ_RC_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock*/ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_MHZ_RC_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_MHZ_RC_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + case MCU_ULP_32KHZ_XTAL_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /* Program the IPMU structure */ + + /* Enable the clock source from NPSS */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_XTAL_CLK_EN_b = 1; + + /*Wait for 0.5 sec delay*/ + _usdelay(MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_1, delayFn); + + /* Program the IPMU structure */ + + /* Wait for clock source to be enabled for 1.5 seconds */ + _usdelay(MCU_ULP_32KHZ_XTAL_CLK_EN_TRUN_ON_DELAY_2, delayFn); + } + break; + + case MCU_ULP_32KHZ_RO_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RO_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_32KHZ_RO_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + case MCU_ULP_32KHZ_RC_CLK_EN: + if (MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b == 1) { + /*Clock is enabled by default*/ + /*Do Nothing*/ + } else { + /*Enable the clock source */ + MCU_FSM->MCU_FSM_CLK_ENS_AND_FIRST_BOOTUP_b.MCU_ULP_32KHZ_RC_CLK_EN_b = 1; + } + if (srcType == ULP_PROCESSOR_CLK) { + /*wait for clock source is enabled*/ + _usdelay(MCU_ULP_32KHZ_RC_CLK_EN_TRUN_ON_DELAY, delayFn); + } + break; + } + return RSI_OK; +} +/** @} */ + +/* End of file not truncated */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c new file mode 100644 index 000000000..c04cff17f --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c @@ -0,0 +1,1171 @@ +/******************************************************************************* +* @file rsi_ulpss_clk.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// Includes + +#include "rsi_ccp_user_config.h" +#include "rsi_rom_ulpss_clk.h" +#ifndef ULPSS_CLOCK_ROMDRIVER_PRESENT +/** @addtogroup SOC3 +* @{ +*/ +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor) + * @brief This API is used to select the ULPSS processor clock source when input is soc clk source which is greater than 100MHz + * @param[in] pCLK : pointer to the processor clock source + * @param[in] clkEnable : clock enable for clock source + * @param[in] divFactor : division factor for clock to configure Reg 4 + * @param[in] oddDivFactor : odd divison factor for clock to configure Reg 5 + * @return RSI_OK on success + */ + +rsi_error_t ulpss_clock_config(M4CLK_Type *pCLK, boolean_t clkEnable, uint16_t divFactor, boolean_t oddDivFactor) +{ + if (pCLK == NULL) { + return INVALID_PARAMETERS; + } + if (clkEnable == Enable) { + pCLK->CLK_CONFIG_REG4_b.ULPSS_CLK_DIV_FAC = (unsigned int)(divFactor & 0x3F); + pCLK->CLK_CONFIG_REG5_b.ULPSS_ODD_DIV_SEL = (unsigned int)(oddDivFactor & 0x01); + pCLK->CLK_ENABLE_SET_REG1 = ULPSS_CLK_ENABLE; + } else { + pCLK->CLK_ENABLE_CLEAR_REG1 = ULPSS_CLK_ENABLE; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_peri_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to enable different peripherial clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock + * @param[in] u32Flags : flags for perpheral clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_peri_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_MISC_SOFT_SET_REG = (pULPCLK->ULP_MISC_SOFT_SET_REG | u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_peri_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to disable different peripherial clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] u32Flags : flags for peripheral clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_peri_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_MISC_SOFT_SET_REG = (pULPCLK->ULP_MISC_SOFT_SET_REG & ~u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_dyn_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to enable different dynamic clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] u32Flags : flags for dynamic clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_dyn_clk_enable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE = (pULPCLK->ULP_DYN_CLK_CTRL_DISABLE | u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_dyn_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) + * @brief This API is used to disable different dynamic clocks in ULPSS + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] u32Flags : flags for dynamic clocks + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_dyn_clk_disable(ULPCLK_Type *pULPCLK, uint32_t u32Flags) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE = (pULPCLK->ULP_DYN_CLK_CTRL_DISABLE & ~u32Flags) & 0xFFFFFFFF; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_ssi_clk_config(ULPCLK_Type *pULPCLK, + * CLK_ENABLE_T clkType, + * ULP_SSI_CLK_SELECT_T clkSource, + * uint16_t divFactor) + * @brief This API is used to configure the SSI clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for SSI clock source + * @param[in] clkSource : clock source for ULP SSI + * @param[in] divFactor : divison factor for ULP SSI + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_ssi_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + ULP_SSI_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_SSI_MAX_DIVISION_FACTOR) || (clkSource > ULP_SSI_MAX_SEL)) { + return INVALID_PARAMETERS; + } + + ulpss_peripheral_disable(pULPCLK, ULP_SSI_CLK); + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_SSI_REF_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_40MHZ_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_SSI_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_SSI_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_SSI_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + /*NOTE: In order to enable the Xtal clk source need to configure the NPSS_GPIO pins + which can be done through clk_xtal_clk_config(uint8_t xtalPin) API i.e we need to call that API first*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*4: ulp_mhz_rc_clk*/ + case ULP_SSI_ULP_MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_SSI_ULP_20MHZ_RO_CLK: + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + case ULP_SSI_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_SEL = clkSource; + break; + + default: + return INVALID_PARAMETERS; + } + + /* Wait for clock switched */ + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_SSI_b != 1) + ; + + /*Update the division factor */ + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_DIV_FACTOR = (unsigned int)(divFactor & 0x7F); + + ulpss_peripheral_enable(pULPCLK, ULP_SSI_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor) + * @brief This API is used to configure the I2S clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for ULP I2S + * @param[in] clkSource : clock source for ULP I2S + * @param[in] divFactor : divison factor for ULP I2S + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_i2s_clk_config(ULPCLK_Type *pULPCLK, ULP_I2S_CLK_SELECT_T clkSource, uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_I2S_MAX_DIVISION_FACTOR) || (clkSource > ULP_I2S_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_I2S_CLK); + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_I2S_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_I2S_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_I2S_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_I2S_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*4: ulp_mhz_rc_clk*/ + case ULP_I2S_ULP_MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_I2S_ULP_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + case ULP_I2S_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + case ULP_I2S_ULP_DOUBLER_CLK: + /*7: ulp_doubler_clk*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + + case ULP_I2S_PLL_CLK: + /*I2s clock*/ + if (M4CLK->PLL_STAT_REG_b.I2SPLL_LOCK == 0) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*NOTE: this clock source is not valid in PS2 state. PLL is turned off in PS2*/ + M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 0; + /*Select clock MUX */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_SEL_b = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /* Wait for clock switched */ + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_I2S_CLK_b != 1U) + ; + + /*Set the division factor */ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLKDIV_FACTOR = (uint8_t)divFactor; + + ulpss_peripheral_enable(pULPCLK, ULP_I2S_CLK, ENABLE_STATIC_CLK); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_uar_clk_config(ULPCLK_Type *pULPCLK, + * CLK_ENABLE_T clkType, + * boolean_t bFrClkSel, + * ULP_UART_CLK_SELECT_T clkSource, + * uint16_t divFactor) + * @brief This API is used to configure the UART clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for UART + * @param[in] bFrClkSel : fractional clock select for ULP UART + * @param[in] clkSource : clock source for ULP UART + * @param[in] divFactor : divison factor for ULP UART + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_uar_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bFrClkSel, + ULP_UART_CLK_SELECT_T clkSource, + uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_UART_MAX_DIVISION_FACTOR) || (clkSource > ULP_UART_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_UART_CLK); + /*UART Fractional clock select */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_FRAC_CLK_SEL_b = (unsigned int)(bFrClkSel & 0x01); + + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_UART_REF_CLK: + /*Configure the ULPSS reference clock from NPSS clock MUX this is common for all these Sources */ + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_UART_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_UART_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_UART_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*4: ulp_mhz_rc_clk*/ + case ULP_UART_ULP_MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_UART_ULP_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + case ULP_UART_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + case ULP_UART_ULP_DOUBLER_CLK: + /*7: ulp_doubler_clk*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /* Wait for clock switched */ + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_UART_CLK_b != 1U) + ; + + pULPCLK->ULP_UART_CLK_GEN_REG_b.ULP_UART_CLKDIV_FACTOR = (unsigned int)(divFactor & 0x07); + + ulpss_peripheral_enable(pULPCLK, ULP_UART_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_time_clk_config(ULPCLK_Type *pULPCLK, + * CLK_ENABLE_T clkType, + * boolean_t bTmrSync, + * ULP_TIMER_CLK_SELECT_T clkSource, + * uint8_t skipSwitchTime) + * @brief This API is used to configure the timer clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for timer + * @param[in] bTmrSync : Timer Synchronisation for ULP timer + * @param[in] clkSource : clock source for ULP timer + * @param[in] skipSwitchTime : wait for clock switched for ULP timer + * @return RSI_OK on success + */ + +rsi_error_t ulpss_time_clk_config(ULPCLK_Type *pULPCLK, + CLK_ENABLE_T clkType, + boolean_t bTmrSync, + ULP_TIMER_CLK_SELECT_T clkSource, + uint8_t skipSwitchTime) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (clkSource > ULP_TIMER_MAX_SEL)) { + return INVALID_PARAMETERS; + } + /*Timer PCLK enable */ + ulpss_peripheral_disable(pULPCLK, ULP_TIMER_CLK); + + if (bTmrSync) { + /*Enable m4 core clock*/ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_IN_SYNC_b = 1; + } else { + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_IN_SYNC_b = 0; + } + /*clock select*/ + switch (clkSource) { + case ULP_TIMER_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_TIMER_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_TIMER_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_TIMER_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*4: ulp_mhz_rc_clk*/ + case ULP_TIMER_MHZ_RC_CLK: + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_TIMER_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + case ULP_TIMER_ULP_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + if (skipSwitchTime == 1) { + /* Wait for clock switched */ + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_TIMER_b != 1U) + ; + } + ulpss_peripheral_enable(pULPCLK, ULP_TIMER_CLK, clkType); + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_aux_clk_config(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource) + * @brief This API is used to configure the AUX clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkType : clock type for AUX + * @param[in] clkSource : clock source for AUX + * @return RSI_OK on success + */ + +rsi_error_t ulpss_aux_clk_config(ULPCLK_Type *pULPCLK, CLK_ENABLE_T clkType, ULP_AUX_CLK_SELECT_T clkSource) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (clkSource > ULP_AUX_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_AUX_CLK); + + /*select clock MUX */ + + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_AUX_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_AUX_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_AUX_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_AUX_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*4: ulp_mhz_rc_clk*/ + case ULP_AUX_MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_AUX_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + case ULP_AUX_ULP_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + case ULP_AUX_ULP_DOUBLER_CLK: + /*7: ulp_doubler_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + case ULP_AUX_I2S_PLL_CLK: + /*8: i2s_pll_clk*/ + if (M4CLK->PLL_STAT_REG_b.I2SPLL_LOCK == 0) { + return ERROR_CLOCK_NOT_ENABLED; + } + /*Enable clock*/ + M4CLK->CLK_CONFIG_REG5_b.I2S_CLK_SEL = 0; + /*Select clock MUX */ + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /* wait for clock switched */ + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_AUXADC_b != 1U) + ; + + ulpss_peripheral_enable(pULPCLK, ULP_AUX_CLK, clkType); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_vad_clk_config(ULPCLK_Type *pULPCLK, + * ULP_VAD_CLK_SELECT_T clkSource, + * ULP_VAD_FCLK_SELECT_T FclkSource, + * uint16_t divFactor) + * @brief This API is used to configure the VAD clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkSource : clock source for ULP VAD + * @param[in] FclkSource : fast clock cource for ULP VAD + * @param[in] divFactor : divison factor for ULP VAD + * @return RSI_OK on success + */ + +rsi_error_t ulpss_vad_clk_config(ULPCLK_Type *pULPCLK, + ULP_VAD_CLK_SELECT_T clkSource, + ULP_VAD_FCLK_SELECT_T FclkSource, + uint16_t divFactor) +{ + /* Parameter validation */ + if (pULPCLK == NULL || divFactor >= ULP_VAD_MAX_DIVISION_FACTOR || clkSource > ULP_VAD_MAX_SEL + || FclkSource > ULP_VAD_FCLK_MAX_SEL) { + return INVALID_PARAMETERS; + } + + ulpss_peripheral_disable(pULPCLK, ULP_VAD_CLK); + /*Select the VAD clock MUX */ + switch (clkSource) { + case ULP_VAD_32KHZ_RO_CLK: + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_SEL = clkSource; + break; + case ULP_VAD_32KHZ_RC_CLK: + /*1:ulp_32khz_rc_clk */ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_SEL = clkSource; + break; + case ULP_VAD_32KHZ_XTAL_CLK: + /*2: ulp_32khz_xtal_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_SEL = clkSource; + break; + default: + return INVALID_PARAMETERS; + } + /*Select the VAD Fast clock MUX */ + switch (FclkSource) { + case ULP_VAD_ULP_PROCESSOR_CLK: + /* ulpss processor clock */ + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_REF_CLK: + /*1: ref_clk */ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_40MHZ_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_MHZ_RC_CLK: + /*2: ulp_mhz_rc_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_20MHZ_RO_CLK: + /*3: ulp_20mhz_ro_clk*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + case ULP_VAD_ULP_SOC_CLK: + /*4: soc_clk*/ + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_SEL = FclkSource; + break; + default: + return INVALID_PARAMETERS; + } + + /*wait for clock switched */ + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_FCLK_VAD_b != 1U) + ; + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_SCLK_VAD_b != 1U) + ; + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_VAD_b != 1U) + ; + /*Set VAD clock division factor */ + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLKDIV_FACTOR = (uint8_t)divFactor; + + ulpss_peripheral_enable(pULPCLK, ULP_VAD_CLK, ENABLE_STATIC_CLK); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor) + * @brief This API is used to configure the Touch clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkSource : clock source for ULP Touch + * @param[in] divFactor : divison factor for ULP Touch + * @return RSI_OK on success + */ + +rsi_error_t ulpss_touch_clk_config(ULPCLK_Type *pULPCLK, ULP_TOUCH_CLK_SELECT_T clkSource, uint16_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_TOUCH_MAX_DIVISION_FACTOR) || (clkSource > ULP_TOUCH_MAX_SEL)) { + return INVALID_PARAMETERS; + } + ulpss_peripheral_disable(pULPCLK, ULP_TOUCH_CLK); + + /*Select */ + switch (clkSource) { + /*0: ref_clk (output of dynamic clock MUX for different possible ref_clk sources)*/ + case ULP_TOUCH_REF_CLK: + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*1: ulp_32khz_ro_clk */ + case ULP_TOUCH_32KHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*2: ulp_32khz_rc_clk*/ + case ULP_TOUCH_32KHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*3: ulp_32khz_xtal_clk*/ + case ULP_TOUCH_32KHZ_XTAL_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PERIPHERAL_CLK, 0); + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*4: ulp_mhz_rc_clk*/ + case ULP_TOUCH_MHZ_RC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + /*5: ulp_20mhz_ro_clk*/ + case ULP_TOUCH_20MHZ_RO_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + /*Select clock MUX */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + case ULP_TOUCH_ULP_SOC_CLK: + /*6: soc_clk*/ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_SEL = clkSource; + break; + + default: + return INVALID_PARAMETERS; + } + + /*Wait for clock switched */ + while ((pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_TOUCH_SENSOR_b) != 1) + ; + + /*Program the division factor */ + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLKDIV_FACTOR = (uint8_t)divFactor; + + ulpss_peripheral_enable(pULPCLK, ULP_TOUCH_CLK, ENABLE_STATIC_CLK); + + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor) + * @brief This API is used to configure the sleep sensor clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkEnable : enable clock for ULP sleep sensor + * @param[in] divFactor : divison factor for ULP sleep sensor + * @return RSI_OK on success + */ + +rsi_error_t ulpss_slp_sensor_clk_config(ULPCLK_Type *pULPCLK, boolean_t clkEnable, uint32_t divFactor) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_SLP_SENSOR_MAX_DIVISION_FACTOR)) { + return INVALID_PARAMETERS; + } + if (clkEnable) { + /*Enable sleep sensor clock */ + pULPCLK->SLP_SENSOR_CLK_REG_b.ENABLE_b = 1; + } else { + /*Disable sleep sensor clock */ + pULPCLK->SLP_SENSOR_CLK_REG_b.ENABLE_b = 0; + } + /*Apply division factor*/ + pULPCLK->SLP_SENSOR_CLK_REG_b.DIVISON_FACTOR = (uint8_t)divFactor; + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_peripheral_enable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) + * @brief This API is used to enable the particular ULP perpheral Clock + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] module : module for ULP peripheral Clock + * @param[in] clkType : clock type for ULP peripheral Clock + * @return RSI_OK on success + */ + +rsi_error_t ulpss_peripheral_enable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module, CLK_ENABLE_T clkType) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case ULP_I2C_CLK: + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_I2C_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_I2C_b = 1; + break; + case ULP_EGPIO_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = 1; + break; + case ULP_AUX_CLK: + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_EN_b = 1; + + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 1; + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_EN_b = 1; + } else { + /**Static enable **/ + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case ULP_FIM_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_PCLK_ENABLE_b = 1; + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_CLK_EN_b = 1; + } else { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.FIM_CLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case ULP_VAD_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_CLK_EN_b = 1; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_EN_b = 1; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_EN = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_PCLK_ENABLE_b = 1; + break; + case ULP_TIMER_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_TIMER_b = 1; + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.TIMER_PCLK_EN_b = 1; + } else { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.TIMER_PCLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_PCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_SCLK_DYN_CTRL_DISABLE_b = 0; + } + break; + case ULP_UDMA_CLK: + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UDMA_CLK_ENABLE_b = 1; + break; + case ULP_TOUCH_CLK: + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_EN_b = 1; + break; + case ULP_UART_CLK: + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_UART_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_UART_b = 1; + } else { + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_CLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_SCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_UART_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_UART_b = 0; + } + break; + case ULP_SSI_CLK: + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_SSI_MASTER_b = 1; + if (clkType == ENABLE_STATIC_CLK) { + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_SSI_MASTER_b = 1; + } else { + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_PCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_SSI_MASTER_b = 0; + } + break; + case ULP_I2S_CLK: + /*ULPSS I2S master*/ + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_EN_b = 1; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_I2S_b = 1; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_PCLK_EN_b = 1; + break; + + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} +#endif + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_peripheral_disable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) + * @brief This API is used to Disable the particulat ULP perpheral Clock + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] module : module for ULP peripheral Clock + * @return RSI_OK on success + */ + +rsi_error_t ulpss_peripheral_disable(ULPCLK_Type *pULPCLK, ULPPERIPHERALS_CLK_T module) +{ + if (pULPCLK == NULL) { + return INVALID_PARAMETERS; + } + switch (module) { + case ULP_I2C_CLK: + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_I2C_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_I2C_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.I2C_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_EGPIO_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_AUX_CLK: + pULPCLK->ULP_AUXADC_CLK_GEN_REG_b.ULP_AUX_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_CLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.AUX_PCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_FIM_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.FIM_PCLK_ENABLE_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.FIM_CLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_VAD_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_CLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.VAD_PCLK_ENABLE_b = 0; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_CLK_EN_b = 0; + pULPCLK->ULP_VAD_CLK_GEN_REG_b.ULP_VAD_FCLK_EN = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.VAD_CLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_TIMER_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.TIMER_PCLK_EN_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_TIMER_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_PCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.TIMER_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_UDMA_CLK: + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UDMA_CLK_ENABLE_b = 0; + break; + case ULP_TOUCH_CLK: + pULPCLK->ULP_TOUCH_CLK_GEN_REG_b.ULP_TOUCH_CLK_EN_b = 0; + break; + case ULP_UART_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_UART_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_UART_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_SCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.UART_CLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_SSI_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.SCLK_ENABLE_SSI_MASTER_b = 0; + pULPCLK->ULP_MISC_SOFT_SET_REG_b.PCLK_ENABLE_SSI_MASTER_b = 0; + pULPCLK->ULP_I2C_SSI_CLK_GEN_REG_b.ULP_SSI_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_PCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.SSI_MST_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + case ULP_I2S_CLK: + pULPCLK->ULP_MISC_SOFT_SET_REG_b.CLK_ENABLE_I2S_b = 0; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_PCLK_EN_b = 0; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_CLK_EN_b = 0; + pULPCLK->ULP_DYN_CLK_CTRL_DISABLE_b.I2S_CLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_PCLK_DYN_CTRL_DISABLE_b = 1; + pULPCLK->ULP_I2S_CLK_GEN_REG_b.ULP_I2S_SCLK_DYN_CTRL_DISABLE_b = 1; + break; + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_time_clk_disable(ULPCLK_Type *pULPCLK) + * @brief This API is used to disable the timer clock + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @return ulpss_peripheral_disable on success + */ + +rsi_error_t ulpss_time_clk_disable(ULPCLK_Type *pULPCLK) +{ + pULPCLK->ULP_TIMER_CLK_GEN_REG_b.ULP_TIMER_CLK_SEL = 0xF; + return ulpss_peripheral_disable(pULPCLK, ULP_TIMER_CLK); +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ref_clk_config(ULPSS_REF_CLK_SEL_T clkSource) + * @brief This API is used to select the ULPSS processor ref clk configuration + * @param[in] clkSource : clock source for ULPSS processor reference clock select + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ref_clk_config(ULPSS_REF_CLK_SEL_T clkSource) +{ + switch (clkSource) { + case ULPSS_REF_BYP_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = clkSource; + system_clocks.ulp_ref_clock_source = clkSource; + system_clocks.ulpss_ref_clk = system_clocks.byp_rc_ref_clock; + break; + + case ULPSS_ULP_MHZ_RC_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = clkSource; + system_clocks.ulp_ref_clock_source = clkSource; + system_clocks.ulpss_ref_clk = system_clocks.rc_mhz_clock; + break; + + case ULPSS_40MHZ_CLK: + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = clkSource; + system_clocks.ulp_ref_clock_source = clkSource; + system_clocks.ulpss_ref_clk = system_clocks.rf_ref_clock; + break; + + case ULPSS_MEMS_REF_CLK: + TASS_PLL_CTRL_SET_REG(AFEPLLCTRLREG1) = MEMS_REF_CLK_ENABLE; + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = clkSource; + system_clocks.ulp_ref_clock_source = clkSource; + system_clocks.ulpss_ref_clk = system_clocks.mems_ref_clock; + break; + + case ULPSS_ULP_20MHZ_RINGOSC_CLK: + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = clkSource; + system_clocks.ulp_ref_clock_source = clkSource; + system_clocks.ulpss_ref_clk = system_clocks.ro_20mhz_clock; + break; + + case ULPSS_ULP_DOUBLER_CLK: + /*6: ulp_doubler_clk*/ + /*Enable clock*/ + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PERIPHERAL_CLK, 0); + MCU_FSM->MCU_FSM_REF_CLK_REG_b.ULPSS_REF_CLK_SEL_b = clkSource; + system_clocks.ulp_ref_clock_source = clkSource; + system_clocks.ulpss_ref_clk = system_clocks.doubler_clock; + break; + + default: + return INVALID_PARAMETERS; + } + return RSI_OK; +} + +/*==============================================*/ +/** + * @fn rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + * ULP_PROC_CLK_SELECT_T clkSource, + * uint16_t divFactor, + * cdDelay delayFn) + * @brief This API is used to configure the ULPSS processor clock source + * @param[in] pULPCLK : pointer to the processor ULP clock source + * @param[in] clkSource : clock source for ULPSS processor clock select + * @param[in] divFactor : divison factor for processor clock source + * @param[in] delayFn : delay functionfor processor clock source + * @return RSI_OK on success + */ + +rsi_error_t ulpss_ulp_proc_clk_config(ULPCLK_Type *pULPCLK, + ULP_PROC_CLK_SELECT_T clkSource, + uint16_t divFactor, + cdDelay delayFn) +{ + /*Parameter validation */ + if ((pULPCLK == NULL) || (divFactor > ULP_PROC_MAX_DIVISOIN_FACTOR) || (clkSource > ULP_PROC_MAX_SEL)) { + return INVALID_PARAMETERS; + } + + /*Select */ + switch (clkSource) { + + case ULP_PROC_REF_CLK: + /*Select clock MUX */ + RSI_SetRegSpiDivision(0U); + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.ulpss_ref_clk; + break; + + case ULP_PROC_ULP_32KHZ_RO_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RO_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.ro_32khz_clock; + break; + + case ULP_PROC_ULP_32KHZ_RC_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_32KHZ_RC_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + SystemCoreClock = system_clocks.rc_32khz_clock; + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + break; + + case ULP_PROC_ULP_32KHZ_XTAL_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_32KHZ_XTAL_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.xtal_32khz_clock; + break; + + case ULP_PROC_ULP_MHZ_RC_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_MHZ_RC_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.rc_mhz_clock; + break; + + case ULP_PROC_ULP_20MHZ_RO_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_20MHZ_RING_OSC_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.ro_20mhz_clock; + break; + + case ULP_PROC_SOC_CLK: + /*6: soc_clk*/ + RSI_SetRegSpiDivision(2U); + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.soc_clock; + break; + + case ULP_PROC_ULP_DOUBLER_CLK: + /*Enable clock*/ + RSI_SetRegSpiDivision(0U); + ulpss_enable_ref_clks(MCU_ULP_DOUBLER_CLK_EN, ULP_PROCESSOR_CLK, delayFn); + /*Select clock MUX */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_SEL = clkSource; + SystemCoreClock = system_clocks.doubler_clock; + break; + default: + return INVALID_PARAMETERS; + } + while (pULPCLK->CLOCK_STAUS_REG_b.CLOCK_SWITCHED_PROC_CLK_b != 1) + ; + /*update the division factor */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP_PROC_CLK_DIV_FACTOR = (char)divFactor; + /*clock Enable */ + pULPCLK->ULP_TA_CLK_GEN_REG_b.ULP2M4_A2A_BRDG_CLK_EN_b = 1; + + if (divFactor) { + SystemCoreClock = (SystemCoreClock / divFactor); + } + system_clocks.soc_clock = SystemCoreClock; + return RSI_OK; +} +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h new file mode 100644 index 000000000..8f5a22a0f --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_driver_gpio.h @@ -0,0 +1,1062 @@ +/******************************************************************************* +* @file sl_driver_gpio.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#ifndef SL_DRIVER_GPIO_H +#define SL_DRIVER_GPIO_H + +#if !defined(GPIO_PRESENT) +#include "sl_status.h" +#include "sl_si91x_peripheral_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ /** + * @addtogroup GPIO General-Purpose Input-Output + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + ******************************************************************************/ +/******************************************************************************* + *************************** DEFINES / MACROS ******************************* ******************************************************************************/ +#define GPIO_MAX_OUTPUT_VALUE 1 ///< GPIO output maximum value +#define MAX_GROUP_INT 2 ///< Maximum number of group interrupts +#define GPIO_PORT_MAX_VALUE 5 ///< Maximum number of GPIO ports +#define MAX_UULP_INT 5 ///< Maximum number of UULP interrupts +#define ULP_MAX_MODE 10 ///< Maximum ULP mode + +#define GPIO_MAX_INTR_VALUE 8 ///< Maximum number of M4 GPIO pin interrupts +#define PORTD_PIN_MAX_VALUE 9 ///< Port D maximum(0-9) number of GPIO pins +#define ULP_PIN_MAX_VALUE 11 ///< Port E maximum(0-11) number of GPIO pins +#define UULP_PIN_MAX_VALUE 5 ///< Port F maximum(0-4) number of GPIO pins +#define MAX_ULP_INTR 8 ///< Maximum number of ULP interrupts +#define MAX_MODE 15 ///< Maximum M4 GPIO mode +#define PORTA_PIN_MAX_VALUE 57 ///< GPIO pin maximum(0-63) value for SL_GPIO_PORT_A of HP instance +#define PORT_PIN_MAX_VALUE 15 ///< GPIO pin maximum(0-15) value for SL_GPIO_PORT_B, SL_GPIO_PORT_C of HP instance +#define GPIO_FLAGS_MAX_VALUE 0x0F ///< GPIO flags maximum value + +#define PAD_SELECT_9 9 ///< GPIO PAD selection number +#define UULP_PORT 5 ///< Refers to port for UULP instance +#define GPIO_MAX_PORT_PINS 0xFFFF ///< Refers to maximum no. of pins port can support + +/******************************************************************************* + ******************************** ENUMS *********************************** ******************************************************************************/ +/// @brief structure to hold parameters of GPIO port and pin numbers. +typedef struct { + sl_gpio_port_t port; ///< GPIO port + uint8_t pin; ///< GPIO pin number +} sl_gpio_t; + +/// @brief Structure to configure GPIO pin settings. +typedef struct { + sl_gpio_t port_pin; ///< The port and pin number of the GPIO + sl_si91x_gpio_direction_t direction; ///< The direction of the GPIO pin (input or output) +} sl_si91x_gpio_pin_config_t; + +/******************************************************************************* + ******************************** Local Variables ************************* ******************************************************************************/ +/// @brief GPIO interrupt callback function pointer. +typedef void (*sl_gpio_irq_callback_t)(uint32_t flag); + +/******************************************************************************* + ***************************** PROTOTYPES ********************************* ******************************************************************************/ + +/***************************************************************************/ +/** + * @brief Clears one or more pending GPIO interrupts. + * + * This function clears the specified GPIO interrupt sources. The `flags` + * parameter is a bitwise OR of the interrupt sources to be cleared. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance to enable pad selection. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance to enable pad receiver. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] flags Bitwise logic OR of GPIO interrupt sources to clear. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_clear_interrupts(uint32_t flags) +{ + sl_gpio_clear_interrupts(flags); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Configures the GPIO pin interrupt. + * + * This function sets up a GPIO pin to trigger an interrupt. The `gpio` parameter + * is a pointer to a structure of type \ref sl_gpio_t, which contains the GPIO + * configuration. The `int_no` parameter specifies the interrupt number to trigger + * (ranging from 0 to 7). The `flags` parameter contains the interrupt configuration + * flags of type sl_gpio_interrupt_flag_t. The `gpio_callback` parameter is a + * pointer to the IRQ callback function of type \ref sl_gpio_irq_callback_t. The + * `avl_intr_no` parameter is an output pointer to the available interrupt number. + * + * @pre Pre-conditions: + * - sl_gpio_set_configuration() must be called to configure the GPIO. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * @param[in] int_no Specifies the interrupt number to trigger (0 to 7). + * @param[in] flags Interrupt configuration flags of type sl_gpio_interrupt_flag_t. + * @param[in] gpio_callback IRQ callback function pointer of type \ref sl_gpio_irq_callback_t. + * @param[out] avl_intr_no Pointer to the available interrupt number. If no interrupt is available, + * it returns SL_GPIO_INTERRUPT_UNAVAILABLE (0xFF). + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_BUSY - Interrupt is busy and cannot carry out the requested operation. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pin is properly configured + * before calling this function. + * + ******************************************************************************/ +sl_status_t sl_gpio_driver_configure_interrupt(sl_gpio_t *gpio, + uint32_t int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + uint32_t *avl_intr_no); + +/***************************************************************************/ +/** + * @brief Configures the GPIO group interrupts for HP and ULP instances. + * + * This function sets up group interrupts for GPIO pins in both High Performance (HP) + * and Ultra Low Power (ULP) instances. The `configuration` parameter is a pointer + * to a structure of type sl_si91x_gpio_group_interrupt_config_t, which contains + * the GPIO group interrupt configuration. The `gpio_callback` parameter is a pointer + * to the IRQ callback function of type \ref sl_gpio_irq_callback_t. + * + * @pre Pre-conditions: + * - sl_gpio_set_configuration() must be called to configure the GPIO. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] configuration Pointer to the structure of type sl_si91x_gpio_group_interrupt_config_t + * @param[in] gpio_callback IRQ callback function pointer of type \ref sl_gpio_irq_callback_t. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_BUSY - Interrupt is busy and cannot carry out the requested operation. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pins are properly configured + * before calling this function. + * + ******************************************************************************/ +sl_status_t sl_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ +/** + * @brief Sets the pin mode for a GPIO pin in HP (or) ULP instance. + * + * @details By default, mode-0 is set, and the GPIO pin acts as a normal GPIO. + * If a GPIO pin needs to be used for some alternate modes, the respective mode + * should be selected. For more information about modes present for different + * instances, refer to the PIN MUX section in the HRM. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_clock() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * Refer to the table below for a description of each port and pins available. + * | GPIO Instance | GPIO Port | GPIO Pin Number | + * |---------------------------------------------|-----------------------|-------------------| + * | | SL_GPIO_PORT_A | (0-15) | + * | HP (High Power) GPIO Instance | SL_GPIO_PORT_B | (16-31) | + * | | SL_GPIO_PORT_C | (32-47) | + * | | SL_GPIO_PORT_D | (48-57) | + * |---------------------------------------------|-----------------------|-------------------| + * | ULP (Ultra Low Power) GPIO Instance | SL_GPIO_ULP_PORT | (0-11) | + * |---------------------------------------------|-----------------------|-------------------| + * | UULP (Ultra Ultra Low Power) GPIO Instance | SL_GPIO_UULP_PORT | (0-3) | + * |---------------------------------------------|-----------------------|-------------------| + * PORT_A can also be a single port to access all GPIO (0-57) pins available in the HP domain, + * instead of using PORT B, C, D. Pins (57-63) are reserved. + * + * @param[in] mode The desired pin mode. + * @param[in] output_value A value to set for the pin in the GPIO register. + * The GPIO setting is important for some input mode configurations. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pin is properly configured + * before calling this function. + ******************************************************************************/ +sl_status_t sl_gpio_driver_set_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t mode, uint32_t output_value); + +/***************************************************************************/ +/** + * @brief Gets the pin mode (alternate function) of a GPIO for either HP instance (or) ULP instance as per the port number. + * + * This function retrieves the current pin mode (alternate function) of a specified GPIO pin. + * The `gpio` parameter is a pointer to a structure of type \ref sl_gpio_t, which contains + * the GPIO configuration. The `mode` parameter is an output parameter that will hold the + * current pin mode after the function executes. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * @param[out] mode Pointer to a variable where the current pin mode will be stored. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pin is properly configured + * before calling this function. + * + ******************************************************************************/ +sl_status_t sl_gpio_driver_get_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t *mode); + +/*******************************************************************************/ +/** + * @brief Initializes the GPIO driver. + * + * This function initializes the GPIO driver by clearing all the interrupts for + * High Performance (HP), Ultra Low Power (ULP), and NPSS instances. It also sets + * all callback function pointers to NULL. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note This function should be called before any other GPIO driver functions + * to ensure proper initialization. + ******************************************************************************/ +sl_status_t sl_gpio_driver_init(void); + +/*******************************************************************************/ +/** + * @brief De-Initializes the GPIO driver. + * + * This function de-initializes the GPIO driver by disabling the clocks for both + * High Performance (HP), Ultra Low Power (ULP) and Ultra Ulta Low Power (UULP) instances. It also sets all + * callback function pointers to NULL. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note This function should be called to properly clean up the GPIO driver + * before the application exits or when the GPIO driver is no longer needed. + ******************************************************************************/ +sl_status_t sl_gpio_driver_deinit(void); + +/*******************************************************************************/ +/** + * @brief Unregisters GPIO driver. + * + * This function unregisters the GPIO driver for a specified GPIO instance and interrupt. + * The `gpio_instance` parameter specifies the GPIO instance of type sl_si91x_gpio_instances_t. + * The `gpio_intr` parameter specifies the GPIO interrupt of type sl_si91x_gpio_intr_t. + * The `flag` parameter specifies the GPIO interrupt flag, with a maximum range of 8. + * + * @param[in] gpio_instance Instances of type sl_si91x_gpio_instances_t. + * @param[in] gpio_intr GPIO interrupts of type sl_si91x_gpio_intr_t. + * @param[in] flag GPIO interrupt flag. Maximum range is 8. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO instance and interrupt are properly configured before + * calling this function. + ******************************************************************************/ +sl_status_t sl_gpio_driver_unregister(sl_si91x_gpio_instances_t gpio_instance, + sl_si91x_gpio_intr_t gpio_intr, + uint8_t flag); + +/*******************************************************************************/ +/** + * @brief Validates the port and pin of a GPIO. + * + * This function checks whether the specified port and pin in the GPIO structure + * are valid. The `gpio` parameter is a pointer to a structure of type \ref sl_gpio_t, + * which contains the GPIO configuration. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the `gpio` structure is properly initialized before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_validation(sl_gpio_t *gpio) +{ + // Checks if gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (gpio->port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (gpio->port == SL_GPIO_PORT_A) { + if (gpio->pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((gpio->port == SL_GPIO_PORT_B) || (gpio->port == SL_GPIO_PORT_C)) { + if (gpio->pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (gpio->port == SL_GPIO_PORT_D) { + if (gpio->pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the GPIO port is the Ultra-Low Power GPIO port. + if (gpio->port == SL_GPIO_ULP_PORT) { + // Check if the GPIO pin exceeds the maximum allowed values. + if (gpio->pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the GPIO port is the Ultra-Ultra Low Power GPIO port. + if (gpio->port == SL_GPIO_UULP_PORT) { + // Check if the GPIO pin exceeds the maximum allowed values. + if (gpio->pin > UULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Sets a single pin in the GPIO configuration register to 1. + * + * This function sets a specified GPIO pin to 1 in the GPIO configuration register. + * The `gpio` parameter is a pointer to a structure of type \ref sl_gpio_t, which + * contains the GPIO configuration. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pin is properly configured + * before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_pin(sl_gpio_t *gpio) +{ + sl_status_t status; + // Checks if the gpio pointer is NULL + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Sets the GPIO pin output + sl_gpio_set_pin_output(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Clears a single pin in the GPIO configuration register. + * + * This function clears (sets to 0) a specified GPIO pin in the GPIO configuration register. + * The `gpio` parameter is a pointer to a structure of type \ref sl_gpio_t, which contains + * the GPIO configuration. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pin is properly configured + * before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_clear_pin(sl_gpio_t *gpio) +{ + sl_status_t status; + // Checks if the gpio pointer is NULL. Returns error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Clears the GPIO pin output + sl_gpio_clear_pin_output(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Toggles a single pin in the GPIO port register. + * + * This function toggles the state of a specified GPIO pin in the GPIO port register. + * The `gpio` parameter is a pointer to a structure of type \ref sl_gpio_t, which + * contains the GPIO configuration. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pin is properly configured + * before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_toggle_pin(sl_gpio_t *gpio) +{ + sl_status_t status; + // Checks if the gpio pointer is NULL. Returns error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Toggles GPIO pin + sl_gpio_toggle_pin_output(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Reads the pin value for a single pin in a GPIO port. + * + * This function reads the value of a specified GPIO pin. The `gpio` parameter + * is a pointer to a structure of type \ref sl_gpio_t, which contains the GPIO + * configuration. The `pin_value` parameter is an output parameter that will + * hold the value of the GPIO pin after the function executes. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * @param[out] pin_value Pointer to a variable where the GPIO pin value will be stored. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pin is properly configured + * before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_get_pin(sl_gpio_t *gpio, uint8_t *pin_value) +{ + sl_status_t status; + // Checks if the gpio pointer is NULL. Returns error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Gets the GPIO pin input + *pin_value = sl_gpio_get_pin_input(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Sets the bits of the GPIO data out register. + * + * This function sets the specified GPIO pins to 1 in the GPIO data out register + * for a given port. The `port` parameter specifies the port to associate with the pin. + * The `pins` parameter specifies the GPIO pins in the port that are set to 1. + * The pins can be specified as a value between 0 and 65535 in decimal (or 0xFFFF in hex), + * allowing up to 16 pins (0-15) to be set at a time. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] port The port to associate with the pin. + * - HP instance: PORT A, B, C, D + * - ULP instance: PORT 4 + * @param[in] pins The GPIO pins in the port that are set to 1 (0 to 65535 in decimal or 0xFFFF in hex). + * If we want to set pins (maximum of 0-15 pins) in a port, it can set all pins at a time. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pins are properly configured + * before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_port(sl_gpio_port_t port, uint32_t pins) +{ + // Checks if the gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if ((port > GPIO_PORT_MAX_VALUE) || (pins > GPIO_MAX_PORT_PINS)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Sets the GPIO port output + sl_gpio_set_port_output(port, pins); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Sets the bits in the configuration register for a port to 0. + * + * This function clears (sets to 0) the specified GPIO pins in the configuration + * register for a given port. The `port` parameter specifies the port to associate + * with the pin. The `pins` parameter specifies the GPIO pins in the port that are + * set to 0. The pins can be specified as a value between 1 and 65535 in decimal + * (or 0xFFFF in hex), allowing up to 16 pins (0-15) to be cleared at a time. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] port The port to associate with the pin. + * - HP instance: PORT A, B, C, D + * - ULP instance: PORT 4 + * @param[in] pins The GPIO pins in the port that are set to 0 (0 to 65535 in decimal or 0xFFFF in hex). + * If we want to clear pins (maximum of 0-15 pins) in a port, it can clear all pins at a time. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pins are properly configured + * before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_clear_port(sl_gpio_port_t port, uint32_t pins) +{ + // Checks if the gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if ((port > GPIO_PORT_MAX_VALUE) || (pins > GPIO_MAX_PORT_PINS)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clears the GPIO port output + sl_gpio_clear_port_output(port, pins); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Gets the current setting for a GPIO configuration register. + * + * This function retrieves the current configuration settings for a specified GPIO port. + * The `port` parameter specifies the port to associate with the pin. The `port_value` + * parameter is an output parameter that will hold the current value of the GPIO port + * configuration register after the function executes. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] port The port to associate with the pin. + * - HP instance: PORT A, B, C, D + * - ULP instance: PORT 4 + * @param[out] port_value Pointer to a variable where the GPIO port value will be stored. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + * + * @note Ensure that the GPIO clock is enabled and the pins are properly configured + * before calling this function. + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_get_port_output(sl_gpio_port_t port, uint32_t *port_value) +{ + // Checks if the gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Gets the GPIO port output + *port_value = sl_gpio_get_port_output(port); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Gets the current setting for a pin in a GPIO configuration register. + * + * This function retrieves the current value of a specified GPIO pin. The `gpio` + * parameter is a pointer to a structure of type \ref sl_gpio_t, which contains + * the GPIO configuration. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] gpio Pointer to the structure of type \ref sl_gpio_t. + * + * @return The GPIO pin value: + * - '0' - Low + * - '1' - High + ******************************************************************************/ +STATIC __INLINE uint8_t sl_gpio_driver_get_pin_output(sl_gpio_t *gpio) +{ + sl_status_t status; + uint8_t pin_output = 0; + // Checks if the gpio pointer is NULL. Returns error code for NULL pointer + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Gets the GPIO pin output + pin_output = sl_gpio_get_pin_output(gpio->port, gpio->pin); + return pin_output; +} + +/***************************************************************************/ +/** + * @brief Sets the GPIO port configuration register. + * + * This function sets the specified bits in the GPIO port configuration register + * for a given port. The `port` parameter specifies the port to associate with the pin. + * The `val` parameter specifies the value to write to the port configuration register. + * The `mask` parameter indicates which bits to modify. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] port The port to associate with the pin. + * - HP instance: PORT A, B, C, D + * - ULP instance: PORT 4 + * @param[in] val Value to write to the port configuration register. + * @param[in] mask Mask indicating which bits to modify. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_port_output_value(sl_gpio_port_t port, uint32_t val, uint32_t mask) +{ + // Checks if the gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Sets the GPIO port output value + sl_gpio_set_port_output_value(port, val, mask); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Sets the slewrate for pins on an HP instance GPIO port. + * + * This function configures the slewrate for the pins on a specified HP instance GPIO port. + * The `port` parameter specifies the GPIO port to configure. The `slewrate` parameter + * specifies the slewrate for the pins on this GPIO port. The `slewrate_alt` parameter + * specifies the slewrate for the pins using alternate modes on this GPIO port. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * + * @param[in] port The GPIO port to configure. + * @param[in] slewrate The slewrate to configure for the pins on this GPIO port. + * @param[in] slewrate_alt The slewrate to configure for the pins using alternate modes on this GPIO port. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_slew_rate(sl_gpio_port_t port, uint32_t slewrate, uint32_t slewrate_alt) +{ + // Checks if the gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Sets the GPIO slew rate + sl_gpio_set_slew_rate(port, slewrate, slewrate_alt); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Reads the port value for GPIO. + * + * This function reads the value of a specified GPIO port. The `port` parameter + * specifies the port to associate with the pin. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] port The port to associate with the pin. + * - HP instance: PORT A, B, C, D + * - ULP instance: PORT 4 + * + * @return The GPIO pin value: + * - '0' - Low + * - '1' - High + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_port_input(sl_gpio_port_t port) +{ + uint32_t port_input = 0; + // Checks if the gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Gets the GPIO port input + port_input = sl_gpio_get_port_input(port); + return port_input; +} + +/***************************************************************************/ +/** + * @brief Toggles the selected pin values in the GPIO port register. + * + * This function toggles the specified GPIO pins in the port register. The `port` + * parameter specifies the port to associate with the pin. The `pins` parameter + * specifies the port pins to toggle, ranging from 0 to 65535 in decimal (or 0xFFFF in hex). + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() must be called for ULP instance. + * + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] port The port to associate with the pin. + * - HP instance: PORT A, B, C, D + * - ULP instance: PORT 4 + * @param[in] pins Port pins to toggle. Ranges from 0 to 65535 in decimal (or 0xFFFF in hex). + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_toggle_port_output(sl_gpio_port_t port, uint32_t pins) +{ + // Checks if the gpio port value exceeds maximum allowed value. Return error code for invalid parameter + if ((port > GPIO_PORT_MAX_VALUE) || (pins > GPIO_MAX_PORT_PINS)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Toggles the GPIO port output + sl_gpio_toggle_port_output(port, pins); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Enables the selected GPIO pin interrupt with the configured interrupt type (Level or Edge). + * + * This function enables the interrupt for the selected GPIO pin with the specified interrupt type, + * which can be either level-triggered or edge-triggered. The `flags` parameter specifies the GPIO + * interrupt sources to enable. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] flags GPIO interrupt sources to enable. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_enable_interrupts(uint32_t flags) +{ + sl_gpio_enable_interrupts(flags); + return SL_STATUS_OK; +} + +/*******************************************************************************/ /** + * @brief Disables the selected GPIO pin interrupt with the configured interrupt type (Level or Edge). + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * + * @param[in] flags - GPIO interrupt sources to disable. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_disable_interrupts(uint32_t flags) +{ + sl_gpio_disable_interrupts(flags); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Sets the selected GPIO pin interrupt with the configured interrupt type (Level or Edge). + * + * This function sets the interrupt for the selected GPIO pin with the specified interrupt type, + * which can be either level-triggered or edge-triggered. The `flags` parameter specifies the GPIO + * interrupt sources to set to pending. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @param[in] flags GPIO interrupt sources to set to pending. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +STATIC __INLINE sl_status_t sl_gpio_driver_set_interrupts(uint32_t flags) +{ + sl_gpio_set_interrupts(flags); + return SL_STATUS_OK; +} + +/***************************************************************************/ +/** + * @brief Gets the pending GPIO interrupts. + * + * This function retrieves the numbers of the GPIO pins that have pending interrupts. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @return Pending GPIO pin interrupt numbers. + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_pending_interrupts(void) +{ + uint32_t status; + status = sl_gpio_get_pending_interrupts(); + return status; +} + +/***************************************************************************/ +/** + * @brief Gets the enabled GPIO interrupts. + * + * This function retrieves the numbers of the GPIO pins that have enabled interrupts. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @return Enabled GPIO pin interrupt numbers. + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_enabled_interrupts(void) +{ + uint32_t status; + status = sl_gpio_get_enabled_interrupts(); + return status; +} + +/***************************************************************************/ +/** + * @brief Gets the enabled and pending GPIO interrupt flags. + * + * This function retrieves the flags for the enabled and pending GPIO interrupts. + * + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() must be called to enable the GPIO clock. + * - \ref sl_si91x_gpio_driver_enable_pad_selection() must be called for HP instance. + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() must be called for HP instance. + * - \ref sl_gpio_driver_set_pin_mode() must be called to set the pin mode. + * - \ref sl_si91x_gpio_driver_set_pin_direction() must be called to set the pin direction. + * + * @return Flags indicating the enabled and pending GPIO interrupts. + ******************************************************************************/ +STATIC __INLINE uint32_t sl_gpio_driver_get_enabled_pending_interrupts(void) +{ + uint32_t status; + status = sl_gpio_get_enabled_pending_interrupts(); + return status; +} + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< GPIO_PRESENT +#endif ///< SL_DRIVER_GPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h new file mode 100644 index 000000000..a7d8e29b8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_driver_gpio.h @@ -0,0 +1,1176 @@ +/***************************************************************************/ /** + * @file sl_si91x_driver_gpio.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SI91X_DRIVER_GPIO_H +#define SL_SI91X_DRIVER_GPIO_H + +#if !defined(GPIO_PRESENT) +#include "sl_status.h" +#include "sl_driver_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ /** + * @addtogroup GPIO General-Purpose Input-Output + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + * + ******************************************************************************/ +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************/ /** + * @brief Configuration of the GPIO based on port and pin. + * @details Port A,B,C,D are considered for HP instance, ULP PORT is considered for ULP instance + * UULP PORT is considered for UULP instance. The configuration of GPIO pin like + * which GPIO pin and port are to be passed through the structure. By default mode is taken + * as mode0, which is normal GPIO selection. + * @param[in] pin_config - Structure containing the configuration information. + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_gpio_set_configuration(sl_si91x_gpio_pin_config_t pin_config); + +/***************************************************************************/ /** + * @brief Set the direction for a GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @param[in] direction - Pin direction of type sl_si91x_gpio_direction_t (Direction of the GPIO pin enum). + * - '0' - Output + * - '1' - Input + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of a selected GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use corresponding pad receiver API for corresponding GPIO instance. + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_get_pin_direction() + * + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @return Returns the direction of the pin. + * - '0' - Output + * - '1' - Input + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_pin_direction(uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit in the PAD configuration register for reading the GPIO pin status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * + * @param[in] gpio_num - GPIO pin number to be use. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit in the PAD configuration register. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_pad_selection(), for HP instance + * + * @param[in] gpio_num - GPIO pin number to be use. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Enable the pad selection bit in the PAD selection register. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_padnum - PAD number to be used. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_selection(uint8_t gpio_padnum); + +/***************************************************************************/ /** + * @brief Enable the host pad selection bit in the PAD selection register. + * GPIO pin number(25 to 30) are valid for HOST PAD selection, referring + * to SL_GPIO_PORT_B, pins 9 to 14. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_num - GPIO pin number(25-30) to be used. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_host_pad_selection(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Select the drive strength for an HP instance GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * @param[in] gpio_num - GPIO pin number to be use. + * @param[in] strength - Drive strength selector(E1,E2) of type + * sl_si91x_gpio_driver_strength_select_t (GPIO driver strength select). + * Possible values are + * - 0, for two_milli_amps (E1=0,E2=0) + * - 1, for four_milli_amps (E1=0,E2=1) + * - 2, for eight_milli_amps (E1=1,E2=0) + * - 3, for twelve_milli_amps(E1=1,E2=1) + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argumen.t + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the driver disabled state control for an HP instance GPIO pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * @param[in] gpio_num - GPIO pin number to be use. + * @param[in] disable_state - Driver disable state of type + * sl_si91x_gpio_driver_disable_state_t. + * Possible values are + * + * - 0, for HiZ (P1=0,P2=0) + * - 1, for Pull-up (P1=0,P2=1) + * - 2, for Pull-down (P1=1,P2=0) + * - 3, for Repeater (P1=1,P2=1) + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Select AND/OR type of the group interrupt. If multiple interrupts + * on same port (or) different are to be generated, then use this API. + * Example: Consider port A: pin 2,3 and port D: pin 1,2 for interrupt generation. + * Choose OR, any of the selected pin condition triggers the group interrupt generation + * Choose AND, all the selected pin conditions should match to trigger group interrupt generation + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - Group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @param[in] and_or - AND/OR of GPIO group interrupts of type + * sl_si91x_gpio_and_or_t (AND/OR of the GPIO group interrupt). + * - '0' - AND + * - '1' - OR + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or); + +/***************************************************************************/ /** + * @brief Clear the selected group interrupt status value. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt() + * @param[in] group_interrupt - Group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Get the current status of the selected group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(), + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - Group interrupt number of type (0 to 1) + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @return Returns the group interrupt status register: + * - 1, when interrupt is enabled + * - 0, when interrupt is disabled + * + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Configure the group interrupt as a wake-up source across sleep wakeups. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - Group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @param[in] flags - GPIO group interrupt wake up flag of type + * sl_si91x_gpio_wakeup_t (GPIO group interrupt wakeup flag). + * - '1' - enable + * - '0' - disable + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_wakeup_t flags); + +/***************************************************************************/ /** + * @brief Configure the MCU HP instance group interrupts with trigger type (level/edge), polarity (high/low), interrupt type (and/or) + * and register the callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock + * - \ref sl_si91x_gpio_driver_enable_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] configuration - configuration pointer to + * sl_si91x_gpio_group_interrupt_config_t structure + * @param[in] gpio_callback - IRQ function pointer + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Get the configured polarity of group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return Returns group interrupt polarity: + * - 1, when GPIO pin status is HIGH + * - 0, when GPIO pin status is LOW + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Configure the polarity to a selected group interrupt which decides the active value of the pin to be + * considered for group interrupt generation. + * '0' – group interrupt gets generated when gpio input pin status is LOW + * '1' – group interrupt gets generated when gpio input pin status is HIGH + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @param[in] polarity - polarity of GPIO group interrupt of type + * sl_si91x_gpio_polarity_t (GPIO polarity enum) + * - 1, group interrupt gets generated when GPIO pin status is '1' + * - 0, group interrupt gets generated when GPIO pin status is '0' + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Get the configured level/edge event for the selected group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode(), + * - \ref sl_si91x_gpio_driver_set_pin_direction(), + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @return Returns group interrupt level_edge: + * - 1, for Edge + * - 0, for Level + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Set the level/edge event for the selected group interrupt. + * '1' Triggers interrupt generation when configured edge is detected on pin. + * '0' Triggers interrupt generation when configured level is detected on pin. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * - HP instance - PORT A,B,C,D + * - ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @param[in] level_edge - GPIO level edge group interrupt of type + * sl_si91x_gpio_level_edge_t (GPIO level edge select): + * - 1, for Edge + * - 0, for Level + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge); + +/***************************************************************************/ /** + * @brief Unmask the selected group interrupt to enable interrupt clearing upon generation. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] port - The port to associate with the pin. + * - HP instance - PORT A,B,C,D + * - ULP instance - ULP PORT + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts) + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Disable the clock for either the HP or ULP instance of the GPIO Peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * sl_si91x_gpio_select_clock_t (HP/ULP GPIO clock select) + * - 0, for M4 GPIO CLK + * - 1, for ULP GPIO CLK + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the clock for either the HP or ULP instance of the GPIO peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * sl_si91x_gpio_select_clock_t (HP/ULP GPIO clock select): + * - 0, for M4 GPIO CLK + * - 1, for ULP GPIO CLK + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the selected group interrupts for either the HP or ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @param[in] port - The port to associate with the pin. + * - HP instance - PORT A,B,C,D + * - ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Disable the selected group interrupts for either the HP or ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_clock, for HP instance + * - \ref sl_si91x_gpio_driver_enable_pad_receiver(), for HP instance + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver(), for ULP instance + * Use the corresponding pad receiver API for the corresponding GPIO instance. + * + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), for HP instance + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, for ULP instance + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts) + * @param[in] port - The port to associate with the pin. + * HP instance - PORT A,B,C,D + * ULP instance - ULP PORT + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port A, B, C has 16 pins each. + * Port D has 9 pins. + * ULP instance has total 12 pins. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the slew rate for the ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * + * @param[in] gpio_num - GPIO pin number to be use. + * @param[in] slew_rate - Slew rate of type sl_si91x_gpio_slew_rate_t (GPIO slew rate select): + * - '0' - Slow + * - '1' - Fast + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate); + +/***************************************************************************/ /** + * @brief Select the drive strength for the ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * + * @param[in] gpio_num - GPIO pin number to be use. + * @param[in] strength - Drive strength selector(E1,E2) of type + * sl_si91x_gpio_driver_strength_select_t (GPIO driver strength select): + * - 0, for two_milli_amps (E1=0,E2=0) + * - 1, for four_milli_amps (E1=0,E2=1) + * - 2, for eight_milli_amps (E1=1,E2=0) + * - 3, for twelve_milli_amps(E1=1,E2=1) + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the driver-disabled state control for the ULP instance of the GPIO peripheral. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * + * @param[in] gpio_num - GPIO pin number to be use. + * @param[in] disable_state - Driver disable state of type + * sl_si91x_gpio_driver_disable_state_t: + * - 0, for HiZ (P1=0,P2=0) + * - 1, for Pull up (P1=0,P2=1) + * - 2, for Pull down (P1=1,P2=0) + * - 3, for Repeater (P1=1,P2=1) + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_disable_state( + uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit for the ULP instance of the GPIO peripheral. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_num - GPIO pin number to be used. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_ulp_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit for the ULP instance of the GPIO peripheral. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] gpio_num - GPIO pin number to be used. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_ulp_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance pin interrupts with the trigger type (level/edge) + * and register the callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] int_no - The interrupt number to trigger. + * @param[in] flags - Interrupt configuration flags of type + * sl_si91x_gpio_interrupt_config_flag_t (GPIO Interrupt Configurations). + * @param[in] pin - GPIO pin number (0 to 11). + * @param[in] gpio_callback - IRQ function pointer. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_pin_interrupt(uint8_t int_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO pin MUX (mode) to the selected mode. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * + * @param[in] pin - NPSS GPIO pin number (0...4) of type + * sl_si91x_uulp_npss_mode_t (NPSS GPIO PIN MUX). + * @param[in] mode - NPSS GPIO MUX value (0 to 10). + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode); + +/***************************************************************************/ /** + * @brief Enable/disable the NPSS GPIO Input Buffer. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] pin - NPSS GPIO pin number (0...4). + * @param[in] receiver - Enable/disable NPSS GPIO receiver of type + * sl_si91x_gpio_receiver_t (NPSS GPIO input buffer). + * - '1' - Enable + * - '0' - Disable + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver); + +/***************************************************************************/ /** + * @brief Set the direction for the selected NPSS GPIO. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * @param[in] pin - NPSS GPIO pin number (0...4). + * @param[in] direction - Direction value (Input / Output) of type + * sl_si91x_gpio_direction_t (Direction of the GPIO pin enum): + * - '1' - Input Direction + * - '0' - Output Direction + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of the selected NPSS GPIO. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * + * @param[in] pin - NPSS GPIO pin number (0...4). + * @return Returns the GPIO pin direction: + * - 1, Input Direction + * - 0, Output Direction + *******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_direction(uint8_t pin); + +/***************************************************************************/ /** + * @brief Control(set or clear) the NPSS GPIO pin value. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] pin - NPSS GPIO pin number (0...4) of type + * sl_si91x_gpio_pin_value_t (GPIO pin set/clear). + * @param[in] pin_value - NPSS GPIO pin value: + * - '0' - Output + * - '1' - Input + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value); + +/***************************************************************************/ /** + * @brief Read the status of the selected NPSS GPIO pin value. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_value() + * @param[in] pin - NPSS GPIO pin number (0...4). + * @return Returns the pin logical state of pin: + * - '0' - Output + * - '1' - Input + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the NPSS GPIO polarity for generating the interrupt. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] pin - NPSS GPIO pin number (0...4). + * @param[in] polarity - GPIO polarity + * sl_si91x_gpio_polarity_t (GPIO polarity enum): + * - '1' - High + * - '0' - Low + * + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO interrupt as a wake-up source across sleep wakeups. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the UULP NPSS GPIO Interrupt as a wake up source. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected NPSS GPIO interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Unmask the selected NPSS GPIO interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the selected NPSS GPIO interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * - sl_si91x_gpio_configure_uulp_interrupt() + * @param[in] npssgpio_interrupt - OR'ed values of the NPSS GPIO interrupts + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Get the current status of all the NPSS GPIO interrupt status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * - sl_si91x_gpio_configure_uulp_interrupt() + * + * @return Returns the UULP INTR status: + * - 1, interrupt has been raised. + * - 0, interrupt is masked or not raised. + * + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_interrupt_status(void); + +/***************************************************************************/ /** + * @brief Get the selected ULP instance GPIO pin interrupt status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - sl_si91x_gpio_configure_ulp_pin_interrupt() + * @param[in] flags - ULP GPIO interrupt sources status. + * @return Returns the ULP INTR status: + * 1, interrupt has been raised + * 0, interrupt is masked or not raised + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_ulp_interrupt_status(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance GPIO pin interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - sl_si91x_gpio_configure_ulp_pin_interrupt() + * @param[in] flags - ULP GPIO interrupt sources to clear. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_interrupt(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance group interrupt. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * - \ref sl_si91x_gpio_driver_configure_ulp_group_interrupt() + * + * Use the corresponding group interrupt configuration API for the corresponding GPIO instance. + * @param[in] group_interrupt - Group interrupt number of type + * sl_si91x_group_interrupt_t (GPIO group interrupts). + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Configure the UULP GPIO pin interrupt with interrupt type level or edge and registers callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - sl_si91x_gpio_set_uulp_pad_configuration() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] flags - Interrupt configuration flags of type + * sl_si91x_gpio_interrupt_config_flag_t (GPIO Interrupt Configurations structure). + * @param[in] npssgpio_interrupt - NPSS GPIO input number (0 to 4). + * @param[in] gpio_callback - IRQ function pointer. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * - SL_STATUS_NULL_POINTER - The parameter is null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, + uint8_t npssgpio_interrupt, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance group interrupts with trigger type (level/edge), polarity (high/low), interrupt type (and/or) + * and register the callback function for interrupts. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_enable_ulp_pad_receiver() + * - \ref sl_gpio_driver_set_pin_mode() + * - \ref sl_si91x_gpio_driver_set_pin_direction() + * @param[in] configuration - Configuration pointer to + * sl_si91x_gpio_group_interrupt_config_t structure. + * @param[in] gpio_callback - IRQ function pointer. + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback); + +/***************************************************************************/ /** + * @brief Toggle the selected UULP pin status. + * @pre Pre-conditions: + * - \ref sl_si91x_gpio_driver_enable_clock() + * - \ref sl_si91x_gpio_driver_select_uulp_npss_receiver() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux() + * - \ref sl_si91x_gpio_driver_set_uulp_npss_direction() + * @param[in] pin - UULP pin number to toggle + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_INVALID_PARAMETER - The parameter is an invalid argument. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_toggle_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Configure the UULP GPIO pin mode, receiver enable, direction and polarity settings. + * @pre Pre-condition: + * - \ref sl_si91x_gpio_driver_enable_clock() + * @param[in] pad_config : PAD configuration pointer to uulp_pad_config_t structure + * @return Status code indicating the result: + * - SL_STATUS_OK - Success. + * - SL_STATUS_NULL_POINTER - The parameter is a null pointer. + * + * For more information on status codes, refer to [SL STATUS DOCUMENTATION](https://docs.silabs.com/gecko-platform/latest/platform-common/status). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_pad_configuration(uulp_pad_config_t *pad_config); + +/***************************************************************************/ /** +* @brief Get the release, SQA, and development version numbers of the GPIO peripheral. +* @return Returns structure of type sl_si91x_gpio_vversion_t (the structure to hold the versions of peripheral API). +*******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_driver_get_version(void); + +/** @} (end addtogroup GPIO) */ + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup GPIO General-Purpose Input-Output +/// @{ +/// +/// @details +/// +/// @n @section GPIO_Intro Introduction +/// The GPIO (General Purpose Input/Output) driver provides a comprehensive set of functions to +/// configure and control the GPIO pins. The GPIO pins can be used for various purposes such as reading +/// digital signals, controlling external devices, generating interrupts, etc. The GPIO driver simplifies the process of interacting +/// with GPIO pins, making it easier to integrate GPIO functionality into the application. +/// +/// @n @section GPIO_Config Configuration +/// +/// @li To configure the GPIO driver, identify the GPIO instance and pins you want to configure. Set the direction of each pin +/// as either input or output. Then, if needed, set the drive strength for the pins to ensure they can +/// handle the required current. Set the GPIO mux/mode and pad selection, if needed. Configure any interrupt settings, such as trigger type (level or edge) and +/// interrupt polarity (high or low). If interrupts are used, register the appropriate callback functions to handle them. +/// +/// @li Additionally, make sure to enable the GPIO clock for the selected instance to ensure the GPIO peripheral operates correctly. +/// +/// +/// @li These steps are necessary for the GPIO pins to function correctly and trigger interrupts as required by the application. +/// The respective APIs for the same functionality will change depending on the GPIO in use (i.e., Ultra Ultra Low Power (UULP), Ultra Low Power (ULP), or High Power (HP)). +/// +/// @n @section GPIO_Usage Usage +/// +/// @li For UULP GPIOs, common functions include: +/// +/// 1. @ref sl_gpio_driver_configure_interrupt +/// 2. @ref sl_gpio_driver_toggle_pin +/// 3. @ref sl_gpio_driver_get_pin +/// 4. @ref sl_gpio_driver_clear_pin +/// 5. @ref sl_gpio_driver_set_pin +/// 6. @ref sl_gpio_set_configuration +/// +/// @li To set the pin MUX mode, @ref sl_si91x_gpio_driver_set_uulp_npss_pin_mux can be used. +/// For enabling or disabling the input buffer, use @ref sl_si91x_gpio_driver_select_uulp_npss_receiver. Additionally, +/// set pin direction with @ref sl_si91x_gpio_driver_set_uulp_npss_direction. Also, use sl_gpio_set_pin to set the pin value. +/// For configuring UULP pin interrupts, use sl_gpio_configure_pin_interrupt. +/// +/// @li For ULP GPIOs, some of the common functions include: +/// +/// 1. @ref sl_gpio_driver_configure_interrupt +/// 2. @ref sl_gpio_driver_toggle_pin +/// 3. @ref sl_gpio_driver_get_pin +/// 4. @ref sl_gpio_driver_clear_pin +/// 5. @ref sl_gpio_driver_set_pin +/// 6. @ref sl_gpio_set_configuration +/// +/// @li With @ref sl_si91x_gpio_driver_select_ulp_pad_slew_rate, set the slew rate for ULP GPIO pins. With @ref sl_si91x_gpio_driver_select_ulp_pad_driver_strength +/// choose the drive strength. To manage the receiver, @ref sl_si91x_gpio_driver_enable_ulp_pad_receiver and for disabling and enabling the receiver +/// @ref sl_si91x_gpio_driver_enable_ulp_pad_receiver can be used, respectively. For configuring ULP pin interrupts, sl_gpio_configure_pin_interrupt +/// can be used to set up pin interrupts with defined trigger types (level/edge). For configuring ULP group interrupts, @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt, +/// more than '1' gpio pin can be considered for group interrupts. +/// +/// @li For HP GPIOs, some of the common functions include: +/// +/// 1. @ref sl_gpio_set_configuration +/// 2. @ref sl_gpio_driver_set_pin +/// 3. @ref sl_gpio_driver_clear_pin +/// 4. @ref sl_gpio_driver_get_pin +/// 5. @ref sl_gpio_driver_toggle_pin +/// 6. @ref sl_gpio_driver_configure_interrupt +/// +/// @li To configure a GPIO pin, first, use @ref sl_si91x_gpio_driver_set_pin_direction to set its direction. +/// To enable the receiver for reading the pin status, use @ref sl_si91x_gpio_driver_enable_pad_receiver. +/// For selecting the pad, use @ref sl_si91x_gpio_driver_enable_pad_selection. To configure group interrupts for the MCU HP instance, +/// use @ref sl_si91x_gpio_driver_configure_group_interrupt. Make sure to enable the clock for HP or ULP instances, +/// using @ref sl_si91x_gpio_driver_enable_clock. To configure HP pin, use interrupts sl_gpio_configure_pin_interrupt. +/// +/// @li There is also an alternate API for configuring GPIO pin straight forward (without configuring mode, direction, pad, clock, and so on, using separate APIs), by providing +/// information to structure members. See @ref sl_gpio_set_configuration. +/// +/// @li Other APIs can be referred to in the API Documentation. +/// +/// @} end group GPIO ********************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif ///< GPIO_PRESENT +#endif ///< SL_SI91X_DRIVER_GPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c new file mode 100644 index 000000000..ef5fcdcc6 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c @@ -0,0 +1,2067 @@ +/****************************************************************************** +* @file sl_si91x_driver_gpio.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#include "sl_si91x_driver_gpio.h" +#include +#include "sl_status.h" +/******************************************************************************* + *************************** DEFINES / MACROS ******************************** + ******************************************************************************/ +#define GPIO_RELEASE_VERSION 0 // GPIO Release version +#define GPIO_MAJOR_VERSION 0 // GPIO SQA version +#define GPIO_MINOR_VERSION 2 // GPIO Developer version +#define GPIO_DIRECTION_MAX_VALUE 1 // GPIO maximum direction set value +#define GPIO_CLOCK_MAX_VAL 1 // Validating clock for GPIO instance +#define GPIO_GROUP_INTERRUPT_MAX_VALUE 1 // Maximum number of GPIO group interrupts +#define GPIO_LEVEL_EDGE_MAX_VALUE 1 // GPIO maximum level edge value +#define GPIO_POLARITY_MAX_VALUE 1 // GPIO maximum polarity value +#define GPIO_AND_OR_MAX_VALUE 1 // GPIO maximum AND_OR value +#define GPIO_SLEW_RATE_MAX_VALUE 1 // GPIO maximum SLEW RATE value +#define GPIO_RECEIVER_MAX_VALUE 1 // GPIO maximum receiver value +#define GPIO_PIN_VALUE_MAX_VALUE 1 // GPIO maximum pin value +#define GPIO_STRENGTH_MAX_VAL 3 // GPIO maximum strength value +#define GPIO_DISABLE_STATE_MAX_VAL 3 // GPIO maximum disable state value +#define GPIO_UULP_MAX_PIN_NUM 5 // GPIO UULP maximum pin number +#define GPIO_MODE_MAX_VALUE 7 // GPIO maximum MODE value +#define GPIO_INTERRUPT_MAX_VALUE 7 // GPIO interrupt maximum value +#define GPIO_ULP_INTERRUPT_MAX_VALUE 7 // GPIO interrupt maximum value +#define GPIO_ULP_MAX_PIN_NUM 11 // GPIO ULP maximum pin number +#define GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE 16 // NPSSGPIO maximum value +#define GPIO_NPSS_WAKEUP_MAX_VALUE 4 //NPSSGPIO maximum value +#define GPIO_NPSS_PIN_MAX_VALUE 4 //NPSSGPIO pin maximum value +#define GPIO_MAX_PAD_NUM 34 // GPIO maximum pad number +#define GPIO_MAX_PIN_NUM 57 // Maximum number of GPIO pins in m4 instance + +#define ULP_GPIO_INTERRUPT_PRIORITY 18 // Priority 18 for ulp pin interrupt +#define GPIO_INTERRUPT_PRIOPRITY0 52 // Priority 52 for m4 pin interrupt 0 +#define GPIO_INTERRUPT_PRIOPRITY1 53 // Priority 53 for m4 pin interrupt 1 +#define GPIO_INTERRUPT_PRIOPRITY2 54 // Priority 54 for m4 pin interrupt 2 +#define GPIO_INTERRUPT_PRIOPRITY3 55 // Priority 55 for m4 pin interrupt 3 +#define GPIO_INTERRUPT_PRIOPRITY4 56 // Priority 56 for m4 pin interrupt 4 +#define GPIO_INTERRUPT_PRIOPRITY5 57 // Priority 57 for m4 pin interrupt 5 +#define GPIO_INTERRUPT_PRIOPRITY6 58 // Priority 58 for m4 pin interrupt 6 +#define GPIO_INTERRUPT_PRIOPRITY7 59 // Priority 59 for m4 pin interrupt 7 + +#define GPIO_PAD_SELECT_NO_PAD 0 // GPIO PAD selection number 0 +#define GPIO_PAD_SELECT_1 1 // GPIO PAD selection number 1 +#define GPIO_PAD_SELECT_2 2 // GPIO PAD selection number 2 +#define GPIO_PAD_SELECT_3 3 // GPIO PAD selection number 3 +#define GPIO_PAD_SELECT_4 4 // GPIO PAD selection number 4 +#define GPIO_PAD_SELECT_5 5 // GPIO PAD selection number 5 +#define GPIO_PAD_SELECT_6 6 // GPIO PAD selection number 6 +#define GPIO_PAD_SELECT_7 7 // GPIO PAD selection number 7 +#define GPIO_PAD_SELECT_8 8 // GPIO PAD selection number 8 +#define GPIO_PAD_SELECT_9 9 // GPIO PAD selection number 9 +#define GPIO_PAD_SELECT_10 10 // GPIO PAD selection number 10 +#define GPIO_PAD_SELECT_11 11 // GPIO PAD selection number 11 +#define GPIO_PAD_SELECT_12 12 // GPIO PAD selection number 12 +#define GPIO_PAD_SELECT_13 13 // GPIO PAD selection number 13 +#define GPIO_PAD_SELECT_14 14 // GPIO PAD selection number 14 +#define GPIO_PAD_SELECT_15 15 // GPIO PAD selection number 15 +#define GPIO_PAD_SELECT_16 16 // GPIO PAD selection number 16 +#define GPIO_PAD_SELECT_17 17 // GPIO PAD selection number 17 +#define GPIO_PAD_SELECT_18 18 // GPIO PAD selection number 18 +#define GPIO_PAD_SELECT_19 19 // GPIO PAD selection number 19 +#define GPIO_PAD_SELECT_20 20 // GPIO PAD selection number 20 +#define GPIO_PAD_SELECT_21 21 // GPIO PAD selection number 21 +#define GPIO_PAD_SELECT_22 22 // GPIO PAD selection number 22 +#define GPIO_PAD_SELECT_23 23 // GPIO PAD selection number 23 +#define GPIO_PAD_SELECT_24 24 // GPIO PAD selection number 24 +#define GPIO_PAD_SELECT_25 25 // GPIO PAD selection number 25 +#define GPIO_PAD_SELECT_26 26 // GPIO PAD selection number 26 +#define GPIO_PAD_SELECT_27 27 // GPIO PAD selection number 27 +#define GPIO_PAD_SELECT_28 28 // GPIO PAD selection number 28 +#define GPIO_PAD_SELECT_29 29 // GPIO PAD selection number 29 +#define GPIO_PAD_SELECT_30 30 // GPIO PAD selection number 30 +#define GPIO_PAD_SELECT_31 31 // GPIO PAD selection number 31 +#define GPIO_PAD_SELECT_32 32 // GPIO PAD selection number 32 +#define GPIO_PAD_SELECT_33 33 // GPIO PAD selection number 33 +#define OUTPUT_VALUE 0 // GPIO output value +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +///@brief structure to hold GPIO interrupt configurations +typedef struct { + uint8_t gpio_priority[8]; + uint8_t gpio_nvic[8]; +} sl_gpio_intr_configure_t; + +/******************************************************************************* + *************************** LOCAL VARIABLES ********************************* + ******************************************************************************/ + +const sl_gpio_intr_configure_t intr_config = { { GPIO_INTERRUPT_PRIOPRITY0, + GPIO_INTERRUPT_PRIOPRITY1, + GPIO_INTERRUPT_PRIOPRITY2, + GPIO_INTERRUPT_PRIOPRITY3, + GPIO_INTERRUPT_PRIOPRITY4, + GPIO_INTERRUPT_PRIOPRITY5, + GPIO_INTERRUPT_PRIOPRITY6, + GPIO_INTERRUPT_PRIOPRITY7 }, + { PININT0_NVIC_NAME, + PININT1_NVIC_NAME, + PININT2_NVIC_NAME, + PININT3_NVIC_NAME, + PININT4_NVIC_NAME, + PININT5_NVIC_NAME, + PININT6_NVIC_NAME, + PININT7_NVIC_NAME } }; +// The m4_gpio_pad array refers to PAD selected for particular GPIO pin. For example GPIO_0 selects GPIO_PAD_SELECT_NO_PAD. +// GPIO_6 selects GPIO_PAD_SELECT_1, GPIO_7 selects GPIO_PAD_SELECT_2 and so on. +static const uint8_t m4_gpio_pad[76] = { + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_1, GPIO_PAD_SELECT_2, + GPIO_PAD_SELECT_3, GPIO_PAD_SELECT_4, GPIO_PAD_SELECT_5, GPIO_PAD_SELECT_6, + GPIO_PAD_SELECT_7, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_8, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_25, GPIO_PAD_SELECT_26, GPIO_PAD_SELECT_27, + GPIO_PAD_SELECT_28, GPIO_PAD_SELECT_29, GPIO_PAD_SELECT_30, GPIO_PAD_SELECT_9, + GPIO_PAD_SELECT_9, GPIO_PAD_SELECT_9, GPIO_PAD_SELECT_9, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_10, GPIO_PAD_SELECT_11, + GPIO_PAD_SELECT_12, GPIO_PAD_SELECT_13, GPIO_PAD_SELECT_14, GPIO_PAD_SELECT_15, + GPIO_PAD_SELECT_16, GPIO_PAD_SELECT_17, GPIO_PAD_SELECT_18, GPIO_PAD_SELECT_19, + GPIO_PAD_SELECT_20, GPIO_PAD_SELECT_21, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, GPIO_PAD_SELECT_NO_PAD, + GPIO_PAD_SELECT_22, GPIO_PAD_SELECT_23, GPIO_PAD_SELECT_24, GPIO_PAD_SELECT_25, + GPIO_PAD_SELECT_26, GPIO_PAD_SELECT_27, GPIO_PAD_SELECT_28, GPIO_PAD_SELECT_29, + GPIO_PAD_SELECT_30, GPIO_PAD_SELECT_31, GPIO_PAD_SELECT_32, GPIO_PAD_SELECT_33 +}; + +static uint8_t ulp_gpio_pad[12] = { GPIO_PAD_SELECT_22, GPIO_PAD_SELECT_23, GPIO_PAD_SELECT_24, GPIO_PAD_SELECT_25, + GPIO_PAD_SELECT_26, GPIO_PAD_SELECT_27, GPIO_PAD_SELECT_28, GPIO_PAD_SELECT_29, + GPIO_PAD_SELECT_30, GPIO_PAD_SELECT_31, GPIO_PAD_SELECT_32, GPIO_PAD_SELECT_33 }; +/******************************************************************************* + ***********************  Global function Prototypes *************************** + ******************************************************************************/ +void PIN_IRQ0_Handler(void); +void PIN_IRQ1_Handler(void); +void PIN_IRQ2_Handler(void); +void PIN_IRQ3_Handler(void); +void PIN_IRQ4_Handler(void); +void PIN_IRQ5_Handler(void); +void PIN_IRQ6_Handler(void); +void PIN_IRQ7_Handler(void); +void GRP_IRQ0_Handler(void); +void GRP_IRQ1_Handler(void); +void UULP_PIN_IRQ_Handler(void); +void ULP_PIN_IRQ_Handler(void); +void ULP_GROUP_IRQ_Handler(void); + +/******************************************************************************* + ************************ GLOBAL FUNCTIONS ************************** + ******************************************************************************/ +sl_gpio_irq_callback_t gpio_callback_function_pointer[GPIO_MAX_INTR_VALUE]; +sl_gpio_irq_callback_t gpio_group_int_callback_fptr[MAX_GROUP_INT]; +sl_gpio_irq_callback_t gpio_ulp_pin_int_callback_fptr[GPIO_MAX_INTR_VALUE]; +sl_gpio_irq_callback_t gpio_ulp_group_int_callback_fptr[MAX_GROUP_INT]; +sl_gpio_irq_callback_t gpio_uulp_pin_int_callback_fptr[MAX_UULP_INT]; + +/******************************************************************************* + * @brief This API is used for GPIO pin configuration to set the direction, mode, + * pin and port, clock. + ******************************************************************************/ +sl_status_t sl_gpio_set_configuration(sl_si91x_gpio_pin_config_t pin_config) +{ + sl_status_t status; + switch (pin_config.port_pin.port) { + case SL_GPIO_PORT_A: + case SL_GPIO_PORT_B: + case SL_GPIO_PORT_C: + case SL_GPIO_PORT_D: + status = sl_gpio_validation(&pin_config.port_pin); + if (status != SL_STATUS_OK) { + return status; + } + // Check if the GPIO pad is selected and it's not NO PAD. + if (m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin] + != GPIO_PAD_SELECT_NO_PAD) { + // Check if the GPIO pad is selected and not PAD_SELECT_9. + if (m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin] != PAD_SELECT_9) { + if (SL_GPIO_VALIDATE_HOST_PIN(pin_config.port_pin.port, pin_config.port_pin.pin)) { + status = sl_si91x_gpio_driver_enable_host_pad_selection( + m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin]); + if (status != SL_STATUS_OK) { + return status; + } + } else { + status = sl_si91x_gpio_driver_enable_pad_selection( + m4_gpio_pad[(pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + pin_config.port_pin.pin]); + if (status != SL_STATUS_OK) { + return status; + } + } + } + } + // Enable the pad receiver for the pin. It will enable the pad for respective GPIO pin + if (pin_config.port_pin.port == SL_GPIO_PORT_A) { + status = sl_si91x_gpio_driver_enable_pad_receiver(pin_config.port_pin.pin); + if (status != SL_STATUS_OK) { + return status; + } + } else { + status = sl_si91x_gpio_driver_enable_pad_receiver((pin_config.port_pin.port * MAX_GPIO_PORT_PIN) + + pin_config.port_pin.pin); + if (status != SL_STATUS_OK) { + return status; + } + } + // Set pin mode for the pin. By default mode 0 is set, which is a normal GPIO + status = sl_gpio_driver_set_pin_mode(&pin_config.port_pin, (sl_gpio_mode_t)SL_GPIO_MODE_0, OUTPUT_VALUE); + if (status != SL_STATUS_OK) { + return status; + } + sl_si91x_gpio_set_pin_direction(pin_config.port_pin.port, + pin_config.port_pin.pin, + (sl_si91x_gpio_direction_t)pin_config.direction); + break; + default: + break; + } + // Check if the GPIO port is the Ultra-Low Power GPIO port. + if (pin_config.port_pin.port == SL_GPIO_ULP_PORT) { + // Enable pad selection for the pin. + status = sl_si91x_gpio_driver_enable_pad_selection(ulp_gpio_pad[pin_config.port_pin.pin]); + if (status != SL_STATUS_OK) { + return status; + } + // Enable ulp pad receiver for the pin. It will enable the pad for respective GPIO pin + status = sl_si91x_gpio_driver_enable_ulp_pad_receiver(pin_config.port_pin.pin); + if (status != SL_STATUS_OK) { + return status; + } + // Set ulp pin mode for the pin. By default mode 0 is set, which is a normal GPIO + status = sl_gpio_driver_set_pin_mode(&pin_config.port_pin, (sl_gpio_mode_t)SL_GPIO_MODE_0, OUTPUT_VALUE); + if (status != SL_STATUS_OK) { + return status; + } + sl_si91x_gpio_set_pin_direction(pin_config.port_pin.port, + pin_config.port_pin.pin, + (sl_si91x_gpio_direction_t)pin_config.direction); + } + // Check if the GPIO port is the Ultra-Ultra Low Power GPIO port. + if (pin_config.port_pin.port == SL_GPIO_UULP_PORT) { + // Enable uulp pad receiver for the pin. + status = sl_si91x_gpio_driver_select_uulp_npss_receiver(pin_config.port_pin.pin, SET); + if (status != SL_STATUS_OK) { + return status; + } + // Set uulp pin mode for the pin. By default mode 0 is set, which is a normal GPIO + status = sl_si91x_gpio_driver_set_uulp_npss_pin_mux(pin_config.port_pin.pin, + (sl_si91x_uulp_npss_mode_t)NPSS_GPIO_PIN_MUX_MODE0); + if (status != SL_STATUS_OK) { + return status; + } + sl_si91x_gpio_set_uulp_npss_direction(pin_config.port_pin.pin, (sl_si91x_gpio_direction_t)pin_config.direction); + } + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used to configure the pin interrupt in 3 instance. + * To configure the interrupt, first GPIO initialization must be done. + * The actions to be performed in GPIO initialization are: + * - Enable the M4/ULP clock based on GPIO instance. + * - Select PAD selection for GPIO instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + ******************************************************************************/ +sl_status_t sl_gpio_driver_configure_interrupt(sl_gpio_t *gpio, + uint32_t int_no, + sl_gpio_interrupt_flag_t flags, + sl_gpio_irq_callback_t gpio_callback, + uint32_t *avl_intr_no) +{ + sl_status_t status; + (void)avl_intr_no; + // Check if gpio pointer and gpio_callback pointer is NULL + if ((gpio == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if flags exceed maximum allowed value + if (flags > GPIO_FLAGS_MAX_VALUE) { + // Return error code for invalid parameter + return SL_STATUS_INVALID_PARAMETER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + switch (gpio->port) { + case SL_GPIO_PORT_A: + case SL_GPIO_PORT_B: + case SL_GPIO_PORT_C: + case SL_GPIO_PORT_D: + // Check if the interrupt number exceeds the maximum allowed value. + if (int_no > GPIO_MAX_INTR_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given interrupt number. + if (gpio_callback_function_pointer[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Enable the NVIC for the GPIO interrupt and set its priority. + NVIC_EnableIRQ(intr_config.gpio_nvic[int_no]); + NVIC_SetPriority(intr_config.gpio_nvic[int_no], intr_config.gpio_priority[int_no]); + // Assign the callback function pointer for the specified interrupt number. + gpio_callback_function_pointer[int_no] = gpio_callback; + // Configure the GPIO interrupt. + sl_gpio_configure_interrupt(gpio->port, gpio->pin, int_no, flags); + break; + default: + break; + } + // Check if the GPIO port is the Ultra-Low Power GPIO port. + if (gpio->port == SL_GPIO_ULP_PORT) { + // Check if the GPIO pin or interrupt number exceeds the maximum allowed values. + if (int_no > GPIO_ULP_INTERRUPT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given Ultra-Low Power GPIO interrupt number. + if (gpio_ulp_pin_int_callback_fptr[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Enable the NVIC for the Ultra-Low Power GPIO pin interrupt and set its priority. + NVIC_EnableIRQ(ULP_PININT0_NVIC_NAME); + NVIC_SetPriority(ULP_PININT0_NVIC_NAME, ULP_GPIO_INTERRUPT_PRIORITY); + // Assign the callback function pointer for the specified Ultra-Low Power GPIO interrupt number. + gpio_ulp_pin_int_callback_fptr[int_no] = gpio_callback; + // Configure the Ultra-Low Power GPIO pin interrupt. + sl_si91x_gpio_configure_ulp_pin_interrupt((uint8_t)int_no, (sl_si91x_gpio_interrupt_config_flag_t)flags, gpio->pin); + } + // Check if the GPIO port is the Ultra-Ultra Low Power GPIO port. + if (gpio->port == SL_GPIO_UULP_PORT) { + // Check if the GPIO pin or interrupt number exceeds the maximum allowed values. + if (int_no > GPIO_NPSS_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given Ultra-Ultra Low Power GPIO interrupt number. + if (gpio_uulp_pin_int_callback_fptr[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified Ultra-Ultra Low Power GPIO interrupt number. + gpio_uulp_pin_int_callback_fptr[int_no] = gpio_callback; + // Configure the Ultra-Ultra Low Power GPIO interrupt. + sl_si91x_gpio_configure_uulp_interrupt((sl_si91x_gpio_interrupt_config_flag_t)flags, (uint8_t)int_no); + } + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used to configure the group interrupts in 3 instance. + * To configure the interrupt, first GPIO initialization must be done. + * The actions to be performed in GPIO initialization are: + * - Enable the M4/ULP clock based on GPIO instance. + * - Select PAD selection for GPIO instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + ******************************************************************************/ +sl_status_t sl_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if configuration pointer and gpio_callback pointer is NULL. + if ((configuration == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + for (uint8_t i = 0; i < configuration->grp_interrupt_cnt; i++) { + switch (configuration->grp_interrupt_port[i]) { + case SL_GPIO_PORT_A: + case SL_GPIO_PORT_B: + case SL_GPIO_PORT_C: + case SL_GPIO_PORT_D: + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified GPIO interrupt number. + gpio_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO group interrupt. + sl_si91x_gpio_configure_group_interrupt(configuration); + break; + default: + break; + } + if (configuration->grp_interrupt_port[i] == SL_GPIO_ULP_PORT) { + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified ULP GPIO interrupt number. + gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO ULP group interrupt. + sl_si91x_gpio_configure_ulp_group_interrupt(configuration); + } + } + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used for GPIO HP, ULP instances to set pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO HP instance, GPIO initialization needs to + * be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO ULP instance, GPIO initialization needs to + * be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_gpio_driver_set_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t mode, uint32_t output_value) +{ + sl_status_t status; + // Check if the GPIO pointer is NULL. + if (gpio == NULL) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Check if the mode or output value exceeds the maximum allowed values. + if ((mode > MAX_MODE) || (output_value > GPIO_MAX_OUTPUT_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set the mode for the GPIO pin. + sl_gpio_set_pin_mode(gpio->port, gpio->pin, mode, output_value); + return SL_STATUS_OK; +} + +/******************************************************************************* + * @brief This API is used for GPIO HP, ULP instances to get pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin status in GPIO HP instance, GPIO initialization needs + * to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are + * performed: + * - To get the pin mode in GPIO ULP instance, GPIO initialization needs + * to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to + * ULP_GPIO_11). + ******************************************************************************/ +sl_status_t sl_gpio_driver_get_pin_mode(sl_gpio_t *gpio, sl_gpio_mode_t *mode) +{ + sl_status_t status; + // Check if the GPIO pointer and mode pointer is NULL. + if ((gpio == NULL) || (mode == NULL)) { + return SL_STATUS_NULL_POINTER; + } + status = sl_gpio_validation(gpio); + if (status != SL_STATUS_OK) { + return status; + } + // Get the mode for the GPIO pin. + *mode = sl_gpio_get_pin_mode(gpio->port, gpio->pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * Initialization of GPIO driver. + ******************************************************************************/ +sl_status_t sl_gpio_driver_init(void) +{ + uint32_t flag; + sl_status_t status; + GPIO_NPSS_GPIO_CONFIG_REG = CLR; //By default making all the interrupts zero. + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + sl_gpio_driver_clear_interrupts(flag); + gpio_callback_function_pointer[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + sl_si91x_gpio_driver_clear_group_interrupt(flag); + gpio_group_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_UULP_INT; flag++) { + sl_si91x_gpio_driver_clear_uulp_interrupt((uint8_t)flag); + gpio_uulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + sl_si91x_gpio_driver_clear_ulp_interrupt((uint8_t)flag); + gpio_ulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + sl_si91x_gpio_driver_clear_ulp_group_interrupt(flag); + gpio_ulp_group_int_callback_fptr[flag] = NULL; + } + status = sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)M4CLK_GPIO); // Enable GPIO M4_CLK + if (status != SL_STATUS_OK) { + return status; + } + status = sl_si91x_gpio_driver_enable_clock((sl_si91x_gpio_select_clock_t)ULPCLK_GPIO); // Enable GPIO ULP_CLK + if (status != SL_STATUS_OK) { + return status; + } + return SL_STATUS_OK; +} + +/******************************************************************************* +* Get the release, SQA, and development version numbers of the GPIO peripheral. +*******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_driver_get_version(void) +{ + sl_si91x_gpio_version_t version; + version = sl_si91x_gpio_get_version(); + return version; +} + +/******************************************************************************* + * Indicate UULP GPIO PAD configuration. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_pad_configuration(uulp_pad_config_t *pad_config) +{ + // Check if the pad configuration pointer is NULL. + if (pad_config == NULL) { + return SL_STATUS_NULL_POINTER; + } + // Set the UULP pad configuration. + sl_si91x_gpio_set_uulp_pad_configuration(pad_config); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to set pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin direction in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are + * performed: + * - To set the pin direction in GPIO ULP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + // Check if the GPIO port and direction exceeds the maximum allowed value. Returns an invalid parameter if true + if ((port > GPIO_PORT_MAX_VALUE) || (direction > GPIO_DIRECTION_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_UULP_PORT) { + if (pin > UULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Set GPIO pin direction + sl_si91x_gpio_set_pin_direction(port, pin, direction); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to get pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin direction in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * - If GPIO ULP instance is considered, the following actions are + * performed: + * - To get the pin direction in GPIO ULP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_pin_direction(uint8_t port, uint8_t pin) +{ + uint8_t direction; + // Check if the GPIO port exceeds the maximum allowed value. Returns an invalid parameter if true + if (port > GPIO_PORT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Get pin direction for GPIO pin + direction = sl_si91x_gpio_get_pin_direction(port, pin); + return direction; +} + +/******************************************************************************* + * This API is used to enable PAD receiver in GPIO HP instance. + * The actions to be performed for enabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_receiver(uint8_t gpio_num) +{ + // Check if the GPIO pin number exceeds the maximum allowed value. + if (gpio_num > GPIO_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable the pad receiver for the GPIO pin. + sl_si91x_gpio_enable_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to disable PAD receiver in GPIO HP instance. + * The actions to be performed for disabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Disable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_pad_receiver(uint8_t gpio_num) +{ + // Check if the GPIO pin number exceeds the maximum allowed value. + if (gpio_num > GPIO_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Disable the pad receiver for the GPIO pin. + sl_si91x_gpio_disable_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to enable PAD selection in GPIO HP instance. + * The actions to be performed for enable PAD selection are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * @note: PAD number(25 to 30) are used for HOST PAD selection. + * Do not use PAD number-9 as it is used for other functionality. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_pad_selection(uint8_t gpio_padnum) +{ + // Check if the GPIO pad number exceeds the maximum allowed value. + if (gpio_padnum > GPIO_MAX_PAD_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable pad selection for the GPIO pad. + sl_si91x_gpio_enable_pad_selection(gpio_padnum); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to enable HOST PAD selection in GPIO HP instance. + * @note: GPIO pin number(25 to 30) are used for HOST PAD selection. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_host_pad_selection(uint8_t gpio_num) +{ + // Check if the GPIO pin number exceeds the maximum allowed value. + if (!(gpio_num >= HOST_PAD_MIN && gpio_num <= HOST_PAD_MAX)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable host pad selection for the GPIO pin. + sl_si91x_gpio_enable_host_pad_selection(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the PAD driver strength in GPIO HP instance, GPIO + *initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref + * sl_si91x_gpio_driver_strength_select_t. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength) +{ + // Check if GPIO pin number or strength value exceeds the maximum allowed. + if ((gpio_num > GPIO_MAX_PIN_NUM) || (strength > GPIO_STRENGTH_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select the pad driver strength for the GPIO pin. + sl_si91x_gpio_select_pad_driver_strength(gpio_num, strength); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the PAD driver disable state in GPIO HP instance, GPIO + *initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref + * sl_si91x_gpio_driver_disable_state_t. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state) +{ + // Check if GPIO pin number or disable state value exceeds the maximum allowed. + if ((gpio_num > GPIO_MAX_PIN_NUM) || (disable_state > GPIO_DISABLE_STATE_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select the pad driver disable state for the GPIO pin. + sl_si91x_gpio_select_pad_driver_disable_state(gpio_num, disable_state); + return SL_STATUS_OK; +} + +/******************************************************************************* + * The GPIO pins to work in different instances, requires this clock. + * For GPIO HP instance, enable M4 clock of type @ref + * sl_si91x_gpio_select_clock_t. For GPIO ULP/UULP instances, enable ULP + * clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_clock(sl_si91x_gpio_select_clock_t clock) +{ + // Check if clock value exceeds the maximum allowed. + if (clock > GPIO_CLOCK_MAX_VAL) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable the clock. + sl_si91x_gpio_enable_clock(clock); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API disables the M4/ ULP clock of GPIO instances. + * For GPIO HP instance, disable M4 clock of type @ref + * sl_si91x_gpio_select_clock_t. For GPIO ULP/UULP instances, disable ULP + * clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_clock(sl_si91x_gpio_select_clock_t clock) +{ + // Check if clock value exceeds the maximum allowed. + if (clock > GPIO_CLOCK_MAX_VAL) { + return SL_STATUS_INVALID_PARAMETER; + } + // Disable the clock. + sl_si91x_gpio_disable_clock(clock); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to enable the group interrupts. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Enable GPIO group interrupt for selected GPIO port pin + sl_si91x_gpio_enable_group_interrupt(group_interrupt, port, pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to disable the group interrupts. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Disable GPIO group interrupt for selected GPIO port pin + sl_si91x_gpio_disable_group_interrupt(group_interrupt, port, pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to mask the group interrupts. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Mask group interrupt for port + sl_si91x_gpio_mask_group_interrupt(port, group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to unmask the group interrupts. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Unmask group interrupt for port + sl_si91x_gpio_unmask_group_interrupt(port, group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set level/edge event of group interrupt. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge) +{ + // Check if group interrupt or port value or level edge exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) + || (level_edge > GPIO_LEVEL_EDGE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set group interrupt level/edge event + sl_si91x_gpio_set_group_interrupt_level_edge(port, group_interrupt, level_edge); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get level/edge event of group interrupt. + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt or port value exceeds the maximum allowed. + uint8_t level_edge; + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get group interrupt level/edge event + level_edge = sl_si91x_gpio_get_group_interrupt_level_edge(port, group_interrupt); + return level_edge; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set polarity of group interrupt. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not + * use GPIO pin number(0 to 5) in HP instance as these are used for other + * functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity) +{ + // Check if group interrupt or port value or polarity exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (polarity > GPIO_POLARITY_MAX_VALUE) + || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + // Returns invalid parameter status code if pin > ULP_PIN_MAX_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + } + // Set group interrupt polarity for GPIO port pin + sl_si91x_gpio_set_group_interrupt_polarity(group_interrupt, port, pin, polarity); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get polarity of group interrupt . + * @note: Select HP GPIO pins for HP instances(6 to 57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + uint8_t polarity = 0; + // Check if group interrupt or port value exceeds the maximum allowed. + if ((group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) || (port > GPIO_PORT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Checks if the port is Port A. If true, checks if the pin value exceeds + // the maximum allowable value for Port A. Returns an invalid parameter status code if true + if (port == SL_GPIO_PORT_A) { + if (pin > PORTA_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is either Port B or Port C. If true, checks if the pin value exceeds + // the maximum allowable value for these ports. Returns an invalid parameter status code if true. + if ((port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C)) { + if (pin > PORT_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Checks if the port is Port D. If true, checks if the pin value exceeds the maximum allowable + // value for Port D. Returns an invalid parameter status code if true. + if (port == SL_GPIO_PORT_D) { + if (pin > PORTD_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Check if the GPIO port is the Ultra-Low Power GPIO port and if the pin exceeds the maximum allowed values. + if (port == SL_GPIO_ULP_PORT) { + if (pin > ULP_PIN_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + } + // Get group interrupt polarity for GPIO port pin + polarity = sl_si91x_gpio_get_group_interrupt_polarity(group_interrupt, port, pin); + return polarity; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to select and/or event of group interrupt. + * @example: Consider two GPIO pins for group interrupts. + * - If AND event is selected then both GPIO pins, interrupt should be + * generated to do specific task. + * - If OR event is selected then any one GPIO pin, interrupt + * generation should be enough to do specific task. + * @note: We are calling this API, inside the group interrupt + * configuration API's + * @ref sl_si91x_gpio_driver_configure_group_interrupt(), used for HP + * instance, + * @ref sl_si91x_gpio_driver_configure_ulp_group_interrupt(), used for ULP + * instance. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or) +{ + // Check if group interrupt or port value or and_or exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) + || (and_or > GPIO_AND_OR_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select group interrupt AND/OR event + sl_si91x_gpio_select_group_interrupt_and_or(port, group_interrupt, and_or); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used in GPIO HP instance to configure group interrupts. + * It has configuration pointer of type @ref + * sl_si91x_gpio_group_interrupt_config_t structure. GPIO HP instance has + * total 4 ports. Port-A, B, C has 16 pins each. Port-D has 9 pins. While + * configuring group interrupts, one can select random ports and pins for + * group interrupt. + * @example 1: + * - If port 1 is selected, any group of pins(0 to 16) can be selected for + * group interrupt. + * - Same applied for other ports also. + * @example 2: + * - Once can select port B, pin 7 and port C, pin 3 as a group for + * interrupt generation. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration + * structure + * @ref sl_si91x_gpio_driver_group_interrupt_config_t. + * @note: Do not use Port A, GPIO pin number(0 to 5) in HP instance + * as these are used for other functionality. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if configuration pointer and gpio_callback pointer is NULL. + if ((configuration == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified GPIO interrupt number. + gpio_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO group interrupt. + sl_si91x_gpio_configure_group_interrupt(configuration); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO ULP instance. + * There are total 12 pin interrupts in this instance. + * To configure the interrupt, first ULP GPIO initialization must be done. + * The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_pin_interrupt(uint8_t int_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if gpio_callback pointer is NULL. + if (gpio_callback == NULL) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if interrupt number or flags or pin exceeds the maximum allowed. + if ((int_no > GPIO_ULP_INTERRUPT_MAX_VALUE) || (flags > GPIO_FLAGS_MAX_VALUE) || (pin > ULP_PIN_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_ulp_pin_int_callback_fptr[int_no] != NULL) { + return SL_STATUS_BUSY; + } + // Enable the NVIC for the GPIO interrupt and set its priority. + NVIC_EnableIRQ(ULP_PININT0_NVIC_NAME); + NVIC_SetPriority(ULP_PININT0_NVIC_NAME, ULP_GPIO_INTERRUPT_PRIORITY); + // Assign the callback function pointer for the specified ULP GPIO interrupt number. + gpio_ulp_pin_int_callback_fptr[int_no] = gpio_callback; + // Configure the GPIO ULP pin interrupt. + sl_si91x_gpio_configure_ulp_pin_interrupt(int_no, flags, pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used in GPIO ULP instance to configure group interrupts. + * It has configuration pointer of type @ref + * sl_si91x_gpio_group_interrupt_config_t structure. ULP GPIO domain has + * only one port and calling as Port 4 in program which has maximum of 12 + * pins. While configuring group interrupts, one can select random pins + * which are allocated for ULP port. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration + * structure + * @ref sl_si91x_gpio_group_interrupt_config_t. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if configuration pointer and gpio_callback pointer is NULL. + if ((configuration == NULL) || (gpio_callback == NULL)) { + // Return error code for NULL pointer + return SL_STATUS_NULL_POINTER; + } + // Check if a callback function is already registered for the given GPIO interrupt number. + if (gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Assign the callback function pointer for the specified ULP GPIO interrupt number. + gpio_ulp_group_int_callback_fptr[configuration->grp_interrupt] = gpio_callback; + // Configure the GPIO ULP group interrupt. + sl_si91x_gpio_configure_ulp_group_interrupt(configuration); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP instance. + * It is used to clear group interrupt. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group_interrupt exceeds the maximum allowed. + if (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clear GPIO group interrupt + sl_si91x_gpio_clear_group_interrupt(group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to get status of group interrupt generated. + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + uint32_t status; + // Check if group_interrupt or port exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get GPIO group interrupt status + status = sl_si91x_gpio_get_group_interrupt_status(port, group_interrupt); + return status; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to select group interrupt wakeup. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_wakeup_t flags) +{ + // Check if group_interrupt or port exceeds the maximum allowed. + if ((port > GPIO_PORT_MAX_VALUE) || (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) + || (flags > GPIO_FLAGS_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select GPIO group interrupt wakeup + sl_si91x_gpio_select_group_interrupt_wakeup(port, group_interrupt, flags); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To enable ULP PAD receiver in GPIO ULP instance, ULP GPIO + * initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to + * ULP_GPIO_11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_enable_ulp_pad_receiver(uint8_t gpio_num) +{ + // Check if gpio_num exceeds the maximum allowed + if (gpio_num > GPIO_ULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Enable ULP GPIO pad receiver + sl_si91x_gpio_enable_ulp_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to disable the ULP PAD receiver. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to + * ULP_GPIO_11). + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_disable_ulp_pad_receiver(uint8_t gpio_num) +{ + // Check if gpio_num exceeds the maximum allowed + if (gpio_num > GPIO_ULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Disable ULP GPIO pad receiver + sl_si91x_gpio_disable_ulp_pad_receiver(gpio_num); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the ULP PAD driver disable state in GPIO ULP instance, ULP + * GPIO initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref + * sl_si91x_gpio_driver_disable_state_t. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state) +{ + // Check if gpio_num or disable_state exceeds the maximum allowed + if ((gpio_num > GPIO_ULP_MAX_PIN_NUM) || (disable_state > GPIO_DISABLE_STATE_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select ULP GPIO pad driver disable state + sl_si91x_gpio_select_ulp_pad_driver_disable_state(gpio_num, disable_state); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the ULP PAD driver strength in GPIO ULP instance, ULP GPIO + *initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref + * sl_si91x_gpio_driver_strength_select_t. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_driver_strength(uint8_t gpio_num, + sl_si91x_gpio_driver_strength_select_t strength) +{ + // Check if gpio_num or strength exceeds the maximum allowed + if ((gpio_num > GPIO_ULP_MAX_PIN_NUM) || (strength > GPIO_STRENGTH_MAX_VAL)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select ULP GPIO pad driver strength + sl_si91x_gpio_select_ulp_pad_driver_strength(gpio_num, strength); + return SL_STATUS_OK; +} + +/******************************************************************************* + * To select the ULP PAD slew rate in GPIO ULP instance, ULP GPIO + * initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is + * selected as output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD slew rate of type @ref sl_si91x_gpio_slew_rate_t. + * @note: Select ULP GPIO pins for ULP instances(0 to 11). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate) +{ + // Check if gpio_num or slew_rate exceeds the maximum allowed + if ((gpio_num > GPIO_ULP_MAX_PIN_NUM) || (slew_rate > GPIO_SLEW_RATE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select ULP GPIO pad slew rate + sl_si91x_gpio_select_ulp_pad_slew_rate(gpio_num, slew_rate); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to select the UULP mode in NPSS GPIO control register. + * Few actions are required to be performed before setting the mode, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode) +{ + // Check if pin or mode exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (mode > GPIO_MODE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO pin mode + sl_si91x_gpio_set_uulp_npss_pin_mux(pin, mode); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to enable receiver bit in NPSS GPIO control register. + * Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API, + * before using this API. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver) +{ + // Check if pin or receiver exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (receiver > GPIO_RECEIVER_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select UULP GPIO receiver + sl_si91x_gpio_select_uulp_npss_receiver(pin, receiver); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to select the UULP direction in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Select UULP NPSS direction for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + // Check if pin or direction exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (direction > GPIO_DIRECTION_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO direction + sl_si91x_gpio_set_uulp_npss_direction(pin, direction); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to get the UULP direction in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Get the direction of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + *******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_direction(uint8_t pin) +{ + uint8_t direction; + // Check if pin exceeds the maximum allowed + if (pin > GPIO_UULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get UULP GPIO direction + direction = sl_si91x_gpio_get_uulp_npss_direction(pin); + return direction; +} + +/******************************************************************************* + * This API is used to select the UULP pin value in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value) +{ + // Check if pin or pin_value exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (pin_value > GPIO_PIN_VALUE_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO pin value + sl_si91x_gpio_set_uulp_npss_pin_value(pin, pin_value); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to toggle the UULP pin. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Toggle the UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_toggle_uulp_npss_pin(uint8_t pin) +{ + // Check if pin exceeds the maximum allowed + if (pin > GPIO_UULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Toggle UULP GPIO pin + sl_si91x_gpio_toggle_uulp_npss_pin(pin); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to get the UULP pin value in NPSS GPIO control + * register. Few actions are required to be performed before setting the + * direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * - Get the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(0 to 4). + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_npss_pin(uint8_t pin) +{ + uint8_t uulp_pin; + // Check if pin exceeds the maximum allowed + if (pin > GPIO_UULP_MAX_PIN_NUM) { + return SL_STATUS_INVALID_PARAMETER; + } + // Get UULP GPIO pin + uulp_pin = sl_si91x_gpio_get_uulp_npss_pin(pin); + return uulp_pin; +} + +/******************************************************************************* + * This API is used to select polarity of the UULP GPIO to be considered + when used as a wakeup source from any of the Sleep States. + ******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity) +{ + // Check if pin or polarity exceeds the maximum allowed + if ((pin > GPIO_UULP_MAX_PIN_NUM) || (polarity > GPIO_POLARITY_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Select UULP GPIO polarity + sl_si91x_gpio_select_uulp_npss_polarity(pin, polarity); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to set the UULP NPSS GPIO to wakeup interrupt + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSS_WAKEUP_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Set UULP GPIO wakeup interrupt + sl_si91x_gpio_set_uulp_npss_wakeup_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear the UULP NPSS GPIO to wakeup interrupt + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSS_WAKEUP_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clear UULP GPIO wakeup interrupt + sl_si91x_gpio_clear_uulp_npss_wakeup_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt mask is + * performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Select the . + * @note: All the UULP interrupts are masked by default. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Mask UULP GPIO interrupt + sl_si91x_gpio_mask_uulp_npss_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * Get the NPSS GPIO interrupt status. + ******************************************************************************/ +uint8_t sl_si91x_gpio_driver_get_uulp_interrupt_status(void) +{ + uint8_t status; + status = sl_si91x_gpio_get_uulp_interrupt_status(); + return status; +} + +/******************************************************************************* + * Get the ULP GPIO interrupt status. + ******************************************************************************/ +uint32_t sl_si91x_gpio_driver_get_ulp_interrupt_status(uint32_t flags) +{ + uint32_t status; + status = sl_si91x_gpio_get_ulp_interrupt_status(flags); + return status; +} + +/******************************************************************************* + * This API is used to un-mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt un-mask is + * performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Un-mask interrupt by setting corresponding bit in register. + * @note: All the UULP interrupts are masked by default. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Unmask UULP GPIO interrupt + sl_si91x_gpio_unmask_uulp_npss_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear the UULP interrupt. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_uulp_interrupt(uint8_t npssgpio_interrupt) +{ + // Check if npssgpio_interrupt exceeds the maximum allowed + if (npssgpio_interrupt > GPIO_NPSSGPIO_INTERRUPT_VALUE_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clear UULP GPIO interrupt + sl_si91x_gpio_clear_uulp_interrupt(npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO UULP instance. + * There are total 5 pin interrupts in this instance. + * To configure the interrupt, first UULP GPIO initialization must be + * done. The actions to be performed in UULP GPIO initialization are: + * - Enable the ULP clock using @ref sl_si91x_gpio_driver_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Configure the UULP pin interrupt. + * Enable the IRQ handler. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, + uint8_t npssgpio_interrupt, + sl_gpio_irq_callback_t gpio_callback) +{ + // Check if gpio_callback pointer is NULL + if (gpio_callback == NULL) { + return SL_STATUS_NULL_POINTER; + } + // Check if a callback function is already registered for the given interrupt number. + if (gpio_uulp_pin_int_callback_fptr[npssgpio_interrupt] != NULL) { + return SL_STATUS_BUSY; + } + // Check if npssgpio_interrupt or flags exceeds the maximum allowed + if ((flags > GPIO_FLAGS_MAX_VALUE) || (npssgpio_interrupt > GPIO_NPSS_PIN_MAX_VALUE)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Assign the callback function pointer for the specified interrupt number. + gpio_uulp_pin_int_callback_fptr[npssgpio_interrupt] = gpio_callback; + // Configure the UULP GPIO interrupt. + sl_si91x_gpio_configure_uulp_interrupt(flags, npssgpio_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear one (or) more pending ULP GPIO interrupts. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_interrupt(uint32_t flags) +{ + // Check if flags exceeds the maximum allowed. + if (flags > GPIO_FLAGS_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clears ULP GPIO pin interrupt + sl_si91x_gpio_clear_ulp_interrupt(flags); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API is used to clear the ULP group interrupts. + *******************************************************************************/ +sl_status_t sl_si91x_gpio_driver_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + // Check if group interrupt exceeds the maximum allowed. + if (group_interrupt > GPIO_GROUP_INTERRUPT_MAX_VALUE) { + return SL_STATUS_INVALID_PARAMETER; + } + // Clears ULP GPIO group interrupt + sl_si91x_gpio_clear_ulp_group_interrupt(group_interrupt); + return SL_STATUS_OK; +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 0 request + ******************************************************************************/ +void PIN_IRQ0_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_0); + gpio_callback_function_pointer[PIN_INTR_0](PIN_INTR_0); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 1 request + ******************************************************************************/ +void PIN_IRQ1_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_1); + gpio_callback_function_pointer[PIN_INTR_1](PIN_INTR_1); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 2 request + ******************************************************************************/ +void PIN_IRQ2_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_2); + gpio_callback_function_pointer[PIN_INTR_2](PIN_INTR_2); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 3 request + ******************************************************************************/ +void PIN_IRQ3_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_3); + gpio_callback_function_pointer[PIN_INTR_3](PIN_INTR_3); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 4 request + ******************************************************************************/ +void PIN_IRQ4_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_4); + gpio_callback_function_pointer[PIN_INTR_4](PIN_INTR_4); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 5 request + ******************************************************************************/ +void PIN_IRQ5_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_5); + gpio_callback_function_pointer[PIN_INTR_5](PIN_INTR_5); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 6 request + ******************************************************************************/ +void PIN_IRQ6_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_6); + gpio_callback_function_pointer[PIN_INTR_6](PIN_INTR_6); +} + +/******************************************************************************* + * This API handles GPIO pin interrupt 7 request + ******************************************************************************/ +void PIN_IRQ7_Handler(void) +{ + sl_gpio_driver_clear_interrupts(PIN_INTR_7); + gpio_callback_function_pointer[PIN_INTR_7](PIN_INTR_7); +} +/******************************************************************************* + * This API handles GPIO Group interrupt 0 request + ******************************************************************************/ +void GRP_IRQ0_Handler(void) +{ + sl_si91x_gpio_driver_clear_group_interrupt(GROUP_INT_1); + gpio_group_int_callback_fptr[GROUP_INT_1](GROUP_INT_1); +} + +/******************************************************************************* + * This API handles GPIO Group interrupt 1 request + ******************************************************************************/ +void GRP_IRQ1_Handler(void) +{ + sl_si91x_gpio_driver_clear_group_interrupt(GROUP_INT_2); + gpio_group_int_callback_fptr[GROUP_INT_2](GROUP_INT_2); +} + +/******************************************************************************* + * This API handles UULP GPIO pin interrupt 0 request + ******************************************************************************/ +void UULP_PIN_IRQ_Handler(void) +{ + uint32_t flag = 0; + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_1) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_1); + flag = PIN_INTR_0; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_2) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_2); + flag = PIN_INTR_1; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_3) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_3); + flag = PIN_INTR_2; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_4) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_4); + flag = PIN_INTR_3; + } + if ((sl_si91x_gpio_driver_get_uulp_interrupt_status() & UULP_INTR_5) != UULP_MASK) { + sl_si91x_gpio_driver_clear_uulp_interrupt(UULP_INTR_5); + flag = PIN_INTR_4; + } + if (gpio_uulp_pin_int_callback_fptr[flag] != NULL) { + gpio_uulp_pin_int_callback_fptr[flag](flag); + } +} + +/******************************************************************************* + * This API handles ULP GPIO OR'ed pin interrupt request + ******************************************************************************/ +void ULP_PIN_IRQ_Handler(void) +{ + uint32_t flag = 0; + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_0)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_0); + flag = ULP_PIN_INTR_0; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_1)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_1); + flag = ULP_PIN_INTR_1; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_2)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_2); + flag = ULP_PIN_INTR_2; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_3)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_3); + flag = ULP_PIN_INTR_3; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_4)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_4); + flag = ULP_PIN_INTR_4; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_5)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_5); + flag = ULP_PIN_INTR_5; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_6)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_6); + flag = ULP_PIN_INTR_6; + } + if ((sl_si91x_gpio_driver_get_ulp_interrupt_status(ULP_PIN_INTR_7)) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_interrupt(ULP_PIN_INTR_7); + flag = ULP_PIN_INTR_7; + } + gpio_ulp_pin_int_callback_fptr[flag](flag); +} + +/******************************************************************************* + * This API handles ULP GPIO group interrupt request + ******************************************************************************/ +void ULP_GROUP_IRQ_Handler(void) +{ + uint32_t flag = 0; + if (sl_si91x_gpio_get_group_interrupt_status(SL_GPIO_ULP_PORT, GROUP_INT_1) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_group_interrupt(GROUP_INT_1); + flag = GROUP_INT_1; + } + if (sl_si91x_gpio_get_group_interrupt_status(SL_GPIO_ULP_PORT, GROUP_INT_2) == ULP_STATUS) { + sl_si91x_gpio_driver_clear_ulp_group_interrupt(GROUP_INT_2); + flag = GROUP_INT_2; + } + + gpio_ulp_group_int_callback_fptr[flag](flag); +} + +/******************************************************************************* + * De-Initialization of GPIO driver. + ******************************************************************************/ +sl_status_t sl_gpio_driver_deinit(void) +{ + sl_status_t status; + uint8_t flag; + do { + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + gpio_callback_function_pointer[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + gpio_group_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_UULP_INT; flag++) { + gpio_uulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < GPIO_MAX_INTR_VALUE; flag++) { + gpio_ulp_pin_int_callback_fptr[flag] = NULL; + } + for (flag = 0; flag < MAX_GROUP_INT; flag++) { + gpio_ulp_group_int_callback_fptr[flag] = NULL; + } + status = sl_si91x_gpio_driver_disable_clock(M4CLK_GPIO); // Disables M4 GPIO clock + if (status != SL_STATUS_OK) { + return status; + } + status = sl_si91x_gpio_driver_disable_clock(ULPCLK_GPIO); // Disables ULP GPIO clock + if (status != SL_STATUS_OK) { + return status; + } + } while (false); + return SL_STATUS_OK; +} + +/******************************************************************************* + * Unregister GPIO interrupts + ******************************************************************************/ +sl_status_t sl_gpio_driver_unregister(sl_si91x_gpio_instances_t gpio_instance, + sl_si91x_gpio_intr_t gpio_intr, + uint8_t flag) +{ + if (gpio_instance >= GPIO_INSTANCE_LAST) { + // Returns invalid parameter status code if gpio_instance > GPIO_INSTANCE_LAST + return SL_STATUS_INVALID_PARAMETER; + } + switch (gpio_instance) { + case M4_GPIO_INSTANCE: + switch (gpio_intr) { + case GPIO_PIN_INTERRUPT: + if (flag > GPIO_MAX_INTR_VALUE) { + // Returns invalid parameter status code if flag > GPIO_MAX_INTR_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + gpio_callback_function_pointer[flag] = NULL; + break; + case GPIO_GROUP_INTERRUPT: + if (flag > MAX_GROUP_INT) { + // Returns invalid parameter status code if flag > MAX_GROUP_INT + return SL_STATUS_INVALID_PARAMETER; + } + gpio_group_int_callback_fptr[flag] = NULL; + break; + } + break; + case ULP_GPIO_INSTANCE: + switch (gpio_intr) { + case GPIO_PIN_INTERRUPT: + if (flag > GPIO_MAX_INTR_VALUE) { + // Returns invalid parameter status code if flag > GPIO_MAX_INTR_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + gpio_ulp_pin_int_callback_fptr[flag] = NULL; + break; + case GPIO_GROUP_INTERRUPT: + if (flag > MAX_GROUP_INT) { + // Returns invalid parameter status code if flag > MAX_GROUP_INT + return SL_STATUS_INVALID_PARAMETER; + } + gpio_ulp_group_int_callback_fptr[flag] = NULL; + break; + } + break; + case UULP_GPIO_INSTANCE: + if (flag > MAX_UULP_INT) { + // Returns invalid parameter status code if flag > GPIO_MAX_INTR_VALUE + return SL_STATUS_INVALID_PARAMETER; + } + gpio_uulp_pin_int_callback_fptr[flag] = NULL; + break; + case GPIO_INSTANCE_LAST: + break; + default: + break; + } + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h new file mode 100644 index 000000000..7035b1b85 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio.h @@ -0,0 +1,1027 @@ +/****************************************************************************** +* @file sl_si91x_gpio.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#ifndef SL_SI91X_GPIO_PERIPHERAL_H +#define SL_SI91X_GPIO_PERIPHERAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +//// Includes +#include "sl_si91x_gpio_common.h" + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ +///@brief NPSS GPIO PIN MUX +typedef enum { + NPSS_GPIO_PIN_MUX_MODE0, ///< NPSS Pin MUX Mode 0 + NPSS_GPIO_PIN_MUX_MODE1, ///< NPSS Pin MUX Mode 1 + NPSS_GPIO_PIN_MUX_MODE2, ///< NPSS Pin MUX Mode 2 + NPSS_GPIO_PIN_MUX_MODE3, ///< NPSS Pin MUX Mode 3 + NPSS_GPIO_PIN_MUX_MODE4, ///< NPSS Pin MUX Mode 4 + NPSS_GPIO_PIN_MUX_MODE5, ///< NPSS Pin MUX Mode 5 + NPSS_GPIO_PIN_MUX_MODE6, ///< NPSS Pin MUX Mode 6 + NPSS_GPIO_PIN_MUX_MODE7, ///< NPSS Pin MUX Mode 7 + NPSS_GPIO_PIN_MUX_MODE8, ///< NPSS Pin MUX Mode 8 + NPSS_GPIO_PIN_MUX_MODE9, ///< NPSS Pin MUX Mode 9 + NPSS_GPIO_PIN_MUX_MODE10, ///< NPSS Pin MUX Mode 10 +} sl_si91x_uulp_npss_mode_t; + +///@brief GPIO group interrupts +typedef enum { + GROUP_INT_1 = 0, ///< GPIO group interrupt 1 + GROUP_INT_2 = 1, ///< GPIO group interrupt 2 +} sl_si91x_group_interrupt_t; + +///@brief GPIO Interrupt Configurations. +typedef enum { + SL_GPIO_INTERRUPT_LEVEL_HIGH = (1 << 0), ///< interrupt when pin level is '1' + SL_GPIO_INTERRUPT_LEVEL_LOW = (1 << 1), ///< interrupt when pin level is '0' + SL_GPIO_INTERRUPT_RISE_EDGE = (1 << 2), ///< interrupt when rising edge is detected + SL_GPIO_INTERRUPT_FALL_EDGE = (1 << 3), ///< interrupt when falling edge is detected +} sl_si91x_gpio_interrupt_config_flag_t; + +///@brief GPIO driver disable state +typedef enum { + GPIO_HZ = 0, ///< 0 for Hi-impedance (P1=0,P2=0) + GPIO_PULLUP, ///< 1 for Pull up (P1=0,P2=1) + GPIO_PULLDOWN, ///< 2 for Pull down(P1=1,P2=0) + GPIO_REPEATER ///< 3 for Repeater (P1=1,P2=1) +} sl_si91x_gpio_driver_disable_state_t; + +///@brief GPIO driver strength select +typedef enum { + GPIO_TWO_MILLI_AMPS = 0, ///< 0 for two_milli_amps (E1=0,E2=0) + GPIO_FOUR_MILLI_AMPS, ///< 1 for four_milli_amps (E1=0,E2=1) + GPIO_EIGHT_MILLI_AMPS, ///< 2 for eight_milli_amps (E1=1,E2=0) + GPIO_TWELVE_MILLI_AMPS ///< 3 for twelve_milli_amps(E1=1,E2=1) +} sl_si91x_gpio_driver_strength_select_t; + +///@brief HP/ULP GPIO clock select +typedef enum { + M4CLK_GPIO = 0, ///< 0 for HP GPIO clock + ULPCLK_GPIO = 1 ///< 1 for ULP GPIO clock +} sl_si91x_gpio_select_clock_t; + +///@brief Direction of the GPIO pin enum +typedef enum { + GPIO_OUTPUT = 0, ///< GPIO direction output + GPIO_INPUT = 1, ///< GPIO direction input +} sl_si91x_gpio_direction_t; + +///@brief UULP GPIO PAD select enum +typedef enum { + GPIO_PAD_M4 = 0, ///< GPIO M4 PAD selection + GPIO_PAD_TA = 1, ///< GPIO NWP PAD selection +} sl_si91x_gpio_uulp_pad_t; + +///@brief AND/OR of the GPIO group interrupt +typedef enum { + GPIO_AND = 0, ///< GPIO AND group interrupt + GPIO_OR = 1, ///< GPIO OR group interrupt +} sl_si91x_gpio_and_or_t; + +///@brief GPIO group interrupt wakeup flag +typedef enum { + GPIO_FLAG_DS = 0, ///< wakeup flag disable + GPIO_FLAG_EN = 1, ///< wakeup flag enable +} sl_si91x_gpio_wakeup_t; + +///@brief GPIO polarity enum +typedef enum { + GPIO_POLARITY_0 = 0, ///< GPIO polarity 0 + GPIO_POLARITY_1 = 1, ///< GPIO polarity 1 +} sl_si91x_gpio_polarity_t; + +///@brief GPIO level edge select +typedef enum { + GPIO_LEVEL = 0, ///< GPIO level trigger + GPIO_EDGE = 1, ///< GPIO edge trigger +} sl_si91x_gpio_level_edge_t; + +///@brief GPIO slew rate select +typedef enum { + GPIO_SR_LOW = 0, ///< GPIO slew rate low + GPIO_SR_HIGH = 1, ///< GPIO slew rate high +} sl_si91x_gpio_slew_rate_t; + +///@brief GPIO pin set/clear +typedef enum { + GPIO_PIN_CLEAR = 0, ///< GPIO clear pin + GPIO_PIN_SET = 1, ///< GPIO set pin +} sl_si91x_gpio_pin_value_t; + +///@brief NPSS GPIO input buffer +typedef enum { + GPIO_RECEIVER_DS = 0, ///< receiver disable + GPIO_RECEIVER_EN = 1, ///< receiver enable +} sl_si91x_gpio_receiver_t; + +///@brief UULP GPIO PAD configuration register fields +typedef struct { + uint8_t gpio_padnum; ///< UULP GPIO pin number + sl_si91x_uulp_npss_mode_t mode; ///< UULP GPIO mode + sl_si91x_gpio_receiver_t receiver; ///< UULP GPIO PAD receiver + sl_si91x_gpio_direction_t direction; ///< UULP GPIO direction of PAD + sl_si91x_gpio_pin_value_t output; ///< UULP GPIO value driven on PAD + sl_si91x_gpio_uulp_pad_t pad_select; ///< UULP GPIO PAD selection + sl_si91x_gpio_polarity_t polarity; ///< UULP GPIO Polarity +} uulp_pad_config_t; + +///@brief GPIO Group Interrupt Configuration. It selects random ports and pins. +typedef struct { + sl_si91x_group_interrupt_t grp_interrupt; ///< configure group interrupt + uint8_t grp_interrupt_cnt; ///< Count of group interrupt pins + uint8_t grp_interrupt_port[MAX_GPIO_PIN_INT]; ///< ports used for group interrupts + uint8_t grp_interrupt_pin[MAX_GPIO_PIN_INT]; ///< pins used for group interrupts + uint8_t grp_interrupt_pol[MAX_GPIO_PIN_INT]; ///< polarity used for interrupts + sl_si91x_gpio_level_edge_t level_edge; ///< configure level or edge trigger + sl_si91x_gpio_and_or_t and_or; ///< AND/OR ing of interrupts +} sl_si91x_gpio_group_interrupt_config_t; + +///@brief GPIO pin numbers +typedef enum { + GPIO_PIN_NUMBER0 = 0, ///< GPIO pin number 0 + GPIO_PIN_NUMBER1 = 1, ///< GPIO pin number 1 + GPIO_PIN_NUMBER2 = 2, ///< GPIO pin number 2 + GPIO_PIN_NUMBER3 = 3, ///< GPIO pin number 3 + GPIO_PIN_NUMBER4 = 4, ///< GPIO pin number 4 + GPIO_PIN_NUMBER5 = 5, ///< GPIO pin number 5 + GPIO_PIN_NUMBER6 = 6, ///< GPIO pin number 6 + GPIO_PIN_NUMBER7 = 7, ///< GPIO pin number 7 + GPIO_PIN_NUMBER8 = 8, ///< GPIO pin number 8 + GPIO_PIN_NUMBER9 = 9, ///< GPIO pin number 9 + GPIO_PIN_NUMBER10 = 10, ///< GPIO pin number 10 + GPIO_PIN_NUMBER11 = 11, ///< GPIO pin number 11 + GPIO_PIN_NUMBER12 = 12, ///< GPIO pin number 12 + GPIO_PIN_NUMBER13 = 13, ///< GPIO pin number 13 + GPIO_PIN_NUMBER14 = 14, ///< GPIO pin number 14 + GPIO_PIN_NUMBER15 = 15, ///< GPIO pin number 15 +} sl_si91x_gpio_pin_t; + +///@brief GPIO ULP pin numbers +typedef enum { + ULP_GPIO_PIN_0 = 0, ///< ULP GPIO pin number 0 + ULP_GPIO_PIN_1 = 1, ///< ULP GPIO pin number 1 + ULP_GPIO_PIN_2 = 2, ///< ULP GPIO pin number 2 + ULP_GPIO_PIN_3 = 3, ///< ULP GPIO pin number 3 + ULP_GPIO_PIN_4 = 4, ///< ULP GPIO pin number 4 + ULP_GPIO_PIN_5 = 5, ///< ULP GPIO pin number 5 + ULP_GPIO_PIN_6 = 6, ///< ULP GPIO pin number 6 + ULP_GPIO_PIN_7 = 7, ///< ULP GPIO pin number 7 + ULP_GPIO_PIN_8 = 8, ///< ULP GPIO pin number 8 + ULP_GPIO_PIN_9 = 9, ///< ULP GPIO pin number 9 + ULP_GPIO_PIN_10 = 10, ///< ULP GPIO pin number 10 + ULP_GPIO_PIN_11 = 11, ///< ULP GPIO pin number 11 +} sl_si91x_gpio_pin_ulp_t; + +///@brief GPIO instances +typedef enum { + M4_GPIO_INSTANCE = 1, ///< 1 for HP GPIO + ULP_GPIO_INSTANCE = 2, ///< 2 for ULP GPIO + UULP_GPIO_INSTANCE = 3, ///< 3 for UULP GPIO + GPIO_INSTANCE_LAST, ///< Last enum for validating +} sl_si91x_gpio_instances_t; + +///@brief GPIO interrupt type +typedef enum { + GPIO_PIN_INTERRUPT, ///< 0 for GPIO pin interrupt + GPIO_GROUP_INTERRUPT, ///< 1 for GPIO group interrupt +} sl_si91x_gpio_intr_t; + +/// @brief Structure to hold the versions of peripheral API +typedef struct { + uint8_t release; ///< Release version number + uint8_t major; ///< SQA version number + uint8_t minor; ///< Development version number +} sl_si91x_gpio_version_t; + +/// @brief UULP GPIO pin/interrupt number +typedef enum { + UULP_GPIO_INTERRUPT_0 = 0, /// UULP GPIO 0 pin/interrupt number + UULP_GPIO_INTERRUPT_1 = 1, /// UULP GPIO 1 pin/interrupt number + UULP_GPIO_INTERRUPT_2 = 2, /// UULP GPIO 2 pin/interrupt number + UULP_GPIO_INTERRUPT_3 = 3, /// UULP GPIO 3 pin/interrupt number + UULP_GPIO_INTERRUPT_4 = 4, /// UULP GPIO 4 pin/interrupt number +} sl_si91x_uulp_gpio_interrupt_t; + +/// @brief UULP GPIO interrupt bit position +typedef enum { + UULP_GPIO_INTERRUPT_0_BIT = BIT(0), /// UULP GPIO 0 interrupt bit position + UULP_GPIO_INTERRUPT_1_BIT = BIT(1), /// UULP GPIO 1 interrupt bit position + UULP_GPIO_INTERRUPT_2_BIT = BIT(2), /// UULP GPIO 2 interrupt bit position + UULP_GPIO_INTERRUPT_3_BIT = BIT(3), /// UULP GPIO 3 interrupt bit position + UULP_GPIO_INTERRUPT_4_BIT = BIT(4), /// UULP GPIO 4 interrupt bit position +} sl_si91x_uulp_gpio_interrupt_bit_t; + +// ----------------------------------------------------------------------------- +// Prototypes +/***************************************************************************/ /** + * @brief Set the direction for a GPIO pin from the selected port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] direction - pin direction of type \ref sl_si91x_gpio_direction_t + * '0' - Output\n + * '1' - Input\n + * @return None +*******************************************************************************/ +void sl_si91x_gpio_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of a GPIO pin from selected port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection, for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_get_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return Returns the direction of the pin. + * '0' - Output\n + * '1' - Input\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_pin_direction(uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit in the PAD configuration register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @param[in] gpio_num - GPIO pin number to be use. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit in the PAD configuration register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @param[in] gpio_num - GPIO pin number to be use. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_disable_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Select the pad enable for HP instance of GPIO pins + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_padnum - PAD number to be use(0 to 21). + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_selection(uint8_t gpio_padnum); + +/***************************************************************************/ /** + * @brief Select the host pad enable for HP instance of GPIO pins + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_num - GPIO pin number(25 to 30). + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_host_pad_selection(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Select drive strength of a GPIO pin for selected port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] strength - Drive strength selector(E1,E2) of type + * \ref sl_si91x_gpio_driver_strength_select_t + * possible values are + * 0, for two_milli_amps (E1=0,E2=0)\n + * 1, for four_milli_amps (E1=0,E2=1)\n + * 2, for eight_milli_amps (E1=1,E2=0)\n + * 3, for twelve_milli_amps(E1=1,E2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the Driver disabled state control of a HP instance GPIO pin. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] disable_state - driver disable state of type + * \ref sl_si91x_gpio_driver_disable_state_t + * possible values are + * 0, for HiZ (P1=0,P2=0)\n + * 1, for Pull-up (P1=0,P2=1)\n + * 2, for Pull-down (P1=1,P2=0)\n + * 3, for Repeater (P1=1,P2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Select AND/OR of the group interrupt. If multiple interrupts + * on same port (or) different are to be generated, then use this API. + * Example: Consider port 0: pin 2,3 and port 3: pin 1,2 for interrupt generation. + * Choose OR, any of the selected pin is fine for group interrupt generation + * Choose AND, all the selected pins are necessary for group interrupt generation + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] and_or - AND/OR of GPIO group interrupts of type + * \ref sl_si91x_gpio_and_or_t + * '0' - AND\n + * '1' - OR\n + * @return None +*******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or); + +/***************************************************************************/ /** + * @brief Clear the selected group interrupt status for HP instance GPIO pins. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt() \n + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None +*******************************************************************************/ +void sl_si91x_gpio_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Get the group interrupt status of selected instance. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode(), + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns the group interrupt status register + * 1, when interrupt is enabled\n + * 0, when interrupt is disabled\n + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Configure the group interrupt as a wake up source across sleep wakeups. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] flags - GPIO group interrupt wake up flag of type + * \ref sl_si91x_gpio_wakeup_t + * '1' - enable\n + * '0' - disable\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_wakeup_t flags); + +/***************************************************************************/ /** + * @brief Configure the MCU HP instance group interrupts with trigger type(level/edge), polarity(high/low),interrupt type(and/or) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection() \n + * \ref sl_si91x_gpio_enable_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] configuration - configuration pointer to + * \ref sl_si91x_gpio_group_interrupt_config_t structure + * @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration); + +/***************************************************************************/ /** + * @brief Get the polarity of selected group interrupt of a HP instance GPIO. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return returns group interrupt polarity + * 1, when GPIO pin status is '1'\n + * 0, when GPIO pin status is '0'\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin); + +/***************************************************************************/ /** + * @brief Configure the polarity of selected group interrupt for HP instance GPIO . + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] polarity - polarity of GPIO group interrupt of type + * \ref sl_si91x_gpio_polarity_t + * 1, group interrupt gets generated when GPIO pin status is '1'\n + * 0, group interrupt gets generated when GPIO pin status is '0'\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Get the level/edge event status of selected group interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode(), \n + * \ref sl_si91x_gpio_set_pin_direction(), \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return returns group interrupt level_edge + * 1, for Edge\n + * 0, for Level\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Set the level/edge event of group interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] level_edge - GPIO level edge group interrupt of type + * \ref sl_si91x_gpio_level_edge_t + * 1, for Edge\n + * 0, for Level\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge); + +/***************************************************************************/ /** + * @brief Unmask the selected group interrupt to enable interrupt clearing upon generation. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None +*******************************************************************************/ +void sl_si91x_gpio_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected group interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None + *******************************************************************************/ +void sl_si91x_gpio_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** + * @brief Disable the clock for either HP or ULP instance of GPIO Peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * \ref sl_si91x_gpio_select_clock_t + * 0, for M4 GPIO CLK\n + * 1, for ULP GPIO CLK\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_disable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the clock for either HP or ULP instance of GPIO peripheral. + * @param[in] clock - Selects M4 clock or ULP clock of type + * \ref sl_si91x_gpio_select_clock_t + * 0, for M4 GPIO CLK\n + * 1, for ULP GPIO CLK\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_enable_clock(sl_si91x_gpio_select_clock_t clock); + +/***************************************************************************/ /** + * @brief Enable the selected group interrupts for either HP or ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Disable the selected group interrupts for either HP or ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_group_interrupt(), for HP instance \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt, for ULP instance \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - GPIO group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * + * @return None +*******************************************************************************/ +void sl_si91x_gpio_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the slew rate for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] slew_rate - slew rate of type \ref sl_si91x_gpio_slew_rate_t + * '0' - Slow\n + * '1' - Fast\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate); + +/***************************************************************************/ /** + * @brief Select the drive strength for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] strength - Drive strength selector(E1,E2) of type + * \ref sl_si91x_gpio_driver_strength_select_t + * 0, for two_milli_amps (E1=0,E2=0)\n + * 1, for four_milli_amps (E1=0,E2=1)\n + * 2, for eight_milli_amps (E1=1,E2=0)\n + * 3, for twelve_milli_amps(E1=1,E2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength); + +/***************************************************************************/ /** + * @brief Select the driver-disabled state control for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * @param[in] gpio_num - GPIO pin number to be use + * @param[in] disable_state - driver disable state of type + * \ref sl_si91x_gpio_driver_disable_state_t + * 0, for HiZ (P1=0,P2=0)\n + * 1, for Pull up (P1=0,P2=1)\n + * 2, for Pull down (P1=1,P2=0)\n + * 3, for Repeater (P1=1,P2=1)\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state); + +/***************************************************************************/ /** + * @brief Disable the receiver enable bit for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_num - GPIO pin number to be used + * @return None +*******************************************************************************/ +void sl_si91x_gpio_disable_ulp_pad_receiver(uint32_t gpio_num); + +/***************************************************************************/ /** + * @brief Enable the receiver enable bit for the ULP instance of GPIO peripheral. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] gpio_num - GPIO pin number to be used + * @return None +*******************************************************************************/ +void sl_si91x_gpio_enable_ulp_pad_receiver(uint8_t gpio_num); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance pin interrupts with trigger type(level/edge) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] interrupt_no - The interrupt number to trigger. + * @param[in] flags - Interrupt configuration flags of type + * \ref sl_si91x_gpio_interrupt_config_flag_t + * @param[in] pin - GPIO pin number + * @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_pin_interrupt(uint8_t interrupt_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO pin MUX(mode) to selected mode. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * @param[in] pin - NPSS GPIO pin number(0 to 4) of type + * \ref sl_si91x_uulp_npss_mode_t + * @param[in] mode - NPSS GPIO MUX value + * @return none +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode); + +/***************************************************************************/ /** + * @brief Enable/disable the NPSS GPIO Input Buffer. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @param[in] receiver - is enable/disable NPSS GPIO receiver of type + * \ref sl_si91x_gpio_receiver_t + * '1' - Enable\n + * '0' - Disable\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver); + +/***************************************************************************/ /** + * @brief Set the direction for the selected NPSS GPIO. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @param[in] direction - is direction value (Input / Output) of type + * \ref sl_si91x_gpio_direction_t + * '1' - Input Direction\n + * '0' - Output Direction\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction); + +/***************************************************************************/ /** + * @brief Get the direction of the selected NPSS GPIO. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] pin - is NPSS GPIO pin number(0...4) + * @return returns the GPIO pin direction + * - 1, Input Direction + * - 0, Output Direction +*******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_direction(uint8_t pin); + +/***************************************************************************/ /** + * @brief Control(set or clear) the NPSS GPIO pin value. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] pin - is NPSS GPIO pin number (0...4) of type + * \ref sl_si91x_gpio_pin_value_t + * @param[in] pin_value - is NPSS GPIO pin value + * '1' - SET \n + * '0' - CLEAR \n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value); + +/***************************************************************************/ /** + * @brief Read the status of selected NPSS GPIO pin value. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_value() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @return returns the pin logical state of pin + * '0' - LOW \n + * '1' - HIGH \n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Select the NPSS GPIO polarity for generating interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] pin - is NPSS GPIO pin number (0 to 4) + * @param[in] polarity - GPIO polarity + * \ref sl_si91x_gpio_polarity_t + * '1' - High\n + * '0' - Low\n + * @return None + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity); + +/***************************************************************************/ /** + * @brief Set the NPSS GPIO interrupt as a wake up source across sleep wakeups. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) + * \ref sl_si91x_uulp_gpio_interrupt_t + * @return none +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the UULP NPSS GPIO Interrupt as wake up source. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] npssgpio_interrupt - NPSS GPIO pin number (0 to 4) + * \ref sl_si91x_uulp_gpio_interrupt_t + * @return none +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Mask the selected NPSS GPIO interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] npssgpio_interrupt - Bit position of the NPSS GPIO interrupt to be masked + * \ref sl_si91x_uulp_gpio_interrupt_bit_t + * @return none +*******************************************************************************/ +void sl_si91x_gpio_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Unmask the selected NPSS GPIO interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] npssgpio_interrupt - Bit position of the NPSS GPIO interrupt to be unmasked + * \ref sl_si91x_uulp_gpio_interrupt_bit_t + * @return none +*******************************************************************************/ +void sl_si91x_gpio_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Clear the selected NPSS GPIO interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * \ref sl_si91x_gpio_configure_uulp_interrupt() \n + * @param[in] npssgpio_interrupt - Bit position of the NPSS GPIO interrupt to be cleared + * \ref sl_si91x_uulp_gpio_interrupt_bit_t + * @return none +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_interrupt(uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Get the current status of all the NPSS GPIO interrupt status. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_set_uulp_pad_configuration() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * \ref sl_si91x_gpio_configure_uulp_interrupt() \n + * @param[in] None + * @return returns the UULP INTR status. + * 1, interrupt has been raised\n + * 0, interrupt is masked or not raised\n + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_interrupt_status(void); + +/***************************************************************************/ /** + * @brief Get the selected ULP instance GPIO pin interrupt status. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_ulp_pin_interrupt() \n + * @param[in] flags : ULP GPIO interrupt sources. + * @return returns the ULP INTR status. + * 1, interrupt has been raised\n + * 0, interrupt is masked or not raised\n + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_ulp_interrupt_status(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_ulp_pin_interrupt() \n + * @param[in] flags : ULP GPIO interrupt sources to clear. + * @return None +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_interrupt(uint32_t flags); + +/***************************************************************************/ /** + * @brief Clear the selected ULP instance group interrupt. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * \ref sl_si91x_gpio_configure_ulp_group_interrupt() \n + * Use corresponding group interrupt configuration API for corresponding GPIO instance. + * @param[in] group_interrupt - Group interrupt number of type + * \ref sl_si91x_group_interrupt_t + * @return None +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt); + +/***************************************************************************/ /** +* @brief Configure the UULP GPIO pin interrupt with interrupt type level or edge and registers callback function for interrupts. +* @pre \ref sl_si91x_gpio_enable_clock() \n +* \ref sl_si91x_gpio_set_uulp_pad_configuration() \n +* \ref sl_si91x_gpio_select_uulp_npss_receiver() \n +* \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n +* \ref sl_si91x_gpio_set_uulp_npss_direction() \n +* @param[in] flags - Interrupt configuration flags of type +* \ref sl_si91x_gpio_interrupt_config_flag_t +* @param[in] npssgpio_interrupt - NPSS GPIO pin number(0 to 4) +* \ref sl_si91x_uulp_gpio_interrupt_t +* @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, uint8_t npssgpio_interrupt); + +/***************************************************************************/ /** + * @brief Configure the MCU ULP instance group interrupts with trigger type(level/edge), polarity(high/low),interrupt type(and/or) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_enable_ulp_pad_receiver() \n + * \ref sl_gpio_set_pin_mode() \n + * \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] configuration - configuration pointer to + * \ref sl_si91x_gpio_group_interrupt_config_t structure + * @return None +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration); + +/***************************************************************************/ /** + * @brief Verify assumptions and print message if the assumption is false. + * @param[in] file - File name + * @param[in] line - Line number + * @return None + ******************************************************************************/ +void sl_assert_failed(uint8_t *file, uint32_t line); + +/***************************************************************************/ /** + * Toggle the selected UULP pin status. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * \ref sl_si91x_gpio_select_uulp_npss_receiver() \n + * \ref sl_si91x_gpio_set_uulp_npss_pin_mux() \n + * \ref sl_si91x_gpio_set_uulp_npss_direction() \n + * @param[in] pin - UULP pin number to toggle + * @return None + ******************************************************************************/ +void sl_si91x_gpio_toggle_uulp_npss_pin(uint8_t pin); + +/***************************************************************************/ /** + * @brief Indicate UULP GPIO PAD configuration. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @param[in] pad_config : PAD configuration pointer to \ref uulp_pad_config_t structure + * @return None +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_pad_configuration(uulp_pad_config_t *pad_config); + +/***************************************************************************/ /** + * @brief Get the release, SQA, and development version numbers of the GPIO peripheral. + * @param[in] None + * @return returns structure of type \ref sl_si91x_gpio_version_t +*******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_get_version(void); + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< SL_SI91X_GPIO_PERIPHERAL_H +/**************************************************************************************************/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h new file mode 100644 index 000000000..61393eece --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_gpio_common.h @@ -0,0 +1,409 @@ +/****************************************************************************** +* @file sl_si91x_gpio_common.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#ifndef SL_SI91X_GPIO_COMMONH +#define SL_SI91X_GPIO_COMMONH + +#ifdef __cplusplus +extern "C" { +#endif + +//// Includes +/// +#include "si91x_device.h" +/***************************************************************************/ /** + * @addtogroup GPIO + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + * + ******************************************************************************/ +/******************************************************************************* + *************************** Defines / Macros ******************************** + ******************************************************************************/ +#define PAD_REG_BASE 0x46004000UL ///< PAD configuration register base address +#define NPSS_INT_BASE 0x12080000UL ///< UULP INTR base address +#define ULP_PAD_REG_BASE 0x2404A000UL ///< ULP PAD configuration base address + +#define GPIO ((EGPIO_Type *)EGPIO_BASE) ///< MCU HP base address +#define ULP_GPIO ((EGPIO_Type *)EGPIO1_BASE) ///< MCU ULP base address +#define UULP_GPIO_FSM ((MCU_FSM_Type *)MCU_FSM_BASE) ///< SLEEP FSM base address +#define UULP_GPIO ((MCU_RET_Type *)MCU_RET_BASE) ///< MCU retention base address + +#define PAD_REG(x) ((PAD_CONFIG_Type *)(PAD_REG_BASE + (4 * x))) ///< PAD configuration register for GPIO_n(n = 0 t0 63) +#define ULP_PAD_CONFIG0_REG ((ULP_PAD_CONFIG_Type0 *)(ULP_PAD_REG_BASE + 0x0)) ///< ULP PAD configuration register 0 +#define ULP_PAD_CONFIG1_REG ((ULP_PAD_CONFIG_Type1 *)(ULP_PAD_REG_BASE + 0x4)) ///< ULP PAD configuration register 1 +#define ULP_PAD_CONFIG2_REG ((ULP_PAD_CONFIG_Type2 *)(ULP_PAD_REG_BASE + 0x8)) ///< ULP PAD configuration register 2 + +#define UULP_PAD_CONFIG_REG(x) \ + ((UULP_PAD_CONFIG_Type *)(0x2404861C + 4 * x)) ///< UULP V_bat PAD configuration base address +#define PADSELECTION \ + (*(volatile uint32_t *)(0x41300000 + 0x610)) ///< PAD selection (0 to 21) A value of 1 on this gives control to M4SS +#define PADSELECTION_1 \ + (*(volatile uint32_t *)(0x41300000 + 0x618)) ///< PAD selection (22 to 33) A value of 1 on this gives control to M4SS +#define HOST_PADS_GPIO_MODE (*(volatile uint32_t *)(0x46008000 + 0x44)) ///< MISC host base address +#define ULP_PAD_CONFIG_REG (*(volatile uint32_t *)(0x2404A008)) ///< ULP PAD register + +#define GPIO_NPSS_INTERRUPT_MASK_SET_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x00)) ///< NPSS mask set register base address +#define GPIO_NPSS_INTERRUPT_MASK_CLR_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x04)) ///< NPSS mask clear register base address +#define GPIO_NPSS_INTERRUPT_CLEAR_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x08)) ///< NPSS clear register base address +#define GPIO_NPSS_INTERRUPT_STATUS_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x0C)) ///< NPSS status register base address +#define GPIO_NPSS_GPIO_CONFIG_REG \ + (*(volatile uint32_t *)(NPSS_INT_BASE + 0x10)) ///< NPSS GPIO configuration register base address +#define UULP_GPIO_STATUS (*(volatile uint32_t *)(NPSS_INT_BASE + 0x14)) ///< UULP GPIO status base address +#define GPIO_25_30_CONFIG_REG (*(volatile uint32_t *)(0X46008000 + 0x0C)) ///< GPIO(25-30) pin configuration register + +#define CLR 0 +#define SET 1 + +#define SL_DEBUG_ASSERT + +#define NIBBLE_SHIFT 4 ///< Nibble shift for interrupt +#define BYTE_SHIFT 8 ///< Byte shift for interrupt +#define WORD_SHIFT 16 ///< Word shift for interrupt +#define LSB_WORD_MASK 0x00FF ///< GPIO LSB word mask +#define LSB_NIBBLE_MASK 0x0F ///< GPIO LSB nibble mask + +#define MAX_GPIO_PORT_PIN 16 ///< GPIO maximum port pins +#define HOST_PAD 12 ///< GPIO Host PAD + +#define GPIO_PA_COUNT 16 ///< GPIO port A maximum pins +#define GPIO_PB_COUNT 16 ///< GPIO port B maximum pins +#define GPIO_PC_COUNT 16 ///< GPIO port C maximum pins +#define GPIO_PD_COUNT 9 ///< GPIO port D maximum pins +#define GPIO_PE_COUNT 12 ///< GPIO port E maximum pins + +#define GPIO_PA_MASK 0xFFFFUL ///< GPIO port A mask +#define GPIO_PB_MASK 0xFFFFUL ///< GPIO port B mask +#define GPIO_PC_MASK 0xFFFFUL ///< GPIO port C mask +#define GPIO_PD_MASK 0x01FFUL ///< GPIO port D mask + +#define SL_PERIPHERAL_CLK M4CLK ///< GPIO instance clock + +#define UNUSED_VAR(expr) ((void)(expr)) + +#define GPIO_PA_PIN_MAX_VALIDATE 75 ///< GPIO port A maximum pins to validate +#define GPIO_PB_PIN_MAX_VALIDATE 59 ///< GPIO port B maximum pins to validate +#define GPIO_PC_PIN_MAX_VALIDATE 43 ///< GPIO port C maximum pins to validate +#define GPIO_PD_PIN_MAX_VALIDATE 27 ///< GPIO port D maximum pins to validate + +#ifdef SL_DEBUG_ASSERT +#define SL_GPIO_ASSERT(expr) ((expr) ? (void)0U : sl_assert_failed((uint8_t *)__FILE__, __LINE__)) +#else +#define SL_GPIO_ASSERT(expr) ((void)(expr)) +#endif + +#define SL_GPIO_VALIDATE_STRENGTH(strength) (strength > 3 ? 0 : 1) ///< Validate driver strength +#define SL_GPIO_VALIDATE_PARAMETER(value) (value > 1 ? 0 : 1) ///< Validate GPIO parameters +#define SL_GPIO_VALIDATE_DISABLE_STATE(disable_state) (disable_state > 3 ? 0 : 1) ///< Validate driver disable state +#define SL_GPIO_VALIDATE_PAD(pad_num) ((pad_num > 34) && (pad_num < 1) ? 0 : 1) ///< Validate GPIO HP pad selection +#define SL_GPIO_VALIDATE_PIN(pin_num) ((pin_num > 63) ? 0 : 1) ///< Validate GPIO HP pin number +#define SL_GPIO_VALIDATE_FLAG(flag) ((flag > 0x0F) ? 0 : 1) ///< Validate GPIO flags +#define SL_GPIO_VALIDATE_ULP_INTR(ulp_intr) ((ulp_intr > 12) ? 0 : 1) ///< Validate ULP interrupts +#define SL_GPIO_VALIDATE_ULP_PIN(pin_num) ((pin_num > 12) ? 0 : 1) ///< Validate ULP pins +#define SL_GPIO_VALIDATE_UULP_PIN(pin_num) ((pin_num) > 5 ? 0 : 1) ///< Validate UULP pins +#define SL_GPIO_VALIDATE_MODE_PARAMETER(mode) ((mode) > 10 ? 0 : 1) ///< Validate UULP, ULP mode +#define SL_GPIO_VALIDATE_UULP_INTR(interrupt) ((interrupt) > 16 ? 0 : 1) ///< Validate UULP interrupt +#define SL_GPIO_VALIDATE_PORT(port) ((port) > 5 ? 0 : 1) ///< Validate GPIO port +#define SL_GPIO_VALIDATE_MODE(mode) ((mode) > 15 ? 0 : 1) ///< Validate GPIO mode +#define SL_GPIO_VALIDATE_INTR(interrupt) ((interrupt > 8) ? 0 : 1) ///< Validate GPIO interrupt +///< Validate GPIO port and pin +#define SL_GPIO_NDEBUG_PORT_PIN(port, pin) \ + (port == 0 ? ((pin > GPIO_PA_PIN_MAX_VALIDATE) ? 0 : 1) \ + : port == 1 ? ((pin > GPIO_PB_PIN_MAX_VALIDATE) ? 0 : 1) \ + : port == 2 ? ((pin > GPIO_PC_PIN_MAX_VALIDATE) ? 0 : 1) \ + : port == 3 ? ((pin > GPIO_PD_PIN_MAX_VALIDATE) ? 0 : 1) \ + : 0) +///< Validate GPIO host pad port and pin +#define SL_GPIO_VALIDATE_HOST_PIN(port, pin) \ + (port == SL_GPIO_PORT_A ? (((pin >= HOST_PAD_MIN) && (pin <= HOST_PAD_MAX)) ? TRUE : FALSE) \ + : port == SL_GPIO_PORT_B ? (((pin >= GPIO_PIN_NUMBER9) && (pin <= GPIO_PIN_NUMBER14)) ? TRUE : FALSE) \ + : FALSE) +#define SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin) (port == 4 ? ((pin > 11) ? 0 : 1) : 0) ///< Validate ULP port and pin +#define SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin) (port == 5 ? ((pin > 5) ? 0 : 1) : 0) ///< Validate UULP port and pin + +#define GRP_IRQ0_Handler IRQ050_Handler ///< GPIO Group Interrupt 0 +#define GRP_IRQ1_Handler IRQ051_Handler ///< GPIO Group Interrupt 1 + +#define PIN_IRQ0_Handler IRQ052_Handler ///< GPIO Pin Interrupt 0 +#define PIN_IRQ1_Handler IRQ053_Handler ///< GPIO Pin Interrupt 1 +#define PIN_IRQ2_Handler IRQ054_Handler ///< GPIO Pin Interrupt 2 +#define PIN_IRQ3_Handler IRQ055_Handler ///< GPIO Pin Interrupt 3 +#define PIN_IRQ4_Handler IRQ056_Handler ///< GPIO Pin Interrupt 4 +#define PIN_IRQ5_Handler IRQ057_Handler ///< GPIO Pin Interrupt 5 +#define PIN_IRQ6_Handler IRQ058_Handler ///< GPIO Pin Interrupt 6 +#define PIN_IRQ7_Handler IRQ059_Handler ///< GPIO Pin Interrupt 7 + +#define UULP_PIN_IRQ_Handler IRQ021_Handler ///< UULP Pin Interrupt 0 + +#define ULP_PIN_IRQ_Handler IRQ018_Handler ///< ULP Pin Interrupt +#define ULP_GROUP_IRQ_Handler IRQ019_Handler ///< ULP Group Interrupt + +#define PIN_INTR_0 0 ///< HP GPIO pin interrupt 0 +#define PIN_INTR_1 1 ///< HP GPIO pin interrupt 1 +#define PIN_INTR_2 2 ///< HP GPIO pin interrupt 2 +#define PIN_INTR_3 3 ///< HP GPIO pin interrupt 3 +#define PIN_INTR_4 4 ///< HP GPIO pin interrupt 4 +#define PIN_INTR_5 5 ///< HP GPIO pin interrupt 5 +#define PIN_INTR_6 6 ///< HP GPIO pin interrupt 6 +#define PIN_INTR_7 7 ///< HP GPIO pin interrupt 7 + +#define UULP_MASK 0x00 ///< UULP GPIO pin mask +#define ULP_STATUS 0x01 ///< ULP GPIO pin status +#define UULP_INTR_1 0x01 ///< UULP GPIO pin interrupt 1 +#define UULP_INTR_2 0x02 ///< UULP GPIO pin interrupt 2 +#define UULP_INTR_3 0x04 ///< UULP GPIO pin interrupt 3 +#define UULP_INTR_4 0x08 ///< UULP GPIO pin interrupt 4 +#define UULP_INTR_5 0x10 ///< UULP GPIO pin interrupt 5 + +#define ULP_PIN_INTR_0 0 ///< ULP GPIO pin interrupt 0 +#define ULP_PIN_INTR_1 1 ///< ULP GPIO pin interrupt 1 +#define ULP_PIN_INTR_2 2 ///< ULP GPIO pin interrupt 2 +#define ULP_PIN_INTR_3 3 ///< ULP GPIO pin interrupt 3 +#define ULP_PIN_INTR_4 4 ///< ULP GPIO pin interrupt 4 +#define ULP_PIN_INTR_5 5 ///< ULP GPIO pin interrupt 5 +#define ULP_PIN_INTR_6 6 ///< ULP GPIO pin interrupt 6 +#define ULP_PIN_INTR_7 7 ///< ULP GPIO pin interrupt 7 + +#define ULP_GROUP_INTR_0 0 ///< ULP GPIO group interrupt 0 +#define ULP_GROUP_INTR_1 1 ///< ULP GPIO group interrupt 1 + +#define MAX_GPIO_PIN_INT 8 ///< Maximum HP GPIO pin interrupts + +#define PININT0_NVIC_NAME EGPIO_PIN_0_IRQn ///< HP GPIO pin interrupt 0 number +#define PININT1_NVIC_NAME EGPIO_PIN_1_IRQn ///< HP GPIO pin interrupt 1 number +#define PININT2_NVIC_NAME EGPIO_PIN_2_IRQn ///< HP GPIO pin interrupt 2 number +#define PININT3_NVIC_NAME EGPIO_PIN_3_IRQn ///< HP GPIO pin interrupt 3 number +#define PININT4_NVIC_NAME EGPIO_PIN_4_IRQn ///< HP GPIO pin interrupt 4 number +#define PININT5_NVIC_NAME EGPIO_PIN_5_IRQn ///< HP GPIO pin interrupt 5 number +#define PININT6_NVIC_NAME EGPIO_PIN_6_IRQn ///< HP GPIO pin interrupt 6 number +#define PININT7_NVIC_NAME EGPIO_PIN_7_IRQn ///< HP GPIO pin interrupt 7 number + +#define GROUP_0_INTERRUPT_NAME EGPIO_GROUP_0_IRQn ///< HP GPIO group interrupt 1 number +#define GROUP_1_INTERRUPT_NAME EGPIO_GROUP_1_IRQn ///< HP GPIO group interrupt 2 number + +#define ULP_PININT0_NVIC_NAME ULP_EGPIO_PIN_IRQn ///< ULP GPIO pin interrupt number +#define ULP_GROUP_INTERRUPT_NAME ULP_EGPIO_GROUP_IRQn ///< ULP GPIO group interrupt number + +#define UULP_PININT_NVIC_NAME NPSS_TO_MCU_GPIO_INTR_IRQn ///< UULP GPIO pin interrupt number + +#define SL_GPIO_GROUP_INTERRUPT_OR 1 ///< GPIO group interrupt AND/OR +#define SL_GPIO_GROUP_INTERRUPT_WAKEUP 4 ///< GPIO group interrupt wakeup +#define SL_GPIO_ULP_PORT 4 ///< ULP GPIO port number +#define SL_GPIO_UULP_PORT 5 ///< Initializing UULP GPIO port value +#define SL_ULP_GPIO_PORT 4 ///< Refers to ULP Port + +#define _MODE0 0 ///< GPIO mode 0 +#define _MODE1 1 ///< GPIO mode 1 +#define _MODE2 2 ///< GPIO mode 2 +#define _MODE3 3 ///< GPIO mode 3 +#define _MODE4 4 ///< GPIO mode 4 +#define _MODE5 5 ///< GPIO mode 5 +#define _MODE6 6 ///< GPIO mode 6 +#define _MODE7 7 ///< GPIO mode 7 +#define _MODE8 8 ///< GPIO mode 8 +#define _MODE9 9 ///< GPIO mode 9 +#define _MODE10 10 ///< GPIO mode 10 +#define _MODE14 14 ///< GPIO mode 14 + +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL ///< Mode DISABLED for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL ///< Mode INPUT for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL ///< Mode INPUTPULL for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL ///< Mode INPUTPULLFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL ///< Mode PUSHPULL for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL ///< Mode PUSHPULLALT for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL ///< Mode WIREDOR for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL ///< Mode WIREDORPULLDOWN for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL ///< Mode WIREDAND for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL ///< Mode WIREDANDFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL ///< Mode WIREDANDPULLUP for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL ///< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL ///< Mode WIREDANDALT for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL ///< Mode WIREDANDALTFILTER for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL ///< Mode WIREDANDALTPULLUP for GPIO_P_MODEL +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL ///< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL + +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) ///< Shifted mode DISABLED for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) ///< Shifted mode INPUT for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) ///< Shifted mode INPUTPULL for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER \ + (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) ///< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) ///< Shifted mode PUSHPULL for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_PUSHPULLALT \ + (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) ///< Shifted mode PUSHPULLALT for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) ///< Shifted mode WIREDOR for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN \ + (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) ///< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) ///< Shifted mode WIREDAND for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) ///< Shifted mode WIREDANDFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP \ + (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) ///< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) ///< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALT \ + (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) ///< Shifted mode WIREDANDALT for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) ///< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP \ + (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) ///< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER \ + (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) ///< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL + +#define GPIO_PAD_0 0 ///< GPIO PAD number 0 +#define GPIO_PAD_3 3 ///< GPIO PAD number 3 +#define GPIO_PAD_4 4 ///< GPIO PAD number 4 +#define GPIO_PAD_7 7 ///< GPIO PAD number 7 +#define GPIO_PAD_8 8 ///< GPIO PAD number 8 + +#define HOST_PAD_SELECT 12 ///< GPIO Host PAD selection +#define PAD_SELECT 22 ///< GPIO PAD number 22 +#define HOST_PAD_MIN 25 ///< GPIO Host PAD number 25 +#define HOST_PAD_MAX 30 ///< GPIO Host PAD number 30 + +#define PRIORITY_19 19 ///< GPIO ulp group Interrupt priority +#define PRIORITY_21 21 ///< GPIO uulp group Interrupt priority +#define PRIORITY_50 50 ///< GPIO m4 group 0 Interrupt priority +#define PRIORITY_51 51 ///< GPIO m4 group 1 Interrupt priority + +#define ULP_PORT_NUM 0 ///< GPIO ULP port number +#define UULP_PIN_MASK 0x1F ///< GPIO UULP pin mask + +#define BIT_0 0 ///< GPIO bit 0 in configuration register +#define BIT_8 8 ///< GPIO bit 8 in configuration register +#define BIT_16 16 ///< GPIO bit 16 in configuration register +#define BIT_24 24 ///< GPIO bit 24 in configuration register + +#define PORT_MASK 0xFFFF ///< GPIO port mask +#define INTR_CLR 0x07 ///< GPIO interrupt clear +#define INTERRUPT_MASK 0x0F ///< GPIO interrupt mask +#define MASK_CTRL 0x03 +#define MASK_INTR 0x01 ///< GPIO interrupt mask + +/** =========================================================================================================================== **/ +/** ================ GPIO ==================**/ +/** =========================================================================================================================== **/ +///@brief HP GPIO PAD configuration register fields +typedef struct { + union { + __IOM uint32_t PAD_CONFIG_REG; ///< (@ 0x46004000) GPIO PAD configuration register + + struct { + __IOM uint32_t PADCONFIG_E1_E2 : 2; ///< [1..0] Drive strength selector + __IOM uint32_t PADCONFIG_POS : 1; ///< [2..2] Power-on-Start enable + __IOM uint32_t PADCONFIG_SMT : 1; ///< [3..3] Active high Schmitt trigger (Hysteresis) select + __IOM uint32_t PADCONFIG_REN : 1; ///< [4..4] Active high receiver enable + __IOM uint32_t PADCONFIG_SR : 1; ///< [5..5] Slew Rate Control + __IOM uint32_t PADCONFIG_P1_P2 : 2; ///< [7..6] Driver disabled state control + __IOM uint32_t RESERVED1 : 24; ///< [31..8] Reserved1 + } GPIO_PAD_CONFIG_REG_b; + }; +} PAD_CONFIG_Type; + +///@brief UULP GPIO PAD configuration register fields +typedef struct { + union { + __IOM uint32_t UULP_PAD_CONFIG_REG; ///< (@ 0x2404861C) UULP VBAT GPIO configuration register + + struct { + __IOM uint32_t GPIO_MODE : 3; ///< [2..0] GPIO Mode for UULP_VBAT_GPIO_n(n=0:4) + __IOM uint32_t GPIO_REN : 1; ///< [3..3] Receiver of PAD enable + __IOM uint32_t GPIO_OEN : 1; ///< [4..4] Direction of PAD + __IOM uint32_t GPIO_OUTPUT : 1; ///< [5..5] Value driven on PAD in OUTPUT mode + __IOM uint32_t GPIO_PAD_SELECT : 1; ///< [6..6] PAD selection between M4,NWP + __IOM uint32_t RESERVED : 1; ///< [7..7] Reserved + __IOM uint32_t GPIO_POLARITY : 1; ///< [8..8] Polarity of UULP GPIO + __IOM uint32_t RESERVED1 : 23; ///< [31..9] Reserved1 + } UULP_GPIO_PAD_CONFIG_REG_b; + }; +} UULP_PAD_CONFIG_Type; + +///@brief ULP GPIO PAD configuration register0 fields +typedef struct { + union { + __IOM uint32_t ULP_PAD_CONFIG_REG0; + + struct { + __IOM uint32_t PADCONFIG_E1_E2_1 : 2; ///< [1..0] Drive strength selector for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_POS_1 : 1; ///< [2..2] Power on start enable for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_SMT_1 : 1; ///< [3..3] Active high schmitt trigger for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t RESERVED : 1; ///< [4..4] Reserved + __IOM uint32_t PADCONFIG_SR_1 : 1; ///< [5..5] Slew rate control for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_P1_P2_1 : 2; ///< [7..6] Driver disabled state control for ULP_GPIO_0 - ULP_GPIO_3 + __IOM uint32_t PADCONFIG_E1_E2_2 : 2; ///< [9..8] Drive strength selector for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t PADCONFIG_POS_2 : 1; ///< [10..10] Power on start enable for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t PADCONFIG_SMT_2 : 1; ///< [11..11] Active high schmitt trigger for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t RESERVED1 : 1; ///< [12..12] Reserved1 + __IOM uint32_t PADCONFIG_SR_2 : 1; ///< [13..13] Slew rate control for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t PADCONFIG_P1_P2_2 : 2; ///< [15..14] Driver disabled state control for ULP_GPIO_4 - ULP_GPIO_7 + __IOM uint32_t RESERVED2 : 16; ///< [31..16] Reserved2 + } ULP_GPIO_PAD_CONFIG_REG_0; + }; +} ULP_PAD_CONFIG_Type0; + +///@brief ULP GPIO PAD configuration register1 fields +typedef struct { + union { + __IOM uint32_t ULP_PAD_CONFIG_REG1; + + struct { + __IOM uint32_t PADCONFIG_E1_E2_1 : 2; ///< [1..0] Drive strength selector for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t PADCONFIG_POS_1 : 1; ///< [2..2] Power on start enable for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t PADCONFIG_SMT_1 : 1; ///< [3..3] Active high schmitt trigger for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t RESERVED : 1; ///< [4..4] Reserved + __IOM uint32_t PADCONFIG_SR_1 : 1; ///< [5..5] Slew rate control for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t PADCONFIG_P1_P2_1 : 2; ///< [7..6] Driver disabled state control for ULP_GPIO_8 - ULP_GPIO_11 + __IOM uint32_t RESERVED1 : 8; ///< [15..8] Reserved1 + __IOM uint32_t RESERVED2 : 16; ///< [31..16] Reserved2 + } ULP_GPIO_PAD_CONFIG_REG_1; + }; +} ULP_PAD_CONFIG_Type1; + +///@brief ULP GPIO PAD configuration register2 fields +typedef struct { + union { + __IOM uint32_t ULP_PAD_CONFIG_REG2; + + struct { + __IOM uint32_t PADCONFIG_REN : 12; ///< [11..0] Active high receiver enable for ULP_GPIO_11 - ULP_GPIO_0 + __IOM uint32_t RESERVED : 20; ///< [31..12] Reserved + } ULP_GPIO_PAD_CONFIG_REG_2; + }; +} ULP_PAD_CONFIG_Type2; + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< SL_SI91X_GPIO_COMMONH + /**************************************************************************************************/ diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h new file mode 100644 index 000000000..8e9499a1a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc/sl_si91x_peripheral_gpio.h @@ -0,0 +1,812 @@ +/****************************************************************************** +* @file sl_si91x_peripheral_gpio.h +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#ifndef SL_PERIPHERAL_GPIO_H +#define SL_PERIPHERAL_GPIO_H + +#if !defined(GPIO_PRESENT) +#include "sl_si91x_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************/ /** + * @addtogroup GPIO-PERIPHERAL-DRIVER GPIO Peripheral Driver + * @ingroup SI91X_PERIPHERAL_APIS + * @{ + * + ******************************************************************************/ +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +#define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT ///< GPIO port A maximum pins +#define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT ///< GPIO port B maximum pins +#define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT ///< GPIO port C maximum pins +#define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT ///< GPIO port D maximum pins +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 0 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) ///< GPIO port A pin mask +#define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) ///< GPIO port B pin mask +#define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) ///< GPIO port C pin mask +#define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) ///< GPIO port D pin mask +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x0000UL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +///< GPIO pins selection for selected port +#define _GPIO_PORT_SIZE(port) \ + ((port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ + : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ + : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ + : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ + : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ + : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ + : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ + : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ + : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ + : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ + : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ + : 0) + +///< GPIO pins mask for selected port +#define _GPIO_PORT_MASK(port) \ + (((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \ + : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \ + : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \ + : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \ + : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \ + : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \ + : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \ + : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \ + : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \ + : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \ + : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \ + : 0UL) + +#define SL_GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) ///< Validation of GPIO port. + +#define SL_GPIO_PORT_PIN_VALID(port, pin) \ + ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) ///< Validating GPIO port and pin + +#define GPIO_PIN_MAX 15 ///< Highest GPIO pin number. + +///@brief Highest GPIO port number. +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define GPIO_PORT_MAX 10 +#elif (_GPIO_PORT_J_PIN_COUNT > 0) +#define GPIO_PORT_MAX 9 +#elif (_GPIO_PORT_I_PIN_COUNT > 0) +#define GPIO_PORT_MAX 8 +#elif (_GPIO_PORT_H_PIN_COUNT > 0) +#define GPIO_PORT_MAX 7 +#elif (_GPIO_PORT_G_PIN_COUNT > 0) +#define GPIO_PORT_MAX 6 +#elif (_GPIO_PORT_F_PIN_COUNT > 0) +#define GPIO_PORT_MAX 5 +#elif (_GPIO_PORT_E_PIN_COUNT > 0) +#define GPIO_PORT_MAX 4 +#elif (_GPIO_PORT_D_PIN_COUNT > 0) +#define GPIO_PORT_MAX 3 +#else +#error "Max GPIO port number is undefined for this part." +#endif + +#define GPIO_EXTINTNO_MAX 15 ///< Highest EXT GPIO interrupt number. + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +///@brief GPIO ports IDs. +typedef enum { +#if (_GPIO_PORT_A_PIN_COUNT > 0) + SL_GPIO_PORT_A = 0, ///< GPIO Port A +#endif +#if (_GPIO_PORT_B_PIN_COUNT > 0) + SL_GPIO_PORT_B = 1, ///< GPIO Port B +#endif +#if (_GPIO_PORT_C_PIN_COUNT > 0) + SL_GPIO_PORT_C = 2, ///< GPIO Port C +#endif +#if (_GPIO_PORT_D_PIN_COUNT > 0) + SL_GPIO_PORT_D = 3, ///< GPIO Port D +#endif +#if (_GPIO_PORT_E_PIN_COUNT > 0) + SL_GPIO_PORT_E = 4, +#endif +#if (_GPIO_PORT_F_PIN_COUNT > 0) + SL_GPIO_PORT_F = 5, +#endif +#if (_GPIO_PORT_G_PIN_COUNT > 0) + SL_GPIO_PORT_G = 6, +#endif +#if (_GPIO_PORT_H_PIN_COUNT > 0) + SL_GPIO_PORT_H = 7, +#endif +#if (_GPIO_PORT_I_PIN_COUNT > 0) + SL_GPIO_PORT_I = 8, +#endif +#if (_GPIO_PORT_J_PIN_COUNT > 0) + SL_GPIO_PORT_J = 9, +#endif +#if (_GPIO_PORT_K_PIN_COUNT > 0) + SL_GPIO_PORT_K = 10, +#endif +} sl_gpio_port_t; + +///@brief GPIO Pin Modes. +typedef enum { + SL_GPIO_MODE_0 = _MODE0, ///< Pin MUX GPIO Mode 0. + SL_GPIO_MODE_1 = _MODE1, ///< Pin MUX GPIO Mode 1. + SL_GPIO_MODE_2 = _MODE2, ///< Pin MUX GPIO Mode 2. + SL_GPIO_MODE_3 = _MODE3, ///< Pin MUX GPIO Mode 3. + SL_GPIO_MODE_4 = _MODE4, ///< Pin MUX GPIO Mode 4. + SL_GPIO_MODE_5 = _MODE5, ///< Pin MUX GPIO Mode 5. + SL_GPIO_MODE_6 = _MODE6, ///< Pin MUX GPIO Mode 6. + SL_GPIO_MODE_7 = _MODE7, ///< Pin MUX GPIO Mode 7. + SL_GPIO_MODE_8 = _MODE8, ///< Pin MUX GPIO Mode 8. + SL_GPIO_MODE_9 = _MODE9, ///< Pin MUX GPIO Mode 9. + SL_GPIO_MODE_10 = _MODE10, ///< Pin MUX GPIO Mode 10. + SL_GPIO_MODE_14 = _MODE14, ///< Pin MUX GPIO Mode 14. + SL_GPIO_MODE_DISABLED = _GPIO_P_MODEL_MODE0_DISABLED, ///< Input disabled. Pull-up if DOUT is set. + SL_GPIO_MODE_INPUT = _GPIO_P_MODEL_MODE0_INPUT, ///< Input enabled. Filter if DOUT is set. + SL_GPIO_MODE_INPUT_PULL = _GPIO_P_MODEL_MODE0_INPUTPULL, ///< Input enabled. DOUT determines pull direction. + SL_GPIO_MODE_INPUT_PULL_FILTER = + _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, ///< Input enabled with filter. DOUT determines pull direction. + SL_GPIO_MODE_PUSH_PULL = _GPIO_P_MODEL_MODE0_PUSHPULL, ///< Push-pull output. + SL_GPIO_MODE_PUSH_PULL_ALTERNATE = _GPIO_P_MODEL_MODE0_PUSHPULLALT, ///< Push-pull using alternate control. + SL_GPIO_MODE_WIRED_OR = _GPIO_P_MODEL_MODE0_WIREDOR, ///< Wired-or output. + SL_GPIO_MODE_WIRED_OR_PULL_DOWN = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, ///< Wired-or output with pull-down. + SL_GPIO_MODE_WIRED_AND = _GPIO_P_MODEL_MODE0_WIREDAND, ///< Open-drain output. + SL_GPIO_MODE_WIRED_AND_FILTER = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, ///< Open-drain output with filter. + SL_GPIO_MODE_WIRED_AND_PULLUP = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, ///< Open-drain output with pull-up. + SL_GPIO_MODE_WIRED_AND_PULLUP_FILTER = + _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, ///< Open-drain output with filter and pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE = _GPIO_P_MODEL_MODE0_WIREDANDALT, ///< Open-drain output using alternate control. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_FILTER = + _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, ///< Open-drain output using alternate control with filter. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP = + _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, ///< Open-drain output using alternate control with pull-up. + SL_GPIO_MODE_WIRED_AND_ALTERNATE_PULLUP_FILTER = + _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, ///< Open-drain output using alternate control with filter and pull-up. +} sl_gpio_mode_t; + +///@brief GPIO Interrupt Configurations. +typedef enum { + SL_GPIO_INTERRUPT_DISABLE = 0, ///< disable the interrupt + SL_GPIO_INTERRUPT_ENABLE = (1 << 0), ///< enable the interrupt + SL_GPIO_INTERRUPT_HIGH = (1 << 0), ///< interrupt when pin level is '1' + SL_GPIO_INTERRUPT_LOW = (1 << 1), ///< interrupt when pin level is '0' + SL_GPIO_INTERRUPT_RISING_EDGE = (1 << 2), ///< interrupt when rising edge is detected + SL_GPIO_INTERRUPT_FALLING_EDGE = (1 << 3), ///< interrupt when falling edge is detected + SL_GPIO_INTERRUPT_RISE_FALL_EDGE = + (SL_GPIO_INTERRUPT_FALLING_EDGE + | SL_GPIO_INTERRUPT_RISING_EDGE), ///< interrupt when rising and falling edge is detected +} sl_gpio_interrupt_flag_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************/ /** + * @brief Configure the MCU HP instance pin interrupts with trigger type(level/edge) + * and register the callback function for interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] int_no - The interrupt number to trigger. + * @param[in] flags - Interrupt configuration flags + * @return None + ******************************************************************************/ +void sl_gpio_configure_interrupt(sl_gpio_port_t port, uint8_t pin, uint32_t int_no, sl_gpio_interrupt_flag_t flags); + +/***************************************************************************/ /** + * @brief Set the pin mode (alternate function) of a GPIO for either HP instance (or) ULP instance as per the port number. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @param[in] mode - The desired pin mode. + * @param[in] output_value - A value to set for the pin in the GPIO register. + * The GPIO setting is important for some input mode configurations. + * @return None + ******************************************************************************/ +void sl_gpio_set_pin_mode(sl_gpio_port_t port, uint8_t pin, sl_gpio_mode_t mode, uint32_t output_value); + +/***************************************************************************/ /** + * @brief Get the pin mode (alternate function) of a GPIO for either HP instance or ULP instance as per the port number. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. + * @pre \ref sl_gpio_set_pin_mode(); + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return returns Pin status + * '0' - Output + * '1' - Input + ******************************************************************************/ +sl_gpio_mode_t sl_gpio_get_pin_mode(sl_gpio_port_t port, uint8_t pin); + +/***************************************************************************/ /** + * @brief Set a single GPIO pin of a GPIO port with 1. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG = SET; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = SET; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Set pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = SET; + } +} + +/***************************************************************************/ /** + * @brief Set the selected bits value of GPIO data out register to 1. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pins - The GPIO pins in a port are set to 1's. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_port_output(sl_gpio_port_t port, uint32_t pins) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (pins); + } else { + GPIO->PORT_CONFIG[port].PORT_SET_REG = (pins); + } +} + +/***************************************************************************/ /** + * @brief Set GPIO port value with the selected mask bits. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] val - Value to write to port configuration register. + * @param[in] mask - Mask indicating which bits to modify. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_port_output_value(sl_gpio_port_t port, uint32_t val, uint32_t mask) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_SET_REG = (ULP_GPIO->PORT_CONFIG[port].PORT_SET_REG & ~mask) + | (val & mask); + } else { + GPIO->PORT_CONFIG[port].PORT_SET_REG = (GPIO->PORT_CONFIG[port].PORT_SET_REG & ~mask) | (val & mask); + } +} + +/***************************************************************************/ /** + * @brief Set slewrate for pins on a GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @param[in] port - The GPIO port to configure. + * @param[in] slewrate - The slewrate to configure for pins on this GPIO port. + * @param[in] slewrate_alt - The slewrate to configure for pins using alternate modes on this GPIO port. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_set_slew_rate(sl_gpio_port_t port, uint32_t slewrate, uint32_t slewrate_alt) +{ + UNUSED_VAR(slewrate_alt); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + for (uint8_t i = (port * MAX_GPIO_PORT_PIN); i < (MAX_GPIO_PORT_PIN * (port + 1)); i++) { + PAD_REG(i)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_SR = (sl_si91x_gpio_slew_rate_t)slewrate; + } +} + +/***************************************************************************/ /** + * @brief Clear a single pin in GPIO configuration register to 0. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(); for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode(); \n + * @pre \ref sl_si91x_gpio_set_pin_direction(); \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin to set. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_clear_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG = CLR; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG = CLR; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Set pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = CLR; + } +} + +/***************************************************************************/ /** + * @brief Clear bits in configuration register for a port to 0. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pins - The GPIO pins in a port to clear. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_clear_port_output(sl_gpio_port_t port, uint32_t pins) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_CLEAR_REG = (pins); + } else { + GPIO->PORT_CONFIG[port].PORT_CLEAR_REG = (pins); + } +} + +/***************************************************************************/ /** + * @brief Read the pin value for a single pin in a GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return The GPIO pin value + * '0' - Output\n + * '1' - Input\n + ******************************************************************************/ +static __INLINE uint8_t sl_gpio_get_pin_input(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + return (uint8_t)GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Read pin status in UULP GPIO instance + return (UULP_GPIO_STATUS >> pin) & MASK_INTR; + } +} + +/***************************************************************************/ /** + * @brief Get the current pin value of selected pin in a GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin to get setting for. + * @return The GPIO pin value + * '0' - Output\n + * '1' - Input\n + ******************************************************************************/ +static __INLINE uint8_t sl_gpio_get_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + return (uint8_t)ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + return (uint8_t)GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG; + } +} + +/***************************************************************************/ /** + * @brief Read the port value for GPIO port. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @return The pin values of the GPIO port. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_port_input(sl_gpio_port_t port) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + return ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK; + } else { + return GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK; + } +} + +/***************************************************************************/ /** + * @brief Get the current pin values of a selected GPIO Port register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @return The port value for the requested port. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_port_output(sl_gpio_port_t port) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + return (ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_READ_REG & PORT_MASK); + } else { + return (GPIO->PORT_CONFIG[port].PORT_READ_REG & PORT_MASK); + } +} + +/***************************************************************************/ /** + * @brief Toggle a single pin in selected GPIO port register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pin - The pin number on the port. + * HP instance has total 57 GPIO pins. Port 0, 1, 2 has 16 pins each. + * Port 3 has 9 pins. + * ULP instance has total 12 pins. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_toggle_pin_output(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].BIT_LOAD_REG ^= SET; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->PIN_CONFIG[pin].BIT_LOAD_REG ^= SET; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PORT_PIN(port, pin)); + // Set or Clear pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT ^= SET; + } +} + +/***************************************************************************/ /** + * @brief Toggle selected pins in GPIO port register. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_ulp_pad_receiver(), for ULP instance \n + * Use corresponding pad receiver API for corresponding GPIO instance. \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] port - The port to associate with the pin. + * HP instance - PORT 0,1,2,3 + * ULP instance - PORT 4 + * @param[in] pins - Port pins to toggle. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_toggle_port_output(sl_gpio_port_t port, uint32_t pins) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + ULP_GPIO->PORT_CONFIG[SL_GPIO_PORT_A].PORT_TOGGLE_REG = pins; + } else { + GPIO->PORT_CONFIG[port].PORT_TOGGLE_REG = pins; + } +} + +/***************************************************************************/ /** + * @brief Enable MCU HP instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - GPIO interrupt sources to enable. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_enable_interrupts(uint32_t flags) +{ + uint16_t intch, int_flag; + intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK); + int_flag = (uint16_t)(flags & INTERRUPT_MASK); + if ((int_flag & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SET; + } + if ((int_flag & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SET; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SET; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SET; + } +} + +/***************************************************************************/ /** + * @brief Disable MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - GPIO interrupt sources to disable. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_disable_interrupts(uint32_t flags) +{ + uint16_t intch, int_flag; + intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK); + int_flag = (uint16_t)(flags & LSB_NIBBLE_MASK); + if ((int_flag & SL_GPIO_INTERRUPT_RISE_EDGE) == SL_GPIO_INTERRUPT_RISE_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = CLR; + } + if ((int_flag & SL_GPIO_INTERRUPT_FALL_EDGE) == SL_GPIO_INTERRUPT_FALL_EDGE) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = CLR; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_HIGH) == SL_GPIO_INTERRUPT_LEVEL_HIGH) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = CLR; + } + if ((int_flag & SL_GPIO_INTERRUPT_LEVEL_LOW) == SL_GPIO_INTERRUPT_LEVEL_LOW) { + GPIO->INTR[intch].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = CLR; + } +} + +/***************************************************************************/ /** + * @brief Clear MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - Bitwise logic OR of GPIO interrupt sources to clear. + * @return None + ******************************************************************************/ +static __INLINE void sl_gpio_clear_interrupts(uint32_t flags) +{ + uint32_t reg_data = GPIO->INTR[flags].GPIO_INTR_STATUS; + if (reg_data != 0) + GPIO->INTR[flags].GPIO_INTR_STATUS = INTR_CLR; +} + +/**************************************************************************/ /** + * @brief Set MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] flags - GPIO interrupt sources to set to pending. + * @return None + *****************************************************************************/ +static __INLINE void sl_gpio_set_interrupts(uint32_t flags) +{ + uint16_t intch, int_flag; + intch = (uint16_t)((flags >> WORD_SHIFT) & LSB_WORD_MASK); + int_flag = (uint16_t)(flags & INTERRUPT_MASK); + GPIO->INTR[intch].GPIO_INTR_CTRL = (GPIO->INTR[intch].GPIO_INTR_CTRL | int_flag); +} + +/***************************************************************************/ /** + * @brief Get pending MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] None + * @return GPIO interrupt sources pending. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_pending_interrupts(void) +{ + uint32_t intflags = 0, tmp = 0; + for (uint8_t intch = 0; intch < MAX_GPIO_PIN_INT; intch++) { + tmp = (GPIO->INTR[intch].GPIO_INTR_STATUS & LSB_NIBBLE_MASK); + intflags |= (tmp << (NIBBLE_SHIFT * intch)); + } + return intflags; +} + +/***************************************************************************/ /** + * @brief Get enabled MCU HP Instance GPIO pin interrupts. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] None + * @return Returns enabled GPIO interrupt sources. + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_enabled_interrupts(void) +{ + uint32_t intflags = 0, tmp = 0; + for (uint8_t intch = 0; intch < MAX_GPIO_PIN_INT; intch++) { + tmp = (GPIO->INTR[intch].GPIO_INTR_CTRL & LSB_NIBBLE_MASK); + intflags |= (tmp << (NIBBLE_SHIFT * intch)); + } + return intflags; +} + +/***************************************************************************/ /** + * @brief Get enabled and pending GPIO pin interrupt of MCU HP Instance. + * Useful for handling more interrupt sources in the same interrupt handler. + * @pre \ref sl_si91x_gpio_enable_clock() \n + * @pre \ref sl_si91x_gpio_enable_pad_selection(), for HP instance \n + * @pre \ref sl_si91x_gpio_enable_pad_receiver(), for HP instance \n + * @pre \ref sl_gpio_set_pin_mode() \n + * @pre \ref sl_si91x_gpio_set_pin_direction() \n + * @param[in] None + * @return Returns pending GPIO interrupt sources + ******************************************************************************/ +static __INLINE uint32_t sl_gpio_get_enabled_pending_interrupts(void) +{ + uint32_t intflags = 0, tmp_ctrl = 0, tmp_sts = 0; + uint8_t intch = 0; + for (intch = 0; intch < MAX_GPIO_PIN_INT; intch++) { + tmp_ctrl = (GPIO->INTR[intch].GPIO_INTR_CTRL & INTERRUPT_MASK); + if (tmp_ctrl & MASK_CTRL) { + tmp_ctrl = (tmp_ctrl >> 1) | MASK_INTR; + } + tmp_sts = ((GPIO->INTR[intch].GPIO_INTR_STATUS) & (tmp_ctrl)); + tmp_sts = (tmp_sts & LSB_NIBBLE_MASK); + intflags |= (tmp_sts << (NIBBLE_SHIFT * intch)); + } + return intflags; +} + +/**************************************************************************/ /** + * @brief This API is used set ulp soc gpio mode + * \n(Gpio pin mode,ranges 000 -> Mode 0 to 111 -> Mode 7 Used for GPIO Pin Muxing ) + * @param[in] ulp_gpio : ulp gpio number + * @param[in] mode : GPIO mode + * \n possible values for this parameter are the following + * - \ref EGPIO_PIN_MUX_MODE0 : Select pin mode 0 + * - \ref EGPIO_PIN_MUX_MODE1 : Select pin mode 1 + * - \ref EGPIO_PIN_MUX_MODE2 : Select pin mode 2 + * - \ref EGPIO_PIN_MUX_MODE3 : Select pin mode 3 + * - \ref EGPIO_PIN_MUX_MODE4 : Select pin mode 4 + * - \ref EGPIO_PIN_MUX_MODE5 : Select pin mode 5 + * - \ref EGPIO_PIN_MUX_MODE6 : Select pin mode 6 + * - \ref EGPIO_PIN_MUX_MODE7 : Select pin mode 7 + * @return None + ******************************************************************************/ +static __INLINE void sl_si91x_gpio_ulp_soc_mode(uint8_t ulp_gpio, uint8_t mode) + +{ + ULPCLK->ULP_SOC_GPIO_MODE_REG[ulp_gpio].ULP_SOC_GPIO_MODE_REG_b.ULP_SOC_GPIO_MODE_REG = (unsigned int)(mode & 0x07); +} + +/** @} (end addtogroup GPIO) */ + +#ifdef __cplusplus +} +#endif + +#endif ///< GPIO_PRESENT +#endif ///< SL_PERIPHERAL_GPIO_H diff --git a/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c new file mode 100644 index 000000000..630815317 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c @@ -0,0 +1,1293 @@ +/****************************************************************************** +* @file sl_si91x_peripheral_gpio.c +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* SPDX-License-Identifier: Zlib +* +* The licensor of this software is Silicon Laboratories Inc. +* +* This software is provided 'as-is', without any express or implied +* warranty. In no event will the authors be held liable for any damages +* arising from the use of this software. +* +* Permission is granted to anyone to use this software for any purpose, +* including commercial applications, and to alter it and redistribute it +* freely, subject to the following restrictions: +* +* 1. The origin of this software must not be misrepresented; you must not +* claim that you wrote the original software. If you use this software +* in a product, an acknowledgment in the product documentation would be +* appreciated but is not required. +* 2. Altered source versions must be plainly marked as such, and must not be +* misrepresented as being the original software. +* 3. This notice may not be removed or altered from any source distribution. +* +******************************************************************************/ +#include "sl_si91x_peripheral_gpio.h" +#ifdef DEBUG_UART +#include "rsi_debug.h" +#endif + +/******************************************************************************* + *************************** DEFINES / MACROS ******************************** + ******************************************************************************/ +#define GPIO_RELEASE_VERSION 0 // gpio Release version +#define GPIO_MAJOR_VERSION 0 // gpio SQA version +#define GPIO_MINOR_VERSION 2 // gpio Developer version + +/******************************************************************************* + ************************ GLOBAL FUNCTIONS ************************** + ******************************************************************************/ +extern __INLINE void sl_gpio_set_pin_output(sl_gpio_port_t port, uint8_t pin); +extern __INLINE void sl_gpio_clear_pin_output(sl_gpio_port_t port, uint8_t pin); +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO HP instance. + * There are total 8 pin interrupts in this instance. + * To configure the interrupt, first GPIO initialization must be done. + * The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * Configuring the pin interrupt requires port number, pin number, interrupt number, + * and interrupt flag to be generated. + * Enable the IRQ handler. + ******************************************************************************/ +void sl_gpio_configure_interrupt(sl_gpio_port_t port, uint8_t pin, uint32_t int_no, sl_gpio_interrupt_flag_t flags) +{ + // Pin interrupt configuration in HP GPIO instance + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_FLAG(flags)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_INTR(int_no)); + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PORT_NUMBER = port; + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PIN_NUMBER = (sl_si91x_gpio_pin_t)pin; + // Enable or disable GPIO interrupt falling edge in GPIO HP instance + if ((flags & SL_GPIO_INTERRUPT_FALLING_EDGE) == SL_GPIO_INTERRUPT_FALLING_EDGE) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt rising edge in GPIO HP instance + if ((flags & SL_GPIO_INTERRUPT_RISING_EDGE) == SL_GPIO_INTERRUPT_RISING_EDGE) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable GPIO interrupt level high + if ((flags & SL_GPIO_INTERRUPT_HIGH) == SL_GPIO_INTERRUPT_HIGH) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } + // Disable GPIO interrupt level high + else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable GPIO interrupt level low + if ((flags & SL_GPIO_INTERRUPT_LOW) == SL_GPIO_INTERRUPT_LOW) { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } + // Disable GPIO interrupt level low + else { + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Un-mask the interrupt + GPIO->INTR[int_no].GPIO_INTR_CTRL_b.MASK = CLR; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to set pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To set the pin mode in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_gpio_set_pin_mode(sl_gpio_port_t port, uint8_t pin, sl_gpio_mode_t mode, uint32_t output_value) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(output_value)); + /* If disabling a pin, do not modify register to reduce the chance of */ + /* a glitch/spike(may not be sufficient precaution in all use cases). */ + if (mode != SL_GPIO_MODE_DISABLED) { + if (output_value) { + sl_gpio_set_pin_output(port, pin); // Set the GPIO pin + } else { + sl_gpio_clear_pin_output(port, pin); // Clear the GPIO pin + } + } + // if condition is satisfied when ULP GPIO instance occurs + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_MODE_PARAMETER(mode)); + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.MODE = mode; // Set mode in ULP GPIO instance + } + // else condition is satisfied when HP GPIO instance occurs + else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_MODE(mode)); + // Set mode in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.MODE = mode; + } + if (mode == SL_GPIO_MODE_DISABLED) { + if (output_value) { + sl_gpio_set_pin_output(port, pin); // Set the GPIO pin + } else { + sl_gpio_clear_pin_output(port, pin); // Clear the GPIO pin + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to get pin mode. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin status in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To get the pin mode in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin mode of GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +sl_gpio_mode_t sl_gpio_get_pin_mode(sl_gpio_port_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Read status of the pin in ULP GPIO instance + return (sl_gpio_mode_t)(ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.MODE); + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Read status of the pin in HP GPIO instance + return (sl_gpio_mode_t)(GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.MODE); + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to set pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To set the pin direction in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To set the pin direction in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_set_pin_direction(uint8_t port, uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(direction)); + if ((port == SL_GPIO_PORT_A) || (port == SL_GPIO_PORT_B) || (port == SL_GPIO_PORT_C) || (port == SL_GPIO_PORT_D)) { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Set the pin direction in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.DIRECTION = direction; + } else if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Set the pin direction in ULP GPIO instance + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.DIRECTION = direction; + } else { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(direction)); + // Set direction(input/output) in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = direction; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances to get pin direction. + * - If GPIO HP instance is considered, the following actions are performed: + * - To get the pin direction in GPIO HP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * - If GPIO ULP instance is considered, the following actions are performed: + * - To get the pin direction in GPIO ULP instance, GPIO initialization needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Get the pin direction of the GPIO pin. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_pin_direction(uint8_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Get the pin direction in ULP GPIO instance + return ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.DIRECTION; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Get the pin direction in HP GPIO instance + return GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.DIRECTION; + } +} + +/******************************************************************************* + * This API is used to enable PAD receiver in GPIO HP instance. + * The actions to be performed for enabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_receiver(uint8_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + // Set the REN(receiver bit) in PAD configuration register + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_REN = SET; +} + +/******************************************************************************* + * This API is used to disable PAD receiver in GPIO HP instance. + * The actions to be performed for disabling PAD are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Disable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_disable_pad_receiver(uint8_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + // Clear the REN(receiver bit) in PAD configuration register + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_REN = CLR; +} + +/******************************************************************************* + * This API is used to enable PAD selection in GPIO HP instance. + * The actions to be performed for enable PAD selection are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * @note: PAD number(25 to 30) are used for HOST PAD selection. + * Do not use PAD number-9 as it is used for other functionality. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_enable_pad_selection(uint8_t gpio_padnum) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PAD(gpio_padnum)); + if (gpio_padnum < PAD_SELECT) { + /*(tass_m4ss_gpio_sel)PAD selection (0 to 21) + A value of 1 on this gives control to M4SS(by default it is 0 means control) */ + PADSELECTION |= BIT(gpio_padnum); + } + if (gpio_padnum >= PAD_SELECT) { + /*(tass_m4ss_gpio_sel)PAD selection (22 to 33) + A value of 1 on this gives control to M4SS(by default it is 0 means NWP control) */ + PADSELECTION_1 |= BIT(gpio_padnum - PAD_SELECT); + } +} + +/******************************************************************************* + * This API is used to enable PAD selection in GPIO HP instance. + * @note: GPIO pin number(25 to 30) are used for HOST PAD selection. +*******************************************************************************/ +void sl_si91x_gpio_enable_host_pad_selection(uint8_t gpio_num) +{ + if (gpio_num >= HOST_PAD_MIN && gpio_num <= HOST_PAD_MAX) { + // (tass_m4ss_gpio_sel)PAD selection (25 to 30) + // A value of 1 on this gives control to M4SS(by default it is 0) + HOST_PADS_GPIO_MODE |= BIT(gpio_num - HOST_PAD_SELECT); + } +} + +/******************************************************************************* + * To select the PAD driver strength in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref sl_si91x_gpio_driver_strength_select_t. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_STRENGTH(strength)); + // Select the required drive strength in HP GPIO instance + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_E1_E2 = strength; +} + +/******************************************************************************* + * To select the PAD driver disable state in GPIO HP instance, GPIO initialization + * needs to be done first. + * - The actions to be performed in GPIO initialization are: + * - Enable the M4 clock of GPIO HP instance. + * - Select PAD selection of the GPIO HP instance. + * - Enable PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref sl_si91x_gpio_driver_disable_state_t. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + ******************************************************************************/ +void sl_si91x_gpio_select_pad_driver_disable_state(uint8_t gpio_num, sl_si91x_gpio_driver_disable_state_t disable_state) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_DISABLE_STATE(disable_state)); + // Select the required driver disable state in HP GPIO instance + PAD_REG(gpio_num)->GPIO_PAD_CONFIG_REG_b.PADCONFIG_P1_P2 = disable_state; +} + +/******************************************************************************* + * The GPIO pins to work in different instances, requires this clock. + * For GPIO HP instance, enable M4 clock of type @ref sl_si91x_gpio_select_clock_t. + * For GPIO ULP/UULP instances, enable ULP clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +void sl_si91x_gpio_enable_clock(sl_si91x_gpio_select_clock_t clock) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(clock)); + // Set M4 clock + if (clock == M4CLK_GPIO) { + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG3_b.EGPIO_CLK_ENABLE_b = SET; + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG2_b.EGPIO_PCLK_ENABLE_b = SET; + } + // Set ULP clock + else { + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = SET; + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = SET; + } +} + +/******************************************************************************* + * This API disables the M4/ ULP clock of GPIO instances. + * For GPIO HP instance, disable M4 clock of type @ref sl_si91x_gpio_select_clock_t. + * For GPIO ULP/UULP instances, disable ULP clock of type + * @ref sl_si91x_gpio_select_clock_t + ******************************************************************************/ +void sl_si91x_gpio_disable_clock(sl_si91x_gpio_select_clock_t clock) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(clock)); + // Clear M4 clock + if (clock == M4CLK_GPIO) { + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG3_b.EGPIO_CLK_ENABLE_b = CLR; + SL_PERIPHERAL_CLK->CLK_ENABLE_SET_REG2_b.EGPIO_PCLK_ENABLE_b = CLR; + } + // Clear ULP clock + else { + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_CLK_EN_b = CLR; + ULPCLK->ULP_MISC_SOFT_SET_REG_b.EGPIO_PCLK_ENABLE_b = CLR; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to enable the group interrupts. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_enable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + // Enable group interrupt in ULP GPIO instance + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = ENABLE; + // Enable group interrupt 1 in ULP GPIO instance + if (group_interrupt == GROUP_INT_1) { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = ENABLE; + } else { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_ENABLE = ENABLE; + } + } + // Enable group interrupt in HP GPIO instance + else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = ENABLE; + if (group_interrupt == GROUP_INT_1) { + // Enable group interrupt 1 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = ENABLE; + } else { + // Enable group interrupt 2 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_ENABLE = ENABLE; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to disable the group interrupts. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_disable_group_interrupt(sl_si91x_group_interrupt_t group_interrupt, uint8_t port, uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + // Disable group interrupt in ULP GPIO instance + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = DISABLE; + // Disable group interrupt 1 in ULP GPIO instance + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = DISABLE; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Disable group interrupt in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_INTERRUPT = DISABLE; + if (group_interrupt == GROUP_INT_1) { + // Disable group interrupt 1 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_ENABLE = DISABLE; + } else { + // Disable group interrupt 2 in HP GPIO instance + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_ENABLE = DISABLE; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to mask the group interrupts. + *******************************************************************************/ +void sl_si91x_gpio_mask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Enable group interrupt mask in ULP GPIO instance + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = ENABLE; + } else { + // Enable group interrupt mask in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = ENABLE; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to unmask the group interrupts. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. +*******************************************************************************/ +void sl_si91x_gpio_unmask_group_interrupt(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Disable group interrupt mask in ULP GPIO instance + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = DISABLE; + } else { + // Disable group interrupt mask in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.MASK = DISABLE; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set level/edge event of group interrupt. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_level_edge(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_level_edge_t level_edge) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(level_edge)); + if (port == SL_GPIO_ULP_PORT) { + // Enable group level edge interrupt in ULP GPIO instance + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE = level_edge; + } else { + // Enable group level edge interrupt in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE = level_edge; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get level/edge event of group interrupt. + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_level_edge(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Get group level edge interrupt in ULP GPIO instance + return ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE; + } else { + // Get group level edge interrupt in HP GPIO instance + return GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.LEVEL_EDGE; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to set polarity of group interrupt. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_set_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin, + sl_si91x_gpio_polarity_t polarity) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(polarity)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Set group interrupt polarity in ULP GPIO instance + if (group_interrupt == GROUP_INT_1) { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY = polarity; + } else { + ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_POLARITY = polarity; + } + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Set group interrupt polarity in HP GPIO instance + if (group_interrupt == GROUP_INT_1) { + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY = polarity; + } else { + GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_POLARITY = polarity; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to get polarity of group interrupt . + * @note: Select HP GPIO pins for HP instances(GPIO_6 to GPIO_57). Do not use + * GPIO pin number(0 to 5) in HP instance as these are used for other functionality. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_group_interrupt_polarity(sl_si91x_group_interrupt_t group_interrupt, + uint8_t port, + uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PORT_PIN(port, pin)); + // Get group interrupt polarity in ULP GPIO instance + return ULP_GPIO->PIN_CONFIG[pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY; + } else { + SL_GPIO_ASSERT(SL_GPIO_NDEBUG_PORT_PIN(port, pin)); + // Get group interrupt polarity in HP GPIO instance + if (group_interrupt == GROUP_INT_1) { + return GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT1_POLARITY; + } else { + return GPIO->PIN_CONFIG[(port * MAX_GPIO_PORT_PIN) + pin].GPIO_CONFIG_REG_b.GROUP_INTERRUPT2_POLARITY; + } + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instances. + * It is used to select and/or event of group interrupt. + * @example: Consider two GPIO pins for group interrupts. + * - If AND event is selected then both GPIO pins, interrupt should be + * generated to do specific task. + * - If OR event is selected then any one GPIO pin, interrupt generation + * should be enough to do specific task. + * @note: We are calling this API, inside the group interrupt configuration API's + * @ref sl_si91x_gpio_configure_group_interrupt(), used for HP instance, + * @ref sl_si91x_gpio_configure_ulp_group_interrupt(), used for ULP instance. +*******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_and_or(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + sl_si91x_gpio_and_or_t and_or) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(and_or)); + if (port == SL_GPIO_ULP_PORT) { + // Set group interrupt OR in ULP GPIO instance + if ((and_or & SL_GPIO_GROUP_INTERRUPT_OR) == (SL_GPIO_GROUP_INTERRUPT_OR)) { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = SET; + } + // Set group interrupt AND in ULP GPIO instance + else { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = CLR; + } + } else { + // Set group interrupt OR in HP GPIO instance + if ((and_or & SL_GPIO_GROUP_INTERRUPT_OR) == (SL_GPIO_GROUP_INTERRUPT_OR)) { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = SET; + } + // Set group interrupt AND in HP GPIO instance + else { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.AND_OR = CLR; + } + } +} + +/******************************************************************************* + * This API is used in GPIO HP instance to configure group interrupts. + * It has configuration pointer of type @ref sl_si91x_gpio_group_interrupt_config_t + * structure. + * GPIO HP instance has total 4 ports. Port-0, 1, 2 has 16 pins each. Port-3 has 9 pins. + * While configuring group interrupts, one can select random ports and pins for + * group interrupt. + * @example 1: + * - If port 1 is selected, any group of pins(0 to 16) can be selected for group interrupt. + * - Same applied for other ports also. + * @example 2: + * - Once can select port 1, pin 7 and port 2, pin 3 as a group for interrupt generation. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration structure + * @ref sl_si91x_gpio_group_interrupt_config_t. + * @note: Do not use Port 0, GPIO pin number(0 to 5) in HP instance + * as these are used for other functionality. +*******************************************************************************/ +void sl_si91x_gpio_configure_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration) +{ + uint8_t int_pin_count; + // Group interrupt pin configuration in HP GPIO instance + for (int_pin_count = 0; int_pin_count < configuration->grp_interrupt_cnt; int_pin_count++) { + sl_gpio_set_pin_mode(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count], + SL_GPIO_MODE_0, + SET); + sl_si91x_gpio_set_pin_direction(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count], + GPIO_INPUT); + sl_si91x_gpio_enable_pad_receiver(configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_polarity(configuration->grp_interrupt, + configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count], + configuration->grp_interrupt_pol[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_level_edge(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt, + configuration->level_edge); + sl_si91x_gpio_select_group_interrupt_and_or(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt, + configuration->and_or); + sl_si91x_gpio_enable_group_interrupt(configuration->grp_interrupt, + configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_unmask_group_interrupt(configuration->grp_interrupt_port[int_pin_count], + configuration->grp_interrupt); + } + // NVIC enable for group interrupt 1 + if (configuration->grp_interrupt == GROUP_INT_1) { + NVIC_EnableIRQ(GROUP_0_INTERRUPT_NAME); + NVIC_SetPriority(GROUP_0_INTERRUPT_NAME, PRIORITY_50); + } + // NVIC enable for group interrupt 2 + else if (configuration->grp_interrupt == GROUP_INT_2) { + NVIC_EnableIRQ(GROUP_1_INTERRUPT_NAME); + NVIC_SetPriority(GROUP_1_INTERRUPT_NAME, PRIORITY_51); + } +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO ULP instance. + * There are total 12 pin interrupts in this instance. + * To configure the interrupt, first ULP GPIO initialization must be done. + * The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * Configuring the pin interrupt requires pin number, interrupt number, + * and interrupt flag to be generated. + * Enable the IRQ handler. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_pin_interrupt(uint8_t int_no, + sl_si91x_gpio_interrupt_config_flag_t flags, + sl_si91x_gpio_pin_ulp_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_FLAG(flags)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_INTR(int_no)); + // Pin interrupt configuration in ULP GPIO instance + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PORT_NUMBER = ULP_PORT_NUM; + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.PIN_NUMBER = pin; + // Enable or disable GPIO interrupt falling edge in GPIO ULP instance + if ((flags & SL_GPIO_INTERRUPT_FALLING_EDGE) == SL_GPIO_INTERRUPT_FALLING_EDGE) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.FALL_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt rising edge in GPIO ULP instance + if ((flags & SL_GPIO_INTERRUPT_RISING_EDGE) == SL_GPIO_INTERRUPT_RISING_EDGE) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.RISE_EDGE_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt level high + if ((flags & SL_GPIO_INTERRUPT_HIGH) == SL_GPIO_INTERRUPT_HIGH) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_HIGH_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Enable or disable GPIO interrupt level low + if ((flags & SL_GPIO_INTERRUPT_LOW) == SL_GPIO_INTERRUPT_LOW) { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_ENABLE; + } else { + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.LEVEL_LOW_ENABLE = SL_GPIO_INTERRUPT_DISABLE; + } + // Un-mask the interrupt + ULP_GPIO->INTR[int_no].GPIO_INTR_CTRL_b.MASK = CLR; +} + +/******************************************************************************* + * This API is used in GPIO ULP instance to configure group interrupts. + * It has configuration pointer of type @ref sl_si91x_gpio_group_interrupt_config_t + * structure. + * ULP GPIO domain has only one port and calling as Port 4 in program which has maximum of 12 pins. + * While configuring group interrupts, one can select random pins which are allocated for + * ULP port. + * - One should assign group count of how many pins are passed. + * For more clarification look into group interrupt configuration structure + * @ref sl_si91x_gpio_group_interrupt_config_t. +*******************************************************************************/ +void sl_si91x_gpio_configure_ulp_group_interrupt(sl_si91x_gpio_group_interrupt_config_t *configuration) +{ + uint8_t int_pin_count; + // Group interrupt pin configuration in ULP GPIO instance + for (int_pin_count = 0; int_pin_count < configuration->grp_interrupt_cnt; int_pin_count++) { + sl_gpio_set_pin_mode(SL_GPIO_ULP_PORT, configuration->grp_interrupt_pin[int_pin_count], SL_GPIO_MODE_0, SET); + sl_si91x_gpio_set_pin_direction(SL_GPIO_ULP_PORT, configuration->grp_interrupt_pin[int_pin_count], GPIO_INPUT); + sl_si91x_gpio_enable_ulp_pad_receiver(configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_polarity(configuration->grp_interrupt, + SL_GPIO_ULP_PORT, + configuration->grp_interrupt_pin[int_pin_count], + configuration->grp_interrupt_pol[int_pin_count]); + sl_si91x_gpio_set_group_interrupt_level_edge(SL_GPIO_ULP_PORT, + configuration->grp_interrupt, + configuration->level_edge); + sl_si91x_gpio_select_group_interrupt_and_or(SL_GPIO_ULP_PORT, configuration->grp_interrupt, configuration->and_or); + sl_si91x_gpio_enable_group_interrupt(configuration->grp_interrupt, + SL_GPIO_ULP_PORT, + configuration->grp_interrupt_pin[int_pin_count]); + sl_si91x_gpio_unmask_group_interrupt(SL_GPIO_ULP_PORT, configuration->grp_interrupt); + } + // NVIC enable for ULP group interrupt + NVIC_EnableIRQ(ULP_GROUP_INTERRUPT_NAME); + NVIC_SetPriority(ULP_GROUP_INTERRUPT_NAME, PRIORITY_19); +} + +/******************************************************************************* + * This API is used for GPIO HP instance. + * It is used to clear group interrupt. +*******************************************************************************/ +void sl_si91x_gpio_clear_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + // Clear group interrupt in HP GPIO instance + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS_b.INTERRUPT_STATUS = SET; +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to get status of group interrupt generated. + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_group_interrupt_status(uint8_t port, sl_si91x_group_interrupt_t group_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + if (port == SL_GPIO_ULP_PORT) { + // Get group interrupt status in ULP GPIO instance + return ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS; + } else { + // Get group interrupt status in HP GPIO instance + return GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS; + } +} + +/******************************************************************************* + * This API is used for GPIO HP, ULP instance. + * It is used to select group interrupt wakeup. + ******************************************************************************/ +void sl_si91x_gpio_select_group_interrupt_wakeup(uint8_t port, + sl_si91x_group_interrupt_t group_interrupt, + uint8_t flags) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PORT(port)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(group_interrupt)); + // Enables or Disables wakeup group interrupt in ULP GPIO instance + if (port == SL_GPIO_ULP_PORT) { + if ((flags & SL_GPIO_GROUP_INTERRUPT_WAKEUP) == (SL_GPIO_GROUP_INTERRUPT_WAKEUP)) { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = SET; + } else { + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = CLR; + } + } else { + // Enables or Disables wakeup group interrupt in HP GPIO instance + if ((flags & SL_GPIO_GROUP_INTERRUPT_WAKEUP) == (SL_GPIO_GROUP_INTERRUPT_WAKEUP)) { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = SET; + } else { + GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_CTRL_REG_b.ENABLE_WAKEUP = CLR; + } + } +} + +/******************************************************************************* + * To enable ULP PAD receiver in GPIO ULP instance, ULP GPIO initialization needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_enable_ulp_pad_receiver(uint8_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + // Enable receiver bit in PAD configuration register in ULP instance + ULP_PAD_CONFIG_REG |= BIT(gpio_num); +} + +/******************************************************************************* + * This API is used to disable the ULP PAD receiver. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). +*******************************************************************************/ +void sl_si91x_gpio_disable_ulp_pad_receiver(uint32_t gpio_num) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + // Disable receiver bit in PAD configuration register in ULP instance + ULP_PAD_CONFIG_REG &= ~BIT(gpio_num); +} + +/******************************************************************************* + * To select the ULP PAD driver disable state in GPIO ULP instance, ULP GPIO initialization + * needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver disable state of type @ref sl_si91x_gpio_driver_disable_state_t. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_disable_state(uint8_t gpio_num, + sl_si91x_gpio_driver_disable_state_t disable_state) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_DISABLE_STATE(disable_state)); + // Select driver disable state in ULP PAD configuration registers + if (gpio_num <= GPIO_PAD_3) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_P1_P2_1 = disable_state; + } else if ((gpio_num >= GPIO_PAD_4) && (gpio_num <= GPIO_PAD_7)) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_P1_P2_2 = disable_state; + } else { + ULP_PAD_CONFIG1_REG->ULP_GPIO_PAD_CONFIG_REG_1.PADCONFIG_P1_P2_1 = disable_state; + } +} + +/******************************************************************************* + * To select the ULP PAD driver strength in GPIO ULP instance, ULP GPIO initialization + * needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD driver strength of type @ref sl_si91x_gpio_driver_strength_select_t. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_driver_strength(uint8_t gpio_num, sl_si91x_gpio_driver_strength_select_t strength) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_STRENGTH(strength)); + // Select drive strength in ULP PAD configuration registers + if (gpio_num <= GPIO_PAD_3) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_E1_E2_1 = strength; + } else if ((gpio_num >= GPIO_PAD_4) && (gpio_num <= GPIO_PAD_7)) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_E1_E2_2 = strength; + } else { + ULP_PAD_CONFIG1_REG->ULP_GPIO_PAD_CONFIG_REG_1.PADCONFIG_E1_E2_1 = strength; + } +} + +/******************************************************************************* + * To select the ULP PAD slew rate in GPIO ULP instance, ULP GPIO initialization + * needs to be done first. + * - The actions to be performed in ULP GPIO initialization are: + * - Enable the ULP clock of GPIO ULP instance. + * - Enable ULP PAD receiver for GPIO pin number, whether GPIO pin is selected as + * output/input. + * - Set pin mode and direction of the GPIO pin. + * - Select the PAD slew rate of type @ref sl_si91x_gpio_slew_rate_t. + * @note: Select ULP GPIO pins for ULP instances(ULP_GPIO_0 to ULP_GPIO_11). + ******************************************************************************/ +void sl_si91x_gpio_select_ulp_pad_slew_rate(uint8_t gpio_num, sl_si91x_gpio_slew_rate_t slew_rate) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_ULP_PIN(gpio_num)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(slew_rate)); + // Select slew rate in ULP PAD configuration registers + if (gpio_num <= GPIO_PAD_3) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_SR_1 = slew_rate; + } else if ((gpio_num >= GPIO_PAD_4) && (gpio_num <= GPIO_PAD_7)) { + ULP_PAD_CONFIG0_REG->ULP_GPIO_PAD_CONFIG_REG_0.PADCONFIG_SR_2 = slew_rate; + } else { + ULP_PAD_CONFIG1_REG->ULP_GPIO_PAD_CONFIG_REG_1.PADCONFIG_SR_1 = slew_rate; + } +} + +/******************************************************************************* + * This API is used to select the UULP mode in NPSS GPIO control register. + * Few actions are required to be performed before setting the mode, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_mux(uint8_t pin, sl_si91x_uulp_npss_mode_t mode) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_MODE_PARAMETER(mode)); + // Select pin mode in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_MODE = mode; +} + +/******************************************************************************* + * This API is used to enable receiver bit in NPSS GPIO control register. + * Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API, before + * using this API. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_receiver(uint8_t pin, sl_si91x_gpio_receiver_t receiver) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(receiver)); + // Select input buffer in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_REN = receiver; +} + +/******************************************************************************* + * This API is used to select the UULP direction in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Select UULP NPSS direction for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_direction(uint8_t pin, sl_si91x_gpio_direction_t direction) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(direction)); + // Set direction(input/output) in UULP GPIO instance + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN = direction; +} + +/******************************************************************************* + * This API is used to get the UULP direction in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Get the direction of the GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). +*******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_direction(uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + // Get direction(input/output) in UULP GPIO instance + return UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OEN; +} + +/******************************************************************************* + * This API is used to select the UULP pin value in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_pin_value(uint8_t pin, sl_si91x_gpio_pin_value_t pin_value) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(pin_value)); + // Set or Clear pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT = pin_value; +} + +/******************************************************************************* + * This API is used to toggle the UULP pin. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Toggle the UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +void sl_si91x_gpio_toggle_uulp_npss_pin(uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + // Set or Clear pin in UULP GPIO instance by controlling pin value + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_OUT ^= SET; +} + +/******************************************************************************* + * This API is used to get the UULP pin value in NPSS GPIO control register. + * Few actions are required to be performed before setting the direction, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Select the GPIO pin value. + * - Get the GPIO pin value. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_npss_pin(uint8_t pin) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + // Read pin status in UULP GPIO instance + return (UULP_GPIO_STATUS >> pin) & MASK_INTR; +} + +/******************************************************************************* + * This API is used to select polarity of the UULP GPIO to be considered + when used as a wakeup source from any of the Sleep States. + ******************************************************************************/ +void sl_si91x_gpio_select_uulp_npss_polarity(uint8_t pin, sl_si91x_gpio_polarity_t polarity) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_PIN(pin)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_PARAMETER(polarity)); + UULP_GPIO->NPSS_GPIO_CNTRL[pin].NPSS_GPIO_CTRLS_b.NPSS_GPIO_POLARITY = polarity; +} + +/******************************************************************************* + * This API is used to set the UULP NPSS GPIO to wakeup interrupt +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + UULP_GPIO_FSM->GPIO_WAKEUP_REGISTER |= (BIT(npssgpio_interrupt)); +} + +/******************************************************************************* + * This API is used to clear the UULP NPSS GPIO to wakeup interrupt +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_npss_wakeup_interrupt(uint8_t npssgpio_interrupt) +{ + UULP_GPIO_FSM->GPIO_WAKEUP_REGISTER &= ~(BIT(npssgpio_interrupt)); +} + +/******************************************************************************* + * This API is used to mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt mask is performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select the . + * @note: All the UULP interrupts are masked by default. +*******************************************************************************/ +void sl_si91x_gpio_mask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_INTR(npssgpio_interrupt)); + GPIO_NPSS_INTERRUPT_MASK_SET_REG = (npssgpio_interrupt << 1); +} + +/******************************************************************************* + * This API is used to un-mask the UULP NPSS GPIO interrupt. + * Few actions are required to be performed before interrupt un-mask is performed, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Un-mask interrupt by setting corresponding bit in register. + * @note: All the UULP interrupts are masked by default. +*******************************************************************************/ +void sl_si91x_gpio_unmask_uulp_npss_interrupt(uint8_t npssgpio_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_UULP_INTR(npssgpio_interrupt)); + GPIO_NPSS_INTERRUPT_MASK_CLR_REG = (npssgpio_interrupt << 1); +} + +/******************************************************************************* + * This API is used to clear the UULP interrupt. +*******************************************************************************/ +void sl_si91x_gpio_clear_uulp_interrupt(uint8_t npssgpio_interrupt) +{ + GPIO_NPSS_INTERRUPT_CLEAR_REG = (npssgpio_interrupt << 1); +} + +/******************************************************************************* + * This API is used to get the UULP interrupt status. + ******************************************************************************/ +uint8_t sl_si91x_gpio_get_uulp_interrupt_status(void) +{ + return (GPIO_NPSS_INTERRUPT_STATUS_REG >> 1) & UULP_PIN_MASK; +} + +/******************************************************************************* + * This API is used to get the ULP interrupt status. + ******************************************************************************/ +uint32_t sl_si91x_gpio_get_ulp_interrupt_status(uint32_t flags) +{ + return ULP_GPIO->INTR[flags].GPIO_INTR_STATUS_b.INTERRUPT_STATUS; +} + +/******************************************************************************* + * This API is used to configure the pin interrupt in GPIO UULP instance. + * There are total 5 pin interrupts in this instance. + * To configure the interrupt, first UULP GPIO initialization must be done. + * The actions to be performed in UULP GPIO initialization are: + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Set UULP PAD configuration register. + * - Select UULP NPSS receiver for UULP GPIO pin. + * - Set the mode of the GPIO pin. + * - Set the direction of the GPIO pin. + * - Configure the UULP pin interrupt. + * Enable the IRQ handler. + * @note: The NPSS GPIO interrupt pin number is transformed into a bit mask by + * shifting a single bit to the left by the specified pin number. +*******************************************************************************/ +void sl_si91x_gpio_configure_uulp_interrupt(sl_si91x_gpio_interrupt_config_flag_t flags, uint8_t npssgpio_interrupt) +{ + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_FLAG(flags)); + SL_GPIO_ASSERT(SL_GPIO_VALIDATE_INTR(npssgpio_interrupt)); + npssgpio_interrupt = BIT(npssgpio_interrupt); + // Unmask NPSS interrupt + sl_si91x_gpio_unmask_uulp_npss_interrupt(npssgpio_interrupt); + // Enable or disable interrupt rising edge in GPIO UULP instance + if ((flags & SL_GPIO_INTERRUPT_RISING_EDGE) == SL_GPIO_INTERRUPT_RISING_EDGE) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_0); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_0); + } + // Enable or disable GPIO interrupt falling edge in GPIO UULP instance + if ((flags & SL_GPIO_INTERRUPT_FALLING_EDGE) == SL_GPIO_INTERRUPT_FALLING_EDGE) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_8); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_8); + } + // Enable or disable interrupt level low in UULP GPIO instance + if ((flags & SL_GPIO_INTERRUPT_LOW) == SL_GPIO_INTERRUPT_LOW) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_16); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_16); + } + // Enable or disable interrupt level high in UULP GPIO instance + if ((flags & SL_GPIO_INTERRUPT_HIGH) == SL_GPIO_INTERRUPT_HIGH) { + GPIO_NPSS_GPIO_CONFIG_REG |= (npssgpio_interrupt << BIT_24); + } else { + GPIO_NPSS_GPIO_CONFIG_REG &= ~((uint32_t)npssgpio_interrupt << BIT_24); + } + NVIC_EnableIRQ(UULP_PININT_NVIC_NAME); +} + +/******************************************************************************* + * This API is used to clear one (or) more pending ULP GPIO interrupts. +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_interrupt(uint32_t flags) +{ + ULP_GPIO->INTR[flags].GPIO_INTR_STATUS_b.INTERRUPT_STATUS = SET; +} + +/******************************************************************************* + * This API is used to clear the ULP group interrupts. +*******************************************************************************/ +void sl_si91x_gpio_clear_ulp_group_interrupt(sl_si91x_group_interrupt_t group_interrupt) +{ + ULP_GPIO->GPIO_GRP_INTR[group_interrupt].GPIO_GRP_INTR_STS_b.INTERRUPT_STATUS = SET; +} + +/******************************************************************************* + * This API is used to verify assumptions and print message if the assumption is false. + ******************************************************************************/ +void sl_assert_failed(uint8_t *file, uint32_t line) +{ +#ifdef DEBUG_UART + DEBUGOUT("Assert failed: file %s on line %lu \r\n", file, line); +#else + (void)file; + (void)line; +#endif +} + +/******************************************************************************* + * This API is used to select the UULP PAD configuration register. + * It has pad_config pointer of type @ref uulp_pad_config_t. + * It selects the mode, direction, polarity, enables receiver etc in the register. + * To set the UULP PAD configuration, + * - Enable the ULP clock using @ref sl_si91x_gpio_enable_clock() API. + * - Select UULP NPSS input buffer for UULP GPIO pin. + * @note: Select UULP GPIO pins for UULP instances(UULP_GPIO_0 to UULP_GPIO_4). +*******************************************************************************/ +void sl_si91x_gpio_set_uulp_pad_configuration(uulp_pad_config_t *pad_config) +{ + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_MODE = + (sl_si91x_uulp_npss_mode_t)pad_config->mode; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_REN = + (sl_si91x_gpio_receiver_t)pad_config->receiver; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_OEN = + (sl_si91x_gpio_direction_t)pad_config->direction; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_OUTPUT = + (sl_si91x_gpio_pin_value_t)pad_config->output; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_PAD_SELECT = + (sl_si91x_gpio_uulp_pad_t)pad_config->pad_select; + UULP_PAD_CONFIG_REG(pad_config->gpio_padnum)->UULP_GPIO_PAD_CONFIG_REG_b.GPIO_POLARITY = + (sl_si91x_gpio_polarity_t)pad_config->polarity; +} + +/******************************************************************************* + * To get the release, sqa and dev version of gpio peripheral + * It returns the structure for gpio version. + * Structure includes three members: + * - Release version + * - Major version (SQA version) + * - Minor version (Dev version) + ******************************************************************************/ +sl_si91x_gpio_version_t sl_si91x_gpio_get_version(void) +{ + sl_si91x_gpio_version_t version; + version.release = GPIO_RELEASE_VERSION; + version.major = GPIO_MAJOR_VERSION; + version.minor = GPIO_MINOR_VERSION; + return version; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h new file mode 100644 index 000000000..3955c9bef --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_m4.h @@ -0,0 +1,253 @@ +/***************************************************************************/ /** + * @file rsi_m4.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _RSI_M4_HAL_H_ +#define _RSI_M4_HAL_H_ +#ifdef SLI_SI91X_MCU_INTERFACE + +#include "rsi_pkt_mgmt.h" +#include "sl_device.h" +#include "sl_status.h" + +/****************************************************** + * * Constants + * ******************************************************/ + +#define M4_ISR_IRQ 74 + +#define TA_MEMORY_OFFSET_ADDRESS 0x00400000 +#if defined(SLI_SI917) || defined(SLI_SI915) +#define M4_MEMORY_OFFSET_ADDRESS 0x00500000 +#else +#define M4_MEMORY_OFFSET_ADDRESS 0x00200000 +#endif + +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#ifndef NVIC +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#endif + +#define M4SS_P2P_INT_BASE_ADDRESS 0x46008000 +#define MCU_PWR_CTRL_BASE_ADDR 0x24048400 +#define MISC_CFG_HOST_CTRL *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x0C) +#ifndef M4SS_P2P_INTR_SET_REG +#define M4SS_P2P_INTR_SET_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x16C) +#endif +#ifndef M4SS_P2P_INTR_CLR_REG +#define M4SS_P2P_INTR_CLR_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x170) +#endif +#define P2P_STATUS_REG *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x174) +#define TASS_P2P_INTR_MASK_SET *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x178) +#define TASS_P2P_INTR_MASK_CLR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x17C) +#define TASS_P2P_INTR_CLEAR *(volatile uint32_t *)(M4SS_P2P_INT_BASE_ADDRESS + 0x180) + +#define TASS_P2P_INT_BASE_ADDRESS 0x41050000 + +#define TASS_P2P_INTR_SET_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x8C) +#define TASS_P2P_INTR_CLR_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x90) + +#define M4_TX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x34) +#define M4_RX_DMA_DESC_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x5C) +#define HOST_INTR_STATUS_REG *(volatile uint32_t *)(TASS_P2P_INT_BASE_ADDRESS + 0x04) + +#define DMA_DESC_REG_VALID (0xA0 << 8) + +#define TA_wakeup_M4 BIT(2) +#define TA_is_active BIT(3) +#define M4_wakeup_TA BIT(0) +#define M4_is_active BIT(1) + +/*Macro used to define the PTE CRC value of the Firmware 17 Boards*/ +#define FIRMWARE_17_PTE_CRC_VALUE 0 + +/*Macro used to notify NWP about M4 XTAL usage*/ +#define TURN_ON_XTAL_REQUEST BIT(9) +#define TURN_OFF_XTAL_REQUEST BIT(10) +#define M4_IS_USING_XTAL_REQUEST BIT(11) + +#define ARM_MASK_1 0xE000E100 +#define ARM_MASK_1 0xE000E100 +#define ARM_MASK_1 0xE000E100 + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +//! This interrupt is raised by M4 to NWP when there is a TX packet from M4 to read +#define RX_BUFFER_VALID BIT(1) +#define TX_PKT_PENDING_INTERRUPT BIT(2) +#define UPGRADE_M4_IMAGE BIT(5) +#if defined(SLI_SI917) || defined(SLI_SI915) +#define M4_WAITING_FOR_TA_TO_WR_ON_FLASH BIT(6) +#endif +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#define SIDE_BAND_CRYPTO_INTR BIT(7) +#endif +#define M4_WAITING_FOR_TA_DEINIT BIT(8) + +#define TX_PKT_TRANSFER_DONE_INTERRUPT BIT(2) +//! This interrupt is received from NWP when RX packet is pending from NWP +#define RX_PKT_TRANSFER_DONE_INTERRUPT BIT(1) +//! This interrupt is received from NWP when TX packet transfer from M4 to NWP is done + +#define M4_IMAGE_UPGRADATION_PENDING_INTERRUPT BIT(4) +//! This interrupt is raised by NWP to M4 when there is a TX packet from M4 to read + +#if defined(SLI_SI917) || defined(SLI_SI915) +//! This interrupt is raised by NWP to M4 when there is a flash write request from M4 to NWP in common flash mode +#define TA_WRITING_ON_COMM_FLASH BIT(5) +#endif + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#define SIDE_BAND_CRYPTO_DONE BIT(6) +#endif +#define NWP_DEINIT_IN_COMM_FLASH BIT(7) + +//! This interrupt is received from TA when RSI_BUFFER_FULL is clear in TA +#define TA_RSI_BUFFER_FULL_CLEAR_EVENT BIT(8) + +#if defined(SLI_SI917) || defined(SLI_SI915) +//! Option value for m4 app from flash to ram API +#define UPGRADE_M4_IMAGE_OTA 1 +#define TA_WRITES_ON_COMM_FLASH 2 +#define M4_WAIT_FOR_NWP_DEINIT 3 +#endif + +#ifdef SLI_SI91X_ENABLE_OS +#define TASS_P2P_INTR_PRI 5 +#define SYSTICK_INTR_PRI 7 +#else +#define TASS_P2P_INTR_PRI 5 +#define SYSTICK_INTR_PRI (1 << __NVIC_PRIO_BITS) - 1 +#endif +/****************************************************** + * * Enumerations + * ******************************************************/ + +/****************************************************** + * * Type Definitions + * ******************************************************/ +typedef struct rsi_m4ta_desc_dword1_s { + //! Reserved + uint32_t reserved : 15; + + //! 1 bit : indicates the presence of more descriptors + //! 1 - last descriptor + //! 0 - more descriptors are present + uint32_t last_desc : 1; + + //! Buffer queue_no to be transfered for this descriptor + uint32_t queue_no : 4; + + //! Buffer length to be transfered for this descriptor + uint32_t length : 12; + +} rsi_m4ta_desc_dword1_t; + +typedef struct rsi_m4ta_desc_s { + //! source address + uint32_t addr; + + uint16_t length; + //! descriptor control fields + +} rsi_m4ta_desc_t; + +//! host descriptor structure +typedef struct rsi_frame_desc_s { + //! Data frame body length. Bits 14:12=queue, 000 for data, Bits 11:0 are the length + uint8_t frame_len_queue_no[2]; + //! Frame type + uint8_t frame_type; + //! Unused , set to 0x00 + uint8_t reserved[9]; + //! Management frame descriptor response status, 0x00=success, else error + uint8_t status; + uint8_t reserved1[3]; +} rsi_frame_desc_t; + +//! P2P registers Backup structure +typedef struct rsi_p2p_intr_status_bkp_s { + uint32_t tass_p2p_intr_mask_clr_bkp; + uint32_t m4ss_p2p_intr_set_reg_bkp; +} rsi_p2p_intr_status_bkp_t; + +/****************************************************** + * * Structures + * ******************************************************/ + +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +int16_t rsi_frame_write(rsi_frame_desc_t *uFrameDscFrame, uint8_t *payloadparam, uint16_t size_param); +rsi_pkt_t *rsi_frame_read(void); +int16_t rsi_device_interrupt_status(uint8_t *int_status); + +sl_status_t sli_m4_interrupt_isr(void); +void sli_m4_ta_interrupt_init(void); +void sli_si91x_raise_pkt_pending_interrupt_to_ta(void); +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +void sli_si91x_raise_side_band_interrupt_to_ta(void); +#endif +int32_t rsi_send_pkt_to_ta(rsi_m4ta_desc_t *tx_desc); +void rsi_transfer_to_ta_done_isr(void); +void rsi_pkt_pending_from_ta_isr(void); +sl_status_t sli_receive_from_ta_done_isr(void); +int16_t rsi_device_buffer_full_status(void); +int rsi_submit_rx_pkt(void); +void unmask_ta_interrupt(uint32_t interrupt_no); +void mask_ta_interrupt(uint32_t interrupt_no); +void raise_m4_to_ta_interrupt(uint32_t interrupt_no); +void clear_m4_to_ta_interrupt(uint32_t interrupt_no); +void clear_ta_interrupt_mask(void); +void set_ta_interrupt_mask(void); +void clear_ta_to_m4_interrupt(uint32_t interrupt_no); +void sl_mv_m4_app_from_flash_to_ram(int option); +uint32_t NVIC_GetIRQEnable(IRQn_Type IRQn); +void sli_si91x_config_m4_dma_desc_on_reset(void); +void rsi_update_tx_dma_desc(uint8_t skip_dma_valid); +void rsi_update_rx_dma_desc(void); +sl_status_t si91x_req_wakeup(void); +void sl_si91x_ta_events_init(void); /*Function used to create and initialize event mechanism for NWP related events */ +bool sli_si91x_is_m4_using_xtal(void); +bool sli_si91x_is_xtal_in_use_by_m4(void); +void sli_si91x_set_m4_is_using_xtal(void); +void sli_si91x_set_xtal_in_use_by_m4(void); +void sli_si91x_xtal_turn_on_request_from_m4_to_TA(void); +void sli_si91x_xtal_turn_off_request_from_m4_to_TA(void); +void sli_si91x_raise_xtal_interrupt_to_ta(uint16_t xtal_enable); +void sli_si91x_send_m4_xtal_usage_notification_to_ta(void); +void sli_si91x_clear_xtal_in_use_by_m4(void); +#endif +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h new file mode 100644 index 000000000..b127f48a3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_os.h @@ -0,0 +1,142 @@ +/***************************************************************************/ /** + * @file rsi_os.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_OS_H +#define RSI_OS_H + +#include "rsi_error.h" +#include +/****************************************************** + * * Macros + * ******************************************************/ +// Macro to increment a value +#define RSI_ATOMIC_INCREMENT(value) \ + { \ + (value)++; \ + } + +// Macro to decrement a value +#define RSI_ATOMIC_DECREMENT(value) \ + { \ + (value)--; \ + } +// Error none (success) +#define RSI_ERR_NONE (0) + +// Error returned when invalid arguments are given +#define RSI_ERR_INVALID_ARGS (1) + +// Error returned when timeout error occurs +#define RSI_ERR_TIMEOUT (3) + +// Mutex unlock value +#define RSI_NO_OS_MUTEX_UNLOCKED (0) + +// Mutex lock value +#define RSI_NO_OS_MUTEX_LOCKED (1) + +// Macro to set the mutex lock +#define RSI_NO_OS_ATOMIC_MUTEX_SET(mutex, value) (mutex) = value + +// Macro for checking whether mutex is locked or not +#define RSI_NO_OS_ATOMIC_MUTEX_CHECK(mutex, value) (((mutex) == value) ? 1 : 0) +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +/****************************************************** + * * Type Definitions + * ******************************************************/ +typedef uint32_t rsi_reg_flags_t; +// Handle to manage Semaphores. +typedef uint32_t rsi_semaphore_handle_t; +// Handle to manage Mutex. +typedef uint32_t rsi_mutex_handle_t; + +// Task handler +typedef void *rsi_task_handle_t; + +typedef long rsi_base_type_t; +// Task function +typedef void (*rsi_task_function_t)(void *function); +/****************************************************** + * * Structures + * ******************************************************/ +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +/* --------- CRITICAL SECTION FUNCTIONS --------- */ +rsi_reg_flags_t rsi_critical_section_entry(void); +void rsi_critical_section_exit(rsi_reg_flags_t flags); +/* -------------- MUTEX FUNCTIONS -------------- */ +rsi_error_t rsi_mutex_create(rsi_mutex_handle_t *p_mutex); +rsi_error_t rsi_mutex_lock(volatile rsi_mutex_handle_t *p_mutex); +void rsi_mutex_lock_from_isr(volatile rsi_mutex_handle_t *mutex); +rsi_error_t rsi_mutex_unlock(volatile rsi_mutex_handle_t *p_mutex); +void rsi_mutex_unlock_from_isr(volatile rsi_mutex_handle_t *mutex); +rsi_error_t rsi_mutex_destroy(rsi_mutex_handle_t *p_mutex); + +/* ------------- SEMAPHORE FUNCTIONS ----------- */ +rsi_error_t rsi_semaphore_create(rsi_semaphore_handle_t *p_sem, uint32_t cnt); +rsi_error_t rsi_semaphore_destroy(rsi_semaphore_handle_t *p_sem); +rsi_error_t rsi_semaphore_check_and_destroy(rsi_semaphore_handle_t *p_sem); +rsi_error_t rsi_semaphore_wait(rsi_semaphore_handle_t *p_sem, uint32_t timeout); +rsi_error_t rsi_semaphore_post(rsi_semaphore_handle_t *p_sem); +rsi_error_t rsi_semaphore_post_from_isr(rsi_semaphore_handle_t *semaphore); +rsi_error_t rsi_semaphore_reset(rsi_semaphore_handle_t *p_sem); + +/* ------------- TASK FUNCTIONS ----------- */ +rsi_error_t rsi_task_create(rsi_task_function_t task_function, + uint8_t *task_name, + uint32_t stack_size, + void *parameters, + uint32_t task_priority, + rsi_task_handle_t *task_handle); + +void rsi_task_destroy(rsi_task_handle_t *task_handle); +void rsi_task_delete(rsi_task_handle_t *task_handle); +void rsi_os_task_delay(uint32_t timeout_ms); +void rsi_task_suspend(rsi_task_handle_t *task_handle); +void rsi_start_os_scheduler(void); +void rsi_wireless_driver_task_create(void); +/* ---------- OS MEMORY MAPPING FUNCTIONS -------- */ +void *rsi_virtual_to_physical_address(void *x); +void *rsi_physical_to_virtual_address(void *x); +void *rsi_malloc(uint32_t size); +void rsi_free(void *p); +void rsi_vport_enter_critical(void); +void rsi_vport_exit_critical(void); +int32_t rsi_get_error(int32_t sockID); +void rsi_set_os_errno(int32_t error); +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h new file mode 100644 index 000000000..54966c59a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_pkt_mgmt.h @@ -0,0 +1,96 @@ +/***************************************************************************/ /** + * @file rsi_pkt_mgmt.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_PKT_MGMT_H +#define RSI_PKT_MGMT_H + +#include "rsi_os.h" +#include +#if ((defined RSI_SDIO_INTERFACE) && (defined SLI_SI917)) +#define SIZE_OF_HEADROOM 216 +#else +#define SIZE_OF_HEADROOM 0 +#endif +/****************************************************** + * * Macros + * ******************************************************/ +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +/****************************************************** + * * Type Definitions + * ******************************************************/ +// driver TX/RX packet structure +typedef struct rsi_pkt_s { + // next packet pointer + struct rsi_pkt_s *next; + +#if ((defined RSI_SDIO_INTERFACE) && (defined SLI_SI917)) + uint8_t headroom[SIZE_OF_HEADROOM]; +#endif + + // host descriptor + uint8_t desc[16]; + + // payload + uint8_t data[1]; +} rsi_pkt_t; + +// packet pool structure +typedef struct rsi_pkt_pool_s { + // Pool total packets count + uint16_t size; + + // Pool avaialble packets count + uint16_t avail; + + // Pool pointer + void **pool; + + rsi_semaphore_handle_t pkt_sem; + +} rsi_pkt_pool_t; + +/****************************************************** + * * Structures + * ******************************************************/ +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +int32_t rsi_pkt_pool_init(rsi_pkt_pool_t *pool_cb, uint8_t *buffer, uint32_t total_size, uint32_t pkt_size); +rsi_pkt_t *rsi_pkt_alloc(rsi_pkt_pool_t *pool_cb); +int32_t rsi_pkt_free(rsi_pkt_pool_t *pool_cb, rsi_pkt_t *pkt); +uint32_t rsi_is_pkt_available(rsi_pkt_pool_t *pool_cb); +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h new file mode 100644 index 000000000..2f6ca1d2b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/rsi_wisemcu_hardware_setup.h @@ -0,0 +1,123 @@ +/***************************************************************************/ /** + * @file rsi_wisemcu_hardware_setup.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RSI_HW_SETUP_H__ +#define __RSI_HW_SETUP_H__ +/*Includes*/ + +// +#include "rsi_power_save.h" +#include "base_types.h" + +/*Configure the PMU and XTAL good times */ +#define PMU_GOOD_TIME 0x34 /* 900 us*/ +#define XTAL_GOOD_TIME 31 /*Duration in us*/ + +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE +#define NWPAON_MEM_HOST_ACCESS_CTRL_SET_1 (*(volatile uint32_t *)(0x41300000 + 0x0)) +#define NWPAON_MEM_HOST_ACCESS_CTRL_CLEAR_1 (*(volatile uint32_t *)(0x41300000 + 0x4)) +#define M4SS_TASS_CTRL_SET_REG (*(volatile uint32_t *)(0x24048400 + 0x34)) +#define M4SS_TASS_CTRL_CLR_REG (*(volatile uint32_t *)(0x24048400 + 0x38)) +#define M4SS_REF_CLK_MUX_CTRL BIT(24) +#define TASS_REF_CLK_MUX_CTRL BIT(25) +#define M4SS_CTRL_TASS_AON_PWR_DMN_RST_BYPASS BIT(2) +#endif + +#ifdef CHIP_9118 +/*Macro to be used for configuring the 'rams_in_use' parameter in 'sl_si91x_configure_ram_retention()' function*/ +#define WISEMCU_0KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_3 | RAM_BANK_4 | RAM_BANK_5 | RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 \ + | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_16KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 \ + | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_48KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_8 | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 \ + | RAM_BANK_13) +#define WISEMCU_112KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_9 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_128KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_144KB_RAM_IN_USE (RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_176KB_RAM_IN_USE (RAM_BANK_2 | RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_192KB_RAM_IN_USE (RAM_BANK_10 | RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_208KB_RAM_IN_USE (RAM_BANK_11 | RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_240KB_RAM_IN_USE (RAM_BANK_12 | RAM_BANK_13) +#define WISEMCU_320KB_RAM_IN_USE (RAM_BANK_13) +#define WISEMCU_384KB_RAM_IN_USE (0) +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) +/*Macro to be used for configuring the 'rams_in_use' parameter in 'sl_si91x_configure_ram_retention()' function*/ +#define WISEMCU_0KB_RAM_IN_USE \ + (RAM_BANK_0 | RAM_BANK_1 | RAM_BANK_2 | RAM_BANK_3 | RAM_BANK_4 | RAM_BANK_5 | RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 \ + | RAM_BANK_9) +#define WISEMCU_16KB_RAM_IN_USE (RAM_BANK_4 | RAM_BANK_5 | RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_64KB_RAM_IN_USE (RAM_BANK_6 | RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_128KB_RAM_IN_USE (RAM_BANK_7 | RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_192KB_RAM_IN_USE (RAM_BANK_8 | RAM_BANK_9) +#define WISEMCU_256KB_RAM_IN_USE (RAM_BANK_9) +#define WISEMCU_320KB_RAM_IN_USE (0U) + +/*Macros are used for antenna front switch-end controls */ +#define FRONT_END_SWITCH_SEL0 0 +#define FRONT_END_SWITCH_SEL1 BIT(29) +#define FRONT_END_SWITCH_SEL2 BIT(30) +#define FRONT_END_SWITCH_SEL3 (BIT(29) | BIT(30)) +void RSI_Wireless_GPIO_Frontend_Switch_Controls(void); +#endif +/*Macro used to define the PTE CRC value of the Firmware 17 Boards*/ +#define FIRMWARE_17_PTE_CRC_VALUE 0 + +/*Macro to be used for configuring the 'rams_retention_during_sleep' parameter in 'sl_si91x_configure_ram_retention()' function*/ +#define WISEMCU_RETAIN_DEFAULT_RAM_DURING_SLEEP (1) +#define WISEMCU_RETAIN_16K_RAM_DURING_SLEEP (M4ULP_RAM16K_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_128K_RAM_DURING_SLEEP (M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_192K_RAM_DURING_SLEEP \ + (M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN | M4SS_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_384K_RAM_DURING_SLEEP \ + (M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN | M4SS_RAM_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_M4SS_RAM_DURING_SLEEP (M4SS_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_ULPSS_RAM_DURING_SLEEP (ULPSS_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_TASS_RAM_DURING_SLEEP (TA_RAM_RETENTION_MODE_EN) +#define WISEMCU_RETAIN_M4ULP_RAM_DURING_SLEEP (M4ULP_RAM_RETENTION_MODE_EN) + +/*Function proto-types*/ +void sli_si91x_configure_wireless_frontend_controls(uint32_t switch_sel); +void sl_si91x_hardware_setup(void); +void sl_si91x_trigger_sleep(SLEEP_TYPE_T sleepType, + uint8_t lf_clk_mode, + uint32_t stack_address, + uint32_t jump_cb_address, + uint32_t vector_offset, + uint32_t mode); +void sl_si91x_configure_ram_retention(uint32_t rams_in_use, uint32_t rams_retention_during_sleep); + +/*End of file not truncated*/ +#endif \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h new file mode 100644 index 000000000..c473b6bb0 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sl_device.h @@ -0,0 +1,33 @@ +/***************************************************************************/ /** + * @file sl_device.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "si91x_device.h" +#include "rsi_m4.h" diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h new file mode 100644 index 000000000..1817aaccc --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_soc.h @@ -0,0 +1,84 @@ +/***************************************************************************/ /** + * @file sli_siwx917_soc.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include + +// Upgrade images +#define RSI_JUMP_TO_PC 'J' + +//! Check CRC +#define CHECK_NWP_INTEGRITY 'K' +#define RSI_UPGRADE_BL '#' + +#define HOST_INTF_REG_OUT 0x4105003C +#define HOST_INTF_REG_IN 0x41050034 +#define BOARD_READY 0xABCD +#define REG_READ 0xD1 +#define REG_WRITE 0xD2 +#define PONG_WRITE 0xD4 +#define PING_WRITE 0xD5 +#define GPIO_RESET 0xD7 +#define LOAD_BOOTLOADER 0xD8 +#ifdef RS9116 +#define HOST_INTERACT_REG_VALID (0xA0 << 8) +#define HOST_INTERACT_REG_VALID_READ (0xAB << 8) +#else +#define HOST_INTERACT_REG_VALID (0xAB << 8) +#define HOST_INTERACT_REG_VALID_READ (0xAB << 8) +#endif + +#define RSI_RESET_LOOP_COUNTER(X) X = 0 +#define RSI_WHILE_LOOP(X, Y) while ((X++) < (uint32_t)Y) +#define RSI_LOOP_COUNT_UPGRADE_IMAGE 0xFFFF +#define RSI_LOOP_COUNT_WAKEUP_REQ 0xFFFFFFFF +#define RSI_LOOP_COUNT_WAKEUP_WAIT 0xFFFFFFFF +#define RSI_LOOP_COUNT_UPGRADE_REQ 0xFFFF +#define RSI_LOOP_COUNT_UPGRADE_CHUNK 0xFFFF +#define RSI_LOOP_COUNT_UPGRADE_STATUS 0xFFFF +#define RSI_LOOP_COUNT_SELECT_OPTION 0xFFFF +#define RSI_CHECK_LOOP_COUNTER(X, Y) \ + do { \ + if (X >= Y) \ + return -1; \ + } while (0) + +void sli_siwx917_update_system_core_clock(void); +void RSI_Set_Cntrls_To_M4(void); +void RSI_Set_Cntrls_To_TA(void); + +void sli_si91x_platform_init(void); +int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data); +int16_t rsi_waitfor_boardready(void); +int16_t rsi_select_option(uint8_t cmd); +int16_t rsi_bl_select_option(uint8_t cmd); +int16_t rsi_boot_insn(uint8_t type, uint16_t *data); +int16_t rsi_mem_rd(uint32_t addr, uint16_t len, uint8_t *dBuf); +void sl_si91x_ulp_wakeup_init(void); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h new file mode 100644 index 000000000..ea3505d70 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/inc/sli_siwx917_timer.h @@ -0,0 +1,57 @@ +/***************************************************************************/ /** + * @file sli_siwx917_timer.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include + +/****************************************************** + * * Macros + * ******************************************************/ +#define sl_si91x_timer_NODE_0 0 + +/****************************************************** + * * Type Definitions + * ******************************************************/ + +typedef struct { + uint32_t start_time; + uint32_t timeout; +} sl_si91x_timer_t; + +/****************************************************** + * * Function Declarations + * ******************************************************/ +void sl_si91x_timer_expiry_interrupt_handler(void); +uint32_t sl_si91x_timer_read_counter(void); +void sl_si91x_timer_init(sl_si91x_timer_t *timer, uint32_t duration); +int32_t sl_si91x_timer_expired(const sl_si91x_timer_t *timer); +uint32_t sl_si91x_timer_left(const sl_si91x_timer_t *timer); + +uint32_t rsi_hal_gettickcount(void); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c new file mode 100644 index 000000000..3ef91f522 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c @@ -0,0 +1,75 @@ +/***************************************************************************/ /** + * @file rsi_hal_mcu_m4_ram.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(SLI_SI917) || defined(SLI_SI915) +//! This file should be in RAM +#include "sl_device.h" + +/*==================================================*/ +/** + * @fn void sl_mv_m4_app_from_flash_to_ram(int option) + * @brief Raise interrupt to NWP and poll for task done + * @param[in] option + * @param[out] none + */ + +void sl_mv_m4_app_from_flash_to_ram(int option) +{ + + //! Disable all interrupts + __disable_irq(); + + if (option == UPGRADE_M4_IMAGE_OTA) { + //! Raise interrupt to NWP + raise_m4_to_ta_interrupt(UPGRADE_M4_IMAGE); + + //! Poll for bit to clear + while (M4SS_P2P_INTR_CLR_REG & UPGRADE_M4_IMAGE) + ; + } else if (option == TA_WRITES_ON_COMM_FLASH) { + //! Raise interrupt to NWP + raise_m4_to_ta_interrupt(M4_WAITING_FOR_TA_TO_WR_ON_FLASH); + + //! Poll for bit to clear + while (M4SS_P2P_INTR_CLR_REG & M4_WAITING_FOR_TA_TO_WR_ON_FLASH) + ; + } else if (option == M4_WAIT_FOR_NWP_DEINIT) { + //! Raise interrupt to NWP + raise_m4_to_ta_interrupt(M4_WAITING_FOR_TA_DEINIT); + + //! Poll for bit to clear + while (M4SS_P2P_INTR_CLR_REG & M4_WAITING_FOR_TA_DEINIT) + ; + } + + //! Enable all interrupts + __enable_irq(); +} + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c new file mode 100644 index 000000000..ee950f4eb --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c @@ -0,0 +1,386 @@ +/***************************************************************************/ /** + * @file rsi_hal_mcu_m4_rom.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_types.h" +#include "sl_constants.h" +#include "sl_status.h" +#include "sl_device.h" +#include "sl_rsi_utility.h" +#include "rsi_m4.h" +#include "rsi_ipmu.h" + +#ifdef SL_WIFI_COMPONENT_INCLUDED +#include "sl_si91x_host_interface.h" +#endif + +#include "cmsis_os2.h" +osEventFlagsId_t ta_events = NULL; +#define TA_PKT_TX_DONE (1 << 1) +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#define SIDE_BAND_DONE (1 << 2) +#endif + +static bool m4_is_using_xtal_without_ta_notification; +static bool m4_using_xtal; + +/** @addtogroup SOC4 +* @{ +*/ +/** + * @fn void sli_si91x_raise_pkt_pending_interrupt_to_ta(void) + * @brief Raise the packet pending interrupt to NWP + * @param[in] void + * @return void + */ +void sli_si91x_raise_pkt_pending_interrupt_to_ta(void) +{ + // Write the packet pending interrupt to NWP register + M4SS_P2P_INTR_SET_REG = TX_PKT_PENDING_INTERRUPT; + osEventFlagsWait(ta_events, TA_PKT_TX_DONE, osFlagsWaitAny, osWaitForever); +} +/** + * @fn bool sli_si91x_is_m4_using_xtal(void); + * @brief This API is used to get the whether XTAL is enabled by M4 without notifying NWP + * @return true : XTAL is enabled by M4 without notifying NWP + * false : XTAL is not enabled by M4 + */ +bool sli_si91x_is_m4_using_xtal(void) +{ + return m4_is_using_xtal_without_ta_notification; +} +/** + * @fn void sli_si91x_set_m4_is_using_xtal(void); + * @brief This API is set XTAL is enabled by M4 without notifying NWP + */ +void sli_si91x_set_m4_is_using_xtal(void) +{ + m4_is_using_xtal_without_ta_notification = true; +} + +/** + * @fn bool sli_si91x_is_xtal_in_use_by_m4(void); + * @brief This API is used to get the whether XTAL is used by M4 or any of HP peripherals + * @return true : XTAL is being used by M4 or HP peripherals + * false : XTAL is not being used + */ +bool sli_si91x_is_xtal_in_use_by_m4(void) +{ + return m4_using_xtal; +} + +/** + * @fn void sli_si91x_set_xtal_in_use_by_m4(void); + * @brief This API is used set XTAL is used by M4 or any of HP peripherals + */ +void sli_si91x_set_xtal_in_use_by_m4(void) +{ + m4_using_xtal = true; +} + +/** + * @fn void sli_si91x_clear_xtal_in_use_by_m4(void); + * @brief This API is used to clear XTAL usage by M4 or any of HP peripherals + */ +void sli_si91x_clear_xtal_in_use_by_m4(void) +{ + m4_using_xtal = false; +} +/** + * @fn void sli_si91x_xtal_turn_off_request_from_m4_to_TA(void); + * @brief This API is used to Notify NWP that M4 doesn't requires XTAL clock source + */ +void sli_si91x_xtal_turn_off_request_from_m4_to_TA(void) +{ + if (sli_si91x_is_xtal_in_use_by_m4() == true) { + /* If M4 is using XTAL then request NWP to turn OFF XTAL as M4 is going to sleep */ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_OFF_XTAL_REQUEST); + sli_si91x_clear_xtal_in_use_by_m4(); + } +} +/** + * @fn void sli_si91x_xtal_turn_on_request_from_m4_to_TA(void); + * @brief This API is used to Notify NWP that M4 requires XTAL clock source + */ +void sli_si91x_xtal_turn_on_request_from_m4_to_TA(void) +{ + if (sli_si91x_is_xtal_in_use_by_m4() == false) { + if (TASS_P2P_INTR_CLEAR_REG & TURN_ON_XTAL_REQUEST) { + clear_ta_to_m4_interrupt(TURN_ON_XTAL_REQUEST); + } else { + + /* Confirm if the NWP has completed its initialization process */ + if (sl_si91x_is_device_initialized()) { + /* Raise the turn ON xtal interrupt to NWP */ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_ON_XTAL_REQUEST); + /* If M4 is using XTAL then notify NWP to turn ON XTAL during programing common flash*/ + sli_si91x_raise_xtal_interrupt_to_ta(M4_IS_USING_XTAL_REQUEST); + } + /*If the 'M4 Enabled XTAL without NWP Notification, +* then after net initialization (NWP device initialization), a request to turn on the XTAL will be sent to the NWP*/ + else { + /* set XTAL is enabled by M4 without notifying NWP */ + sli_si91x_set_m4_is_using_xtal(); + } + } + /* Set M4 XTAL usage flag */ + sli_si91x_set_xtal_in_use_by_m4(); + } +} + +/** + * @fn void sli_si91x_raise_xtal_interrupt_to_ta(uint16_t interrupt_no) + * @brief Raise the turn on/off xtal interrupt to NWP + * @param[in] xtal_enable - true to enable xtal, false to disable xtal + * @return void + */ +void sli_si91x_raise_xtal_interrupt_to_ta(uint16_t interrupt_no) +{ + //! Wake up NWP + P2P_STATUS_REG |= M4_WAKEUP_TA; + + //!wait for NWP active + while (!(P2P_STATUS_REG & TA_IS_ACTIVE)) + ; + + // Write the turn_on_xtal interrupt to NWP register + M4SS_P2P_INTR_SET_REG = interrupt_no; + + //! Poll for bit to clear + //!Wait for NWP using flash bit + while (!(TASS_P2P_INTR_CLEAR_REG & interrupt_no)) + ; + clear_ta_to_m4_interrupt(interrupt_no); + + sl_si91x_host_clear_sleep_indicator(); +} + +/** + * @fn void sli_si91x_send_m4_xtal_usage_notification_to_ta(void); + * @brief This API sends a notification to the NWP indicating whether + * the M4 core is currently utilizing the XTAL as its clock source. + */ +void sli_si91x_send_m4_xtal_usage_notification_to_ta(void) +{ + +#if !(SLI_SI91X_MCU_PSRAM_PRESENT) + /* Check whether M4 is using XTAL */ + if (sli_si91x_is_m4_using_xtal() == true) +#endif + { + /* If M4 is using XTAL then request NWP to turn ON XTAL*/ + sli_si91x_raise_xtal_interrupt_to_ta(TURN_ON_XTAL_REQUEST); + /* If M4 is using XTAL then notify NWP to turn ON XTAL during programing common flash*/ + sli_si91x_raise_xtal_interrupt_to_ta(M4_IS_USING_XTAL_REQUEST); + } +} + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +/** + * @fn void sli_si91x_raise_side_band_interrupt_to_ta(void) + * @brief Raise the side band interrupt to NWP + * @param[in] void + * @return void + */ +void sli_si91x_raise_side_band_interrupt_to_ta(void) +{ + // Write the packet pending interrupt to NWP register + M4SS_P2P_INTR_SET_REG = SIDE_BAND_CRYPTO_INTR; +} +#endif + +/** + * @fn void raise_m4_to_ta_interrupt(uint32_t interrupt_no) + * @brief Set interrupt. + * @param[in] interrupt_no - Process of a interrupt number + * @return void + */ + +void raise_m4_to_ta_interrupt(uint32_t interrupt_no) +{ + M4SS_P2P_INTR_SET_REG = interrupt_no; +} + +/** + * @fn void mask_ta_interrupt(uint32_t interrupt_no) + * @brief Process a interrupt mask. + * @param[in] void + * @return void + */ +void mask_ta_interrupt(uint32_t interrupt_no) +{ + TASS_P2P_INTR_MASK_SET = interrupt_no; +} + +/** + * @fn void clear_ta_to_m4_interrupt(uint32_t interrupt_no) + * @brief Clear interrupt raised by NWP. + * @param[in] interrupt_no - Process of a interrupt number + * @return void + */ +void clear_ta_to_m4_interrupt(uint32_t interrupt_no) +{ + TASS_P2P_INTR_CLEAR = interrupt_no; + TASS_P2P_INTR_CLR_REG = interrupt_no; +} + +/** + * @fn void sli_m4_interrupt_isr(void) + * @brief Raise the packet pending interrupt to NWP + * @param[in] void + * @return void + */ + +sl_status_t sli_m4_interrupt_isr(void) +{ + if (TASS_P2P_INTR_CLEAR & TX_PKT_TRANSFER_DONE_INTERRUPT) { + + osEventFlagsSet(ta_events, TA_PKT_TX_DONE); + // Clear the interrupt + clear_ta_to_m4_interrupt(TX_PKT_TRANSFER_DONE_INTERRUPT); + + } else if (TASS_P2P_INTR_CLEAR & RX_PKT_TRANSFER_DONE_INTERRUPT) { + + // Call done interrupt isr + sl_status_t status = sli_receive_from_ta_done_isr(); + VERIFY_STATUS_AND_RETURN(status); + + // Clear the interrupt + clear_ta_to_m4_interrupt(RX_PKT_TRANSFER_DONE_INTERRUPT); + + } else if (TASS_P2P_INTR_CLEAR & TA_RSI_BUFFER_FULL_CLEAR_EVENT) { + + mask_ta_interrupt(TA_RSI_BUFFER_FULL_CLEAR_EVENT); + + sli_si91x_set_event(SL_SI91X_TA_BUFFER_FULL_CLEAR_EVENT); + + // Clear the interrupt + clear_ta_to_m4_interrupt(TA_RSI_BUFFER_FULL_CLEAR_EVENT); + } +#if defined(SLI_SI917) || defined(SLI_SI915) + else if (TASS_P2P_INTR_CLEAR & TA_WRITING_ON_COMM_FLASH) { + //! moves m4 app to RAM and polls for NWP done + sl_mv_m4_app_from_flash_to_ram(TA_WRITES_ON_COMM_FLASH); + // Clear the interrupt + clear_ta_to_m4_interrupt(TA_WRITING_ON_COMM_FLASH); + } else if (TASS_P2P_INTR_CLEAR & NWP_DEINIT_IN_COMM_FLASH) { + //! moves m4 app to RAM and polls for NWP done + sl_mv_m4_app_from_flash_to_ram(M4_WAIT_FOR_NWP_DEINIT); + // Clear the interrupt + clear_ta_to_m4_interrupt(NWP_DEINIT_IN_COMM_FLASH); + } + //! Below changes are requried for M4 Image upgration in dual flash config + else if (TASS_P2P_INTR_CLEAR & M4_IMAGE_UPGRADATION_PENDING_INTERRUPT) { + //! moves m4 app to RAM and polls for NWP done + sl_mv_m4_app_from_flash_to_ram(UPGRADE_M4_IMAGE_OTA); + // Clear the interrupt + clear_ta_to_m4_interrupt(M4_IMAGE_UPGRADATION_PENDING_INTERRUPT); + } +#endif +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + //! Below changes are requried for SIDE BAND CRYPTO + else if (TASS_P2P_INTR_CLEAR & SIDE_BAND_CRYPTO_DONE) { + osEventFlagsSet(ta_events, SIDE_BAND_DONE); + // Clear the interrupt + clear_ta_to_m4_interrupt(SIDE_BAND_CRYPTO_DONE); + } +#endif + else { + SL_DEBUG_LOG("\r\n INVALID INTERRUPT \r\n", 0); + BREAKPOINT(); + } + return SL_STATUS_OK; +} + +/** + * @fn sl_status_t sli_receive_from_ta_done_isr(void) + * @brief Called when DMA done for RX packet is received + * @param[in] global_cb_p - pointer to the global control block + * @return void + */ +sl_status_t sli_receive_from_ta_done_isr(void) +{ +#ifdef SL_WIFI_COMPONENT_INCLUDED + extern sl_wifi_buffer_t *rx_pkt_buffer; + extern sl_si91x_buffer_queue_t sli_ahb_bus_rx_queue; + // Add to rx packet to CCP queue + sl_status_t status = sli_si91x_add_to_queue(&sli_ahb_bus_rx_queue, rx_pkt_buffer); + VERIFY_STATUS_AND_RETURN(status); + + //! Set event RX pending event to host + sl_si91x_host_set_bus_event(SL_SI91X_NCP_HOST_BUS_RX_EVENT); +#endif + + return SL_STATUS_OK; +} + +/*==================================================*/ +/** + * @fn sl_status_t sl_si91x_bus_read_interrupt_status(uint8_t *int_status) + * @brief Returns the value of the Interrupt register + * @param[in] status + * @param[out] buffer full status reg value + * @return errorcode + * 0 = Success + * -2 = Reg read failure + */ +sl_status_t sl_si91x_bus_read_interrupt_status(uint16_t *int_status) +{ + *int_status = (uint8_t)HOST_INTR_STATUS_REG; + + return RSI_SUCCESS; +} + +sl_status_t si91x_req_wakeup(void) +{ + P2P_STATUS_REG |= M4_wakeup_TA; + if (!(P2P_STATUS_REG & TA_is_active)) { + //!TBD Need add timeout + while (!(P2P_STATUS_REG & TA_is_active)) + ; + } + return SL_STATUS_OK; +} + +void sl_si91x_host_clear_sleep_indicator(void) +{ + P2P_STATUS_REG &= ~M4_wakeup_TA; +} + +void IRQ074_Handler(void) +{ + sli_m4_interrupt_isr(); +} + +void sl_si91x_ta_events_init(void) +{ + if (ta_events == NULL) { + ta_events = osEventFlagsNew(NULL); + } +} +/** @} */ \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c new file mode 100644 index 000000000..2808aa34d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c @@ -0,0 +1,129 @@ +/***************************************************************************/ /** + * @file sl_platform.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sli_siwx917_soc.h" +#include "sl_device.h" +#include "sl_si91x_constants.h" +#include "sl_si91x_status.h" +#include "sl_si91x_core_utilities.h" +#include "sl_status.h" +#include "sl_constants.h" +#include +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#include "sl_board_configuration.h" +#include "rsi_rom_clks.h" + +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "cmsis_os2.h" +#include "FreeRTOSConfig.h" +#endif + +sl_status_t sli_si91x_submit_rx_pkt(void); +void sl_board_enable_vcom(void); +sl_status_t si91x_bootup_firmware(const uint8_t select_option); + +void sli_si91x_platform_init(void) +{ +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + /* Before NWP going to power save mode ,set m4ss_ref_clk_mux_ctrl ,tass_ref_clk_mux_ctrl, + AON domain power supply controls from NWP to M4 */ + RSI_Set_Cntrls_To_M4(); +#endif + + // Enable DWT and cycle counting + CoreDebug->DEMCR |= 0x01000000; + DWT->CTRL |= 0x1; + +#if (configUSE_TICKLESS_IDLE == 0) + SysTick_Config(SystemCoreClock / CONFIG_SYS_CLOCK_TICKS_PER_SEC); + // Set P2P Intr priority + NVIC_SetPriority(SysTick_IRQn, SYSTICK_INTR_PRI); +#endif + //On boot-up, verify the M4_wakeup_TA bit in the P2P status register and clearing the bit if it is set. + if (P2P_STATUS_REG & M4_wakeup_TA) { + P2P_STATUS_REG &= ~M4_wakeup_TA; + } +} + +void sl_board_enable_vcom(void) +{ + //empty function +} + +sl_status_t si91x_bootup_firmware(const uint8_t select_option) +{ + uint8_t skip_bootload_sequence = 0; + si91x_status_t retval = RSI_ERROR_NONE; + + if (!(P2P_STATUS_REG & TA_is_active)) { + P2P_STATUS_REG |= M4_wakeup_TA; + skip_bootload_sequence = 1; + } + while (!(P2P_STATUS_REG & TA_is_active)) { + //loop is waiting for the TA to become active + } + + if (!skip_bootload_sequence) { + do { + retval = rsi_waitfor_boardready(); + if (retval == RSI_ERROR_NONE) { + break; + } + if ((retval < 0) && (retval != RSI_ERROR_WAITING_FOR_BOARD_READY) && (retval != RSI_ERROR_IN_OS_OPERATION)) { + return convert_si91x_status_to_sl_status(retval); + } + } while ((retval == RSI_ERROR_WAITING_FOR_BOARD_READY) || (retval == RSI_ERROR_IN_OS_OPERATION)); + retval = rsi_select_option(select_option); + VERIFY_STATUS_AND_RETURN(convert_si91x_status_to_sl_status(retval)); + } + + // Update TX & RX DMA descriptor address + rsi_update_tx_dma_desc(skip_bootload_sequence); + rsi_update_rx_dma_desc(); + +#if SL_SI91X_FAST_FW_UP + status = rsi_set_fast_fw_up(); + if (status != RSI_SUCCESS) { + SL_PRINTF(SL_DEVICE_INIT_SET_FAST_FIRMWARE_UP_ERROR, COMMON, LOG_ERROR, "status: %4x", status); + return status; + } +#endif + + sli_m4_ta_interrupt_init(); + if (!(M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID)) { + sli_si91x_submit_rx_pkt(); + } + +#if defined(SL_CATALOG_KERNEL_PRESENT) + osKernelInitialize(); +#endif + + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c new file mode 100644 index 000000000..9fe21e8a6 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c @@ -0,0 +1,296 @@ +/***************************************************************************/ /** + * @file sl_platform_wireless.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "rsi_wisemcu_hardware_setup.h" +#include "rsi_m4.h" +#include "rsi_rom_egpio.h" +#include "rsi_pll.h" +#include "rsi_rom_clks.h" +#include "rsi_rom_ulpss_clk.h" +#include "rsi_rom_power_save.h" +#include "sl_si91x_host_interface.h" +#include "sl_rsi_utility.h" +#include "system_si91x.h" +#include +#include "cmsis_os2.h" +#include "sl_rsi_utility.h" + +extern osEventFlagsId_t si91x_events; +extern osEventFlagsId_t si91x_bus_events; +extern osEventFlagsId_t si91x_async_events; +extern uint32_t frontend_switch_control; +extern osMutexId_t side_band_crypto_mutex; +extern sli_si91x_command_queue_t cmd_queues[SI91X_CMD_MAX]; + +/** @addtogroup SOC2 +* @{ +*/ + +/** + * @brief Configure the default hardware configuration required for 'WiSeMCU' mode. + * @param[in] None + * @note Must be called in main before using any power save related configurations in applications. + * @return Void + */ +void sl_si91x_hardware_setup(void) +{ + /* Disable OTHER_CLK that was enabled at Start-up*/ + RSI_CLK_PeripheralClkDisable3(M4CLK, M4_SOC_CLK_FOR_OTHER_ENABLE); + +#ifndef SL_ULP_TIMER + /* Disable Timer clock that was enabled in Bootloader*/ + RSI_ULPSS_TimerClkDisable(ULPCLK); +#endif + +#if !(defined(SLI_SI917) || defined(SLI_SI915)) + /* Disable 40MHz Clocks*/ + RSI_ULPSS_DisableRefClks(MCU_ULP_40MHZ_CLK_EN); +#endif + + /* Power-Down Button Calibration*/ + RSI_PS_BodPwrGateButtonCalibDisable(); + + /* Disable PTAT for Analog Peripherals*/ + RSI_PS_AnalogPeriPtatDisable(); + + /* Disable PTAT for Brown-Out Detection Clocks*/ + RSI_PS_BodClksPtatDisable(); + + /* Power-Down unused Analog(IPMU) Domain peripherals*/ + RSI_IPMU_PowerGateClr(AUXDAC_PG_ENB | AUXADC_PG_ENB | WURX_CORR_PG_ENB | WURX_PG_ENB | ULP_ANG_CLKS_PG_ENB + | CMP_NPSS_PG_ENB); + + /* Power-Down unused NPSS Domain peripherals*/ + RSI_PS_NpssPeriPowerDown(SLPSS_PWRGATE_ULP_MCUWDT | SLPSS_PWRGATE_ULP_MCUPS | SLPSS_PWRGATE_ULP_MCUTS + | SLPSS_PWRGATE_ULP_MCUSTORE2 | SLPSS_PWRGATE_ULP_MCUSTORE3 +#ifndef SL_SLEEP_TIMER + | SLPSS_PWRGATE_ULP_MCURTC +#endif + ); + +#ifndef DS_BASED_WKP + RSI_PS_PowerSupplyDisable(POWER_ENABLE_DEEPSLEEP_TIMER); +#endif + /* Power-Down unused NPSS Domain peripherals*/ + RSI_PS_PowerSupplyDisable(POWER_ENABLE_TIMESTAMPING); + +#ifdef CHIP_9118 + /* Power-Down Unused M4SS Domain peripherals */ + RSI_PS_M4ssPeriPowerDown( + +#ifndef DEBUG_UART + M4SS_PWRGATE_ULP_M4_FPU | +#endif + M4SS_PWRGATE_ULP_ETHERNET | M4SS_PWRGATE_ULP_EFUSE | M4SS_PWRGATE_ULP_SDIO_SPI | M4SS_PWRGATE_ULP_USB + | M4SS_PWRGATE_ULP_RPDMA +#ifndef DEBUG_UART + | M4SS_PWRGATE_ULP_PERI1 +#endif + | M4SS_PWRGATE_ULP_PERI2 | M4SS_PWRGATE_ULP_PERI3 | M4SS_PWRGATE_ULP_CCI | M4SS_PWRGATE_ULP_SD_MEM); + /* Power-Down unused ULPSS Domain peripherals*/ + RSI_PS_UlpssPeriPowerDown( +#ifndef SL_ULP_TIMER + ULPSS_PWRGATE_ULP_MISC | +#endif + ULPSS_PWRGATE_ULP_AUX | ULPSS_PWRGATE_ULP_CAP | ULPSS_PWRGATE_ULP_VAD +#ifndef DEBUG_UART + | ULPSS_PWRGATE_ULP_UART +#endif + | ULPSS_PWRGATE_ULP_SSI | ULPSS_PWRGATE_ULP_I2S | ULPSS_PWRGATE_ULP_I2C | ULPSS_PWRGATE_ULP_IR + | ULPSS_PWRGATE_ULP_UDMA | ULPSS_PWRGATE_ULP_FIM); + + /* Turn off ULPSS SRAM domains*/ + RSI_PS_UlpssRamBanksPowerDown(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3 | ULPSS_2K_BANK_4 + | ULPSS_2K_BANK_5 | ULPSS_2K_BANK_6 | ULPSS_2K_BANK_7); + /* Turn off ULPSS SRAM Core/Periphery domains*/ + RSI_PS_UlpssRamBanksPeriPowerDown(ULPSS_2K_BANK_0 | ULPSS_2K_BANK_1 | ULPSS_2K_BANK_2 | ULPSS_2K_BANK_3 + | ULPSS_2K_BANK_4 | ULPSS_2K_BANK_5 | ULPSS_2K_BANK_6 | ULPSS_2K_BANK_7); +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) + /* Power-Down Unused M4SS Domains */ + RSI_PS_M4ssPeriPowerDown( +#ifndef SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION + M4SS_PWRGATE_ULP_QSPI_ICACHE | +#endif +#ifndef DEBUG_UART + M4SS_PWRGATE_ULP_EFUSE_PERI | +#endif + M4SS_PWRGATE_ULP_SDIO_SPI | M4SS_PWRGATE_ULP_RPDMA); + + /* Power-Down Unused ULPSS Domain peripherals */ + RSI_PS_UlpssPeriPowerDown( +#ifndef SL_ULP_TIMER + ULPSS_PWRGATE_ULP_MISC | +#endif + ULPSS_PWRGATE_ULP_AUX | ULPSS_PWRGATE_ULP_CAP +#ifndef DEBUG_UART + | ULPSS_PWRGATE_ULP_UART +#endif + | ULPSS_PWRGATE_ULP_SSI | ULPSS_PWRGATE_ULP_I2S | ULPSS_PWRGATE_ULP_I2C | ULPSS_PWRGATE_ULP_IR + | ULPSS_PWRGATE_ULP_UDMA | ULPSS_PWRGATE_ULP_FIM); +#endif + /* Power-Down High-Frequency PLL Domain */ + RSI_PS_SocPllSpiDisable(); + /* Power-Down QSPI-DLL Domain */ + RSI_PS_QspiDllDomainDisable(); + /* Configure PMU Start-up Time to be used on Wake-up*/ + RSI_PS_PmuGoodTimeDurationConfig(PMU_GOOD_TIME); + /* Configure XTAL Start-up Time to be used on Wake-up*/ + RSI_PS_XtalGoodTimeDurationConfig(XTAL_GOOD_TIME); + /*Enable first boot up*/ + RSI_PS_EnableFirstBootUp(1); +} + +/** + * @brief This API is used to configure wireless GPIO front end controls from NWP to M4 + * @return none + */ +void sli_si91x_configure_wireless_frontend_controls(uint32_t switch_sel) +{ +#if SLI_SI91X_MCU_INTERFACE + switch (switch_sel) { + case FRONT_END_SWITCH_SEL0: + //!GPIO 46,47,48 + break; + case FRONT_END_SWITCH_SEL1: +#if defined(SLI_SI917B0) || defined(SLI_SI915) + { + //!Program GPIO mode6 in ULP for ULP4,ULP5,ULP0 GPIOS + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO4, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO5, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO0, 6); + } +#else + { + //!GPIO 46,47,48 + } +#endif + break; + case FRONT_END_SWITCH_SEL2: +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + //!Program GPIO mode6 in ULP for ULP4,ULP5,ULP0 GPIOS + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO4, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO5, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO0, 6); +#endif + break; + case FRONT_END_SWITCH_SEL3: +#if !defined(SLI_SI917B0) && !defined(SLI_SI915) + //!Program GPIO mode6 in ULP for ULP4,ULP5,ULP7 GPIOS + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO4, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO5, 6); + RSI_EGPIO_SetPinMux(EGPIO1, 0, GPIO7, 6); +#endif + break; + default: + break; + } +#endif +} + +/** + * @brief Configure the default hardware configuration required for 'WiSeMCU' mode. + * @param[in] rams_in_use - RAMs to be powered functionally (the rest of the RAM banks will be power gates) + * \n Macros used for this parameter: + * \n WISEMCU_0KB_RAM_IN_USE : None of the RAMs will be powered , i.e., all RAM banks will be power gates + * \n WISEMCU_16KB_RAM_IN_USE : Only 16KB RAM will be retained + * \n WISEMCU_48KB_RAM_IN_USE : Only 48KB RAM will be retained + * \n WISEMCU_112KB_RAM_IN_USE : Only 112KB RAM will be retained + * \n WISEMCU_128KB_RAM_IN_USE : Only 128KB RAM will be retained + * \n WISEMCU_144KB_RAM_IN_USE : Only 114KB RAM will be retained + * \n WISEMCU_176KB_RAM_IN_USE : Only 176KB RAM will be retained + * \n WISEMCU_192KB_RAM_IN_USE : Only 192KB RAM will be retained + * \n WISEMCU_208KB_RAM_IN_USE : Only 208KB RAM will be retained + * \n WISEMCU_240KB_RAM_IN_USE : Only 240KB RAM will be retained + * \n WISEMCU_320KB_RAM_IN_USE : Only 320KB RAM will be retained + * \n WISEMCU_384KB_RAM_IN_USE : Only 384KB RAM will be retained + * + * \n Macros used for 9117: + * \n WISEMCU_64KB_RAM_IN_USE : 320KB RAM will be retained + * \n WISEMCU_128KB_RAM_IN_USE : 320KB RAM will be retained + * \n WISEMCU_192KB_RAM_IN_USE : 320KB RAM will be retained + * \n WISEMCU_256KB_RAM_IN_USE : 320KB RAM will be retained + * + * @param[in] rams_retention_during_sleep - Configure RAM retentions to the hardware so that particular RAM banks are retained during sleep + * \n Macros used for this parameter: + * \n WISEMCU_RETAIN_DEFAULT_RAM_DURING_SLEEP : Select the RAM Retention controls automatically by API based on 'rams_power_gate' value passed by user + * \n WISEMCU_RETAIN_16K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM + * \n WISEMCU_RETAIN_128K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM and 112KB M4-ULP RAM + * \n WISEMCU_RETAIN_192K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM and 112KB M4-ULP RAM and 64KB M4SS RAM + * \n WISEMCU_RETAIN_384K_RAM_DURING_SLEEP : Retain 16KB M4-ULP RAM and 112KB M4-ULP RAM and 64KB M4SS RAM and TASS 192KB RAM + * \n WISEMCU_RETAIN_M4SS_RAM_DURING_SLEEP : Retain Only 64KB M4SS RAM + * \n WISEMCU_RETAIN_ULPSS_RAM_DURING_SLEEP : Retain Only 16KB ULPSS RAM + * \n WISEMCU_RETAIN_TASS_RAM_DURING_SLEEP : Retain Only 192KB TASS RAM + * \n WISEMCU_RETAIN_M4ULP_RAM_DURING_SLEEP : Retain Only 112KB M4-ULP RAM + * @return void + * @note Must be called in main before using any power save related configurations in applications. + */ +void sl_si91x_configure_ram_retention(uint32_t rams_in_use, uint32_t rams_retention_during_sleep) +{ + + uint32_t rams_to_be_powered_down = rams_in_use; + +#if (SL_SI91X_SI917_RAM_MEM_CONFIG == 1) // SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC + rams_to_be_powered_down &= ~(RAM_BANK_8 | RAM_BANK_9); +#elif (SL_SI91X_SI917_RAM_MEM_CONFIG == 2) // SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM + rams_to_be_powered_down &= ~(RAM_BANK_9); +#endif + + /* Turn off Unused SRAMs*/ + RSI_PS_M4ssRamBanksPowerDown(rams_to_be_powered_down); + + /* Turn off Unused SRAM Core/Periphery domains*/ + RSI_PS_M4ssRamBanksPeriPowerDown(rams_to_be_powered_down); + + /* Clear all RAM retention control before configuring the user RAM retentions*/ + RSI_PS_ClrRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN); + + /* If user selects the default RAM retentions, then select the RAM retentions based on RAM power gates*/ + if (rams_retention_during_sleep & WISEMCU_RETAIN_DEFAULT_RAM_DURING_SLEEP) { + /* If none of the banks are powered on, clear all retention controls*/ + if (rams_in_use & WISEMCU_0KB_RAM_IN_USE) { + RSI_PS_ClrRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | TA_RAM_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN); + } + /* Set the 16KB SRAM memory retention */ + if (rams_in_use == WISEMCU_16KB_RAM_IN_USE) { + RSI_PS_SetRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN); + } + /* Set the full SRAM memory retention if the SRAM memory usage is greater than 16KB */ + /* For different SRAM retention modes, respective unused SRAM banks (both SRAM power and core/periphery domains) are powered down as part of the initial configuration above */ + else { + RSI_PS_SetRamRetention(M4ULP_RAM16K_RETENTION_MODE_EN | M4ULP_RAM_RETENTION_MODE_EN); + } + } else { + /* Program user configuration*/ + RSI_PS_SetRamRetention(rams_retention_during_sleep); + } +} + +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c new file mode 100644 index 000000000..5640b342c --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c @@ -0,0 +1,208 @@ +/***************************************************************************/ /** + * @file sl_si91x_bus.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_status.h" +#include "sl_si91x_types.h" +#include "system_si91x.h" +#include "rsi_m4.h" +#include "sl_constants.h" +#include "cmsis_os2.h" +#include "rsi_power_save.h" +#include "sl_si91x_host_interface.h" +#include +#include +#include "sl_rsi_utility.h" + +rsi_m4ta_desc_t tx_desc[2]; +rsi_m4ta_desc_t rx_desc[2]; +sl_si91x_buffer_queue_t sli_ahb_bus_rx_queue; + +/****************************************************** + * * Function Declarations + * ******************************************************/ +sl_status_t sli_si91x_submit_rx_pkt(void); +void sli_submit_rx_buffer(void); +void sli_si91x_raise_pkt_pending_interrupt_to_ta(void); + +sl_status_t sl_si91x_bus_init(void) +{ + sli_ahb_bus_rx_queue.head = NULL; + sli_ahb_bus_rx_queue.tail = NULL; + mask_ta_interrupt(TA_RSI_BUFFER_FULL_CLEAR_EVENT); + return RSI_SUCCESS; +} + +/** + * @fn sl_status_t sli_si91x_submit_rx_pkt(void) + * @brief Submit receiver packets + * @param[in] None + * @return 0 - Success \n + * Non-Zero - Failure + */ +sl_wifi_buffer_t *rx_pkt_buffer; +sl_status_t sli_si91x_submit_rx_pkt(void) +{ + sl_status_t status; + uint16_t data_length = 0; + sl_si91x_packet_t *packet; + int8_t *pkt_buffer = NULL; + + if (M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID) { + return -2; + } + + // Allocate packet to receive packet from module + status = sl_si91x_host_allocate_buffer(&rx_pkt_buffer, SL_WIFI_RX_FRAME_BUFFER, 1616, 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + + packet = sl_si91x_host_get_buffer_data(rx_pkt_buffer, 0, &data_length); + pkt_buffer = (int8_t *)&packet->desc[0]; + + // Fill source address in the TX descriptors + rx_desc[0].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)pkt_buffer); + + // Fill source address in the TX descriptors + rx_desc[0].length = 16; + + // Fill source address in the TX descriptors + rx_desc[1].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)(pkt_buffer + 16)); + + // Fill source address in the TX descriptors + rx_desc[1].length = 1600; + + raise_m4_to_ta_interrupt(RX_BUFFER_VALID); + + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_bus_read_frame(sl_wifi_buffer_t **buffer) +{ + sl_status_t status = sli_si91x_remove_from_queue(&sli_ahb_bus_rx_queue, buffer); + VERIFY_STATUS_AND_RETURN(status); + + return SL_STATUS_OK; +} + +/** + * @fn sl_status_t sl_si91x_bus_write_frame(sl_si91x_packet_t *packet, + * uint8_t *payloadparam, uint16_t size_param) + * @brief writing a command to the module. + * @param[in] payloadparam - pointer to the command payload parameter structure + * @param[in] size_param - size of the payload for the command + * @return 0 - Success \n + * Negative Value - Failure + */ + +sl_status_t sl_si91x_bus_write_frame(sl_si91x_packet_t *packet, const uint8_t *payloadparam, uint16_t size_param) +{ + + // Fill source address in the TX descriptors + tx_desc[0].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)&packet->desc[0]); + + // Fill source address in the TX descriptors + tx_desc[0].length = 16; + + // Fill source address in the TX descriptors + tx_desc[1].addr = (M4_MEMORY_OFFSET_ADDRESS + (uint32_t)payloadparam); + + // Fill source address in the TX descriptors + tx_desc[1].length = size_param; + + sli_si91x_raise_pkt_pending_interrupt_to_ta(); + + return SL_STATUS_OK; +} + +void sli_submit_rx_buffer(void) +{ + mask_ta_interrupt(RX_PKT_TRANSFER_DONE_INTERRUPT); + + //! submit to NWP submit packet + sli_si91x_submit_rx_pkt(); + + unmask_ta_interrupt(RX_PKT_TRANSFER_DONE_INTERRUPT); +} + +/** + * @fn void rsi_update_tx_dma_desc(uint8 skip_dma_valid) + * @brief This function updates the TX DMA descriptor address + * @param[in] skip_dma_valid + * @param[out] none + * @return none + * @section description + * This function updates the TX DMA descriptor address + * + * + */ + +void rsi_update_tx_dma_desc(uint8_t skip_dma_valid) +{ + if (!skip_dma_valid +#ifdef SLI_SI91X_MCU_COMMON_FLASH_MODE + && !(M4_ULP_SLP_STATUS_REG & MCU_ULP_WAKEUP) +#endif + ) { + while (M4_TX_DMA_DESC_REG & DMA_DESC_REG_VALID) + ; + } + M4_TX_DMA_DESC_REG = (uint32_t)&tx_desc; +} + +/*==============================================*/ +/** + * @fn void rsi_update_rx_dma_desc() + * @brief This function updates the RX DMA descriptor address + * @param[in] none + * @param[out] none + * @return none + * @section description + * This function updates the RX DMA descriptor address + * + * + */ +void rsi_update_rx_dma_desc(void) +{ + M4_RX_DMA_DESC_REG = (uint32_t)&rx_desc; +} + +void sli_si91x_config_m4_dma_desc_on_reset(void) +{ + + //! Wait for NWP to wakeup and should be in bootloader + while (!(P2P_STATUS_REG & TA_is_active)) + ; + SL_DEBUG_LOG("\r\nTA is in active state\r\n"); + //! TBD Need to address why soft reset expecting delay + osDelay(100); + //! Update M4 Tx and Rx DMA descriptors + M4_TX_DMA_DESC_REG = (uint32_t)&tx_desc; + M4_RX_DMA_DESC_REG = (uint32_t)&rx_desc; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c new file mode 100644 index 000000000..eff178d8b --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c @@ -0,0 +1,484 @@ +/***************************************************************************/ /** + * @file sli_siwx917_soc.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#include "system_si91x.h" +#include "rsi_error.h" +#include "rsi_ccp_common.h" +#include "sl_si91x_constants.h" +#include "rsi_ipmu.h" +#include "rsi_rom_clks.h" +#include "rsi_rom_ulpss_clk.h" +#include "rsi_m4.h" +#include "sl_si91x_status.h" +#include "sli_siwx917_timer.h" +#include "sli_siwx917_soc.h" +#include "sl_constants.h" +#include "rsi_temp_sensor.h" +#include "sl_si91x_host_interface.h" +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "cmsis_os2.h" +#endif + +#define RSI_HAL_MAX_WR_BUFF_LEN 4096 + +#define SI91X_INTERFACE_OUT_REGISTER (*(uint32_t *)(RSI_HOST_INTF_REG_OUT)) +#define SI91X_INTERFACE_IN_REGISTER (*(uint32_t *)(RSI_HOST_INTF_REG_IN)) +#define SI91X_INTERFACE_STATUS_REGISTER (*(uint32_t *)(RSI_HOST_INTF_STATUS_REG)) +#define SI91X_PING_BUFFER_ADDRESS_REGISTER (*(uint32_t *)(RSI_PING_BUFFER_ADDR)) +#define SI91X_PONG_BUFFER_ADDRESS_REGISTER (*(uint32_t *)(RSI_PONG_BUFFER_ADDR)) + +typedef struct { + uint8_t _[2048]; +} sli_si91x_pingpong_buffer_t; + +#define SI91X_PING_BUFFER ((sli_si91x_pingpong_buffer_t *)(0x19000)) +#define SI91X_PONG_BUFFER ((sli_si91x_pingpong_buffer_t *)(0x1A000)) + +/** + * @fn int16_t rsi_bl_select_option(uint8_t cmd) + * @brief Send firmware load request to module or update default configurations. + * @param[in] cmd - type of configuration to be saved \n + * BURN_NWP_FW - 0x42 \n + * LOAD_NWP_FW - 0x31 \n + * LOAD_DEFAULT_NWP_FW_ACTIVE_LOW - 0x71 \n + * @return 0 - Success \n + * Non-Zero Value - Failure \n + * -28 - Firmware Load or Upgrade timeout error \n + * -14 - Valid Firmware not present \n + * -15 - Invalid Option + * + */ +/// @private +int16_t rsi_bl_select_option(uint8_t cmd) +{ + uint16_t boot_cmd = 0; + int16_t retval = 0; + uint16_t read_value = 0; + sl_si91x_timer_t timer_instance; + + SI91X_INTERFACE_OUT_REGISTER = boot_cmd; + + if (cmd == BURN_NWP_FW) { + boot_cmd = RSI_HOST_INTERACT_REG_VALID_FW | cmd; + } else { + boot_cmd = RSI_HOST_INTERACT_REG_VALID | cmd; + } + retval = sli_si91x_send_boot_instruction(RSI_REG_WRITE, &boot_cmd); + if (retval < 0) { + return retval; + } + + sl_si91x_timer_init(&timer_instance, 300); + + while ((cmd != LOAD_NWP_FW) && (cmd != LOAD_DEFAULT_NWP_FW_ACTIVE_LOW)) { + retval = sli_si91x_send_boot_instruction(RSI_REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if (cmd == BURN_NWP_FW) { + if (read_value == (RSI_HOST_INTERACT_REG_VALID | RSI_SEND_RPS_FILE)) { + break; + } + } + + else if (read_value == (RSI_HOST_INTERACT_REG_VALID | cmd)) { + break; + } + if (sl_si91x_timer_expired(&timer_instance)) { + return RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT; + } + } + if ((cmd == LOAD_NWP_FW) || (cmd == LOAD_DEFAULT_NWP_FW_ACTIVE_LOW)) { + sl_si91x_timer_init(&timer_instance, 3000); + do { + retval = sli_si91x_send_boot_instruction(RSI_REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if ((read_value & 0xF000) == (RSI_HOST_INTERACT_REG_VALID_FW & 0xF000)) { + if ((read_value & 0xFF) == VALID_FIRMWARE_NOT_PRESENT) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL4, "VALID_FIRMWARE_NOT_PRESENT\n"); +#endif + return RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT; + } + if ((read_value & 0xFF) == RSI_INVALID_OPTION) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL4, "INVALID CMD\n"); +#endif + + return RSI_ERROR_INVALID_OPTION; + } + if ((read_value & 0xFF) == RSI_CHECKSUM_SUCCESS) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL4, "LOAD SUCCESS\n"); +#endif + break; + } + } + if (sl_si91x_timer_expired(&timer_instance)) { + return RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT; + } + + } while (1); + } + return retval; +} + +/** + * @fn int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data) + * @brief Send boot instructions to module. + * @param[in] type - type of the insruction to perform \n + * 0xD1 - RSI_REG_READ \n + * 0xD2 - RSI_REG_WRITE \n + * 0xD5 - RSI_PING_WRITE \n + * 0xD4 - RSI_PONG_WRITE \n + * 0x42 - BURN_NWP_FW \n + * 0x31 - LOAD_NWP_FW \n + * 0x71 - LOAD_DEFAULT_NWP_FW_ACTIVE_LOW + * @param[in] data - pointer to data which is to be read/write \n + * @return 0 - Success \n + * Non-Zero Value - Failure \n + * -28 - Firmware Load or Upgrade timeout error \n + * -2 - Invalid Parameter \n + * -1 or -2 - SPI Failure + * @note This is a proprietry API and it is not recommended to be used by the user directly. + */ +/// @private +int16_t sli_si91x_send_boot_instruction(uint8_t type, uint16_t *data) +{ + int16_t retval = 0; + uint32_t cmd = 0; + uint16_t read_data = 0; + sl_si91x_timer_t timer_instance; + + switch (type) { + case RSI_REG_READ: + *data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; + break; + + case RSI_REG_WRITE: + SI91X_INTERFACE_IN_REGISTER = *data; + break; + + case BURN_NWP_FW: + cmd = BURN_NWP_FW | RSI_HOST_INTERACT_REG_VALID; + + SI91X_INTERFACE_IN_REGISTER = cmd; + + sl_si91x_timer_init(&timer_instance, 300); + + do { + read_data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; + if (sl_si91x_timer_expired(&timer_instance)) { + return RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT; + } + } while (read_data != (RSI_SEND_RPS_FILE | RSI_HOST_INTERACT_REG_VALID)); + break; + + case LOAD_NWP_FW: + SI91X_INTERFACE_IN_REGISTER = LOAD_NWP_FW | RSI_HOST_INTERACT_REG_VALID; + break; + + case LOAD_DEFAULT_NWP_FW_ACTIVE_LOW: + SI91X_INTERFACE_IN_REGISTER = LOAD_DEFAULT_NWP_FW_ACTIVE_LOW | RSI_HOST_INTERACT_REG_VALID; + break; + + default: + retval = RSI_ERROR_INVALID_PARAM; + break; + } + return retval; +} + +/** + * @fn int16 rsi_waitfor_boardready(void) + * @brief Waits to receive board ready from WiFi module + * @param[in] none + * @param[out] none + * @return errCode + * 0 = SUCCESS + * < 0 = Failure + * -7 = Error in OS operation + * -9 = Bootup options last configuration not saved + * -10 = Bootup options checksum failed + * -11 = Bootloader version mismatch + * -12 = Board ready not received + * @section description + * This API is used to check board ready from WiFi module. + */ +int16_t rsi_waitfor_boardready(void) +{ + int16_t retval = 0; + uint16_t read_value = 0; + + retval = rsi_boot_insn(REG_READ, &read_value); + + if (retval < 0) { + return retval; + } + if (read_value == 0) { + return RSI_ERROR_IN_OS_OPERATION; + } + if ((read_value & 0xFF00) == (HOST_INTERACT_REG_VALID_READ & 0xFF00)) { + if ((read_value & 0xFF) == RSI_BOOTUP_OPTIONS_LAST_CONFIG_NOT_SAVED) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTUP OPTIOINS LAST CONFIGURATION NOT SAVED\n"); +#endif + return RSI_ERROR_BOOTUP_OPTIONS_NOT_SAVED; + } else if ((read_value & 0xFF) == RSI_BOOTUP_OPTIONS_CHECKSUM_FAIL) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTUP OPTIONS CHECKSUM FAIL\n"); +#endif + return RSI_ERROR_BOOTUP_OPTIONS_CHECKSUM_FAIL; + } +#if defined(BOOTLOADER_VERSION_CHECK) && (BOOTLOADER_VERSION_CHECK == 1) + else if ((read_value & 0xFF) == BOOTLOADER_VERSION) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTLOADER VERSION CORRECT\n"); +#endif + } else { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "BOOTLOADER VERSION NOT MATCHING\n"); +#endif + + return RSI_ERROR_BOOTLOADER_VERSION_NOT_MATCHING; + } +#endif + +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "RECIEVED BOARD READY\n"); +#endif + return RSI_ERROR_NONE; + } + +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "WAITING FOR BOARD READY\n"); +#endif + return RSI_ERROR_WAITING_FOR_BOARD_READY; +} + +/** + * @fn int16 rsi_select_option(uint8 cmd) + * @brief Sends cmd to select option to load or update configuration + * @param[in] uint8 cmd, type of configuration to be saved + * @param[out] none + * @return errCode + < 0 = Command issue failed + * 0 = SUCCESS + * @section description + * This API is used to send firmware load request to WiFi module or update default configurations. + */ +int16_t rsi_select_option(uint8_t cmd) +{ + uint16_t boot_cmd = 0; + int16_t retval = 0; + uint16_t read_value = 0; + uint8_t image_number = 0; + volatile int32_t loop_counter = 0; + + boot_cmd = HOST_INTERACT_REG_VALID | cmd; + if (cmd == CHECK_NWP_INTEGRITY) { + boot_cmd &= 0xF0FF; + boot_cmd = boot_cmd | (uint16_t)(image_number << 8); + } + retval = rsi_boot_insn(REG_WRITE, &boot_cmd); + if (retval < 0) { + return retval; + } + + if ((cmd != LOAD_NWP_FW) && (cmd != LOAD_DEFAULT_NWP_FW_ACTIVE_LOW) && (cmd != RSI_JUMP_TO_PC)) { + RSI_RESET_LOOP_COUNTER(loop_counter); + RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_SELECT_OPTION) + { + retval = rsi_boot_insn(REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if (cmd == CHECK_NWP_INTEGRITY) { + if ((read_value & 0xFF) == RSI_CHECKSUM_SUCCESS) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "CHECKSUM SUCCESS\n"); +#endif + } else if (read_value == RSI_CHECKSUM_FAILURE) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "CHECKSUM FAIL\n"); +#endif + } else if (read_value == RSI_CHECKSUM_INVALID_ADDRESS) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "Invalid Address \n"); +#endif + } + } + if (read_value == (HOST_INTERACT_REG_VALID | cmd)) { + break; + } + } + RSI_CHECK_LOOP_COUNTER(loop_counter, RSI_LOOP_COUNT_SELECT_OPTION); + } else if ((cmd == LOAD_NWP_FW) || (cmd == LOAD_DEFAULT_NWP_FW_ACTIVE_LOW) || (cmd == RSI_JUMP_TO_PC)) { + retval = rsi_boot_insn(REG_READ, &read_value); + if (retval < 0) { + return retval; + } + if ((read_value & 0xFF) == VALID_FIRMWARE_NOT_PRESENT) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "VALID_FIRMWARE_NOT_PRESENT\n"); +#endif + return RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT; + } + if ((read_value & 0xFF) == RSI_INVALID_OPTION) { +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "INVALID CMD\n"); +#endif + return RSI_ERROR_COMMAND_NOT_SUPPORTED; + } + } + return retval; +} + +/** + * @fn int16 rsi_boot_insn(uint8 type, uint16 *data) + * @brief Sends boot instructions to WiFi module + * @param[in] uint8 type, type of the insruction to perform + * @param[in] uint32 *data, pointer to data which is to be read/write + * @param[out] none + * @return errCode + * < 0 = Command issued failure/Invalid command + * 0 = SUCCESS + * > 0 = Read value + * @section description + * This API is used to send boot instructions to WiFi module. + */ + +int16_t rsi_boot_insn(uint8_t type, uint16_t *data) +{ + int16_t retval = 0; + uint16_t read_data = 0; + volatile int32_t loop_counter = 0; +#ifdef RSI_DEBUG_PRINT + RSI_DPRINT(RSI_PL3, "\nBootInsn\n"); +#endif + + switch (type) { + case REG_READ: + *data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; + break; + + case REG_WRITE: + SI91X_INTERFACE_IN_REGISTER = *data; + break; + + case PING_WRITE: + memcpy(SI91X_PING_BUFFER, data, sizeof(sli_si91x_pingpong_buffer_t)); + SI91X_INTERFACE_IN_REGISTER = 0xab49; + break; + + case PONG_WRITE: + memcpy(SI91X_PONG_BUFFER, data, sizeof(sli_si91x_pingpong_buffer_t)); + SI91X_INTERFACE_IN_REGISTER = 0xab4f; + break; + + case BURN_NWP_FW: + SI91X_INTERFACE_IN_REGISTER = BURN_NWP_FW | HOST_INTERACT_REG_VALID; + + RSI_RESET_LOOP_COUNTER(loop_counter); + RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE) + { + read_data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; + if (read_data == (RSI_SEND_RPS_FILE | HOST_INTERACT_REG_VALID)) { + break; + } + } + RSI_CHECK_LOOP_COUNTER(loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE); + break; + + case LOAD_NWP_FW: + SI91X_INTERFACE_IN_REGISTER = LOAD_NWP_FW | HOST_INTERACT_REG_VALID; + break; + case LOAD_DEFAULT_NWP_FW_ACTIVE_LOW: + SI91X_INTERFACE_IN_REGISTER = LOAD_DEFAULT_NWP_FW_ACTIVE_LOW | HOST_INTERACT_REG_VALID; + break; + case RSI_UPGRADE_BL: + SI91X_INTERFACE_IN_REGISTER = RSI_UPGRADE_BL | HOST_INTERACT_REG_VALID; + RSI_RESET_LOOP_COUNTER(loop_counter); + RSI_WHILE_LOOP((uint32_t)loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE) + { + read_data = (uint16_t)SI91X_INTERFACE_OUT_REGISTER; + if (read_data == (RSI_SEND_RPS_FILE | HOST_INTERACT_REG_VALID)) { + break; + } + } + RSI_CHECK_LOOP_COUNTER(loop_counter, RSI_LOOP_COUNT_UPGRADE_IMAGE); + break; + default: + retval = -2; + break; + } + return retval; +} + +void unmask_ta_interrupt(uint32_t interrupt_no) +{ + TASS_P2P_INTR_MASK_CLR = interrupt_no; +} + +void sli_m4_ta_interrupt_init(void) +{ +#if defined(SLI_SI917) || defined(SLI_SI915) + //! Unmask the interrupt + unmask_ta_interrupt(TX_PKT_TRANSFER_DONE_INTERRUPT | RX_PKT_TRANSFER_DONE_INTERRUPT | TA_WRITING_ON_COMM_FLASH + | NWP_DEINIT_IN_COMM_FLASH +#ifdef SLI_SI91X_MCU_FW_UPGRADE_OTA_DUAL_FLASH + | M4_IMAGE_UPGRADATION_PENDING_INTERRUPT +#endif +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + | SIDE_BAND_CRYPTO_DONE +#endif + ); +#else + //! Unmask the interrupt + unmask_ta_interrupt(TX_PKT_TRANSFER_DONE_INTERRUPT | RX_PKT_TRANSFER_DONE_INTERRUPT); +#endif + P2P_STATUS_REG |= M4_is_active; + + *(volatile uint32_t *)0xE000E108 = 0x00000400; + + //! Set P2P Intr priority + NVIC_SetPriority(TASS_P2P_IRQn, TASS_P2P_INTR_PRI); + + return; +} + +void sl_si91x_ulp_wakeup_init(void) +{ + // for compilation +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h new file mode 100644 index 000000000..c6b1134a2 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/inc/sl_si91x_socket.h @@ -0,0 +1,513 @@ +/***************************************************************************/ /** + * @file sl_si91x_socket.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once +#include "sl_si91x_socket_types.h" + +/** + * @addtogroup SI91X_SOCKET_FUNCTIONS + * @{ + */ +/** + * @brief Creates a new socket. + * + * @details + * The function creates a new socket and returns a file descriptor for the respective socket. + * The socket is used for communication within the specified protocol family, + * type, and protocol. The created socket is used for various network operations + * such as, connecting to a remote host, sending and receiving data, and so on. + * + * @param[in] family + * Specifies the communication domain for the socket. This selects the protocol family to be used. + * Accepts values from @ref BSD_SOCKET_FAMILIY. Currently, only @ref AF_INET and @ref AF_INET6 are supported. + * + * @param[in] type + * Specifies the type of the socket, which determines the semantics of communication. + * Accepts values from @ref BSD_SOCKET_TYPES. Currently, only @ref SOCK_STREAM and @ref SOCK_DGRAM are supported. + * + * @param[in] protocol + * Specifies a particular protocol to be used with the socket. + * Accepts values from @ref BSD_SOCKET_PROTOCOL. Currently, only @ref IPPROTO_TCP, @ref IPPROTO_UDP, and @ref IPPROTO_IP are supported. + * + * @return + * Returns the socket ID or file descriptor for the newly created socket on success, or -1 on failure. + */ +int sl_si91x_socket(int family, int type, int protocol); + +/** + * @brief Creates an asynchronous socket and registers the provided callback. + * + * @details + * This function creates a new asynchronous socket and registers a callback function + * that is called whenever data is received on the socket. The socket can be used + * for communication within the specified protocol family, type, and protocol. + * + * @param[in] family Specifies the communication domain for the socket. This selects the protocol family to be used. + * Accepts values from @ref BSD_SOCKET_FAMILIY. Currently, only @ref AF_INET and @ref AF_INET6 are supported. + * + * @param[in] type Specifies the type of the socket, which determines the semantics of communication. + * Accepts values from @ref BSD_SOCKET_TYPES. Currently, only @ref SOCK_STREAM and @ref SOCK_DGRAM are supported. + * + * @param[in] protocol Specifies a particular protocol to be used with the socket. + * Accepts values from @ref BSD_SOCKET_PROTOCOL. Currently, only @ref IPPROTO_TCP, @ref IPPROTO_UDP, and @ref IPPROTO_IP are supported. + * + * @param[in] callback A function pointer of type @ref sl_si91x_socket_receive_data_callback_t. This function is called when the socket receives data. + * + * @return Returns the socket ID or file descriptor for the newly created socket on success, or -1 on failure. + */ +int sl_si91x_socket_async(int family, int type, int protocol, sl_si91x_socket_receive_data_callback_t callback); + +/** + * @brief Sets a specified socket option on the identified socket asynchronously. + * + * @details + * This function sets a specified option for a given socket asynchronously. The options + * can be set at various levels and include parameters such as receive timeout, maximum + * retries, maximum segment size, TCP keepalive, SSL options, and so on. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * + * @param[in] level + * The option level. Accepts values from @ref BSD_SOCKET_OPTION_LEVEL. + * + * @param[in] option_name + * The option to be configured. Accepts values from @ref SI91X_SOCKET_OPTION_NAME. + * Currently, following options are supported: + * - @ref SL_SI91X_SO_RCVTIME + * - @ref SL_SI91X_SO_MAXRETRY + * - @ref SL_SI91X_SO_MSS + * - @ref SL_SI91X_SO_TCP_KEEPALIVE + * - @ref SL_SI91X_SO_HIGH_PERFORMANCE_SOCKET + * - @ref SL_SI91X_SO_SSL_ENABLE + * - @ref SL_SI91X_SO_SSL_V_1_0_ENABLE + * - @ref SL_SI91X_SO_SSL_V_1_1_ENABLE + * - @ref SL_SI91X_SO_SSL_V_1_2_ENABLE + * - @ref SL_SI91X_SO_SOCK_VAP_ID + * - @ref SL_SI91X_SO_SSL_V_1_3_ENABLE + * - @ref SL_SI91X_SO_CERT_INDEX + * - @ref SL_SI91X_SO_TLS_SNI + * - @ref SL_SI91X_SO_TLS_ALPN + * - @ref SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE + * + * @param[in] option_value + * The value of the parameter. + * | option_name | option_value | description | + * |---------------------------------------------------|--------------------------------------|----------------------------------------------------------------------------------------------------------------------------| + * | @ref SL_SI91X_SO_RCVTIME | sl_si91x_time_value | Socket Receive timeout. sl_si91x_time_value structure is used to represent time in two parts: seconds and microseconds. | + * | @ref SL_SI91X_SO_MAXRETRY | uint16_t | Maximum number of TCP retries | + * | @ref SL_SI91X_SO_MSS | uint16_t | Maximum Segment Size (MSS) for the TCP connection | + * | @ref SL_SI91X_SO_TCP_KEEPALIVE | uint16_t | Set TCP keepalive in seconds | + * | @ref SL_SI91X_SO_HIGH_PERFORMANCE_SOCKET | BIT(7) | Set high performance socket | + * | @ref SL_SI91X_SO_SSL_ENABLE | SL_SI91X_ENABLE_TLS | Enable TLS/SSL | + * | @ref SL_SI91X_SO_SSL_V_1_0_ENABLE | SL_SI91X_TLS_V_1_0 | Enable TLS v1.0 | + * | @ref SL_SI91X_SO_SSL_V_1_1_ENABLE | SL_SI91X_TLS_V_1_1 | Enable TLS v1.1 | + * | @ref SL_SI91X_SO_SSL_V_1_2_ENABLE | SL_SI91X_TLS_V_1_2 | Enable TLS v1.2 | + * | @ref SL_SI91X_SO_SSL_V_1_3_ENABLE | SL_SI91X_TLS_V_1_3 | Enable TLS v1.3 | + * | @ref SL_SI91X_SO_SOCK_VAP_ID | uint8_t | Specifies the interface on which the socket will operate | + * | @ref SL_SI91X_SO_CERT_INDEX | uint8_t | Certificate index | + * | @ref SL_SI91X_SO_TLS_SNI | sl_si91x_socket_type_length_value_t | Server Name Indication (SNI) | + * | @ref SL_SI91X_SO_TLS_ALPN | sl_si91x_socket_type_length_value_t | Application-Layer Protocol Negotiation (ALPN) | + * | @ref SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE | uint8_t | Maximum retransmission timeout value for TCP | + * + * @param[in] option_len + * The length of the parameter of type @ref socklen_t. + * + * @return + * Returns 0 on success, or -1 on failure. + * + * @note + * This function is used only for the SiWx91x socket API. + * The options set in this function will not be effective if called after `sl_si91x_connect()` or `sl_si91x_listen()` for TCP, or after `sl_si91x_sendto()`, `sl_si91x_recvfrom()`, or `sl_si91x_connect()` for UDP. + * The value of the option SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE should be a power of 2. + */ +int sl_si91x_setsockopt(int32_t socket, int level, int option_name, const void *option_value, socklen_t option_len); + +/** + * @brief Assigns a local protocol address to a socket. + * + * @details + * The function binds a socket to a specific local address and port number. + * It is typically used on the server side to specify the port on which the server + * will listen for incoming connections. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * + * @param[in] addr + * Pointer to a `struct sockaddr` contains the address to which the socket is bound. + * This address specifies the local IP address and port number. + * + * @param[in] addr_len + * The length of the socket address, in bytes, of type `socklen_t`. + * + * @return + * Returns 0 on success, or -1 on failure. + */ +int sl_si91x_bind(int socket, const struct sockaddr *addr, socklen_t addr_len); + +/** + * @brief Enables a socket to listen for remote connection requests in passive mode. + * + * @details + * The function configures a socket to listen for incoming connection requests. + * It is typically used on the server side after the socket has been bound to a local + * address using the `sl_si91x_bind` function. The socket enters passive mode, + * where it waits for remote clients to connect. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * + * @param[in] max_number_of_clients + * The maximum number of pending connections which the socket can queue. + * + * @return + * Returns 0 on success, or -1 on failure. + */ +int sl_si91x_listen(int socket, int max_number_of_clients); + +/** + * @brief Accepts a connection request from a remote peer. + * + * @details + * The function blocks until a client attempts to connect to the server socket. After receiving a connection request, it proceeds. + * + * @param[in] socket The socket ID or file descriptor for the specified socket. + * @param[in] addr The address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] addr_len The length of the socket address of type @ref socklen_t in bytes. + * @return int + */ +int sl_si91x_accept(int socket, const struct sockaddr *addr, socklen_t addr_len); + +/** + * @brief + * Accepts a connection request from the remote peer and registers a callback. + * + * @details + * The function sets up the server socket to listen for incoming connections, + * and immediately returns without blocking the main program's execution. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * @param[in] callback + * A function pointer of type @ref sl_si91x_socket_accept_callback_t that is called when a new client is connected to the server. + * @return int + */ +int sl_si91x_accept_async(int socket, sl_si91x_socket_accept_callback_t callback); + +/** + * @brief + * Initiates a connection to a remote socket specified by the addr parameter. + * + * @details + * The function initiates a connection to a remote socket specified by the `addr` parameter. + * It is typically used on the client side to establish a connection to a server. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * @param[in] addr + * Address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] addr_len + * Length of the socket address of type @ref socklen_t in bytes. + * @return int + */ +int sl_si91x_connect(int socket, const struct sockaddr *addr, socklen_t addr_len); + +/** + * @brief + * Sends the data to the remote peer on the given socket. + * + * @details + * This should be used only when the socket is in a connected state. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * @param[in] buffer + * Pointer to the buffer containing data to send to the remote peer. + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_send(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags); + +/** + * @brief + * Transmits one or more messages to a socket asynchronously. + * + * @details + * This should be used only when the socket is in a connected state. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * @param[in] buffer + * Pointer to the buffer containing data to send to the remote peer + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @param[in] callback + * A function pointer of type @ref sl_si91x_socket_data_transfer_complete_handler_t that is called after complete data transfer. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_send_async(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + sl_si91x_socket_data_transfer_complete_handler_t callback); + +/** + * @brief + * Transmits one or more messages to another socket. + * + * @details + * The function is called from an unconnected socket, typically like a UDP socket. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * @param[in] buffer + * Pointer to data buffer contains data to send to remote peer. + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @param[in] addr + * Address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] addr_len + * Length of the socket address of type @ref socklen_t in bytes. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_sendto(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *addr, + socklen_t addr_len); + +/** + * @brief + * Transmits one or more messages to another socket asynchronously, and receives acknowledgement through the registered callback. + * + * @details + * The function can also be called from an unconnected socket, typically like a UDP socket. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * @param[in] buffer + * Pointer to data buffer contains data to send to remote peer. + * @param[in] buffer_length + * Length of the buffer pointed to by the buffer parameter. + * @param[in] flags + * Controls the transmission of the data. + * @param[in] to_addr + * Address of type @ref sockaddr to which datagrams are to be sent. + * @param[in] to_addr_len + * Length of the socket address of type @ref socklen_t in bytes. + * @param[in] callback + * A function pointer of type @ref sl_si91x_socket_data_transfer_complete_handler_t that is called after complete data transfer. + * @return int + * @note The flags parameter is not currently supported. + */ +int sl_si91x_sendto_async(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *to_addr, + socklen_t to_addr_len, + sl_si91x_socket_data_transfer_complete_handler_t callback); + +/** + * @brief Sends data that is larger than the Maximum Segment Size (MSS). + * + * @details + * This function sends data that exceeds the MSS size to a remote peer. It handles + * the segmentation of the data into smaller chunks that fit within the MSS limit. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * + * @param[in] buffer + * Pointer to the data buffer contains the data to be sent to the remote peer. + * + * @param[in] buffer_length + * The length of the buffer pointed to by the buffer parameter. + * + * @param[in] flags + * Controls the transmission of the data. Note that the flags parameter is not currently supported. + * + * @return + * Returns the number of bytes sent on success, or -1 on failure. + */ +int sl_si91x_send_large_data(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags); + +/** + * @brief Receives data from a connected socket. + * + * @details + * This function receives data from a connected socket and stores it in the specified buffer. + * It is typically used on the client or server side to read incoming data from a remote peer. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * + * @param[out] buffer + * Pointer to the buffer holds the data received from the remote peer. + * + * @param[in] bufferLength + * The length of the buffer pointed to by the buffer parameter. + * + * @param[in] flags + * Controls the reception of the data. Note that the flags parameter are not currently supported. + * + * @return + * Returns the number of bytes received on success, or -1 on failure. + */ +int sl_si91x_recv(int socket, uint8_t *buffer, size_t bufferLength, int32_t flags); + +/** + * @brief Receives data from an unconnected socket, typically a UDP socket. + * + * @details + * This function receives data from an unconnected socket and stores it in the specified buffer. + * It is typically used to receive data from a remote peer without establishing a connection. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket. + * + * @param[out] buffer + * Pointer to the buffer that will hold the data received from the remote peer. + * + * @param[in] buffersize + * The size of the buffer pointed to by the buffer parameter. + * + * @param[in] flags + * Controls the reception of the data. Note that the flags parameter is not currently supported. + * + * @param[out] fromAddr + * Pointer to a @ref sockaddr that will hold the address of the remote peer from which the current packet was received. + * + * @param[in, out] fromAddrLen + * Pointer to a @ref socklen_t that contains the length of the remote peer address (fromAddr). + * On return, it will contain the actual length of the address. + * + * @return + * Returns the number of bytes received on success, or -1 on failure. + */ +int sl_si91x_recvfrom(int socket, + uint8_t *buffer, + size_t buffersize, + int32_t flags, + struct sockaddr *fromAddr, + socklen_t *fromAddrLen); + +/** + * @brief Disables send or receive operations on a socket. + * + * @details + * This function disables further send or receive operations on a specified socket. + * It can either close a specific socket or all sockets associated with a given port number. + * + * @param[in] socket + * The socket ID or file descriptor for the specified socket that is to be closed. + * + * @param[in] how + * Determines the scope of the shutdown operation: + * - 0: Close the specified socket. + * - 1: Close all sockets open on the specified socket's source port number. + * + * @return + * Returns 0 on success, or -1 on failure. + * + * @note + * If the socket is a server socket, the `how` parameter is ignored, and the socket is always closed based on the port number. + */ +int sl_si91x_shutdown(int socket, int how); + +/** + * @brief + * The sl_si91x_select() function is used to monitor multiple file descriptors for readiness to + * perform I/O operations. The file descriptors in the sets are monitored to + * see if they are ready for reading, ready for writing, or have an error + * condition pending. + * @details + * sl_si91x_select() allows a program to monitor multiple file descriptors, + * waiting until one or more of the file descriptors become "ready" + * for some class of I/O operation (e.g., input possible). A file + * descriptor is considered ready if it is possible to perform a + * corresponding I/O operation without blocking. + * + * @param[in] nfds + * The first nfds descriptors are checked in each set; that is, the descriptors from 0 through nfds-1. + * @param[in,out] readfds + * A pointer to a fd_set object that specifies the descriptors to check for files that are ready for reading. + * @param[in,out] writefds + * A pointer to a fd_set object that specifies the descriptors to check for files that are ready for writing. + * @param[in,out] exceptfds + * A pointer to a fd_set object that will be watched for exceptions. + * @param[in] timeout + * If timeout is provided, the device shall wait for timeout duration for the file descriptors to become ready. + * If timeout is NULL, the device shall wait indefinitely for the file descriptors to become ready. + * @param[in] callback + * A function pointer of type @ref sl_si91x_socket_select_callback_t that will be called when an asynchronous response is received for a select request. + * @return + * If callback is provided, the function will immediately return zero for success, and -1 for failure. + * If callback is NULL, returns: + * - total number of file descriptors set on success. + * - 0 when no file descriptors are ready within the specified timeout. + * - -1 on failure. + * + * @note + * The select function modifies the sets passed to it, so if the function + * is to be called again, the sets must be reinitialized. + * The exceptfds parameter is not currently supported. + */ +int sl_si91x_select(int nfds, + sl_si91x_fd_set *readfds, + sl_si91x_fd_set *writefds, + sl_si91x_fd_set *exceptfds, + const struct timeval *timeout, + sl_si91x_socket_select_callback_t callback); + + +/** + * @brief Registers a callback for remote socket termination events. + * + * @details + * This function registers a callback function is called when a remote socket is terminated. + * The callback function should be of type @ref sl_si91x_socket_remote_termination_callback_t. + * + * @param[in] callback + * A valid function pointer of type @ref sl_si91x_socket_remote_termination_callback_t that is called when the remote socket is terminated. + */ +void sl_si91x_set_remote_termination_callback(sl_si91x_socket_remote_termination_callback_t callback); +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c new file mode 100644 index 000000000..18bdf4a11 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c @@ -0,0 +1,572 @@ +/***************************************************************************/ /** + * @file sl_si91x_socket.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_socket_utility.h" +#include "sl_status.h" +#include "sl_constants.h" +#include "sl_si91x_socket.h" +#include "sl_si91x_socket_callback_framework.h" +#include "sl_si91x_socket_types.h" +#include "sl_si91x_socket_constants.h" +#include "sl_si91x_protocol_types.h" +#include "sl_rsi_utility.h" +#include "sl_si91x_driver.h" +#include +#include + +/****************************************************** + * Macros + ******************************************************/ +#define TCP_HEADER_LENGTH 56 +#define UDP_HEADER_LENGTH 44 +#define TCP_V6_HEADER_LENGTH 76 +#define UDP_V6_HEADER_LENGTH 64 +#define SI91X_SSL_HEADER_SIZE_IPV4 90 +#define SI91X_SSL_HEADER_SIZE_IPV6 110 + +void sl_si91x_set_remote_termination_callback(sl_si91x_socket_remote_termination_callback_t callback) +{ + sli_si91x_set_remote_socket_termination_callback(callback); +} + +// Create a new socket +int sl_si91x_socket(int family, int type, int protocol) +{ + return sli_si91x_socket(family, type, protocol, NULL); +} + +int sl_si91x_socket_async(int family, int type, int protocol, sl_si91x_socket_receive_data_callback_t callback) +{ + SET_ERRNO_AND_RETURN_IF_TRUE(NULL == callback, 0); + + return sli_si91x_socket(family, type, protocol, callback); +} + +int sl_si91x_bind(int socket, const struct sockaddr *addr, socklen_t addr_len) +{ + return sli_si91x_bind(socket, addr, addr_len); +} + +int sl_si91x_connect(int socket, const struct sockaddr *addr, socklen_t addr_len) +{ + return sli_si91x_connect(socket, addr, addr_len); +} + +int sl_si91x_listen(int socket, int max_number_of_clients) +{ + int32_t status; + sli_si91x_socket_t *si91x_socket = get_si91x_socket(socket); + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != INITIALIZED && si91x_socket->state != BOUND, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type != SOCK_STREAM, EOPNOTSUPP); + + // Create and send a socket request to make it a TCP server with the specified maximum number of clients + status = create_and_send_socket_request(socket, SI91X_SOCKET_TCP_SERVER, &max_number_of_clients); + SOCKET_VERIFY_STATUS_AND_RETURN(status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); + + si91x_socket->state = LISTEN; + + return SI91X_NO_ERROR; +} + +int sl_si91x_accept(int socket, const struct sockaddr *addr, socklen_t addr_len) +{ + return sli_si91x_accept(socket, (struct sockaddr *)addr, &addr_len, NULL); +} + +int sl_si91x_shutdown(int socket, int how) +{ + return sli_si91x_shutdown(socket, how); +} + +int sl_si91x_accept_async(int socket, sl_si91x_socket_accept_callback_t callback) +{ + return sli_si91x_accept(socket, NULL, 0, callback); +} + +int sl_si91x_setsockopt(int32_t sockID, int level, int option_name, const void *option_value, socklen_t option_len) +{ + UNUSED_PARAMETER(level); + + // Retrieve the socket using the socket index + sli_si91x_socket_t *si91x_socket = get_si91x_socket(sockID); + sl_si91x_time_value *timeout = NULL; + uint16_t timeout_val; + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + + // Check if the option value is not NULL + SET_ERRNO_AND_RETURN_IF_TRUE(option_value == NULL, EFAULT); + + switch (option_name) { + case SL_SI91X_SO_RCVTIME: { + // Configure receive timeout + timeout = (sl_si91x_time_value *)option_value; + + // Ensure that the timeout value is at least 1 millisecond + if ((timeout->tv_sec == 0) && (timeout->tv_usec != 0) && (timeout->tv_usec < 1000)) { + timeout->tv_usec = 1000; + } + // Calculate the timeout value in milliseconds + timeout_val = (uint16_t)((timeout->tv_usec / 1000) + (timeout->tv_sec * 1000)); + + // Need to add check here if Synchronous bit map is set (after async socket_id implementation) + memcpy(&si91x_socket->read_timeout, + &timeout_val, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->read_timeout), option_len)); + break; + } + + case SL_SI91X_SO_MAXRETRY: { + // Set the maximum number of TCP retries + memcpy(&si91x_socket->max_tcp_retries, + (const uint16_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->max_tcp_retries), option_len)); + break; + } + + case SL_SI91X_SO_MSS: { + memcpy(&si91x_socket->mss, + (const uint16_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->mss), option_len)); + break; + } + + case SL_SI91X_SO_TCP_KEEPALIVE: { + // Set the TCP keep-alive initial time + memcpy(&si91x_socket->tcp_keepalive_initial_time, + (const uint16_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->tcp_keepalive_initial_time), option_len)); + break; + } + case SL_SI91X_SO_HIGH_PERFORMANCE_SOCKET: { + // Enable high-performance socket mode + SET_ERRNO_AND_RETURN_IF_TRUE(*(uint8_t *)option_value != SI91X_HIGH_PERFORMANCE_SOCKET, EINVAL); + si91x_socket->ssl_bitmap |= SI91X_HIGH_PERFORMANCE_SOCKET; + break; + } + + case SL_SI91X_SO_SSL_ENABLE: { + // Enable SSL for the socket + SET_ERRNO_AND_RETURN_IF_TRUE((*(uint8_t *)option_value) != SI91X_SOCKET_FEAT_SSL, EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL; + break; + } + case SL_SI91X_SO_SSL_V_1_0_ENABLE: { + // Enable SSL version 1.0 for the socket + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_0)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_0; + break; + } + case SL_SI91X_SO_SSL_V_1_1_ENABLE: { + // Enable SSL version 1.1 for the socket + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_1)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_1; + break; + } + case SL_SI91X_SO_SSL_V_1_2_ENABLE: { + // Enable SSL version 1.2 for the socket + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_2)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_2; + break; + } + + case SL_SI91X_SO_SOCK_VAP_ID: { + // Set the VAP ID for the socket + si91x_socket->vap_id = *((const uint8_t *)option_value); + break; + } + + case SL_SI91x_SO_TCP_ACK_INDICATION: { + // Enable TCP_ACK_INDICATION + SET_ERRNO_AND_RETURN_IF_TRUE((*(uint8_t *)option_value) != SI91X_SOCKET_FEAT_TCP_ACK_INDICATION, EINVAL); + si91x_socket->socket_bitmap |= SI91X_SOCKET_FEAT_TCP_ACK_INDICATION; + break; + } +#if defined(SLI_SI917) || defined(SLI_SI915) + case SL_SI91X_SO_SSL_V_1_3_ENABLE: { + // Enable SSL version 1.3 for the socket. + SET_ERRNO_AND_RETURN_IF_TRUE(((*(uint8_t *)option_value) != (SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_3)), + EINVAL); + si91x_socket->ssl_bitmap |= SI91X_SOCKET_FEAT_SSL | SL_SI91X_TLS_V_1_3; + break; + } +#endif + + case SL_SI91X_SO_CERT_INDEX: { + SET_ERRNO_AND_RETURN_IF_TRUE( + ((*(uint8_t *)option_value < SI91X_CERT_INDEX_0) || (*(uint8_t *)option_value > SI91X_CERT_INDEX_2)), + EINVAL); + + si91x_socket->certificate_index = *(const uint8_t *)option_value; + break; + } + + case SL_SI91X_SO_TLS_SNI: + case SL_SI91X_SO_TLS_ALPN: { + sl_status_t status = sli_si91x_add_tls_extension(&si91x_socket->tls_extensions, + (const sl_si91x_socket_type_length_value_t *)option_value); + + if (status != SL_STATUS_OK) { + SET_ERROR_AND_RETURN(ENOMEM); + } + break; + } + +#if defined(SLI_SI917) || defined(SLI_SI915) + case SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE: { + if (IS_POWER_OF_TWO((*(uint8_t *)option_value)) + && ((*(const uint8_t *)option_value) < MAX_RETRANSMISSION_TIME_VALUE)) { + memcpy(&si91x_socket->max_retransmission_timeout_value, + (const uint8_t *)option_value, + GET_SAFE_MEMCPY_LENGTH(sizeof(si91x_socket->max_retransmission_timeout_value), option_len)); + } else { + SL_DEBUG_LOG("\n Max retransmission timeout value in between 1 - 32 and " + "should be power of two. ex:1,2,4,8,16,32 \n"); + SET_ERROR_AND_RETURN(EINVAL); + } + break; + } +#endif + default: { + // Invalid socket option + SET_ERROR_AND_RETURN(ENOPROTOOPT); + } + } + return SI91X_NO_ERROR; +} + +int sl_si91x_send(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags) +{ + return sl_si91x_send_async(socket, buffer, buffer_length, flags, NULL); +} + +int sl_si91x_send_async(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + sl_si91x_socket_data_transfer_complete_handler_t callback) +{ + return sl_si91x_sendto_async(socket, buffer, buffer_length, flags, NULL, 0, callback); +} + +int sl_si91x_sendto(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *addr, + socklen_t addr_len) +{ + return sl_si91x_sendto_async(socket, buffer, buffer_length, flags, addr, addr_len, NULL); +} + +int sl_si91x_send_large_data(int socket, const uint8_t *buffer, size_t buffer_length, int32_t flags) +{ + const sli_si91x_socket_t *si91x_socket = get_si91x_socket(socket); + int bsd_ret_code = 0; + size_t offset = 0; + size_t chunk_size = 0; + size_t max_len = 0; + + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state == RESET || si91x_socket->state == INITIALIZED, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(buffer == NULL, EFAULT); + + // Find maximum limit based on the protocol + if (si91x_socket->type == SOCK_STREAM && si91x_socket->ssl_bitmap & SL_SI91X_ENABLE_TLS) { + max_len = (si91x_socket->local_address.sin6_family == AF_INET) ? si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV4 + : si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV6; + } else if (si91x_socket->type == SOCK_DGRAM) { + max_len = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_DATAGRAM_MSS_SIZE_IPV4 + : DEFAULT_DATAGRAM_MSS_SIZE_IPV6; + } else { + max_len = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_STREAM_MSS_SIZE_IPV4 + : DEFAULT_STREAM_MSS_SIZE_IPV6; + } + + while (offset < buffer_length) { + chunk_size = (max_len < (buffer_length - offset)) ? max_len : (buffer_length - offset); + // Send chunk of data and return the total data sent in successful case + bsd_ret_code = sl_si91x_send_async(socket, buffer + offset, chunk_size, flags, NULL); + if (bsd_ret_code < 0) { + SL_DEBUG_LOG("\n Send failed with error code 0x%X \n", errno); + break; + } else { + offset += bsd_ret_code; + } + } + return offset; +} + +int sl_si91x_sendto_async(int socket, + const uint8_t *buffer, + size_t buffer_length, + int32_t flags, + const struct sockaddr *to_addr, + socklen_t to_addr_len, + sl_si91x_socket_data_transfer_complete_handler_t callback) +{ + + UNUSED_PARAMETER(flags); + sl_status_t status = SL_STATUS_OK; + sli_si91x_socket_t *si91x_socket = get_si91x_socket(socket); + sli_si91x_socket_send_request_t request = { 0 }; + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_STREAM && si91x_socket->state != CONNECTED, ENOTCONN); + SET_ERRNO_AND_RETURN_IF_TRUE(buffer == NULL, EFAULT); + if (si91x_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION) { + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->is_waiting_on_ack == true, EWOULDBLOCK); + } + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != CONNECTED && to_addr == NULL, EFAULT); + + // Set the data transfer callback for this socket + si91x_socket->data_transfer_callback = callback; + + // Check message size depending on socket type + if (si91x_socket->type == SOCK_STREAM) { + if (si91x_socket->ssl_bitmap & SL_SI91X_ENABLE_TLS) { + // For SOCK_STREAM (TCP), consider SSL overhead if TLS is enabled + size_t max_size = (si91x_socket->local_address.sin6_family == AF_INET) + ? si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV4 + : si91x_socket->mss - SI91X_SSL_HEADER_SIZE_IPV6; + SET_ERRNO_AND_RETURN_IF_TRUE(buffer_length > max_size, EMSGSIZE); + } else { + size_t max_size = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_STREAM_MSS_SIZE_IPV4 + : DEFAULT_STREAM_MSS_SIZE_IPV6; + SET_ERRNO_AND_RETURN_IF_TRUE(buffer_length > max_size, EMSGSIZE); + } + if (si91x_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION) { + // When using SOCK_STREAM (TCP), socket will wait for an ack if the SI91X_SOCKET_FEAT_TCP_ACK_INDICATION bit is set. + si91x_socket->is_waiting_on_ack = true; + } + } else if (si91x_socket->type == SOCK_DGRAM) { + // For SOCK_DGRAM (UDP), check the message size against the default maximum size + size_t max_size = (si91x_socket->local_address.sin6_family == AF_INET) ? DEFAULT_DATAGRAM_MSS_SIZE_IPV4 + : DEFAULT_DATAGRAM_MSS_SIZE_IPV6; + SET_ERRNO_AND_RETURN_IF_TRUE(buffer_length > max_size, EMSGSIZE); + } + + if (si91x_socket->type == SOCK_DGRAM && (si91x_socket->state == BOUND || si91x_socket->state == INITIALIZED)) { + status = create_and_send_socket_request(socket, SI91X_SOCKET_UDP_CLIENT, NULL); + + SET_ERRNO_AND_RETURN_IF_TRUE(status != SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + si91x_socket->state = UDP_UNCONNECTED_READY; + } + + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_DGRAM && si91x_socket->state != CONNECTED + && si91x_socket->state != UDP_UNCONNECTED_READY, + EBADF); + + SET_ERRNO_AND_RETURN_IF_TRUE( + si91x_socket->state == UDP_UNCONNECTED_READY + && ((si91x_socket->local_address.sin6_family == AF_INET && to_addr_len < sizeof(struct sockaddr_in)) + || (si91x_socket->local_address.sin6_family == AF_INET6 && to_addr_len < sizeof(struct sockaddr_in6))), + EINVAL); + + // create a socket send request + if (si91x_socket->local_address.sin6_family == AF_INET6) { + // If the socket uses IPv6, set the IP version and destination IPv6 address + const struct sockaddr_in6 *socket_address = (const struct sockaddr_in6 *)to_addr; + request.ip_version = SL_IPV6_ADDRESS_LENGTH; + request.data_offset = (si91x_socket->type == SOCK_STREAM) ? TCP_V6_HEADER_LENGTH : UDP_V6_HEADER_LENGTH; + const uint8_t *destination_ip = + (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len >= sizeof(struct sockaddr_in6)) + ? socket_address->sin6_addr.s6_addr + : si91x_socket->remote_address.sin6_addr.s6_addr; + + memcpy(&request.dest_ip_addr.ipv6_address[0], destination_ip, SL_IPV6_ADDRESS_LENGTH); + } else { + // If the socket uses IPv4, set the IP version and destination IPv4 address + const struct sockaddr_in *socket_address = (const struct sockaddr_in *)to_addr; + request.ip_version = SL_IPV4_ADDRESS_LENGTH; + request.data_offset = (si91x_socket->type == SOCK_STREAM) ? TCP_HEADER_LENGTH : UDP_HEADER_LENGTH; + uint32_t destination_ip = + (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len >= sizeof(struct sockaddr_in)) + ? socket_address->sin_addr.s_addr + : ((struct sockaddr_in *)&si91x_socket->remote_address)->sin_addr.s_addr; + + memcpy(&request.dest_ip_addr.ipv4_address[0], &destination_ip, SL_IPV4_ADDRESS_LENGTH); + } + // Set other parameters in the send request + request.socket_id = (uint16_t)si91x_socket->id; + request.dest_port = (si91x_socket->state == UDP_UNCONNECTED_READY || to_addr_len > 0) + ? ((const struct sockaddr_in *)to_addr)->sin_port + : si91x_socket->remote_address.sin6_port; + request.length = buffer_length; + + // Send the socket data + status = sl_si91x_driver_send_socket_data(&request, buffer, 0); + if (status != SL_STATUS_OK && (si91x_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION)) { + si91x_socket->is_waiting_on_ack = false; + } + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, ENOBUFS); + + return buffer_length; +} + +int sl_si91x_recv(int socket, uint8_t *buf, size_t buf_len, int32_t flags) +{ + return sl_si91x_recvfrom(socket, buf, buf_len, flags, NULL, NULL); +} + +int sl_si91x_recvfrom(int socket, + uint8_t *buf, + size_t buf_len, + int32_t flags, + struct sockaddr *addr, + socklen_t *addr_len) +{ + UNUSED_PARAMETER(flags); + + // Initialize variables for socket communication + sl_si91x_wait_period_t wait_time = 0; + sl_si91x_req_socket_read_t request = { 0 }; + ssize_t bytes_read = 0; + size_t max_buf_len = 0; + sl_si91x_socket_metadata_t *response = NULL; + sli_si91x_socket_t *si91x_socket = get_si91x_socket(socket); + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + + // Check if the socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_STREAM && si91x_socket->state != CONNECTED, ENOTCONN); + + // Check if the buffer pointer is valid + SET_ERRNO_AND_RETURN_IF_TRUE(buf == NULL, EFAULT); + + // Check if the specified buffer length is valid + SET_ERRNO_AND_RETURN_IF_TRUE(buf_len <= 0, EINVAL); + + // create and send a socket request to configure it as UDP. + if (si91x_socket->type == SOCK_DGRAM && (si91x_socket->state == BOUND || si91x_socket->state == INITIALIZED)) { + int bsd_status = create_and_send_socket_request(socket, SI91X_SOCKET_UDP_CLIENT, NULL); + SOCKET_VERIFY_STATUS_AND_RETURN(bsd_status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); + + si91x_socket->state = UDP_UNCONNECTED_READY; + } + + // Possible states are only reset and disconnected. + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->state != CONNECTED && si91x_socket->state != UDP_UNCONNECTED_READY, EBADF); + + // Limit the buffer length based on the socket type + if (si91x_socket->local_address.sin6_family == AF_INET) { + if (si91x_socket->type == SOCK_STREAM) { + max_buf_len = DEFAULT_STREAM_MSS_SIZE_IPV4; + } else if (si91x_socket->type == SOCK_DGRAM) { + max_buf_len = DEFAULT_DATAGRAM_MSS_SIZE_IPV4; + } + } else if (si91x_socket->local_address.sin6_family == AF_INET6) { + if (si91x_socket->type == SOCK_STREAM) { + max_buf_len = DEFAULT_STREAM_MSS_SIZE_IPV6; + } else if (si91x_socket->type == SOCK_DGRAM) { + max_buf_len = DEFAULT_DATAGRAM_MSS_SIZE_IPV6; + } + } + + if (max_buf_len && (buf_len > max_buf_len)) { + buf_len = max_buf_len; + } + // Initialize the socket read request with the socket ID and requested buffer length + request.socket_id = (uint8_t)si91x_socket->id; + memcpy(request.requested_bytes, &buf_len, sizeof(buf_len)); + memcpy(request.read_timeout, &si91x_socket->read_timeout, sizeof(si91x_socket->read_timeout)); + wait_time = (SL_SI91X_WAIT_FOR_EVER | SL_SI91X_WAIT_FOR_RESPONSE_BIT); + + sl_status_t status = sli_si91x_send_socket_command(si91x_socket, + RSI_WLAN_REQ_SOCKET_READ_DATA, + &request, + sizeof(request), + wait_time, + &buffer); + + // If the command failed and a buffer was allocated, free the buffer + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + + // Retrieve the packet from the buffer + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + // Extract the socket receive response data from the firmware packet + response = (sl_si91x_socket_metadata_t *)packet->data; + + // Determine the number of bytes read, considering the buffer length and response length + bytes_read = (response->length <= buf_len) ? response->length : buf_len; + memcpy(buf, ((uint8_t *)response + response->offset), bytes_read); + + // If address information is provided, populate it based on the IP version + if (addr != NULL) { + if (response->ip_version == SL_IPV4_ADDRESS_LENGTH && *addr_len >= sizeof(struct sockaddr_in)) { + struct sockaddr_in *socket_address = (struct sockaddr_in *)addr; + + socket_address->sin_port = response->dest_port; + socket_address->sin_family = AF_INET; + memcpy(&socket_address->sin_addr.s_addr, response->dest_ip_addr.ipv4_address, SL_IPV4_ADDRESS_LENGTH); + + *addr_len = sizeof(struct sockaddr_in); + } else if (response->ip_version == SL_IPV6_ADDRESS_LENGTH && *addr_len >= sizeof(struct sockaddr_in6)) { + struct sockaddr_in6 *ipv6_socket_address = ((struct sockaddr_in6 *)addr); + + ipv6_socket_address->sin6_port = response->dest_port; + ipv6_socket_address->sin6_family = AF_INET; + memcpy(&ipv6_socket_address->sin6_addr.s6_addr, + response->dest_ip_addr.ipv6_address, + SL_IPV6_ADDRESS_LENGTH); + + *addr_len = sizeof(struct sockaddr_in6); + } else { + *addr_len = 0; + } + } + + sl_si91x_host_free_buffer(buffer); + + return bytes_read; +} + +int sl_si91x_select(int nfds, + sl_si91x_fd_set *readfds, + sl_si91x_fd_set *writefds, + sl_si91x_fd_set *exceptfds, + const struct timeval *timeout, + sl_si91x_socket_select_callback_t callback) +{ + return sli_si91x_select(nfds, readfds, writefds, exceptfds, timeout, callback); +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h new file mode 100644 index 000000000..d7e4d42bf --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble.h @@ -0,0 +1,2805 @@ +/******************************************************************************* + * @file rsi_ble.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_BLE_H +#define RSI_BLE_H + +#include "rsi_ble_apis.h" +#include "sl_common.h" + +/****************************************************** + * * Macros + * ******************************************************/ +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/// Represents the BLE state when there is no active connection. +#define RSI_BLE_STATE_NONE 0x00 +/// Represents the BLE state when the device is connected. +#define RSI_BLE_STATE_CONNECTION 0x01 +/// Represents the BLE state when the device is disconnected +#define RSI_BLE_STATE_DSICONNECT 0x02 +/// Defines the maximum number of request list entries in BLE. +#define RSI_BLE_MAX_REQ_LIST 0x05 +/// Indicates that legacy BLE commands are used (BIT 0). +#define RSI_BLE_LEGACY_CMD_USED (1 << 0) //BIT(0) +/// Indicates that advertising extension commands are used (BIT 1). +#define RSI_BLE_ADV_EXT_CMD_USED (1 << 1) //BIT(1) +/// Command to check BLE status (BIT 15). +#define RSI_BLE_CHECK_CMD (1 << 15) //BIT(15) +/// Indicates that the buffer is available. +#define SI_LE_BUFFER_AVL 0 +/// Indicates that the buffer is full. +#define SI_LE_BUFFER_FULL 1 +/// Indicates that the buffer operation is in progress. +#define SI_LE_BUFFER_IN_PROGRESS 2 +/// Vendor-specific RF type command opcode. +#define BLE_VENDOR_RF_TYPE_CMD_OPCODE 0xFC14 +/// BLE_VENDOR_ACCEPTLIST_USING_ADV_DATA_PAYLOAD. +#define BLE_VENDOR_ACCEPTLIST_USING_ADV_DATA_PAYLOAD 0xFC1B +/// Defines the maximum number of GAP extension callbacks. +#define RSI_BLE_MAX_NUM_GAP_EXT_CALLBACKS 2 +/// Defines the maximum number of advertising extension event callbacks. +#define RSI_BLE_MAX_NUM_ADV_EXT_EVENT_CALLBACKS 0x08 +/// Advertising extension reporting is disabled. +#define BLE_AE_REPORTING_DISABLED 0x01 +/// Advertising extension reporting is enabled. +#define BLE_AE_REPORTING_ENABLED 0x00 +/// Enables periodic duplicate filtering. +#define BLE_AE_PERODIC_DUPLICATE_FILTERING_ENABLED 0x01 +/// Disables periodic duplicate filtering. +#define BLE_AE_PERODIC_DUPLICATE_FILTERING_DISABLED 0x00 +/// Periodic list usage flag. +#define BLE_AE_PERIODIC_LIST_USED 0x01 + +/****************************************************** + * * Constants + * ******************************************************/ + +/****************************************************** + * * Enumerations + * ******************************************************/ +/// Enumeration for BLE advertising extension command request codes +typedef enum RSI_BLE_CMD_AE_opcode_e { + RSI_BLE_GET_AE_MAX_NO_OF_ADV_SETS = 0x0001, + RSI_BLE_GET_AE_MAX_ADV_DATA_LEN = 0x0002, + RSI_BLE_SET_AE_SET_RANDOM_ADDR = 0x0003, + RSI_BLE_SET_AE_PARAMS = 0x0004, + RSI_BLE_SET_AE_DATA = 0x0005, + RSI_BLE_SET_AE_ENABLE = 0x006, + RSI_BLE_ADV_SET_CLEAR_OR_REMOVE = 0x0007, + RSI_BLE_SET_AE_PERIODIC_ADV_PARAMS = 0x0008, + RSI_BLE_SET_AE_PERIODIC_ADV_ENABLE = 0x0009, + RSI_BLE_SET_AE_SCAN_PARAMS = 0x000A, + RSI_BLE_SET_AE_SCAN_ENABLE = 0x000B, + RSI_BLE_SET_AE_PERIODIC_SYNC = 0x000C, + RSI_BLE_AE_DEV_TO_PERIODIC_LIST = 0x000D, + RSI_BLE_AE_READ_PERIODIC_LIST_SIZE = 0x000E, + RSI_BLE_AE_EXTENDED_CREATE_CONNECT = 0x000F, +} RSI_BLE_CMD_AE_opcode_t; + +/// Enumeration for BLE command request codes +typedef enum rsi_ble_cmd_request_e { + RSI_BLE_REQ_HCI_RAW = 0x0050, + RSI_BLE_REQ_ADV = 0x0075, + RSI_BLE_REQ_SCAN = 0x0076, + RSI_BLE_REQ_CONN = 0x0077, + RSI_BLE_REQ_DISCONNECT = 0x0078, + RSI_BLE_GET_DEV_STATE = 0x0079, + RSI_BLE_CMD_CONN_PARAMS_UPDATE = 0x007A, + RSI_BLE_REQ_START_ENCRYPTION = 0x007B, + RSI_BLE_REQ_SMP_PAIR = 0x007C, + RSI_BLE_SMP_PAIR_RESPONSE = 0x007D, + RSI_BLE_SMP_PASSKEY = 0x007E, + RSI_BLE_REQ_PROFILES = 0x007F, + RSI_BLE_REQ_PROFILE = 0x0080, + RSI_BLE_REQ_CHAR_SERVICES = 0x0081, + RSI_BLE_REQ_INC_SERVICES = 0x0082, + RSI_BLE_REQ_READ_BY_UUID = 0x0083, + RSI_BLE_REQ_DESC = 0x0084, + RSI_BLE_REQ_READ_VAL = 0x0085, + RSI_BLE_REQ_MULTIPLE_READ = 0x0086, + RSI_BLE_REQ_LONG_READ = 0x0087, + RSI_BLE_REQ_WRITE = 0x0088, + RSI_BLE_REQ_WRITE_NO_ACK = 0x0089, + RSI_BLE_REQ_LONG_WRITE = 0x008A, + RSI_BLE_REQ_PREPARE_WRITE = 0x008B, + RSI_BLE_REQ_EXECUTE_WRITE = 0x008C, + RSI_BLE_ADD_SERVICE = 0x0092, + RSI_BLE_ADD_ATTRIBUTE = 0x0093, + RSI_BLE_SET_LOCAL_ATT_VALUE = 0x0094, + RSI_BLE_GET_LOCAL_ATT_VALUE = 0x0095, + RSI_BLE_CMD_NOTIFY = 0x0096, + RSI_BLE_CMD_INDICATE = 0x0097, + RSI_BLE_SET_ADVERTISE_DATA = 0x009C, + RSI_BLE_GET_LE_PING = 0x00A1, + RSI_BLE_SET_LE_PING = 0x00A2, + RSI_BLE_SET_RANDOM_ADDRESS = 0x00A3, + RSI_BLE_ENCRYPT = 0x00A4, + RSI_BLE_CMD_READ_RESP = 0x00A5, + RSI_BLE_SET_SCAN_RESPONSE_DATA = 0x00A8, + RSI_BLE_LE_ACCEPT_LIST = 0x00AA, + RSI_BLE_CMD_REMOVE_SERVICE = 0x00AB, + RSI_BLE_CMD_REMOVE_ATTRIBUTE = 0x00AC, + RSI_BLE_PROCESS_RESOLV_LIST = 0x00AD, + RSI_BLE_GET_RESOLVING_LIST_SIZE = 0x00AE, + RSI_BLE_SET_ADDRESS_RESOLUTION_ENABLE = 0x00AF, + RSI_BLE_REQ_READ_PHY = 0x00B0, + RSI_BLE_REQ_SET_PHY = 0x00B1, + RSI_BLE_SET_DATA_LEN = 0x00B2, + RSI_BLE_READ_MAX_DATA_LEN = 0X00B3, + RSI_BLE_SET_PRIVACY_MODE = 0x00B4, + RSI_BLE_CBFC_CONN_REQ = 0x00B5, + RSI_BLE_CBFC_CONN_RESP = 0x00B6, + RSI_BLE_CBFC_TX_DATA = 0x00B7, + RSI_BLE_CBFC_DISCONN = 0x00B8, + RSI_BLE_LE_LTK_REQ_REPLY = 0X00BA, + RSI_BLE_RX_TEST_MODE = 0x00BB, + RSI_BLE_TX_TEST_MODE = 0x00BC, + RSI_BLE_END_TEST_MODE = 0x00BD, + RSI_BLE_PER_TX_MODE = 0x00BF, + RSI_BLE_PER_RX_MODE = 0x00C0, + RSI_BLE_CMD_ATT_ERROR = 0x00C1, + RSI_BLE_REQ_PROFILES_ASYNC = 0x00F2, + RSI_BLE_REQ_PROFILE_ASYNC = 0x00F3, + RSI_BLE_GET_CHARSERVICES_ASYNC = 0x00F4, + RSI_BLE_GET_INCLUDESERVICES_ASYNC = 0x00F5, + RSI_BLE_READCHARVALUEBYUUID_ASYNC = 0x00F6, + RSI_BLE_GET_ATTRIBUTE_ASYNC = 0x00F7, + RSI_BLE_GET_DESCRIPTORVALUE_ASYNC = 0x00F8, + RSI_BLE_GET_MULTIPLEVALUES_ASYNC = 0x00F9, + RSI_BLE_GET_LONGDESCVALUES_ASYNC = 0x00FA, + RSI_BLE_SET_DESCVALUE_ASYNC = 0x00FB, + RSI_BLE_SET_PREPAREWRITE_ASYNC = 0x00FC, + RSI_BLE_EXECUTE_LONGDESCWRITE_ASYNC = 0x00FD, + RSI_BLE_SET_SMP_PAIRING_CAPABILITY_DATA = 0x0101, + RSI_BLE_CONN_PARAM_RESP_CMD = 0x0105, + RSI_BLE_CMD_INDICATE_CONFIRMATION = 0x0106, + RSI_BLE_MTU_EXCHANGE_REQUEST = 0x0107, + RSI_BLE_CMD_SET_WWO_RESP_NOTIFY_BUF_INFO = 0x0108, + RSI_BLE_CMD_WRITE_RESP = 0x010A, + RSI_BLE_CMD_PREPARE_WRITE_RESP = 0x010B, + RSI_BLE_CMD_SET_LOCAL_IRK = 0x010C, + RSI_BLE_REQ_SMP_PAIRING_FAILED = 0x0111, + RSI_BLE_CMD_SET_PROP_PROTOCOL_BLE_BANDEDGE_TXPOWER = 0x012A, + RSI_BLE_CMD_MTU_EXCHANGE_RESP = 0x012B, + RSI_BLE_CMD_SET_BLE_TX_POWER = 0x012D, + RSI_BLE_CMD_INDICATE_SYNC = 0x016F, + RSI_BLE_CMD_AE = 0x0171, + RSI_BLE_CMD_READ_TRANSMIT_POWER = 0x0172, + RSI_BLE_CMD_READ_RF_PATH_COMP = 0x0173, + RSI_BLE_CMD_WRITE_RF_PATH_COMP = 0x0174, + RSI_BLE_REQ_CONN_ENHANCE = 0x1FFF, // Please add new cmd ids above this cmd id. +} rsi_ble_cmd_request_t; + +/// Enumeration for BLE command response codes +typedef enum rsi_ble_cmd_resp_e { + RSI_BLE_RSP_ADVERTISE = 0x0075, + RSI_BLE_RSP_SCAN = 0x0076, + RSI_BLE_RSP_CONNECT = 0x0077, + RSI_BLE_RSP_DISCONNECT = 0x0078, + RSI_BLE_RSP_QUERY_DEVICE_STATE = 0x0079, + RSI_BLE_RSP_CONN_PARAMS_UPDATE = 0x007A, + RSI_BLE_RSP_START_ENCRYPTION = 0x007B, + RSI_BLE_RSP_SMP_PAIR = 0x007C, + RSI_BLE_RSP_SMP_PAIR_RESPONSE = 0x007D, + RSI_BLE_RSP_SMP_PASSKEY = 0x007E, + RSI_BLE_RSP_PROFILES = 0x007F, + RSI_BLE_RSP_PROFILE = 0x0080, + RSI_BLE_RSP_CHAR_SERVICES = 0x0081, + RSI_BLE_RSP_INC_SERVICES = 0x0082, + RSI_BLE_RSP_READ_BY_UUID = 0x0083, + RSI_BLE_RSP_DESC = 0x0084, + RSI_BLE_RSP_READ_VAL = 0x0085, + RSI_BLE_RSP_MULTIPLE_READ = 0x0086, + RSI_BLE_RSP_LONG_READ = 0x0087, + RSI_BLE_RSP_WRITE = 0x0088, + RSI_BLE_RSP_WRITE_NO_ACK = 0x0089, + RSI_BLE_RSP_LONG_WRITE = 0x008A, + RSI_BLE_RSP_PREPARE_WRITE = 0x008B, + RSI_BLE_RSP_EXECUTE_WRITE = 0x008C, + RSI_BLE_RSP_INIT = 0x008D, + RSI_BLE_RSP_DEINIT = 0x008E, + RSI_BLE_RSP_SET_ANTENNA = 0x008F, + RSI_BLE_RSP_ADD_SERVICE = 0x0092, + RSI_BLE_RSP_ADD_ATTRIBUTE = 0x0093, + RSI_BLE_RSP_SET_LOCAL_ATT_VALUE = 0x0094, + RSI_BLE_RSP_GET_LOCAL_ATT_VALUE = 0x0095, + RSI_BLE_RSP_NOTIFY = 0x0096, + RSI_BLE_RSP_GET_LE_PING = 0x00A1, + RSI_BLE_RSP_SET_LE_PING = 0x00A2, + RSI_BLE_RSP_SET_RANDOM_ADDRESS = 0x00A3, + RSI_BLE_RSP_ENCRYPT = 0x00A4, + RSI_BLE_RSP_READ_RESP = 0x00A5, + RSI_BLE_RSP_LE_ACCEPT_LIST = 0x00AA, + RSI_BLE_RSP_REMOVE_SERVICE = 0x00AB, + RSI_BLE_RSP_REMOVE_ATTRIBUTE = 0x00AC, + RSI_BLE_RSP_PROCESS_RESOLV_LIST = 0x00AD, + RSI_BLE_RSP_GET_RESOLVING_LIST_SIZE = 0x00AE, + RSI_BLE_RSP_SET_ADDRESS_RESOLUTION_ENABLE = 0x00AF, + RSI_BLE_RSP_READ_PHY = 0x00B0, + RSI_BLE_RSP_SET_PHY = 0x00B1, + RSI_BLE_RSP_SET_DATA_LEN = 0x00B2, + RSI_BLE_RSP_READ_MAX_DATA_LEN = 0X00B3, + RSI_BLE_RSP_PRIVACY_MODE = 0x00B4, + RSI_BLE_RSP_CBFC_CONN_REQ = 0x00B5, + RSI_BLE_RSP_CBFC_CONN_RESP = 0x00B6, + RSI_BLE_RSP_CBFC_TX_DATA = 0x00B7, + RSI_BLE_RSP_CBFC_DISCONN = 0x00B8, + + RSI_BLE_RSP_LE_LTK_REQ_REPLY = 0X00BA, + RSI_BLE_RSP_RX_TEST_MODE = 0x00BB, + RSI_BLE_RSP_TX_TEST_MODE = 0x00BC, + RSI_BLE_RSP_END_TEST_MODE = 0x00BD, + RSI_BLE_RSP_PER_TX_MODE = 0x00BE, + RSI_BLE_RSP_PER_RX_MODE = 0x00BF, + + RSI_BLE_RSP_ATT_ERROR = 0x00C1, + + RSI_BLE_RSP_PROFILES_ASYNC = 0x00F2, + RSI_BLE_RSP_PROFILE_ASYNC = 0x00F3, + RSI_BLE_RSP_GET_CHARSERVICES_ASYNC = 0x00F4, + RSI_BLE_RSP_GET_INCLUDESERVICES_ASYNC = 0x00F5, + RSI_BLE_RSP_READCHARVALUEBYUUID_ASYNC = 0x00F6, + RSI_BLE_RSP_GET_ATTRIBUTE_ASYNC = 0x00F7, + RSI_BLE_RSP_GET_DESCRIPTORVALUE_ASYNC = 0x00F8, + RSI_BLE_RSP_GET_MULTIPLEVALUES_ASYNC = 0x00F9, + RSI_BLE_RSP_GET_LONGDESCVALUES_ASYNC = 0x00FA, + RSI_BLE_RSP_SET_DESCVALUE_ASYNC = 0x00FB, + RSI_BLE_RSP_SET_PREPAREWRITE_ASYNC = 0x00FC, + RSI_BLE_RSP_EXECUTE_LONGDESCWRITE_ASYNC = 0x00FD, + + RSI_BLE_RSP_SET_SMP_PAIRING_CAPABILITY_DATA = 0x0101, + RSI_BLE_RSP_CONN_PARAM_RESP = 0x0105, + RSI_BLE_RSP_INDICATE_CONFIRMATION = 0x0106, + RSI_BLE_RSP_MTU_EXCHANGE_REQUEST = 0x0107, + RSI_BLE_RSP_SET_WWO_RESP_NOTIFY_BUF_INFO = 0x0108, + RSI_BLE_RSP_SET_LOCAL_IRK = 0x010C, + RSI_BLE_RSP_SMP_PAIRING_FAILED = 0x0111, + RSI_BLE_RSP_SET_PROP_PROTOCOL_BLE_BANDEDGE_TXPOWER = 0x012A, + RSI_BLE_RSP_MTU_EXCHANGE_RESP = 0x012B, + RSI_BLE_RSP_SET_BLE_TX_POWER = 0x012D, + + RSI_BLE_RSP_AE = 0x0171, + RSI_BLE_RSP_READ_TRANSMIT_POWER = 0x0172, + RSI_BLE_RSP_READ_RF_PATH_COMP = 0x0173, + RSI_BLE_RSP_WRITE_RF_PATH_COMP = 0x0174, +} rsi_ble_cmd_resp_t; + +/// Enumeration for BLE event codes +typedef enum rsi_ble_event_e { + RSI_BLE_EVENT_DISCONNECT = 0x1006, + RSI_BLE_EVENT_GATT_ERROR_RESPONSE = 0x1500, + RSI_BLE_EVENT_GATT_DESC_VAL_RESPONSE = 0x1501, + RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_BY_UUID = 0x1502, + RSI_BLE_EVENT_GATT_READ_CHAR_SERVS = 0x1503, //read by type: read char, include serivces and read value by uuid. + RSI_BLE_EVENT_GATT_READ_INC_SERVS = 0x1504, //read by type: read char, include serivces and read value by uuid. + RSI_BLE_EVENT_GATT_READ_VAL_BY_UUID = 0x1505, //read by type: read char, include serivces and read value by uuid. + RSI_BLE_EVENT_GATT_READ_RESP = 0x1506, + RSI_BLE_EVENT_GATT_READ_BLOB_RESP = 0x1507, + RSI_BLE_EVENT_GATT_READ_MULTIPLE_RESP = 0x1508, + RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_LIST = 0x1509, + RSI_BLE_EVENT_GATT_WRITE_RESP = 0x150A, + RSI_BLE_EVENT_GATT_PREPARE_WRITE_RESP = 0x150B, + RSI_BLE_EVENT_GATT_EXECUTE_WRITE_RESP = 0x150C, + RSI_BLE_EVENT_GATT_INDICATE_CONFIRMATION = 0x150D, + RSI_BLE_EVENT_ADV_REPORT = 0x150E, + RSI_BLE_EVENT_CONN_STATUS = 0x150F, + RSI_BLE_EVENT_SMP_REQUEST = 0x1510, + RSI_BLE_EVENT_SMP_RESPONSE = 0x1511, + RSI_BLE_EVENT_SMP_PASSKEY = 0x1512, + RSI_BLE_EVENT_SMP_FAILED = 0x1513, + RSI_BLE_EVENT_GATT_NOTIFICATION = 0x1514, + RSI_BLE_EVENT_GATT_INDICATION = 0x1515, + RSI_BLE_EVENT_ENCRYPT_STARTED = 0x1516, + RSI_BLE_EVENT_GATT_WRITE = 0x1517, + RSI_BLE_EVENT_LE_PING_TIME_EXPIRED = 0x1518, + RSI_BLE_EVENT_PREPARE_WRITE = 0x1519, + RSI_BLE_EVENT_EXECUTE_WRITE = 0x151A, + RSI_BLE_EVENT_READ_REQ = 0x151B, + RSI_BLE_EVENT_MTU = 0x151C, + RSI_BLE_EVENT_SMP_PASSKEY_DISPLAY_EVENT = 0x151D, + RSI_BLE_EVENT_PHY_UPDATE_COMPLETE = 0x151E, + RSI_BLE_EVENT_DATA_LENGTH_UPDATE_COMPLETE = 0x151F, + RSI_BLE_EVENT_SC_PASSKEY = 0x1520, + RSI_BLE_EVENT_ENHANCE_CONN_STATUS = 0x1521, + RSI_BLE_EVENT_DIRECTED_ADV_REPORT = 0x1522, + RSI_BLE_EVENT_SECURITY_KEYS = 0x1523, + RSI_BLE_EVENT_PSM_CONN_REQ = 0x1524, + RSI_BLE_EVENT_PSM_CONN_COMPLETE = 0x1525, + RSI_BLE_EVENT_PSM_RX_DATA = 0x1526, + RSI_BLE_EVENT_PSM_DISCONNECT = 0x1527, + RSI_BLE_EVENT_LE_LTK_REQUEST = 0x152A, + RSI_BLE_EVENT_CONN_UPDATE_COMPLETE = 0x152B, + RSI_BLE_EVENT_REMOTE_FEATURES = 0x152C, + RSI_BLE_EVENT_LE_MORE_DATA_REQ = 0x152D, + RSI_BLE_EVENT_REMOTE_CONN_PARAMS_REQUEST = 0x153C, + RSI_BLE_EVENT_CLI_SMP_RESPONSE = 0x153D, + RSI_BLE_EVENT_CHIP_MEMORY_STATS = 0x1530, + RSI_BLE_EVENT_SC_METHOD = 0x1540, + RSI_BLE_EVENT_MTU_EXCHANGE_INFORMATION = 0x1541, + RSI_BLE_EVENT_CTKD = 0x1542, + RSI_BLE_EVENT_REMOTE_DEVICE_INFORMATION = 0x1543, + RSI_BLE_EVENT_AE_ADVERTISING_REPORT = 0x1544, + RSI_BLE_EVENT_PER_ADV_SYNC_ESTBL = 0x1545, + RSI_BLE_EVENT_PER_ADV_REPORT = 0x1546, + RSI_BLE_EVENT_PER_ADV_SYNC_LOST = 0x1547, + RSI_BLE_EVENT_SCAN_TIMEOUT = 0x1548, + RSI_BLE_EVENT_ADV_SET_TERMINATED = 0x1549, + RSI_BLE_EVENT_SCAN_REQ_RECVD = 0x154a, + RSI_BLE_EVENT_RCP_DATA_RCVD = 0x15FF, +} rsi_ble_event_t; + +/// Enumerations for smp failure error +typedef enum { + RSI_SMP_PAIRING_NOT_SUPPORTED = 0x05, + RSI_SMP_UNSPECIFIED_REASON = 0x08, + RSI_SMP_REPEATED_ATTEMPTS = 0x09, +} smp_failure_error; + +/// Enumerations for call back types +typedef enum rsi_ble_callback_id_e { + RSI_BLE_ON_CTKD = 1, + RSI_BLE_ON_ADV_EXT_ADVERTISE_REPORT_EVENT = 2, + RSI_BLE_ON_ADV_EXT_PERIODIC_ADV_SYNC_ESTBL_EVENT = 3, + RSI_BLE_ON_ADV_EXT_PERIODIC_ADVERTISE_REPORT_EVENT = 4, + RSI_BLE_ON_ADV_EXT_PERIODIC_ADV_SYNC_LOST_EVENT = 5, + RSI_BLE_ON_ADV_EXT_SCAN_TIMEOUT_EVENT = 6, + RSI_BLE_ON_ADV_EXT_ADVERTISE_SET_TERMINATED_EVENT = 7, + RSI_BLE_ON_ADV_EXT_SCAN_REQUEST_RECEIVED_EVENT = 8, +} rsi_ble_callback_id_t; +/** @} */ +/******************************************************** + * * Structure Definitions + * ******************************************************/ +/** @addtogroup BT_BLE_TYPES + * @{ */ + +// GAP command structures + +/** + * @brief Structure representing the BLE request to set a random address. + * + * This structure is used to define the parameters for the BLE request to set a random address, + * including the random address of the device to be set. + */ +typedef struct rsi_ble_req_rand_s { + /** Random address of the device to be set */ + uint8_t rand_addr[RSI_DEV_ADDR_LEN]; +} rsi_ble_req_rand_t; + +// Advertising command structure +/** + * @brief Structure representing a BLE advertising request. + */ +typedef struct rsi_ble_req_adv_s { + /** Advertising Status +- + + 0 - disable +- + 1 - enable*/ + uint8_t status; + /** Advertising type used during advertising +- + + 1. Advertising will be visible(discoverable) to all the devices. Scanning/Connection is also accepted from all devices. +- + + #define UNDIR_CONN 0x80 +- + + 2. Advertising will be visible(discoverable) to the particular device mentioned in RSI_BLE_ADV_DIR_ADDR only. +- + + Scanning and Connection will be accepted from that device only. +- + + #define DIR_CONN 0x81 +- + + 3. Advertising will be visible(discoverable) to all the devices. Scanning will be accepted from all the devices. +- + + Connection will be not be accepted from any device. +- + + #define UNDIR_SCAN 0x82 +- + + 4. Advertising will be visible(discoverable) to all the devices. Scanning and Connection will not be accepted from any device. +- + + #define UNDIR_NON_CONN 0x83 +- + + 5. Advertising will be visible(discoverable) to the particular device mentioned in RSI_BLE_ADV_DIR_ADDR only. +- + + Scanning and Connection will be accepted from that device only. +- + + #define DIR_CONN_LOW_DUTY_CYCLE 0x84 */ + uint8_t adv_type; + /** Advertising filter type +- + + #define ALLOW_SCAN_REQ_ANY_CONN_REQ_ANY 0x00 +- + + #define ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ANY 0x01 +- + + #define ALLOW_SCAN_REQ_ANY_CONN_REQ_ACCEPT_LIST 0x02 +- + + #define ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ACCEPT_LIST 0x03 */ + uint8_t filter_type; + /** Address type of the device to which directed advertising has to be done +- + + #define LE_PUBLIC_ADDRESS 0x00 +- + + #define LE_RANDOM_ADDRESS 0x01 +- + + #define LE_RESOLVABLE_PUBLIC_ADDRESS 0x02 +- + + #define LE_RESOLVABLE_RANDOM_ADDRESS 0x03 */ + uint8_t direct_addr_type; + /** Address of the device to which directed advertising has to be done */ + uint8_t direct_addr[RSI_DEV_ADDR_LEN]; + + /** Advertising interval min 0x0020 to 0x4000 */ + uint16_t adv_int_min; + + /** Advertising interval max 0x0020 to 0x4000 */ + uint16_t adv_int_max; + + /** Address of the local device. +- + + #define LE_PUBLIC_ADDRESS 0x00 +- + + #define LE_RANDOM_ADDRESS 0x01 +- + + #define LE_RESOLVABLE_PUBLIC_ADDRESS 0x02 +- + + #define LE_RESOLVABLE_RANDOM_ADDRESS 0x03 */ + uint8_t own_addr_type; + + /** Advertising channel map. +- + + #define RSI_BLE_ADV_CHANNEL_MAP 0x01 or 0x03 or 0x07 */ + uint8_t adv_channel_map; +} rsi_ble_req_adv_t; + +// Advertising data command structure + +/** + * @brief Structure representing the BLE request to set advertising data. + * + * This structure is used to define the parameters for the BLE request to set advertising data, + * including the advertising data length and the advertising data itself. + */ +typedef struct rsi_ble_req_adv_data_s { + /** Advertising data length */ + uint8_t data_len; + /** Advertising data */ + uint8_t adv_data[31]; +} rsi_ble_req_adv_data_t; + +/** + * @brief Structure representing the BLE request to manage the accept list using a payload. + * + * This structure is used to define the parameters for the BLE request to manage the accept list, + * including the operation code, enable flag, total length of the payload, data compare index, + * length of the data to compare, and the advertising data payload. + */ +typedef struct rsi_ble_req_acceptlist_using_payload_s { + /** Operation code for the request */ + uint8_t opcode[2]; + /** Enable or disable the accept list */ + uint8_t enable; + /** Total length of the payload */ + uint8_t total_len; + /** Index for comparing data */ + uint8_t data_compare_index; + /** Length of the data to compare */ + uint8_t len_for_compare_data; + /** Advertising data payload */ + uint8_t adv_data_payload[31]; +} rsi_ble_req_acceptlist_using_payload_t; + +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ +/// BLE protocol identifier. +#define BLE_PROTOCOL 0x01 +/// Proprietary protocol identifier. +#define PROP_PROTOCOL 0x02 +/// Advertising role identifier. +#define ADV_ROLE 0x01 +/// Scanning and central role identifier. +#define SCAN_AND_CENTRAL_ROLE 0x02 +#ifndef PERIPHERAL_ROLE +/// Peripheral role identifier. +#define PERIPHERAL_ROLE 0x03 +#endif +/// Connection role identifier. +#define CONN_ROLE 0x04 +/** @} */ + +// Set BLE tx power cmd_ix=0x012D + +/** + * @brief Structure representing the BLE request to set the transmission power. + * + * This structure is used to define the parameters for the BLE request to set the transmission power, + * including the transmission power value. + */ +typedef struct rsi_ble_set_ble_tx_power_s { + /** Transmission power value */ + int8_t tx_power; +} rsi_ble_set_ble_tx_power_t; + +//Scan response data command structure + +/** + * @brief Structure representing the set scan response data for the BLE scan request. + * + * This structure is used to define the parameters to set scan response data for the BLE scan request, + * including the scan response data length. + */ +typedef struct rsi_ble_req_scanrsp_data_s { + /** Scan response data length */ + uint8_t data_len; + /** Scan response data */ + uint8_t scanrsp_data[31]; +} rsi_ble_req_scanrsp_data_t; + +//Scan command structure +/** + * @brief Structure representing a BLE scan request. + */ +typedef struct rsi_ble_req_scan_s { + + /** Scanning Status +- + + 0 - disable +- + 1 - enable*/ + uint8_t status; + + /** Scanning type +- + + SCAN_TYPE_ACTIVE 0x01 +- + + SCAN_TYPE_PASSIVE 0x00 */ + uint8_t scan_type; + + /** To filter incoming advertising reports +- + + FILTERING_DISABLED = 0 (default) +- + + ACCEPTLIST_FILTERING = 1 + @note In order to allow only acceptlisted devices, need to add bd_addr + into acceptlist by calling @ref rsi_ble_addto_acceptlist() API */ + uint8_t filter_type; + + /** Address type of the local device +- + + #define LE_PUBLIC_ADDRESS 0x00 +- + + #define LE_RANDOM_ADDRESS 0x01 +- + + #define LE_RESOLVABLE_PUBLIC_ADDRESS 0x02 +- + + #define LE_RESOLVABLE_RANDOM_ADDRESS 0x03 */ + uint8_t own_addr_type; + + /** Scan interval +- + + This is defined as the time interval from when the Controller started + its last LE scan until it begins the subsequent LE scan. +- + + Range: 0x0004 to 0x4000 */ + uint16_t scan_int; + + /** Scan window +- + + The duration of the LE scan. LE_Scan_Window shall be less than or equal to LE_Scan_Interval +- + + Range: 0x0004 to 0x4000 */ + uint16_t scan_win; + +} rsi_ble_req_scan_t; + +//ENCRYPT COMMAND STRUCTURE + +/** + * @brief Structure representing the BLE encryption request. + * + * This structure is used to define the parameters for the BLE encryption request, + * including the encryption key and the data to be encrypted. + */ +typedef struct rsi_ble_encrypt_s { + /** Encryption key (16 bytes) */ + uint8_t key[16]; + /** Data to be encrypted (16 bytes) */ + uint8_t data[16]; +} rsi_ble_encrypt_t; + +/** + * @brief Structure representing a data packet. + * + * This structure is used to define the parameters for a data packet, + * including an array to hold the data packet, up to 1024 bytes. + */ +typedef struct rsi_data_packet_s { + /** Array to hold the data packet, up to 1024 bytes */ + uint8_t data[1024]; +} rsi_data_packet_t; + +//accept list structure + +/** + * @brief Structure representing the BLE accept list. + * + * This structure is used to define the parameters for the BLE accept list, + * including the operation to add or delete the address, the device address, and the address type. + */ +typedef struct rsi_ble_accept_list_s { + /** Bit used to add or delete the address from/to the allow list */ + uint8_t addordeltowhitlist; + /** Address of the device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Address type */ + uint8_t bdaddressType; +} rsi_ble_accept_list_t; + +//Connect command structure + +/** + * @brief Structure representing the BLE connection request. + * + * This structure is used to define the parameters for a BLE connection request, + * including the address type and address of the device to connect, scan interval, scan window, + * connection interval, connection latency, and supervision timeout. + */ +typedef struct rsi_ble_req_conn_s { + /** Address type of the device to connect */ + uint8_t dev_addr_type; + /** Address of the device to connect */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Scan interval */ + uint16_t le_scan_interval; + /** Scan window */ + uint16_t le_scan_window; + /** Minimum connection interval */ + uint16_t conn_interval_min; + /** Maximum connection interval */ + uint16_t conn_interval_max; + /** Connection latency */ + uint16_t conn_latency; + /** Supervision timeout */ + uint16_t supervision_tout; +} rsi_ble_req_conn_t; + +/** + * @brief Structure representing the BLE enhanced connection request. + * + * This structure is used to define the parameters for a BLE enhanced connection request, + * including the address type and address of the device to connect, filter policy, own address type, + * scan interval, scan window, connection interval, connection latency, supervision timeout, + * and connection event length. + */ +typedef struct rsi_ble_req_enhance_conn_s { + /** Address type of the device to connect */ + uint8_t dev_addr_type; + /** Address of the device to connect */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Filter policy */ + uint8_t filter_policy; + /** Own address type */ + uint8_t own_addr_type; + /** Scan interval */ + uint16_t le_scan_interval; + /** Scan window */ + uint16_t le_scan_window; + /** Minimum connection interval */ + uint16_t conn_interval_min; + /** Maximum connection interval */ + uint16_t conn_interval_max; + /** Connection latency */ + uint16_t conn_latency; + /** Supervision timeout */ + uint16_t supervision_tout; + /** Minimum connection event length */ + uint16_t min_ce_length; + /** Maximum connection event length */ + uint16_t max_ce_length; +} rsi_ble_req_enhance_conn_t; + +//Disconnect command structure + +/** + * @brief Structure representing the BLE request to disconnect. + * + * This structure is used to define the parameters for the BLE request to disconnect, + * including the device address and the type of disconnect operation. + */ +typedef struct rsi_ble_req_disconnect_s { + /** Address of the device to disconnect */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/// Indicates compatibility mode for BLE operations. +#define COMPATABILITY 0 +/// Command to cancel an ongoing BLE connection attempt. +#define BLE_CONNECT_CANCEL 1 +/// Command to disconnect an established BLE connection. +#define BLE_DISCONNECT 2 + /** @} */ + /** Type of the disconnect operation */ + uint8_t type; +} rsi_ble_req_disconnect_t; + +//SMP protocol structures + +//start encryption cmd structures + +/** + * @brief Structure representing the BLE start encryption request. + * + * This structure is used to define the parameters for a BLE start encryption request, + * including the address of the connected device, the remote device's Encrypted Diversifier (EDIV) value, + * Random (RAND) value, and Long Term Key (LTK) value. + */ +typedef struct rsi_ble_start_encryption_s { + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Remote device EDIV value */ + uint16_t ediv; + /** Remote device RAND value */ + uint8_t rand[8]; + /** Remote device LTK value */ + uint8_t ltk[16]; +} rsi_ble_strat_encryption_t; + +//SMP Pair Request command structure = 0x007C + +/** + * @brief Structure representing the BLE Security Manager Protocol (SMP) pairing request. + * + * This structure is used to define the parameters for a BLE SMP pairing request, + * including the device address, IO capability, and MITM (Man-In-The-Middle) protection requirement. + */ +typedef struct rsi_ble_req_smp_pair_s { + /** Device address for the pairing request */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** IO capability of the device */ + uint8_t io_capability; + /** MITM (Man-In-The-Middle) protection requirement */ + uint8_t mitm_req; +} rsi_ble_req_smp_pair_t; + +//SMP Response command structure = 0x007D + +/** + * @brief Structure representing the BLE Security Manager Protocol (SMP) response. + * + * This structure is used to define the parameters for a BLE SMP response, + * including the device address, IO capability, and Man-In-The-Middle (MITM) protection requirement. + */ +typedef struct rsi_ble_smp_response_s { + /** Device address for the SMP response */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** IO capability of the device */ + uint8_t io_capability; + /** MITM protection requirement */ + uint8_t mitm_req; +} rsi_ble_smp_response_t; + +//SMP Passkey command structure, cmd_ix - 0x007E + +/** + * @brief Structure representing the BLE SMP (Security Manager Protocol) passkey. + * + * This structure is used to define the parameters for a BLE SMP passkey, + * including the device address, reserved bytes for future use, and the passkey used for pairing. + */ +typedef struct rsi_ble_smp_passkey_s { + /** Address of the device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Reserved for future use (2 bytes) */ + uint8_t reserved[2]; + /** Passkey used for pairing */ + uint32_t passkey; +} rsi_ble_smp_passkey_t; + +//LE ping get auth payload timeout command structure, cmd_ix - 0x00A1 + +/** + * @brief Structure representing the BLE command to get the LE ping timeout. + * + * This structure is used to define the parameters for a BLE command to get the LE ping timeout, + * including the remote device address. + */ +typedef struct rsi_ble_get_le_ping_timeout_s { + /** Remote device address (6 bytes) */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; +} rsi_ble_get_le_ping_timeout_t; + +//LE ping get auth payload timeout command structure, cmd_ix - 0x00A2 +/** + * @brief Structure representing the BLE response for getting LE ping timeout. + * + * This structure is used to define the parameters for the BLE response to get the LE ping timeout, + * including the address of the connected device and the LE ping timeout value. + */ +typedef struct rsi_ble_rsp_get_le_ping_timeout_s { + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** LE ping timeout value */ + uint16_t time_out; +} rsi_ble_rsp_get_le_ping_timeout_t; + +//LE ping get auth payload timeout command structure, cmd_ix - 0x00A2 +/** + * @brief Structure representing the BLE request to set LE ping timeout. + * + * This structure is used to define the parameters for a BLE request to set the LE ping timeout, + * including the address of the connected device and the LE ping timeout value to be set. + */ +typedef struct rsi_ble_set_le_ping_timeout_s { + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** LE ping timeout value to be set */ + uint16_t time_out; +} rsi_ble_set_le_ping_timeout_t; + +/** + * @brief Structure representing the BLE resolving list entry. + * + * This structure is used to define the parameters for a BLE resolving list entry, + * including the type of process (e.g., add, remove, clear), the address type and address of the remote device, + * and the Identity Resolving Keys (IRKs) of both the peer and local devices. + */ +typedef struct rsi_ble_resolvlist_s { + /** Type of process (e.g., add, remove, clear) */ + uint8_t process_type; + /** Address type of the remote device */ + uint8_t remote_dev_addr_type; + /** Address of the remote device */ + uint8_t remote_dev_addr[RSI_DEV_ADDR_LEN]; + /** Identity Resolving Key (IRK) of the peer device */ + uint8_t peer_irk[16]; + /** Identity Resolving Key (IRK) of the local device */ + uint8_t local_irk[16]; +} rsi_ble_resolvlist_t; + +//LE Get resolvlist size command structure, cmd_ix - 0x00AE + +/** + * @brief Structure representing the BLE request to get the size of the resolving list. + * + * This structure is used to define the parameter for a BLE request to get the size of the resolving list. + */ +typedef struct rsi_ble_get_resolving_list_size_s { + /** Size of the resolving list */ + uint8_t size; +} rsi_ble_get_resolving_list_size_t; + +/** + * @brief Structure representing the BLE request to enable or disable address resolution. + * + * This structure is used to define the parameters for a BLE request to enable or disable address resolution, + * including the enable flag, reserved field for future use, and the timeout value for address resolution. + */ +typedef struct rsi_ble_set_addr_resolution_enable_s { + /** Enable or disable address resolution */ + uint8_t enable; + /** Reserved for future use */ + uint8_t reserved; + /** Timeout value for address resolution */ + uint16_t tout; +} rsi_ble_set_addr_resolution_enable_t; + +//LE conn params update command structure, cmd_ix - 0x007A + +/** + * @brief Structure representing the BLE command to update connection parameters. + * + * This structure is used to define the parameters for a BLE command to update connection parameters, + * including the address of the connected device, minimum and maximum connection intervals, + * peripheral latency, and supervision timeout. + */ +typedef struct rsi_ble_cmd_conn_params_update_s { + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Minimum connection interval */ + uint16_t min_interval; + /** Maximum connection interval */ + uint16_t max_interval; + /** Peripheral latency */ + uint16_t latency; + /** Supervision timeout */ + uint16_t timeout; +} rsi_ble_cmd_conn_params_update_t; + +//LE read phy request command structure, cmd_ix - 0x00B0 + +/** + * @brief Structure representing the BLE request to read PHY. + * + * This structure is used to define the parameter for a BLE request to read the PHY, + * including the address of the connected device. + */ +typedef struct rsi_ble_req_read_phy_s { + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; +} rsi_ble_req_read_phy_t; + +//LE set phy command response structure, cmd_ix - 0x00B1 + +/** + * @brief Structure representing the BLE request to set PHY. + * + * This structure is used to define the parameters for a BLE request to set the PHY, + * including the address of the connected device, all PHYs preference, preferred TX PHY, + * preferred RX PHY, reserved field for future use, and PHY options. + */ +typedef struct rsi_ble_set_phy_s { + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** All PHYs preference */ + uint8_t all_phy; + /** Preferred TX PHY */ + uint8_t tx_phy; + /** Preferred RX PHY */ + uint8_t rx_phy; + /** Reserved for future use */ + uint8_t reserved; + /** PHY options */ + uint16_t phy_options; +} rsi_ble_set_phy_t; + +//LE set data length command response structure, cmd_ix - 0x00B2 + +/** + * @brief Structure representing the BLE request to set data length. + * + * This structure is used to define the parameters for a BLE request to set the data length, + * including the address of the connected device, the maximum number of payload octets that the local device will send, + * and the maximum time that the local device will take to send the payload. + */ +typedef struct rsi_ble_setdatalength_s { + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Maximum number of payload octets that the local device will send */ + uint16_t txoctets; + /** Maximum time that the local device will take to send the payload */ + uint16_t txtime; +} rsi_ble_setdatalength_t; + +//LE set privacy mode command structure, cmd_ix - 0x00B4 + +/** + * @brief Structure representing the BLE request to set privacy mode. + * + * This structure is used to define the parameters for a BLE request to set the privacy mode, + * including the address type and address of the remote device, and the privacy mode to be set. + */ +typedef struct rsi_ble_set_privacy_mode_s { + /** Address type of the remote device */ + uint8_t remote_dev_addr_type; + /** Address of the remote device */ + uint8_t remote_dev_addr[RSI_DEV_ADDR_LEN]; + /** Privacy mode to be set */ + uint8_t privacy_mode; +} rsi_ble_set_privacy_mode_t; + +//LE cbfc connection req command structure, cmd_ix - 0x00B5 + +/** + * @brief Structure representing the BLE Credit Based Flow Control (CBFC) connection request. + * + * This structure is used to define the parameters for a BLE CBFC connection request, + * including the address of the remote device and the Protocol/Service Multiplexer (PSM) value. + */ +typedef struct rsi_ble_cbfc_conn_req_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Protocol/Service Multiplexer (PSM) value */ + uint8_t psm; +} rsi_ble_cbfc_conn_req_t; + +//LE cbfc connection resp command structure, cmd_ix - 0x00B6 + +/** + * @brief Structure representing the BLE Credit Based Flow Control (CBFC) connection response. + * + * This structure is used to define the parameters for a BLE CBFC connection response, + * including the address of the remote device, the Local Channel Identifier (LCID), and the result of the connection request. + */ +typedef struct rsi_ble_cbfc_conn_resp_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Local Channel Identifier (LCID) */ + uint16_t lcid; + /** Result of the connection request */ + uint8_t result; +} rsi_ble_cbfc_conn_resp_t; + +//LE cbfc data TX command structure, cmd_ix - 0x00B7 + +/** + * @brief Structure representing the BLE Credit Based Flow Control (CBFC) data transmission. + * + * This structure is used to define the parameters for a BLE CBFC data transmission, + * including the address of the remote device, the Local Channel Identifier (LCID), + * the length of the data to be transmitted, and the data to be transmitted. + */ +typedef struct rsi_ble_cbfc_data_tx_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Local Channel Identifier (LCID) */ + uint16_t lcid; + /** Length of the data to be transmitted */ + uint16_t len; + /** Data to be transmitted */ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_cbfc_data_tx_t; + +//LE cbfc disconn command structure, cmd_ix - 0x00B8 + +/** + * @brief Structure representing the BLE CBFC (Credit Based Flow Control) disconnection. + * + * This structure is used to define the parameters for a BLE CBFC disconnection, + * including the address of the remote device and the Local Channel Identifier (LCID). + */ +typedef struct rsi_ble_cbfc_disconn_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Local Channel Identifier (LCID) */ + uint16_t lcid; +} rsi_ble_cbfc_disconn_t; + +//LE RX text mode (cmd), cmd_ix = 0x00BB + +/** + * @brief Structure representing the BLE RX test mode parameters. + * + * This structure is used to define the parameters for a BLE RX test mode, + * including the RX channel, PHY, and modulation type to be used for the test. + */ +typedef struct rsi_ble_rx_test_mode_s { + /** RX channel to be used for the test */ + uint8_t rx_channel; + /** PHY to be used for the test */ + uint8_t phy; + /** Modulation type to be used for the test */ + uint8_t modulation; +} rsi_ble_rx_test_mode_t; + +//LE TX test mode (cmd), cmd_ix = 0x00BC +/** + * @brief Structure representing the BLE TX test mode parameters. + * + * This structure is used to define the parameters for a BLE TX test mode, + * including the TX channel, PHY, length of the data to be transmitted, and data mode to be used for the test. + */ +typedef struct rsi_ble_tx_test_mode_s { + /** TX channel to be used for the test */ + uint8_t tx_channel; + /** PHY to be used for the test */ + uint8_t phy; + /** Length of the data to be transmitted */ + uint8_t tx_len; + /** Data mode to be used for the test */ + uint8_t tx_data_mode; +} rsi_ble_tx_test_mode_t; + +//LE End test mode (cmd), cmd_ix = 0x00BD + +/** + * @brief Structure representing the BLE end test mode parameters. + * + * This structure is used to define the parameter for a BLE end test mode. + * Number of TX / RX packets received are displayed when test is stopped. + */ +typedef struct rsi_ble_end_test_mode_s { + /** Number of TX / RX packets received when test is stopped */ + uint16_t num_of_pkts; +} rsi_ble_end_test_mode_t; + +/** + * @brief Structure representing the BLE request to set LE Long Term Key (LTK) request reply. + * + * This structure is used to define the parameters for a BLE request to set the LE LTK request reply, + * including the address of the remote device, the type of reply (e.g., positive or negative), + * and the local Long Term Key (LTK). + */ +typedef struct rsi_ble_set_le_ltkreqreply_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Type of reply (e.g., positive or negative) */ + uint8_t replytype; + /** Local Long Term Key (LTK) (16 bytes) */ + uint8_t localltk[16]; +} rsi_ble_set_le_ltkreqreply_t; + +//SMP Pairing Failed (cmd), cmd_ix = 0x0111 + +/** + * @brief Structure representing the BLE Security Manager Protocol (SMP) pairing failure request. + * + * This structure is used to define the parameters for a BLE SMP pairing failure request, + * including the address of the remote device and the reason for the pairing failure. + */ +typedef struct rsi_ble_req_smp_pair_failed_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Reason for the pairing failure */ + uint8_t reason; +} rsi_ble_req_smp_pair_failed_t; + +// GATT structures + +// GATT Profiles list request structure + +/** + * @brief Structure representing the BLE request for profiles list. + * + * This structure is used to define the parameters for a BLE request to get the profiles list, + * including the remote device address, the handle from which the profiles search will start, + * and the handle at which the profiles search will stop. + */ +typedef struct rsi_ble_req_profiles_list_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Profiles search will start from this handle */ + uint16_t start_handle; + /** Profiles search will stop at this handle */ + uint16_t end_handle; +} rsi_ble_req_profiles_list_t; + +// GATT Profile request structure + +/** + * @brief Structure representing the BLE request for a specific profile. + * + * This structure is used to define the parameters for a BLE request to get a specific profile, + * including the remote device address, reserved bytes for future use, and the profile UUID. + */ +typedef struct rsi_ble_req_profile_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Reserved for future use */ + uint8_t reserved[2]; + /** Profile UUID (20 bytes) */ + uuid_t profile_uuid; +} rsi_ble_req_profile_t; + +// GATT Profile response structure +//profile_descriptors_t; + +// GATT multiple characteristic services request structure + +/** + * @brief Structure representing the BLE request for characteristic services. + * + * This structure is used to define the parameters for a BLE request to get characteristic services, + * including the remote device address, the handle from which the search will start, + * and the handle at which the search will end. + */ +typedef struct rsi_ble_req_char_services_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Search will start from this handle */ + uint8_t start_handle[2]; + /** Search will end at this handle */ + uint8_t end_handle[2]; +} rsi_ble_req_char_services_t; + +// GATT include service query request structure + +/** + * @brief Structure representing the BLE request for included services. + * + * This structure is used to define the parameters for a BLE request to get included services, + * including the remote device address, the handle from which the search will start, + * and the handle at which the search will end. + */ +typedef struct rsi_ble_req_inc_services_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Search will start from this handle */ + uint8_t start_handle[2]; + /** Search will end at this handle */ + uint8_t end_handle[2]; +} rsi_ble_req_inc_services_t; + +// GATT read value by UUID request structure + +/** + * @brief Structure representing the BLE request for characteristic value by UUID. + * + * This structure is used to define the parameters for a BLE request to get a characteristic value by UUID, + * including the remote device address, the handle from which the search will start, + * the handle at which the search will end, reserved bytes for future use, and the search UUID value. + */ +typedef struct rsi_ble_req_char_val_by_uuid_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Search will start from this handle */ + uint8_t start_handle[2]; + /** Search will end at this handle */ + uint8_t end_handle[2]; + /** Reserved for future use */ + uint8_t reserved[2]; + /** Search UUID value (20 bytes) */ + uuid_t char_uuid; +} rsi_ble_req_char_val_by_uuid_t; + +// GATT read value by UUID response structure +//rsi_ble_resp_att_value_t + +// GATT multiple attribute descriptors request structure + +/** + * @brief Structure representing the BLE request for attribute descriptors. + * + * This structure is used to define the parameters for a BLE request to get attribute descriptors, + * including the remote device address, the handle from which the search will start, + * and the handle at which the search will end. + */ +typedef struct rsi_ble_req_att_descs_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Search will start from this handle */ + uint8_t start_handle[2]; + /** Search will end at this handle */ + uint8_t end_handle[2]; +} rsi_ble_req_att_descs_t; + +// GATT attribute value request structure +/** + * @brief Structure representing the BLE request for attribute value. + * + * This structure is used to define the parameters for a BLE request to get an attribute value, + * including the remote device address and the attribute handle. + */ +typedef struct rsi_ble_req_att_value_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint8_t handle[2]; +} rsi_ble_req_att_value_t; + +// GATT multiple attribute values request structure + +/** + * @brief Structure representing the BLE request for multiple attribute values. + * + * This structure is used to define the parameters for a BLE request to get multiple attribute values, + * including the remote device address, the number of attribute handles, reserved bytes for future use, + * and the list of attribute handles. + */ +typedef struct rsi_ble_req_multiple_att_val_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Number of attribute handles */ + uint8_t num_of_handles; + /** Reserved for future use */ + uint8_t reserved; + /** List of attribute handles */ + uint16_t handles[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_req_multi_att_values_t; + +// GATT multiple attribute values response structure +//rsi_ble_resp_att_value_t + +// GATT long attribute value request structure + +/** + * @brief Structure representing the BLE request for a long attribute value. + * + * This structure is used to define the parameters for a BLE request to get a long attribute value, + * including the remote device address, the attribute handle, and the attribute value offset. + */ +typedef struct rsi_ble_req_long_att_value_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint16_t handle; + /** Attribute value offset */ + uint16_t offset; +} rsi_ble_req_long_att_value_t; + +// GATT long attribute value response structure +//rsi_ble_resp_att_value_t + +// GATT write attribute value request structure + +/** + * @brief Structure representing the BLE request to set an attribute value. + * + * This structure is used to define the parameters for a BLE request to set an attribute value, + * including the remote device address, the attribute handle, the length of the attribute value, + * and the attribute value itself. The module will receive the acknowledgement from the remote device. + * + */ +typedef struct rsi_ble_set_att_val_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint8_t handle[2]; + /** Length of the attribute value */ + uint8_t length; + /** Attribute value */ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_set_att_value_t; +// GATT write attribute value without ack request structure + +/** + * @brief Structure representing the BLE command to set an attribute value. + * + * This structure is used to define the parameters for a BLE command to set an attribute value, + * including the remote device address, the attribute handle, the length of the attribute value, + * and the attribute value itself. The module won't receive the acknowledgement from the remote device. + */ +typedef struct rsi_ble_set_att_cmd_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint8_t handle[2]; + /** Length of the attribute value */ + uint8_t length; + /** Attribute value */ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_set_att_cmd_t; + +// GATT write long attribute value request structure + +/** + * @brief Structure representing the BLE command to set a long attribute value. + * + * This structure is used to define the parameters for a BLE command to set a long attribute value, + * including the remote device address, the attribute handle, the attribute value offset, + * the length of the attribute value, and the attribute value itself. + */ +typedef struct rsi_ble_set_long_att_val_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint8_t handle[2]; + /** Attribute value offset */ + uint8_t offset[2]; + /** Length of the attribute value */ + uint8_t length; + /** Attribute value */ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_set_long_att_value_t; + +// GATT prepare write value request structure + +/** + * @brief Structure representing the BLE request to prepare a write operation. + * + * This structure is used to define the parameters for a BLE request to prepare a write operation, + * including the remote device address, the attribute handle, the attribute value offset, + * the length of the attribute value, and the attribute value itself. + */ +typedef struct rsi_ble_req_prepare_write_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint8_t handle[2]; + /** Attribute value offset */ + uint8_t offset[2]; + /** Length of the attribute value */ + uint8_t length; + /** Attribute value */ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_req_prepare_write_t; + +// GATT execute write request structure + +/** + * @brief Structure representing the BLE request to execute a write operation. + * + * This structure is used to define the parameters for a BLE request to execute a write operation, + * including the remote device address and the execute flag indicating whether to write or not. + */ +typedef struct rsi_ble_req_execute_write_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Execute flag (write/don't write) */ + uint8_t flag; +} rsi_ble_req_execute_write_t; + +//RSI_BLE_CONN_PARAM_RESP_CMD, cmd_id: 0x0105 + +/** + * @brief Structure representing the BLE command response for connection parameters. + * + * This structure is used to define the parameters for a BLE command response to a connection parameter request, + * including the remote device address and the status indicating whether to accept or reject the request. + */ +typedef struct rsi_ble_cmd_conn_param_resp { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Accept or reject the remote connection parameter request */ + uint8_t status; +} rsi_ble_cmd_conn_param_resp_t; + +//GATT Events + +//GATT Service +// add new GATT service request structure + +/** + * @brief Structure representing the BLE request to add a service. + * + * This structure is used to define the parameters for a BLE request to add a service, + * including the service UUID, the number of attributes in the service, + * and the total size of the attributes' values (data). + */ +typedef struct rsi_ble_req_add_serv_s { + /** Service UUID */ + uuid_t service_uuid; + /** Number of attributes in the service */ + uint8_t num_of_attributes; + /** Total size of the attributes' values (data) */ + uint8_t total_att_datasize; +} rsi_ble_req_add_serv_t; + +// write or change local attribute value request structure + +/** + * @brief Structure representing the BLE command to set a local attribute value. + * + * This structure is used to define the parameters for a BLE command to set a local attribute value, + * including the attribute handle, the length of the attribute value, and the attribute value itself. + */ +typedef struct rsi_ble_set_local_att_value_s { + /** Attribute handle */ + uint16_t handle; + /** Attribute value length */ + uint16_t data_len; + /** Attribute value (data) */ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_set_local_att_value_t; + +// write or change local attribute value request structure + +/** + * @brief Structure representing the BLE notification for an attribute value. + * + * This structure is used to define the parameters for a BLE notification of an attribute value, + * including the remote device address, the attribute handle, the length of the attribute value, + * and the attribute value itself. + */ +typedef struct rsi_ble_notify_att_value_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint16_t handle; + /** Attribute value length */ + uint16_t data_len; + /** Attribute value (data) */ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_notify_att_value_t; + +// set wo_resp and notify buffer info + +/** + * @brief Structure representing the BLE configuration for write without response notification buffer. + * + * This structure is used to define the parameters for configuring the buffer for write without response notifications, + * including the remote device address, the buffer configuration mode, and the buffer count. + */ +typedef struct rsi_ble_set_wo_resp_notify_buf_info_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Buffer config mode: 0 for small buffer mode, 1 for big buffer mode */ + uint8_t buf_mode; + /** Buffer count */ + uint8_t buf_count; +} rsi_ble_set_wo_resp_notify_buf_info_t; + +// indicate confirmation structure + +/** + * @brief Structure representing the BLE indication confirmation. + * + * This structure is used to define the parameters for a BLE indication confirmation, + * including the remote device address. + */ +typedef struct rsi_ble_indicate_confirm_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; +} rsi_ble_indicate_confirm_t; + +// read local attribute value request structure + +/** + * @brief Structure representing the BLE request to get a local attribute value. + * + * This structure is used to define the parameters for a BLE request to get a local attribute value, + * including the attribute handle. + */ +typedef struct rsi_ble_get_local_att_value_s { + /** Attribute handle */ + uint16_t handle; +} rsi_ble_get_local_att_value_t; + +/** + * @brief Structure representing the BLE GATT read response. + * + * This structure is used to define the parameters for a BLE GATT read response, + * including the remote device address, the type of the read response, reserved field for future use, + * the length of the attribute value, and the attribute value itself. + */ +typedef struct rsi_ble_gatt_read_response_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Type of the read response */ + uint8_t type; + /** Reserved for future use */ + uint8_t reserved; + /** Attribute value length */ + uint16_t data_len; + /** Attribute value (data) */ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_gatt_read_response_t; + +// Att write/ execute write response cmd = 0x010A + +/** + * @brief Structure representing the BLE GATT write response. + * + * This structure is used to define the parameters for a BLE GATT write response, + * including the remote device address and the response type. + */ +typedef struct rsi_ble_gatt_write_response_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Response type */ + uint8_t type; +} rsi_ble_gatt_write_response_t; + +// Att prepare write response cmd = 0x010B + +/** + * @brief Structure representing the BLE GATT prepare write response. + * + * This structure is used to define the parameters for a BLE GATT prepare write response, + * including the remote device address, the attribute handle, the attribute value offset, + * the length of the attribute value, and the attribute value itself. + */ +typedef struct rsi_ble_gatt_prepare_write_response_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint16_t handle; + /** Attribute value offset */ + uint16_t offset; + /** Attribute value length */ + uint16_t data_len; + /** Attribute value (data) */ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_gatt_prepare_write_response_t; + +/** + * @brief Structure representing the BLE command to set the local Identity Resolving Key (IRK). + * + * This structure is used to define the parameters for a BLE command to set the local IRK, + * including the local device IRK. + */ +typedef struct rsi_ble_set_local_irk_s { + /** Local device IRK (16 bytes) */ + uint8_t irk[16]; +} rsi_ble_set_local_irk_t; + +// BLE GAP extended callback ids +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/** + * + * @brief Enumeration representing the BLE GAP extended callback types. + * + * This enumeration defines the possible callback types for the BLE GAP extended feature. + * + */ +typedef enum rsi_ble_gap_extended_callbacks_s { + /** Callback type for remote device information events */ + RSI_BLE_ON_REMOTE_DEVICE_INFORMATION = 1, + /** Callback type for RCP (Remote Control Protocol) events */ + RSI_BLE_ON_RCP_EVENT = 2, +} rsi_ble_gap_extended_callbacks_t; +//attribute codes +/// Attribute Protocol (ATT) Exchange MTU request. +#define RSI_BLE_ATT_EXCHANGE_MTU_REQUEST 0x02 +/// Attribute Protocol (ATT) Find Information request. +#define RSI_BLE_ATT_FIND_INFORMATION_REQUEST 0x04 +/// Attribute Protocol (ATT) Find By Type Value request. +#define RSI_BLE_ATT_FIND_BY_TYPE_VALUE_REQUEST 0x06 +/// Attribute Protocol (ATT) Read By Type request. +#define RSI_BLE_ATT_READ_BY_TYPE_REQUEST 0x08 +/// Attribute Protocol (ATT) Read request. +#define RSI_BLE_ATT_READ_REQUEST 0x0A +/// Attribute Protocol (ATT) Read Blob request. +#define RSI_BLE_ATT_READ_BLOB_REQUEST 0x0C +/// Attribute Protocol (ATT) Read Multiple request. +#define RSI_BLE_ATT_READ_MULTIPLE_REQUEST 0x0E +/// Attribute Protocol (ATT) Read By Group Type request. +#define RSI_BLE_ATT_READ_BY_GROUP_TYPE_REQUEST 0x10 +/// Attribute Protocol (ATT) Write request. +#define RSI_BLE_ATT_WRITE_REQUEST 0x12 +/// Attribute Protocol (ATT) Prepare Write request. +#define RSI_BLE_ATT_PREPARE_WRITE_REQUEST 0x16 +/// Attribute Protocol (ATT) Execute Write request. +#define RSI_BLE_ATT_EXECUTE_WRITE_REQUEST 0x18 +/** @} */ + +// Att error response cmd = 0x00C1 + +/** + * @brief Structure representing the BLE attribute error response. + * + * This structure is used to define the parameters for a BLE event + * that involves an error response for an attribute operation from a remote device. + */ +typedef struct rsi_ble_att_error_response_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** The request opcode for the BLE operation */ + uint8_t req_opcode; + /** The attribute handle for the Bluetooth Low Energy (BLE) device */ + uint16_t att_handle; + /** The error code for the operation */ + uint8_t err_code; +} rsi_ble_att_error_response_t; + +/** + * @brief Structure representing the BLE GATT remove service request. + * + * This structure is used to define the parameters for a BLE event + * that involves removing a GATT service from a remote device. + */ +typedef struct rsi_ble_gatt_remove_serv_s { + /** Service handler */ + uint32_t serv_hndler; +} rsi_ble_gatt_remove_serv_t; + +/** + * @brief Structure representing the BLE GATT command to remove an attribute. + * + * This structure is used to define the parameters for a BLE GATT command to remove an attribute, + * including the service handler and the attribute handle. + */ +typedef struct rsi_ble_gatt_remove_att_s { + /** Service handler */ + uint32_t serv_hndler; + /** Attribute handle */ + uint16_t att_hndl; +} rsi_ble_gatt_remove_att_t; + +// rf type command structure + +/** + * @brief Structure representing the BLE vendor-specific RF type command. + * + * This structure is used to define the parameters for a BLE vendor-specific RF type command, + * including the opcode and the BLE power index. + */ +typedef struct rsi_ble_vendor_rf_type_s { + /** Opcode */ + uint8_t opcode[2]; + /** BLE power index */ + uint8_t ble_power_index; +} rsi_ble_vendor_rf_type_t; + +// rf type command structure + +/** + * @brief Structure representing the BLE MTU exchange request. + * + * This structure is used to define the parameters for a BLE MTU exchange request, + * including the remote device address and the requested MTU size. + */ +typedef struct rsi_ble_mtu_exchange_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Requested MTU size */ + uint16_t req_mtu_size; +} rsi_ble_mtu_exchange_t; + +// mtu exchange resp command structure + +/** + * @brief Structure representing the BLE MTU exchange response. + * + * This structure is used to define the parameters for a BLE MTU exchange response, + * including the Bluetooth device address of the peer device and the requested MTU size from the peer device. + */ +typedef struct rsi_ble_mtu_exchange_resp_s { + /** The Bluetooth device address of the peer device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** The requested MTU size from the peer device */ + uint16_t req_mtu_size; +} rsi_ble_mtu_exchange_resp_t; + +/** + * @brief Structure representing the BLE Advertising Extensions (AE) command to get the supported number of advertising sets. + * + * This structure is used to define the parameters for a BLE AE command to get the supported number of advertising sets, + * including a reserved field. + */ +typedef struct rsi_ble_ae_get_supported_no_of_adv_sets_s { + /** Reserved field */ + uint16_t reserved; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_get_supported_no_of_adv_sets_t; + +/** + * @brief Structure representing the BLE Advertising Extensions (AE) command to read the supported maximum advertising data. + * + * This structure is used to define the parameters for a BLE AE command to read the supported maximum advertising data, + * including a reserved field for future use or alignment. + */ +typedef struct rsi_ble_ae_read_supported_max_adv_data_s { + /** Reserved field for future use or alignment */ + uint16_t reserved; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_read_supported_max_adv_data_t; + +// AE Set Random Address (cmd), cmd_ix = + +/** + * @brief Structure representing the BLE Advertising Extensions (AE) command to set a random address. + * + * This structure is used to define the parameters for a BLE AE command to set a random address, + * including the advertising handle and the random address. + */ +typedef struct rsi_ble_ae_set_random_address_s { + /** Advertising_Handle, used to identify an advertising set, Range: 0x00 to 0xEF */ + uint8_t adv_handle; + /** Random_Address, The Random Address may be of either Static Address or Private Address */ + uint8_t addr[RSI_DEV_ADDR_LEN]; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_set_random_address_t; + +//! AE Advertising Params +typedef struct ae_adv_params_s { + /** uint8_t, Advertising Handle, Used to identify an Advertising set , Range : 0x00 to 0xEF */ + uint8_t adv_handle; + /** + * uint16_t, Advertising Event Properties, indicates the properties of Advertising Event + * --------------------------------------------------------------------------------------------------------- + * | Bit Number | Parameter Description | + * ----------------------|----------------------------------------------------------------------------------- + * | 0 | Connectable Advertising | + * | 1 | Scannable Advertising | + * | 2 | Direct Advertising | + * | 3 | High Duty cycle Directed Connectable advertising (≤ 3.75 ms Advertising interval)| + * | 4 | Use legacy advertising PDUs | + * | 5 | Omit advertiser's address from all PDUs("anonymous advertising") | + * | 6 | Include Tx Power in the extended header of at least one advertising PDU | + * */ + uint16_t adv_event_prop; + /** uint32_t, Primary Advertising Interval Minimum, Minimum advertising interval for undirected and low duty cycle directed advertising */ + uint32_t primary_adv_intterval_min : 24; + /** uint32_t, Primary Advertising Interval Maximum, Maximum advertising interval for undirected and low duty cycle directed advertising + primary_adv_intterval_min <= primary_adv_intterval_max */ + uint32_t primary_adv_intterval_max : 24; + /** uint8_t, Primary Advertising Channel Map, It specifies on which channel it shall advertise + Bit Number Parameter Description + 0 Channel 37 shall be used + 1 Channel 38 Shall be used + 2 Channel 39 shall be used + */ + uint8_t primary_adv_chnl_map; + /** + uint8_t, Own_Address_type, Indicates the type of the Address + 0x00 - Public Device Address + 0x01 - Random Device Address + 0x02 - Controller generates the Resolvable Private Address based on the local + IRK from the resolving list. If the resolving list contains no matching + entry, use the public address + 0x03 - Controller generates the Resolvable Private Address based on the local + IRK from the resolving list. If the resolving list contains no matching + entry, use the random address from LE_Set_Advertising_Set_Random_Address + */ + uint8_t own_addr_type; + /** uint8_t, Peer_Address_Type, Specifies Peer Address Type + 0x00 - Public Device Address or Public Identity Address + 0x01 - Random Device Address or Random (static) Identity Address + */ + uint8_t peer_addr_type; + /** uint8[6], Peer_Device_Address, Address of the Peer_Address_Type */ + uint8_t peer_dev_addr[RSI_DEV_ADDR_LEN]; + /** uint8_t, Advertising_Filter_Policy + 0x00 - Process scan and connection requests from all devices (i.e., the Filter Accept List is not in use) + 0x01 - Process connection requests from all devices and scan requests only from devices that are in the Filter Accept List. + 0x02 - Process scan requests from all devices and connection requests only from devices that are in the Filter Accept List. + 0x03 - Process scan and connection requests only from devices in the Filter Accept List. + */ + uint8_t adv_filter_policy; + /** uint8_t Advertising_TX_Power, Advertising TX Power ranges from -127 to +20 and units are in dBm */ + uint8_t adv_tx_power; + /** uint8_t Primary_Advertising_PHY, This parameter specifies the PHY used for the periodic advertising. + 0x01 - Advertiser PHY is LE 1M + 0x03 - Advertiser PHY is LE Coded + */ + uint8_t primary_adv_phy; + /** uint8_t Secondary_Advertising_Max_Skip + 0x00 AUX_ADV_IND shall be sent prior to the next advertising event + 0x01 to 0xFF Maximum advertising events the Controller can skip before sending the AUX_ADV_IND packets on the secondary advertising physical channel + */ + uint8_t sec_adv_max_skip; + /** uint8_t Secondary_Advertising_PHY, This parameter specifies the PHY used for the periodic advertising. + 0x01 - Advertiser PHY is LE 1M + 0x02 - Advertiser PHY is LE 2M + 0x03 - Advertiser PHY is LE Coded + */ + uint8_t sec_adv_phy; + /** uint8_t Advertising_Sid, Value of the Advertising SID subfield in the ADI field of the PDU, Range : 0x00 to 0x0F */ + uint8_t adv_sid; + /** uint8_t Scan Request Notification Enable + 0x00 Scan request notifications disabled + 0x01 Scan request notifications enabled + */ + uint8_t scan_req_notify_enable; + +} SL_ATTRIBUTE_PACKED rsi_ble_ae_adv_params_t; + +// AE adv,scan_rsp and periodic data + +/** + * @brief Structure representing the AE (Application Event) data for BLE. + */ +typedef struct rsi_ble_ae_data_s { + + /** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + + /// Advertising Extension (AE) advertising data. +#define AE_ADV_DATA 0x01 + /// Advertising Extension (AE) scan response data. +#define AE_SCAN_RSP_DATA 0x02 + /** @} */ + /** uint8_t AE_ADV_DATA_TYPE 1, AE_PERIODIC_ADV_DATA_TYPE 2, AE_SCAN_RSP_DATA_TYPE 3 */ + uint8_t type; + /** uint8_t Advertising Handle, used to identify an Advertising set, Ranges from 0x00 to 0xEF */ + uint8_t adv_handle; + /** uint8_t Operation + 0x00 - Intermediate fragment of fragmented extended advertising data + 0x01 - First fragment of fragmented extended advertising data + 0x02 - Last fragment of fragmented extended advertising data + 0x03 - Complete extended advertising data + 0x04 - Unchanged data (just update the Advertising DID) + */ + uint8_t operation; + /** + uint8_t Fragment_Preference, Specifies the controller on where to fragment the Host advertising Data + 0x00 - The Controller may fragment all Host advertising data + 0x01 - The Controller should not fragment or should minimize fragmentation of Host advertising data + */ + uint8_t frag_pref; + /** uint8_t Data Length, Specifies Advertising_Data_Length , This parameter ranges from 0 to 251 */ + uint8_t data_len; + /** uint8_t Data ,Specifies Advertising_Data. */ + uint8_t data[0xC8]; //FIXME +} SL_ATTRIBUTE_PACKED rsi_ble_ae_data_t; + +//! AE Advertising enable +typedef struct rsi_ble_ae_adv_enabel_s { + /** + uint8_t Enable, This parameter specifies whether to disable or Enable Advertising + 0x00 - Advertising is disabled + 0x01 - Advertising is Enabled + */ + uint8_t enable; + /** + uint8_t Num_of_Sets , Indicates the number of Advertising sets to be disabled or enabled for Advertising + 0x00 - Disable all advertising sets + 0x01 to 0x3F - Number of advertising sets to enable or disable + */ + uint8_t no_of_sets; + /** uint8_t Advertising_Handle, used to identify Advertising set, Ranges from 0x00 to 0xEF */ + uint8_t adv_handle; + /** + uint16_t Duration, specifies the duration to continue advertising + 0x00 - No Advertising + 0x0001 to 0xFFFF , Advertising Duration + */ + uint16_t duration; + /** uint8_t Maximum Extended Advertising Events, It specifies the Maximum number of extended advertising events the Controller shall + attempt to send prior to terminating the extended advertising */ + uint8_t max_ae_events; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_adv_enable_t; + +//AE adv set clear/remove + +/** + * @brief Structure for Advertising Event (AE) Advertisement (ADV) Set, Clear, or Remove. + */ +typedef struct rsi_ble_ae_adv_set_clear_or_remove_s { + + /** + type - Specifies whether to remove or clear the advertising sets. + {1} - clear + {2} - remove + */ + uint8_t type; + /** uint8_t Advertising_Handle, used to identify Advertising set, Ranges from 0x00 to 0xEF */ + uint8_t adv_handle; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_adv_set_clear_or_remove_t; + +//AE periodic adv params + +/** + * @brief Structure representing the parameters for periodic advertising in BLE. + */ +typedef struct ae_periodic_adv_params { + + /** uint8_t, Advertising Handle , this parameter identifies the advertising set whose periodic advertising parameters are being configured + * Rang : 0x00 to 0xEF */ + uint8_t adv_handle; + /** uint16_t, Minimum Interval,Minimum advertising interval for periodic advertising.Range: 0x0006 to 0xFFFF */ + uint16_t min_interval; + /**uint16_t, Maximum Interval,Maximum advertising interval for periodic advertising.Range: 0x0006 to 0xFFFF */ + uint16_t max_interval; + /** uint16_t, Periodic Advertising Properties, this parameter indicates which fields should be included in the advertising packet + * Bit Number, 6: Include TxPower in the advertising PDU + * All other Values - Reserved For future use */ + uint16_t properties; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_periodic_adv_params_t; + +//AE periodic adv enable + +/** + * @brief Structure representing the enable/disable state of periodic advertising. + */ +typedef struct ae_periodic_adv_enable { + + /** uint8_t, enable, If this parameter is set Periodic Advertising starts + * 0 - Enable Periodic Advertising + * 1 - Include the ADI field in AUX_SYNC_IND PDUs +*/ + uint8_t enable; + /** uint8_t, Advertising Handle, Used to identify an advertising set + * Range : 0x00 to 0xEF +*/ + uint8_t adv_handle; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_periodic_adv_enable_t; + +/** + * @brief Structure representing the scan parameters for Active Energy (AE) scanning. + */ +typedef struct ae_scan_params_s { + /** uint8_t, Scan Type, this parameter specifies the type of scan to perform + * 0x00 - Passive Scanning. No scan request PDUs shall be sent. + * 0x01 - Active Scanning. Scan request PDUs may be sent. +*/ + uint8_t ScanType; + /** uint16_t, Scan Interval, this parameter is a recommendation from the Host on how frequently the Controller should scan + * Range : 0x0004 to 0xFFFF */ + uint16_t ScanInterval; + /** uint16_t, Scan Window, this parameter is a recommendation from the Host on how long the Controller should scan + * Range : 0x0004 to 0xFFFF */ + uint16_t ScanWindow; +} SL_ATTRIBUTE_PACKED ae_scan_params_t; + +//AE set sacn params +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ +/// Indicates the number of supported scanning physical channels. +#define SUPPORTED_SCNNING_PHYS 2 +/** @} */ +/** + * @brief Structure to set the scan parameters for BLE Active Scanning. + */ +typedef struct rsi_ble_ae_set_scan_params_s { + + /** unit8_t,The Own Address Type parameter indicates the type of address being used in the scan request packets + * Value Parameter Description + * 0x00 Public Device Address + * 0x01 Random Device Address + * 0x02 Controller generates the Resolvable Private Address based on the local IRK from the resolving list. + * If the resolving list contains no matching entry, then use the public address. + * 0x03 Controller generates the Resolvable Private Address based on the local IRK from the resolving list. + * If the resolving list contains no matching entry, then use the random address from LE_Set_Random_Address. + * All other values Reserved for future use + * + */ + uint8_t own_addr_type; + /** uint8_t, It is used to determine whether the Filter Accept List is used + * + * 0x00 Basic unfiltered scanning filter policy + * 0x01 Basic filtered scanning filter policy + * 0x02 Extended unfiltered scanning filter policy + * 0x03 Extended filtered scanning filter policy + * All other values Reserved for future use + */ + uint8_t scanning_filter_policy; + /** uint8_t, The Scanning_PHYs parameter indicates the PHY(s) on which the advertising packets should be + received on the primary advertising physical channel. + * + * 0 Scan advertisements on the LE 1M PHY + * 2 Scan advertisements on the LE Coded PHY + * All other bits Reserved for future use + */ + uint8_t scanning_phys; + /** ScanParams is an array of variable of structure ae_scan_params_s */ + ae_scan_params_t ScanParams[SUPPORTED_SCNNING_PHYS]; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_set_scan_params_t; + +//AE set scan enable + +/** + * @brief Structure to configure BLE scanning parameters. + * + * This structure is used to set various parameters for enabling or disabling scanning + * in the module. It allows the configuration of scan enablement, + * duplicate filtering, scan duration, and scan period. + */ +typedef struct rsi_ble_ae_set_scan_enable_s { + + /** uint8_t, Enable, this Parameter determines whether scanning is enabled or disabled + * + * 0x00 Scanning disabled + * 0x01 Scanning enabled + * All other values Reserved for future use + */ + uint8_t enable; + /** uint8_t, Filter duplicates, this parameter controls whether the Link Layer should filter out duplicate advertising reports + * to the Host or if the Link Layer should generate advertising reports for each packet received + * + * 0x00 Duplicate Filtering Disabled + * 0x01 Duplicate Filtering Enabled + * 0x02 Duplicate filtering enabled, reset for each scan period + * All other Values Reserved for future use + */ + uint8_t filter_duplicates; + /** uint16_t, Duration, The duration of a scan period refers to the time spent scanning on both the primary and secondary advertising physical channels + * Range : 0x0001 to 0xFFFF + */ + uint16_t duration; + /** uint16_t, Period , Time interval from when the Controller started its last Scan_Duration until it begins the subsequent Scan_Duration + * Range : 0x0001 to 0xFFFF +*/ + uint16_t period; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_set_scan_enable_t; + +/** + * + * @brief Structure representing the parameters for setting periodic advertising and creating synchronization. + * This structure is used in BLE operations to configure periodic advertising and create synchronization. + */ +typedef struct rsi_ble_ae_set_periodic_adv_create_sync_s { + + /** uint8_t, Options field, The Options parameter is used to determine whether the Periodic Advertiser List is used + + Bit_NUmber parameter description + + * 0 0: Use the Advertising_SID, Advertiser_Address_Type, and Advertiser_Address parameters to determine which advertiser to listen to + 1: Use the Periodic Advertiser List to determine which advertiser to listen to. + + * 1 0: Reporting initially enabled + 1: Reporting initially disabled + + * 2 0: Duplicate filtering initially disabled + 1: Duplicate filtering initially enabled + + All other bits Reserved for future use **/ + uint8_t options; + /** uint8_t, Advertising SID subfield in the ADI field used to identify the Periodic Advertising. + * Range : 0x00 to 0x0F, All other bits - Reserved for future use +*/ + uint8_t adv_sid; + /** uint8_t, Advertiser Address Type, this parameter indicates the type of address being used in the connection request packets + * + * 0x00 Public Device Address or Public Identity Address + * 0x01 Random Device Address or Random (static) Identity Address + * All other values Reserved for future use + */ + uint8_t adv_addr_type; + /** uint8_t, Advertiser Address[6]*/ + uint8_t adv_addr[RSI_DEV_ADDR_LEN]; + /** uint16_t, Skip,The maximum number of periodic advertising events that can be skipped after a successful receive + * Range : 0x0000 to 0x01F3 */ + uint16_t skip; + /** uint16_t, Sync Timeout, Synchronization timeout for the periodic advertising train + * Range : 0x000A to 0x4000 */ + uint16_t sync_timeout; + /** Reserved for future use */ + uint8_t reserved; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_set_periodic_adv_create_sync_t; +/** + * + * @brief Structure to set periodic advertising and terminate synchronization. + */ +typedef struct rsi_ble_ae_set_periodic_adv_terminate_sync_s { + + /** uint16_t, Sync Handle, identifies the periodic Advertising Train + * Range : 0x0000 to 0x0EFF*/ + uint16_t sync_handle; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_set_periodic_adv_terminate_sync_t; + +//AE set periodic sync(create/terminate or cancel) params +/** + * @brief Structure representing the BLE Advertising Extension(AE) set periodic synchronization. + * + * This structure is used to define the parameters for setting periodic synchronization + * for Advertising Extension in a BLE device. + */ +typedef struct rsi_ble_ae_set_periodic_sync_s { + /** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + + /// Command to create a periodic synchronization for Advertising Extension. +#define BLE_AE_PERIODIC_SYNC_CREATE 0x01 + /// Command to cancel the creation of a periodic synchronization for Advertising Extension. +#define BLE_AE_PERIODIC_SYNC_CREATE_CANCEL 0x02 + /// Command to terminate a periodic synchronization for Advertising Extension. +#define BLE_AE_PERIODIC_SYNC_TERMINATE 0x03 + /** @} */ + uint8_t type; ///< Type of the periodic synchronization command. + union { + rsi_ble_ae_set_periodic_adv_create_sync_t create_sync; ///< Parameters for creating periodic synchronization. + rsi_ble_ae_set_periodic_adv_terminate_sync_t + terminate_sync; ///< Parameters for terminating periodic synchronization. + } SL_ATTRIBUTE_PACKED sync_type; ///< Union for periodic synchronization parameters. +} SL_ATTRIBUTE_PACKED rsi_ble_ae_set_periodic_sync_t; +//#pragma pack(pop) +// AE add/remove/clear dev to/from periodic adv list + +/** + * @brief Structure representing the AE (Advertising extension) device to periodic list. + */ +typedef struct rsi_ble_ae_dev_to_periodic_list_s { + + /** uint8_t, Type + * Type Values Description + * 1 Adding Device to Periodic Advertising list + * 2 Removing Device from Periodic Advertising list + * 3 Clearing Periodic Advertising List +*/ + uint8_t type; + /** uint8_t, Advertiser Address Type, this parameter indicates the type of address being used in the connection request packets + * + * 0x00 Public Device Address or Public Identity Address + * 0x01 Random Device Address or Random (static) Identity Address + * All other values Reserved for future use +*/ + uint8_t adv_addr_type; + /** uint8_t, Advertiser Address[6]*/ + uint8_t adv_addr[RSI_DEV_ADDR_LEN]; + /** uint8_t, Advertising_Sid, Value of the Advertising SID subfield in the ADI field of the PDU, Range : 0x00 to 0x0F*/ + uint8_t adv_sid; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_dev_to_periodic_list_t; + +/** + * @brief Structure representing connection initiation parameters. + * + * This structure is used to define various parameters required for initiating a BLE + * connection. It includes parameters for scan intervals, scan window, connection + * intervals, peripheral latency, supervision timeout, and minimum and maximum length of the connection events. + */ +typedef struct rsi_ble_initiation_params_s { + + /** uint16_t, ScanInterval, It is the Time interval from when the Controller started its last scan until it begins the subsequent scan on the primary + * advertising physical channel. Range : 0x0004 to 0xFFFF */ + uint16_t ScanInterval; + /** uint16_t, Scan Window parameter is a recommendation from the host on how long the controller should scan. + * Range : 0x0004 to 0xFFFF */ + uint16_t ScanWindow; + /** uint16_t, Connection interval minimum parameter defines the minimum allowed connection interval. + * Range: 0x0006 to 0x0C80 */ + uint16_t ConnIntervalMin; + /** uint16_t, Connection interval maximum parameter defines the maximum allowed connection interval. + * Range: 0x0006 to 0x0C80*/ + uint16_t ConnIntervalMax; + /** uint16_t, Peripheral Latency or Maximum Latency parameter defines the maximum allowed Peripheral latency. + * Range: 0x0000 to 0x01F3 */ + uint16_t ConnLatency; + /** uint16_t, Connection Timeout or Supervision Timeout parameter defines the link supervision timeout for the connection. + * Range: 0x000A to 0x0C80*/ + uint16_t ConnSTO; //SuperVisionTimeout + /** uint16_t,The Min CE Length parameter provide the Controller with the expected minimum length of the connection events. + * Range: 0x0000 to 0xFFFF */ + uint16_t MinCELen; + /** uint16_t,The Max CE Length parameter provide the controller with the expected maximum length of the connection events. + * Range: 0x0000 to 0xFFFF */ + uint16_t MaxCELen; +} SL_ATTRIBUTE_PACKED rsi_ble_initiation_params_t; + +// AE extended create connect + +/** + * @brief Structure representing the extended create connect command for BLE AE. + */ +typedef struct rsi_ble_ae_extended_create_connect_s { + + /** uint8_t, Initiator Filter Policy,It is used to determine whether the Filter Accept List is used + * Value Parameter Description + * 0x00 Filter Accept List is not used to determine which advertiser to connect to Peer_Address_Type and Peer_Address shall be used. + * 0x01 Filter Accept List is used to determine which advertiser to connect to Peer_Address_Type and Peer_Address shall be ignored. + * All other values Reserved for future use + */ + uint8_t initiator_filter_policy; + /** uint8_t, Own Address Type, this parameter indicates the type of address being used in the connection request packets + * + * Value Parameter Description + * 0x00 Public Device Address + * 0x01 Random Device Address + * 0x02 Controller generates the Resolvable Private Address based on the local IRK from the resolving list. + * If the resolving list contains no matching entry, then use the public address. + * 0x03 Controller generates the Resolvable Private Address based on the local IRK from the resolving list. + * If the resolving list contains no matching entry, then use the random address from the most recent successful + * HCI_LE_Set_Random_Address command. + * All other values Reserved for future use + */ + uint8_t own_addr_type; + /** uint8_t, Remote Address Type or Peer Address Type, this parameter indicates the type of address used in the + connectable advertisement sent by the peer + * Value Parameter Description + * 0x00 Public Device Address or Public Identity Address + * 0x01 Random Device Address or Random (static) Identity Address + * All other values Reserved for future use + */ + uint8_t remote_addr_type; + /** uint8_t, Remote Address or Peer Address, this parameter indicates the Peer’s Public Device Address, + Random (static) Device Address, Non-Resolvable Private Address, or Resolvable Private Address depending on the Peer_Address_Type parameter */ + uint8_t remote_addr[RSI_DEV_ADDR_LEN]; + /** uint8_t, Initiating PHYs, this parameter indicates the PHY(s) on which the advertising packets should be received on the + primary advertising physical channel and the PHYs for which connection parameters have been specified + * Bit number Parameter Description + * 0 Scan connectable advertisements on the LE 1M PHY. Connection parameters for the LE 1M PHY are provided. + * 1 Connection parameters for the LE 2M PHY are provided. + * 2 Scan connectable advertisements on the LE Coded PHY. Connection parameters for the LE Coded PHY are provided. + * All other bits Reserved for future use + */ + uint8_t init_phys; + /** init_params is an array of Variable of Structure rsi_ble_initiation_params_s */ + rsi_ble_initiation_params_t init_params[3]; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_extended_create_connect_t; + +// LE Read Transmit Power +/** + * @brief Structure representing the BLE transmit power. + */ +typedef struct rsi_ble_tx_pwr_s { + /** int8_t, Minimum TX Power, Range: -127 to +20 */ + int8_t min_tx_pwr; + /** int8_t, Maximum TX Power, Range: -127 to +20 */ + int8_t max_tx_pwr; +} SL_ATTRIBUTE_PACKED rsi_ble_tx_pwr_t; + +// Query Rf Path Compensation + +/** + * @brief Structure to hold the information for querying RF path compensation. + */ +typedef struct rsi_ble_query_rf_path_comp_s { + + /** int16_t, RF TX Path Compensation Value, Range: -128.0 dB (0xFB00) to 128.0 dB (0x0500) */ + int16_t tx_path_value; + /** int16_t, RF RX Path Compensation Value, Range: -128.0 dB (0xFB00) to 128.0 dB (0x0500) */ + int16_t rx_path_value; +} SL_ATTRIBUTE_PACKED rsi_ble_query_rf_path_comp_t; + +// write Rf Path Compensation +/** + * @brief Structure representing the parameters for writing RF path compensation values. + */ +typedef struct rsi_ble_write_rf_path_comp_s { + /** int16_t, RF TX Path Compensation Value, Range: -128.0 dB (0xFB00) to 128.0 dB (0x0500) */ + int16_t tx_path_value; + /** int16_t, RF RX Path Compensation Value, Range: -128.0 dB (0xFB00) to 128.0 dB (0x0500)*/ + int16_t rx_path_value; +} SL_ATTRIBUTE_PACKED rsi_ble_write_rf_path_comp_t; + +/** + * @brief Structure representing the BLE Advertising Extensions (AE) Protocol Data Unit (PDU). + * + * This structure is used to define the BLE Advertising Extensions PDU. + * It contains a command sub-opcode and a union of various possible PDU types related to + * advertising, scanning, and connection parameters. + * + */ +typedef struct rsi_ble_ae_pdu { + /** Command sub-opcode */ + uint16_t cmd_sub_opcode; + + /** Union of various possible PDU types */ + union { + /** Supported number of advertising sets */ + rsi_ble_ae_get_supported_no_of_adv_sets_t ae_supported_no_of_sets; + /** Supported maximum advertising data */ + rsi_ble_ae_read_supported_max_adv_data_t ae_supported_max_data; + /** Set random address */ + rsi_ble_ae_set_random_address_t ae_random_address; + /** Advertising parameters */ + rsi_ble_ae_adv_params_t ae_adv_params; + /** Advertising or scan response data */ + rsi_ble_ae_data_t ae_adv_or_scn_rsp_data; + /** Advertising enable */ + rsi_ble_ae_adv_enable_t ae_adv_enable; + /** Advertising set clear or remove */ + rsi_ble_ae_adv_set_clear_or_remove_t ae_adv_set_clear_or_remove; + /** Periodic advertising parameters */ + rsi_ble_ae_periodic_adv_params_t ae_periodic_adv_params; + /** Periodic advertising enable */ + rsi_ble_ae_periodic_adv_enable_t ae_periodic_adv_enable; + /** Scan parameters */ + rsi_ble_ae_set_scan_params_t ae_scan_params; + /** Scan enable */ + rsi_ble_ae_set_scan_enable_t ae_scan_enable; + /** Periodic sync settings */ + rsi_ble_ae_set_periodic_sync_t ae_periodic_sync; + /** Device to periodic list */ + rsi_ble_ae_dev_to_periodic_list_t dev_to_periodic_list; + /** Extended create connection */ + rsi_ble_ae_extended_create_connect_t extended_create_conn; + } SL_ATTRIBUTE_PACKED pdu_type; +} SL_ATTRIBUTE_PACKED rsi_ble_ae_pdu_t; + +/** @} */ + +/** + * \addtogroup rsi_ble_cb_s_group rsi_ble_cb_s Driver BLE control block + * @brief Driver BLE control block group + * + * @ingroup BT_BLE_TYPES + * @{ + */ + +/** + * @brief Structure representing the BLE control block. + * + * This structure contains various callback functions for handling BLE events, + * including GAP, SMP, GATT, L2CAP, and AE events. + */ +struct rsi_ble_cb_s { + + /** + * \addtogroup gap_callbacks_group GAP Callbacks Group + * @brief Group for GAP callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + + /** + * @brief Advertising report event callback. + */ + rsi_ble_on_adv_report_event_t ble_on_adv_report_event; + + /** + * @brief Connection status event callback. + */ + rsi_ble_on_connect_t ble_on_conn_status_event; + + /** + * @brief Disconnect event callback. + */ + rsi_ble_on_disconnect_t ble_on_disconnect_event; + + /** + * @brief LE ping payload timeout event callback. + */ + rsi_ble_on_le_ping_payload_timeout_t ble_on_le_ping_time_expired_event; + + /** + * @brief PHY update complete event callback. + */ + rsi_ble_on_phy_update_complete_t ble_on_phy_update_complete_event; + + /** + * @brief Data length update event callback. + */ + rsi_ble_on_data_length_update_t rsi_ble_on_data_length_update_event; + + /** + * @brief Enhanced connection status event callback. + */ + rsi_ble_on_enhance_connect_t ble_on_enhance_conn_status_event; + + /** + * @brief Directed advertising report event callback. + */ + rsi_ble_on_directed_adv_report_event_t ble_on_directed_adv_report_event; + + /** + * @brief Connection update complete event callback. + */ + rsi_ble_on_conn_update_complete_t ble_on_conn_update_complete_event; + + /** + * @brief Remote connection parameters request event callback. + */ + rsi_ble_on_remote_conn_params_request_t ble_on_remote_conn_params_request_event; + + /** @} */ // end of gap_callbacks_group + + /** + * \addtogroup gap_extended_callbacks_group GAP Extended Callbacks Group + * @brief Group for GAP Extended callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + /** + * @brief Remote device info event callback. + */ + rsi_ble_on_remote_device_info_t ble_on_remote_device_info_event; + + /** + * @brief Remote features event callback. + */ + rsi_ble_on_remote_features_t ble_on_remote_features_event; + + /** + * @brief LE more data request event callback. + */ + rsi_ble_on_le_more_data_req_t ble_on_le_more_data_req_event; + + /** @} */ // end of gap_extended_callbacks_group + + /** + * \addtogroup smp_callbacks_group SMP Callbacks Group + * @brief Group for SMP callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + /** + * @brief SMP request event callback. + */ + rsi_ble_on_smp_request_t ble_on_smp_request_event; + + /** + * @brief SMP response event callback. + */ + rsi_ble_on_smp_response_t ble_on_smp_response_event; + + /** + * @brief SMP passkey event callback. + */ + rsi_ble_on_smp_passkey_t ble_on_smp_passkey_event; + + /** + * @brief SMP failed event callback. + */ + rsi_ble_on_smp_failed_t ble_on_smp_fail_event; + + /** + * @brief SMP encryption started event callback. + */ + rsi_ble_on_encrypt_started_t ble_on_smp_encrypt_started; + + /** + * @brief SMP passkey display event callback. + */ + rsi_ble_on_smp_passkey_display_t ble_on_smp_passkey_display; + + /** + * @brief Secure connections passkey event callback. + */ + rsi_ble_on_sc_passkey_t ble_on_sc_passkey; + + /** + * @brief LE LTK request event callback. + */ + rsi_ble_on_le_ltk_req_event_t ble_on_le_ltk_req_event; + + /** + * @brief LE security keys event callback. + */ + rsi_ble_on_le_security_keys_t ble_on_le_security_keys_event; + + /** + * @brief Client SMP response event callback. + */ + rsi_ble_on_smp_response_t ble_on_cli_smp_response_event; + + /** + * @brief Secure connections method event callback. + */ + rsi_ble_on_sc_method_t ble_on_sc_method_event; + + /** @} */ // end of smp_callbacks_group + + /** + * \addtogroup gatt_callbacks_group GATT Callbacks Group + * @brief Group for GATT callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + /** + * @brief Profiles list response callback. + */ + rsi_ble_on_profiles_list_resp_t ble_on_profiles_list_resp; + + /** + * @brief Profile response callback. + */ + rsi_ble_on_profile_resp_t ble_on_profile_resp; + + /** + * @brief Characteristic services response callback. + */ + rsi_ble_on_char_services_resp_t ble_on_char_services_resp; + + /** + * @brief Included services response callback. + */ + rsi_ble_on_inc_services_resp_t ble_on_inc_services_resp; + + /** + * @brief Attribute description response callback. + */ + rsi_ble_on_att_desc_resp_t ble_on_att_desc_resp; + + /** + * @brief Read response callback. + */ + rsi_ble_on_read_resp_t ble_on_read_resp; + + /** + * @brief Write response callback. + */ + rsi_ble_on_write_resp_t ble_on_write_resp; + + /** + * @brief GATT write event callback. + */ + rsi_ble_on_gatt_write_event_t ble_on_gatt_events; + + /** + * @brief Prepare write event callback. + */ + rsi_ble_on_gatt_prepare_write_event_t ble_on_prepare_write_event; + + /** + * @brief Execute write event callback. + */ + rsi_ble_on_execute_write_event_t ble_on_execute_write_event; + + /** + * @brief Read request event callback. + */ + rsi_ble_on_read_req_event_t ble_on_read_req_event; + + /** + * @brief MTU event callback. + */ + rsi_ble_on_mtu_event_t ble_on_mtu_event; + + /** + * @brief GATT error response event callback. + */ + rsi_ble_on_gatt_error_resp_t ble_on_gatt_error_resp_event; + + /** + * @brief GATT descriptor value response event callback. + */ + rsi_ble_on_gatt_desc_val_event_t ble_on_gatt_desc_val_resp_event; + + /** + * @brief Profiles list event callback. + */ + rsi_ble_on_event_profiles_list_t ble_on_profiles_list_event; + + /** + * @brief Profile by UUID event callback. + */ + rsi_ble_on_event_profile_by_uuid_t ble_on_profile_by_uuid_event; + + /** + * @brief Read by characteristic services event callback. + */ + rsi_ble_on_event_read_by_char_services_t ble_on_read_by_char_services_event; + + /** + * @brief Read by included services event callback. + */ + rsi_ble_on_event_read_by_inc_services_t ble_on_read_by_inc_services_event; + + /** + * @brief Read attribute value event callback. + */ + rsi_ble_on_event_read_att_value_t ble_on_read_att_value_event; + + /** + * @brief Read response event callback. + */ + rsi_ble_on_event_read_resp_t ble_on_read_resp_event; + + /** + * @brief Write response event callback. + */ + rsi_ble_on_event_write_resp_t ble_on_write_resp_event; + + /** + * @brief Indicate confirmation event callback. + */ + rsi_ble_on_event_indicate_confirmation_t ble_on_indicate_confirmation_event; + + /** + * @brief Prepare write response event callback. + */ + rsi_ble_on_event_prepare_write_resp_t ble_on_prepare_write_resp_event; + + /** @} */ // end of gatt_callbacks_group + + /** + * \addtogroup gatt_extended_callbacks_group GATT Extended Callbacks Group + * @brief Group for GATT extended callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + + /** + * @brief MTU exchange info event callback. + * @note extended + */ + rsi_ble_on_mtu_exchange_info_t ble_on_mtu_exchange_info_event; + + /** @} */ // end of gatt_extended_callbacks_group + + /** + * \addtogroup l2cap_callbacks_group L2CAP Callbacks Group + * @brief Group for L2CAP callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + /** + * @brief CBFC connection request event callback. + */ + rsi_ble_on_cbfc_conn_req_event_t ble_on_cbfc_conn_req_event; + + /** + * @brief CBFC connection complete event callback. + */ + rsi_ble_on_cbfc_conn_complete_event_t ble_on_cbfc_conn_complete_event; + + /** + * @brief CBFC receive data event callback. + */ + rsi_ble_on_cbfc_rx_data_event_t ble_on_cbfc_rx_data_event; + + /** + * @brief CBFC disconnect event callback. + */ + rsi_ble_on_cbfc_disconn_event_t ble_on_cbfc_disconn_event; + + /** @} */ // end of l2cap_callbacks_group + + /** + * \addtogroup chip_memory_status_callbacks_group Chip Memory Status Callbacks Group + * @brief Group for Chip memory status callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + + /** + * @brief Chip memory status event callback. + * @note rsi_ble_on_chip_memory_status_callbacks_register + */ + chip_ble_buffers_stats_handler_t ble_on_chip_memory_status_event; + + /** @} */ // end of chip_memory_status_callbacks_group + + /** + * \addtogroup ae_callbacks_group AE Callbacks Group + * @brief Group for AE callbacks. + * @ingroup rsi_ble_cb_s_group + * @{ + */ + /** + * @brief AE report complete event callback. + */ + rsi_ble_ae_report_complete_t ble_ae_report_complete_event; + + /** + * @brief AE periodic advertising sync established event callback. + */ + rsi_ble_ae_per_adv_sync_estbl_t ble_ae_per_adv_sync_estbl_event; + + /** + * @brief AE periodic advertising report event callback. + */ + rsi_ble_ae_per_adv_report_t ble_ae_per_adv_report_event; + + /** + * @brief AE periodic advertising sync lost event callback. + */ + rsi_ble_ae_per_adv_sync_lost_t ble_ae_per_adv_sync_lost_event; + + /** + * @brief AE scan timeout event callback. + */ + rsi_ble_ae_scan_timeout_t ble_ae_scan_timeout_event; + + /** + * @brief AE advertising set terminated event callback. + */ + rsi_ble_ae_adv_set_terminated_t ble_ae_adv_set_terminated_event; + + /** + * @brief AE scan request received event callback. + */ + rsi_ble_ae_scan_req_recvd_t ble_ae_scan_req_recvd_event; + + /** + * @brief RCP response received event callback. + * + */ + rsi_ble_on_rcp_resp_rcvd_t ble_on_rcp_resp_rcvd_event; + + /** @} */ // end of ae_callbacks_group +}; + +/** @} */ // end of rsi_ble_cb_s_group + +/****************************************************** + * * BLE internal function declarations + * ******************************************************/ +void rsi_ble_callbacks_handler(rsi_bt_cb_t *ble_cb, uint16_t rsp_type, uint8_t *payload, uint16_t payload_length); + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h new file mode 100644 index 000000000..14d7e5ad8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_apis.h @@ -0,0 +1,5795 @@ +/******************************************************************************* + * @file rsi_ble_apis.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_BLE_APIS_H +#define RSI_BLE_APIS_H + +#include "rsi_bt_common.h" + +/****************************************************** + * * Macros + * ******************************************************/ + +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ +/// Maximum number of response list for BLE. +#define RSI_BLE_MAX_RESP_LIST 0x05 +/// Maximum size of an advertising report. +#define RSI_MAX_ADV_REPORT_SIZE 31 +/// Size of the BLE passkey. +#define BLE_PASSKEY_SIZE 6 + +/// Defines the output power front end loss for BLE +#ifndef BLE_OUTPUT_POWER_FRONT_END_LOSS +#define BLE_OUTPUT_POWER_FRONT_END_LOSS 0 /* db */ +#endif + +/// Host descriptor length +#define RSI_HOST_DESC_LENGTH 16 + +/** @} */ + +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ + +/****************************************************** + * * Type Definitions + * ******************************************************/ + +/****************************************************** + * * Structures +******************************************************/ + +/** @addtogroup BT_BLE_EVENT_TYPES Event Types + * @{ */ + +// GAP Event structures + +//Advertise report event structure +/** + * @brief Structure representing a BLE advertising report event. + */ +typedef struct rsi_ble_event_adv_report_s { + /**Address type of the advertising device */ + uint8_t dev_addr_type; + /**Address of the advertising device*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**Raw advertisement data length*/ + uint8_t adv_data_len; + /**advertisement data*/ + uint8_t adv_data[RSI_MAX_ADV_REPORT_SIZE]; + /**Signal strength*/ + int8_t rssi; + /** Report type +- + 0x00 Connectable and scannable undirected advertising (ADV_IND) +- + 0x01 Connectable directed advertising (ADV_DIRECT_IND) +- + 0x02 Scannable undirected advertising (ADV_SCAN_IND) +- + 0x03 Non connectable undirected advertising (ADV_NONCONN_IND) +- + 0x04 Scan Response (SCAN_RSP) +- + All other values Reserved for future use*/ + uint8_t report_type; +} rsi_ble_event_adv_report_t; + +//Connection status event structure +/** + * @brief Structure representing the connection status event in the BLE module. + */ +typedef struct rsi_ble_event_conn_status_s { + /** Address type of the connected device */ + uint8_t dev_addr_type; + /** Address of the connected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Status of the connection - success/failure */ + uint16_t status; +} rsi_ble_event_conn_status_t; + +//enhance connection status event structure +/** + * @brief Structure representing the enhanced connection status event in the BLE module. + */ +typedef struct rsi_ble_event_enhnace_conn_status_s { + + /**Device address type of the Connected Remote Device*/ + uint8_t dev_addr_type; + /**Device address of the remote device.*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**Local Device resolvable address*/ + uint8_t local_resolvlable_addr[RSI_DEV_ADDR_LEN]; + /**Remote Device resolvable address*/ + uint8_t peer_resolvlable_addr[RSI_DEV_ADDR_LEN]; + /**The role of the device - central/ peripheral*/ + uint8_t role; + /**Connection interval used on this connection. Range: 0x0006 to 0x0C80*/ + uint16_t conn_interval; + /**Peripheral latency for the connection in number of connection events. Range: 0x0000 to 0x01F3*/ + uint16_t conn_latency; + /**Connection supervision timeout. Range: 0x000A to 0x0C80*/ + uint16_t supervision_timeout; + /**Only applicable for peripheral, for central this value is set to 0x00*/ + uint8_t master_clock_accuracy; + /**Status of the Connection - success/failure*/ + uint16_t status; +} rsi_ble_event_enhance_conn_status_t; + +//Disconnect event structure +/** + * @brief Disconnection event structure for BLE. + * + * This structure contains information about the disconnection event of a BLE device. + */ +typedef struct rsi_ble_event_disconnect_s { + /** Device address of the disconnected device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** The type of the disconnected device (LE) */ + uint8_t dev_type; +} rsi_ble_event_disconnect_t; + +//le ping timeout expired event structure +/** + * @brief Structure representing the BLE event for LE ping time expiration. + */ +typedef struct rsi_ble_event_le_ping_time_expired_s { + /**Device address of the disconnected device*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + +} rsi_ble_event_le_ping_time_expired_t; + +//le ltk request event Structure +/** + * @brief Structure representing a Bluetooth Low Energy (LE) Long Term Key (LTK) request event. + */ +typedef struct rsi_bt_event_le_ltk_request_s { + /**BD Address of the remote device*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**ediv of local device*/ + uint16_t localediv; + /**rand of local device*/ + uint8_t localrand[8]; + /**Address type of remote device*/ + uint8_t dev_addr_type; +} rsi_bt_event_le_ltk_request_t; + +//le security keys event Structure +/** + * @brief Structure representing the Bluetooth Low Energy (BLE) event for security keys. + */ +typedef struct rsi_bt_event_le_security_keys_s { + /**BD Address of the remote device*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**16 byte irk of the local device*/ + uint8_t local_irk[16]; + /**16 byte irk of the remote device*/ + uint8_t remote_irk[16]; + /**remote device ediv value*/ + uint16_t remote_ediv; + /**remote device rand value*/ + uint8_t remote_rand[16]; + /**remote device ltk value*/ + uint8_t remote_ltk[16]; + /**Identity address type - public/random +- + 0x00 --> Public Identity Address +- + 0x01 --> Random (static) Identity Address +- + All other values Reserved for future use*/ + uint8_t Identity_addr_type; + /**Identity address which is resolved after security keys exchange*/ + uint8_t Identity_addr[6]; + /**Device address type*/ + uint8_t dev_addr_type; +} rsi_bt_event_le_security_keys_t; + +//encryption enabled structure +/** + * @brief Structure to hold the event data for encryption enabled event. + */ +typedef struct rsi_bt_event_encryption_enabled_s { + /**Remote device Address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**Status of the Encryption +- + ENCRYPT_ENABLED BIT(0) --> To indicate or set encryption is enabled AUTH_LTK_OR_STK_ENC +- + BIT(1) --> To indicate or set Authenticated Pairing and Encryption UN_AUTH_LTK_OR_STK_ENC +- + BIT(2) --> To indicate or set UnAuthenticated pairing and Encryption AUTH_LTK_WITH_LE_SC_ENC +- + BIT(3) --> To indicate or set Authenticated Pairing and Enc with LE SC */ + uint8_t enabled; + /**BLE Secure Connections Enable/disable indication +- + 0 --> Disable +- + 1 --> Enable */ + uint8_t sc_enable; + /**Local device EDIV*/ + uint16_t localediv; + /**Local RAND*/ + uint8_t localrand[8]; + /**Local Long term Key*/ + uint8_t localltk[16]; + /**Remote Device Address type*/ + uint8_t dev_addr_type; +} rsi_bt_event_encryption_enabled_t; + +//SMP protocol structure +//SMP Request event structure +/** + * @brief Structure to hold the Security Manager Protocol (SMP) request event. + */ +typedef struct rsi_bt_event_smp_req_s { + /**address of remote device*/ + uint8_t dev_addr[6]; + /**auth req of remote device*/ + uint8_t auth_req; +} rsi_bt_event_smp_req_t; + +//SMP Response event structure +/** + * @brief Structure to hold the SMP response event data. + */ +typedef struct rsi_bt_event_smp_resp_s { + /**address of remote device*/ + uint8_t dev_addr[6]; + /**Device input output capability +- + 0x00 - Display Only +- + 0x01 - Display Yes/No +- + 0x02 - Keyboard Only +- + 0x03 - No Input No Output + 0x04 - Keyboard Display*/ + uint8_t io_cap; + /**Out Of the Band data*/ + uint8_t oob_data; + /**Authentication Request contains bonding type +- + MITM Request - BIT(2) +- + Secure Connections - BIT(3) +- + Keypress - BIT(4) +- + CT2 - BIT(5)*/ + uint8_t auth_req; + /**Minimum required key size*/ + uint8_t min_req_key_size; + /** Initiator generates/requires the no .of keys after successful paring +- + BIT(0) - EncKey: Initiator distributes the LTK followed by EDIV and Rand +- + BIT(1) - IdKey : Initiator distributes the IRK followed by its address +- + BIT(2) - Sign : Initiator distributes the CSRK +- + BIT(3) - BIT(7): Reserved for future use */ + uint8_t ini_key_distrb; + /** Responder generates/requires the no .of keys after successful paring +- + BIT(0) - EncKey: Responder distributes the LTK followed by EDIV and Rand +- + BIT(1) - IdKey : Responder distributes the IRK followed by its address +- + BIT(2) - Sign : Responder distributes the CSRK +- + BIT(3) - BIT(7): Reserved for future use */ + uint8_t resp_key_distrb; +} rsi_bt_event_smp_resp_t; + +//SMP passkey event structure +/** + * @brief Structure to hold the SMP passkey event data. + */ +typedef struct rsi_bt_event_smp_passkey_s { + /**address of remote device*/ + uint8_t dev_addr[6]; +} rsi_bt_event_smp_passkey_t; + +//SMP passkey display event structure +/** + * @brief Structure to hold the SMP passkey display event. + */ +typedef struct rsi_bt_event_smp_passkey_display_s { + /**address of remote device*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**This is the key required in pairing process( 6 bytes)*/ + uint8_t passkey[BLE_PASSKEY_SIZE]; +} rsi_bt_event_smp_passkey_display_t; + +//SC passkey display event structure +/** + * @brief Structure to hold the Secure Connections (SC) passkey event. + */ +typedef struct rsi_bt_event_sc_passkey_s { + /**address of remote device*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**Reserved for future use*/ + uint8_t reserved[2]; + /**This is the key required in pairing process*/ + uint32_t passkey; +} rsi_bt_event_sc_passkey_t; + +//SMP failed event structure +/** + * @brief Structure to hold the information related to a Bluetooth Low Energy (BLE) Security Manager Protocol (SMP) failed event. + */ +typedef struct rsi_bt_event_smp_failed_s { + /**device address of the disconnected device*/ + uint8_t dev_addr[6]; +} rsi_bt_event_smp_failed_t; + +//Security Methods event structure +/** + * @brief Structure to define the Bluetooth event security method. + */ +typedef struct rsi_bt_event_sc_method_s { + /**Security Method --> Justworks or Passkey +- + RSI_BT_LE_SC_JUST_WORKS 0x01 +- + RSI_BT_LE_SC_PASSKEY 0x02 */ + uint8_t sc_method; +} rsi_bt_event_sc_method_t; + +/** + * @brief Structure representing the BLE event for Cross Transport Key Derivation (CTKD). + * + * This structure is used to define the parameters for the BLE event related to Cross Transport Key Derivation, + * including the remote device address and the derived key. + */ +typedef struct rsi_bt_event_ctkd_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Derived key */ + uint8_t key[16]; +} rsi_ble_event_ctkd_t; + +// phy update complete event +/** + * @brief Structure to hold the BLE PHY update event information. + */ +typedef struct rsi_ble_event_phy_update_s { + + /**Device address of the remote device.*/ + uint8_t dev_addr[6]; + /**Transmission PHY rate(1 byte) +- + BIT(0) - The Host prefers to use the LE 1M transmitter PHY (possibly among others) +- + BIT(1) - The Host prefers to use the LE 2M transmitter PHY (possibly among others) +- + BIT(2) - The Host prefers to use the LE Coded transmitter PHY (possibly among others) +- + BIT(3) - BIT(7) Reserved for future use */ + uint8_t TxPhy; + /**Reception PHY rate(1 byte) +- + BIT(0) - The Host prefers to use the LE 1M transmitter PHY (possibly among others) +- + BIT(1) - The Host prefers to use the LE 2M transmitter PHY (possibly among others) +- + BIT(2) - The Host prefers to use the LE Coded transmitter PHY (possibly among others) +- + BIT(3) - BIT(7) Reserved for future use */ + uint8_t RxPhy; +} rsi_ble_event_phy_update_t; + +// connection parameters complete event + +/** + * @brief Structure to hold the data of the BLE connection update event. + * + */ +typedef struct rsi_ble_event_conn_update_s { + /**Device address of the remote device*/ + uint8_t dev_addr[6]; + /**Connection Interval*/ + uint16_t conn_interval; + /**Slave Latency*/ + uint16_t conn_latency; + /**Supervision Timeout*/ + uint16_t timeout; +} rsi_ble_event_conn_update_t; + +// remote conn params request event //event_id : 0x152E + +/** + * @brief Structure representing the parameters of a remote connection parameter request event in BLE. + */ +typedef struct rsi_ble_event_remote_conn_param_req_s { + /** Device address of the remote device */ + uint8_t dev_addr[6]; + /** Minimum connection interval */ + uint16_t conn_interval_min; + /** Maximum connection interval */ + uint16_t conn_interval_max; + /** Slave Latency */ + uint16_t conn_latency; + /** Supervision Timeout */ + uint16_t timeout; +} rsi_ble_event_remote_conn_param_req_t; + +// remote features event +/** + * @brief Structure to hold the data of the remote features event. + */ +typedef struct rsi_ble_event_remote_features_s { + /**Remote device address*/ + uint8_t dev_addr[6]; + /**Remote device supported features +- + @note please refer spec for the supported features list */ + uint8_t remote_features[8]; +} rsi_ble_event_remote_features_t; + +// LE Device Buffer Indication +/** + * @brief Structure to hold the BLE event LE device buffer indication. + */ +typedef struct rsi_ble_event_le_dev_buf_ind_s { + + /**Remote device address*/ + uint8_t remote_dev_bd_addr[RSI_DEV_ADDR_LEN]; + /**No. of Available buffer*/ + uint8_t avail_buf_cnt; +} rsi_ble_event_le_dev_buf_ind_t; + +// PHY update complete event +/** + * @brief Structure representing the data for the BLE length update event. + * + */ +typedef struct rsi_ble_event_data_length_update_s { + + /**Device address of the remote device.*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**Maximum TX Octets to be transmitted*/ + uint16_t MaxTxOctets; + /**Maximum TX time to transmit the MaxTxOctets*/ + uint16_t MaxTxTime; + /**Maximum Rx Octets to be received*/ + uint16_t MaxRxOctets; + /**Maximum Rx time to receive the MaxRxOctets*/ + uint16_t MaxRxTime; +} rsi_ble_event_data_length_update_t; + +// Basic GATT structures + +// 128 bit UUID format structure +/** + * @brief Structure representing a 128-bit UUID. + */ +typedef struct uuid128_s { + /** Holds the value of data1 */ + uint32_t data1; + /** Holds the value of data2 */ + uint16_t data2; + /** + * @brief Holds the value of data3. + */ + uint16_t data3; + /** + * @brief Array to store 8 bytes of data. + */ + uint8_t data4[8]; +} uuid128_t; + +/// 16 bit UUID format structure +typedef uint16_t uuid16_t; + +/// 32 bit UUID format structure +typedef uint32_t uuid32_t; + +// UUID format structure + +/** + * @brief Structure representing a Universally Unique Identifier (UUID). + * + * This structure encapsulates a UUID, which can be of varying sizes—16-bit, 32-bit, or 128-bit. + * It includes the size of the UUID, a reserved field, and a union to hold the value + * of one of the three types of UUIDs. + */ +typedef struct uuid_s { + /** + * Size of the UUID. + * Indicates the size of the UUID in bits. It can be 16, 32, or 128, depending on the type of UUID used. + */ + uint8_t size; + + /** + * Reserved field. + * This field is reserved for future use. + */ + uint8_t reserved[3]; + + /** + * @brief Union representing the value of the UUID. + * This union stores the value of the UUID, which can be of three different sizes: + * 128-bit, 32-bit, or 16-bit. The appropriate field in the union should be used + * depending on the size of the UUID. + */ + union uuid_t { + /** + * @brief 128-bit UUID value. \ref uuid128_t + * + * This member holds the value of a 128-bit UUID, which is divided into four segments: + * - The first 32 bits (`data1`) + * - The next 16 bits (`data2`) + * - The following 16 bits (`data3`) + * - The final 64 bits (`data4`), stored as an array of 8 bytes + * + * These segments together represent a full 128-bit UUID, compliant with the standard UUID format. + */ + uuid128_t val128; + + /** + * 32-bit UUID value. + * This field holds the value of a 32-bit UUID, stored as an array of 4 bytes. + */ + uuid32_t val32; + + /** + * 16-bit UUID value. + * This field holds the value of a 16-bit UUID, stored as an array of 2 bytes. + */ + uuid16_t val16; + } val; ///< Value of one of the 3 types (128-bit, 32-bit, or 16-bit) of UUIDs +} uuid_t; + +/** @} */ +/** @addtogroup BT_BLE_TYPES + * @{ */ +// profile descriptor/primary service structure +/** + * @brief Represents the data of the particular profile descriptor. + */ +typedef struct profile_descriptor_s { + /** Start handle. */ + uint8_t start_handle[2]; + /** End handle. */ + uint8_t end_handle[2]; + /** profile uuid. */ + uuid_t profile_uuid; +} profile_descriptors_t; +/** @} */ + +// GATT attribute descriptor structure +/** @addtogroup BT_BLE_TYPES + * @{ */ +/** + * @brief Structure representing an attribute descriptor. + * + * This structure is used to define the parameters for an attribute descriptor, + * including the attribute handle, reserved field, and attribute UUID. + */ +typedef struct att_desc_s { + /** Attribute handle */ + uint8_t handle[2]; + /** Reserved */ + uint8_t reserved[2]; + /** Attribute UUID (attribute type) */ + uuid_t att_type_uuid; +} att_desc_t; + +//characteristic service attribute value structure + +/** + * @brief Structure representing characteristic service data. + * + * This structure is used to define the parameters for characteristic service data, + * including the characteristic value property, handle, and UUID. + */ +typedef struct char_serv_data_s { + /** Characteristic value property */ + uint8_t char_property; + /** Reserved */ + uint8_t reserved; + /** Characteristic value handle */ + uint16_t char_handle; + /** Characteristic value attributes UUID */ + uuid_t char_uuid; +} char_serv_data_t; + +//characteristic service attribute structure + +/** + * @brief Structure representing a characteristic service. + * + * This structure is used to define the parameters for a characteristic service, + * including the attribute handle, reserved space for future use, and the characteristic service attribute value. + */ +typedef struct char_serv_s { + /** Characteristic service attribute handle */ + uint16_t handle; + /** Reserved for future use */ + uint8_t reserved[2]; + /** Characteristic service attribute value */ + char_serv_data_t char_data; +} char_serv_t; + +//include service attribute value structure +/** + * @brief Structure representing the included service data. + */ +typedef struct inc_serv_data_s { + + /**include service start handle*/ + uint16_t start_handle; + /**include service end handle*/ + uint16_t end_handle; + /**UUID value of the included service*/ + uuid_t uuid; +} inc_serv_data_t; + +// include service attribute structure +/** + * @brief Structure representing an included service attribute in a GATT server. + * + */ +typedef struct inc_serv_s { + /**Include service attribute handle*/ + uint16_t handle; + /**Reserved field */ + uint8_t reserved[2]; + /**Include service attribute data structure */ + inc_serv_data_t inc_serv; +} inc_serv_t; + +/** @} */ +/** @addtogroup BT_BLE_TYPES + * @{ */ +// GATT Request structures +// add new attributes to service request structure +/** + * @brief Structure representing a request to add an attribute in the BLE stack. + */ +typedef struct rsi_ble_req_add_att_s { + /** service handler */ + void *serv_handler; + /** Attribute handle */ + uint16_t handle; + /** If this variable is 1, Host has to maintain attributes and records in the application. +- + If 0, Stack will maintain the attributes and records + */ + uint16_t config_bitmap; + /** Attribute type UUID */ + uuid_t att_uuid; + /** Attribute property */ + uint8_t property; + /** Attribute data length */ + uint16_t data_len; + /** Attribute data. The maximum value is 240, please refer RSI_DEV_ATT_LEN Macro*/ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_req_add_att_t; +/** @} */ + +// GATT Response structures + +//Presentation Format descriptor structure +// actual value = char value * 10 ^ exponent; +/** + * @brief Structure representing the presentation format of a Bluetooth Low Energy (BLE) device. + */ +typedef struct rsi_ble_presentation_format { + /**Format of the data*/ + uint8_t format; + /**Exponent of the data*/ + uint8_t exponent; + /**uints of the data*/ + uint16_t unit; + /**name space of the data*/ + uint8_t name_space; + /**Description for data*/ + uint16_t description; +} rsi_ble_pesentation_format_t; + +/** @addtogroup BT_BLE_EVENT_TYPES Event Types + * @{ */ + +//RSI_BLE_EVENT_GATT_ERROR_RESP, event_id: 0x1500 +/** + * @brief Structure representing the response for a BLE event error. + */ +typedef struct rsi_ble_event_error_resp_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**attribute handle*/ + uint8_t handle[2]; + /**Error indicates the type of Gatt Error*/ + uint8_t error[2]; +} rsi_ble_event_error_resp_t; + +//RSI_BLE_EVENT_GATT_CHAR_DESC - event_ix = 1501 + +/** + * @brief Structure representing a GATT descriptor event. + */ +typedef struct rsi_ble_event_gatt_desc_s { + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**number of descriptors found*/ + uint8_t num_of_att; + /**Reserved for future use*/ + uint8_t reserved; + /**Attribute descriptors list. The maximum value is 5*/ + att_desc_t att_desc[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_event_gatt_desc_t; + +//RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_LIST, event_id: 0x1509 + +/** + * @brief Structure representing the BLE event profiles list. + * + * This structure is used to define the parameters for the BLE event profiles list, + * including the remote device address, number of profiles found, and the list of found profiles. + */ +typedef struct rsi_ble_event_profiles_list_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Number of profiles found */ + uint8_t number_of_profiles; + /** Reserved for future use */ + uint8_t reserved; + /** List of found profiles. The maximum value is 5 */ + profile_descriptors_t profile_desc[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_event_profiles_list_t; + +//RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_BY_UUID, event_id = 0x1502 +/** + * @brief Structure to hold the BLE event profile by UUID. + */ +typedef struct rsi_ble_event_profile_by_uuid_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**profile start handle*/ + uint8_t start_handle[2]; + /**profile end handle*/ + uint8_t end_handle[2]; +} rsi_ble_event_profile_by_uuid_t; + +//RSI_BLE_EVENT_GATT_READ_CHAR_SERVS, event_id = 0x1503 +/** + * @brief Structure representing the BLE event for reading characteristic services by type. + * + * This structure is used to represent the BLE event `RSI_BLE_EVENT_GATT_READ_CHAR_SERVS` + * with event ID `0x1503`. It provides information related to the read operation + * of characteristic services. + */ +typedef struct rsi_ble_event_read_by_type1_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Number of characteristic services found */ + uint8_t num_of_services; + /** Reserved for future use */ + uint8_t reserved; + /** It contains the characteristic service list. The maximum value is 5. */ + char_serv_t char_services[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_event_read_by_type1_t; + +//RSI_BLE_EVENT_GATT_READ_INC_SERVS, event_id = 0x1504 +/** + * @brief Structure for BLE event read by type 2. + */ +typedef struct rsi_ble_event_read_by_type2_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**number of characteristic services found*/ + uint8_t num_of_services; + /**Reserved for future use*/ + uint8_t reserved; + /**list of included services. The maximum value is 5*/ + inc_serv_t services[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_event_read_by_type2_t; + +//RSI_BLE_EVENT_GATT_READ_VAL_BY_UUID, event_id = 0x1505 +/** + * @brief Structure definition for the BLE event "Read By Type 3" response. + */ +typedef struct rsi_ble_event_read_by_type3_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**attribute handle*/ + uint8_t handle[2]; + /**length of attribute value*/ + uint16_t length; + /**This contains the attribute value. The maximum value is 240, please refer RSI_DEV_ATT_LEN Macro*/ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_event_read_by_type3_t; + +//RSI_BLE_EVENT_GATT_READ_RESP , evet_id = 0x1506,0x1507,0x1508 +/** + * @brief Structure representing the BLE ATT value event. + */ +typedef struct rsi_ble_event_att_value_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**length of attribute value*/ + uint16_t length; + /**This contains the attribute value. The maximum value is 240, please refer RSI_DEV_ATT_LEN Macro*/ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_event_att_value_t; + +//RSI_BLE_EVENT_GATT_WRITE_RESP, event_id: 0x150A,0x150C +/** + * @brief Structure to hold the response for the BLE set attribute request. + */ +typedef struct rsi_ble_set_att_resp_s { + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; +} rsi_ble_set_att_resp_t; + +//RSI_BLE_EVENT_GATT_PREPARE_WRITE_RESP, event_id: 0x150B +/** + * @brief Structure representing the response for the prepare write operation in BLE. + */ +typedef struct rsi_ble_prepare_write_resp_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**attribute handle*/ + uint8_t handle[2]; + /**attribute value offset*/ + uint8_t offset[2]; + /**length of attribute value*/ + uint8_t length; + /**This contains the attribute value. The maximum value is 240, please refer RSI_DEV_ATT_LEN Macro*/ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_prepare_write_resp_t; + +// GATT Profiles list response structure +/** + * @brief Structure to hold the response for the BLE profiles list command. + */ +typedef struct rsi_ble_resp_profiles_list_s { + /** Number of profiles found */ + uint8_t number_of_profiles; + /** Reserved */ + uint8_t reserved[3]; + /** List of found profiles +- + The maximum value is 5 */ + profile_descriptors_t profile_desc[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_resp_profiles_list_t; + +/** + * @brief Structure representing the response for querying profile descriptors in BLE. + */ +typedef struct rsi_ble_resp_query_profile_descriptor_s { + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**List of found profiles +- + The maximum value is 5 */ + profile_descriptors_t profile_desc[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_resp_query_profile_descriptor_t; + +// GATT characteristic query service response structure + +#ifndef RSI_BLE_APIS_H +#define RSI_BLE_APIS_H + +#include + +/** + * @brief Structure to hold the response of characteristic services. + */ +typedef struct rsi_ble_resp_char_serv_s { + uint8_t num_of_services; /**< The number of profiles found */ + uint8_t reserved[3]; /**< Reserved */ + char_serv_t char_services[RSI_BLE_MAX_RESP_LIST]; /**< Characteristic service array. The maximum value is 5. */ +} rsi_ble_resp_char_services_t; + +#endif /* RSI_BLE_APIS_H */ +/** + * @brief Structure to hold the response of characteristic services. + */ +typedef struct rsi_ble_resp_char_serv_s { + /** The number of profiles found */ + uint8_t num_of_services; + /** Reserved */ + uint8_t reserved[3]; + /** Characteristic service array. +- + The maximum value is 5. */ + char_serv_t char_services[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_resp_char_services_t; + +// GATT include service response structure +/** + * @brief Structure representing the response for including a service in BLE. + */ +typedef struct rsi_ble_resp_inc_serv { + /** Number of profiles found */ + uint8_t num_of_services; + /** Reserved */ + uint8_t reserved[3]; + /** Include service list. +- + The maximum value is 5. */ + inc_serv_t services[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_resp_inc_services_t; + +// GATT attribute value response structure +/** + * @brief Structure representing the response for an Attribute Protocol (ATT) value in Bluetooth Low Energy (BLE). + */ +typedef struct rsi_ble_resp_att_value_t { + /** Length of attribute value */ + uint8_t len; + /** Attribute values list. +- + Each attribute value is maximum of size 240, see RSI_DEV_ATT_LEN Macro */ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_resp_att_value_t; + +// GATT attribute descriptors response structure +/** + * @brief Structure representing the response for Attribute Descriptors in BLE. + */ +typedef struct rsi_ble_resp_att_descs_s { + /** Number of descriptors found */ + uint8_t num_of_att; + /** Reserved */ + uint8_t reserved[3]; + /** Attribute descriptors list. +- + The maximum value is 5. */ + att_desc_t att_desc[RSI_BLE_MAX_RESP_LIST]; +} rsi_ble_resp_att_descs_t; + +// add new service response structure +/** + * @brief Structure representing the response for adding a service in BLE. + */ +typedef struct rsi_ble_resp_add_serv_s { + /** Contains the address of the service record stored in the Silicon Labs stack. */ + void *serv_handler; + /** The handle from where the service starts. */ + uint16_t start_handle; +} rsi_ble_resp_add_serv_t; + +// read local attribute value response structure +/** + * @brief Structure representing the response for local attribute value in BLE. + */ +typedef struct rsi_ble_resp_local_att_value_s { + /** Attribute handle */ + uint16_t handle; + /** Attribute value length */ + uint16_t data_len; + /** Attribute value (data). The maximum value is 240, see RSI_DEV_ATT_LEN Macro */ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_resp_local_att_value_t; + +/** + * @brief Structure representing the BLE event for remote device information. + * + * This structure is used to define the parameters for a BLE event + * that provides information about a remote device. + */ +typedef struct rsi_ble_event_remote_device_info_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Remote device version */ + uint8_t remote_version; + /** Remote device company ID */ + uint16_t remote_company_id; + /** Remote device sub-version */ + uint16_t remote_sub_version; +} rsi_ble_event_remote_device_info_t; + +/** + * @brief Structure representing the BLE event for received Remote Control Protocol (RCP) information. + * + * This structure is used to define the parameters for a BLE event + * that involves receiving RCP information. + */ +typedef struct rsi_ble_event_rcp_rcvd_info_s { + /** Received RCP data */ + uint8_t data[1024]; +} rsi_ble_event_rcp_rcvd_info_t; +// GATT Event structures + +// GATT Write event structure +/** + * @brief Structure representing a BLE write event. + */ +typedef struct rsi_ble_event_write_s { + /** remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Reserved for future use */ + uint8_t reserved; + +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/// BLE write command event +#define RSI_BLE_WRITE_CMD_EVENT 0x01 +/// BLE write request event +#define RSI_BLE_WRITE_REQUEST_EVENT 0x02 +/// BLE notification event +#define RSI_BLE_NOTIFICATION_EVENT 0x03 +/// BLE indication event +#define RSI_BLE_INDICATION_EVENT 0x04 + /** @} */ + /**Type of the event received from the remote device +- + RSI_BLE_WRITE_CMD_EVENT 0x01 +- + RSI_BLE_WRITE_REQUEST_EVENT 0x02 +- + RSI_BLE_NOTIFICATION_EVENT 0x03 +- + RSI_BLE_INDICATION_EVENT 0x04 */ + uint8_t pkt_type; + /**attribute handle*/ + uint8_t handle[2]; + /**length of attribute value*/ + uint8_t length; + /**This contains the attribute value. The maximum value is 240, see RSI_DEV_ATT_LEN Macro*/ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_event_write_t; + +// GATT prepare Write event structure +/** + * @brief Structure definition for preparing a write operation in BLE event. + */ +typedef struct rsi_ble_event_prepare_write_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**attribute handle*/ + uint8_t handle[2]; + /**attribute value offset*/ + uint8_t offset[2]; + /**length of attribute value*/ + uint16_t length; + /**This contains the attribute value. The maximum value is 240, see RSI_DEV_ATT_LEN Macro*/ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_event_prepare_write_t; + +/** + * @brief Structure representing the BLE execute write request. + * + * This structure is used to define the parameters for an execute write request + * to a remote BLE device. + */ +typedef struct rsi_ble_execute_write_s { + /** Remote device address (6 bytes) */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Execute write flag */ + uint8_t exeflag; +} rsi_ble_execute_write_t; + +// GATT Read event structure + +/** + * @brief Structure representing the BLE read request. + * + * This structure is used to define the parameters for a BLE read request, + * including the remote device address, attribute handle, request type, and offset. + */ +typedef struct rsi_ble_read_req_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint16_t handle; + /** Request type: 0 - Read request, 1 - Read Blob request */ + uint8_t type; + /** Reserved for future use */ + uint8_t reserved; + /** Offset of attribute value to be read */ + uint16_t offset; +} rsi_ble_read_req_t; + +// GATT MTU event structure +/** + * @brief Structure to hold the BLE MTU event information. + */ +typedef struct rsi_ble_event_mtu_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**MTU size*/ + uint16_t mtu_size; +} rsi_ble_event_mtu_t; +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ +#define PEER_DEVICE_INITATED_MTU_EXCHANGE 0x1 ///< Indicates that the MTU exchange was initiated by the peer device. +#define LOCAL_DEVICE_INITATED_MTU_EXCHANGE 0x2 ///< Indicates that the MTU exchange was initiated by the local device. +/** @} */ +//MTU Exchange Information event structure +/** + * @brief Structure to hold the MTU exchange information for a BLE event. + */ +typedef struct rsi_ble_event_mtu_exchange_information_s { + /**uint8_t[6], remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**uint8_t[2], Remote MTU Size*/ + uint16_t remote_mtu_size; + /**uint8_t[2], Local MTU Size*/ + uint16_t local_mtu_size; + /**uint8_t Initiated role, who initiated MTU exchange +- + PEER_DEVICE_INITATED_MTU_EXCHANGE 0x01 +- + LOCAL_DEVICE_INITATED_MTU_EXCHANGE 0x02 */ + uint8_t initiated_role; +} rsi_ble_event_mtu_exchange_information_t; +// GATT Notification event structure +/** + * @brief Structure for BLE event notification. + */ +typedef struct rsi_ble_event_notify_s { + + /**remote device address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**attribute handle*/ + uint8_t handle[2]; + /**length of attribute value*/ + uint8_t length; + /**This contains the attribute value. The maximum value is 240, see RSI_DEV_ATT_LEN Macro*/ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_event_notify_t; + +// GATT Indication event structure + +/** + * @brief Structure representing the BLE event for an indication. + * + * This structure is used to define the parameters for a BLE event + * that involves an indication from a remote device. + */ +typedef struct rsi_ble_event_indication_s { + /** Remote device address */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Attribute handle */ + uint8_t handle[2]; + /** Length of attribute value */ + uint8_t length; + /** This contains the attribute value. The maximum value is 240, see RSI_DEV_ATT_LEN Macro */ + uint8_t att_value[RSI_DEV_ATT_LEN]; +} rsi_ble_event_indication_t; + +/** + * @brief Structure to hold the information of a directed advertising report event. + */ +typedef struct rsi_ble_event_directedadv_report_s { + /**Event type +- + 0x01 Connectable directed advertising (ADV_DIRECT_IND) */ + uint16_t event_type; + /**Address type of remote device*/ + uint8_t dev_addr_type; + /**Address of the remote device*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /**Directed address type*/ + uint8_t directed_addr_type; + /**Directed device address*/ + uint8_t directed_dev_addr[RSI_DEV_ADDR_LEN]; + /**rssi value*/ + int8_t rssi; +} rsi_ble_event_directedadv_report_t; + +/** + * @brief Structure representing the BLE event for CBFC connection request. + * + * This structure is used to define the parameters for a BLE event + * that involves a Circular Buffer Flow Control (CBFC) connection request from a remote device. + */ +typedef struct rsi_ble_event_cbfc_conn_req_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Protocol/Service Multiplexer (PSM) value */ + uint16_t psm; + /** Local Channel Identifier (LCID) */ + uint16_t lcid; +} rsi_ble_event_cbfc_conn_req_t; + +/** + * @brief Structure representing the BLE event for CBFC connection complete. + * + * This structure is used to define the parameters for a BLE event + * that indicates the completion of a Circular Buffer Flow Control (CBFC) connection with a remote device. + */ +typedef struct rsi_ble_event_cbfc_conn_complete_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Protocol/Service Multiplexer (PSM) value */ + uint16_t psm; + /** Maximum Transmission Unit (MTU) size */ + uint16_t mtu; + /** Maximum PDU Size (MPS) */ + uint16_t mps; + /** Local Channel Identifier (LCID) */ + uint16_t lcid; +} rsi_ble_event_cbfc_conn_complete_t; + +/** + * @brief Structure representing the BLE event for CBFC received data. + * + * This structure is used to define the parameters for a BLE event + * that involves receiving data over a Circular Buffer Flow Control (CBFC) connection from a remote device. + */ +typedef struct rsi_ble_event_cbfc_rx_data_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Local Channel Identifier (LCID) */ + uint16_t lcid; + /** Length of the received data */ + uint16_t len; + /** Received data */ + uint8_t data[RSI_DEV_ATT_LEN]; +} rsi_ble_event_cbfc_rx_data_t; + +/** + * @brief Structure representing the BLE event for CBFC disconnection. + * + * This structure is used to define the parameters for a BLE event + * that involves the disconnection of a Circular Buffer Flow Control (CBFC) connection with a remote device. + */ +typedef struct rsi_ble_event_cbfc_disconn_s { + /** Address of the remote device */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** Local Channel Identifier (LCID) */ + uint16_t lcid; +} rsi_ble_event_cbfc_disconn_t; + +/** @addtogroup BT-LOW-ENERGY1 GAP + * @{ */ +// SMP pairing capabilities cmd_ix = 0x00FE +/** + * @brief Structure for setting SMP pairing capability data. + */ +typedef struct rsi_ble_set_smp_pairing_capabilty_data { + + /**Device input output capability +- + 0x00 - Display Only +- + 0x01 - Display Yes/No +- + 0x02 - Keyboard Only +- + 0x03 - No Input No Output + 0x04 - Keyboard Display*/ + uint8_t io_capability; + /** oob_data_flag +- + 0 - disable +- 1 - enable */ + uint8_t oob_data_flag; + /** Authentication Request contains bonding type +- + MITM Request - BIT(2) +- + Secure Connections - BIT(3) +- + Keypress - BIT(4) +- + CT2 - BIT(5) */ + uint8_t auth_req; + /** Supported Encryption key size 7 to 16 bytes */ + uint8_t enc_key_size; + /** Initiator generates/requires the no .of keys after successful paring +- + BIT(0) - EncKey: Initiator distributes the LTK followed by EDIV and Rand +- + BIT(1) - IdKey : Initiator distributes the IRK followed by its address +- + BIT(2) - Sign : Initiator distributes the CSRK +- + BIT(3) - BIT(7): Reserved for future use */ + uint8_t ini_key_distribution; + /** Responder generates/requires the no .of keys after successful paring +- + BIT(0) - EncKey: Responder distributes the LTK followed by EDIV and Rand +- + BIT(1) - IdKey : Responder distributes the IRK followed by its address +- + BIT(2) - Sign : Responder distributes the CSRK +- + BIT(3) - BIT(7): Reserved for future use */ + uint8_t rsp_key_distribution; + +} rsi_ble_set_smp_pairing_capabilty_data_t; + +//LE read PHY request command response structure, cmd_ix - 0x00B0 + +/** + * @brief Structure to hold the response for the BLE read PHY command. + */ +typedef struct rsi_ble_resp_read_phy_s { + /** Remote device Bluetooth Address*/ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; + /** TX PHY Rate +- + 0x01 The transmitter PHY for the connection is LE 1M +- + 0x02 The transmitter PHY for the connection is LE 2M +- + 0x03 The transmitter PHY for the connection is LE Coded +- + All other values Reserved for future use*/ + uint8_t tx_phy; + /** RX PHY Rate +- + 0x01 The receiver PHY for the connection is LE 1M +- + 0x02 The receiver PHY for the connection is LE 2M +- + 0x03 The receiver PHY for the connection is LE Coded +- + All other values Reserved for future use*/ + uint8_t rx_phy; +} rsi_ble_resp_read_phy_t; + +//LE read max data length command response structure, cmd_ix - 0x00B3 +/** + * @brief Structure representing the response for reading the maximum data length in BLE. + */ +typedef struct rsi_ble_resp_read_max_data_length_s { + /** maxtxoctets +- + Preferred maximum number of payload octets that the local Controller should + include in a single Link Layer packet on this connection. */ + uint16_t maxtxoctets; + /** maxtxtime +- + Preferred maximum number of microseconds that the local Controller + should use to transmit a single Link Layer packet on this connection */ + uint16_t maxtxtime; + /** maxrxoctets +- + Maximum number of payload octets that the local Controller supports + for reception of a single Link Layer packet on a data connection */ + uint16_t maxrxoctets; + /** maxrxtime +- + Maximum time, in microseconds, that the local Controller supports for + reception of a single Link Layer packet on a data connection. */ + uint16_t maxrxtime; +} rsi_ble_read_max_data_length_t; + +/** @} */ + +/** @addtogroup BT-LOW-ENERGY6 Test Mode + * @{ */ +//LE Per Transmit mode, cmd_ix = 0x00BE + +/** + * @brief Structure to hold the parameters for BLE periodic advertising transmission. + */ +typedef struct rsi_ble_per_transmit_s { + /** Command ID +- + Takes per BLE_TRANSMIT_CMD_ID of value 0x13*/ + uint8_t cmd_ix; + /** Enables/disables the BLE per transmit mode +- + 1 PER Transmit Enable +- + 0 PER Transmit Disable */ + uint8_t transmit_enable; + /** Access address with which packets are transmitted */ + uint8_t access_addr[4]; + /** Phy rate at which packets are transmitted +- + 1 1Mbps +- + 2 2 Mbps +- + 4 125 Kbps Coded +- + 8 500 Kbps Coded */ + uint8_t phy_rate; + /** Rx channel number (0 - 39) + @note Removed the BLE packet transmission on channel-39 (2480MHz) at a 2Mbps data rate */ + uint8_t rx_chnl_num; + /** Tx channel number (0 - 39) + @note Removed the BLE packet transmission on channel-39 (2480MHz) at a 2Mbps data rate */ + uint8_t tx_chnl_num; + /** Initial seed to be used for whitening. It should be set to 0 in order to disable whitening. +- + In order to enable, one should give the scrambler seed value which is used on the receive side */ + uint8_t scrambler_seed; + /** LE channel type (data or advertise channel) +- + 0x00 Advertise Channel +- + 0x01 Data Channel (to be used by Default) */ + uint8_t le_chnl_type; + /** Frequency hopping type to be used +- + 0 No Hopping +- + 1 Fixed Hopping +- + 2 Random Hopping (rx_chnl_num, tx_chnl_num parameters are unused in this mode) */ + uint8_t freq_hop_en; + /** Select the antenna to be used. Refer to the data sheet for your hardware to check whether or not it contains an onboard antenna. +- + 2 ONBOARD_ANT_SEL +- + 3 EXT_ANT_SEL */ + uint8_t ant_sel; + /** pll_mode type to be used +- + 0 PLL_MODE0 (to be used by Default) +- + 1 PLL_MODE1 */ + uint8_t pll_mode; + /** Selection of RF type (internal/external) +- + 0 BT_EXTERNAL_RF +- + 1 BT_INTERNAL_RF (to be used by Default) + @note The above macros are applicable for both BT and BLE */ + uint8_t rf_type; + /** Selection of RF Chain (HP/LP) to be used +- + 2 BT_HP_CHAIN +- + 3 BT_LP_CHAIN + @note The above macros are applicable for both BT and BLE */ + uint8_t rf_chain; + /** Length of the packet to be transmitted*/ + uint8_t pkt_len[2]; + /** Type of payload data sequence +- + 0x00 PRBS9 sequence �11111111100000111101... +- + 0x01 Repeated �11110000� +- + 0x02 Repeated �10101010� +- + 0x03 PRBS15 +- + 0x04 Repeated �11111111� +- + 0x05 Repeated �00000000� +- + 0x06 Repeated '00001111' +- + 0x07 Repeated '01010101' */ + uint8_t payload_type; + /** Transmit Power +- + Default Value for BLE TX Power Index is 31, The range for the BLE TX Power Index is 1 to 127 (0, 32 indexes are invalid). +- + TX power index for the BLE LP Chain : 1 to 31 (0dBm Mode), 33 to 63 ( 10dBm Mode) +- + TX power index for the BLE HP Chain : 1 to 127 +- + @note For the LP Chain - Power index vs Outpt power in dBm. + + * ----------------------------------------------------------------------------------------- + * | Power Index | Output Power in dBm | + * ----------------------|------------------------------------------------------------------- + * | 1 | -22.3054959 | + * | 2 | -16.59332574 | + * | 3 | -13.38278365 | + * | 4 | -11.19804718 | + * | 5 | -9.576522466 | + * | 6 | -8.312070432 | + * | 7 | -7.294640362 | + * | 8 | -6.458448154 | + * | 9 | -5.760963318 | + * | 10 | -5.173042366 | + * | 11 | -4.673788189 | + * | 12 | -4.247653993 | + * | 13 | -3.882708784 | + * | 14 | -3.569545894 | + * | 15 | -3.300567503 | + * | 16 | -3.069499167 | + * | 17 | -2.871050592 | + * | 18 | -2.700672503 | + * | 19 | -2.554378603 | + * | 20 | -2.428612817 | + * | 21 | -2.32014891 | + * | 22 | -2.226013876 | + * | 23 | -2.143429275 | + * | 24 | -2.069766557 | + * | 25 | -2.002513642 | + * | 26 | -1.939250859 | + * | 27 | -1.87763493 | + * | 28 | -1.815390046 | + * | 29 | -1.750305305 | + * | 30 | -1.680237892 | + * | 31 | -1.603121401 | + * | 32 | NA | + * | 33 | -10.4822997 | + * | 34 | -4.9531679 | + * | 35 | -1.931961022 | + * | 36 | 0.057132993 | + * | 37 | 1.476764101 | + * | 38 | 2.5332116 | + * | 39 | 3.336771823 | + * | 40 | 3.953605265 | + * | 41 | 4.426779615 | + * | 42 | 4.786171523 | + * | 43 | 5.053647759 | + * | 44 | 5.246007208 | + * | 45 | 5.37676618 | + * | 46 | 5.457304255 | + * | 47 | 5.497635316 | + * | 48 | 5.506945838 | + * | 49 | 5.493978354 | + * | 50 | 5.467302132 | + * | 51 | 5.435491631 | + * | 52 | 5.407220119 | + * | 53 | 5.391268248 | + * | 54 | 5.396444507 | + * | 55 | 5.431416481 | + * | 56 | 5.504458826 | + * | 57 | 5.62313521 | + * | 58 | 5.793945208 | + * | 59 | 6.02197959 | + * | 60 | 6.310634089 | + * | 61 | 6.661428559 | + * | 62 | 7.073964236 | + * | 63 | 7.546029076 | + * ----------------------------------------------------------------------------------------- +- + @note For the HP Chain - Power index vs Outpt power in dBm. + + * ----------------------------------------------------------------------------------------- + * | Power Index | Output Power in dBm | + * ----------------------|------------------------------------------------------------------- + * | 1 | 1 | + * | 2 | 2 | + * | 3 | 3 | + * | 4 | 4 | + * | 5 | 5 | + * | 6 | 6 | + * | 7 | 7 | + * | 8 | 8 | + * | 9 | 9 | + * | 10 | 10 | + * | - | - | + * | - | - | + * | - | - | + * | - | - | + * | 41 | 0.5 | + * | 42 | 1 | + * | 43 | 1.5 | + * | 44 | 2 | + * | 45 | 2.5 | + * | 46 | 3 | + * | 47 | 3.5 | + * | 48 | 4 | + * | 49 | 4.5 | + * | 50 | 5 | + * | - | - | + * | - | - | + * | 127 | (Max Power Supported by Country region) | + * ----------------------|------------------------------------------------------------------- + */ + + uint8_t tx_power; + /** Transmit mode to be used either Burst/Continuous +- + 0 BURST_MODE +- + 1 CONTINUOUS_MODE +- + 2 CONTINUOUS_WAVE_MODE (CW_MODE) */ + uint8_t transmit_mode; + /** This field takes the value of inter packet gap. +- + Number of slots to be skipped between two packets - Each slot will be 1250 usec */ + uint8_t inter_pkt_gap; + /** This field defines the number of packets to be transmitted, default to zero for continuous transmission */ + uint8_t num_pkts[4]; +} rsi_ble_per_transmit_t; + +//LE Per Receive mode, cmd_ix = 0x00BF +/** + * @brief Structure representing the parameters for BLE periodic receive operation. + */ +typedef struct rsi_ble_per_receive_s { + /** Command ID +- + Takes per BLE_RECEIVE_CMD_ID of value 0x14*/ + uint8_t cmd_ix; + /** Enables/disables the ble per receive mode +- + 1 PER Receive Enable +- + 0 PER Receive Disable */ + uint8_t receive_enable; + /** Access address with which packets are received */ + uint8_t access_addr[4]; + /** Phy rate at which packets are received +- + 1 1Mbps +- + 2 2 Mbps +- + 4 125 Kbps Coded +- + 8 500 Kbps Coded */ + uint8_t phy_rate; + /** Rx channel number (0 - 39) */ + uint8_t rx_chnl_num; + /** Tx channel number (0 - 39) */ + uint8_t tx_chnl_num; + /** Initial seed to be used for whitening. It should be set to 0 in order to disable whitening. +- + In order to enable, one should give the scrambler seed value which is used on the transmit side */ + uint8_t scrambler_seed; + /** LE channel type (data or advertise channel) +- + 0x00 Advertise Channel +- + 0x01 Data Channel (to be used by Default) */ + uint8_t le_chnl_type; + /** Frequency hopping type to be used +- + 0 No Hopping +- + 1 Fixed Hopping +- + 2 Random Hopping (rx_chnl_num, tx_chnl_num parameters are unused in this mode) */ + uint8_t freq_hop_en; + /** Select the antenna to be used. Refer to the datasheet for your hardware to check whether or not it contains an onboard antenna. +- + 2 ONBOARD_ANT_SEL +- + 3 EXT_ANT_SEL */ + uint8_t ant_sel; + /** pll_mode type to be used +- + 0 PLL_MODE0 (to be used by Default) +- + 1 PLL_MODE1 */ + uint8_t pll_mode; + /** Selection of RF type (internal/external) +- + 0 BT_EXTERNAL_RF +- + 1 BT_INTERNAL_RF (to be used by Default) + @note The above macros are applicable for both BT and BLE */ + uint8_t rf_type; + /** Selection of RF Chain (HP/LP) to be used +- + 2 BT_HP_CHAIN +- + 3 BT_LP_CHAIN + @note The above macros are applicable for both BT and BLE */ + uint8_t rf_chain; + /** This field enables/disables the extended data length +- + 0 Extended Data length disabled +- + 1 Extended Data length enabled */ + uint8_t ext_data_len_indication; + /** This field defines the loopback to be enable or disable +- + 0 LOOP_BACK_MODE_DISABLE +- + 1 LOOP_BACK_MODE_ENABLE*/ + uint8_t loop_back_mode; + /** This field enables/disables the duty cycling +- + 0 Duty Cycling Disabled (to be used by Default) +- + 1 Duty Cycling Enabled */ + uint8_t duty_cycling_en; +} rsi_ble_per_receive_t; +/** @} */ +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +///The maximum length of advertising data. +#define ADV_DATA_LEN 210 +///Length of the device address in bytes. +#define DEVICE_ADDR_LEN 6 +/** @} */ +//! ae adv report event +typedef struct rsi_ble_ae_adv_report_s { + /** + * ----------------------------------------------------------------------------------------- + * | Bit Number | Parameter Description | + * ----------------------|------------------------------------------------------------------- + * | 0 | Connectable Advertising | + * | 1 | Scannable Advertising | + * | 2 | Direct Advertising | + * | 3 | Scan Response | + * | 4 | Legacy Advertising PDUs used | + * | 5 to 6 | Data status : + * | + * | | 0b00 = complete + * | + * | | 0b01 = Incomplete, more data to come + * | + * | | 0b10 = Incomplete, data truncated, no more to come + *| + * | | 0b11 = Reserved for future use | + */ + uint16_t event_type; + /** + uint8_t Remote Address Type, Indicates the type of the Address + 0x00 - Public Device Address + 0x01 - Random Device Address + 0x02 - Public Identity Address (corresponds to Resolved Private Address) + 0x03 - Random (static) Identity Address (corresponds to Resolved Private Address) + */ + uint8_t remote_addr_type; + /** uint8[6] remote_Address : Address of the remote address Type */ + uint8_t remote_addr[DEVICE_ADDR_LEN]; + /** + uint8_t Primary PHY + 0x01 - Advertiser PHY is LE 1M + 0x03 - Advertiser PHY is LE Coded + */ + uint8_t pri_phy; + /** + uint8_t Secondary PHY + 0x00 - No packets on the secondary advertising physical channel + 0x01 - Advertiser PHY is LE 1M + 0x02 - Advertiser PHY is LE 2M + 0x03 - Advertiser PHY is LE Coded + */ + uint8_t sec_phy; + /** uint8_t Advertising_SID + * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + * | Value | Parameter Description | + * ----------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + * | 0x00 to 0x0F | Value of the Advertising SID subfield in the ADI field of the PDU or, + * for scan responses, in the ADI field of the original scannable advertisement | + * | 0xFF | No ADI field provided | + * + */ + uint8_t SID; + /** + uint8_t TX_Power, It shall be set based on the AUX_SYNC_IND PDU + TX_Power ranges from -127 to +20 and it's units is in dBm + */ + uint8_t tx_power; + /** + uint8_t RSSI , this parameter contains the RSSI value, excluding any constant tone Extension. + RSSI ranges from -127 to +20 and it's units is in dBm + */ + uint8_t RSSI; + /** uint16_t Periodic_Advertising_Interval. This parameter specifies the interval between the periodic advertising events */ + uint16_t per_adv_interval; + /** + uint8_t Direct Address Type ,Indicates the type of the Address + 0x00 - Public Device Address + 0x01 - Random Device Address + 0x02 - Public Identity Address (corresponds to Resolved Private Address) + 0x03 - Random (static) Identity Address (corresponds to Resolved Private Address) + 0xFE - Resolves Private Address + */ + uint8_t direct_addr_type; + /** uint8[6] Direct_Address, Direct_Address of the Advertiser type */ + uint8_t direct_addr[DEVICE_ADDR_LEN]; + /** uint8_t Data _length , Length of the Data field for each device which responded , ranges from 0 to 229 */ + uint8_t data_len; + /** uint8[256] Data */ + uint8_t data[ADV_DATA_LEN]; +} rsi_ble_ae_adv_report_t; + +//! ae periodic sync establishment report event +typedef struct rsi_ble_per_adv_sync_estbl_s { + /** + uint8_t status , It indicates whether Periodic Advertising is successful or not + 0 - Periodic advertising sync successful + !0 - Periodic advertising sync failed + */ + uint8_t status; + /** uint16_t Sync_Handle, It identifies the periodic Advertising train. Range : 0x0000 to 0x0EFF */ + uint16_t sync_handle; + /** uint8_t Advertising_SID, Value of the Advertising SID subfield in the ADI field of the PDU, Range : 0x00 to 0x0F */ + uint8_t adv_sid; + /** + uint8_t Advertiser_Address_Type : Indicates the type of the Address + 0x00 - Public Device Address + 0x01 - Random Device Address + 0x02 - Public Identity Address (corresponds to Resolved Private Address) + 0x03 - Random (static) Identity Address (corresponds to Resolved Private Address) + */ + uint8_t advertiser_addr_type; + /** uint8[6], Advertiser_Address of the Advertiser type */ + uint8_t advertiser_addr[DEVICE_ADDR_LEN]; + /** + uint8_t Advertiser_PHY. This parameter specifies the PHY used for the periodic advertising. + 0x01 - Advertiser PHY is LE 1M + 0x02 - Advertiser PHY is LE 2M + 0x03 - Advertiser PHY is LE Coded + */ + uint8_t advertiser_phy; + /** uint16_t Periodic_Advertising_Interval. This parameter specifies the interval between the periodic advertising events. */ + uint16_t per_adv_interval; + /** + uint16_t Advertiser_Clock_Accuracy. This parameter specifies the accuracy of the periodic advertiser's clock. + 0x00 - 500ppm + 0x01 - 250ppm + 0x02 - 150ppm + 0x03 - 100 ppm + 0x04 - 75 ppm + 0x05 - 50 ppm + 0x06 - 30 ppm + 0x07 - 20 ppm + */ + uint16_t advertiser_clock_accuracy; +} rsi_ble_per_adv_sync_estbl_t; + +//! ae periodic adv report event +typedef struct rsi_ble_per_adv_report_s { + /** uint16_t Sync_Handle, It identifies the periodic Advertising train. Range : 0x0000 to 0x0EFF */ + uint16_t sync_handle; + /** int8_t TX_Power, It shall be set based on the AUX_SYNC_IND PDU + TX_Power ranges from -127 to +20 and it's units is in dBm + */ + int8_t tx_power; + /** int8_t RSSI , this parameter contains the RSSI value, excluding any constant tone Extension. + RSSI ranges from -127 to +20 and it's units is in dBm + */ + int8_t RSSI; + /** Unused byte for alignment */ + uint8_t unused; + /** + uint8_t Data_Status, It specifies about the status of the data sent + 0x00 - Data Complete + 0x01 - Data Incomplete, more Data to come + */ + uint8_t data_status; + /** uint8_t Data_Length ,Length of the Data Field, Ranges from 0 to 247 */ + uint8_t data_len; + /** uint8[256] Data, Data received from a Periodic Advertising Packet */ + uint8_t data[ADV_DATA_LEN]; +} rsi_ble_per_adv_report_t; + +//! ae periodic sync lost report event +typedef struct rsi_ble_per_adv_sync_lost_s { + /** uint16_t Sync_Handle, It identifies the periodic Advertising train. Range : 0x0000 to 0x0EFF */ + uint16_t sync_handle; +} rsi_ble_per_adv_sync_lost_t; + +//! ae scan timeout report event +typedef struct rsi_ble_scan_timeout_s { + /** uint8_t status , Status indicates that scanning has ended because the duration has expired */ + uint8_t status; +} rsi_ble_scan_timeout_t; + +//! ae adv set terminated report event +typedef struct rsi_ble_adv_set_terminated_s { + /** uint8_t status : Status shows the status on how the Advertising ended + 0 - Advertising successfully ended with a connection being created + !0 - Advertising ended for another reason and usually error codes would be listed + */ + uint8_t status; + /** uint8_t Advertising_Handle : Advertising_Handle in which Advertising has ended, Range : 0x00 to 0xEF */ + uint8_t adv_handle; + /** uint16_t Connection_Handle : It is the Connection Handle of the connection whose creation ended the advertising, Range : 0x00 to 0xEF */ + uint16_t conn_handle; + /** + uint8_t Num_Completed_Extended_Advertising_Events + Number of completed extended advertising events transmitted by the Controller + */ + uint8_t num_completed_ae_events; +} rsi_ble_adv_set_terminated_t; + +//! ae scan request recvd report event +typedef struct rsi_ble_scan_req_recvd_s { + /** uint8_t Advertising_Handle : Used to identify an Advertising set , Range : 0x00 to 0xEF */ + uint8_t adv_handle; + /** + uint8_t Scanner_Address_Type : Indicates the type of the Address + 0x00 - Public Device Address + 0x01 - Random Device Address + 0x02 - Public Identity Address (corresponds to Resolved Private Address) + 0x03 - Random (static) Identity Address (corresponds to Resolved Private Address) + */ + uint8_t scanner_addr_type; + /** uint8[6] Scanner_Address : Address of the Advertising Type */ + uint8_t scanner_addr[DEVICE_ADDR_LEN]; +} rsi_ble_scan_req_recvd_t; + +/****************************************************** + * * Global Variables + * ******************************************************/ +/** + * @brief Structure representing the BLE buffer statistics. + * + * This structure is used to define the parameters for BLE buffer statistics, + * including the utilization of Asynchronous Connection-Less (ACL) buffers and command packet buffers. + */ +typedef struct chip_ble_buffers_stats_s { + /** Utilization of ACL (Asynchronous Connection-Less) buffers*/ + uint8_t acl_buffer_utilization; + /** Utilization of command packet buffers */ + uint8_t cp_buffer_utilization; +} chip_ble_buffers_stats_t; + +/****************************************************** + * * GAP API's Declarations + * ******************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @fn uint8_t rsi_convert_db_to_powindex(int8_t tx_power_in_dBm) + * @brief Converts the given transmit power in dBm to power index. + * + * This function takes a transmit power value in dBm and converts it to a power index value. + * The power index is used to set the transmit power level in the BLE module. + * + * @param tx_power_in_dBm The transmit power in dBm. + * @return The power index corresponding to the given transmit power. + */ +uint8_t rsi_convert_db_to_powindex(int8_t tx_power_in_dBm); + +/** @addtogroup BT-LOW-ENERGY1 +* @{ +*/ +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_random_address(void) + * @brief Request the local device to set a random address. This is a blocking API. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_random_address(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_random_address_with_value(uint8_t *random_addr) + * @brief Request the local device to set a given random address. This is a blocking API. + * @pre Pre-condition: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] random_addr - random address of the device to be set + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_random_address_with_value(uint8_t *random_addr); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_start_advertising(void) + * @brief Request the local device to start advertising. This is a blocking API. + * A received event \ref rsi_ble_on_enhance_connect_t/ \ref rsi_ble_on_connect_t indicates remote device given ble connect command and got connected + * @pre Pre-condition: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * 0x4E0C - Command disallowed + * 0x4046 - Invalid Arguments + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ + +int32_t rsi_ble_start_advertising(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_start_advertising_with_values(const void *rsi_ble_adv) + * @brief Request the local device to start advertising with specified values. This is a blocking API. + * A received event \ref rsi_ble_on_enhance_connect_t/ \ref rsi_ble_on_connect_t indicates remote device given ble connect command and got connected + * @pre Pre-condition: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API, this is a blocking API. + * @param[in] rsi_ble_adv - This structure pointer holds the information of advertising values. This variable is the pointer of the \ref rsi_ble_req_adv_s structure. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * 0x4E0C - Command disallowed + * 0x4046 - Invalid Arguments + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_start_advertising_with_values(const void *rsi_ble_adv); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_encrypt(const uint8_t *key, const uint8_t *data, uint8_t *resp) + * @brief Encrypt the plain text data fed by the user using the key provided, it uses the AES-128 bit block cypher a logo to generate encrypted data, refer to Bluetooth Spec 5.0 for further details. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API, this is a blocking API. + * @param[in] key - 16 Bytes key for Encryption of data. + * @param[in] data - 16 Bytes of Data request to encrypt. + * @param[out] resp - Encrypted data + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_encrypt(const uint8_t *key, const uint8_t *data, uint8_t *resp); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_stop_advertising(void) + * @brief Stop advertising, this is a Blocking API + * @pre Pre-conditions: + * Call rsi_ble_start_advertising() before calling this API. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * 0x4E0C - Command disallowed + * 0x4046 - Invalid Arguments + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_stop_advertising(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_advertise_data(const uint8_t *data, uint16_t data_len) + * @brief Set the advertising data. This is a blocking API. + * @pre Pre-condition: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] data - Advertising data. + * @param[in] data_len - Total length of advertising data. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + * @note The maximum length of advertising data payload is 31 bytes. + * @note The basic format of advertising payload record contains length and data. + */ +int32_t rsi_ble_set_advertise_data(const uint8_t *data, uint16_t data_len); + +/*========================================================*/ +/** + * @fn int32_t rsi_ble_set_scan_response_data(const uint8_t *data, uint16_t data_len); + * @brief Request the local device to set the scan response data, this is a Blocking API + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API, this is a Blocking API. + * @param[in] data - Data about to be sent + * @param[in] data_len - Length of data, which is about to be sent + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_scan_response_data(const uint8_t *data, uint16_t data_len); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_start_scanning(void) + * @brief Start scanning, this is a Blocking API + * A received event \ref rsi_ble_on_adv_report_event_t indicates advertise report of remote device received. + * @pre Pre-condition: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API, this is a Blocking API. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * 0x4E0C - Command disallowed + * 0x4046 - Invalid Arguments + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_start_scanning(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_start_scanning_with_values(void *rsi_ble_scan_params) + * @brief Start scanning with values. This is a blocking API. A received event \ref rsi_ble_on_adv_report_event_t indicates the advertise report of a remote device received. + * @pre Pre-condition: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] rsi_ble_scan_params - BLE scan parameters structure + * please refer rsi_ble_req_scan_s structure for more info + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * 0x4E0C - Command disallowed + * 0x4046 - Invalid Arguments + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_start_scanning_with_values(void *rsi_ble_scan_params); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_stop_scanning(void) + * @brief Stop scanning. This is a blocking API + * @pre Pre-conditions: + * - \ref rsi_ble_start_scanning() API needs to be called before this API. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * 0x4E0C - Command disallowed + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_stop_scanning(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_connect_with_params(uint8_t remote_dev_addr_type, + * const int8_t *remote_dev_addr, + * uint16_t scan_interval, + * uint16_t scan_window, + * uint16_t conn_interval_max, + * uint16_t conn_interval_min, + * uint16_t conn_latency, + * uint16_t supervision_tout) + * @brief Connect to the remote BLE device with the user configured parameters. This is a blocking API, + * a received event \ref rsi_ble_on_enhance_connect_t / \ref rsi_ble_on_connect_t indicates that the connection successful and + * a received event \ref rsi_ble_on_disconnect_t indicates that connection failures have occurred. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] remote_dev_addr_type - AddressType - Specifies the type of the address mentioned in BD Address + * - 0 - Public Address + * - 1 - Random Address + * @param[in] remote_dev_addr - This parameter describes the device address of remote device + * @param[in] scan_interval - LE Scan Interval : N=0xXXXX + * - It is defined as the time interval from when the Controller started its last LE scan until it + * begins the subsequent LE scan. + * - Range: 0x0004 to 0x4000 + * - Time = N * 0.625 msec + * - Time Range: 2.5 msec to 10 . 24 seconds + * @param[in] scan_window - LE Scan Window : N=0xXXXX + * - Amount of time for the duration of the LE scan. LE_Scan_Window + * must be less than or equal to LE_Scan_Interval + * - Range: 0x0004 to 0x4000 + * - Time = N * 0.625 msec + * - Time Range: 2.5 msec to 10 . 24 seconds + * @param[in] conn_interval_max - Max Connection Interval : N=0xXXXX + * - Minimum value for the connection event interval, which must + * be greater than or equal to Conn_Interval_Min. + * - Range: 0x0006 to 0x0C80 + * - Time = N * 1.25 msec + * - Time Range: 7.5 msec to 4 seconds. + * - 0x0000 - 0x0005 and 0x0C81 - 0xFFFF - Reserved for future use + * @param[in] conn_interval_min - Min Connection Interval : N=0xXXXX + * - Minimum value for the connection event interval, which must + * be greater than or equal to Conn_Interval_Max. + * - Range: 0x0006 to 0x0C80 + * - Time = N * 1.25 msec + * - Time Range: 7.5 msec to 4 seconds. + * - 0x0000 - 0x0005 and 0x0C81 - 0xFFFF - Reserved for future use + * @param[in] conn_latency - Connection Latency : N = 0xXXXX + * - Peripheral latency for the connection in number of connection events. + * - Range: 0x0000 to 0x01F4 + * @param[in] supervision_tout - Supervision Timeout : N = 0xXXXX + * - Supervision timeout for the LE Link. + * - Range: 0x000A to 0x0C80 + * - Time = N * 10 msec + * - Time Range: 100 msec to 32 seconds + * - 0x0000 - 0x0009 and 0x0C81 - 0xFFFF - Reserved for future use + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E0C - Command disallowed + * - 0x4046 - Invalid Arguments + * @note If a connection can't be established, for example, the remote device has gone out of range, has entered into deep sleep, or is not advertising, + * the stack will try to connect forever. In this case, the application will not get an event related to the connection request. + * @note To recover from this situation, the application can implement a timeout and call rsi_ble_connect_cancel() to cancel the connection request. + * Subsequent calls of this command have to wait for the ongoing command to complete. + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_connect_with_params(uint8_t remote_dev_addr_type, + const int8_t *remote_dev_addr, + uint16_t scan_interval, + uint16_t scan_window, + uint16_t conn_interval_max, + uint16_t conn_interval_min, + uint16_t conn_latency, + uint16_t supervision_tout); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_connect(uint8_t remote_dev_addr_type, const int8_t *remote_dev_addr) + * @brief Connect to the remote BLE device. This is a blocking API, + * a received event \ref rsi_ble_on_enhance_connect_t/ \ref rsi_ble_on_connect_t indicates that the connection successful and + * a received event \ref rsi_ble_on_disconnect_t indicates that connection failures have occurred. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] remote_dev_addr_type - This parameter describes the address type of the remote device + * @param[in] remote_dev_addr - This parameter describes the device address of the remote device + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * 0x4E0C - Command disallowed + * 0x4046 - Invalid Arguments + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + * @note If a connection can't be established, for example, the remote device has gone out of range, has entered into deep sleep, or is not advertising, + * @note The stack will try to connect forever. In this case, the application will not get an event related to the connection request. + * @note To recover from this situation, the application can implement a timeout and call rsi_ble_connect_cancel() to cancel the connection request. + * @note Subsequent calls of this command have to wait for the ongoing command to complete. + */ +int32_t rsi_ble_connect(uint8_t remote_dev_addr_type, const int8_t *remote_dev_addr); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_enhance_connect_with_params(void* ble_enhance_conn_params) + * @brief Connect to the remote BLE device with the user configured parameters. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] ble_enhance_conn_params - BLE enhance connection parameter structure. See notes for the fields in this structure. + * @return The following values are returned: + * * - 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 - Buffer not available to serve the command + * 0x4E0C - Command disallowed + * 0x4046 - Invalid Arguments + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + * @note The following fields are included in the ble_enhance_conn_params parameter structure: + * - dev_addr_type - Address type of the device to connect. + * - 0 - Public Address + * - 1 - Random Address + * - dev_addr - Address of the device to connect. + * - filter_policy - Policy used to determine whether the filter accept list is used. + * - 0 - Filter accept list is not used to determine which advertiser to connect to. + * - 1 - Filter accept list is used to determine which advertiser to connect to. + * - own_addr_type - Own address type + * - le_scan_interval - The time interval from when the Controller started its last LE scan until it begins the subsequent LE scan. + * - Range: 0x0004 to 0x4000 + * - Time = le_scan_interval * 0.625 msec + * - Time Range: 2.5 msec to 10 . 24 seconds + * - le_scan_window - Amount of time for the duration of the LE scan. This must be less than or equal to le_scan_interval. + * - Range: 0x0004 to 0x4000 + * - Time = le_scan_window * 0.625 msec + * - Time Range: 2.5 msec to 10 . 24 seconds + * - conn_interval_min - Minimum value for the connection event interval. This must be greater than or equal to conn_interval_max. + * - Range: 0x0006 to 0x0C80 + * - Time = conn_interval_min * 1.25 msec + * - Time Range: 7.5 msec to 4 seconds. + * - 0x0000 - 0x0005 and 0x0C81 - 0xFFFF - Reserved for future use + * - conn_interval_max - Maximum value for the connection event interval. This must be greater than or equal to conn_interval_min. + * - Range: 0x0006 to 0x0C80 + * - Time = conn_interval_max * 1.25 msec + * - Time Range: 7.5 msec to 4 seconds. + * - 0x0000 - 0x0005 and 0x0C81 - 0xFFFF - Reserved for future use + * - conn_latency - Peripheral latency for the connection in number of connection events. + * - Range: 0x0000 to 0x01F4 + * - supervision_tout - Supervision timeout for the LE Link. + * - Range: 0x000A to 0x0C80 + * - Time = N * 10 msec + * - Time Range: 100 msec to 32 seconds + * - 0x0000 - 0x0009 and 0x0C81 - 0xFFFF - Reserved for future use + * - min_ce_length - Minimum length of connection event recommended for this LE connection. + * - Range: 0x0000 to 0xFFFF + * - Time = N * 0.625 msec + * - max_ce_length - Maximum length of connection event recommended for this LE connection. + * - Range: 0x0000 to 0xFFFF + * - Time = N * 0.625 msec + */ +int32_t rsi_ble_enhance_connect_with_params(void *ble_enhance_conn_params); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_connect_cancel(const int8_t *remote_dev_address) + * @brief Cancel the connection to the remote BLE device. This is a blocking API, + * A received event \ref rsi_ble_on_disconnect_t indicates disconnect complete. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - This parameter describes the device address of the remote device + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E0C - Command disallowed + * - 0x4046 - Invalid Arguments + * - 0x4E02 - Unknown Connection Identifier + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_connect_cancel(const int8_t *remote_dev_address); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_disconnect(const int8_t *remote_dev_address) + * @brief Disconnect with the remote BLE device. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - This parameter describes the device address of the remote device + * @return The following values are returned: + * 0 - Success + * Non-Zero Value - Failure + * 0x4E0C - Command disallowed + * 0x4D05 BLE socket not available + * 0x4E62 Invalid Parameters + * 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_disconnect(const int8_t *remote_dev_address); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_device_state(uint8_t *resp) + * @brief Get the local device state. This is a blocking API. The state value is filled in "resp". + * @pre Pre-conditions: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[out] resp - This is an output parameter which consists of local device state. + * This is a 1-byte value. The possible states are described below: + * BIT(0) Advertising state + * BIT(1) Scanning state + * BIT(2) Initiating state + * BIT(3) Connected state + * BIT(4) Extended Advertising state + * BIT(5) Extended Scanning state + * BIT(6) Extended Initiating state + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_device_state(uint8_t *resp); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_smp_pairing_cap_data(rsi_ble_set_smp_pairing_capabilty_data_t *smp_pair_cap_data) + * @brief Set the SMP Pairing Capability of local device. This is a blocking API. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] smp_pair_cap_data - This structure pointer holds the information of the SMP capability data values + * please refer rsi_ble_set_smp_pairing_capabilty_data structure for more info + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_smp_pairing_cap_data(rsi_ble_set_smp_pairing_capabilty_data_t *smp_pair_cap_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_local_irk_value(const uint8_t *l_irk) + * @brief Set the IRK value to the local device. This is a blocking API. + * @pre Pre-conditions: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] l_irk - l_irk Pointer to local_irk + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_local_irk_value(const uint8_t *l_irk); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_conn_param_resp(const uint8_t *remote_dev_address, uint8_t status) + * @brief Give the response for the remote device connection parameter request. This is a blocking API. + * A received event \ref rsi_ble_on_conn_update_complete_t indicates connection update procedure is successful. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - remote device address + * @param[in] status - accept or reject the connection parameters update request + * - 0 - ACCEPT, + * - 1 - REJECT + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E0C - Command disallowed + * - 0x4046 - Invalid Arguments + * - 0x4E02 - Unknown Connection Identifier + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_conn_param_resp(const uint8_t *remote_dev_address, uint8_t status); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_smp_pair_request(uint8_t *remote_dev_address, uint8_t io_capability, uint8_t mitm_req) + * @brief Request the SMP pairing process with the remote device. This is a blocking API. + * - A received event \ref rsi_ble_on_smp_request_t indicated remote device is given Security Request and need to respond back with \ref rsi_ble_smp_pair_request + * - A received event \ref rsi_ble_on_smp_response_t indicated remote device is given SMP Pair Request and need to respond back with \ref rsi_ble_smp_pair_response + * - A received event \ref rsi_ble_on_smp_failed_t indicated SMP procedure have failed + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - This is the remote device address + * @param[in] io_capability - This is the device input output capability + * - 0x00 - Display Only + * - 0x01 - Display Yes/No + * - 0x02 - Keyboard Only + * - 0x03 - No Input No Output + * @param[in] mitm_req - MITM enable/disable + * - 0 - Disable + * - 1 - Enable + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_smp_pair_request(uint8_t *remote_dev_address, uint8_t io_capability, uint8_t mitm_req); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_smp_pair_failed(uint8_t *remote_dev_address, uint8_t reason) + * @brief Send SMP pairing failure reason to the remote device. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - This is the remote device address + * @param[in] reason - This is the reason for SMP Pairing Failure + * - 0x05 - Pairing Not Supported + * - 0x08 - Unspecified Reason + * - 0x09 - Repeated Attempts + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + */ +int32_t rsi_ble_smp_pair_failed(uint8_t *remote_dev_address, uint8_t reason); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_ltk_req_reply(uint8_t *remote_dev_address, + * uint8_t reply_type, const uint8_t *ltk) + * @brief Send the local long term key of its associated local EDIV and local Rand. This is a blocking API. + * - A received event \ref rsi_ble_on_encrypt_started_t indicated encrypted event is received from module + * - A received event \ref rsi_ble_on_smp_failed_t indicated SMP procedure have failed + * @param[in] remote_dev_address - remote device address + * @param[in] reply_type - 0 - Negative reply + * - BIT(0) - Positive Reply (Encryption Enabled) + * - BIT(1) - Un authenticated LTK or STK-based Encryption Enabled + * - BIT(2) - Authenticated LTK or STK-based Encryption Enabled + * - BIT(3) - Authenticated LTK with LE Secure Connections based Encryption Enabled + * - BIT(4) to BIT(6) - Reserved for Future use + * - BIT(7) - LE Secure Connection Enabled + * @param[in] ltk - Long Term Key 16 bytes + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_ltk_req_reply(uint8_t *remote_dev_address, uint8_t reply_type, const uint8_t *ltk); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_smp_pair_response(uint8_t *remote_dev_address, uint8_t io_capability, uint8_t mitm_req) + * @brief Send SMP pairing response during the process of pairing with the remote device. This is a blocking API. + * - A received event \ref rsi_ble_on_smp_passkey_t indicated Legacy SMP passkey is received and need to respond back with \ref rsi_ble_smp_passkey() + * - A received event \ref rsi_ble_on_sc_passkey_t indicated BLE SC passkey is received and need to respond back with \ref rsi_ble_smp_passkey() + * - A received event \ref rsi_ble_on_smp_passkey_display_t indicates SMP passkey display is received from the module + * - A received event \ref rsi_ble_on_smp_failed_t indicated SMP Failed event is received + * @pre Pre-condition: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - This is the remote device address + * @param[in] io_capability - This is the device input output capability + * 0x00 - Display Only + * 0x01 - Display Yes/No + * 0x02 - Keyboard Only + * 0x03 - No Input No Output + * @param[in] mitm_req - MITM Request info + * - 0 - Disable + * - 1 - Enable + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_smp_pair_response(uint8_t *remote_dev_address, uint8_t io_capability, uint8_t mitm_req); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_smp_passkey(uint8_t *remote_dev_address, uint32_t passkey) + * @brief Send SMP passkey during SMP pairing process with the remote device. This is a Blocking API + * A received event \ref rsi_ble_on_encrypt_started_t indicated encrypted event is received from module + * A received event \ref rsi_ble_on_le_security_keys_t indicates exchange of security keys completed after encryption + * A received event \ref rsi_ble_on_smp_failed_t indicated SMP procedure have failed + * @pre Pre-conditions: + * Call \ref rsi_ble_smp_pair_request and \ref rsi_ble_smp_pair_response + * before calling this API. + * @param[in] remote_dev_address - This is the remote device address + * @param[in] passkey - This is the key required in pairing process + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_smp_passkey(uint8_t *remote_dev_address, uint32_t passkey); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_le_ping_timeout(uint8_t *remote_dev_address, uint16_t *time_out) + * @brief Get the timeout value of the LE ping. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - This is the remote device address + * @param[out] time_out - This a response parameter which holds timeout value for + * authentication payload command. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + * @note Currently Get ping is not supported. + */ +int32_t rsi_ble_get_le_ping_timeout(uint8_t *remote_dev_address, uint16_t *time_out); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_le_ping_timeout(uint8_t *remote_dev_address, uint16_t time_out) + * @brief Set the timeout value of the LE ping. This is a blocking API. + * A received event of \ref rsi_ble_on_le_ping_payload_timeout_t indicates LE ping payload timeout expired + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - This is the remote device address + * @param[out] time_out - This input parameter sets timeout value for authentication + * payload command.(in milliseconds) + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_le_ping_timeout(uint8_t *remote_dev_address, uint16_t time_out); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_clear_acceptlist(void) + * @brief Clear all the BD address present in accept list. This is a blocking API. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_clear_acceptlist(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_addto_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type) + * @brief Add BD address to accept list. This is a blocking API. + * @pre Pre-conditions: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] dev_address - Address of the device which is going to add in accept list + * @param[in] dev_addr_type - address type of BD address + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * @note Maximum number of device address that firmware can store is 10. + * Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_addto_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_deletefrom_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type) + * @brief Delete particular BD address from accept list. This is a blocking API. + * @pre Pre-conditions: + * - \ref rsi_ble_addto_acceptlist() API needs to be called before this API. + * @param[in] dev_address - Address of the device which is going to delete from accept list + * @param[in] dev_addr_type - address type of BD address + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_deletefrom_acceptlist(const int8_t *dev_address, uint8_t dev_addr_type); +/*==============================================*/ +/** + * @fn int32_t rsi_ble_resolvlist(uint8_t process_type, + * uint8_t remote_dev_addr_type, + * uint8_t *remote_dev_address, + * const uint8_t *peer_irk, + * const uint8_t *local_irk) + * @brief Resolvlist API used for multiple purposes based on the process type. It will be used to add/remove/clear a device to/from the list. This is a blocking API. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] process_type - Indicates which type of process this is, as follows: + * 1 - add a device to the resolve list + * 2 - remove a device from the resolve list + * 3 - clear the entire resolve list + * @param[in] remote_dev_addr_type - typr of the remote device address + * @param[in] remote_dev_address - remote device address + * 0 - Public identity address + * 1 - Random (static) identity address + * @param[in] peer_irk - 16-byte IRK of the peer device + * @param[in] local_irk - 16-byte IRK of the local device + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_resolvlist(uint8_t process_type, + uint8_t remote_dev_addr_type, + uint8_t *remote_dev_address, + const uint8_t *peer_irk, + const uint8_t *local_irk); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_resolving_list_size(uint8_t *resp) + * @brief Request to get resolving list size. This is a blocking API. + * @pre Pre-conditions: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[out] resp - output parameter which consists of supported resolving the list size. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 : Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_resolving_list_size(uint8_t *resp); +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_addr_resolution_enable(uint8_t enable, uint16_t tout) + * @brief Request to enable address resolution, and to set resolvable private address timeout. This is a blocking API. + * @pre Pre-conditions: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] enable - value to enable/disable address resolution + * - 1 - enables address resolution + * - 0 - disables address resolution + * @param[in] tout - the period for changing address of our local device in seconds + * Value ranges from 0x0001 to 0xA1B8 (1 s to approximately 11.5 hours) + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 : Buffer not available to serve the command + */ +int32_t rsi_ble_set_addr_resolution_enable(uint8_t enable, uint16_t tout); +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_privacy_mode(uint8_t remote_dev_addr_type, + * uint8_t *remote_dev_address, uint8_t privacy_mode) + * @brief Request to set privacy mode for particular device, this is a Blocking API + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] remote_dev_addr_type - type of the remote device address + * 0 - Public Identity Address + * 1 - Random (static) Identity Address + * @param[in] remote_dev_address - remote device address + * @param[in] privacy_mode - type of the privacy mode + * 0 - Network privacy mode + * 1 - Device privacy mode + * @return The following values are returned: + * 0 - Success + * Non-Zero Value - Failure + * If the return value is less than 0 + * -4 : Buffer not available to serve the command + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_privacy_mode(uint8_t remote_dev_addr_type, uint8_t *remote_dev_address, uint8_t privacy_mode); +/*==============================================*/ +/** + * @fn int32_t rsi_ble_readphy(const int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *resp) + * @brief Reads the TX and RX PHY rates of the Connection. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - remote device address + * @param[out] resp - pointer to store the response + please refer \ref rsi_ble_resp_read_phy_s structure for more info. + * @return The following values are returned: + * 0 - Success + * Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_readphy(const int8_t *remote_dev_address, rsi_ble_resp_read_phy_t *resp); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_setphy(const int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_phy, + * uint16_t coded_phy) + * @brief Set TX and RX PHY. This is a blocking API. + * A received event \ref rsi_ble_on_phy_update_complete_t indicates PHY rate update complete. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - remote device address + * @param[in] tx_phy - transmit PHY rate + * BIT(0) - Host prefers to use the LE 1M transmitter PHY (possibly among others) + * - BIT(1) - Host prefers to use the LE 2M transmitter PHY (possibly among others) + * - BIT(2) - Host prefers to use the LE Coded transmitter PHY (possibly among others) + * - BIT(3) - BIT(7) Reserved for future use + * @param[in] rx_phy - receive PHY rate + * BIT(0) - Host prefers to use the LE 1M receiver PHY (possibly among others) + * - BIT(1) - Host prefers to use the LE 2M receiver PHY (possibly among others) + * - BIT(2) - Host prefers to use the LE Coded receiver PHY (possibly among others) + * - BIT(3) - BIT(7) Reserved for future use + * @param[in] coded_phy - TX/RX coded PHY rate + * - 0 = Host has no preferred coding when transmitting on the LE Coded PHY + * - 1 = Host prefers that S=2 coding be used when transmitting on the LE Coded PHY + * - 2 = Host prefers that S=8 coding be used when transmitting on the LE Coded PHY + * - 3 = Reserved for future use + * @return The following values are returned: + * 0 - Success + * Non-Zero Value - Failure + * 0x4D05 BLE socket not available + * 0x4E62 Invalid Parameters + * 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_setphy(const int8_t *remote_dev_address, uint8_t tx_phy, uint8_t rx_phy, uint16_t coded_phy); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_conn_params_update(const uint8_t *remote_dev_address, + * uint16_t min_int, + * uint16_t max_int, + * uint16_t latency, + * uint16_t timeout) + * @brief Requests the connection parameters change with the remote device, + * When the Silicon Labs device acts as a central, this API is used to update the connection parameters. + * When the Silicon Labs device acts as a peripheral, this API is used to request the central to initiate the connection update procedure. This is a blocking API. + * A received event \ref rsi_ble_on_conn_update_complete_t indicates connection parameters update complete. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - remote device address + * @param[in] min_int - minimum value for the connection interval. + * this shall be less than or equal to max_int . + * @param[in] max_int - maximum value for the connection interval. + * this shall be greater than or equal to min_int. + * @param[in] latency - peripheral latency for the connection in number of connection events. + * Ranges from 0 to 499 + * @param[in] timeout - supervision timeout for the LE Link. + * Ranges from 10 to 3200 (Time = N * 10 ms, Time Range: 100 ms to 32 s) + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + * @note min_int and max_int values ranges from 6 to 3200 (Time = N * 1.25 ms, Time Range: 7.5 ms to 4 s) + latency : If latency value is greater than 32 ,Limiting the peripheral latency value to 32 + Max supported peripheral latency is 32 when Device is in peripheral Role. + * + */ +int32_t rsi_ble_conn_params_update(const uint8_t *remote_dev_address, + uint16_t min_int, + uint16_t max_int, + uint16_t latency, + uint16_t timeout); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_data_len(uint8_t *remote_dev_address, uint16_t tx_octets, uint16_t tx_time) + * @brief Sets the TX octets and the TX time of specified link (remote device connection), this is a Blocking API. + * A received event \ref rsi_ble_on_data_length_update_t indicates data length update complete. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] remote_dev_address - remote device device + * @param[in] tx_octets - preferred maximum number of payload octets that the local Controller + * should include in a single Link Layer packet on this connection. + * @param[in] tx_time - preferred maximum number of microseconds that the local Controller + * should use to transmit a single Link Layer packet on this connection. + * @return The following values are returned: + * - 0 - LE_Set_Data_Length command succeeded. + * - Non-Zero Value - Failure + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_data_len(uint8_t *remote_dev_address, uint16_t tx_octets, uint16_t tx_time); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_read_max_data_len(rsi_ble_read_max_data_length_t *blereaddatalen) + * @brief reads the max supported values of TX octets, TX time, RX octets and Rx time. This is a blocking API. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[out] blereaddatalen - pointer to structure variable, + Please refer rsi_ble_resp_read_max_data_length_s structure for more info. + * @return The following values are returned: + * - 0 - command success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_read_max_data_len(rsi_ble_read_max_data_length_t *blereaddatalen); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY6 +* @{ +*/ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_rx_test_mode(uint8_t rx_channel, uint8_t phy, uint8_t modulation) + * @brief Start the BLE RX test mode in controller. This is a blocking API. + * @param[in] rx_channel - Channel in which packet have to be received (0 - 39) + * @param[in] phy - 0x00 Reserved for future use + * 0x01 Receiver set to use the LE 1M PHY + * 0x02 Receiver set to use the LE 2M PHY + * 0x03 Receiver set to use the LE Coded PHY + * (0x04 - 0xFF) Reserved for future use. + * @param[in] modulation - 0x00 Assume transmitter will have a standard standard modulation index + * 0x01 Assume transmitter will have a stable modulation index + * (0x02 - 0xFF) Reserved for future use + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_rx_test_mode(uint8_t rx_channel, uint8_t phy, uint8_t modulation); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_tx_test_mode(uint8_t tx_channel, uint8_t phy, + * uint8_t tx_len, uint8_t mode) + * @brief Start the BLE TX test mode in controller. This is a blocking API. + * @param[in] tx_channel - RF Channel (0-39). + * @param[in] phy - 0x00 Reserved for future use + * - 0x01 Transmitter set to use the LE 1M PHY + * - 0x02 Transmitter set to use the LE 2M PHY + * - 0x03 Transmitter set to use the LE Coded PHY with S=8 data coding + * - 0x04 Transmitter set to use the LE Coded PHY with S=2 data coding + * - (0x05 - 0xFF) Reserved for future use. + * @param[in] tx_len - Length in bytes of payload data in each packet ( 1 - 251 bytes). + * @param[in] mode - 0x00 PRBS9 sequence '11111111100000111101...' + * - 0x01 Repeated '11110000' + * - 0x02 Repeated '10101010' + * - 0x03 PRBS15 + * - 0x04 Repeated '11111111' + * - 0x05 Repeated '00000000' + * - 0x06 Repeated '00001111' + * - 0x07 Repeated '01010101' + * - 0x08 - 0xFF Reserved for future use + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_tx_test_mode(uint8_t tx_channel, uint8_t phy, uint8_t tx_len, uint8_t mode); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_end_test_mode(uint16_t *num_of_pkts) + * @brief Stop the BLE TX / RX test mode in controller. This is a blocking API. + * @param[out] num_of_pkts - Number of RX packets received are displayed when RX test is stopped + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_end_test_mode(uint16_t *num_of_pkts); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_per_transmit(struct rsi_ble_per_transmit_s *rsi_ble_per_tx) + * @brief Initiate the BLE transmit PER mode in the controller. This is a blocking API. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] rsi_ble_per_tx - This parameter is the buffer to hold the structure values + * This is a structure variable of struct \ref rsi_ble_per_transmit_s + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_per_transmit(struct rsi_ble_per_transmit_s *rsi_ble_per_tx); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_per_receive(struct rsi_ble_per_receive_s *rsi_ble_per_rx) + * @brief Initiate the BLE receive PER mode in the controller. This is a blocking API. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] rsi_ble_per_rx - This parameter is the buffer to hold the structure values + * This is a structure variable of struct \ref rsi_ble_per_receive_s + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_per_receive(struct rsi_ble_per_receive_s *rsi_ble_per_rx); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY1 +* @{ +*/ +/*==============================================*/ +/** + * @fn int32_t rsi_ble_accept_list_using_adv_data(uint8_t enable, + * uint8_t data_compare_index, + * uint8_t len_for_compare_data, + * const uint8_t *payload) + * @brief Give vendor-specific command to set the acceptlist feature based on + * the advertisers advertising payload, this is a Blocking API + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] enable - enable/disable + * @param[in] data_compare_index - the starting index of the data to compare + * @param[in] len_for_compare_data - total length of data to compare + * @param[in] payload - Payload + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4E62 Invalid Parameters + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_accept_list_using_adv_data(uint8_t enable, + uint8_t data_compare_index, + uint8_t len_for_compare_data, + const uint8_t *payload); + +/*==============================================*/ +/** + * @fn void BT_LE_ADPacketExtract(uint8_t *remote_name, const uint8_t *pbuf, uint8_t buf_len); + * @brief Used to extract remote Bluetooth device name from the received advertising report. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] remote_name - device name + * @param[in] pbuf - advertise data packet buffer pointer + * @param[in] buf_len - buffer length + * + */ +void BT_LE_ADPacketExtract(uint8_t *remote_name, const uint8_t *pbuf, uint8_t buf_len); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_start_encryption(uint8_t *remote_dev_address, uint16_t ediv, + * const uint8_t *rand, const uint8_t *ltk) + * @brief Start the encryption process with the remote device. This is a blocking API. + * A received event \ref rsi_ble_on_encrypt_started_t indicated encrypted event is received from module. + * A received event \ref rsi_ble_on_le_security_keys_t indicates exchange of security keys completed after encryption. + * A received event \ref rsi_ble_on_smp_failed_t indicated SMP procedure have failed. + * @pre Pre-conditions: + * - Encryption enabled event should come before calling this API for second time SMP connection. + * @param[in] remote_dev_address - Remote BD address in string format + * @param[in] ediv - remote device ediv value. + * @param[in] rand - remote device rand value. + * @param[in] ltk - remote device ltk value. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * - -4 - Buffer not available to serve the command + * - 0x4D05 BLE socket not available + * - 0x4E62 Invalid Parameters + * - 0x4D04 BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_ble_start_encryption(uint8_t *remote_dev_address, uint16_t ediv, const uint8_t *rand, const uint8_t *ltk); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_ble_tx_power(int8_t tx_power) + * @brief Set TX power + * @param[in] tx_power Power value + * @return The following values are returned: + * - 0 - Success + * - Non-zero value - Failure + * - 0x4E02 - Unknown connection identifier + * - 0x4E01 - Unknown HCI command + * - 0x4E0C - Command disallowed + * - 0x4046 - Invalid arguments + * - 0x4D04 - BLE not connected + * - 0x4D14 - BLE parameter out of mandatory range + * - 0x4D15 - Unsuported power index for 915 + * @note This is a Blocking API. + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + * @note The higher power will be backed off based on country region. + * @note Use the following setting to indicate tx_power as an index: `#define RSI_BLE_PWR_INX 30` + * Default value for power index is 31. + * Valid values for power index range from 1 to 31 and 33 to 127: + * - 1 to 31: BLE - 0dBm mode. + * - 33 to 63: BLE - 10dBm mode. + * - 64 to 82: BLE - 1dBm - 18dBm HP mode in the resolution of 1dBm. + * - 104 to 126: BLE - 0.5dBm - 11dBm HP mode in the resolution of 0.5dbm. + * - 127: BLE HP Mode, max power supported. + * @note Use the following setting to indicate tx_power in dBm (-8dBm to 18dBm): `#define RSI_BLE_PWR_INX_DBM 1` + * @note When switching between HP mode and LP mode, please ensure that no protocol activity is running. + * @note For the LP Chain - Power index vs output power in dBm in E2E mode: + * | Power Index | Output Power in dBm | + * ----------------------|-------------------------------------------------------------------| + * | 1 | -22.3054959 | + * | 2 | -16.59332574 | + * | 3 | -13.38278365 | + * | 4 | -11.19804718 | + * | 5 | -9.576522466 | + * | 6 | -8.312070432 | + * | 7 | -7.294640362 | + * | 8 | -6.458448154 | + * | 9 | -5.760963318 | + * | 10 | -5.173042366 | + * | 11 | -4.673788189 | + * | 12 | -4.247653993 | + * | 13 | -3.882708784 | + * | 14 | -3.569545894 | + * | 15 | -3.300567503 | + * | 16 | -3.069499167 | + * | 17 | -2.871050592 | + * | 18 | -2.700672503 | + * | 19 | -2.554378603 | + * | 20 | -2.428612817 | + * | 21 | -2.32014891 | + * | 22 | -2.226013876 | + * | 23 | -2.143429275 | + * | 24 | -2.069766557 | + * | 25 | -2.002513642 | + * | 26 | -1.939250859 | + * | 27 | -1.87763493 | + * | 28 | -1.815390046 | + * | 29 | -1.750305305 | + * | 30 | -1.680237892 | + * | 31 | -1.603121401 | + * | 32 | N/A | + * | 33 | -10.4822997 | + * | 34 | -4.9531679 | + * | 35 | -1.931961022 | + * | 36 | 0.057132993 | + * | 37 | 1.476764101 | + * | 38 | 2.5332116 | + * | 39 | 3.336771823 | + * | 40 | 3.953605265 | + * | 41 | 4.426779615 | + * | 42 | 4.786171523 | + * | 43 | 5.053647759 | + * | 44 | 5.246007208 | + * | 45 | 5.37676618 | + * | 46 | 5.457304255 | + * | 47 | 5.497635316 | + * | 48 | 5.506945838 | + * | 49 | 5.493978354 | + * | 50 | 5.467302132 | + * | 51 | 5.435491631 | + * | 52 | 5.407220119 | + * | 53 | 5.391268248 | + * | 54 | 5.396444507 | + * | 55 | 5.431416481 | + * | 56 | 5.504458826 | + * | 57 | 5.62313521 | + * | 58 | 5.793945208 | + * | 59 | 6.02197959 | + * | 60 | 6.310634089 | + * | 61 | 6.661428559 | + * | 62 | 7.073964236 | + * | 63 | 7.546029076 | + * @note For the HP Chain - Power index vs output power in dBm in E2E mode: + * | Power Index | Output Power in dBm | + * |---------------------|-------------------------------------------------------------------| + * | 64 | 1 | + * | 65 | 2 | + * | 66 | 3 | + * | 67 | 4 | + * | 68 | 5 | + * | 69 | 6 | + * | 70 | 7 | + * | 71 | 8 | + * | 72 | 9 | + * | 73 | 10 | + * | 74 | 11 | + * | 75 | 12 | + * | 76 | 13 | + * | 77 | 14 | + * | 78 | 15 | + * | - | - | + * | - | - | + * | 104 | 0.5 | + * | 105 | 1 | + * | 106 | 1.5 | + * | 107 | 2 | + * | 108 | 2.5 | + * | 109 | 3 | + * | 110 | 3.5 | + * | 111 | 4 | + * | - | - | + * | 126 | 10.5 | + * | 127 | Max Power Supported by Country region | + */ +int32_t rsi_ble_set_ble_tx_power(int8_t tx_power); +/** @} */ + +/****************************************************** + * * GATT Client API's Declarations + * ******************************************************/ + +/** @addtogroup BT-LOW-ENERGY3 +* @{ +*/ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_profiles(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_profiles_list_t *p_prof_list) + * @brief Get the supported profiles / services of the connected + * remote device. The \ref rsi_ble_on_profiles_list_resp_t callback + * function will be called after the profiles list response is received. This is a non-blocking API, + * Still user need to wait until the callback \ref rsi_ble_on_profiles_list_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_prof_list - profiles/services information will be filled in this structure after retrieving from the remote device, + please refer rsi_ble_resp_profiles_list_s structure for more info. + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_profiles(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_profiles_list_t *p_prof_list); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_profile(uint8_t *dev_addr, uuid_t profile_uuid, + * profile_descriptors_t *p_profile) + * @brief Get the specific profile / service of the connected remote device. + * The \ref rsi_ble_on_profile_resp_t callback function is called after the service + * characteristics response is received. This is a non-blocking API, + * Still user need to wait until the callback \ref rsi_ble_on_profile_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] profile_uuid - services/profiles which are searched using profile_uuid + * + * @param[out] p_profile - profile / service information filled in this structure after retrieving from the remote device. + See profile_descriptor_s structure for more info. + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_profile(uint8_t *dev_addr, uuid_t profile_uuid, profile_descriptors_t *p_profile); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_char_services(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_char_services_t *p_char_serv_list) + * @brief Get the service characteristic services of the connected / remote device, + * \ref rsi_ble_on_char_services_resp_t callback function is called after the characteristic service + * response is received, this is a non-blocking API, + * Still user need to wait until the callback \ref rsi_ble_on_char_services_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_char_serv_list - service characteristics details are filled in this structure, please refer rsi_ble_resp_char_serv_s structure for more info. + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_char_services(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_char_services_t *p_char_serv_list); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_inc_services(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_inc_services_t *p_inc_serv_list) + * @brief Get the supported include services of the connected / remote device. + * The \ref rsi_ble_on_inc_services_resp_t callback function is called after + * the include service response is received. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_inc_services_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_inc_serv_list - include service characteristics details are filled in this structure, please refer rsi_ble_resp_inc_serv structure for more info. + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_inc_services(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_inc_services_t *p_inc_serv_list); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_char_value_by_uuid(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * uuid_t char_uuid, + * rsi_ble_resp_att_value_t *p_char_val) + * @brief Get the characteristic value by UUID (char_uuid). + * The \ref rsi_ble_on_read_resp_t callback function is called after the attribute value is received. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_read_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[in] char_uuid - UUID of the characteristic + * @param[out] p_char_val - Characteristic value is filled in this structure. See rsi_ble_resp_att_value_s structure for more info. + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - If the return value is less than 0 + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_char_value_by_uuid(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + uuid_t char_uuid, + rsi_ble_resp_att_value_t *p_char_val); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_att_descriptors(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_att_descs_t *p_att_desc) + * @brief Get the characteristic descriptors list from the remote device. + * The \ref rsi_ble_on_att_desc_resp_t callback function is called after + * the attribute descriptors response is received. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_att_desc_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_att_desc - pointer to characteristic descriptor structure, Please refer rsi_ble_resp_att_descs_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_att_descriptors(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_att_descs_t *p_att_desc); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_att_value(uint8_t *dev_addr, uint16_t handle, rsi_ble_resp_att_value_t *p_att_val) + * @brief Get the attribute by handle. + * The \ref rsi_ble_on_read_resp_t callback function is called upon receiving the attribute value. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_read_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - handle value of the attribute + * @param[out] p_att_val - attribute value is filled in this structure, Please refer rsi_ble_resp_att_value_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + * + */ +int32_t rsi_ble_get_att_value(uint8_t *dev_addr, uint16_t handle, rsi_ble_resp_att_value_t *p_att_val); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_multiple_att_values(uint8_t *dev_addr, + * uint8_t num_of_handlers, + * const uint16_t *handles, + * rsi_ble_resp_att_value_t *p_att_vals) + * @brief Get the multiple attribute values by using multiple handles. + * The \ref rsi_ble_on_read_resp_t callback function is called after the attribute value is received. This is a non-blocking API, + * Still user need to wait until the callback \ref rsi_ble_on_read_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] num_of_handlers - number of handles in the list + * @param[in] handles - list of attribute handles + * @param[out] p_att_vals - attribute values filled in this structure, please refer rsi_ble_resp_att_value_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_multiple_att_values(uint8_t *dev_addr, + uint8_t num_of_handlers, + const uint16_t *handles, + rsi_ble_resp_att_value_t *p_att_vals); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_long_att_value(uint8_t *dev_addr, + * uint16_t handle, + * uint16_t offset, + * rsi_ble_resp_att_value_t *p_att_vals) + * @brief Get the long attribute value by using handle and offset. + * The \ref rsi_ble_on_read_resp_t callback function is called after the attribute value is received. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_read_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute handle + * @param[in] offset - offset within the attribute value + * @param[out] p_att_vals - attribute value filled in this structure, please refer rsi_ble_resp_att_value_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_long_att_value(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + rsi_ble_resp_att_value_t *p_att_vals); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, + * uint8_t data_len, const uint8_t *p_data) + * @brief Set the attribute value of the remote device, + * \ref rsi_ble_on_write_resp_t callback function is called if the attribute set action is completed, this is a non-blocking API, + * Still user need to wait until the callback \ref rsi_ble_on_write_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute value handle + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_att_value(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_att_cmd(uint8_t *dev_addr, uint16_t handle, + * uint8_t data_len, const uint8_t *p_data) + * @brief Set the attribute value without waiting for an ACK from the remote device. This is a blocking API. + * If the API returns RSI_ERROR_BLE_DEV_BUF_FULL (-31) error then wait until the \ref rsi_ble_on_le_more_data_req_t event gets received from the module. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute value handle + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * - 0x4E65 - Invalid Attribute Length When Small Buffer Mode is Configured + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_att_cmd(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_long_att_value(uint8_t *dev_addr, + * uint16_t handle, + * uint16_t offset, + * uint8_t data_len, + * const uint8_t *p_data) + * @brief Set the long attribute value of the remote device. The \ref rsi_ble_on_write_resp_t + * callback function is called after the attribute set action is completed. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_write_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute handle + * @param[in] offset - attribute value offset + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_long_att_value(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + uint8_t data_len, + const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_prepare_write(uint8_t *dev_addr, uint16_t handle, uint16_t offset, + * uint8_t data_len, const uint8_t *p_data) + * @brief Prepare the attribute value. The \ref rsi_ble_on_write_resp_t + * callback function is called after the prepare attribute write action is completed. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_write_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute handle + * @param[in] offset - attribute value offset + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + * + */ +int32_t rsi_ble_prepare_write(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + uint8_t data_len, + const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_execute_write(uint8_t *dev_addr, uint8_t exe_flag) + * @brief Execute the prepared attribute values. The \ref rsi_ble_on_write_resp_t + * callback function is called after the execute attribute write action is completed. This is a non-blocking API. + * Still user need to wait until the callback \ref rsi_ble_on_write_resp_t is received from the device, + * to initiate further attribute related transactions on this remote device address. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] exe_flag - execute flag to write, possible values mentioned below + * - 0 - BLE_ATT_EXECUTE_WRITE_CANCEL + * - 1 - BLE_ATT_EXECUTE_PENDING_WRITES_IMMEDIATELY + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_execute_write(uint8_t *dev_addr, uint8_t exe_flag); +/** @} */ + +/******************************************************** + * * GATT Server API's Declarations + * ******************************************************/ +/** @addtogroup BT-LOW-ENERGY5 +* @{ +*/ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_add_service(uuid_t service_uuid, rsi_ble_resp_add_serv_t *p_resp_serv) + * @brief Add a new service to the local GATT Server. This is a blocking API. + * @pre Pre-conditions: + * - Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] service_uuid - new service UUID value, please refer uuid_s structure for more info. + * @param[out] p_resp_serv - new service handler filled in this structure, please refer rsi_ble_resp_add_serv_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4D08 - Profile record full + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_add_service(uuid_t service_uuid, rsi_ble_resp_add_serv_t *p_resp_serv); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_add_attribute(rsi_ble_req_add_att_t *p_attribute) + * @brief Add a new attribute to a specific service. This is a blocking API. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] p_attribute - add a new attribute to the service, please refer rsi_ble_req_add_att_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4D09 - Attribute record full + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_add_attribute(rsi_ble_req_add_att_t *p_attribute); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, + * const uint8_t *p_data) + * @brief Change the local attribute value. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] handle - attribute value handle + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4D06 - Attribute record not found + * - 0x4E60 - Invalid Handle Range + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + * @note This API can only be used if the service is maintained inside the firmware. + * @note The services which are maintained by firmware must follow the below rules. + * @note Rule 1: The attribute_data_size is less than 20 bytes during the service_creation + * @note Rule 2: while creating the service, don't use the RSI_BLE_ATT_MAINTAIN_IN_HOST bit + * in the RSI_BLE_ATT_CONFIG_BITMAP macro. + * @note Rule 3: The data_len must be less than or equal to the dat_length mentioned while + * creating the service/attribute + * @note Rule 4: If the services are maintained in the Application/Host, + * then need to use \ref rsi_ble_notify_value() API to send the notifications to the remote devices. + */ +int32_t rsi_ble_set_local_att_value(uint16_t handle, uint16_t data_len, const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_wo_resp_notify_buf_info(const uint8_t *dev_addr, uint8_t buf_mode, + * uint8_t buf_cnt) + * @brief Configure the buf mode for Notify and WO response commands for the remote device. This is a blocking API. + * @param[in] dev_addr - remote device address + * @param[in] buf_mode - buffer mode configuration + * - 0 - BLE_SMALL_BUFF_MODE + * - 1 - BLE_BIG_BUFF_MODE + * @param[in] buf_cnt - no of buffers to be configured + * only value 1 and 2 are supported in BLE_SMALL_BUFF_MODE + in BLE_BIG_BUFF_MODE, buffers allocated based on the below notations. + intial available_buf_cnt = RSI_BLE_NUM_CONN_EVENTS, + a) When connection 1 is formed, the possible range of buffers is (available_buf_cnt - remaining possible number of connections) + b) After allocating X buffers using \ref rsi_ble_set_wo_resp_notify_buf_info to the 1st connection remaining available_buf_cnt = (available_buf_cnt - X ) + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4D05 - BLE socket not available + * - 0x4D06 - Attribute record not found + * - 0x4E60 - Invalid Handle Range + * - 0x4E63 - BLE Buffer Count Exceeded + * - 0x4E64 - BLE Buffer already in use + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_wo_resp_notify_buf_info(const uint8_t *dev_addr, uint8_t buf_mode, uint8_t buf_cnt); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_notify_value(const uint8_t *dev_addr, uint16_t handle, + * uint16_t data_len, const uint8_t *p_data) + * @brief Notify the local value to the remote device. This is a blocking API. + * If the API returns RSI_ERROR_BLE_DEV_BUF_FULL (-31) error then wait until the \ref rsi_ble_on_le_more_data_req_t event gets received from the module. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - local attribute handle + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4A0D - Invalid attribute value length + * - 0x4D05 - BLE socket not available + * - 0x4D06 - Attribute record not found + * - 0x4E60 - Invalid Handle Range + * - 0x4E65 - Invalid Attribute Length When Small Buffer Mode is Configured + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + * @note If the services are maintained in the Application/Host, + * then need to use \ref rsi_ble_notify_value() API instead of using \ref rsi_ble_set_local_att_value() API + * to send the notifications to the remote devices. + */ +int32_t rsi_ble_notify_value(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_indicate_value(const uint8_t *dev_addr, uint16_t handle, + * uint16_t data_len, const uint8_t *p_data) + * @brief Indicate the local value to the remote device. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_indicate_confirmation_t. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - local attribute handle + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D05 - BLE socket not available + * - 0x4E60 - Invalid Handle Range + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_indicate_value(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY4 + * @{ + */ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_indicate_value_sync(const uint8_t *dev_addr, uint16_t handle, + * uint16_t data_len, const uint8_t *p_data) + * @brief Indicate the local value to the remote device. This is a blocking API. + * + * This will not send any confirmation event to the application instead + * + * send the status as success on receiving confirmation from remote side. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - local attribute handle + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D05 - BLE socket not available + * - 0x4E60 - Invalid Handle Range + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_indicate_value_sync(const uint8_t *dev_addr, uint16_t handle, uint16_t data_len, const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_indicate_confirm(const uint8_t *dev_addr) + * @brief Send indicate confirmation to the remote device. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D05 - BLE socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_indicate_confirm(const uint8_t *dev_addr); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY5 +* @{ +*/ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_local_att_value(uint16_t handle, + * rsi_ble_resp_local_att_value_t *p_resp_local_att_val) + * @brief Get the local attribute value. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] handle - local attribute handle + * @param[out] p_resp_local_att_val - local attribute value filled in this structure, see rsi_ble_resp_local_att_value_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4D06 - Attribute record not found + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + * @note This API can only be used if the service is maintained inside the firmware. The services which are maintained by firmware must + * follow the below rules. + * @note Rule 1: The attribute_data_size is less than 20 bytes during the service_creation + * @note Rule 2: While creating the service, don't use the RSI_BLE_ATT_MAINTAIN_IN_HOST bit in the RSI_BLE_ATT_CONFIG_BITMAP macro. + */ +int32_t rsi_ble_get_local_att_value(uint16_t handle, rsi_ble_resp_local_att_value_t *p_resp_local_att_val); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_gatt_read_response(uint8_t *dev_addr, + * uint8_t read_type, + * uint16_t handle, + * uint16_t offset, + * uint16_t length, + * const uint8_t *p_data) + * @brief Send the response for the read request received from the remote device This is a blocking API. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device Address + * @param[in] read_type - read value type + * - 0 - Read response + * - 1 - Read blob response + * @param[in] handle - attribute value handle + * @param[in] offset - attribute value offset + * @param[in] length - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D04 - BLE not connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_gatt_read_response(uint8_t *dev_addr, + uint8_t read_type, + uint16_t handle, + uint16_t offset, + uint16_t length, + const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_remove_gatt_service(uint32_t service_handler) + * @brief Remove the GATT service record. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] service_handler - GATT service record handle + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D0A - BLE profile not found (profile handler invalid) + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_remove_gatt_service(uint32_t service_handler); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_remove_gatt_attibute(uint32_t service_handler, uint16_t att_hndl) + * @brief Remove the GATT attribute record. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] service_handler - GATT service record handle + * @param[in] att_hndl - attribute handle + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D06 - Attribute record not found + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_remove_gatt_attibute(uint32_t service_handler, uint16_t att_hndl); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_att_error_response(uint8_t *dev_addr, uint16_t handle, + * uint8_t opcode, uint8_t err) + * @brief Send attribute error response for any of the att request. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute handle + * @param[in] opcode - error response opcode + * @param[in] err - specific error related Gatt + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D04 - BLE not Connected + * - 0x4E62 - Invalid Parameters + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_att_error_response(uint8_t *dev_addr, uint16_t handle, uint8_t opcode, uint8_t err); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY3 +* @{ +*/ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_mtu_exchange_event(uint8_t *dev_addr, uint8_t mtu_size) + * @brief Initiates the MTU exchange request with the remote device. + * This is a blocking API and will receive a callback event \ref rsi_ble_on_mtu_event_t as the response for this API. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] mtu_size - requested MTU value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D04 - BLE not Connected + * - 0x4E62 - Invalid Parameters + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_mtu_exchange_event(uint8_t *dev_addr, uint8_t mtu_size); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_mtu_exchange_resp(uint8_t *dev_addr, uint8_t mtu_size) + * @brief This function (Exchange MTU Response) is sent in reply to a received Exchange MTU Request. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - Remote Device Address + * @param[in] mtu_size - requested MTU value + * @return The following values are returned: + * - 0 - Success + * - 0x4D0C - When RSI_BLE_MTU_EXCHANGE_FROM_HOST BIT is not SET. + * - 0x4D05 - BLE Socket Not Available. + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_mtu_exchange_resp(uint8_t *dev_addr, uint8_t mtu_size); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY5 +* @{ +*/ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_gatt_write_response(uint8_t *dev_addr, uint8_t type) + * @brief Send the response to the write request received from the remote device. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] type - response type + * - 0 - write response, + * - 1 - execute write response. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4D04 - BLE not Connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_gatt_write_response(uint8_t *dev_addr, uint8_t type); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_gatt_prepare_write_response(uint8_t *dev_addr, + * uint16_t handle, + * uint16_t offset, + * uint16_t length, + * const uint8_t *data) + * @brief Send the response for the prepare write requests received from the remote device. This is a blocking API. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute value handle + * @param[in] offset - attribute value offset + * @param[in] length - attribute value length + * @param[in] data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4046 - Invalid Arguments + * - 0x4D04 - BLE not Connected + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) + */ +int32_t rsi_ble_gatt_prepare_write_response(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + uint16_t length, + const uint8_t *data); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY1 +* @{ */ +/*========================================================*/ +/** + * @fn int32_t rsi_ble_get_max_adv_data_len(uint8_t *resp) + * @brief Get maximum advertising data length + * @param[out] resp Maximum supported advertising data length returned by the controller. Possible values range from 0x001F to 0x0672. + * @return The following values are returned: + * - 0 = success + * @return The following values are returned: + * - !0 = failure + * @note This function requests the controller to return the maximum supported advertising data length. + */ +int32_t rsi_ble_get_max_adv_data_len(uint8_t *resp); + +/*========================================================*/ +/** + * @fn int32_t rsi_ble_get_max_no_of_supp_adv_sets(uint8_t *resp) + * @brief Get maximum number of advertising sets + * @param[out] resp Number of supported advertising sets returned by the controller. Possible values range from 0x01 to 0xF0. + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + * @note This function requests the controller to return the maximum number of supporting advertising sets. + * @note The number of supported advertising sets can be configured through the operating modes. + */ +int32_t rsi_ble_get_max_no_of_supp_adv_sets(uint8_t *resp); + +/*==============================================*/ +/** + * @fn rsi_ble_set_ae_set_random_address(uint8_t handle, const uint8_t *rand_addr) + * @brief Update AE random address + * @param[in] handle The advertising handle used to identify an advertising set + * @param[in] rand_addr Random device address set to either a static or private address + * @return The following values are returned: + * - 0 = success + * @return The following values are returned: + * - !0 = failure + */ +int32_t rsi_ble_set_ae_set_random_address(uint8_t handle, const uint8_t *rand_addr); + +/*========================================================*/ +/** + * @fn int32_t rsi_ble_set_ae_data(void *ble_ae_data) + * @brief Update AE advertiser data + * @param[in] ble_ae_data Extended Advertising data to be updated + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + * @note This function sets the AE advertiser data used in advertising PDUs. + * @note Refer to Bluetooth specification 5.3 for possible combinations ae_adv/scanresp data can be set for . + */ +int32_t rsi_ble_set_ae_data(void *ble_ae_data); + +/*========================================================*/ +/** + * @fn int32_t rsi_ble_set_ae_params(void *ble_ae_params, int8_t *sel_tx_pwr) + * @brief Update AE parameters + * @param[in] ble_ae_params Extended Advertising parameters to be updated + * @param[out] sel_tx_pwr Output transmit power in dBm, ranging from -127 to +20. + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + */ +int32_t rsi_ble_set_ae_params(void *ble_ae_params, int8_t *sel_tx_pwr); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_start_ae_advertising(void *adv_enable) + * @brief Enable or disable AE advertising + * @param[in] adv_enable Parameters to enable or disable specific advertising sets identified by advertising handle + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + */ +int32_t rsi_ble_start_ae_advertising(void *adv_enable); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_app_adv_set_clear_or_remove(uint8_t type, uint8_t handle) + * @brief Clear or remove an advertising set + * @param[in] type Set to 1 to clear, or 2 to remove an advertising set + * @param[in] handle Advertising handle identifying the advertising set to remove or clear. Possible values range from 0x00 to 0xEF. + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + */ +int32_t rsi_ble_app_adv_set_clear_or_remove(uint8_t type, uint8_t handle); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_app_set_periodic_ae_params(void *periodic_adv_params) + * @brief Update periodic AE parameters + * @param[in] periodic_adv_params Periodic advertising parameters to be updated + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + */ +int32_t rsi_ble_app_set_periodic_ae_params(void *periodic_adv_params); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_app_set_periodic_ae_enable(uint8_t enable, uint8_t handle) + * @brief Enable or disable periodic advertising + * @param[in] enable Set to 0 to enable, or 1 to include the ADI field in AUX_SYNC_IND PDUs + * @param[in] handle Advertising handle of the advertising set to enable or disable + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + * @note + * This function requests the controller to enable or disable periodic advertising for the specified advertising set. + */ +int32_t rsi_ble_app_set_periodic_ae_enable(uint8_t enable, uint8_t handle); + +/*========================================================*/ +/** + * @fn int32_t rsi_ble_ae_set_scan_params(void *ae_scan_params) + * @brief Update AE scan parameters + * @param[in] ae_scan_params Extended scan parameters to be updated + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + * @note + * This function sets the extended scan parameters to be used on the physical advertising channels. + */ +int32_t rsi_ble_ae_set_scan_params(void *ae_scan_params); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_ae_set_scan_enable(void *ae_scan_enable) + * @brief Enable or disable legacy and extended scanning + * @param[in] ae_scan_enable Parameters specify whether to enable or disable both legacy and extended advertising PDUs + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + */ +int32_t rsi_ble_ae_set_scan_enable(void *ae_scan_enable); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_ae_set_periodic_sync(uint8_t type, void *periodic_sync_data) + * @brief Synchronize periodic advertising with advertiser + * @param[in] type Set to 1 to begin, 2 to cancel, or 3 to terminate the periodic advertising sync + * @param[in] periodic_sync_data Parameters for starting a perodic advertising sync operation + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * 0x4E42 = unknown advertising identifier + * @return The following values are returned: + * 0x4E0C = command not permitted + * @note + * This function performs an operation to synchronize with a periodic advertising train from an advertiser and begin receiving periodic advertising packets. + * @note + * The operation is either started, cancelled or terminated depending on the type parameter. + */ +int32_t rsi_ble_ae_set_periodic_sync(uint8_t type, void *periodic_sync_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_ae_dev_to_periodic_list(void *dev_to_list) + * @brief Manage a device in the periodic advertiser list + * @param[in] dev_to_list Details of a device to be added to the periodic advertiser list + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + * @note + * This function adds, removes, or clears a device from the periodic advertiser list. + */ +int32_t rsi_ble_ae_dev_to_periodic_list(void *dev_to_list); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_ae_read_periodic_adv_list_size(uint8_t *resp) + * @brief Get periodic advertiser list size + * @param[out] resp Periodic advertiser list size returned by the controller + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + */ +int32_t rsi_ble_ae_read_periodic_adv_list_size(uint8_t *resp); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_extended_connect_with_params(void *ble_extended_conn_params) + * @brief Establish ACL connection to advertiser + * @param[in] ble_extended_conn_params Connection parameters + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + * @note + * This function establishes an ACL connection to an advertiser, with the local device in the BLE central role. + */ +int32_t rsi_ble_extended_connect_with_params(void *ext_create_conn); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_read_transmit_power(void *resp) + * @brief Get supported transmit power range + * @param[out] resp Minimum and maximum supported transmit power, returned by the controller. Power ranges from -127 dBm to +20 dBm. + * @return The following values are returned: + * 0 = success + * @return The following values are returned: + * !0 = failure + * @note + * This function requests the controller to return the minimum and maximum supported transmit power. + */ +int32_t rsi_ble_read_transmit_power(void *resp); + +/** @} */ + +// GATT Client Functions +/********************************************************************** + * In all GAT client APIs, all actions (get/set/write) are referred to + * the GATT server running on the remote / connected device. + *********************************************************************/ + +/** @addtogroup BT-LOW-ENERGY4 +* @{ +*/ + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_profiles_async(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_profiles_list_t *p_prof_list) + * @brief Get the supported profiles / services of the connected + * remote device asynchronously. The \ref rsi_ble_on_event_profiles_list_t callback function will be + * called after the profiles list event is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_profiles_list_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_prof_list - Profiles/services information will be filled in this structure after retrieving from the remote device. + See the rsi_ble_resp_profiles_list_s structure for more info. + * + * @note p_prof_list structure should be passed as NULL because nothing will be filled in this structure + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ + +int32_t rsi_ble_get_profiles_async(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_profiles_list_t *p_prof_list); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_profile_async(uint8_t *dev_addr, uuid_t profile_uuid, + * profile_descriptors_t *p_profile) + * @brief Get the specific profile / service of the connected remote device. + * The rsi_ble_one_event_profile_by_uuid_t callback function is called after + * the service characteristics response is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either rsi_ble_one_event_profile_by_uuid_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] profile_uuid - services/profiles which are searched using profile_uuid + * @param[out] p_profile - profile / service information filled in this structure after retrieving from the remote device, + * please refer profile_descriptor_s structure for more info. + * @note p_profile structure should be passed as NULL because nothing will be filled in this structure + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_profile_async(uint8_t *dev_addr, uuid_t profile_uuid, profile_descriptors_t *p_profile); + +/*==============================================*/ +/** + * @fn rint32_t rsi_ble_get_char_services_async(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_char_services_t *p_char_serv_list) + * @brief Get the service characteristics of the connected / remote device. + * The \ref rsi_ble_on_event_read_by_char_services_t callback function is called after + * the included service characteristics response is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_read_by_char_services_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_char_serv_list - Service Characteristics details are filled in this structure. See rsi_ble_resp_char_serv_s structure for more info. + * + * @note p_char_services_list structure should be passed as NULL because nothing will be filled in this structure + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_char_services_async(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_char_services_t *p_char_serv_list); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_inc_services_async(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_inc_services_t *p_inc_serv_list) + * @brief Get the supported include services of the connected / remote device. + * The \ref rsi_ble_on_event_read_by_inc_services_t callback function is called after + * the service characteristics response is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_read_by_inc_services_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_inc_serv_list - include service characteristics details are filled in this structure, please refer rsi_ble_resp_inc_serv structure for more info. + * + * @note p_inc_serv_list structure should be passed as NULL because nothing will be filled in this structure + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_inc_services_async(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_inc_services_t *p_inc_serv_list); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_char_value_by_uuid_async(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * uuid_t char_uuid, + * rsi_ble_resp_att_value_t *p_char_val) + * @brief Get the characteristic value by UUID (char_uuid). + * The \ref rsi_ble_on_event_read_att_value_t callback function is called + * after the attribute value is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_read_att_value_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * - \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[in] char_uuid - UUID of the characteristic + * @param[out] p_char_val - characteristic value is filled in this structure, please refer rsi_ble_resp_att_value_s structure for more info. + * @note p_char_val structure should be passed as NULL because nothing will be filled in this structure + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_char_value_by_uuid_async(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + uuid_t char_uuid, + rsi_ble_resp_att_value_t *p_char_val); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_att_descriptors_async(uint8_t *dev_addr, + * uint16_t start_handle, + * uint16_t end_handle, + * rsi_ble_resp_att_descs_t *p_att_desc) + * @brief Get the characteristic descriptors list from the remote device. The \ref rsi_ble_on_gatt_desc_val_event_t + * callback function is called after the attribute descriptors response is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_gatt_desc_val_event_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] start_handle - start handle (index) of the remote device's service records + * @param[in] end_handle - end handle (index) of the remote device's service records + * @param[out] p_att_desc - pointer to characteristic descriptor structure, Please refer rsi_ble_resp_att_descs_s strcuture for more info. + * + * @note p_att_desc structure should be passed as NULL because nothing will be filled in this structure + * + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_att_descriptors_async(uint8_t *dev_addr, + uint16_t start_handle, + uint16_t end_handle, + rsi_ble_resp_att_descs_t *p_att_desc); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_att_value_async(uint8_t *dev_addr, uint16_t handle, + * rsi_ble_resp_att_value_t *p_att_val) + * @brief Get the attribute with a handle. + * The \ref rsi_ble_on_event_read_resp_t callback function is called upon receiving the attribute value. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_read_resp_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - handle value of the attribute + * @param[out] p_att_val - attribute value is filled in this structure, Please refer rsi_ble_resp_att_value_s structure for more info. + * @note p_att_val structure should be passed as NULL because nothing will be filled in this structure + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_att_value_async(uint8_t *dev_addr, uint16_t handle, rsi_ble_resp_att_value_t *p_att_val); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_multiple_att_values_async(uint8_t *dev_addr, + * uint8_t num_of_handlers, + * const uint16_t *handles, + * rsi_ble_resp_att_value_t *p_att_vals) + * @brief Get the multiple attribute values by using multiple handles. + * The \ref rsi_ble_on_event_read_resp_t callback function is called after the attribute value is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_read_resp_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] num_of_handlers - number of handles in the list + * @param[in] handles - list of attribute handles + * @param[out] p_att_vals - attribute values filled in this structure, please refer rsi_ble_resp_att_value_s structure for more info. + * @note p_att_vals structure should be passed as NULL because nothing will be filled in this structure + * @return The following values are returned: + * - 0 - Success + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_multiple_att_values_async(uint8_t *dev_addr, + uint8_t num_of_handlers, + const uint16_t *handles, + rsi_ble_resp_att_value_t *p_att_vals); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_get_long_att_value_async(uint8_t *dev_addr, + * uint16_t handle, + * uint16_t offset, + * rsi_ble_resp_att_value_t *p_att_vals) + * @brief Get the long attribute value by using handle and offset. + * The \ref rsi_ble_on_event_read_resp_t callback function is called after the attribute value is received. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_read_resp_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute handle + * @param[in] offset - offset within the attribute value + * @param[out] p_att_vals - attribute value filled in this structure, please refer rsi_ble_resp_att_value_s structure for more info. + * @note p_att_vals structure should be passed as NULL because nothing will be filled in this structure + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_get_long_att_value_async(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + rsi_ble_resp_att_value_t *p_att_vals); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_set_att_value_async(uint8_t *dev_addr, uint16_t handle, + * uint8_t data_len, const uint8_t *p_data) + * @brief Set the attribute value of the remote device. The \ref rsi_ble_on_event_write_resp_t + * callback function is called after the attribute set action is completed. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_write_resp_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute value handle + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_set_att_value_async(uint8_t *dev_addr, uint16_t handle, uint8_t data_len, const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_prepare_write_async(uint8_t *dev_addr, + * uint16_t handle, + * uint16_t offset, + * uint8_t data_len, + * const uint8_t *p_data) + * @brief Prepare the attribute value. The \ref rsi_ble_on_event_prepare_write_resp_t + * callback function is called after the prepare attribute write action is completed. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_prepare_write_resp_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API + * @param[in] dev_addr - remote device address + * @param[in] handle - attribute handle + * @param[in] offset - attribute value offset + * @param[in] data_len - attribute value length + * @param[in] p_data - attribute value + * @return The following values are returned: + * - 0 - Success + * - 0x4E60 - Invalid Handle range + * - 0x4E62 - Invalid Parameters + * - 0x4D04 - BLE not connected + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_prepare_write_async(uint8_t *dev_addr, + uint16_t handle, + uint16_t offset, + uint8_t data_len, + const uint8_t *p_data); + +/*==============================================*/ +/** + * @fn int32_t rsi_ble_execute_write_async(uint8_t *dev_addr, uint8_t exe_flag) + * @brief Execute the prepared attribute values. The \ref rsi_ble_on_event_write_resp_t + * callback function is called after the execute attribute write action is completed. This is a blocking API and can unblock the application + * on the reception of the callback functions either \ref rsi_ble_on_event_write_resp_t or \ref rsi_ble_on_gatt_error_resp_t. + * @pre Pre-conditions: + * \ref rsi_ble_connect() API needs to be called before this API. + * @param[in] dev_addr - remote device address + * @param[in] exe_flag - execute flag to write, possible values mentioned below + * - 0 - BLE_ATT_EXECUTE_WRITE_CANCEL + * - 1 - BLE_ATT_EXECUTE_PENDING_WRITES_IMMEDIATELY + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 0x4D05 - BLE Socket not available + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_ble_execute_write_async(uint8_t *dev_addr, uint8_t exe_flag); +/** @} */ + +/*==============================================*/ + +/** + * @fn uint32_t rsi_ble_cbfc_connreq(uint8_t *dev_addr, uint16_t psm) + * @brief Sends a connection request to a remote device using the Credit Based Flow Control (CBFC) mechanism. + * + * This function sends a connection request to a remote device using the CBFC mechanism. It takes the device address and the Protocol Service Multiplexer (PSM) as input parameters. + * + * @param dev_addr Pointer to the device address of the remote device. + * @param psm The Protocol Service Multiplexer (PSM) value. + * + * @return Returns a 32-bit unsigned integer indicating the status of the connection request. + * - 0: If the connection request is successful. + * - Non-zero: If there is an error in sending the connection request. + */ +uint32_t rsi_ble_cbfc_connreq(uint8_t *dev_addr, uint16_t psm); + +/** + * @fn uint32_t rsi_ble_cbfc_connresp(uint8_t *dev_addr, uint16_t lcid, uint8_t result) + * @brief Sends a connection response for a credit-based flow control (CBFC) connection. + * + * This function is used to send a connection response for a CBFC connection in the Bluetooth Low Energy (BLE) module. + * + * @param dev_addr The device address of the remote device. + * @param lcid The logical channel ID of the connection. + * @param result The result of the connection response. + * + * @return The status of the operation. Returns a 32-bit unsigned integer. + */ +uint32_t rsi_ble_cbfc_connresp(uint8_t *dev_addr, uint16_t lcid, uint8_t result); + +/** + * @fn uint32_t rsi_ble_cbfc_data_tx(uint8_t *dev_addr, uint16_t lcid, uint16_t len, uint8_t *p_data) + * @brief Transmits data over a Connection-Based Flow Control (CBFC) channel in the Bluetooth Low Energy (BLE) module. + * + * This function is used to transmit data over a CBFC channel in the BLE module. It takes the device address, logical channel ID (LCID), + * length of the data, and a pointer to the data as input parameters. The function returns a 32-bit unsigned integer as the status of the transmission. + * + * @param dev_addr Pointer to the device address of the BLE module. + * @param lcid Logical channel ID of the CBFC channel. + * @param len Length of the data to be transmitted. + * @param p_data Pointer to the data to be transmitted. + * + * @return 32-bit unsigned integer representing the status of the transmission. + */ +uint32_t rsi_ble_cbfc_data_tx(uint8_t *dev_addr, uint16_t lcid, uint16_t len, uint8_t *p_data); + +/** + * @fn uint32_t rsi_ble_cbfc_disconnect(uint8_t *dev_addr, uint16_t lcid) + * @brief Disconnects a Connection-Based Flow Control (CBFC) connection with the specified device address and logical channel ID. + * + * This function is used to disconnect a CBFC connection with the specified device address and logical channel ID. + * + * @param dev_addr The device address of the remote device. + * @param lcid The logical channel ID of the CBFC connection. + * + * @return The status code indicating the success or failure of the operation. + * - Returns 0 on success. + * - Returns a non-zero value on failure. + */ +uint32_t rsi_ble_cbfc_disconnect(uint8_t *dev_addr, uint16_t lcid); + +/****************************************************** + * * BLE GAP Callbacks Declarations + * ******************************************************/ +/** @addtogroup BT-LOW-ENERGY8 +* @{ +*/ +/** + * @typedef void (*rsi_ble_on_adv_report_event_t)(rsi_ble_event_adv_report_t *rsi_ble_event_adv); + * @brief Callback function advertise event report from the module. + * This callback function is called whenever an advertise event report is received from the module. + * It has to registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] rsi_ble_event_adv contains the advertise report information. Please refer rsi_ble_event_adv_report_s for more info. + * @return The following values are returned: + * void + */ +typedef void (*rsi_ble_on_adv_report_event_t)(rsi_ble_event_adv_report_t *rsi_ble_event_adv); + +/** + * @typedef void (*rsi_ble_on_connect_t)(rsi_ble_event_conn_status_t *rsi_ble_event_conn); + * @brief Callback function for the BLE connection status from the module. + * + * This callback function is called whenever the BLE connection status is received from the module. + * For BLE 4.1 and lower versions, this callback will be called. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] rsi_ble_event_conn contains the BLE connection status. Please refer rsi_ble_event_conn_status_s for more info. + * @return The following values are returned: + * void + */ +typedef void (*rsi_ble_on_connect_t)(rsi_ble_event_conn_status_t *rsi_ble_event_conn); + +/** + * @typedef void (*rsi_ble_on_enhance_connect_t)(rsi_ble_event_enhance_conn_status_t *rsi_ble_event_enhance_conn); + * @brief Callback function for the BLE connection status from the module. + * + * This callback function is called whenever the BLE connection status is received from the module. + * For BLE 4.2 and above versions, this callback will be called. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] rsi_ble_event_enhance_conn contains the BLE connection status. Please refer rsi_ble_event_enhance_conn_status_s for more info. + * @return The following values are returned: + * void + */ +typedef void (*rsi_ble_on_enhance_connect_t)(rsi_ble_event_enhance_conn_status_t *rsi_ble_event_enhance_conn); + +/** + * @typedef void (*rsi_ble_on_disconnect_t)(rsi_ble_event_disconnect_t *rsi_ble_event_disconnect, uint16_t reason); + * @brief Callback function for the disconnect status event from the module. + * + * This callback function is called whenever the disconnect status event is received from the module. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] rsi_ble_event_disconnect contains the disconnect status. Please refer rsi_ble_event_disconnect_s for more information. + * @param[out] reason contains reason for failure. + * @note Few reason for failure are given below + * 0x4E13 Remote user terminated connection + * 0x4E14 Remote device terminated connection due to low resources + * 0x4E15 Remote device terminated connection due to power off + * 0x4E3D Connection terminated due to MIC failure + * 0x4E3E Connection Failed to be Established + * 0x4E60 Invalid Handle Range + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_disconnect_t)(rsi_ble_event_disconnect_t *rsi_ble_event_disconnect, uint16_t reason); + +/** + * @typedef void (*rsi_ble_on_le_ping_payload_timeout_t)(rsi_ble_event_le_ping_time_expired_t *rsi_ble_event_timeout_expired); + * @brief Callback function for the LE ping time expired event from the module. + * + * This callback function is called whenever the LE ping time expired event is received from the module. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] rsi_ble_event_timeout_expired contains the disconnect status. See rsi_ble_event_le_ping_time_expired_s for more information. + * @return The following values are returned: + * void + */ +typedef void (*rsi_ble_on_le_ping_payload_timeout_t)( + rsi_ble_event_le_ping_time_expired_t *rsi_ble_event_timeout_expired); + +/** + * @typedef void (*rsi_ble_on_le_ltk_req_event_t)(rsi_bt_event_le_ltk_request_t *rsi_ble_event_le_ltk_request); + * @brief Callback function for the LE LTK request event from the module. + * + * This callback function is called whenever the LE LTK request event is received from the module. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] rsi_ble_event_le_ltk_request contains the LTK request info. See rsi_bt_event_le_ltk_request_s for more information. + * @return The following values are returned: + * void + */ +typedef void (*rsi_ble_on_le_ltk_req_event_t)(rsi_bt_event_le_ltk_request_t *rsi_ble_event_le_ltk_request); + +/** + * @typedef void (*rsi_ble_on_le_security_keys_t)(rsi_bt_event_le_security_keys_t *rsi_ble_event_le_security_keys); + * @brief Callback function for the LE security keys event from the module. + * + * This callback function is called whenever the LE security keys event is received from the module. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] rsi_ble_event_le_security_keys contains security keys. See rsi_bt_event_le_security_keys_s for more information. + * @return The following values are returned: + * void + */ +typedef void (*rsi_ble_on_le_security_keys_t)(rsi_bt_event_le_security_keys_t *rsi_ble_event_le_security_keys); +/** @} */ + +/****************************************************** + * * BLE SMP EVENT Callbacks Declarations + * ******************************************************/ +/** @addtogroup BT-LOW-ENERGY8 +* @{ +*/ +/** + * @typedef void (*rsi_ble_on_smp_request_t)(rsi_bt_event_smp_req_t *remote_dev_address); + * @brief Callback function for SMP request in central mode from the remote device. + * + * This callback function is called whenever an SMP request is received in central mode from the remote device. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] remote_dev_address contains the smp requested device address. See rsi_bt_event_smp_req_s for more information. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_smp_request_t)(rsi_bt_event_smp_req_t *remote_dev_address); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_smp_response_t)(rsi_bt_event_smp_resp_t *remote_dev_address); + * @brief Callback function for SMP request in peripheral mode from the remote device. + * + * This callback function is called whenever an SMP request is received in peripheral mode from the remote device. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] remote_dev_address contains the smp resp information. See rsi_bt_event_smp_resp_s for more information. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_smp_response_t)(rsi_bt_event_smp_resp_t *remote_dev_address); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_smp_passkey_t)(rsi_bt_event_smp_passkey_t *remote_dev_address); + * @brief Callback function for SMP passkey event from the module. + * + * This callback function is called whenever an SMP passkey event is received from the module. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] remote_dev_address contains the remote device address. See rsi_bt_event_smp_passkey_s for more information. + * @return The following values are returned: + * void + * + * + */ +typedef void (*rsi_ble_on_smp_passkey_t)(rsi_bt_event_smp_passkey_t *remote_dev_address); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_smp_passkey_display_t)(rsi_bt_event_smp_passkey_display_t *smp_passkey_display); + * @brief Callback function for SMP passkey display event from the module. + * + * This callback function is called whenever an SMP passkey display event is received from the module. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] smp_passkey_display contains the smp passkey display information. See rsi_bt_event_smp_passkey_display_s for more information. + * @return The following values are returned: + * void + * + + */ +typedef void (*rsi_ble_on_smp_passkey_display_t)(rsi_bt_event_smp_passkey_display_t *smp_passkey_display); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_smp_failed_t)(uint16_t resp_status, rsi_bt_event_smp_failed_t *remote_dev_address); + * @brief Callback function for SMP failed event from the module. + * + * This callback function will be called if the smp process is failed with remote device. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] resp_status contains the response status (Success or Error code) + * @note Error codes for SMP FAILED are given below: + * 0x4B01 SMP Passkey entry failed + * 0x4B02 SMP OOB not available + * 0x4B03 SMP Authentication Requirements + * 0x4B04 SMP confirm value failed + * 0x4B05 SMP Pairing not supported + * 0x4B06 SMP Encryption key size insufficient + * 0x4B07 SMP command not supported + * 0x4B08 SMP Unspecified Reason + * 0x4B09 SMP repeated attempts + * 0x4B0C SMP Numeric Comparison Failed + * 0x4B0B DHKEY Check Failed + * @param[out] remote_dev_address contains the remote device address. See rsi_bt_event_smp_failed_s for more information. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_smp_failed_t)(uint16_t resp_status, rsi_bt_event_smp_failed_t *remote_dev_address); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_sc_method_t)(rsi_bt_event_sc_method_t *scmethod); + * @brief Callback function for a security method event from the module. + * + * This callback function will be called if the SC method is done with remote device. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] scmethod contains Security Method 1 means Just works or 2 means Passkey. See rsi_bt_event_sc_method_s for more information. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_sc_method_t)(rsi_bt_event_sc_method_t *scmethod); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_encrypt_started_t)(uint16_t resp_status, rsi_bt_event_encryption_enabled_t *enc_enabled); + * @brief Callback function an encrypted event from the module. + * + * This callback function will be called if the encryption process is started with remote device. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] resp_status contains the response status (Success or Error code) + * @param[out] enc_enabled contains encryption information. See rsi_bt_event_encryption_enabled_s for more information. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_encrypt_started_t)(uint16_t resp_status, rsi_bt_event_encryption_enabled_t *enc_enabled); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_sc_passkey_t)(rsi_bt_event_sc_passkey_t *sc_passkey); +* @brief Callback function for a BLE Secure Connection passkey event from the module. + * + * This callback function is called whenever a BLE Secure Connection passkey event is received from the module. + * It has to be registered using the `rsi_ble_smp_register_callbacks` API. + * @param[out] sc_passkey contains LE SC Passkey information. See rsi_bt_event_encryption_enabled_s for more information. + * @return The following values are returned: + * void + * + * + * + */ +typedef void (*rsi_ble_on_sc_passkey_t)(rsi_bt_event_sc_passkey_t *sc_passkey); + +/** + * @typedef void (*rsi_ble_on_phy_update_complete_t)(rsi_ble_event_phy_update_t *rsi_ble_event_phy_update_complete); + * @brief Callback function for receiving the PHY update complete event. + * + * This callback function is called whenever the PHY update complete event is received. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] rsi_ble_event_phy_update_complete contains the controller support PHY information. See rsi_ble_event_phy_update_s for more information. + * @return The following values are returned: + * void + * + * + * + */ +typedef void (*rsi_ble_on_phy_update_complete_t)(rsi_ble_event_phy_update_t *rsi_ble_event_phy_update_complete); + +/** + * @typedef void (*rsi_ble_on_conn_update_complete_t)(rsi_ble_event_conn_update_t *rsi_ble_event_conn_update_complete, + uint16_t resp_status); + * @brief Callback function for a connection update complete event from the module. + * + * This callback function is called whenever the connection update complete event is received. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] rsi_ble_event_conn_update_complete contains the controller support conn information. See rsi_ble_event_conn_update_s for more information. + * @param[out] resp_status contains the response status (Success or Error code) + * @return The following values are returned: + * void + * + * + * + */ +typedef void (*rsi_ble_on_conn_update_complete_t)(rsi_ble_event_conn_update_t *rsi_ble_event_conn_update_complete, + uint16_t resp_status); +/** + * @typedef void (*rsi_ble_on_remote_conn_params_request_t)( + * rsi_ble_event_remote_conn_param_req_t *rsi_ble_event_remote_conn_param, + * uint16_t resp_status); + * @brief Callback function for remote connection parameters request. + * + * This callback function is called whenever a remote connection parameters request is received. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] resp_status contains the response status (Success or Error code) + * @param[out] rsi_ble_event_remote_conn_param contains the remote device connection parameters. See rsi_ble_event_remote_conn_param_req_s for more information. + * @return The following values are returned: + * void + * + * + */ +typedef void (*rsi_ble_on_remote_conn_params_request_t)( + rsi_ble_event_remote_conn_param_req_t *rsi_ble_event_remote_conn_param, + uint16_t resp_status); + +/** + * @typedef void (*rsi_ble_on_remote_features_t)(rsi_ble_event_remote_features_t *rsi_ble_event_remote_features); + * @brief Callback function for peer device supported features. + * This callback function will be called when conn update complete event is received. + * it has to be registered using rsi_ble_gap_extended_register_callbacks API. + * @param[out] rsi_ble_event_remote_features contains the remote device supported features. See rsi_ble_event_remote_features_s for more information. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_remote_features_t)(rsi_ble_event_remote_features_t *rsi_ble_event_remote_features); + +/** + * @typedef void (*rsi_ble_on_le_more_data_req_t)(rsi_ble_event_le_dev_buf_ind_t *rsi_ble_more_data_evt); + * @brief Callback function for the LE more data event. + * + * This callback function is called whenever an LE more data event is received. + * It has to be registered using the `rsi_ble_gap_extended_register_callbacks` API. + * @param[out] rsi_ble_more_data_evt contains the LE Device Buffer Indication information. See rsi_ble_event_le_dev_buf_ind_s for more infomation. + * @return The following values are returned: + * void + * + * + * + */ +typedef void (*rsi_ble_on_le_more_data_req_t)(rsi_ble_event_le_dev_buf_ind_t *rsi_ble_more_data_evt); + +/*==============================================*/ +/** + * @typedef void (*rsi_ble_on_data_length_update_t)(rsi_ble_event_data_length_update_t *remote_dev_address); + * @brief Callback function for the data length update complete event. + * + * This callback function is called whenever the data length update complete event is received. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[out] remote_dev_address contains the controller support TX and RX length information. See rsi_ble_event_data_length_update_s for more information. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_data_length_update_t)(rsi_ble_event_data_length_update_t *remote_dev_address); + +/** + * @typedef void (*rsi_ble_on_directed_adv_report_event_t)(rsi_ble_event_directedadv_report_t *rsi_ble_event_directed); + * @brief Callback function for a directed advertise report event from the module. + * + * This callback function is called whenever a directed advertise report event is received from the module. + * It has to be registered using the `rsi_ble_gap_register_callbacks` API. + * @param[in] rsi_ble_event_directed contains the advertise report information + * + */ +typedef void (*rsi_ble_on_directed_adv_report_event_t)(rsi_ble_event_directedadv_report_t *rsi_ble_event_directed); +/** @} */ + +/** @addtogroup BT-LOW-ENERGY7 +* @{ +*/ +/*==============================================*/ +/** + * @brief Register GAP callbacks. + * @param[in] ble_on_adv_report_event - Callback function for Advertise events + * @param[in] ble_on_conn_status_event - Callback function for Connect events + * @param[in] ble_on_disconnect_event - Callback function for Disconnect events + * @param[in] timeout_expired_event - Callback function for LE ping timeout events + * @param[in] ble_on_phy_update_complete_event - Callback function for PHY update complete events + * @param[in] ble_on_data_length_update_complete_event - Callback function for data length update events + * @param[in] ble_on_enhance_conn_status_event - Callback function for enhanced connection status events + * @param[in] ble_on_directed_adv_report_event - Callback function for directed advertising report events + * @param[in] ble_on_conn_update_complete_event - Callback function for conn update complete events + * @param[in] ble_on_remote_conn_params_request_event - Callback function to remote conn params request events + * + */ +void rsi_ble_gap_register_callbacks(rsi_ble_on_adv_report_event_t ble_on_adv_report_event, + rsi_ble_on_connect_t ble_on_conn_status_event, + rsi_ble_on_disconnect_t ble_on_disconnect_event, + rsi_ble_on_le_ping_payload_timeout_t timeout_expired_event, + rsi_ble_on_phy_update_complete_t ble_on_phy_update_complete_event, + rsi_ble_on_data_length_update_t ble_on_data_length_update_complete_event, + rsi_ble_on_enhance_connect_t ble_on_enhance_conn_status_event, + rsi_ble_on_directed_adv_report_event_t ble_on_directed_adv_report_event, + rsi_ble_on_conn_update_complete_t ble_on_conn_update_complete_event, + rsi_ble_on_remote_conn_params_request_t ble_on_remote_conn_params_request_event); + +/*==============================================*/ +/** + * @brief Register GAP Extended responses/events callbacks. + * @pre Pre-conditions: + * Call [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) before calling this API. + * @param[in] ble_on_remote_features_event - Call back function for Remote feature request + * @param[in] ble_on_le_more_data_req_event - Call back function for LE More data request + * @note For more information about each callback, see the GAP Extended callbacks description section. + * + */ + +void rsi_ble_gap_extended_register_callbacks(rsi_ble_on_remote_features_t ble_on_remote_features_event, + rsi_ble_on_le_more_data_req_t ble_on_le_more_data_req_event); + +/** + * @fn uint32_t rsi_ble_enhanced_gap_extended_register_callbacks(uint16_t callback_id, + * void (*callback_handler_ptr)(uint16_t status, + * uint8_t *buffer)); + * @brief Registers a callback function for the Enhanced GAP Extended feature in the RSI BLE module. + * + * This function allows you to register a callback function to handle events related to the Enhanced GAP Extended feature. + * The callback function will be called when an event occurs, providing the status and a buffer containing additional data. + * + * @param callback_id The ID of the callback to register. + * @param callback_handler_ptr A pointer to the callback function that will handle the events. + * + * @return The status of the registration process. Possible values are defined by the uint16_t data type. + * + * @note Ensure that the callback function is implemented to handle the specific events you are interested in. + * The callback function should match the signature specified in the function parameters. + * This function should be called during the initialization phase of your application to ensure that + * the callbacks are registered before any events occur. + */ +uint32_t rsi_ble_enhanced_gap_extended_register_callbacks(uint16_t callback_id, + void (*callback_handler_ptr)(uint16_t status, + uint8_t *buffer)); + +/*==============================================*/ +/** + * + */ +/** + * @fn int32_t rsi_ble_adv_ext_events_register_callbacks(uint16_t callback_id, + * void (*callback_handler_ptr)(uint16_t status, uint8_t *buffer)); + * @brief Registers callback functions for extended advertising events in the BLE module. + * + * This function allows the application to register callback functions to handle extended advertising events + * in the BLE module. The callback functions will be invoked when an extended advertising event occurs. + * + * @param callback_id The ID of the callback function to register. + * @param callback_handler_ptr A pointer to the callback function that will handle the extended advertising events. + * The callback function should have the following signature: + * void callback_handler(uint16_t status, uint8_t *buffer) + * - status: The status of the extended advertising event. + * - buffer: A pointer to the buffer containing the extended advertising event data. + * + * @return Returns 0 on success, or a negative error code on failure. + */ +int32_t rsi_ble_adv_ext_events_register_callbacks(uint16_t callback_id, + void (*callback_handler_ptr)(uint16_t status, uint8_t *buffer)); + +/*==============================================*/ +/** + * @brief Register the SMP callbacks + * @param[in] ble_on_smp_request_event - smp request callback + * @param[in] ble_on_smp_response_event - smp response callback + * @param[in] ble_on_smp_passkey_event - smp passkey callback + * @param[in] ble_on_smp_fail_event - smp failed callback + * @param[in] rsi_ble_on_encrypt_started_event - encryption enabled callback + * @param[in] ble_on_smp_passkey_display_event - smp passkey display callback + * @param[in] ble_sc_passkey_event - sc passkey display callback + * @param[in] ble_on_le_ltk_req_event - This is the SMP LTK request callback + * @param[in] ble_on_le_security_keys_event - This is the SMP security keys callback + * @param[in] ble_on_cli_smp_response_event - This is the client smp response callback - + * @param[in] ble_on_sc_method_event - sc method display callback + * + */ +void rsi_ble_smp_register_callbacks(rsi_ble_on_smp_request_t ble_on_smp_request_event, + rsi_ble_on_smp_response_t ble_on_smp_response_event, + rsi_ble_on_smp_passkey_t ble_on_smp_passkey_event, + rsi_ble_on_smp_failed_t ble_on_smp_fail_event, + rsi_ble_on_encrypt_started_t rsi_ble_on_encrypt_started_event, + rsi_ble_on_smp_passkey_display_t ble_on_smp_passkey_display_event, + rsi_ble_on_sc_passkey_t ble_sc_passkey_event, + rsi_ble_on_le_ltk_req_event_t ble_on_le_ltk_req_event, + rsi_ble_on_le_security_keys_t ble_on_le_security_keys_event, + rsi_ble_on_smp_response_t ble_on_cli_smp_response_event, + rsi_ble_on_sc_method_t ble_on_sc_method_event); + +/** @} */ + +/****************************************************** + * * BLE GATT Response Callbacks Declarations + * ******************************************************/ +/** @addtogroup BT-LOW-ENERGY8 +* @{ +*/ +/** + * @typedef void (*rsi_ble_on_gatt_error_resp_t)(uint16_t event_status, rsi_ble_event_error_resp_t *rsi_ble_gatt_error); + * @brief Callback function for a GATT error event from the module. + * + * This callback function is called whenever a GATT error event is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the error response + * Non-Zero Value - Failure + * Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A06 - Request not supported + * 0x4A0A - Attribute not found + * 0x4A05 - Insufficient authentication + * 0x4A08 - Insufficient authorization + * 0x4A0C - Insufficient encryption key size + * 0x4A0F - Insufficient encryption + * 0x4A02 - Read not permitted + * 0x4A03 - Write not permitted + * 0x4A07 - Invalid offset + * 0x4A0B - Attribute not Long + * @param[out] rsi_ble_gatt_error contains the GATT error information. Please refer rsi_ble_event_error_resp_s for more info + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_gatt_error_resp_t)(uint16_t event_status, rsi_ble_event_error_resp_t *rsi_ble_gatt_error); +/** + * @typedef void (*rsi_ble_on_gatt_desc_val_event_t)(uint16_t event_status, + rsi_ble_event_gatt_desc_t *rsi_ble_gatt_desc_val); + * @brief Callback function for an attribute descriptors event from the module. + * + * This callback function is called whenever an attribute descriptors event is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * - 0 - Success + * - Non-Zero Value - Failure + * + * @param[out] rsi_ble_gatt_desc_val contains the profiles list event information. Please refer rsi_ble_event_gatt_desc_s for more info + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_gatt_desc_val_event_t)(uint16_t event_status, + rsi_ble_event_gatt_desc_t *rsi_ble_gatt_desc_val); + +/** + * @typedef void (*rsi_ble_on_event_profiles_list_t)(uint16_t event_status, + rsi_ble_event_profiles_list_t *rsi_ble_event_profiles); + * @brief Callback function for a profiles list response from the module. + * + * This callback function is called whenever a profiles list response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * + * @param[out] rsi_ble_event_profiles contains the profiles list event information. Please refer rsi_ble_event_profiles_list_s for more info + * @return The following values are returned: + * void + * + * + * + */ +typedef void (*rsi_ble_on_event_profiles_list_t)(uint16_t event_status, + rsi_ble_event_profiles_list_t *rsi_ble_event_profiles); + +/** + * @typedef void (*rsi_ble_on_event_profile_by_uuid_t)(uint16_t event_status, + rsi_ble_event_profile_by_uuid_t *rsi_ble_event_profile); + * @brief Callback function for a profile response from the module. + * + * This callback function is called whenever a profile response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * + * @param[out] rsi_ble_event_profile contains the profile response information. Please refer rsi_ble_event_profile_by_uuid_s for more info. + * @return The following values are returned: + * void + * + * + * + */ +typedef void (*rsi_ble_on_event_profile_by_uuid_t)(uint16_t event_status, + rsi_ble_event_profile_by_uuid_t *rsi_ble_event_profile); +/** + * @typedef void (*rsi_ble_on_event_read_by_char_services_t)(uint16_t event_status, + rsi_ble_event_read_by_type1_t *rsi_ble_event_read_type1); + * @brief This callback function will be called if the characteristic services list response is received from the module. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @param[out] rsi_ble_event_read_type1 contains the char services event information. Please refer rsi_ble_event_read_by_type1_s for more info. + * @return The following values are returned: + * void + * + * + */ +typedef void (*rsi_ble_on_event_read_by_char_services_t)(uint16_t event_status, + rsi_ble_event_read_by_type1_t *rsi_ble_event_read_type1); + +/** + * @typedef void (*rsi_ble_on_event_read_by_inc_services_t)(uint16_t event_status, + rsi_ble_event_read_by_type2_t *rsi_ble_event_read_type2); + * @brief Callback function for an include services list response from the module. + * + * This callback function is called whenever an include services list response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @param[out] rsi_ble_event_read_type2 contains the inc services information. Please refer rsi_ble_event_read_by_type2_s for more info. + * @return The following values are returned: + * void + * + * + * + * + */ +typedef void (*rsi_ble_on_event_read_by_inc_services_t)(uint16_t event_status, + rsi_ble_event_read_by_type2_t *rsi_ble_event_read_type2); +/** + * @typedef void (*rsi_ble_on_event_read_att_value_t)(uint16_t event_status, + rsi_ble_event_read_by_type3_t *rsi_ble_event_read_type3); + * @brief Callback function for an attribute value response from the module. + * + * This callback function is called whenever an attribute value response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @param[out] rsi_ble_event_read_type3 contains the char services event information. Please refer rsi_ble_event_read_by_type3_s for more info. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_event_read_att_value_t)(uint16_t event_status, + rsi_ble_event_read_by_type3_t *rsi_ble_event_read_type3); + +/** + * @typedef void (*rsi_ble_on_event_read_resp_t)(uint16_t event_status, rsi_ble_event_att_value_t *rsi_ble_event_att_val); + * @brief Callback function for an attribute value from the module. + * + * This callback function is called whenever an attribute value is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @param[out] rsi_ble_event_att_val contains the profile response information. Please refer rsi_ble_event_att_value_s for more info. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_event_read_resp_t)(uint16_t event_status, rsi_ble_event_att_value_t *rsi_ble_event_att_val); + +/** + * @typedef void (*rsi_ble_on_event_write_resp_t)(uint16_t event_status, rsi_ble_set_att_resp_t *rsi_ble_event_set_att_rsp); + * @brief Callback function for a GATT write response from the module. + * + * This callback function is called whenever a GATT write response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * + * @param[out] rsi_ble_event_set_att_rsp contains the profile response information. Please refer rsi_ble_set_att_resp_t for more info. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_event_write_resp_t)(uint16_t event_status, rsi_ble_set_att_resp_t *rsi_ble_event_set_att_rsp); +/** + * @typedef void (*rsi_ble_on_event_indicate_confirmation_t)(uint16_t event_status, + rsi_ble_set_att_resp_t *rsi_ble_event_set_att_rsp); + * @brief Callback function for indication confirmation event + * + * This callback function is called whenever an indication confirmation response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @param[out] rsi_ble_event_set_att_rsp contains the profile response information. Please refer rsi_ble_set_att_resp_s for more info. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_event_indicate_confirmation_t)(uint16_t event_status, + rsi_ble_set_att_resp_t *rsi_ble_event_set_att_rsp); +/** + * @typedef void (*rsi_ble_on_event_prepare_write_resp_t)(uint16_t event_status, + rsi_ble_prepare_write_resp_t *rsi_ble_event_prepare_write); + * @brief Callback function for a GATT prepare response from the module. + * + * This callback function is called whenever a GATT prepare response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_status contains the response status + * - 0 - Success + * - Non-Zero Value - Failure + * @param[out] rsi_ble_event_prepare_write contains the char services event information. Please refer rsi_ble_prepare_write_resp_s for more info. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_event_prepare_write_resp_t)(uint16_t event_status, + rsi_ble_prepare_write_resp_t *rsi_ble_event_prepare_write); + +/** + * @typedef void (*rsi_ble_on_profiles_list_resp_t)(uint16_t resp_status, + rsi_ble_resp_profiles_list_t *rsi_ble_resp_profiles); + * @brief Callback function for a profiles list response from the module. + * + * This callback function is called whenever a profiles list response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] resp_status contains the response status + * - 0 - Success + * - Non-Zero Value - Failure + * @note Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A0A - Attribute not found + * @param[out] rsi_ble_resp_profiles contains the profiles list response information. Please refer rsi_ble_resp_profiles_list_s for more info. + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_profiles_list_resp_t)(uint16_t resp_status, + rsi_ble_resp_profiles_list_t *rsi_ble_resp_profiles); + +/** + * @typedef void (*rsi_ble_on_profile_resp_t)(uint16_t resp_status, profile_descriptors_t *rsi_ble_resp_profile); + * @brief Callback function for a profile response from the module. + * + * This callback function is called whenever a profile response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] resp_status contains the response status + * - 0 - Success + * - Non-Zero Value - Failure + * @note Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A06 - Request not supported + * 0x4A0A - Attribute not found + * @param[out] rsi_ble_resp_profile contains the profile response information. Please refer profile_descriptors_s for more info + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_profile_resp_t)(uint16_t resp_status, profile_descriptors_t *rsi_ble_resp_profile); + +/** + * @typedef void (*rsi_ble_on_char_services_resp_t)(uint16_t resp_status, + rsi_ble_resp_char_services_t *rsi_ble_resp_char_serv); + * @brief Callback function for a service characteristics response from the module. + * + * This callback function is called whenever a service characteristics response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] resp_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @note Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A06 - Request not supported + * 0x4A0A - Attribute not found + * 0x4A05 - Insufficient authentication + * 0x4A08 - Insufficient authorization + * 0x4A0C - Insufficient encryption key size + * 0x4A0F - Insufficient encryption + * 0x4A02 - Read not permitted + * @param[out] rsi_ble_resp_char_serv contains the service characteristics response information. Please refer rsi_ble_resp_char_services_s for more info + * @return The following values are returned: + * void + */ +typedef void (*rsi_ble_on_char_services_resp_t)(uint16_t resp_status, + rsi_ble_resp_char_services_t *rsi_ble_resp_char_serv); + +/** + * @typedef void (*rsi_ble_on_inc_services_resp_t)(uint16_t resp_status, + rsi_ble_resp_inc_services_t *rsi_ble_resp_inc_serv); + * @brief Callback function for an include service response from the module. + * + * This callback function is called whenever an include service response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] resp_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @note Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A06 - Request not supported + * 0x4A0A - Attribute not found + * 0x4A05 - Insufficient authentication + * 0x4A08 - Insufficient authorization + * 0x4A0C - Insufficient encryption key size + * 0x4A0F - Insufficient encryption + * 0x4A02 - Read not permitted + * @param[out] rsi_ble_resp_inc_serv contains the include services response information. Please refer rsi_ble_resp_inc_services_s for more info + * @return The following values are returned: + * void + * + * + * + */ +typedef void (*rsi_ble_on_inc_services_resp_t)(uint16_t resp_status, + rsi_ble_resp_inc_services_t *rsi_ble_resp_inc_serv); + +/** + * @typedef void (*rsi_ble_on_att_desc_resp_t)(uint16_t resp_status, rsi_ble_resp_att_descs_t *rsi_ble_resp_att_desc); + * @brief Callback function for an attribute descriptors response from the module. + * + * This callback function is called whenever an attribute descriptors response is received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] resp_status contains the response status + * - 0 - Success + * - Non-Zero Value - Failure + * @note Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A0A - Attribute not found + * 0x4A05 - Insufficient authentication + * 0x4A08 - Insufficient authorization + * 0x4A0C - Insufficient encryption key size + * 0x4A0F - Insufficient encryption + * 0x4A02 - Read not permitted + * @param[out] rsi_ble_resp_att_desc contains the attribute descriptors response information. Please refer rsi_ble_resp_att_descs_s for more info + * @return The following values are returned: + * void + * + */ +typedef void (*rsi_ble_on_att_desc_resp_t)(uint16_t resp_status, rsi_ble_resp_att_descs_t *rsi_ble_resp_att_desc); + +/** + * @typedef void (*rsi_ble_on_read_resp_t)(uint16_t resp_status, + uint16_t resp_id, + rsi_ble_resp_att_value_t *rsi_ble_resp_att_val); + * @brief Callback function for receiving an attribute value from the module. + * + * This callback function is called upon receiving an attribute value from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] resp_status contains the response status + * - 0 - Success + * - Non-Zero Value - Failure + * @note Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A0A - Attribute not found + * 0x4A05 - Insufficient authentication + * 0x4A08 - Insufficient authorization + * 0x4A0C - Insufficient encryption key size + * 0x4A0F - Insufficient encryption + * 0x4A02 - Read not permitted + * 0x4A06 - Request not supported + * 0x4A07 - Invalid offset + * 0x4A0B - Attribute not Long + * @param[out] resp_id contains the response id because of which, this callback is called + * response ids: (RSI_BLE_RSP_READ_VAL, RSI_BLE_RSP_READ_BY_UUID, RSI_BLE_RSP_LONG_READ, RSI_BLE_RSP_MULTIPLE_READ) + * @param[out] rsi_ble_resp_att_val contains the attribute value. Please refer rsi_ble_resp_att_value_s for more info + * @return The following values are returned: + * void + * + * + */ +typedef void (*rsi_ble_on_read_resp_t)(uint16_t resp_status, + uint16_t resp_id, + rsi_ble_resp_att_value_t *rsi_ble_resp_att_val); + +/** + * @typedef void (*rsi_ble_on_write_resp_t)(uint16_t resp_status, uint16_t resp_id); + * @brief Callback function for attribute set/prepare/execute action completion. + * + * This callback function is called when an attribute set, prepare, or execute action is completed. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] resp_status contains the response status + * + * - 0 - Success + * - Non-Zero Value - Failure + * @note Attribute protocol error codes + * 0x4A01 - Invalid Handle + * 0x4A0A - Attribute not found + * 0x4A05 - Insufficient authentication + * 0x4A08 - Insufficient authorization + * 0x4A0C - Insufficient encryption key size + * 0x4A0F - Insufficient encryption + * 0x4A03 - Write not permitted + * 0x4A07 - Invalid offset + * 0x4A0D - Invalid attribute value length + * @param[out] resp_id contains the response id because of which, this callback is called + * response ids: (RSI_BLE_RSP_WRITE, RSI_BLE_RSP_WRITE_NO_ACK, RSI_BLE_RSP_LONG_WRITE, RSI_BLE_RSP_EXECUTE_WRITE) + * + */ +typedef void (*rsi_ble_on_write_resp_t)(uint16_t resp_status, uint16_t resp_id); +/** @} */ + +/****************************************************** + * * BLE GATT Event Callbacks Declarations + * ******************************************************/ +/** @addtogroup BT-LOW-ENERGY8 +* @{ +*/ +/** + * @typedef void (*rsi_ble_on_gatt_write_event_t)(uint16_t event_id, rsi_ble_event_write_t *rsi_ble_write); + * @brief Callback function for GATT write, notify, or indicate events from the module. + * + * This callback function is called when GATT write, notify, or indicate events are received from the module. + * It has to be registered using the `rsi_ble_gatt_register_callbacks` API. + * @param[out] event_id contains the gatt_write event id (RSI_BLE_EVENT_GATT_WRITE) + * @param[out] rsi_ble_write contains the GATT event information. Please refer rsi_ble_event_write_s for more info + * + */ +typedef void (*rsi_ble_on_gatt_write_event_t)(uint16_t event_id, rsi_ble_event_write_t *rsi_ble_write); + +/** + * @typedef void (*rsi_ble_on_gatt_prepare_write_event_t)(uint16_t event_id, rsi_ble_event_prepare_write_t *rsi_ble_write); + * @brief The callback function will be called if the GATT prepare events are received. + * This callback has to be registered using rsi_ble_gatt_register_callbacks API. + * @param[out] event_id contains the gatt_prepare_write event id (RSI_BLE_EVENT_PREPARE_WRITE) + * @param[out] rsi_ble_write contains the GATT prepare event information. Please refer rsi_ble_event_prepare_write_s for more info + * + * + */ +typedef void (*rsi_ble_on_gatt_prepare_write_event_t)(uint16_t event_id, rsi_ble_event_prepare_write_t *rsi_ble_write); + +/** + * @typedef void (*rsi_ble_on_execute_write_event_t)(uint16_t event_id, rsi_ble_execute_write_t *rsi_ble_execute_write); + * @brief The callback function will be called if the GATT execute events are received. + * This callback has to be registered using rsi_ble_gatt_register_callbacks API. + * @param[out] event_id contains the gatt_execute_write event id (RSI_BLE_EVENT_EXECUTE_WRITE) + * + * @param[out] rsi_ble_execute_write contains the GATT event information. Please refer rsi_ble_execute_write_s for more info. + * + * + */ +typedef void (*rsi_ble_on_execute_write_event_t)(uint16_t event_id, rsi_ble_execute_write_t *rsi_ble_execute_write); + +/** + * @typedef void (*rsi_ble_on_read_req_event_t)(uint16_t event_id, rsi_ble_read_req_t *rsi_ble_read_req); + * @brief The callback function will be called if the GATT read request events are received. + * This callback has to be registered using rsi_ble_gatt_register_callbacks API. + * @param[out] event_id contains the gatt_read_req_event id (RSI_BLE_EVENT_READ_REQ) + * @param[out] rsi_ble_read_req contains the GATT event information. Please refer rsi_ble_read_req_s for more info. + * + */ +typedef void (*rsi_ble_on_read_req_event_t)(uint16_t event_id, rsi_ble_read_req_t *rsi_ble_read_req); + +/** + * @typedef void (*rsi_ble_on_mtu_event_t)(rsi_ble_event_mtu_t *rsi_ble_event_mtu); + * @brief The callback function will be called if MTU size request is received. + * This callback function will be called when connected to indicate MTU size. + * This callback has to be registered using rsi_ble_gatt_register_callbacks API. + * @param[out] rsi_ble_event_mtu contains the MTU size information. Please refer rsi_ble_event_mtu_s for more info. + * + */ +typedef void (*rsi_ble_on_mtu_event_t)(rsi_ble_event_mtu_t *rsi_ble_event_mtu); + +/** + * @typedef void (*rsi_ble_on_mtu_exchange_info_t)(rsi_ble_event_mtu_exchange_information_t *rsi_ble_event_mtu_exchange_info); + * @brief Callback function to indicate MTU size and who initiated MTU Exchange Request. + * This callback function will be called when connected, this event will contain MTU Exchange Information. + * This callback has to be registered using rsi_ble_gatt_extended_register_callbacks API. + * @param[out] rsi_ble_event_mtu_exchange_info contains the MTU exchange information. Please refer rsi_ble_event_mtu_exchange_information_s for more info. + * + * + */ +typedef void (*rsi_ble_on_mtu_exchange_info_t)( + rsi_ble_event_mtu_exchange_information_t *rsi_ble_event_mtu_exchange_info); + +/** + * @typedef void (*rsi_ble_on_remote_device_info_t)(uint16_t status, rsi_ble_event_remote_device_info_t *resp_buffer); + * @brief Callback function to peer device information.This callback function will be called when conn update complete event is received + * This callback has to be registered using rsi_ble_enhanced_gap_extended_register_callbacks API. + * @param[out] status contains the response status (Success or Error code) + * - 0 - SUCCESS + * - Non-Zero Value - ErrorCodes + * @note Refer Bluetooth Generic Error Codes section up to 0x4FF8 from error-codes. + * @param[out] resp_buffer contains the remote device version information. + * + * + * + */ +typedef void (*rsi_ble_on_remote_device_info_t)(uint16_t status, rsi_ble_event_remote_device_info_t *resp_buffer); +/** + * @file rsi_ble_apis.h + * @brief This file contains the declarations of the BLE API functions. + */ + +/** + * @typedef void (*rsi_ble_on_rcp_resp_rcvd_t)(uint16_t status, rsi_ble_event_rcp_rcvd_info_t *resp_buffer); + * @brief Callback function type for receiving RCP response events. + * @param status The status of the RCP response event. + * @param resp_buffer Pointer to the buffer containing the RCP response information. + * + */ +typedef void (*rsi_ble_on_rcp_resp_rcvd_t)(uint16_t status, rsi_ble_event_rcp_rcvd_info_t *resp_buffer); + +/** @} */ + +/********************************************************************************* + * * BLE L2CAP Credit based flow control(CBFC) Callbacks register function Declarations + * *******************************************************************************/ + +/** + * @typedef void (*rsi_ble_on_cbfc_conn_req_event_t)(rsi_ble_event_cbfc_conn_req_t *rsi_ble_cbfc_conn_req); + * @brief Callback function to indicate L2CAP CBFC connection request.This callback function will be called when connected to indicate connection request + * This callback has to be registered using rsi_ble_l2cap_cbfc_callbacks API. + * @param[in] rsi_ble_cbfc_conn_req contains the connection request information + * + * + * + */ +typedef void (*rsi_ble_on_cbfc_conn_req_event_t)(rsi_ble_event_cbfc_conn_req_t *rsi_ble_cbfc_conn_req); + +/** + * @typedef void (*rsi_ble_on_cbfc_conn_complete_event_t)(rsi_ble_event_cbfc_conn_complete_t *rsi_ble_cbfc_conn_complete, + * uint16_t status); + * @brief Callback function to indicate L2CAP CBFC connection complete status. This callback function will be called when connected to indicate connection complete status. + * This callback has to be registered using rsi_ble_l2cap_cbfc_callbacks API. + * @param[in] status + * @param[in] rsi_ble_cbfc_conn_complete contains the connection completed information + * + * + * + */ +typedef void (*rsi_ble_on_cbfc_conn_complete_event_t)(rsi_ble_event_cbfc_conn_complete_t *rsi_ble_cbfc_conn_complete, + uint16_t status); + +/** + * @typedef void (*rsi_ble_on_cbfc_rx_data_event_t)(rsi_ble_event_cbfc_rx_data_t *rsi_ble_cbfc_rx_data); + * @brief Callback function to indicate L2CAP CBFC RX data event. This callback function will be called when connected to indicate received data. + * This callback has to be registered using rsi_ble_l2cap_cbfc_callbacks API. + * @param[in] rsi_ble_cbfc_rx_data contains the received data information + * + * + * + */ +typedef void (*rsi_ble_on_cbfc_rx_data_event_t)(rsi_ble_event_cbfc_rx_data_t *rsi_ble_cbfc_rx_data); + +/** + * @typedef void (*rsi_ble_on_cbfc_disconn_event_t)(rsi_ble_event_cbfc_disconn_t *rsi_ble_cbfc_disconn); + * @brief Callback function to indicate L2CAP CBFC disconnection event. + * This callback function will be called when connected to indicate disconnect l2cap connection. + * This callback has to be registered using rsi_ble_l2cap_cbfc_callbacks API. + * @param[in] rsi_ble_cbfc_disconn contains the disconnect device information + * + * + * + */ +typedef void (*rsi_ble_on_cbfc_disconn_event_t)(rsi_ble_event_cbfc_disconn_t *rsi_ble_cbfc_disconn); + +/** + * @fn void rsi_ble_l2cap_cbsc_register_callbacks(rsi_ble_on_cbfc_conn_req_event_t ble_on_cbsc_conn_req, + * rsi_ble_on_cbfc_conn_complete_event_t ble_on_cbsc_conn_complete, + * rsi_ble_on_cbfc_rx_data_event_t ble_on_cbsc_rx_data, + * rsi_ble_on_cbfc_disconn_event_t ble_on_cbsc_disconn); + * @brief Register callbacks for BLE L2CAP Credit Based Flow Control (CBFC) events. + * + * This function is used to register callbacks for various CBFC events in BLE L2CAP. + * The registered callbacks will be invoked when the corresponding events occur. + * + * @param ble_on_cbsc_conn_req Callback function to handle CBFC connection request event. + * @param ble_on_cbsc_conn_complete Callback function to handle CBFC connection complete event. + * @param ble_on_cbsc_rx_data Callback function to handle CBFC receive data event. + * @param ble_on_cbsc_disconn Callback function to handle CBFC disconnection event. + */ +void rsi_ble_l2cap_cbsc_register_callbacks(rsi_ble_on_cbfc_conn_req_event_t ble_on_cbsc_conn_req, + rsi_ble_on_cbfc_conn_complete_event_t ble_on_cbsc_conn_complete, + rsi_ble_on_cbfc_rx_data_event_t ble_on_cbsc_rx_data, + rsi_ble_on_cbfc_disconn_event_t ble_on_cbsc_disconn); + +/** + * @typedef void (*chip_ble_buffers_stats_handler_t)(chip_ble_buffers_stats_t *chip_ble_buffers_stats); + * @brief Typedef for the chip_ble_buffers_stats_handler_t function pointer. + * + * This function pointer type is used to define a callback function that handles + * the statistics of the BLE buffers in the chip. + * + * @param chip_ble_buffers_stats Pointer to the chip_ble_buffers_stats_t structure + * that contains the statistics of the BLE buffers. + */ +typedef void (*chip_ble_buffers_stats_handler_t)(chip_ble_buffers_stats_t *chip_ble_buffers_stats); + +/** + * @typedef void (*rsi_ble_ae_report_complete_t)(uint16_t resp_status, rsi_ble_ae_adv_report_t *rsi_ble_event_ae_report); + * @brief Callback function to report the AE Advertisements. + * This callback function will be called when AE adv report event is received. + * This callback has to be registered using rsi_ble_ae_events_register_callbacks API. + * @param[out] rsi_ble_event_ae_report contains the controller support AE Adv packets information + * @param[out] resp_status contains the response status (Success or Error code) + * + * + * + */ +typedef void (*rsi_ble_ae_report_complete_t)(uint16_t resp_status, rsi_ble_ae_adv_report_t *rsi_ble_event_ae_report); + +/** + * @typedef void (*rsi_ble_ae_per_adv_sync_estbl_t)(uint16_t resp_status, + * rsi_ble_per_adv_sync_estbl_t *rsi_ble_event_per_adv_sync_estbl); + * @brief Callback function to report the AE periodic sync established event. + * This callback function will be called when AE periodic sync established event is received. + * This callback has to be registered using rsi_ble_ae_events_register_callbacks API. + * @param[out] rsi_ble_event_per_adv_sync_estbl contains the controller support AE periodic sync established information + * @param[out] resp_status contains the response status (Success or Error code) + * + * + * + */ +typedef void (*rsi_ble_ae_per_adv_sync_estbl_t)(uint16_t resp_status, + rsi_ble_per_adv_sync_estbl_t *rsi_ble_event_per_adv_sync_estbl); + +/** + * @typedef void (*rsi_ble_ae_per_adv_report_t)(uint16_t resp_status, + * rsi_ble_per_adv_report_t *rsi_ble_event_per_adv_report); + * @brief Callback function to report the AE periodic advertisement event + * @param[out] rsi_ble_event_per_adv_report contains the controller support AE periodic advertisement information + * @param[out] resp_status contains the response status (Success or Error code) + * + * This callback function will be called when AE periodic advertisement event is received + * This callback has to be registered using rsi_ble_ae_events_register_callbacks API + */ +typedef void (*rsi_ble_ae_per_adv_report_t)(uint16_t resp_status, + rsi_ble_per_adv_report_t *rsi_ble_event_per_adv_report); + +/** + * @typedef void (*rsi_ble_ae_per_adv_sync_lost_t)(uint16_t resp_status, + * rsi_ble_per_adv_sync_lost_t *rsi_ble_event_per_adv_sync_lost); + * @brief Callback function to report the AE periodic sync lost event + * @param[out] rsi_ble_event_per_adv_sync_lost contains the controller support AE periodic sync lost information + * @param[out] resp_status contains the response status (Success or Error code) + * + * This callback function will be called when AE periodic sync lost event is received + * This callback has to be registered using rsi_ble_ae_events_register_callbacks API + */ +typedef void (*rsi_ble_ae_per_adv_sync_lost_t)(uint16_t resp_status, + rsi_ble_per_adv_sync_lost_t *rsi_ble_event_per_adv_sync_lost); + +/** + * @typedef void (*rsi_ble_ae_scan_timeout_t)(uint16_t resp_status, rsi_ble_scan_timeout_t *rsi_ble_event_scan_timeout); + * @brief Callback function to report the AE scan timeout event + * @param[out] rsi_ble_event_scan_timeout contains the controller support AE scan timeout information + * @param[out] resp_status contains the response status (Success or Error code) + * + * This callback function will be called when AE scan timeout is received + * This callback has to be registered using rsi_ble_ae_events_register_callbacks API + * + */ +typedef void (*rsi_ble_ae_scan_timeout_t)(uint16_t resp_status, rsi_ble_scan_timeout_t *rsi_ble_event_scan_timeout); + +/** + * @typedef void (*rsi_ble_ae_adv_set_terminated_t)(uint16_t resp_status, + * rsi_ble_adv_set_terminated_t *rsi_ble_event_adv_set_terminated); + * @brief Callback function to report the AE advertising set terminated event + * @param[out] rsi_ble_event_adv_set_terminated contains the controller support AE advertising set terminated information + * @param[out] resp_status contains the response status (Success or Error code) + * + * + * This callback function will be called when AE advertising set terminated is received. + * This callback has to be registered using rsi_ble_ae_events_register_callbacks API. + * + */ +typedef void (*rsi_ble_ae_adv_set_terminated_t)(uint16_t resp_status, + rsi_ble_adv_set_terminated_t *rsi_ble_event_adv_set_terminated); + +/** + * @typedef void (*rsi_ble_ae_scan_req_recvd_t)(uint16_t resp_status, + * rsi_ble_scan_req_recvd_t *rsi_ble_event_scan_req_recvd); + * @brief Callback function to report the AE scan request received event + * @param[out] rsi_ble_event_scan_req_recvd contains the controller support AE scan request received information + * @param[out] resp_status contains the response status (Success or Error code) + * + * This callback function will be called when AE scan request received is received + * This callback has to be registered using rsi_ble_ae_events_register_callbacks API + */ +typedef void (*rsi_ble_ae_scan_req_recvd_t)(uint16_t resp_status, + rsi_ble_scan_req_recvd_t *rsi_ble_event_scan_req_recvd); + +/****************************************************** + * * BLE GATT Callbacks register function Declarations + * ******************************************************/ +/** @addtogroup BT-LOW-ENERGY7 +* @{ +*/ +/*==============================================*/ +/** + * @brief Register the GATT callbacks. + * @param[in] ble_on_profiles_list_resp - Callback for rsi_ble_get_profiles command. + * @param[in] ble_on_profile_resp - Callback for rsi_ble_get_profile command. + * @param[in] ble_on_char_services_resp - Callback for rsi_ble_get_char_services command. + * @param[in] ble_on_inc_services_resp - Callback for rsi_ble_get_inc_services command. + * @param[in] ble_on_att_desc_resp - Callback for rsi_ble_get_att_descriptors command. + * @param[in] ble_on_read_resp - Callback for all read requests command. + * @param[in] ble_on_write_resp - Callback for all write commands. + * @param[in] ble_on_gatt_event - Callback for all GATT events. + * @param[in] ble_on_gatt_prepare_write_event - Callback for GATT prepare write events. + * @param[in] ble_on_execute_write_event - Callback for GATT execute write events. + * @param[in] ble_on_read_req_event - Callback for read request events. + * @param[in] ble_on_mtu_event - Callback for MTU events. + * @param[in] ble_on_gatt_error_resp_event - Callback for GATT error events. + * @param[in] ble_on_gatt_desc_val_resp_event - Callback for GATT descriptor value events. + * @param[in] ble_on_profiles_list_event - Callback for profiles list events. + * @param[in] ble_on_profile_by_uuid_event - Callback for profile by UUID events. + * @param[in] ble_on_read_by_char_services_event - Callback for read by characteristic services events. + * @param[in] ble_on_read_by_inc_services_event - Callback for read by included services events. + * @param[in] ble_on_read_att_value_event - Callback for read attribute value events. + * @param[in] ble_on_read_resp_event - Callback for read response events. + * @param[in] ble_on_write_resp_event - Callback for write response events. + * @param[in] ble_on_indicate_confirmation_event - Callback for indication confirmation events. + * @param[in] ble_on_prepare_write_resp_event - Callback for prepare write response events. + * + */ +void rsi_ble_gatt_register_callbacks(rsi_ble_on_profiles_list_resp_t ble_on_profiles_list_resp, + rsi_ble_on_profile_resp_t ble_on_profile_resp, + rsi_ble_on_char_services_resp_t ble_on_char_services_resp, + rsi_ble_on_inc_services_resp_t ble_on_inc_services_resp, + rsi_ble_on_att_desc_resp_t ble_on_att_desc_resp, + rsi_ble_on_read_resp_t ble_on_read_resp, + rsi_ble_on_write_resp_t ble_on_write_resp, + rsi_ble_on_gatt_write_event_t ble_on_gatt_event, + rsi_ble_on_gatt_prepare_write_event_t ble_on_gatt_prepare_write_event, + rsi_ble_on_execute_write_event_t ble_on_execute_write_event, + rsi_ble_on_read_req_event_t ble_on_read_req_event, + rsi_ble_on_mtu_event_t ble_on_mtu_event, + rsi_ble_on_gatt_error_resp_t ble_on_gatt_error_resp_event, + rsi_ble_on_gatt_desc_val_event_t ble_on_gatt_desc_val_resp_event, + rsi_ble_on_event_profiles_list_t ble_on_profiles_list_event, + rsi_ble_on_event_profile_by_uuid_t ble_on_profile_by_uuid_event, + rsi_ble_on_event_read_by_char_services_t ble_on_read_by_char_services_event, + rsi_ble_on_event_read_by_inc_services_t ble_on_read_by_inc_services_event, + rsi_ble_on_event_read_att_value_t ble_on_read_att_value_event, + rsi_ble_on_event_read_resp_t ble_on_read_resp_event, + rsi_ble_on_event_write_resp_t ble_on_write_resp_event, + rsi_ble_on_event_indicate_confirmation_t ble_on_indicate_confirmation_event, + rsi_ble_on_event_prepare_write_resp_t ble_on_prepare_write_resp_event); + +/*==============================================*/ +/** + * @brief Register the GATT Extended responses/events callbacks. + * @param[in] ble_on_mtu_exchange_info_event ble_on_mtu_exchange_info_event - Call back function for MTU Exchange information Event + * + * + */ +void rsi_ble_gatt_extended_register_callbacks(rsi_ble_on_mtu_exchange_info_t ble_on_mtu_exchange_info_event); +/** @} */ +/** @} */ + +#ifdef __cplusplus +} +#endif +#endif \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_common_config.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_common_config.h new file mode 100644 index 000000000..f6697ab32 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_ble_common_config.h @@ -0,0 +1,756 @@ +/******************************************************************************* + * @file rsi_ble_common_config.h + * @brief : This file contains user configurable details to configure the device + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_BLE_COMMON_CONFIG_H +#define RSI_BLE_COMMON_CONFIG_H +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +#ifndef RSI_BLE_SET_RESOLVABLE_PRIV_ADDR_TOUT +#define RSI_BLE_SET_RESOLVABLE_PRIV_ADDR_TOUT 120 ///< BLE Resolvable Private Address timeout value (in seconds) +#endif +#ifndef NO_OF_ADV_REPORTS +#define NO_OF_ADV_REPORTS 10 ///< Maximum number of advertise reports to hold. +#endif +#ifndef BLE_CP_BUFF_SIZE_512 +#define BLE_CP_BUFF_SIZE_512 0 ///< Enabled for BLE PER Test. +#endif +/*=======================================================================*/ +// attribute properties +/*=======================================================================*/ +#ifndef RSI_BLE_ATT_PROPERTY_READ +#define RSI_BLE_ATT_PROPERTY_READ 0x02 ///< Attribute property for read operation in BLE. +#endif +#ifndef RSI_BLE_ATT_PROPERTY_WRITE_NO_RESPONSE +#define RSI_BLE_ATT_PROPERTY_WRITE_NO_RESPONSE 0x04 ///< Attribute property allows writing without requiring a response. +#endif +#ifndef RSI_BLE_ATT_PROPERTY_WRITE +#define RSI_BLE_ATT_PROPERTY_WRITE 0x08 ///< Attribute property is for write operations. +#endif +#ifndef RSI_BLE_ATT_PROPERTY_NOTIFY +#define RSI_BLE_ATT_PROPERTY_NOTIFY 0x10 ///< Enables the BLE Attribute Property for Notification. +#endif +#ifndef RSI_BLE_ATT_PROPERTY_INDICATE +#define RSI_BLE_ATT_PROPERTY_INDICATE 0x20 ///< Attribute property for indication. +#endif +#ifndef BT_GLOBAL_BUFF_LEN +#define BT_GLOBAL_BUFF_LEN 10000 ///< Memory length for driver. +#endif +#ifndef BLE_PERIPHERAL_MODE_ENABLE +#define BLE_PERIPHERAL_MODE_ENABLE 1 ///< Enabling peripheral mode. +#endif +/*=======================================================================*/ +// BLE Attribute Security Define +/*=======================================================================*/ +#define ATT_REC_MAINTAIN_IN_HOST BIT(0) ///< Att record maintained by the stack +#define SEC_MODE_1_LEVEL_1 BIT(1) ///< NO Auth & No Enc +#define SEC_MODE_1_LEVEL_2 BIT(2) ///< UnAUTH with Enc +#define SEC_MODE_1_LEVEL_3 BIT(3) ///< AUTH with Enc +#define SEC_MODE_1_LEVEL_4 BIT(4) ///< AUTH LE_SC Pairing with Enc +#define ON_BR_EDR_LINK_ONLY BIT(5) ///< BR/EDR link-only mode +#define ON_LE_LINK_ONLY BIT(6) ///< LE link-only mode +/*=======================================================================*/ +// Max Tx data length and Tx timeout values +/*=======================================================================*/ +#ifndef TX_LEN +#define TX_LEN 0x001e ///< The transmission length. +#endif +#ifndef TX_TIME +#define TX_TIME 0x01f4 ///< Transmission time configuration. +#endif +#ifndef RSI_BLE_SMP_IO_CAPABILITY +#define RSI_BLE_SMP_IO_CAPABILITY 0x00 ///< The I/O capability for BLE Security Manager Protocol (SMP). +#endif +#ifndef RSI_BLE_APP_SMP_PASSKEY +#define RSI_BLE_APP_SMP_PASSKEY 0 ///< The default Security Manager Protocol (SMP) passkey for BLE applications. +#endif +/*=======================================================================*/ +// PHY rate selections +/*=======================================================================*/ +#ifndef TX_PHY_RATE +#define TX_PHY_RATE 0x02 ///< The PHY rate for transmission. +#endif +#ifndef RX_PHY_RATE +#define RX_PHY_RATE 0x02 ///< The PHY rate for RX (Receiver). +#endif +#ifndef CODDED_PHY_RATE +#define CODDED_PHY_RATE 0x00 ///< Specifies the PHY rate for coded PHY. +#endif + +/*=======================================================================*/ +// privacy mode 0-Network privacy mode 1-Device privacy mode +/*=======================================================================*/ +#ifndef RSI_BLE_NETWORK_PRIVACY_MODE +#define RSI_BLE_NETWORK_PRIVACY_MODE 0 ///< This macro defines the value `0` for enabling Network Privacy Mode. +#endif +#ifndef RSI_BLE_DEVICE_PRIVACY_MODE +#define RSI_BLE_DEVICE_PRIVACY_MODE 1 ///< This macro defines the value `1` for enabling Device Privacy Mode. +#endif +#ifndef RSI_BLE_PRIVACY_MODE +#define RSI_BLE_PRIVACY_MODE RSI_BLE_DEVICE_PRIVACY_MODE ///< The BLE privacy mode is set to the device privacy mode. +#endif + +#ifndef RSI_BLE_RESOLVING_LIST_SIZE +#define RSI_BLE_RESOLVING_LIST_SIZE 5 ///< Resovable list size +#endif +#ifndef RSI_BLE_MAX_DATA_LEN +#define RSI_BLE_MAX_DATA_LEN 20 ///< max data length +#endif +/*=======================================================================*/ +// process type 1-add device to resolvlist, 2-remove device from resolvlist, 3-clear the resolvlist +/*=======================================================================*/ +#ifndef RSI_BLE_ADD_TO_RESOLVE_LIST +#define RSI_BLE_ADD_TO_RESOLVE_LIST 1 ///< Enable or disable adding devices to the BLE resolve list. +#endif +#ifndef RSI_BLE_REMOVE_FROM_RESOLVE_LIST +#define RSI_BLE_REMOVE_FROM_RESOLVE_LIST 2 ///< Defines the value used to remove a device from the BLE resolve list. +#endif +#ifndef RSI_BLE_CLEAR_RESOLVE_LIST +#define RSI_BLE_CLEAR_RESOLVE_LIST 3 ///< Clears the resolving list in the BLE stack. +#endif +/*=======================================================================*/ +// BLE attribute service types uuid values +/*=======================================================================*/ +#ifndef RSI_BLE_BATTERY_SERVICE_UUID +#define RSI_BLE_BATTERY_SERVICE_UUID 0x180F ///< UUID for the Battery Service. +#endif +#ifndef RSI_BLE_CHAR_SERV_UUID +#define RSI_BLE_CHAR_SERV_UUID 0x2803 ///< UUID for BLE Characteristic Service. +#endif +#ifndef RSI_BLE_CLIENT_CHAR_UUID +#define RSI_BLE_CLIENT_CHAR_UUID 0x2902 ///< UUID for the BLE Client Characteristic Configuration Descriptor. +#endif +#ifndef RSI_BLE_CHAR_PRESENTATION_FORMATE_UUID +#define RSI_BLE_CHAR_PRESENTATION_FORMATE_UUID \ + 0x2904 ///< UUID for the BLE Characteristic Presentation Format Descriptor. +#endif +/*=======================================================================*/ +// BLE characteristic service and attribute uuid +/*=======================================================================*/ +#ifndef RSI_BLE_NEW_SERVICE_UUID +#define RSI_BLE_NEW_SERVICE_UUID 0xAABB ///< Defines the UUID for a new BLE service. +#endif +#ifndef RSI_BLE_NEW_SERVICE_UUID2 +#define RSI_BLE_NEW_SERVICE_UUID2 0xCCDD ///< Defines the UUID for a new BLE service. +#endif +#ifndef RSI_BLE_ATTRIBUTE_1_UUID +#define RSI_BLE_ATTRIBUTE_1_UUID 0x1AA1 ///< UUID for BLE Attribute 1. +#endif +#ifndef RSI_BLE_ATTRIBUTE_2_UUID +#define RSI_BLE_ATTRIBUTE_2_UUID 0x1BB1 ///< Defines the UUID for the second BLE attribute. +#endif +#ifndef RSI_BLE_ATTRIBUTE_3_UUID +#define RSI_BLE_ATTRIBUTE_3_UUID 0x1CC1 ///< UUID for the third BLE attribute. +#endif +#ifndef RSI_BLE_ATTRIBUTE_4_UUID +#define RSI_BLE_ATTRIBUTE_4_UUID 0x1DD1 ///< UUID for BLE Attribute 4. +#endif + +#ifndef RSI_BLE_SET_RAND_ADDR +#define RSI_BLE_SET_RAND_ADDR "00:23:A7:12:34:56" ///< Defines the random Bluetooth address for BLE configuration. +#endif + +#ifndef CLEAR_ACCEPTLIST +#define CLEAR_ACCEPTLIST 0x00 ///< Clears the accept list. +#endif +#ifndef ADD_DEVICE_TO_ACCEPTLIST +#define ADD_DEVICE_TO_ACCEPTLIST 0x01 ///< Adds a device to the accept list. +#endif +#ifndef DELETE_DEVICE_FROM_ACCEPTLIST +#define DELETE_DEVICE_FROM_ACCEPTLIST 0x02 ///< Operation code for deleting a device from the accept list. +#endif + +#ifndef ALL_PHYS +#define ALL_PHYS 0x00 ///< Specify that all physical layer settings should be applied. +#endif + +#ifndef RSI_BLE_DEV_ADDR_RESOLUTION_ENABLE +#define RSI_BLE_DEV_ADDR_RESOLUTION_ENABLE 0 ///< Enable or disable BLE device address resolution. +#endif + +#ifndef RSI_OPERMODE_WLAN_BLE +#define RSI_OPERMODE_WLAN_BLE 13 ///< The operation mode for WLAN and BLE coexistence. +#endif + +#ifndef RSI_BLE_MAX_NBR_ATT_REC +#define RSI_BLE_MAX_NBR_ATT_REC 80 ///< Maximum number of Attribute Records. +#endif +#ifndef RSI_BLE_MAX_NBR_ATT_SERV +#define RSI_BLE_MAX_NBR_ATT_SERV 10 ///< Defines the maximum number of Attribute Services supported by the BLE stack. +#endif + +#ifndef RSI_BLE_MAX_NBR_PERIPHERALS +#define RSI_BLE_MAX_NBR_PERIPHERALS 3 ///< Defines the maximum number of BLE peripheral devices that can be connected. +#endif +#ifndef RSI_BLE_MAX_NBR_CENTRALS +#define RSI_BLE_MAX_NBR_CENTRALS \ + 2 ///< Defines the maximum number of BLE central devices that can be connected simultaneously. +#endif +#ifndef RSI_BLE_NUM_CONN_EVENTS +#define RSI_BLE_NUM_CONN_EVENTS 20 ///< Defines the number of BLE connection events. +#endif + +/* Number of BLE GATT RECORD SIZE IN (n*16 BYTES), eg:(0x40*16)=1024 bytes */ +#ifndef RSI_BLE_NUM_REC_BYTES +#define RSI_BLE_NUM_REC_BYTES 0x40 ///< Defines the number of bytes to be received in a BLE operation. +#endif +/*=======================================================================*/ +// Advertising command parameters +/*=======================================================================*/ +#ifndef RSI_BLE_ADV_DIR_ADDR +#define RSI_BLE_ADV_DIR_ADDR "00:15:83:6A:64:17" ///< Defines the Bluetooth Low Energy (BLE) advertising direct address. +#endif + +#ifndef RSI_BLE_ADV_CHANNEL_MAP +#define RSI_BLE_ADV_CHANNEL_MAP \ + 0x07 ///< Defines the advertising channel map for BLE. Setting all bits to 1 (0x07) enables advertising on all three channels. +#endif +///< BLE Tx Power Index On Air +#ifndef RSI_BLE_PWR_INX +#ifdef SLI_SI915 +#define RSI_BLE_PWR_INX 75 ///< HP chain for Si915 +#else +#define RSI_BLE_PWR_INX 30 ///< LP chain +#endif +#endif + +#ifndef RSI_BLE_PWR_INX_DBM +#define RSI_BLE_PWR_INX_DBM 0 ///< BLE Tx Power Index On Air per Gap role +#endif + +#ifndef RSI_BLE_START_ADV +#define RSI_BLE_START_ADV 0x01 ///< Start the advertising process. +#endif +#ifndef RSI_BLE_STOP_ADV +#define RSI_BLE_STOP_ADV 0x00 ///< Stop the advertising process. +#endif +/*=======================================================================*/ +// Advertise type +/*=======================================================================*/ +/** + * @def UNDIR_CONN + * @brief Advertising will be visible(discoverable) to all the devices. + * Scanning/Connection is also accepted from all devices + */ +#ifndef UNDIR_CONN +#define UNDIR_CONN 0x80 +#endif +/** + * @def DIR_CONN + * @brief Advertising will be visible(discoverable) to the particular device + * mentioned in RSI_BLE_ADV_DIR_ADDR only. + * Scanning and Connection will be accepted from that device only. + */ +#ifndef DIR_CONN +#define DIR_CONN 0x81 +#endif +/** + * @def UNDIR_SCAN + * @brief Advertising will be visible(discoverable) to all the devices. + * Scanning will be accepted from all the devices. + * Connection will be not be accepted from any device. + */ +#ifndef UNDIR_SCAN +#define UNDIR_SCAN 0x82 +#endif +/** + * @def UNDIR_NON_CONN + * @brief Advertising will be visible(discoverable) to all the devices. + * Scanning and Connection will not be accepted from any device + */ +#ifndef UNDIR_NON_CONN +#define UNDIR_NON_CONN 0x83 +#endif +/** + * @def DIR_CONN_LOW_DUTY_CYCLE + * @brief Advertising will be visible(discoverable) to the particular device + * mentioned in RSI_BLE_ADV_DIR_ADDR only. + * Scanning and Connection will be accepted from that device only. + */ +#ifndef DIR_CONN_LOW_DUTY_CYCLE +#define DIR_CONN_LOW_DUTY_CYCLE 0x84 +#endif +/** + * @def RSI_BLE_ADV_TYPE + * @brief Defines the type of BLE advertisement. + * + * This macro sets the type of Bluetooth Low Energy (BLE) advertisement. + * The value `UNDIR_CONN` indicates that the advertisement type is + * undirected connectable. + * + * Possible values: + * - `UNDIR_CONN`: Undirected connectable advertisement. + * - Other values may be defined based on the BLE stack being used. + * + * Example usage: + * @code + * #define RSI_BLE_ADV_TYPE UNDIR_CONN + * @endcode + */ +#ifndef RSI_BLE_ADV_TYPE +#define RSI_BLE_ADV_TYPE UNDIR_CONN +#endif +/*=======================================================================*/ +// Advertising flags +/*=======================================================================*/ +/** + * @def LE_LIMITED_DISCOVERABLE + * @brief Limited Discoverable mode + * + * The Limited Discoverable mode is used to indicate that the device is discoverable for a limited period of time. + * This mode is typically used for devices that are not always discoverable and only become discoverable for a short duration. + * + */ +#ifndef LE_LIMITED_DISCOVERABLE +#define LE_LIMITED_DISCOVERABLE 0x01 +#endif +/** + * @def LE_GENERAL_DISCOVERABLE + * @brief LE General Discoverable Mode + * + * This macro defines the value for the LE General Discoverable mode. + * It is used to set the device in a mode where it can be discovered + * by other Bluetooth Low Energy (BLE) devices. + * + */ +#ifndef LE_GENERAL_DISCOVERABLE +#define LE_GENERAL_DISCOVERABLE 0x02 +#endif +/** + * @def LE_BR_EDR_NOT_SUPPORTED + * @brief BR/EDR (Basic Rate/Enhanced Data Rate) is not supported. + * + * The value `0x04` is used to signify that the device does not support BR/EDR + * + * @note + * Ensure that this macro is used in contexts where the absence of BR/EDR support is relevant. + */ +#ifndef LE_BR_EDR_NOT_SUPPORTED +#define LE_BR_EDR_NOT_SUPPORTED 0x04 +#endif +/*=======================================================================*/ +// Advertise filters +/*=======================================================================*/ +/** + * @def ALLOW_SCAN_REQ_ANY_CONN_REQ_ANY + * @brief Allow any scan request and any connection request. + * + * Allow any device to send a scan request and any device to send a connection request. + * + * @note This setting might be used in scenarios where the device needs to be + * discoverable and connectable by any other BLE device without restrictions. + */ +#ifndef ALLOW_SCAN_REQ_ANY_CONN_REQ_ANY +#define ALLOW_SCAN_REQ_ANY_CONN_REQ_ANY 0x00 +#endif +/** @def ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ANY + * @brief Allows scan requests from devices in the accept list and connection requests from any device. + * + * Configures the device to: + * - Accept scan requests only from devices in the accept list. + * - Accept connection requests from any device, regardless of whether it is in the accept list. + */ +#ifndef ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ANY +#define ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ANY 0x01 +#endif +/** @def ALLOW_SCAN_REQ_ANY_CONN_REQ_ACCEPT_LIST + * @brief Allows scan requests from any device and connection requests only from devices in the accept list. + * + * Configures the device to: + * - Accept scan requests from any device, regardless of whether it is in the accept list. + * - Accept connection requests only from devices in the accept list. + */ +#ifndef ALLOW_SCAN_REQ_ANY_CONN_REQ_ACCEPT_LIST +#define ALLOW_SCAN_REQ_ANY_CONN_REQ_ACCEPT_LIST 0x02 +#endif +/** @def ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ACCEPT_LIST + * @brief Allows both scan and connection requests only from devices in the accept list. + * + * Configures the device to: + * - Accept scan requests only from devices in the accept list. + * - Accept connection requests only from devices in the accept list. + */ +#ifndef ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ACCEPT_LIST +#define ALLOW_SCAN_REQ_ACCEPT_LIST_CONN_REQ_ACCEPT_LIST 0x03 +#endif +/** @def RSI_BLE_ADV_FILTER_TYPE + * @brief Sets the advertising filter policy to allow both scan and connection requests from any device. + * + * Configures the advertising filter policy to: + * - Accept scan requests from any device, regardless of whether it is in the accept list. + * - Accept connection requests from any device, regardless of whether it is in the accept list. + * + * Uses the `ALLOW_SCAN_REQ_ANY_CONN_REQ_ANY` setting. + */ +#ifndef RSI_BLE_ADV_FILTER_TYPE +#define RSI_BLE_ADV_FILTER_TYPE ALLOW_SCAN_REQ_ANY_CONN_REQ_ANY +#endif +/*=======================================================================*/ +// Address types +/*=======================================================================*/ +/** + * @def LE_PUBLIC_ADDRESS + * @brief Defines the public address type used in BLE communication. + * + * Represents the public address type with a value of 0x00. + */ +#ifndef LE_PUBLIC_ADDRESS +#define LE_PUBLIC_ADDRESS 0x00 +#endif +/** + * @def LE_RANDOM_ADDRESS + * @brief Defines the type for a random address used in BLE communication. + * + * Specifies the value for a random address type with a value of 0x01. + */ +#ifndef LE_RANDOM_ADDRESS +#define LE_RANDOM_ADDRESS 0x01 +#endif +/** + * @def LE_RESOLVABLE_PUBLIC_ADDRESS + * @brief Defines the resolvable public address type used in communication. + * + * Represents the resolvable public address type with a value of 0x02. + */ +#ifndef LE_RESOLVABLE_PUBLIC_ADDRESS +#define LE_RESOLVABLE_PUBLIC_ADDRESS 0x02 +#endif +/** + * @def LE_RESOLVABLE_RANDOM_ADDRESS + * @brief Defines the resolvable random address type used in communication. + * + * Represents the resolvable random address type with a value of 0x03. + */ +#ifndef LE_RESOLVABLE_RANDOM_ADDRESS +#define LE_RESOLVABLE_RANDOM_ADDRESS 0x03 +#endif +/** + * @def RSI_BLE_ADV_DIR_ADDR_TYPE + * @brief Defines the directed advertising address type used in communication. + * + * Represents the directed advertising address type, set to LE_PUBLIC_ADDRESS. + */ +#ifndef RSI_BLE_ADV_DIR_ADDR_TYPE +#define RSI_BLE_ADV_DIR_ADDR_TYPE LE_PUBLIC_ADDRESS +#endif +/*=======================================================================*/ +// Connection parameters +/*=======================================================================*/ +/** + * @def CONNECTION_LATENCY + * @brief Defines the peripheral latency used in communication. + * + * Represents the peripheral latency with a value of 0x0000. + * + * Peripheral latency is the number of connection events the peripheral device + * can skip. A value of 0x0000 means no events are skipped. + */ +#ifndef CONNECTION_LATENCY +#define CONNECTION_LATENCY 0x0000 +#endif +/** + * @def SUPERVISION_TIMEOUT + * @brief Defines the supervision timeout used in BLE communication. + * + * Represents the supervision timeout with a value of 0x07D0 (2000). + * + * The supervision timeout is the maximum time, in milliseconds, that a + * connection can remain idle before being considered lost and terminated. + */ +#ifndef SUPERVISION_TIMEOUT +#define SUPERVISION_TIMEOUT 0x07D0 //2000 +#endif + +/*=======================================================================*/ +// Scan command parameters +/*=======================================================================*/ +//Scan status +/** + * @def RSI_BLE_START_SCAN + * @brief Defines the command to start scanning for BLE devices. + * + * Represents the command to initiate scanning with a value of 0x01. + */ +#ifndef RSI_BLE_START_SCAN +#define RSI_BLE_START_SCAN 0x01 +#endif +/** + * @def RSI_BLE_STOP_SCAN + * @brief Defines the command to stop scanning for BLE devices. + * + * Represents the command to stop scanning with a value of 0x00. + */ +#ifndef RSI_BLE_STOP_SCAN +#define RSI_BLE_STOP_SCAN 0x00 +#endif +//Scan types +/** + * @def SCAN_TYPE_ACTIVE + * @brief Defines the active scan type for BLE communication. + * + * In active scanning, the scanner sends scan request packets to + * advertising devices to obtain additional information. + */ +#ifndef SCAN_TYPE_ACTIVE +#define SCAN_TYPE_ACTIVE 0x01 +#endif +/** + * @def SCAN_TYPE_PASSIVE + * @brief Defines the passive scan type for BLE communication. + * + * In passive scanning, the scanner listens for advertising packets + * without sending scan request packets to the advertising devices. + */ +#define SCAN_TYPE_PASSIVE 0x00 + +#ifndef SCAN_TYPE_PASSIVE +#define SCAN_TYPE_PASSIVE 0x00 +#endif +//Scan filters +/** + * @def SCAN_FILTER_TYPE_ALL + * @brief Defines the scan filter type to accept all advertising packets. + * + * Configures the scanner to accept all advertising packets, + * regardless of their address or data content. + */ +#ifndef SCAN_FILTER_TYPE_ALL +#define SCAN_FILTER_TYPE_ALL 0x00 +#endif +/** + * @def SCAN_FILTER_TYPE_ONLY_ACCEPT_LIST + * @brief Defines the scan filter type to accept only advertising packets from devices in the accept list. + * + * Configures the scanner to accept advertising packets only from devices + * that are included in the accept list, ignoring packets from other devices. + */ +#ifndef SCAN_FILTER_TYPE_ONLY_ACCEPT_LIST +#define SCAN_FILTER_TYPE_ONLY_ACCEPT_LIST 0x01 +#endif +/** + * @def RSI_BLE_SCAN_TYPE + * @brief Configures the BLE scan type to active scanning. + * + * Sets the scan type to active, where the scanner sends scan request packets + * to advertising devices to obtain additional information. + * + * Uses the `SCAN_TYPE_ACTIVE` setting. + */ +#ifndef RSI_BLE_SCAN_TYPE +#define RSI_BLE_SCAN_TYPE SCAN_TYPE_ACTIVE +#endif +/** + * @def RSI_BLE_SCAN_FILTER_TYPE + * @brief Configures the BLE scan filter to accept all advertising packets. + * + * Sets the scan filter type to accept all advertising packets, + * regardless of their address or data content. + * + * Uses the `SCAN_FILTER_TYPE_ALL` setting. + */ +#ifndef RSI_BLE_SCAN_FILTER_TYPE +#define RSI_BLE_SCAN_FILTER_TYPE SCAN_FILTER_TYPE_ALL +#endif +/*-------------------------------------------------------------------------------------------*/ +/** + * @def BLE_DISABLE_DUTY_CYCLING + * @brief Disables duty cycling for BLE operations. + * + * Configures the device to disable duty cycling, which means that BLE + * operations will run continuously without the power-saving sleep cycles. + */ +#ifndef BLE_DISABLE_DUTY_CYCLING +#define BLE_DISABLE_DUTY_CYCLING 0 +#endif +/** + * @def BLE_DUTY_CYCLING + * @brief Enables duty cycling for BLE operations. + * + * Configures the device to enable duty cycling, which means that BLE + * operations will include power-saving sleep cycles to conserve energy. + */ +#ifndef BLE_DUTY_CYCLING +#define BLE_DUTY_CYCLING 1 +#endif +/** + * @def BLR_DUTY_CYCLING + * @brief Enables duty cycling for BLE operations. + * + * Configures the device to enable duty cycling, which includes power-saving + * sleep cycles to conserve energy. The value 2 indicates the specific duty cycling mode. + */ +#ifndef BLR_DUTY_CYCLING +#define BLR_DUTY_CYCLING 2 +#endif +/** + * @def BLE_4X_PWR_SAVE_MODE + * @brief Enables power save mode for BLE 4.x operations. + * + */ +#ifndef BLE_4X_PWR_SAVE_MODE +#define BLE_4X_PWR_SAVE_MODE 4 +#endif +/** + * @def RSI_BLE_PWR_SAVE_OPTIONS + * @brief Configures power save options for BLE operations. + * + * Disables duty cycling to keep the device active and avoid power-saving sleep cycles. + */ +#ifndef RSI_BLE_PWR_SAVE_OPTIONS +#define RSI_BLE_PWR_SAVE_OPTIONS BLE_DISABLE_DUTY_CYCLING +#endif +/*-------------------------------------------------------------------------------------------*/ +/** + * @def RSI_SEL_INTERNAL_ANTENNA + * @brief Selects the internal antenna for BLE operations. + * + * Configures the device to use the internal antenna. The value 0x00 indicates + * the selection of the internal antenna. + */ +#ifndef RSI_SEL_INTERNAL_ANTENNA +#define RSI_SEL_INTERNAL_ANTENNA 0x00 +#endif +/** + * @def RSI_SEL_EXTERNAL_ANTENNA + * @brief Selects the external antenna for BLE operations. + * + * Configures the device to use the external antenna. The value 0x01 indicates + * the selection of the external antenna. + */ +#ifndef RSI_SEL_EXTERNAL_ANTENNA +#define RSI_SEL_EXTERNAL_ANTENNA 0x01 +#endif +#endif + +#ifndef RSI_SEL_ANTENNA +#define RSI_SEL_ANTENNA \ + RSI_SEL_INTERNAL_ANTENNA ///< Antenna Selection - RSI_SEL_EXTERNAL_ANTENNA / RSI_SEL_INTERNAL_ANTENNA +#endif +/*-------------------------------------------------------------------------------------------*/ +/** + * @def RSI_BLE_GATT_ASYNC_ENABLE + * @brief Enables or disables asynchronous GATT operations. + * + * Configures the device to enable or disable asynchronous GATT operations. + * The value 0 indicates that asynchronous GATT operations are disabled. + */ +#ifndef RSI_BLE_GATT_ASYNC_ENABLE +#define RSI_BLE_GATT_ASYNC_ENABLE 0 +#endif +/** + * @def RSI_BLE_GATT_INIT + * @brief Initializes the GATT in Firmware for BLE operations. + * + * 0 - GATT Init in Firmware: Both the GAP service and GATT service will be maintained by Firmware. + * 1 - GATT Init in Host: GAP service and GATT service should be created by the APP/Host/User, + * and the ATT transactions like read, write, notify, and indicate shall be handled by the + * APP/Host/User. Default: GATT Init in Firmware. + */ +#ifndef RSI_BLE_GATT_INIT +#define RSI_BLE_GATT_INIT 0 +#endif +/** + * @def RSI_BLE_INDICATE_CONFIRMATION_FROM_HOST + * @brief Configures indication confirmation from the host. + * + * When this macro is enabled, the host needs to provide confirmation for the indicatation. + * If it is disabled, the firmware will send the confirmation automatically. + */ +#ifndef RSI_BLE_INDICATE_CONFIRMATION_FROM_HOST +#define RSI_BLE_INDICATE_CONFIRMATION_FROM_HOST 0 +#endif +/** + * @def RSI_BLE_MTU_EXCHANGE_FROM_HOST + * @brief Configures whether the MTU exchange process is initiated by the host. + * + * If this macro is disabled, the firmware will initiate the MTU request to the remote device on the successful connection. + * And if Peer initiates MTU exchange Request, then firmware will send Exchange MTU Response in reply to a received Exchange MTU Request. + * If this macro is enabled then APP/Host/User needs to initiate the MTU request by using the rsi_ble_mtu_exchange_event API. + * And if Peer initiates MTU exchange Request, then APP/Host/User shall send Exchange MTU Response in reply to a received Exchange MTU Request using rsi_ble_mtu_exchange_resp API. + */ +#ifndef RSI_BLE_MTU_EXCHANGE_FROM_HOST +#define RSI_BLE_MTU_EXCHANGE_FROM_HOST 0 +#endif +/** + * @def RSI_BLE_SET_SCAN_RESP_DATA_FROM_HOST + * @brief Configures scan response data from the host. + * + * Device will maintain some default scan response data and will be used in the scan_response controller frame. + * By enabling this bit we can make the default data as Null(empty) in the controller and set scan resp data from APP/Host/User. + * + */ +#ifndef RSI_BLE_SET_SCAN_RESP_DATA_FROM_HOST +#define RSI_BLE_SET_SCAN_RESP_DATA_FROM_HOST 0 +#endif +/** + * @def RSI_BLE_DISABLE_CODED_PHY_FROM_HOST + * @brief Configures the disabling of coded PHY from the host. + * + * Device will support the LE-coded phy feature (that is, LR - 125 kbps and 500 kbps) by default. + * If this bit is enabled, the device will not the support the LE-coded phy rates. + */ +#ifndef RSI_BLE_DISABLE_CODED_PHY_FROM_HOST +#define RSI_BLE_DISABLE_CODED_PHY_FROM_HOST 0 +#endif +/*-------------------------------------------------------------------------------------------*/ +// Advertising command parameters +#ifndef RSI_BLE_ADV_INT_MIN +#define RSI_BLE_ADV_INT_MIN 0x100 ///< Minimum advertising interval +#endif +#ifndef RSI_BLE_ADV_INT_MAX +#define RSI_BLE_ADV_INT_MAX 0x200 ///< Maximum advertising interval +#endif + +#ifndef CONNECTION_INTERVAL_MIN +#define CONNECTION_INTERVAL_MIN 0x00A0 ///< Minimum connection interval +#endif +#ifndef CONNECTION_INTERVAL_MAX +#define CONNECTION_INTERVAL_MAX 0x00A0 ///< Maximum connection interval +#endif + +#ifndef LE_SCAN_INTERVAL +#define LE_SCAN_INTERVAL 0x0100 ///< Scan interval +#endif +#ifndef LE_SCAN_WINDOW +#define LE_SCAN_WINDOW 0x0050 ///< Scan window +#endif + +/*=======================================================================*/ +// Extended Advertising parameters +/*=======================================================================*/ +#ifndef RSI_BLE_ENABLE_ADV_EXTN +#define RSI_BLE_ENABLE_ADV_EXTN 0 ///< disabled by default +#endif + +#ifndef RSI_BLE_AE_MAX_ADV_SETS +#define RSI_BLE_AE_MAX_ADV_SETS 2 ///< default number of Advertising sets in extended advertising (Max value = 3) +#endif +/** @} */ \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common.h new file mode 100644 index 000000000..0c9784bd9 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common.h @@ -0,0 +1,537 @@ +/******************************************************************************* + * @file rsi_bt_common.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_BT_COMMON_H +#define RSI_BT_COMMON_H + +#include "sl_si91x_types.h" + +#include "cmsis_os2.h" + +/****************************************************** + * * Macros + * ******************************************************/ +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/// Specifies that packet type is Bluetooth HCI command packet. +#define RSI_BT_HCI_CMD_PKT 0x1 +/// Represents the HCI ACL packet type. +#define RSI_BT_HCI_ACL_PKT 0x2 +/// Specifies the number of packets that can be sent per HCI command. +#define RSI_BT_HCI_PER_CMD_PKT 0x3 +/// Indicates dual mode operation in Bluetooth. +#define RSI_BT_DUAL_MODE 0x8 +/// This macro is used to enable the Bluetooth Low Energy (BLE) protocol. +#define BLE_PROTO_ENABLE BIT(2) +/// This macro is used to enable the Bluetooth Classic protocol. +#define BT_CLASSIC_PROTO_ENABLE BIT(3) +/// This macro is used to enable the proprietary protocol. It sets the 8th bit of the property. +#define PROP_PROTO_ENABLE (BIT(8)) +/// Enable both BLE and Classic Bluetooth protocols. +#define BT_DUAL_MODE_PROTO_ENABLE (BLE_PROTO_ENABLE | BT_CLASSIC_PROTO_ENABLE) +/// Define the bits for Bluetooth Low Energy (BLE) mode. +#define RSI_BT_BLE_MODE_BITS (BIT(2) | BIT(3)) +/// Offset of the BT status in the Bluetooth module. +#define RSI_BT_STATUS_OFFSET 0x0C +/// Offset value for the response type in the Bluetooth module. +#define RSI_BT_RSP_TYPE_OFFSET 0x02 +///Offset value for the length field in the Bluetooth response. +#define RSI_BT_RSP_LEN_OFFSET 0x00 +///Mask used to extract the response length from a Bluetooth response. +#define RSI_BT_RSP_LEN_MASK 0x0FFF +///Protocol identifier for Bluetooth Common. +#define RSI_PROTO_BT_COMMON 0x01 +///Bluetooth protocol type for classic Bluetooth. +#define RSI_PROTO_BT_CLASSIC 0x02 +///Defines the protocol value for Bluetooth Low Energy (BLE). +#define RSI_PROTO_BLE 0x03 +///Definition of the Bluetooth Low Energy (BLE) stack protocol. +#define RSI_PROTO_BT_BLE_STACK 0x05 +///The maximum length of the device name. +#define RSI_DEV_NAME_LEN 50 +///Length of the device address in bytes. +#define RSI_DEV_ADDR_LEN 6 +///Length of the Attribute Protocol (ATT) buffer for the device. +#define RSI_DEV_ATT_LEN 240 +///Defines the Bluetooth classic device type. +#define RSI_BT_CLASSIC_DEVICE 0x00 +///Defines the Bluetooth Low Energy (LE) device type. +#define RSI_BT_LE_DEVICE 0x01 +///Macro definition for an unknown Bluetooth device. The value of this macro is 0xFF. +#define RSI_BT_UNKWON_DEVICE 0xFF +///Defines the stack mode for Bluetooth. +#define STACK_BT_MODE 0x01 +///Defines the stack mode for Bluetooth Low Energy (BLE). +#define STACK_BTLE_MODE 0x02 +//RF types +/// Specify the external RF mode. +#define RSI_EXTERNAL_RF 0x00 +/// Specify the internal RF mode. +#define RSI_INTERNAL_RF 0x01 +/** + * @brief Defines the RF type for the Bluetooth module. + * + * This macro is used to specify the RF type for the Bluetooth module. + * The value `RSI_INTERNAL_RF` indicates that the module uses an internal RF. + * + * @note This macro should be defined before including this header file. + */ +#define RSI_RF_TYPE RSI_INTERNAL_RF +///Maximum number of attributes supported by the Bluetooth module. +#define RSI_MAX_ATT 5 +/** + * @brief Defines the operating mode for WLAN and Bluetooth dual mode. + * + * This macro is used to specify the operating mode for WLAN and Bluetooth dual mode. + * The value 9 represents the dual mode operation. + */ +#define RSI_OPERMODE_WLAN_BT_DUAL_MODE 9 +/// Bluetooth state indicating none. +#define RSI_BT_STATE_NONE 0 +///Defines the state value indicating that the Bluetooth operation mode is done. +#define RSI_BT_STATE_OPERMODE_DONE 1 +///Mask to extract the lower nibble of a byte. +#define LOWERNIBBLE 0x0F +/** @} */ +/****************************************************** + * * Constants + * ******************************************************/ + +/****************************************************** + * * Type Definitions + * ******************************************************/ +/** @addtogroup BT_BLE_TYPES + * @{ */ +typedef struct rsi_ble_cb_s + rsi_ble_cb_t; ///< Typedef for the BLE control block structure refer \ref rsi_ble_cb_s_group for complete information of Driver BLE control block. +typedef struct rsi_bt_classic_cb_s rsi_bt_classic_cb_t; ///< Typedef for the Bluetooth Classic control block structure. +typedef struct rsi_bt_common_specific_cb_s + rsi_bt_common_specific_cb_t; ///< Typedef for the Bluetooth common specific control block structure. +typedef int32_t (*rsi_bt_get_ber_pkt_t)(uint8_t *pkt, + uint16_t pkt_len); ///< Typedef for a function pointer to get BER packet. +/** @} */ +/****************************************************** + * * Enumerations + * ******************************************************/ + +/****************************************************** + * * Enumerations + * ******************************************************/ +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/** + * + * @brief Enumeration of Bluetooth common command requests. + * + * Defines various command requests for Bluetooth operations, including setting + * and getting local device information, initializing and deinitializing the + * device, and configuring antenna and power settings. + */ +typedef enum rsi_bt_common_cmd_request_e { + RSI_BT_SET_LOCAL_NAME = 0x0001, ///< Set the local device name. + RSI_BT_GET_LOCAL_NAME = 0x0002, ///< Get the local device name. + RSI_BT_GET_RSSI = 0x0005, ///< Get the Received Signal Strength Indicator (RSSI). + RSI_BT_GET_LOCAL_DEV_ADDR = 0x0007, ///< Get the local device address. + RSI_BT_REQ_INIT = 0x008D, ///< Initialize the BT classic protocol. + RSI_BT_REQ_DEINIT = 0x008E, ///< De-Initialize the BT classic protocol. + RSI_BT_SET_ANTENNA_SELECT = 0x008F, ///< Select the antenna. + RSI_BT_REQ_PER_CMD = 0x009A, ///< Request Packet Error Rate (PER) command. + RSI_BT_SET_FEATURES_BITMAP = 0x00A6, ///< Set the features bitmap. + RSI_BT_VENDOR_SPECIFIC = 0x00BE, ///< Vendor-specific command. + RSI_BT_SET_ANTENNA_TX_POWER_LEVEL = 0x00A7, ///< Set the antenna transmission power level. + RSI_BT_SET_GAIN_TABLE_OFFSET_OR_MAX_POWER_UPDATE = 0x012C, ///< Set gain table offset or update maximum power. + RSI_BT_SET_BD_ADDR_REQ = 0x012E, ///< Set the Bluetooth device address. + RSI_BT_GET_BT_STACK_VERSION = 0x012F, ///< Get the Bluetooth stack version. + + RSI_BLE_ONLY_OPER_MODE = 0x8010, ///< Set BLE-only operation mode. + RSI_BLE_REQ_PWRMODE = 0x8015, ///< Request BLE power mode. + RSI_BLE_REQ_SOFTRESET = 0x801C ///< Request BLE soft reset. +} rsi_bt_common_cmd_request_t; + +/** + * + * @brief Enumeration of Bluetooth common events. + * + * Defines various events for Bluetooth operations, including the event + * indicating that the Bluetooth card is ready. + */ +typedef enum rsi_bt_common_event_e { + RSI_BT_EVENT_CARD_READY = 0x0505, ///< Event indicating that the Bluetooth card is ready. +} rsi_bt_common_event_t; + +/** + * + * @brief Enumeration of Bluetooth common command responses. + * + * Defines various command responses for Bluetooth operations, including responses + * for setting and querying local device information, initializing and deinitializing + * the device, and configuring antenna and power settings. + */ +typedef enum rsi_bt_common_cmd_resp_e { + RSI_BT_RSP_SET_LOCAL_NAME = 0x0001, ///< Response for setting the local device name. + RSI_BT_RSP_QUERY_LOCAL_NAME = 0x0002, ///< Response for querying the local device name. + RSI_BT_RSP_QUERY_RSSI = 0x0005, ///< Response for querying the Received Signal Strength Indicator (RSSI). + RSI_BT_RSP_QUERY_LOCAL_BD_ADDRESS = 0x0007, ///< Response for querying the local device address. + RSI_BT_RSP_INIT = 0x008D, ///< Response for initializing the BT classic protocol. + RSI_BT_RSP_DEINIT = 0x008E, ///< Response for deinitializing the BT classic protocol. + RSI_BT_RSP_ANTENNA_SELECT = 0x008F, ///< Response for selecting the antenna. + RSI_BT_RSP_SET_FEATURES_BITMAP = 0x00A6, ///< Response for setting the features bitmap. + RSI_BT_RSP_ANTENNA_TX_POWER_LEVEL = 0x00A7, ///< Response for setting the antenna transmission power level. + RSI_BT_RSP_SET_GAIN_TABLE_OFFSET_OR_MAX_POWER_UPDATE = + 0x012C, ///< Response for setting gain table offset or updating maximum power. + RSI_BT_RSP_SET_BD_ADDR = 0x012E, ///< Response for setting the Bluetooth device address. + + RSI_BLE_RSP_ONLY_OPER_MODE = 0x8010, ///< Response for setting BLE-only operation mode. + RSI_BLE_RSP_PWRMODE = 0x8015, ///< Response for requesting BLE power mode. + RSI_BLE_RSP_SOFTRESET = 0x801C ///< Response for requesting BLE soft reset. +} rsi_bt_common_cmd_resp_t; +/** @} */ +/****************************************************** + * * Structures + * ******************************************************/ +/** @addtogroup BT_BLE_TYPES + * @{ */ +/// Driver control block +struct rsi_driver_cb_s; +// Driver BT Common control block +/** + * @brief Structure representing the Bluetooth common specific callback. + * + * This structure is used to define the parameters for Bluetooth common specific callbacks, + * including the PER Bit Error Rate (BER) callback. + */ +struct rsi_bt_common_specific_cb_s { + /** PER BER Callbacks */ + rsi_bt_get_ber_pkt_t rsi_bt_get_ber_pkt; +}; +// Specific BT, BLE blocks +/** + * @brief Structure representing the Bluetooth global callback. + * + * This structure is used to define the parameters for Bluetooth global callbacks, + * including common specific callbacks, BLE specific callbacks, and BT Classic specific callbacks. + */ +typedef struct rsi_bt_global_cb_s { + /** BT Common specific callback */ + rsi_bt_common_specific_cb_t *bt_common_specific_cb; + /** BLE specific callback */ + rsi_ble_cb_t *ble_specific_cb; + /** BT Classic specific callback */ + rsi_bt_classic_cb_t *bt_specific_cb; +} rsi_bt_global_cb_t; + +// Remote LE Device info structure + +/** + * @brief Structure representing the remote BLE device information. + * + * This structure is used to define the parameters for storing information about a remote BLE device, + * including its address, buffer counts, and synchronization mechanisms. + */ +typedef struct rsi_remote_ble_info_s { + /** BD Address of the remote LE device */ + uint8_t remote_dev_bd_addr[RSI_DEV_ADDR_LEN]; + /** Address type of the remote LE device */ + uint8_t remote_dev_addr_type; + /** Available Buffer Count */ + uint8_t avail_buf_cnt; + /** Max Buffer Count */ + uint8_t max_buf_cnt; + /** Max Buffer Length */ + uint16_t max_buf_len; + /** Flag for dev info used or not */ + uint8_t used; + /** Flag for checking command in use */ + uint8_t cmd_in_use; + /** Flag for checking expected remote response for each procedure */ + uint16_t expected_resp; + /** Buffer config mode */ + uint8_t mode; + /** Mutex handle for avail_buf_info update */ + osMutexId_t ble_buff_mutex; +} rsi_remote_ble_info_t; +// Driver BT/BLE/PROP_PROTOCOL control block +/** + * @brief Structure representing the Bluetooth control block. + * + * This structure is used to define the parameters for the Bluetooth control block, + * including status, state, synchronization mechanisms, and remote BLE device information. + */ +typedef struct rsi_bt_cb_s { + /** Driver BT control block status */ + volatile int32_t status; + /** Driver BT control block state */ + uint16_t state; + /** Driver BT control block mutex */ + osMutexId_t bt_mutex; + /** Driver BT control block expected command response */ + void *expected_response_buffer; + /** Expected command response type */ + uint16_t expected_response_type; + /** Sync command flag to identify that the command is blocking / sync type */ + uint8_t sync_rsp; + /** BT device type at disconnect */ + uint8_t dev_type; + /** Driver BT control block semaphore for commands */ + osSemaphoreId_t bt_cmd_sem; + /** Driver BT control block semaphore */ + osSemaphoreId_t bt_sem; + /** Buffer pointer given by application to driver */ + uint8_t *app_buffer; + /** Buffer length given by application to driver */ + uint32_t app_buffer_length; + /** Pointer to global Bluetooth callback structure */ + rsi_bt_global_cb_t *bt_global_cb; + /** Address of the device to which directed advertising has to be done in ll privacy mode */ + uint8_t directed_addr[RSI_DEV_ADDR_LEN]; +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/** Maximum number of remote BLE devices */ +#define MAX_REMOTE_BLE_DEVICES 10 + /** @} */ + /** Structure holding remote LE device info (BD address and controller buffer availability) */ + rsi_remote_ble_info_t remote_ble_info[MAX_REMOTE_BLE_DEVICES]; + /** Variable indicating buffer full/empty status --> 0 -> Empty, 1 -> Full */ + uint8_t buf_status; + /** Variable indicating command in use status --> 0 -> Not In Use, 1 -> In Use */ + uint8_t cmd_status; + /** Variable to save remote info index */ + uint8_t remote_ble_index; + /** Driver BT control block asynchronous status */ + volatile int32_t async_status; +} rsi_bt_cb_t; + +// Set local name command structure + +/** + * @brief Structure representing the Bluetooth request to set the local device name. + * + * This structure is used to define the parameters for setting the local Bluetooth device name, + * including the name length and the name itself. + */ +typedef struct rsi_bt_req_set_local_name_s { + /** Length of the required name to be set */ + uint8_t name_len; + /** Required name */ + int8_t name[RSI_DEV_NAME_LEN]; +} rsi_bt_req_set_local_name_t; + +// Get RSSI command structure + +/** + * @brief Structure representing the Bluetooth request to get the Received Signal Strength Indicator (RSSI). + * + * This structure is used to define the parameters for requesting the RSSI of a remote Bluetooth device, + * including the device address. + */ +typedef struct rsi_bt_get_rssi_s { + /** Device address (6 bytes) */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; +} rsi_bt_get_rssi_t; + +// Response structures + +// Get local name response structures + +/** + * @brief Structure representing the Bluetooth response to get the local device name. + * + * This structure is used to define the parameters for the response that includes the local Bluetooth device name, + * including the name length, the name itself, and a reserved variable. + */ +typedef struct rsi_bt_resp_get_local_name_s { + /** Name length */ + uint8_t name_len; + /** Array which consists name of the local device. The maximum size of this array is 50 */ + int8_t name[RSI_DEV_NAME_LEN]; + /** Reserved variable */ + uint8_t _reserved; +} rsi_bt_resp_get_local_name_t; +/** @} */ + +/** @addtogroup BT-BLE Common + * @{ */ +// Get Stack Version +/** + * @brief Structure representing the Bluetooth response to get the BT stack version. + * + * This structure is used to define the parameters for the response that includes the Bluetooth stack version. + */ +typedef struct rsi_bt_resp_get_bt_stack_version_s { + /** Bluetooth stack version */ + int8_t stack_version[10]; +} rsi_bt_resp_get_bt_stack_version_t; + +// Set antenna structure +/** + * @brief Structure representing the BLE set antenna request. + * + * This structure is used to define the parameters for setting the BLE antenna, + * including the antenna value which can be internal or external. + */ +typedef struct rsi_ble_set_antenna_s { + /** Antenna value - internal/external */ + uint8_t value; +} rsi_ble_set_antenna_t; + +/** + * @brief Structure representing the Bluetooth set feature bitmap. + * + * This structure is used to define the parameters for setting the Bluetooth feature bitmap, + * which includes feature bits in a bit map format. + */ +typedef struct rsi_bt_set_feature_bitmap_s { + /** Features bits (bit map) */ + uint32_t bit_map; +} rsi_bt_set_feature_bitmap_t; + +/** + * @brief Structure representing the BLE operation mode. + * + * This structure is used to define the parameters for the BLE operation mode, + * including Bluetooth features and the module type. + */ +typedef struct rsi_ble_oper_mode_s { + /** Bluetooth features */ + uint32_t bt_features; + /** Module type */ + uint8_t module_type; +} rsi_ble_oper_mode_t; + +/** + * @brief Structure representing the BLE power mode. + * + * This structure is used to define the parameters for setting the BLE power mode, + * including the power mode and Ultra-Low-Power (ULP) mode enable settings. + */ +typedef struct rsi_ble_power_mode_s { + /** Power mode to set */ + uint8_t power_mode; + /** Set LP/ULP/ULP-without RAM retention */ + uint8_t ulp_mode_enable; +} rsi_ble_power_mode_t; + +// Set antenna tx power level structure + +/** + * @brief Structure representing the Bluetooth set antenna transmit power level. + * + * This structure is used to define the parameters for setting the antenna transmit power level, + * including the protocol mode and transmit power. + */ +typedef struct rsi_bt_set_antenna_tx_power_level_s { + /** Protocol mode: 1-BT, 2-LE */ + uint8_t protocol_mode; + /** Transmit power */ + int8_t tx_power; +} rsi_bt_set_antenna_tx_power_level_t; + +// BT PER Stats +/** + * @brief Structure representing the Bluetooth Packet Error Rate (PER) statistics. + * + * This structure is used to define the parameters for collecting Bluetooth PER statistics, + * including counts of CRC fails, successful transmissions, and other relevant metrics. + */ +typedef struct rsi_bt_per_stats_s { + /** Packet count of CRC fails (Cyclic Redundancy Check (CRC)) */ + uint16_t crc_fail_cnt; + /** Packet count of CRC passes */ + uint16_t crc_pass_cnt; + /** Packet count of aborted transmissions */ + uint16_t tx_abort_cnt; + /** Packet count of dropped receptions */ + uint16_t rx_drop_cnt; + /** Packet count of CCA Idle (Clear Channel Assessment (CCA)) */ + uint16_t rx_cca_idle_cnt; + /** Packet count of Rx start */ + uint16_t rx_start_idle_cnt; + /** Packet count of aborted receptions */ + uint16_t rx_abrt_cnt; + /** Packet count of successful transmissions */ + uint16_t tx_dones; + /** Received Signal Strength Indicator of the packet */ + int8_t rssi; + /** Packet count of ID packets received */ + uint16_t id_pkts_rcvd; + /** Dummy array of length 5 */ + uint16_t dummy[5]; +} rsi_bt_per_stats_t; + +/** + * @brief Structure representing the Bluetooth set local Bluetooth Device (BD) address. + * + * This structure is used to define the parameters for setting the local Bluetooth device address. + */ +typedef struct rsi_bt_set_local_bd_addr_s { + /** Device address (6 bytes) */ + uint8_t dev_addr[RSI_DEV_ADDR_LEN]; +} rsi_bt_set_local_bd_addr_t; + +/** + * @brief Structure for updating gain table offset or max power in Bluetooth commands. + */ +typedef struct rsi_bt_cmd_update_gain_table_offset_or_maxpower_s { + /** node id (0 - BLE, 1 - BT) */ + uint8_t node_id; + /** gain table request type (0 - max power update, 1 - offset update) */ + uint8_t update_gain_table_type; + /** gain table payload length */ + uint8_t payload_len; + /** gain table payload data */ + uint8_t payload[128]; +} rsi_bt_cmd_update_gain_table_offset_or_maxpower_t; +/** @} */ +/****************************************************** + * * BT/BLE common function declarations + * ******************************************************/ +void rsi_bt_set_status(rsi_bt_cb_t *bt_cb, int32_t status); +void rsi_bt_common_tx_done(sl_si91x_packet_t *pkt); +int8_t rsi_bt_cb_init(rsi_bt_cb_t *bt_cb, uint16_t protocol_type); +int32_t rsi_bt_driver_send_cmd(uint16_t cmd, void *cmd_struct, void *resp); +uint16_t rsi_bt_global_cb_init(struct rsi_driver_cb_s *driver_cb, uint8_t *buffer); +uint16_t rsi_driver_process_bt_resp_handler(void *rx_pkt); +uint16_t rsi_bt_get_proto_type(uint16_t rsp_type, rsi_bt_cb_t **bt_cb); + +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ +#define HCI_BT_PER_STATS_CMD_ID 0x08 ///< HCI command ID for Bluetooth Packet Error Rate (PER) statistics. +#define HCI_BLE_TRANSMIT_CMD_ID 0x13 ///< HCI command ID for BLE transmit command. +#define HCI_BLE_RECEIVE_CMD_ID 0x14 ///< HCI command ID for BLE receive command. +#define HCI_BT_TRANSMIT_CMD_ID 0x15 ///< HCI command ID for Bluetooth transmit command. +#define HCI_BT_RECEIVE_CMD_ID 0x16 ///< HCI command ID for Bluetooth receive command. +/** @} */ +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h new file mode 100644 index 000000000..046ef8071 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_apis.h @@ -0,0 +1,295 @@ +/******************************************************************************* + * @file rsi_bt_common_apis.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_BT_COMMON_APIS_H +#define RSI_BT_COMMON_APIS_H + +#include "rsi_bt_common.h" +#include "rsi_utils.h" + +/****************************************************** + * * Macros + * ******************************************************/ + +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +/// success return value +#define RSI_SUCCESS 0 + +/// failure return value +#define RSI_FAILURE -1 +/** @} */ +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ + +/****************************************************** + * * Type Definitions + * ******************************************************/ + +/****************************************************** + * * Structures + * ******************************************************/ + +/****************************************************** + * * Global Variables + * ******************************************************/ + +/****************************************************** + * * BT Common API's Declarations + * ******************************************************/ +/** @addtogroup BT-BLE +* @{ +*/ +#ifdef __cplusplus +extern "C" { +#endif +/*==============================================*/ +/** + * @fn int32_t rsi_bt_set_bd_addr(const uint8_t *dev_addr) + * @brief Set the device BD address. This is a blocking API. + * @pre Pre-conditions: + * - needs to be called immediately after device initialization. + * @param[in] dev_addr - public address of the device to be set + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * - 3 - Command is given in wrong state (i.e., not immediate after opermode) + * @note This is a blocking API. Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) . + */ +int32_t rsi_bt_set_bd_addr(const uint8_t *dev_addr); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_set_local_name(const uint8_t *local_name) + * @brief Set the given name to local device. This is a blocking API. + * @pre Pre-conditions: + * - Device should be initialized before calling this API. + * @param[in] local_name - Name to be set to the local device. + * @note For BLE alone Opermode : When the name of the local device is set to a value with length more than 16 bytes then error is returned with an error code 0x4E66. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_set_local_name(const uint8_t *local_name); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_cmd_update_gain_table_offset_or_max_pwr(uint8_t node_id, uint8_t payload_len, uint8_t *payload, uint8_t req_type) + * @brief Update gain table offset/max power. This is blocking API. + * @pre Pre-conditions: + * - Device should be initialized before calling this API. + * @param[in] node_id - Node ID (0 - BLE, 1 - BT). + * @param[in] payload_len - Length of the payload. + * @param[in] payload - Payload containing table data of gain table offset/max power + * @param[in] req_type - Update gain table request type + * - 0 - Max power update + * - 1 - Max power offset update + * - 2 - LP_Chain 0dBm offset update + * - 3 - LP_chain 10dBm offset update. + * @return The following values are returned: + * - 0 - Success + * - 0x4F01 - Invalid gain table payload length + * - 0x4F02 - Invalid region. + * - 0x4F03 - Invalid gain table offset request type + * - 0x4F04 - Invalid node id. + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_cmd_update_gain_table_offset_or_max_pwr(uint8_t node_id, + uint8_t payload_len, + uint8_t *payload, + uint8_t req_type); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_get_local_name(rsi_bt_resp_get_local_name_t *bt_resp_get_local_name) + * @brief Get the local device name. This is a blocking API. + * @pre Pre-conditions: + * - Device should be initialized before calling this API. + * @param[out] bt_resp_get_local_name - This parameter is the response buffer to hold the response of this API. Please refer rsi_bt_resp_get_local_name_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_get_local_name(rsi_bt_resp_get_local_name_t *bt_resp_get_local_name); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_get_rssi(uint8_t *dev_addr, int8_t *resp) + * @brief Get the RSSI of the remote device. This is a blocking API. + * @pre Pre-conditions: + * - rsi_bt_connect() API need to be called before this API. + * @param[in] dev_addr - Remote device address. + * @param[out] resp - Parameter to hold the response of this API, RSSI is filled in this resp parameter. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_get_rssi(uint8_t *dev_addr, int8_t *resp); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_get_local_device_address(uint8_t *resp) + * @brief Get the local device address. This is a blocking API. + * @pre Pre-conditions: + * - Device should be initialized before calling this API. + * @param[out] resp - Parameter to hold the response of this API, local bd_addr is filled in this resp parameter. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_get_local_device_address(uint8_t *resp); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_get_bt_stack_version(rsi_bt_resp_get_bt_stack_version_t *bt_resp_get_bt_stack_version) + * @brief Get the BT stack version. This is a blocking API. + * @param[out] bt_resp_get_bt_stack_version - Response buffer to hold the response of this API. Please refer rsi_bt_resp_get_bt_stack_version_s structure for more info + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_get_bt_stack_version(rsi_bt_resp_get_bt_stack_version_t *bt_resp_get_bt_stack_version); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_init(void) + * @brief Initialize the BT device. This is a blocking API. + * @pre Pre-conditions: + * - Device should be initialized before calling this API. + * - If the device is in powersave, get back the device to ACTIVE MODE by using \ref rsi_bt_power_save_profile() + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_init(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_deinit(void) + * @brief Deinitialize the BT device. This is a blocking API. + * @pre Pre-conditions: + * - Device should be initialized before this API. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_deinit(void); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_set_antenna(uint8_t antenna_value) + * @brief Select either internal / external antenna on the chip. This is a blocking API. + * @pre Pre-conditions: + * - Device should be initialized before calling this API. + * @param[in] antenna_value - Parameter is used to select either internal or external antenna. Possible values: + * - 0x00 RSI_SEL_INTERNAL_ANTENNA + * - 0x01 RSI_SEL_EXTERNAL_ANTENNA + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + */ +int32_t rsi_bt_set_antenna(uint8_t antenna_value); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_power_save_profile(uint8_t psp_mode, uint8_t psp_type) + * @brief Select the power save profile mode for BT / BLE. This is a blocking API. + * @pre Pre-conditions: + * - Device should be initialized before calling this API + * @param[in] psp_mode Following psp_mode is defined. + * - 0 - RSI_ACTIVE. In this mode module is active and power save is disabled. + * - 1 - RSI_SLEEP_MODE_1. On mode. In this sleep mode, SoC will never turn off, therefore no + * handshake is required before sending data to the module. BT/BLE does not support this mode. + * - 2 - RSI_SLEEP_MODE_2. Connected sleep mode. In this sleep mode, SoC will go to sleep based + * on GPIO or Message, therefore handshake is required before sending data to the module. + * - 8 - RSI_SLEEP_MODE_8 :Deep sleep mode with RAM RETENTION. + * - 10- RSI_SLEEP_MODE_10 : Deep sleep mode without RAM RETENTION. + * In this sleep mode, module will turn off the + * SoC. Since SoC is turn off, therefore handshake is required before sending data to the module. + * @param[in] psp_type Following psp_type is defined. + * - 0 - RSI_MAX_PSP. This psp_type will be used for max power saving + * - 1 - Fast PSP + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note If the user wants to enable power save in CoEx mode (WLAN + BT LE) mode - It is mandatory to enable WLAN power save along with BT LE power save. + * @note The device will enter into power save if and only if both protocol (WLAN, BLE) power save modes are enabled. + * @note Refer to the Status Codes section for the above error codes at [additional-status-codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors). + * @note psp_type is only valid in psp_mode 2. + * - BT/BLE does not support in RSI_SLEEP_MODE_1. + * - BT/BLE supports only RSI_MAX_PSP mode. Remaining modes are not supported. + */ +int32_t rsi_bt_power_save_profile(uint8_t psp_mode, uint8_t psp_type); + +/*==============================================*/ +/** + * @fn int32_t rsi_bt_per_stats(uint8_t cmd_type, struct rsi_bt_per_stats_s *rsi_bt_per_stats) + * @brief Request the local device for BT PER operation. + * @pre Pre-conditions: + * - Call rsi_bt_per_tx() or rsi_bt_per_rx() before calling this API. + * @param[in] cmd_type - Parameter to define the command id type for PER operation. + * - BT_PER_STATS_CMD_ID (0x08) - Command id enables PER statistics + * - BT_TRANSMIT_CMD_ID (0x15) - Command id enables PER transmit + * - BT_RECEIVE_CMD_ID (0x16) - Command id enables PER receive + * @param[in] rsi_bt_per_stats - reference to the response structure. Please refer to rsi_bt_per_stats_s structure for more info. + * @return The following values are returned: + * - 0 - Success + * - Non-Zero Value - Failure + * @note Refer Error Codes section for common error codes error-codes. + */ +int32_t rsi_bt_per_stats(uint8_t cmd_type, struct rsi_bt_per_stats_s *per_stats); + +/** @} */ + +/*==============================================*/ +/** + * @fn rsi_bt_set_feature_bitmap + * + */ +int32_t rsi_bt_set_feature_bitmap(uint32_t feature_bit_map); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_config.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_config.h new file mode 100644 index 000000000..f6a038ebc --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_bt_common_config.h @@ -0,0 +1,220 @@ +/******************************************************************************* + * @file rsi_bt_common_config.h + * @brief : This file contains user configurable details to configure the device + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_BT_COMMON_CONFIG_H +#define RSI_BT_COMMON_CONFIG_H +/** @addtogroup BT_BLE_CONSTANTS + * @{ + */ + +#ifndef BD_ADDR_ARRAY_LEN +#define BD_ADDR_ARRAY_LEN 18 ///< length of the Bluetooth device address array +#endif +#ifndef RSI_LINKKEY_REPLY_SIZE +#define RSI_LINKKEY_REPLY_SIZE 16 ///< size of the link key reply +#endif +// WLAN + BT Classic coex mode +#ifndef RSI_OPERMODE_WLAN_BT_CLASSIC +#define RSI_OPERMODE_WLAN_BT_CLASSIC 5 ///< operation mode for WLAN and Bluetooth Classic +#endif +#ifndef RSI_BT_BLE_DUAL_MODE +#define RSI_BT_BLE_DUAL_MODE 9 ///< operation mode for Bluetooth and BLE dual mode +#endif + +#ifndef BT_GLOBAL_BUFF_LEN +#define BT_GLOBAL_BUFF_LEN 10000 ///< size of the global buffer for Bluetooth operations +#endif +/*=======================================================================*/ +// Discovery command parameters +/*=======================================================================*/ + +// Discovery mode +// Start the discoverable mode +#ifndef START_DISCOVERY +#define START_DISCOVERY 0x01 ///< command to start device discovery +#endif + +// Start the limited discoverable mode +#ifndef START_LIMITED_DISCOVERY +#define START_LIMITED_DISCOVERY 0x02 ///< command to start limited discovery mode +#endif + +// Stop the discoverable mode +#ifndef STOP_DISCOVERY +#define STOP_DISCOVERY 0x00 ///< command to stop discovery mode +#endif +/*=======================================================================*/ +// Connectability command parameters +/*=======================================================================*/ + +// Connectable mode +// Start the connectable mode +#ifndef CONNECTABLE +#define CONNECTABLE 0x01 ///< state indicating the device is connectable +#endif + +// Stop the connectable mode +#ifndef NON_CONNECTABLE +#define NON_CONNECTABLE 0x00 ///< state indicating the device is non-connectable +#endif + +/*=======================================================================*/ +// SSP Confirmation command parameters +/*=======================================================================*/ +// Confimation type +// Accept confirmation +#ifndef ACCEPT +#define ACCEPT 0x01 ///< SSP confirmation command parameter indicating acceptance +#endif + +// Reject confirmation +#ifndef REJECT +#define REJECT 0x00 ///< SSP confirmation command parameter indicating rejection +#endif +/*=======================================================================*/ +// BT classic profile enable BITS +/*=======================================================================*/ +#ifndef RSI_SPP_PROFILE_BIT +#define RSI_SPP_PROFILE_BIT BIT(0) ///< bitmask to enable the SPP profile in Bluetooth Classic (BIT(0)) +#endif + +#ifndef RSI_A2DP_PROFILE_BIT +#define RSI_A2DP_PROFILE_BIT BIT(1) ///< bitmask to enable the A2DP profile in Bluetooth Classic (BIT(1)) +#endif + +#ifndef RSI_AVRCP_PROFILE_BIT +#define RSI_AVRCP_PROFILE_BIT BIT(2) ///< bitmask to enable the AVRCP profile in Bluetooth Classic (BIT(2)) +#endif + +#ifndef RSI_HFP_PROFILE_BIT +#define RSI_HFP_PROFILE_BIT BIT(3) ///< bitmask to enable the HFP profile in Bluetooth Classic (BIT(3)) +#endif + +#ifndef RSI_PBAP_PROFILE_BIT +#define RSI_PBAP_PROFILE_BIT \ + BIT(4) #define RSI_PBAP_PROFILE_BIT BIT(4) ///< bitmask to enable the PBAP profile in Bluetooth Classic (BIT(4)) +#endif +/*=======================================================================*/ +// A2DP Profile Related +/*=======================================================================*/ + +#ifndef A2DP_BURST_MODE +#define A2DP_BURST_MODE 1 ///< A2DP profile setting for burst mode , 0 - Disable, 1 - Enable +#endif + +#ifndef A2DP_BURST_SIZE +#define A2DP_BURST_SIZE 1 ///< Number of PCM/MP3 packets buffered +#endif + +#ifndef PCM_AUDIO +#define PCM_AUDIO 1 ///< Audio mode using PCM (Pulse Code Modulation) +#endif +#ifndef SBC_AUDIO +#define SBC_AUDIO 2 ///< Audio mode using SBC (Subband Coding) +#endif +#ifndef MP3_AUDIO +#define MP3_AUDIO 3 ///< Audio mode using MP3 (MPEG-1 Audio Layer 3) +#endif + +#ifndef RSI_AUDIO_DATA_TYPE +#define RSI_AUDIO_DATA_TYPE \ + SBC_AUDIO ///< Defines the audio data type for the A2DP profile as SBC (Subband Coding) (Value = SBC_AUDIO) +#endif +#ifndef PCM_INPUT_BUFFER_SIZE +#define PCM_INPUT_BUFFER_SIZE (30 * 512) ///< Size of the PCM input buffer in bytes +#endif + +#ifndef MP3_INPUT_BUFFER_SIZE +#define MP3_INPUT_BUFFER_SIZE (10 * 512) ///< Size of the MP3 input buffer in bytes +#endif + +#ifndef BIN_FILE +#define BIN_FILE 1 ///< File type indicating binary format +#endif +#ifndef BT_ARRAY +#define BT_ARRAY 2 ///< Array type for Bluetooth data +#endif +#ifndef SD_BIN_FILE +#define SD_BIN_FILE 3 ///< File type indicating a binary format for SD +#endif + +#ifndef RSI_AUDIO_DATA_SRC +#define RSI_AUDIO_DATA_SRC BIN_FILE ///< Defines the audio data source as a binary file (Value = BIN_FILE) +#endif + +#ifndef PRE_ENC_BUF_LEN +#define PRE_ENC_BUF_LEN 8 ///< Length of the pre-encoded buffer (Value = 8) +#endif + +//avdtp related defines +#ifndef ACCEPTOR_ROLE +#define ACCEPTOR_ROLE 1 ///< AVDTP role indicating the acceptor (Value = 1) +#endif +#ifndef INITIATOR_ROLE +#define INITIATOR_ROLE 2 ///< AVDTP role indicating the initiator (Value = 2) +#endif +#ifndef ANY_ROLE +#define ANY_ROLE 3 ///< AVDTP role indicating any role +#endif + +#ifndef RSI_BT_MAX_PAYLOAD_SIZE +#define RSI_BT_MAX_PAYLOAD_SIZE \ + 1040 ///< BT MTU size changes //310 /* Max supported is 200, but 190 gives optimum Tx throughput */ +#endif + +#ifndef BT_BDR_MODE +#define BT_BDR_MODE 0 ///< 1 - HP chain +#endif + +#ifndef USE_REM_MTU_SIZE_ONLY +#define USE_REM_MTU_SIZE_ONLY 1 ///< Flag to use only the remote MTU size +#endif + +#ifndef TA_BASED_ENCODER +#define TA_BASED_ENCODER 0 ///< Encoder type based on TA +#endif +/** @} */ + +/*=======================================================================*/ +// Added default macros which was expected to be defined in the ble_config.h +/*=======================================================================*/ +#ifndef RSI_BLE_SET_RAND_ADDR +#define RSI_BLE_SET_RAND_ADDR "00:23:A7:12:34:56" +#endif + +#ifndef RSI_BLE_MAX_NBR_PERIPHERALS +#define RSI_BLE_MAX_NBR_PERIPHERALS 3 +#endif + +#ifndef RSI_BLE_MAX_NBR_CENTRALS +#define RSI_BLE_MAX_NBR_CENTRALS 1 +#endif + +#endif //RSI_BT_COMMON_CONFIG_H diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_common.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_common.h new file mode 100644 index 000000000..721d2280a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_common.h @@ -0,0 +1,323 @@ +/******************************************************************************* + * @file rsi_common.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_COMMON_H +#define RSI_COMMON_H + +#include "sl_constants.h" + +#include "cmsis_os2.h" +#include "sl_si91x_status.h" + +#include + +#include "rsi_user.h" +#include "rsi_utils.h" +#include "rsi_common_apis.h" + +#include + +/****************************************************** + * * Macros + * ******************************************************/ +//SL_PRINTF logging call +#ifndef SL_PRINTF +#define SL_PRINTF(...) +#endif + +#define IS_LITTLE_ENDIAN 0 +#define IS_BIG_ENDIAN 1 + +#define RSI_TRUE 1 +#define RSI_FALSE 0 + +// Max packet length of common command responses +//changed cmd len for crypto and PUF +#if defined(SLI_PUF_ENABLE) || (defined RSI_CRYPTO_ENABLE) +#define RSI_COMMON_CMD_LEN 1600 +#else +#define RSI_COMMON_CMD_LEN 100 +#endif + +// Max packet length of ssl rx packet +#define RSI_SSL_RECV_BUFFER_LENGTH 0 + +// Max packet length of rx packet +#define RSI_DRIVER_RX_PKT_LEN 0 +#define SIZE_OF_HEADROOM 0 + +// Max packet length of BT COMMON tx packet +#define RSI_BT_COMMON_CMD_LEN (300 + SIZE_OF_HEADROOM) +#if ENCODER_IN_RS9116 +#define RSI_BT_CLASSIC_CMD_LEN 4000 +#else +#define RSI_BT_CLASSIC_CMD_LEN (1040 + SIZE_OF_HEADROOM) +#endif +#define RSI_BLE_CMD_LEN (300 + SIZE_OF_HEADROOM) + +#define RSI_DRIVER_POOL_SIZE sizeof(uint32_t) + ((((uint32_t)(sizeof(rsi_driver_cb_t))) + 3) & ~3) + +#define RSI_WAIT_TIME RSI_WAIT_FOREVER + +#define RSI_TX_EVENT_WAIT_TIME (30000 + TX_WAIT_TIME) +#define DEFAULT_TIMEOUT RSI_TX_EVENT_WAIT_TIME +#define WAIT_TIMEOOUT 5000 + +// Internal command timeout defines +#define RSI_BAND_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_MAC_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_DISCONNECT_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_TRANSMIT_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_RX_STATS_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WMM_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_AUTO_CONFIG_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SOCK_CONFIG_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_ANTENNA_SEL_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_DEBUG_LOG_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_GET_RAM_DUMP_RESPONSE_WAIT_TIME ((1000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_FEATURE_FRAME_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_UART_FLOW_CTRL_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PWRMODE_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_START_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_SET_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_DIS_SET_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_GET_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_DIS_GET_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_LOAD_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_AES_ENCRYPT_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_AES_DECRYPT_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_AES_MAC_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_INTR_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SEND_DATA_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SWITCH_PROTO_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_RAW_DATA_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_DIS_ENROLL_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PUF_ENROLL_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_GAIN_TABLE_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_GET_PROFILE_RESPONSE_WAIT_TIME ((1000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SET_PROFILE_RESPONSE_WAIT_TIME ((1000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_EAP_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_REGION_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_REGION_AP_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_DYNAMIC_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_ROAMING_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_MULTICAST_FIL_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_HT_CAPS_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_MULTICAST_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BCAST_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_CARD_READY_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_INIT_RESPONSE_WAIT_TIME ((3000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_CONFIG_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_GET_RANDOM_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_RSSI_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_QUERY_NETWORK_PARAMS_WAIT_TIME ((200 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_REQ_GET_CFG_WAIT_TIME ((200 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_CFG_SAVE_WAIT_TIME ((1000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BOARD_READY_WAIT_TIME ((50000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SET_SLEEP_TIMER_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_DEINIT_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_CERTIFICATE_RESPONSE_WAIT_TIME ((1000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_REJOIN_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_USER_SC_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_REQ_GET_STATS_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_AUTO_JOIN_RESPONSE_WAIT_TIME \ + ((60000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) //! Here timeout should wait for init,scan and join commands +#define RSI_DELETE_PROFILE_RESPONSE_WAIT_TIME ((1000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_IAP_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_IAP_GET_CERT_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_IAP_GEN_SIG_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_TA_M4_COMMAND_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_ADD_MFI_IE_RESPONSE_WAIT_TIME ((500 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_FILTER_BROADCAST_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SET_RTC_TIMER_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#ifdef RSI_ASSERT_API +#define RSI_ASSERT_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#endif +#define RSI_WLAN_RADIO_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_GET_RTC_TIMER_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_TCP_WINDOW_RESPONSE_WAIT_TIME ((5000 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_TIMEOUT_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SET_CONFIG_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#ifdef FW_LOGGING_ENABLE +#define RSI_DEVICE_LOG_RESPONSE_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#endif +// WIFI WAIT timeout defines +#define RSI_SCAN_RESPONSE_WAIT_TIME ((10000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_JOIN_RESPONSE_WAIT_TIME ((10000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_P2P_RESPONSE_WAIT_TIME ((1000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BGSCAN_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PING_RESPONSE_WAIT_TIME ((60000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WEP_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_IPCONFV4_RESPONSE_WAIT_TIME ((20000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_IPCONFV6_RESPONSE_WAIT_TIME ((20000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_MDNSD_RESPONSE_WAIT_TIME \ + ((250000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) //!Firmware max timeout value is 240 seconds +#define RSI_HTTP_RESPONSE_WAIT_TIME \ + ((110000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) //!Firmware max timeout value is 100 seconds +#define RSI_AP_CONFIG_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_FWUP_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_MTYPE_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WP_LOAD_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_JSON_LOAD_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WP_ERASE_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_JSON_ERASE_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WP_CLEAR_ALL_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_CONNECT_RESPONSE_WAIT_TIME ((10000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WPS_RESPONSE_WAIT_TIME ((180000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_FREQ_OFFSET_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_CALIB_WRITE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SMTP_RESPONSE_WAIT_TIME ((60000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_DNS_SERVER_ADD_RESPONSE_WAIT_TIME ((150000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_FTP_RESPONSE_WAIT_TIME ((120000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_OTA_FWUP_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_CRYPTO_RESPONSE_WAIT_TIME ((2000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SOCKET_CREATE_RESPONSE_WAIT_TIME ((100000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_CERT_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SCAN_WITH_BITMAP_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_DNS_QUERY_RESPONSE_WAIT_TIME ((150000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_DNS_UPDATE_RESPONSE_WAIT_TIME ((150000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_HOST_WP_SEND_RESPONSE_WAIT_TIME ((200000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_POP3_RESPONSE_WAIT_TIME ((60000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_HTTP_ABORT_RESPONSE_WAIT_TIME \ + ((100000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) //!Firmware max timeout value is 100 seconds +#define RSI_HTTP_CLIENT_PUT_RESPONSE_WAIT_TIME \ + ((100000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) //!Firmware max timeout value is 100 seconds +#define RSI_SNTP_RESPONSE_WAIT_TIME ((100000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_EMB_MQTT_RESPONSE_WAIT_TIME ((60000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_PSK_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SOCKET_CLOSE_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_11AX_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_TWT_RESPONSE_WAIT_TIME ((5000 * WIFI_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) + +// WIFI BLOCKED timeout defines +#define RSI_ACCEPT_RESPONSE_WAIT_TIME (RSI_WAIT_FOREVER * WIFI_BLOCKED_TIMEOUT_SF) +#define RSI_SELECT_RESPONSE_WAIT_TIME ((RSI_WAIT_FOREVER * WIFI_BLOCKED_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_SOCKET_RECVFROM_RESPONSE_WAIT_TIME ((RSI_WAIT_FOREVER * WIFI_BLOCKED_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_GPIO_WAIT_TIME 10000 +#define RSI_RX_EVENT_WAIT_TIME DEFAULT_TIMEOUT +#define RSI_COMMON_SEND_CMD_RESPONSE_WAIT_TIME ((250000 * WIFI_BLOCKED_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_WLAN_SEND_CMD_RESPONSE_WAIT_TIME ((250000 * WIFI_BLOCKED_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_NWK_SEND_CMD_RESPONSE_WAIT_TIME ((250000 * WIFI_BLOCKED_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_GPIO_CONFIG_RESP_WAIT_TIME ((100 * WIFI_INTERNAL_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) + +//BT/BLE command timeouts in ms +#define RSI_BT_COMMON_CMD_RESP_WAIT_TIME ((500 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BT_A2DP_CMD_RESP_WAIT_TIME ((500 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BT_A2DP_DATA_CMD_RESP_WAIT_TIME ((2000 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BT_AVRCP_CMD_RESP_WAIT_TIME ((200 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BT_HFP_CMD_RESP_WAIT_TIME ((500 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BT_PBAP_CMD_RESP_WAIT_TIME ((500 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BT_HID_CMD_RESP_WAIT_TIME ((500 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BT_SPP_CMD_RESP_WAIT_TIME ((500 * BT_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) + +#define RSI_BLE_GAP_CMD_RESP_WAIT_TIME ((500 * BLE_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) +#define RSI_BLE_GATT_CMD_RESP_WAIT_TIME ((200 * BLE_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) + +#define RSI_BT_BLE_CMD_MAX_RESP_WAIT_TIME ((2000 * BT_COMMON_WAIT_TIMEOUT_SF) + (DEFAULT_TIMEOUT)) + +// Module type +typedef enum { + RSI_MODULE_TYPE_Q7 = 1, + RSI_MODULE_TYPE_SB = 4, + RSI_MODULE_TYPE_M7DB = 5, + RSI_MODULE_TYPE_M4SB = 6, + RSI_MODULE_TYPE_WMS = 10 +} module_type; + +//Antenna Output power in dBm +#define RSI_MIN_OUTPUT_POWER_IN_DBM -8 +#define RSI_MAX_OUTPUT_POWER_IN_DBM 15 + +/******************************************************/ + +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +// enumeration for states used in initial control block in driver +typedef enum rsi_device_state_e { + RSI_DEVICE_STATE_NONE = 0, + RSI_DRIVER_INIT_DONE, + RSI_DEVICE_INIT_DONE +} rsi_device_state_t; + +#define RSI_DMA_VALID 0 +#define RSI_SKIP_DMA_VALID 1 +//#define DEBUGOUT(...) + +#define BT_CMD 6 + +/****************************************************** + * * Type Definitions + * ******************************************************/ + +/****************************************************** + * * Structures + * ******************************************************/ + +// driver control block structure + +/** + * @brief Structure representing the driver control block. + * + * This structure is used to define the parameters for the driver control block, + * including endianness, global Bluetooth callback, common Bluetooth callback, + * BLE callback, and device state. + */ +typedef struct rsi_driver_cb_s { + /** Endianness */ + uint8_t endian; + + /** Global Bluetooth callback */ + rsi_bt_global_cb_t *bt_global_cb; + /** Common Bluetooth callback */ + rsi_bt_cb_t *bt_common_cb; + /** BLE callback */ + rsi_bt_cb_t *ble_cb; + +#if defined(SL_SI91X_PRINT_DBG_LOG) + /** Mutex for debug prints */ + osMutexId_t debug_prints_mutex; +#endif + + /** Device state */ + volatile rsi_device_state_t device_state; +} rsi_driver_cb_t; + +extern rsi_driver_cb_t *rsi_driver_cb; + +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_common_apis.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_common_apis.h new file mode 100644 index 000000000..b1d20c636 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_common_apis.h @@ -0,0 +1,131 @@ +/******************************************************************************* + * @file rsi_common_apis.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_COMMON_APIS_H +#define RSI_COMMON_APIS_H + +#if defined(SL_SI91X_PRINT_DBG_LOG) +#include +#include "rsi_common.h" +#endif +/****************************************************** + * * Macros + * ******************************************************/ +#if !(defined(FRDM_K28F) || defined(MXRT_595s)) +#if defined(SL_SI91X_PRINT_DBG_LOG) +#define LOG_PRINT(...) \ + { \ + osMutexAcquire(rsi_driver_cb->debug_prints_mutex, 0xFFFFFFFFUL); \ + printf(__VA_ARGS__); \ + osMutexRelease(rsi_driver_cb->debug_prints_mutex); \ + } +#elif defined(DEBUGOUT) +#define LOG_PRINT(...) DEBUGOUT(__VA_ARGS__) +#else +#define LOG_PRINT(...) +#endif +#endif + +// success return value +#define RSI_SUCCESS 0 + +// failure return value +#define RSI_FAILURE -1 + +// Feature not supported +#define RSI_FEATURE_NOT_SUPPORTED 0x00F7 + +//Load Image types +#define LOAD_NWP_FW '1' +#define LOAD_DEFAULT_NWP_FW_ACTIVE_LOW 0x71 + +// Upgrade images +#define BURN_NWP_FW 'B' + +// Upgrade images +#define RSI_JUMP_TO_PC 'J' + +#define RSI_ACTIVE_LOW_INTR 0x2 +#define RSI_ACTIVE_HIGH_INTR 0x0 +#define RSI_RX_BUFFER_CHECK 0x15 +// TX buffer full macro +#define RSI_TX_BUFFER_FULL -2 +#define RSI_SOFT_RESET 0 +#define RSI_HARD_RESET 1 + +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +// enumerations for power save profile modes +typedef enum rsi_power_save_profile_mode_e { + RSI_ACTIVE = 0, + RSI_SLEEP_MODE_1 = 1, + RSI_SLEEP_MODE_2 = 2, + RSI_SLEEP_MODE_8 = 8, + RSI_SLEEP_MODE_10 = 10, +} rsi_power_save_profile_mode_t; + +// enumerations for power save profile types +typedef enum rsi_power_save_profile_type_e { + RSI_MAX_PSP = 0, + RSI_FAST_PSP = 1, + RSI_UAPSD = 2 +} rsi_power_save_profile_type_t; + +/****************************************************** + * * Type Definitions + * ******************************************************/ +/****************************************************** + * * Structures + * ******************************************************/ +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +#include +extern int32_t rsi_ble_driver_init(uint8_t *buffer, uint32_t length); +extern int32_t rsi_ble_driver_deinit(void); +extern int32_t rsi_get_fw_version(uint8_t *response, uint16_t length); +extern int32_t rsi_get_module_type(uint8_t *response); +extern int32_t rsi_common_debug_log(int32_t assertion_type, int32_t assertion_level); +extern int32_t rsi_get_ram_log(uint32_t addr, uint32_t length); +extern int32_t rsi_driver_version(uint8_t *request); + +/** + * @brief Wait for BT card ready + * @return void + * */ +void rsi_bt_common_init(void); + +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_user.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_user.h new file mode 100644 index 000000000..0dbcfc525 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_user.h @@ -0,0 +1,70 @@ +/******************************************************************************* + * @file rsi_user.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_USER_H +#define RSI_USER_H +/****************************************************** + * * Macros + * ******************************************************/ + +// Silicon Version 1.3 +#define CHIP_VER_1P3 0 + +// Silicon Version 1.4 and above +#define CHIP_VER_1P4_AND_ABOVE 1 + +// To selcet Silicon version, select either of one from among two macros +#define RS9116_SILICON_CHIP_VER \ + CHIP_VER_1P4_AND_ABOVE // Set 1 for Silicon Chip Version 1p4 and Above, 0 for Silicon Chip Version 1p3 + +#define TX_WAIT_TIME 0 + +#define BT_WAIT_TIMEOUT_SF 1 +#define BLE_WAIT_TIMEOUT_SF 1 +#define BT_COMMON_WAIT_TIMEOUT_SF 1 + +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +/****************************************************** + * * Type Definitions + * ******************************************************/ +/****************************************************** + * * Structures + * ******************************************************/ +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h new file mode 100644 index 000000000..f2e6be573 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/rsi_utils.h @@ -0,0 +1,85 @@ +/******************************************************************************* + * @file rsi_utils.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RSI_UTILS_H +#define RSI_UTILS_H + +#include +/****************************************************** + * * Macros + * ******************************************************/ +#ifndef BIT +#define BIT(a) ((uint32_t)1U << a) +#endif + +//#define RSI_MIN(x, y) ((x) > (y) ? (y) : (x)) //This statement is modified to avoid compilation warning +#define RSI_MIN(x, y) ((int32_t)(x) > (int32_t)(y) ? (int32_t)(y) : (int32_t)(x)) + +#ifndef NULL +#define NULL 0 +#endif + +/****************************************************** + * * Constants + * ******************************************************/ +/****************************************************** + * * Enumerations + * ******************************************************/ +/****************************************************** + * * Type Definitions + * ******************************************************/ +/****************************************************** + * * Structures + * ******************************************************/ +/****************************************************** + * * Global Variables + * ******************************************************/ +/****************************************************** + * * Function Declarations + * ******************************************************/ +void rsi_uint32_to_4bytes(uint8_t *dBuf, uint32_t val); +void rsi_uint16_to_2bytes(uint8_t *dBuf, uint16_t val); +uint16_t rsi_bytes2R_to_uint16(const uint8_t *dBuf); +uint32_t rsi_bytes4R_to_uint32(const uint8_t *dBuf); +uint8_t *rsi_ascii_dev_address_to_6bytes_rev(uint8_t *hex_addr, int8_t *ascii_mac_address); +uint8_t *rsi_6byte_dev_address_to_ascii(uint8_t *ascii_mac_address, const uint8_t *hex_addr); +uint8_t convert_lower_case_to_upper_case(uint8_t lwrcase); +void string2array(uint8_t *dst, const uint8_t *src, uint32_t length); +int32_t rsi_atoi(const int8_t *str); +void rsi_ascii_dot_address_to_4bytes(uint8_t *hexAddr, int8_t *asciiDotAddress); +void rsi_ascii_mac_address_to_6bytes(uint8_t *hexAddr, int8_t *asciiMacAddress); + +int8_t rsi_ascii_hex2num(int8_t ascii_hex_in); +int8_t rsi_char_hex2dec(int8_t *cBuf); +int8_t hex_to_ascii(uint8_t hex_num); +uint8_t *rsi_itoa(uint32_t val, uint8_t *str); +int8_t asciihex_2_num(int8_t ascii_hex_in); +int8_t rsi_charhex_2_dec(int8_t *cBuf); +uint32_t rsi_ntohl(uint32_t a); +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/sl_si91x_ble.h b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/sl_si91x_ble.h new file mode 100644 index 000000000..77cf71ed5 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/inc/sl_si91x_ble.h @@ -0,0 +1,55 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_wifi_device.h" + +/***************************************************************************/ /** + * @brief + * Sets BT performance profile + * @param[in] profile + * BT performance profile as indicated by sl_bt_performance_profile_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_bt_set_performance_profile(const sl_bt_performance_profile_t *profile); + +/***************************************************************************/ /** + * @brief + * Gets BT performance profile + * @param[out] profile + * BT performance profile as indicated by sl_bt_performance_profile_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_bt_get_performance_profile(sl_bt_performance_profile_t *profile); + +sl_status_t sl_si91x_bt_get_performance_profile(sl_bt_performance_profile_t *profile); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c b/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c new file mode 100644 index 000000000..e02fa9522 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c @@ -0,0 +1,2252 @@ +/******************************************************************************* + * @file rsi_bt_ble.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "rsi_bt_common_config.h" + +#include "rsi_common.h" +#include "cmsis_os2.h" + +#include "sl_wifi_host_interface.h" +#include "sl_si91x_driver.h" + +#include "rsi_bt_common.h" +#include "rsi_ble.h" +#include "stdio.h" + +#include "sl_si91x_host_interface.h" + +sl_status_t sli_si91x_allocate_command_buffer(sl_wifi_buffer_t **host_buffer, + void **buffer, + uint32_t requested_buffer_size, + uint32_t wait_duration_ms); +uint32_t rsi_get_bt_state(const rsi_bt_cb_t *bt_cb); + +#define BT_SEM 0x1 +#define BT_CMD_SEM 0x2 + +/* + * Global Variables + * */ + +// rsi_bt_ble.c function declarations +void rsi_bt_common_register_callbacks(rsi_bt_get_ber_pkt_t rsi_bt_get_ber_pkt_from_app); +uint32_t rsi_bt_get_timeout(uint16_t cmd_type, uint16_t protocol_type); +uint32_t rsi_bt_get_status(const rsi_bt_cb_t *bt_cb); +void rsi_ble_update_le_dev_buf(const rsi_ble_event_le_dev_buf_ind_t *rsi_ble_event_le_dev_buf_ind); +void rsi_add_remote_ble_dev_info(const rsi_ble_event_enhance_conn_status_t *remote_dev_info); +void rsi_remove_remote_ble_dev_info(const rsi_ble_event_disconnect_t *remote_dev_info); +int32_t rsi_driver_process_bt_resp( + rsi_bt_cb_t *bt_cb, + sl_si91x_packet_t *pkt, + void (*rsi_bt_async_callback_handler)(rsi_bt_cb_t *cb, uint16_t type, uint8_t *data, uint16_t length), + uint16_t protocol_type); +void rsi_ble_on_chip_memory_status_callbacks_register(chip_ble_buffers_stats_handler_t ble_on_chip_memory_status_event); +uint16_t rsi_bt_prepare_common_pkt(uint16_t cmd_type, void *cmd_struct, sl_si91x_packet_t *pkt); +uint16_t rsi_bt_prepare_le_pkt(uint16_t cmd_type, void *cmd_struct, sl_si91x_packet_t *pkt); + +/* + Global Variables + */ +/** @addtogroup DRIVER14 +* @{ +*/ +/** + * @brief Register the bt-common callbacks + * @param[in] rsi_bt_get_ber_pkt_from_app - BER Call back + * @return void + * + * + */ + +void rsi_bt_common_register_callbacks(rsi_bt_get_ber_pkt_t rsi_bt_get_ber_pkt_from_app) +{ + // Get bt cb struct pointer + rsi_bt_common_specific_cb_t *bt_common_specific_cb = rsi_driver_cb->bt_global_cb->bt_common_specific_cb; + + // Assign the call backs to the respective call back + bt_common_specific_cb->rsi_bt_get_ber_pkt = rsi_bt_get_ber_pkt_from_app; +} + +/** + * @brief Determine the BT protocol (BT COMMON / BT classic / BLE ) using the packet type + * @param[in] rsp_type - Packet type + * @param[in] bt_cb - BT control back + * @return 0 - Success \n + * Non-Zero Value - Failure + * + * + */ + +uint16_t rsi_bt_get_proto_type(uint16_t rsp_type, rsi_bt_cb_t **bt_cb) +{ + SL_PRINTF(SL_RSI_BT_GET_PROTO_TYPE_TRIGGER, BLUETOOTH, LOG_INFO, "RESPONSE_TYPE: %2x", rsp_type); + uint16_t return_value = 0xFF; + + if (rsp_type == RSI_BLE_EVENT_DISCONNECT) { + if (rsi_driver_cb->bt_common_cb->dev_type == RSI_BT_LE_DEVICE) { + return_value = RSI_PROTO_BLE; + *bt_cb = rsi_driver_cb->ble_cb; + } + + return return_value; + } + /** @} */ + // Determine the protocol type by looking at the packet type + if ((rsp_type == RSI_BT_EVENT_CARD_READY) + || ((rsp_type >= RSI_BT_SET_LOCAL_NAME) && (rsp_type <= RSI_BT_GET_LOCAL_DEV_ADDR)) + || ((rsp_type >= RSI_BT_REQ_INIT) && (rsp_type <= RSI_BT_SET_ANTENNA_SELECT)) + || (rsp_type == RSI_BT_SET_FEATURES_BITMAP) || (rsp_type == RSI_BT_SET_ANTENNA_TX_POWER_LEVEL) + || (rsp_type == RSI_BT_SET_BD_ADDR_REQ) || (rsp_type == RSI_BLE_ONLY_OPER_MODE) + || (rsp_type == RSI_BLE_REQ_PWRMODE) || (rsp_type == RSI_BLE_REQ_SOFTRESET) || (rsp_type == RSI_BT_REQ_PER_CMD) + || (rsp_type == RSI_BT_VENDOR_SPECIFIC) || (rsp_type == RSI_BT_GET_BT_STACK_VERSION) + || (rsp_type == RSI_BT_SET_GAIN_TABLE_OFFSET_OR_MAX_POWER_UPDATE)) { + return_value = RSI_PROTO_BT_COMMON; + *bt_cb = rsi_driver_cb->bt_common_cb; + } else if (((rsp_type >= RSI_BLE_REQ_ADV) && (rsp_type <= RSI_BLE_REQ_EXECUTE_WRITE)) + || ((rsp_type >= RSI_BLE_ADD_SERVICE) && (rsp_type <= RSI_BLE_CMD_INDICATE)) + || (rsp_type == RSI_BLE_SET_ADVERTISE_DATA) + || ((rsp_type >= RSI_BLE_GET_LE_PING) && (rsp_type <= RSI_BLE_CMD_READ_RESP)) + || (rsp_type == RSI_BLE_SET_SCAN_RESPONSE_DATA) + || ((rsp_type >= RSI_BLE_LE_ACCEPT_LIST) && (rsp_type <= RSI_BLE_CBFC_DISCONN)) + || ((rsp_type >= RSI_BLE_LE_LTK_REQ_REPLY) && (rsp_type <= RSI_BLE_PER_RX_MODE)) + || (rsp_type == RSI_BLE_CMD_ATT_ERROR) || (rsp_type == RSI_BLE_CMD_SET_BLE_TX_POWER) + || (rsp_type == RSI_BLE_CMD_INDICATE_SYNC) || (rsp_type == RSI_BLE_CMD_AE) + || ((rsp_type >= RSI_BLE_REQ_PROFILES_ASYNC) && (rsp_type <= RSI_BLE_EXECUTE_LONGDESCWRITE_ASYNC)) + || (rsp_type == RSI_BLE_SET_SMP_PAIRING_CAPABILITY_DATA) || (rsp_type == RSI_BLE_REQ_SMP_PAIRING_FAILED) + || (rsp_type == RSI_BLE_REQ_HCI_RAW) || (rsp_type == RSI_BLE_EVENT_RCP_DATA_RCVD) + || ((rsp_type >= RSI_BLE_CONN_PARAM_RESP_CMD) && (rsp_type <= RSI_BLE_CMD_MTU_EXCHANGE_RESP)) + || ((rsp_type >= RSI_BLE_EVENT_GATT_ERROR_RESPONSE) && (rsp_type <= RSI_BLE_EVENT_SCAN_REQ_RECVD)) + || (rsp_type == RSI_BLE_REQ_CONN_ENHANCE) || (rsp_type == RSI_BLE_EVENT_REMOTE_DEVICE_INFORMATION) + || ((rsp_type >= RSI_BLE_CMD_READ_TRANSMIT_POWER) && (rsp_type <= RSI_BLE_CMD_WRITE_RF_PATH_COMP))) { + + return_value = RSI_PROTO_BLE; + *bt_cb = rsi_driver_cb->ble_cb; + } + + return return_value; +} +/** @addtogroup DRIVER14 +* @{ +*/ + +/** + * @brief Calculate semaphore wait time for a protocol (BT COMMON / BT classic / BLE ) + * using the packet type + * @param[in] cmd_type - Command Type + * @param[in] protocol_type - Protocol type , whether it is BT Common/BT Classic/BLE + * @return 0 - Success \n + * Non-Zero Value - Failure + * + * + */ + +uint32_t rsi_bt_get_timeout(uint16_t cmd_type, uint16_t protocol_type) +{ + + SL_PRINTF(SL_RSI_BT_GET_TIMEOUT_TRIGGER, + BLUETOOTH, + LOG_INFO, + "COMMAND_TYPE: %2x, PROTOCOL_TYPE: %2x", + cmd_type, + protocol_type); + uint32_t return_value = 0; // 0 means RSI_WAIT_FOREVER + + switch (protocol_type) { + case RSI_PROTO_BT_COMMON: { + return_value = RSI_BT_COMMON_CMD_RESP_WAIT_TIME; + } break; + case RSI_PROTO_BLE: { + if (((cmd_type >= RSI_BLE_REQ_ADV) && (cmd_type <= RSI_BLE_SMP_PASSKEY)) + || ((cmd_type >= RSI_BLE_SET_ADVERTISE_DATA) && (cmd_type <= RSI_BLE_PER_RX_MODE)) + || (cmd_type == RSI_BLE_CONN_PARAM_RESP_CMD) + || ((cmd_type == RSI_BLE_MTU_EXCHANGE_REQUEST) || (cmd_type == RSI_BLE_CMD_MTU_EXCHANGE_RESP))) { + return_value = RSI_BLE_GAP_CMD_RESP_WAIT_TIME; + } else if (((cmd_type >= RSI_BLE_REQ_PROFILES) && (cmd_type <= RSI_BLE_CMD_INDICATE)) + || ((cmd_type >= RSI_BLE_CMD_ATT_ERROR) && (cmd_type <= RSI_BLE_SET_SMP_PAIRING_CAPABILITY_DATA)) + || (cmd_type == RSI_BLE_CMD_INDICATE_CONFIRMATION) || (cmd_type == RSI_BLE_CMD_INDICATE_SYNC)) { + return_value = RSI_BLE_GATT_CMD_RESP_WAIT_TIME; + } else { + return_value = RSI_BT_BLE_CMD_MAX_RESP_WAIT_TIME; + } + } break; + + default: { + return_value = RSI_BT_BLE_CMD_MAX_RESP_WAIT_TIME; + } break; + } + return return_value; +} + +/** + * @brief Handle BT data transfer completion. + * @param[in] pkt - Pointer to packet + * @return void + */ + +void rsi_bt_common_tx_done(sl_si91x_packet_t *pkt) +{ + + SL_PRINTF(SL_RSI_BT_COMMON_TX_DONE, BLUETOOTH, LOG_INFO); + const uint8_t *host_desc = NULL; + uint8_t protocol_type = 0; + uint16_t rsp_type = 0; + rsi_bt_cb_t *bt_cb = NULL; + + // Get Host Descriptor + host_desc = pkt->desc; + + // Get Command response Type + rsp_type = rsi_bytes2R_to_uint16(host_desc + RSI_BT_RSP_TYPE_OFFSET); + + // Get the protocol Type + protocol_type = (uint8_t)rsi_bt_get_proto_type(rsp_type, &bt_cb); + + if (protocol_type == 0xFF) { + return; + } + + // If the command is not a synchronous/blocking one + if (!bt_cb->sync_rsp) { + // Set bt_common status as success + rsi_bt_set_status(bt_cb, RSI_SUCCESS); + + // Post the semaphore which is waiting on driver_send API + osSemaphoreRelease(bt_cb->bt_sem); + } +} +/** @} */ +/** @addtogroup DRIVER14 +* @{ +*/ +/** + * + * @brief Return BT status + * @param[in] bt_cb - BT control block + * @return 0 - Success \n + * Non-Zero Value - Failure + */ + +uint32_t rsi_get_bt_state(const rsi_bt_cb_t *bt_cb) +{ + SL_PRINTF(SL_RSI_BT_STATE_TRIGGER, BLUETOOTH, LOG_INFO); + return bt_cb->state; +} + +/*==============================================*/ +/** + * @brief Set BT status + * @param[in] bt_cb - BT control block + * @param[in] status - Status value to be set + * @param[out] None + * @return void + */ + +void rsi_bt_set_status(rsi_bt_cb_t *bt_cb, int32_t status) +{ + + SL_PRINTF(SL_RSI_BT_SET_STATUS_TRIGGER, BLUETOOTH, LOG_INFO, "STATUS: %4x", status); + bt_cb->status = status; +} + +/*==============================================*/ +/** + * @brief Get bt status + * @param[in] bt_cb - BT control block + * @return 0 - Success \n + * Non-Zero Value - Failure + */ +uint32_t rsi_bt_get_status(const rsi_bt_cb_t *bt_cb) +{ + return bt_cb->status; +} + +/** + * @brief Update local Device buffer availability per peripheral in global ble cb structure + * @param[in] void + * @return void + * + */ + +void rsi_ble_update_le_dev_buf(const rsi_ble_event_le_dev_buf_ind_t *rsi_ble_event_le_dev_buf_ind) +{ + + SL_PRINTF(SL_RSI_BT_UPDATE_LE_DEV_BUF_TRIGGER, BLUETOOTH, LOG_INFO); + rsi_bt_cb_t *le_cb = rsi_driver_cb->ble_cb; + + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + if (!memcmp(rsi_ble_event_le_dev_buf_ind->remote_dev_bd_addr, + le_cb->remote_ble_info[inx].remote_dev_bd_addr, + RSI_DEV_ADDR_LEN)) { + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexAcquire(le_cb->remote_ble_info[inx].ble_buff_mutex, 0xFFFFFFFFUL); + } + + le_cb->remote_ble_info[inx].avail_buf_cnt += rsi_ble_event_le_dev_buf_ind->avail_buf_cnt; + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexRelease(le_cb->remote_ble_info[inx].ble_buff_mutex); + } + break; + } + } +} + +/** + * @brief Update Remote BLE Device info in global ble cb structure + * @param[in] void + * @return void + * + * + */ + +void rsi_add_remote_ble_dev_info(const rsi_ble_event_enhance_conn_status_t *remote_dev_info) +{ + + SL_PRINTF(SL_RSI_ADD_REMOTE_BLE_DEV_INFO_TRIGGER, BLUETOOTH, LOG_INFO); + rsi_bt_cb_t *le_cb = rsi_driver_cb->ble_cb; + + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + if (!le_cb->remote_ble_info[inx].used) { + memcpy(le_cb->remote_ble_info[inx].remote_dev_bd_addr, remote_dev_info->dev_addr, RSI_DEV_ADDR_LEN); + le_cb->remote_ble_info[inx].used = 1; + /* On connection default values are set as follows*/ + le_cb->remote_ble_info[inx].max_buf_cnt = 1; + le_cb->remote_ble_info[inx].avail_buf_cnt = 1; + le_cb->remote_ble_info[inx].mode = 1; + le_cb->remote_ble_info[inx].ble_buff_mutex = osMutexNew(NULL); + break; + } + } +} + +/** + * @brief Remove Remote BLE Device info in global ble cb structure + * @param[in] remote_dev_info - Remote device information + * @return void + * + * + */ + +void rsi_remove_remote_ble_dev_info(const rsi_ble_event_disconnect_t *remote_dev_info) +{ + + SL_PRINTF(SL_RSI_REMOVE_REMOTE_BLE_DEV_INFO_TRIGGER, BLUETOOTH, LOG_INFO); + rsi_bt_cb_t *le_cb = rsi_driver_cb->ble_cb; + + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + if (!memcmp(remote_dev_info->dev_addr, le_cb->remote_ble_info[inx].remote_dev_bd_addr, RSI_DEV_ADDR_LEN)) { + memset(le_cb->remote_ble_info[inx].remote_dev_bd_addr, 0, RSI_DEV_ADDR_LEN); + le_cb->remote_ble_info[inx].used = 0; + le_cb->remote_ble_info[inx].avail_buf_cnt = 0; + le_cb->remote_ble_info[inx].cmd_in_use = 0; + le_cb->remote_ble_info[inx].max_buf_cnt = 0; + le_cb->remote_ble_info[inx].expected_resp = 0; + le_cb->remote_ble_info[inx].mode = 0; + le_cb->remote_ble_info[inx].remote_dev_addr_type = 0; + le_cb->remote_ble_info[inx].max_buf_len = 0; + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexDelete(le_cb->remote_ble_info[inx].ble_buff_mutex); + } + break; + } + } +} + +/** + * @brief Process BT RX packets + * @param[in ] bt_cb - BT control block + * @param[in] pkt - Pointer to received RX packet + * @param[in] bt_aync_callback_handler + * @return 0 - Success \n + * Non-Zero Value - Failure + * + */ + +int32_t rsi_driver_process_bt_resp( + rsi_bt_cb_t *bt_cb, + sl_si91x_packet_t *pkt, + void (*rsi_bt_async_callback_handler)(rsi_bt_cb_t *cb, uint16_t type, uint8_t *data, uint16_t length), + uint16_t protocol_type) +{ + UNUSED_PARAMETER(protocol_type); + + SL_PRINTF(SL_RSI_DRIVER_PROCESS_BT_RESPONSE_TRIGGER, BLUETOOTH, LOG_INFO, "PROTOCOL_TYPE: %2x", protocol_type); + uint16_t rsp_type = 0; + int16_t status = RSI_SUCCESS; + const uint8_t *host_desc = NULL; + uint8_t *payload; + uint16_t payload_length; + uint16_t expected_resp = 0; + + // Get Host Descriptor + host_desc = pkt->desc; + + // Get Command response Type + rsp_type = rsi_bytes2R_to_uint16(host_desc + RSI_BT_RSP_TYPE_OFFSET); + + // Get Payload start pointer + payload = pkt->data; + + // Get Payload length + payload_length = (rsi_bytes2R_to_uint16(host_desc) & 0xFFF); + + // Get Status + status = rsi_bytes2R_to_uint16(host_desc + RSI_BT_STATUS_OFFSET); + + // Check bt_cb for any task is waiting for response + if (bt_cb->expected_response_type == rsp_type) { + // Update the status in bt_cb + rsi_bt_set_status(bt_cb, status); + if (bt_cb->expected_response_type == RSI_BT_EVENT_CARD_READY) { + bt_cb->state = RSI_BT_STATE_OPERMODE_DONE; + } + + //To not allow BT SetAddress after these states are triggered + if ((status == RSI_SUCCESS) + && (bt_cb->expected_response_type == RSI_BLE_REQ_ADV || bt_cb->expected_response_type == RSI_BLE_REQ_SCAN + || bt_cb->expected_response_type == RSI_BLE_REQ_CONN)) { + rsi_driver_cb->bt_common_cb->state = RSI_BT_STATE_NONE; + } + expected_resp = bt_cb->expected_response_type; + // Clear expected response type + bt_cb->expected_response_type = 0; + + // Copy the expected response to response structure/buffer, if any, passed in API + if (bt_cb->expected_response_buffer != NULL) { + memcpy(bt_cb->expected_response_buffer, payload, payload_length); + + // Save expected_response pointer to a local variable, since it is being cleared below + payload = bt_cb->expected_response_buffer; + + // Clear the expected response pointer + bt_cb->expected_response_buffer = NULL; + } + + // Check if it is sync response + if (bt_cb->sync_rsp) { + + /* handling this for the new buf configuration */ + if ((expected_resp == RSI_BLE_RSP_SET_WWO_RESP_NOTIFY_BUF_INFO) && (status == RSI_SUCCESS)) { + const rsi_ble_set_wo_resp_notify_buf_info_t *buf_info = (rsi_ble_set_wo_resp_notify_buf_info_t *)payload; + + bt_cb->remote_ble_info[bt_cb->remote_ble_index].mode = buf_info->buf_mode; + + if (buf_info->buf_mode == 0) /* small buf cnt */ + { + bt_cb->remote_ble_info[bt_cb->remote_ble_index].max_buf_cnt = (buf_info->buf_count * 10); + bt_cb->remote_ble_info[bt_cb->remote_ble_index].avail_buf_cnt = (buf_info->buf_count * 10); + } else /* big buf cnt */ + { + bt_cb->remote_ble_info[bt_cb->remote_ble_index].max_buf_cnt = buf_info->buf_count; + bt_cb->remote_ble_info[bt_cb->remote_ble_index].avail_buf_cnt = buf_info->buf_count; + } + bt_cb->remote_ble_index = 0; /* assigning value to 0 after successful response */ + } + // Signal the bt semaphore + osSemaphoreRelease(bt_cb->bt_sem); + } else if (rsi_bt_async_callback_handler != NULL) { + + bt_cb->async_status = status; + // Call callbacks handler + rsi_bt_async_callback_handler(bt_cb, rsp_type, payload, payload_length); + } + } else if (rsi_bt_async_callback_handler != NULL) { + bt_cb->async_status = status; + // Call callbacks handler + rsi_bt_async_callback_handler(bt_cb, rsp_type, payload, payload_length); + } + + return status; +} + +/** + * @brief Process BT RX packets + * @param[in] pkt - Pointer to received RX packet + * @return 0 - Success \n + * Non-Zero Value - Failure + */ + +uint16_t rsi_driver_process_bt_resp_handler(void *rx_pkt) +{ + + SL_PRINTF(SL_RSI_DRIVER_PROCESS_BT_RESP_HANDLER_TRIGGER, BLUETOOTH, LOG_INFO); + sl_si91x_packet_t *pkt = (sl_si91x_packet_t *)rx_pkt; + const uint8_t *host_desc = NULL; + uint8_t protocol_type = 0; + uint16_t rsp_type = 0; + int16_t status = RSI_SUCCESS; + rsi_bt_cb_t *bt_cb = NULL; + const rsi_ble_event_disconnect_t *temp_data = NULL; + + // Get Host Descriptor + host_desc = pkt->desc; + + // Get Command response Type + rsp_type = rsi_bytes2R_to_uint16(host_desc + RSI_BT_RSP_TYPE_OFFSET); + + if (rsp_type == RSI_BLE_EVENT_DISCONNECT) { + + // rsi_driver_cb->bt_common_cb->dev_type = ((rsi_ble_event_disconnect_t *)pkt->data)->dev_type; + temp_data = (rsi_ble_event_disconnect_t *)pkt->data; + rsi_driver_cb->bt_common_cb->dev_type = + ((temp_data->dev_type) & LOWERNIBBLE); //Getting the dev_type from lower nibble + } + + // Get the protocol Type + protocol_type = (uint8_t)rsi_bt_get_proto_type(rsp_type, &bt_cb); + + SL_PRINTF(SL_RSI_BT_DRIVER_PROCESS_BT_RESP_HANDLER_TRIGGER, BLUETOOTH, LOG_INFO, "PROTOCOL_TYPE: %1x", protocol_type); + if (protocol_type == 0xFF) { + return 0; + } + // Call the corresponding protocol process rsp handler + if (protocol_type == RSI_PROTO_BT_COMMON) { + // Call BT common process rsp handler + status = (int16_t)rsi_driver_process_bt_resp(bt_cb, pkt, NULL, protocol_type); + } else { + // Call BLE process response handler + status = (int16_t)rsi_driver_process_bt_resp(bt_cb, pkt, rsi_ble_callbacks_handler, protocol_type); + } + return status; +} + +/** + * @brief Initialize bt control block structure + * @param[in] bt_cb - Pointer to bt_cb structure + * @param[in] protocol_type - Protocol type + * @return 0 - Success \n + * Non-Zero Value - Failure + * + */ + +int8_t rsi_bt_cb_init(rsi_bt_cb_t *bt_cb, uint16_t protocol_type) +{ + UNUSED_PARAMETER(protocol_type); + + SL_PRINTF(SL_RSI_BT_CB_INIT_TRIGGER, BLUETOOTH, LOG_INFO, "PROTOCOL_TYPE: %2x", protocol_type); + + int8_t retval = 0; + + // validate input parameter + if (bt_cb == NULL) { + return RSI_ERROR_INVALID_PARAM; + } + + // Initialize bt control block with default values + bt_cb->state = 0; + bt_cb->status = 0; + + // Create bt mutex + bt_cb->expected_response_type = 0; + bt_cb->expected_response_buffer = NULL; + + // Create common/bt/ble sync semaphore + bt_cb->bt_sem = osSemaphoreNew(1, 0, NULL); + if (bt_cb->bt_sem == NULL) { + retval = RSI_ERROR_SEMAPHORE_CREATE_FAILED; + } + + // Create common/bt/ble command semaphore + bt_cb->bt_cmd_sem = osSemaphoreNew(1, 0, NULL); + if (bt_cb->bt_cmd_sem == NULL) { + retval = RSI_ERROR_SEMAPHORE_CREATE_FAILED; + } + + osSemaphoreRelease(bt_cb->bt_cmd_sem); + bt_cb->app_buffer = 0; + + return retval; +} + +/** + * @brief Initialize bt global control block + * @param[in] driver_cb - Pointer to bt_cb structure + * @param[in] buffer - Buffer + * @return 0 - Success \n + * Non-Zero Value - Failure + * + */ +uint16_t rsi_bt_global_cb_init(rsi_driver_cb_t *driver_cb, uint8_t *buffer) +{ + + SL_PRINTF(SL_RSI_BT_GLOBAL_CB_INIT_TRIGGER, BLUETOOTH, LOG_INFO); + rsi_bt_global_cb_t *bt_global_cb = driver_cb->bt_global_cb; + uint16_t total_size = 0; + + bt_global_cb->ble_specific_cb = (rsi_ble_cb_t *)buffer; + + driver_cb->ble_cb->bt_global_cb = bt_global_cb; + total_size += sizeof(rsi_ble_cb_t); + + return total_size; +} +/** @} */ +/** @addtogroup DRIVER14 +* @{ +*/ +/** + * @brief Wait for BT card ready + * @param[in] void + * @return void + * */ + +void rsi_bt_common_init(void) +{ + // Get bt_common_cb structure pointer + rsi_bt_cb_t *bt_common_cb = rsi_driver_cb->bt_common_cb; + + // Save expected response type + bt_common_cb->expected_response_type = RSI_BT_EVENT_CARD_READY; + bt_common_cb->sync_rsp = 1; + + // Wait on BLE semaphore + if (bt_common_cb->bt_sem) { + osSemaphoreAcquire(bt_common_cb->bt_sem, osWaitForever); + } + + // BT card ready is received +} +/** @} */ + +/** @addtogroup BT-LOW-ENERGY7 +* @{ +*/ +/*==============================================*/ +/** + * @brief Register GAP callbacks. + * @param[in] ble_on_adv_report_event - Callback function for Advertise events + * @param[in] ble_on_connect - Callback function for Connect events + * @param[in] ble_on_disconnect - Callback function for Disconnect events + * @param[in] timeout_expired_event - Callback function for le ping timeout events + * @param[in] ble_on_phy_update_complete_event - Callback function for phy update complete events + * @param[in] ble_on_data_length_update_complete_event - Callback function for data length update events + * @param[in] ble_on_enhance_conn_status_event - Callback function for enhanced connection status events + * @param[in] ble_on_directed_adv_report_event - Callback function for directed advertiseing report events + * @param[in] ble_on_conn_update_complete_event - Callback function for conn update complete events + * @param[in] ble_on_remote_conn_params_request_event - Callback function to remote conn params request events + * @return void + */ + +void rsi_ble_gap_register_callbacks(rsi_ble_on_adv_report_event_t ble_on_adv_report_event, + rsi_ble_on_connect_t ble_on_conn_status_event, + rsi_ble_on_disconnect_t ble_on_disconnect_event, + rsi_ble_on_le_ping_payload_timeout_t ble_on_le_ping_time_expired_event, + rsi_ble_on_phy_update_complete_t ble_on_phy_update_complete_event, + rsi_ble_on_data_length_update_t rsi_ble_on_data_length_update_event, + rsi_ble_on_enhance_connect_t ble_on_enhance_conn_status_event, + rsi_ble_on_directed_adv_report_event_t ble_on_directed_adv_report_event, + rsi_ble_on_conn_update_complete_t ble_on_conn_update_complete_event, + rsi_ble_on_remote_conn_params_request_t ble_on_remote_conn_params_request_event) +{ + + SL_PRINTF(SL_RSI_BLE_GAP_REGISTER_CALLBACKS_TRIGGER, BLE, LOG_INFO); + // Get ble cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + // Assign the call backs to the respective call back + ble_specific_cb->ble_on_adv_report_event = ble_on_adv_report_event; + ble_specific_cb->ble_on_conn_status_event = ble_on_conn_status_event; + ble_specific_cb->ble_on_disconnect_event = ble_on_disconnect_event; + ble_specific_cb->ble_on_le_ping_time_expired_event = ble_on_le_ping_time_expired_event; + ble_specific_cb->ble_on_phy_update_complete_event = ble_on_phy_update_complete_event; + ble_specific_cb->rsi_ble_on_data_length_update_event = rsi_ble_on_data_length_update_event; + ble_specific_cb->ble_on_enhance_conn_status_event = ble_on_enhance_conn_status_event; + ble_specific_cb->ble_on_directed_adv_report_event = ble_on_directed_adv_report_event; + ble_specific_cb->ble_on_conn_update_complete_event = ble_on_conn_update_complete_event; + ble_specific_cb->ble_on_remote_conn_params_request_event = ble_on_remote_conn_params_request_event; +} +/*==============================================*/ +/** + * @brief Register GAP Extended responses/events callbacks. + * @pre Device should be initialized before calling this API. + * @param[in] ble_on_remote_features_event - Call back function for Remote feature request + * @param[in] ble_on_le_more_data_req_event - Call back function for LE More data request + * @note For more information about each callback, please refer to GAP Extended callbacks description section. + * @return void + */ + +void rsi_ble_gap_extended_register_callbacks(rsi_ble_on_remote_features_t ble_on_remote_features_event, + rsi_ble_on_le_more_data_req_t ble_on_le_more_data_req_event) +{ + + SL_PRINTF(SL_RSI_BLE_GAP_EXTENDED_REGISTER_CALLBACKS_TRIGGER, BLE, LOG_INFO); + // Get ble cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + // Assign the call backs to the respective call back + ble_specific_cb->ble_on_remote_features_event = ble_on_remote_features_event; + ble_specific_cb->ble_on_le_more_data_req_event = ble_on_le_more_data_req_event; +} +/** @} */ + +/** @addtogroup BT-LOW-ENERGY7 +* @{ +*/ +/** + * @brief Register the SMP callbacks + * @param[in] ble_on_smp_request_event - smp request callback + * @param[in] ble_on_smp_response_event - smp response callback + * @param[in] ble_on_smp_passkey_event - smp passkey callback + * @param[in] ble_on_smp_failed_event - smp failed callback + * @param[in] ble_on_smp_encryptrd - encription enabled callback + * @param[in] ble_on_smp_passkey_display_event - smp passkey display callback + * @param[in] ble_sc_passkey_event - sc passkey display callback + * @param[in] ble_on_le_ltk_req_event - This is the SMP ltk request callback + * @param[in] ble_on_le_security_keys_event - This is the SMP security keys callback + * @param[in] ble_on_sc_method_event - sc method display callback + * @return void + * + */ + +void rsi_ble_smp_register_callbacks(rsi_ble_on_smp_request_t ble_on_smp_request_event, + rsi_ble_on_smp_response_t ble_on_smp_response_event, + rsi_ble_on_smp_passkey_t ble_on_smp_passkey_event, + rsi_ble_on_smp_failed_t ble_on_smp_failed_event, + rsi_ble_on_encrypt_started_t ble_on_smp_encryptrd, + rsi_ble_on_smp_passkey_display_t ble_on_smp_passkey_display_event, + rsi_ble_on_sc_passkey_t ble_sc_passkey_event, + rsi_ble_on_le_ltk_req_event_t ble_on_le_ltk_req_event, + rsi_ble_on_le_security_keys_t ble_on_le_security_keys_event, + rsi_ble_on_smp_response_t ble_on_cli_smp_response_event, + rsi_ble_on_sc_method_t ble_on_sc_method_event) +{ + + SL_PRINTF(SL_RSI_BLE_SMP_REGISTER_CALLBACKS_TRIGGER, BLE, LOG_INFO); + // Get ble cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + // Assign the call backs to the respective call back + ble_specific_cb->ble_on_smp_request_event = ble_on_smp_request_event; + ble_specific_cb->ble_on_smp_response_event = ble_on_smp_response_event; + ble_specific_cb->ble_on_smp_passkey_event = ble_on_smp_passkey_event; + ble_specific_cb->ble_on_smp_fail_event = ble_on_smp_failed_event; + ble_specific_cb->ble_on_smp_encrypt_started = ble_on_smp_encryptrd; + ble_specific_cb->ble_on_smp_passkey_display = ble_on_smp_passkey_display_event; + ble_specific_cb->ble_on_sc_passkey = ble_sc_passkey_event; + ble_specific_cb->ble_on_le_ltk_req_event = ble_on_le_ltk_req_event; + ble_specific_cb->ble_on_le_security_keys_event = ble_on_le_security_keys_event; + ble_specific_cb->ble_on_cli_smp_response_event = ble_on_cli_smp_response_event; + ble_specific_cb->ble_on_sc_method_event = ble_on_sc_method_event; +} + +/** + * @brief Register the GATT callbacks. + * @param[in] rsi_ble_on_profiles_list_resp_t ble_on_profiles_list_resp - Callback for rsi_ble_get_profiles command + * @param[in] rsi_ble_on_profile_resp_t ble_on_profile_resp - Callback for rsi_ble_get_profile command + * @param[in] rsi_ble_on_char_services_resp_t ble_on_char_services_resp - Callback for rsi_ble_get_char_services command + * @param[in] rsi_ble_on_inc_services_resp_t ble_on_inc_services_resp - Callback for rsi_ble_get_inc_services command + * @param[in] rsi_ble_on_att_desc_resp_t ble_on_att_desc_resp - Callback for rsi_ble_get_att_descriptors command + * @param[in] rsi_ble_on_read_resp_t ble_on_read_resp - Callback for all read requests command + * @param[in] rsi_ble_on_write_resp_t ble_on_write_resp - Callback for all write commands + * @param[in] rsi_ble_on_gatt_write_event_t blw_on_gatt_event - Callback for all GATT events + * @param[in] rsi_ble_on_gatt_error_resp_t ble_on_gatt_error_resp_event - Callback for GATT error events + * @param[in] rsi_ble_on_gatt_desc_val_event_t ble_on_gatt_desc_val_resp_event - Callback for GATT descriptor value event + * @param[in] rsi_ble_on_event_profiles_list_t ble_on_profiles_list_event - Callback function for profiles list event + * @param[in] rsi_ble_on_event_profile_by_uuid_t ble_on_profile_by_uuid_event - Callback function for profile event + * @param[in] rsi_ble_on_event_read_by_char_services_t ble_on_read_by_char_services_event- Callback function for char services event + * @param[in] rsi_ble_on_event_read_by_inc_services_t ble_on_read_by_inc_services_event - Callback function for inc services event + * @param[in] rsi_ble_on_event_read_att_value_t ble_on_read_att_value_event - Callback function for read att value event + * @param[in] rsi_ble_on_event_read_resp_t ble_on_read_resp_event - Callback function for read att event + * @param[in] rsi_ble_on_event_write_resp_t ble_on_write_resp_event - Callback function for write event + * @param[in] rsi_ble_on_event_indicate_confirmation_t ble_on_indicate_confirmation_event- Callback function for indicate confirmation event + * @param[in] rsi_ble_on_event_prepare_write_resp_t ble_on_prepare_write_resp_event - Callback function for prepare write event + * @return void + * + */ + +void rsi_ble_gatt_register_callbacks(rsi_ble_on_profiles_list_resp_t ble_on_profiles_list_resp, + rsi_ble_on_profile_resp_t ble_on_profile_resp, + rsi_ble_on_char_services_resp_t ble_on_char_services_resp, + rsi_ble_on_inc_services_resp_t ble_on_inc_services_resp, + rsi_ble_on_att_desc_resp_t ble_on_att_desc_resp, + rsi_ble_on_read_resp_t ble_on_read_resp, + rsi_ble_on_write_resp_t ble_on_write_resp, + rsi_ble_on_gatt_write_event_t ble_on_gatt_event, + rsi_ble_on_gatt_prepare_write_event_t ble_on_gatt_prepare_write_event, + rsi_ble_on_execute_write_event_t ble_on_execute_write_event, + rsi_ble_on_read_req_event_t ble_on_read_req_event, + rsi_ble_on_mtu_event_t ble_on_mtu_event, + rsi_ble_on_gatt_error_resp_t ble_on_gatt_error_resp_event, + rsi_ble_on_gatt_desc_val_event_t ble_on_gatt_desc_val_resp_event, + rsi_ble_on_event_profiles_list_t ble_on_profiles_list_event, + rsi_ble_on_event_profile_by_uuid_t ble_on_profile_by_uuid_event, + rsi_ble_on_event_read_by_char_services_t ble_on_read_by_char_services_event, + rsi_ble_on_event_read_by_inc_services_t ble_on_read_by_inc_services_event, + rsi_ble_on_event_read_att_value_t ble_on_read_att_value_event, + rsi_ble_on_event_read_resp_t ble_on_read_resp_event, + rsi_ble_on_event_write_resp_t ble_on_write_resp_event, + rsi_ble_on_event_indicate_confirmation_t ble_on_indicate_confirmation_event, + rsi_ble_on_event_prepare_write_resp_t ble_on_prepare_write_resp_event) +{ + + SL_PRINTF(SL_RSI_BLE_GATT_REGISTER_CALLBACKS_TRIGGER, BLE, LOG_INFO); + // Get ble specific cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + // Assign the call backs to the respective call back + ble_specific_cb->ble_on_profiles_list_resp = ble_on_profiles_list_resp; + ble_specific_cb->ble_on_profile_resp = ble_on_profile_resp; + ble_specific_cb->ble_on_char_services_resp = ble_on_char_services_resp; + ble_specific_cb->ble_on_inc_services_resp = ble_on_inc_services_resp; + ble_specific_cb->ble_on_att_desc_resp = ble_on_att_desc_resp; + ble_specific_cb->ble_on_read_resp = ble_on_read_resp; + ble_specific_cb->ble_on_write_resp = ble_on_write_resp; + ble_specific_cb->ble_on_gatt_events = ble_on_gatt_event; + ble_specific_cb->ble_on_prepare_write_event = ble_on_gatt_prepare_write_event; + ble_specific_cb->ble_on_execute_write_event = ble_on_execute_write_event; + ble_specific_cb->ble_on_read_req_event = ble_on_read_req_event; + ble_specific_cb->ble_on_mtu_event = ble_on_mtu_event; + ble_specific_cb->ble_on_gatt_error_resp_event = ble_on_gatt_error_resp_event; + ble_specific_cb->ble_on_profiles_list_event = ble_on_profiles_list_event; + ble_specific_cb->ble_on_gatt_desc_val_resp_event = ble_on_gatt_desc_val_resp_event; + ble_specific_cb->ble_on_profile_by_uuid_event = ble_on_profile_by_uuid_event; + ble_specific_cb->ble_on_read_by_char_services_event = ble_on_read_by_char_services_event; + ble_specific_cb->ble_on_read_by_inc_services_event = ble_on_read_by_inc_services_event; + ble_specific_cb->ble_on_read_att_value_event = ble_on_read_att_value_event; + ble_specific_cb->ble_on_read_resp_event = ble_on_read_resp_event; + ble_specific_cb->ble_on_write_resp_event = ble_on_write_resp_event; + ble_specific_cb->ble_on_indicate_confirmation_event = ble_on_indicate_confirmation_event; + ble_specific_cb->ble_on_prepare_write_resp_event = ble_on_prepare_write_resp_event; + + return; +} +/** + * @brief Register the GATT Extended responses/events callbacks. + * @param[in] rsi_ble_on_mtu_exchange_info_t ble_on_mtu_exchange_info_event - Call back function for MTU Exchange information Event + * @return void + * + */ + +void rsi_ble_gatt_extended_register_callbacks(rsi_ble_on_mtu_exchange_info_t ble_on_mtu_exchange_info_event) +{ + // Get ble cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + // Assign the call backs to the respective call back + ble_specific_cb->ble_on_mtu_exchange_info_event = ble_on_mtu_exchange_info_event; +} + +/** + * @fn uint16_t rsi_ble_enhanced_gap_extended_register_callbacks(uint16_t callback_id, void (*callback_handler_ptr)(uint16_t status, + * uint8_t *buffer)) + * @brief Register the BLE call back functions. + * @param[in] callback_id - This is the Id of the call back function following ids are supported: + * @param[in] void (*callback_handler_ptr)(void - This is the Call back handler + * @param[in] status - status of the asynchronous response + * @param[in] buffer - payload of the asynchronous response + * @return 0 - Success \n + * -53 - Failure \n + * If call_back_id is greater than the maximum callbacks to register, returns ref/ RSI_ERROR_BLE_INVALID_CALLBACK_CNT. + * @note In callbacks, application should not initiate any TX operation to the module. + */ +uint32_t rsi_ble_enhanced_gap_extended_register_callbacks(uint16_t callback_id, + void (*callback_handler_ptr)(uint16_t status, + uint8_t *buffer)) +{ + // Get BLE cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + if (callback_id > RSI_BLE_MAX_NUM_GAP_EXT_CALLBACKS) { + + /*Return , if the callback number exceeds the RSI_BT_COMMON_MAX_NUM_EXT_CALLBACKS */ + + return RSI_ERROR_BLE_INVALID_CALLBACK_CNT; + } + switch (callback_id) { + case RSI_BLE_ON_REMOTE_DEVICE_INFORMATION: { + ble_specific_cb->ble_on_remote_device_info_event = (rsi_ble_on_remote_device_info_t)callback_handler_ptr; + } break; + case RSI_BLE_ON_RCP_EVENT: { + ble_specific_cb->ble_on_rcp_resp_rcvd_event = (rsi_ble_on_rcp_resp_rcvd_t)callback_handler_ptr; + } break; + default: + LOG_PRINT("\nInvalid Callback ID\n"); + return RSI_ERROR_BLE_INVALID_CALLBACK_CNT; + } + return RSI_SUCCESS; +} + +/** + * @fn uint16_t rsi_ble_adv_ext_events_register_callbacks (uint16_t callback_id, void (*callback_handler_ptr)(uint16_t status, + * uint8_t *buffer)) + * @brief Register the BLE call back functions. + * @param[in] callback_id - This is the Id of the call back function following ids are supported: + * @param[in] void (*callback_handler_ptr)(void - This is the Call back handler + * @param[in] status - status of the asynchronous response + * @param[in] buffer - payload of the asynchronous response + * @return 0 - Success \n + * -53 - Failure \n + * If call_back_id is greater than the maximum callbacks to register, returns ref/ RSI_ERROR_BLE_INVALID_CALLBACK_CNT. + * @note In callbacks, application should not initiate any TX operation to the module. + */ + +int32_t rsi_ble_adv_ext_events_register_callbacks(uint16_t callback_id, + void (*callback_handler_ptr)(uint16_t status, uint8_t *buffer)) +{ + //Get ble cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + if (callback_id > RSI_BLE_MAX_NUM_ADV_EXT_EVENT_CALLBACKS) { + /* + *Return , if the callback number exceeds the RSI_BLE_MAX_NUM_CALLBACKS ,or + * the callback is already registered + */ + return RSI_ERROR_BLE_INVALID_CALLBACK_CNT; + } + + switch (callback_id) { + case RSI_BLE_ON_ADV_EXT_ADVERTISE_REPORT_EVENT: { + ble_specific_cb->ble_ae_report_complete_event = (rsi_ble_ae_report_complete_t)callback_handler_ptr; + } break; + case RSI_BLE_ON_ADV_EXT_PERIODIC_ADV_SYNC_ESTBL_EVENT: { + ble_specific_cb->ble_ae_per_adv_sync_estbl_event = (rsi_ble_ae_per_adv_sync_estbl_t)callback_handler_ptr; + } break; + case RSI_BLE_ON_ADV_EXT_PERIODIC_ADVERTISE_REPORT_EVENT: { + ble_specific_cb->ble_ae_per_adv_report_event = (rsi_ble_ae_per_adv_report_t)callback_handler_ptr; + } break; + case RSI_BLE_ON_ADV_EXT_PERIODIC_ADV_SYNC_LOST_EVENT: { + ble_specific_cb->ble_ae_per_adv_sync_lost_event = (rsi_ble_ae_per_adv_sync_lost_t)callback_handler_ptr; + } break; + case RSI_BLE_ON_ADV_EXT_SCAN_TIMEOUT_EVENT: { + ble_specific_cb->ble_ae_scan_timeout_event = (rsi_ble_ae_scan_timeout_t)callback_handler_ptr; + } break; + case RSI_BLE_ON_ADV_EXT_ADVERTISE_SET_TERMINATED_EVENT: { + ble_specific_cb->ble_ae_adv_set_terminated_event = (rsi_ble_ae_adv_set_terminated_t)callback_handler_ptr; + } break; + case RSI_BLE_ON_ADV_EXT_SCAN_REQUEST_RECEIVED_EVENT: { + ble_specific_cb->ble_ae_scan_req_recvd_event = (rsi_ble_ae_scan_req_recvd_t)callback_handler_ptr; + } break; + default: + return RSI_ERROR_BLE_INVALID_CALLBACK_CNT; + } + + return RSI_SUCCESS; +} + +/** @} */ + +/*==============================================*/ +/** + * @brief Register the function pointers for GATT responses + * @param[in] ble_on_cbsc_conn_req - Callback function for CBFC connection request event + * @param[in] ble_on_cbsc_conn_complete - Callback function for CBFC connection complete status event + * @param[in] ble_on_cbsc_rx_data - Callback function for CBFC data receive event + * @param[in] ble_on_cbsc_disconn - Callback function for CBFC disconnect event + * @return void + */ + +void rsi_ble_l2cap_cbsc_register_callbacks(rsi_ble_on_cbfc_conn_req_event_t ble_on_cbsc_conn_req, + rsi_ble_on_cbfc_conn_complete_event_t ble_on_cbsc_conn_complete, + rsi_ble_on_cbfc_rx_data_event_t ble_on_cbsc_rx_data, + rsi_ble_on_cbfc_disconn_event_t ble_on_cbsc_disconn) +{ + + SL_PRINTF(SL_RSI_BLE_L2CAP_CBSC_REGISTER_CALLBACKS_TRIGGER, BLE, LOG_INFO); + // Get ble specific cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + // Assign the call backs to the respective call back + ble_specific_cb->ble_on_cbfc_conn_req_event = ble_on_cbsc_conn_req; + ble_specific_cb->ble_on_cbfc_conn_complete_event = ble_on_cbsc_conn_complete; + ble_specific_cb->ble_on_cbfc_rx_data_event = ble_on_cbsc_rx_data; + ble_specific_cb->ble_on_cbfc_disconn_event = ble_on_cbsc_disconn; + + return; +} + +/** @addtogroup DRIVER14 +* @{ +*/ +/** + * @brief Initailize the BT callbacks register. + * @param[in] ble_cb - BLE control back + * @param[in] rsp_type - BLE Packet type + * @param[in] payload - Payload + * @param[in] payload_length - Payload length + * @return void + * + */ +void rsi_ble_callbacks_handler(rsi_bt_cb_t *ble_cb, uint16_t rsp_type, uint8_t *payload, uint16_t payload_length) +{ + SL_PRINTF(SL_RSI_BLE_CALLBACKS_HANDLER_TRIGGER, BLE, LOG_INFO, "RESPONSE_TYPE: %2x", rsp_type); + // This statement is added only to resolve compilation warning, value is unchanged + UNUSED_PARAMETER(payload_length); + // Get ble cb struct pointer + const rsi_ble_cb_t *ble_specific_cb = ble_cb->bt_global_cb->ble_specific_cb; + uint16_t status = 0; + uint16_t sync_status = 0; + uint8_t le_cmd_inuse_check = 0; + + // updating the response status; + status = (uint16_t)ble_cb->async_status; + + sync_status = (uint16_t)rsi_bt_get_status(ble_cb); + + SL_PRINTF(SL_RSI_BLE_CALLBACKS_HANDLER_STATUS, BLE, LOG_INFO, "STATUS: %2x", status); + + // Check each cmd_type like decode_resp_handler and call the respective callback + switch (rsp_type) { + case RSI_BLE_EVENT_ADV_REPORT: { + if (ble_specific_cb->ble_on_adv_report_event != NULL) { + ble_specific_cb->ble_on_adv_report_event((rsi_ble_event_adv_report_t *)payload); + } + } break; + case RSI_BLE_EVENT_CONN_STATUS: { + if (ble_specific_cb->ble_on_conn_status_event != NULL) { + ((rsi_ble_event_conn_status_t *)payload)->status = status; + ble_specific_cb->ble_on_conn_status_event((rsi_ble_event_conn_status_t *)payload); + } + rsi_add_remote_ble_dev_info((rsi_ble_event_enhance_conn_status_t *)payload); + } break; + + case RSI_BLE_EVENT_ENHANCE_CONN_STATUS: { + if (ble_specific_cb->ble_on_enhance_conn_status_event != NULL) { + ((rsi_ble_event_enhance_conn_status_t *)payload)->status = status; + ble_specific_cb->ble_on_enhance_conn_status_event((rsi_ble_event_enhance_conn_status_t *)payload); + } + rsi_add_remote_ble_dev_info((rsi_ble_event_enhance_conn_status_t *)payload); + } break; + + case RSI_BLE_EVENT_DISCONNECT: { + if (ble_specific_cb->ble_on_disconnect_event != NULL) { + ble_specific_cb->ble_on_disconnect_event((rsi_ble_event_disconnect_t *)payload, status); + } + rsi_remove_remote_ble_dev_info((rsi_ble_event_disconnect_t *)payload); + } break; + case RSI_BLE_EVENT_GATT_ERROR_RESPONSE: { + if (ble_specific_cb->ble_on_gatt_error_resp_event != NULL) { + ble_specific_cb->ble_on_gatt_error_resp_event(status, (rsi_ble_event_error_resp_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_DESC_VAL_RESPONSE: { + if (ble_specific_cb->ble_on_gatt_desc_val_resp_event != NULL) { + ble_specific_cb->ble_on_gatt_desc_val_resp_event(status, (rsi_ble_event_gatt_desc_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + + case RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_LIST: { + if (ble_specific_cb->ble_on_profiles_list_event != NULL) { + ble_specific_cb->ble_on_profiles_list_event(status, (rsi_ble_event_profiles_list_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_BY_UUID: { + if (ble_specific_cb->ble_on_profile_by_uuid_event != NULL) { + ble_specific_cb->ble_on_profile_by_uuid_event(status, (rsi_ble_event_profile_by_uuid_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_READ_CHAR_SERVS: { + if (ble_specific_cb->ble_on_read_by_char_services_event != NULL) { + ble_specific_cb->ble_on_read_by_char_services_event(status, (rsi_ble_event_read_by_type1_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_READ_INC_SERVS: { + if (ble_specific_cb->ble_on_read_by_inc_services_event != NULL) { + ble_specific_cb->ble_on_read_by_inc_services_event(status, (rsi_ble_event_read_by_type2_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_READ_VAL_BY_UUID: { + if (ble_specific_cb->ble_on_read_att_value_event != NULL) { + ble_specific_cb->ble_on_read_att_value_event(status, (rsi_ble_event_read_by_type3_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_READ_RESP: + case RSI_BLE_EVENT_GATT_READ_BLOB_RESP: + case RSI_BLE_EVENT_GATT_READ_MULTIPLE_RESP: { + if (ble_specific_cb->ble_on_read_resp_event != NULL) { + ble_specific_cb->ble_on_read_resp_event(status, (rsi_ble_event_att_value_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_WRITE_RESP: + case RSI_BLE_EVENT_GATT_EXECUTE_WRITE_RESP: { + if (ble_specific_cb->ble_on_write_resp_event != NULL) { + ble_specific_cb->ble_on_write_resp_event(status, (rsi_ble_set_att_resp_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_INDICATE_CONFIRMATION: { + if (ble_specific_cb->ble_on_indicate_confirmation_event != NULL) { + ble_specific_cb->ble_on_indicate_confirmation_event(status, (rsi_ble_set_att_resp_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_GATT_PREPARE_WRITE_RESP: { + if (ble_specific_cb->ble_on_prepare_write_resp_event != NULL) { + ble_specific_cb->ble_on_prepare_write_resp_event(status, (rsi_ble_prepare_write_resp_t *)payload); + } + le_cmd_inuse_check = 1; + } break; + case RSI_BLE_EVENT_SMP_REQUEST: { + if (ble_specific_cb->ble_on_smp_request_event != NULL) { + ble_specific_cb->ble_on_smp_request_event((rsi_bt_event_smp_req_t *)payload); + } + } break; + + case RSI_BLE_EVENT_SMP_RESPONSE: { + if (ble_specific_cb->ble_on_smp_response_event != NULL) { + ble_specific_cb->ble_on_smp_response_event((rsi_bt_event_smp_resp_t *)payload); + } + } break; + + case RSI_BLE_EVENT_CLI_SMP_RESPONSE: { + if (ble_specific_cb->ble_on_cli_smp_response_event != NULL) { + ble_specific_cb->ble_on_cli_smp_response_event((rsi_bt_event_smp_resp_t *)payload); + } + } break; + case RSI_BLE_EVENT_CHIP_MEMORY_STATS: { + if (ble_specific_cb->ble_on_chip_memory_status_event != NULL) { + ble_specific_cb->ble_on_chip_memory_status_event((chip_ble_buffers_stats_t *)payload); + } + } break; + + case RSI_BLE_EVENT_SMP_PASSKEY: { + if (ble_specific_cb->ble_on_smp_passkey_event != NULL) { + ble_specific_cb->ble_on_smp_passkey_event((rsi_bt_event_smp_passkey_t *)payload); + } + } break; + + case RSI_BLE_EVENT_SMP_FAILED: { + if (ble_specific_cb->ble_on_smp_fail_event != NULL) { + ble_specific_cb->ble_on_smp_fail_event(status, (rsi_bt_event_smp_failed_t *)payload); + } + } break; + + case RSI_BLE_EVENT_SC_METHOD: { + if (ble_specific_cb->ble_on_sc_method_event != NULL) { + ble_specific_cb->ble_on_sc_method_event((rsi_bt_event_sc_method_t *)payload); + } + } break; + + case RSI_BLE_EVENT_ENCRYPT_STARTED: { + if (ble_specific_cb->ble_on_smp_encrypt_started != NULL) { + ble_specific_cb->ble_on_smp_encrypt_started(status, (rsi_bt_event_encryption_enabled_t *)payload); + } + } break; + case RSI_BLE_EVENT_SMP_PASSKEY_DISPLAY_EVENT: { + if (ble_specific_cb->ble_on_smp_passkey_display != NULL) { + ble_specific_cb->ble_on_smp_passkey_display((rsi_bt_event_smp_passkey_display_t *)payload); + } + } break; + case RSI_BLE_RSP_PROFILES: { + if (ble_specific_cb->ble_on_profiles_list_resp != NULL) { + ble_specific_cb->ble_on_profiles_list_resp(sync_status, (rsi_ble_resp_profiles_list_t *)payload); + } + } break; + case RSI_BLE_RSP_PROFILE: { + if (ble_specific_cb->ble_on_profile_resp != NULL) { + ble_specific_cb->ble_on_profile_resp(sync_status, (profile_descriptors_t *)payload); + } + } break; + case RSI_BLE_RSP_CHAR_SERVICES: { + if (ble_specific_cb->ble_on_char_services_resp != NULL) { + ble_specific_cb->ble_on_char_services_resp(sync_status, (rsi_ble_resp_char_services_t *)payload); + } + } break; + case RSI_BLE_RSP_INC_SERVICES: { + if (ble_specific_cb->ble_on_inc_services_resp != NULL) { + ble_specific_cb->ble_on_inc_services_resp(sync_status, (rsi_ble_resp_inc_services_t *)payload); + } + } break; + case RSI_BLE_RSP_DESC: { + if (ble_specific_cb->ble_on_att_desc_resp != NULL) { + ble_specific_cb->ble_on_att_desc_resp(sync_status, (rsi_ble_resp_att_descs_t *)payload); + } + } break; + case RSI_BLE_RSP_READ_BY_UUID: + case RSI_BLE_RSP_READ_VAL: + case RSI_BLE_RSP_MULTIPLE_READ: + case RSI_BLE_RSP_LONG_READ: { + if (ble_specific_cb->ble_on_read_resp != NULL) { + ble_specific_cb->ble_on_read_resp(sync_status, rsp_type, (rsi_ble_resp_att_value_t *)payload); + } + } break; + case RSI_BLE_RSP_WRITE: + case RSI_BLE_RSP_WRITE_NO_ACK: + case RSI_BLE_RSP_LONG_WRITE: + case RSI_BLE_RSP_PREPARE_WRITE: + case RSI_BLE_RSP_EXECUTE_WRITE: { + if (ble_specific_cb->ble_on_write_resp != NULL) { + ble_specific_cb->ble_on_write_resp(sync_status, rsp_type); + } + } break; + case RSI_BLE_EVENT_GATT_NOTIFICATION: + case RSI_BLE_EVENT_GATT_INDICATION: + case RSI_BLE_EVENT_GATT_WRITE: + if (ble_specific_cb->ble_on_gatt_events != NULL) { + ble_specific_cb->ble_on_gatt_events(rsp_type, (rsi_ble_event_write_t *)payload); + } + break; + case RSI_BLE_EVENT_MTU: + if (ble_specific_cb->ble_on_mtu_event != NULL) { + ble_specific_cb->ble_on_mtu_event((rsi_ble_event_mtu_t *)payload); + } + le_cmd_inuse_check = 1; + break; + case RSI_BLE_EVENT_MTU_EXCHANGE_INFORMATION: + if (ble_specific_cb->ble_on_mtu_exchange_info_event != NULL) { + ble_specific_cb->ble_on_mtu_exchange_info_event((rsi_ble_event_mtu_exchange_information_t *)payload); + } + le_cmd_inuse_check = 1; + break; + case RSI_BLE_EVENT_LE_PING_TIME_EXPIRED: + if (ble_specific_cb->ble_on_le_ping_time_expired_event != NULL) { + ble_specific_cb->ble_on_le_ping_time_expired_event((rsi_ble_event_le_ping_time_expired_t *)payload); + } + break; + + case RSI_BLE_EVENT_PREPARE_WRITE: + if (ble_specific_cb->ble_on_prepare_write_event != NULL) { + ble_specific_cb->ble_on_prepare_write_event(rsp_type, (rsi_ble_event_prepare_write_t *)payload); + } + break; + + case RSI_BLE_EVENT_EXECUTE_WRITE: + if (ble_specific_cb->ble_on_execute_write_event != NULL) { + ble_specific_cb->ble_on_execute_write_event(rsp_type, (rsi_ble_execute_write_t *)payload); + } + break; + + case RSI_BLE_EVENT_READ_REQ: + if (ble_specific_cb->ble_on_read_req_event != NULL) { + ble_specific_cb->ble_on_read_req_event(rsp_type, (rsi_ble_read_req_t *)payload); + } + break; + + case RSI_BLE_EVENT_PHY_UPDATE_COMPLETE: { + if (ble_specific_cb->ble_on_phy_update_complete_event != NULL) { + ble_specific_cb->ble_on_phy_update_complete_event((rsi_ble_event_phy_update_t *)payload); + } + } break; + + case RSI_BLE_EVENT_DATA_LENGTH_UPDATE_COMPLETE: + if (ble_specific_cb->rsi_ble_on_data_length_update_event != NULL) { + ble_specific_cb->rsi_ble_on_data_length_update_event((rsi_ble_event_data_length_update_t *)payload); + } + break; + + case RSI_BLE_EVENT_SC_PASSKEY: { + if (ble_specific_cb->ble_on_sc_passkey != NULL) { + ble_specific_cb->ble_on_sc_passkey((rsi_bt_event_sc_passkey_t *)payload); + } + } break; + + case RSI_BLE_EVENT_DIRECTED_ADV_REPORT: { + if (ble_specific_cb->ble_on_directed_adv_report_event != NULL) { + ble_specific_cb->ble_on_directed_adv_report_event((rsi_ble_event_directedadv_report_t *)payload); + } + } break; + + case RSI_BLE_EVENT_LE_LTK_REQUEST: + if (ble_specific_cb->ble_on_le_ltk_req_event != NULL) { + ble_specific_cb->ble_on_le_ltk_req_event((rsi_bt_event_le_ltk_request_t *)payload); + } + break; + + case RSI_BLE_EVENT_SECURITY_KEYS: { + if (ble_specific_cb->ble_on_le_security_keys_event != NULL) { + ble_specific_cb->ble_on_le_security_keys_event((rsi_bt_event_le_security_keys_t *)payload); + } + } break; + + case RSI_BLE_EVENT_PSM_CONN_REQ: { + if (ble_specific_cb->ble_on_cbfc_conn_req_event != NULL) { + ble_specific_cb->ble_on_cbfc_conn_req_event((rsi_ble_event_cbfc_conn_req_t *)payload); + } + } break; + + case RSI_BLE_EVENT_PSM_CONN_COMPLETE: { + if (ble_specific_cb->ble_on_cbfc_conn_complete_event != NULL) { + ble_specific_cb->ble_on_cbfc_conn_complete_event((rsi_ble_event_cbfc_conn_complete_t *)payload, status); + } + } break; + + case RSI_BLE_EVENT_PSM_RX_DATA: { + if (ble_specific_cb->ble_on_cbfc_rx_data_event != NULL) { + ble_specific_cb->ble_on_cbfc_rx_data_event((rsi_ble_event_cbfc_rx_data_t *)payload); + } + } break; + + case RSI_BLE_EVENT_PSM_DISCONNECT: { + if (ble_specific_cb->ble_on_cbfc_disconn_event != NULL) { + ble_specific_cb->ble_on_cbfc_disconn_event((rsi_ble_event_cbfc_disconn_t *)payload); + } + } break; + + case RSI_BLE_EVENT_CONN_UPDATE_COMPLETE: { + if (ble_specific_cb->ble_on_conn_update_complete_event != NULL) { + ble_specific_cb->ble_on_conn_update_complete_event((rsi_ble_event_conn_update_t *)payload, status); + } + } break; + case RSI_BLE_EVENT_REMOTE_FEATURES: { + if (ble_specific_cb->ble_on_remote_features_event != NULL) { + ble_specific_cb->ble_on_remote_features_event((rsi_ble_event_remote_features_t *)payload); + } + } break; + case RSI_BLE_EVENT_LE_MORE_DATA_REQ: { + rsi_ble_update_le_dev_buf((rsi_ble_event_le_dev_buf_ind_t *)payload); + if (ble_specific_cb->ble_on_le_more_data_req_event != NULL) { + ble_specific_cb->ble_on_le_more_data_req_event((rsi_ble_event_le_dev_buf_ind_t *)payload); + } + } break; + case RSI_BLE_EVENT_REMOTE_CONN_PARAMS_REQUEST: { + if (ble_specific_cb->ble_on_remote_conn_params_request_event != NULL) { + ble_specific_cb->ble_on_remote_conn_params_request_event((rsi_ble_event_remote_conn_param_req_t *)payload, + status); + } + } break; + case RSI_BLE_EVENT_REMOTE_DEVICE_INFORMATION: { + if (ble_specific_cb->ble_on_remote_device_info_event != NULL) { + ble_specific_cb->ble_on_remote_device_info_event(status, (rsi_ble_event_remote_device_info_t *)payload); + } + } break; + + case RSI_BLE_EVENT_AE_ADVERTISING_REPORT: { + if (ble_specific_cb->ble_ae_report_complete_event != NULL) { + ble_specific_cb->ble_ae_report_complete_event(status, (rsi_ble_ae_adv_report_t *)payload); + } + } break; + case RSI_BLE_EVENT_PER_ADV_SYNC_ESTBL: { + if (ble_specific_cb->ble_ae_per_adv_sync_estbl_event != NULL) { + ble_specific_cb->ble_ae_per_adv_sync_estbl_event(status, (rsi_ble_per_adv_sync_estbl_t *)payload); + } + } break; + case RSI_BLE_EVENT_PER_ADV_REPORT: { + if (ble_specific_cb->ble_ae_per_adv_report_event != NULL) { + ble_specific_cb->ble_ae_per_adv_report_event(status, (rsi_ble_per_adv_report_t *)payload); + } + } break; + case RSI_BLE_EVENT_PER_ADV_SYNC_LOST: { + if (ble_specific_cb->ble_ae_per_adv_sync_lost_event != NULL) { + ble_specific_cb->ble_ae_per_adv_sync_lost_event(status, (rsi_ble_per_adv_sync_lost_t *)payload); + } + } break; + case RSI_BLE_EVENT_SCAN_TIMEOUT: { + if (ble_specific_cb->ble_ae_scan_timeout_event != NULL) { + ble_specific_cb->ble_ae_scan_timeout_event(status, (rsi_ble_scan_timeout_t *)payload); + } + } break; + case RSI_BLE_EVENT_ADV_SET_TERMINATED: { + if (ble_specific_cb->ble_ae_adv_set_terminated_event != NULL) { + ble_specific_cb->ble_ae_adv_set_terminated_event(status, (rsi_ble_adv_set_terminated_t *)payload); + } + } break; + case RSI_BLE_EVENT_SCAN_REQ_RECVD: { + if (ble_specific_cb->ble_ae_scan_req_recvd_event != NULL) { + ble_specific_cb->ble_ae_scan_req_recvd_event(status, (rsi_ble_scan_req_recvd_t *)payload); + } + } break; + case RSI_BLE_EVENT_RCP_DATA_RCVD: { + if (ble_specific_cb->ble_on_rcp_resp_rcvd_event != NULL) { + ble_specific_cb->ble_on_rcp_resp_rcvd_event(status, (rsi_ble_event_rcp_rcvd_info_t *)payload); + } + } + default: + break; + } + + if (le_cmd_inuse_check) { + const uint8_t *remote_dev_bd_addr = payload; + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + if (!memcmp(ble_cb->remote_ble_info[inx].remote_dev_bd_addr, remote_dev_bd_addr, RSI_DEV_ADDR_LEN)) { + if ((ble_cb->remote_ble_info[inx].cmd_in_use) + && ((rsp_type == RSI_BLE_EVENT_GATT_ERROR_RESPONSE) + || (rsp_type == ble_cb->remote_ble_info[inx].expected_resp))) { + ble_cb->remote_ble_info[inx].cmd_in_use = 0; + ble_cb->remote_ble_info[inx].expected_resp = 0; + } + break; + } + } + } +} +/** + * @brief Chip memory status + * @param[in] ble_on_chip_memory_status_event - Memory status + * @return 0 - Success \n + * Non-Zero Value - Failure + * + */ +void rsi_ble_on_chip_memory_status_callbacks_register(chip_ble_buffers_stats_handler_t ble_on_chip_memory_status_event) +{ + + SL_PRINTF(SL_RSI_BLE_CHIP_MEMORY_STATUS_CALLBACKS_REGISTER, BLE, LOG_INFO); + // Get ble cb struct pointer + rsi_ble_cb_t *ble_specific_cb = rsi_driver_cb->ble_cb->bt_global_cb->ble_specific_cb; + + // Assign the call backs to the respective call back + ble_specific_cb->ble_on_chip_memory_status_event = ble_on_chip_memory_status_event; +} + +/** + * @brief Form the payload of the BT command packet + * @param[in] cmd_type - Type of the command + * @param[in] cmd_stuct - Pointer of the command structure + * @param[out] pkt - Pointer of the packet to fill the contents of the payload + * @return 0 - Success \n + * Non-Zero Value - Failure + * + */ + +uint16_t rsi_bt_prepare_common_pkt(uint16_t cmd_type, void *cmd_struct, sl_si91x_packet_t *pkt) +{ + + SL_PRINTF(SL_RSI_BT_PREPARE_COMMON_PACKET_TRIGGER, BLUETOOTH, LOG_INFO, "COMMAND_TYPE: %2x", cmd_type); + uint16_t payload_size = 0; + + switch (cmd_type) { + case RSI_BT_SET_LOCAL_NAME: { + payload_size = sizeof(rsi_bt_req_set_local_name_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BT_SET_BD_ADDR_REQ: { + rsi_bt_cb_t *bt_cb = rsi_driver_cb->bt_common_cb; + if (bt_cb->state == RSI_BT_STATE_OPERMODE_DONE) { + bt_cb->state = RSI_BT_STATE_NONE; + payload_size = sizeof(rsi_bt_set_local_bd_addr_t); + memcpy(pkt->data, cmd_struct, payload_size); + } + } break; + + case RSI_BT_GET_RSSI: { + payload_size = sizeof(rsi_bt_get_rssi_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BT_GET_LOCAL_DEV_ADDR: + case RSI_BT_GET_LOCAL_NAME: + case RSI_BT_REQ_INIT: + case RSI_BT_REQ_DEINIT: + case RSI_BT_GET_BT_STACK_VERSION: + break; + case RSI_BT_SET_ANTENNA_SELECT: { + payload_size = sizeof(rsi_ble_set_antenna_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BT_SET_FEATURES_BITMAP: { + payload_size = sizeof(rsi_bt_set_feature_bitmap_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BT_SET_ANTENNA_TX_POWER_LEVEL: { + payload_size = sizeof(rsi_bt_set_antenna_tx_power_level_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_ONLY_OPER_MODE: { + payload_size = sizeof(rsi_ble_oper_mode_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_REQ_PWRMODE: { + payload_size = sizeof(rsi_ble_power_mode_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_REQ_SOFTRESET: + break; + case RSI_BT_REQ_PER_CMD: { + pkt->data[0] = *(uint8_t *)cmd_struct; + switch (pkt->data[0]) { + case HCI_BT_PER_STATS_CMD_ID: + payload_size = 1; + pkt->data[0] = *(uint8_t *)cmd_struct; + break; + case HCI_BLE_TRANSMIT_CMD_ID: + payload_size = sizeof(rsi_ble_per_transmit_t); + memcpy(pkt->data, cmd_struct, payload_size); + break; + case HCI_BLE_RECEIVE_CMD_ID: + payload_size = sizeof(rsi_ble_per_receive_t); + memcpy(pkt->data, cmd_struct, payload_size); + break; + default: + return RSI_ERROR_INVALID_PARAM; + } + } break; + case RSI_BT_VENDOR_SPECIFIC: { + pkt->data[0] = ((uint8_t *)cmd_struct)[0]; + pkt->data[1] = ((uint8_t *)cmd_struct)[1]; + switch (pkt->data[0] | (pkt->data[1] << 8)) { + case BLE_VENDOR_RF_TYPE_CMD_OPCODE: + payload_size = sizeof(rsi_ble_vendor_rf_type_t); + memcpy(pkt->data, cmd_struct, payload_size); + break; + case BLE_VENDOR_ACCEPTLIST_USING_ADV_DATA_PAYLOAD: + payload_size = sizeof(rsi_ble_req_acceptlist_using_payload_t); + memcpy(pkt->data, cmd_struct, payload_size); + break; + default: + break; + } + } break; + case RSI_BT_SET_GAIN_TABLE_OFFSET_OR_MAX_POWER_UPDATE: { + payload_size = sizeof(rsi_bt_cmd_update_gain_table_offset_or_maxpower_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + default: + break; + } + + // Return payload_size + return payload_size; +} + +/** @} */ + +/** + * @brief Form the payload of the BT Classic command packet. + * @param[in] cmd_type - Type of the command + * @param[in] cmd_stuct - Pointer of the command structure + * @param[out] pkt - Pointer of the packet to fill the contents of the payload + * @return 0 - Success \n + * Non-Zero Value - Failure + */ + +uint16_t rsi_bt_prepare_le_pkt(uint16_t cmd_type, void *cmd_struct, sl_si91x_packet_t *pkt) +{ + + SL_PRINTF(SL_RSI_BT_PREPARE_LE_PKT_TRIGGER, BLUETOOTH, LOG_INFO, "COMMAND_TYPE: %2x", cmd_type); + uint16_t payload_size = 0; + uint8_t le_buf_check = 0; + uint8_t le_cmd_inuse_check = 0; + uint8_t le_buf_in_use_check = 0; + uint8_t le_buf_config_check = 0; + uint8_t pkt_type = 0; + uint16_t expected_resp = 0; + uint8_t is_it_legacy_cmd = 0; + rsi_bt_cb_t *le_cb = rsi_driver_cb->ble_cb; + + switch (cmd_type) { + case RSI_BLE_REQ_ADV: { + payload_size = sizeof(rsi_ble_req_adv_t); + memcpy(pkt->data, cmd_struct, payload_size); + is_it_legacy_cmd = 1; + } break; + case RSI_BLE_SET_ADVERTISE_DATA: { + payload_size = sizeof(rsi_ble_req_adv_data_t); + memcpy(pkt->data, cmd_struct, payload_size); + is_it_legacy_cmd = 1; + } break; + case RSI_BLE_SET_SCAN_RESPONSE_DATA: { + payload_size = sizeof(rsi_ble_req_scanrsp_data_t); + memcpy(pkt->data, cmd_struct, payload_size); + is_it_legacy_cmd = 1; + } break; + case RSI_BLE_REQ_SCAN: { + payload_size = sizeof(rsi_ble_req_scan_t); + memcpy(pkt->data, cmd_struct, payload_size); + is_it_legacy_cmd = 1; + } break; + case RSI_BLE_REQ_CONN: { + payload_size = sizeof(rsi_ble_req_conn_t); + memcpy(pkt->data, cmd_struct, payload_size); + is_it_legacy_cmd = 1; + } break; + case RSI_BLE_REQ_CONN_ENHANCE: { + payload_size = sizeof(rsi_ble_req_enhance_conn_t); + memcpy(pkt->data, cmd_struct, payload_size); + is_it_legacy_cmd = 1; + } break; + case RSI_BLE_CMD_CONN_PARAMS_UPDATE: { + payload_size = sizeof(rsi_ble_cmd_conn_params_update_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_REQ_DISCONNECT: { + payload_size = sizeof(rsi_ble_req_disconnect_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_REQ_START_ENCRYPTION: { + payload_size = sizeof(rsi_ble_strat_encryption_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_REQ_SMP_PAIR: { + payload_size = sizeof(rsi_ble_req_smp_pair_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_SMP_PAIR_RESPONSE: { + payload_size = sizeof(rsi_ble_smp_response_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_SMP_PASSKEY: { + payload_size = sizeof(rsi_ble_smp_passkey_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_REQ_SMP_PAIRING_FAILED: { + payload_size = sizeof(rsi_ble_req_smp_pair_failed_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_REQ_HCI_RAW: { + payload_size = *((uint8_t *)cmd_struct + 3); + pkt_type = *(uint8_t *)cmd_struct; + if (pkt_type == 0x01) { + payload_size += 3; + } else { + payload_size |= ((uint16_t)(*((uint8_t *)cmd_struct + 4)) << 8); + payload_size += 4; + } + memcpy(pkt->data, ((uint8_t *)cmd_struct + 1), payload_size); + le_cb->sync_rsp = 0; + } break; + + //GATT cases + case RSI_BLE_REQ_PROFILES: { + payload_size = sizeof(rsi_ble_req_profiles_list_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_PROFILE: { + payload_size = sizeof(rsi_ble_req_profile_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_CHAR_SERVICES: { + payload_size = sizeof(rsi_ble_req_char_services_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_INC_SERVICES: { + payload_size = sizeof(rsi_ble_req_inc_services_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_READ_BY_UUID: { + payload_size = sizeof(rsi_ble_req_char_val_by_uuid_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_DESC: { + payload_size = sizeof(rsi_ble_req_att_descs_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_READ_VAL: { + payload_size = sizeof(rsi_ble_req_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_MULTIPLE_READ: { + payload_size = sizeof(rsi_ble_req_multi_att_values_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_LONG_READ: { + payload_size = sizeof(rsi_ble_req_long_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_WRITE: { + payload_size = sizeof(rsi_ble_set_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_WRITE_NO_ACK: { + payload_size = sizeof(rsi_ble_set_att_cmd_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_buf_check = 1; + } break; + + case RSI_BLE_REQ_LONG_WRITE: { + payload_size = sizeof(rsi_ble_set_long_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_PREPARE_WRITE: { + payload_size = sizeof(rsi_ble_req_prepare_write_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + case RSI_BLE_REQ_EXECUTE_WRITE: { + payload_size = sizeof(rsi_ble_req_execute_write_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + case RSI_BLE_ADD_SERVICE: { + payload_size = sizeof(rsi_ble_req_add_serv_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_ADD_ATTRIBUTE: { + payload_size = sizeof(rsi_ble_req_add_att_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_SET_LOCAL_ATT_VALUE: { + payload_size = sizeof(rsi_ble_set_local_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_CMD_SET_WWO_RESP_NOTIFY_BUF_INFO: { + payload_size = sizeof(rsi_ble_set_wo_resp_notify_buf_info_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_buf_in_use_check = 1; + le_buf_config_check = 1; + } break; + case RSI_BLE_CMD_NOTIFY: { + payload_size = sizeof(rsi_ble_notify_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_buf_check = 1; + } break; + case RSI_BLE_CMD_INDICATE: { + payload_size = sizeof(rsi_ble_notify_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_INDICATE_CONFIRMATION; + } break; + case RSI_BLE_CMD_INDICATE_CONFIRMATION: { + payload_size = sizeof(rsi_ble_indicate_confirm_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_GET_LOCAL_ATT_VALUE: { + payload_size = sizeof(rsi_ble_get_local_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_GET_LE_PING: { + payload_size = sizeof(rsi_ble_get_le_ping_timeout_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_SET_LE_PING: { + payload_size = sizeof(rsi_ble_set_le_ping_timeout_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_ENCRYPT: { + payload_size = sizeof(rsi_ble_encrypt_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_SET_RANDOM_ADDRESS: { + uint8_t dummy_rand_addr[6] = { 0 }; + rsi_ble_req_rand_t *rsi_ble_rand = (rsi_ble_req_rand_t *)pkt->data; + memcpy(rsi_ble_rand, cmd_struct, sizeof(rsi_ble_req_rand_t)); + if (memcmp(rsi_ble_rand->rand_addr, dummy_rand_addr, 6) == 0) { + rsi_ascii_dev_address_to_6bytes_rev(rsi_ble_rand->rand_addr, (int8_t *)RSI_BLE_SET_RAND_ADDR); + } + // fill payload size + payload_size = sizeof(rsi_ble_req_rand_t); + } break; + + case RSI_BLE_CMD_READ_RESP: { + payload_size = sizeof(rsi_ble_gatt_read_response_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_LE_ACCEPT_LIST: { + payload_size = sizeof(rsi_ble_accept_list_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_RSP_REMOVE_SERVICE: { + payload_size = sizeof(rsi_ble_gatt_remove_serv_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_RSP_REMOVE_ATTRIBUTE: { + payload_size = sizeof(rsi_ble_gatt_remove_att_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_PROCESS_RESOLV_LIST: { + payload_size = sizeof(rsi_ble_resolvlist_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_GET_RESOLVING_LIST_SIZE: + break; + + case RSI_BLE_SET_ADDRESS_RESOLUTION_ENABLE: { + payload_size = sizeof(rsi_ble_set_addr_resolution_enable_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_SET_PRIVACY_MODE: { + payload_size = sizeof(rsi_ble_set_privacy_mode_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_REQ_READ_PHY: { + payload_size = sizeof(rsi_ble_req_read_phy_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_REQ_SET_PHY: { + payload_size = sizeof(rsi_ble_set_phy_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_SET_DATA_LEN: { + payload_size = sizeof(rsi_ble_setdatalength_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_CBFC_CONN_REQ: { + payload_size = sizeof(rsi_ble_cbfc_conn_req_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_CBFC_CONN_RESP: { + payload_size = sizeof(rsi_ble_cbfc_conn_resp_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_CBFC_TX_DATA: { + payload_size = sizeof(rsi_ble_cbfc_data_tx_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_CBFC_DISCONN: { + payload_size = sizeof(rsi_ble_cbfc_disconn_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_CMD_ATT_ERROR: { + payload_size = sizeof(rsi_ble_att_error_response_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_LE_LTK_REQ_REPLY: { + payload_size = sizeof(rsi_ble_set_le_ltkreqreply_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_RX_TEST_MODE: { + payload_size = sizeof(rsi_ble_rx_test_mode_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_TX_TEST_MODE: { + payload_size = sizeof(rsi_ble_tx_test_mode_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_REQ_PROFILES_ASYNC: { + payload_size = sizeof(rsi_ble_req_profiles_list_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_LIST; + } break; + + case RSI_BLE_REQ_PROFILE_ASYNC: { + payload_size = sizeof(rsi_ble_req_profile_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_PRIMARY_SERVICE_BY_UUID; + } break; + case RSI_BLE_GET_CHARSERVICES_ASYNC: { + payload_size = sizeof(rsi_ble_req_char_services_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_READ_CHAR_SERVS; + } break; + + case RSI_BLE_GET_INCLUDESERVICES_ASYNC: { + payload_size = sizeof(rsi_ble_req_inc_services_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_READ_INC_SERVS; + } break; + + case RSI_BLE_READCHARVALUEBYUUID_ASYNC: { + payload_size = sizeof(rsi_ble_req_char_val_by_uuid_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_READ_VAL_BY_UUID; + } break; + + case RSI_BLE_GET_ATTRIBUTE_ASYNC: { + payload_size = sizeof(rsi_ble_req_att_descs_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_DESC_VAL_RESPONSE; + } break; + + case RSI_BLE_GET_DESCRIPTORVALUE_ASYNC: { + payload_size = sizeof(rsi_ble_req_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_READ_RESP; + } break; + + case RSI_BLE_GET_MULTIPLEVALUES_ASYNC: { + payload_size = sizeof(rsi_ble_req_multi_att_values_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_READ_MULTIPLE_RESP; + } break; + + case RSI_BLE_GET_LONGDESCVALUES_ASYNC: { + payload_size = sizeof(rsi_ble_req_long_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_READ_BLOB_RESP; + } break; + case RSI_BLE_SET_DESCVALUE_ASYNC: { + payload_size = sizeof(rsi_ble_set_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_WRITE_RESP; + } break; + case RSI_BLE_SET_PREPAREWRITE_ASYNC: { + payload_size = sizeof(rsi_ble_req_prepare_write_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_PREPARE_WRITE_RESP; + } break; + case RSI_BLE_EXECUTE_LONGDESCWRITE_ASYNC: { + payload_size = sizeof(rsi_ble_req_execute_write_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_GATT_EXECUTE_WRITE_RESP; + } break; + case RSI_BLE_SET_SMP_PAIRING_CAPABILITY_DATA: { + payload_size = sizeof(rsi_ble_set_smp_pairing_capabilty_data_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_CONN_PARAM_RESP_CMD: { + payload_size = sizeof(rsi_ble_cmd_conn_param_resp_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_END_TEST_MODE: + break; + case RSI_BLE_MTU_EXCHANGE_REQUEST: { + payload_size = sizeof(rsi_ble_mtu_exchange_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cmd_inuse_check = 1; + expected_resp = RSI_BLE_EVENT_MTU; + } break; + case RSI_BLE_CMD_MTU_EXCHANGE_RESP: { + payload_size = sizeof(rsi_ble_mtu_exchange_resp_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_CMD_WRITE_RESP: { + payload_size = sizeof(rsi_ble_gatt_write_response_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_CMD_PREPARE_WRITE_RESP: { + payload_size = sizeof(rsi_ble_gatt_prepare_write_response_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + case RSI_BLE_CMD_SET_LOCAL_IRK: { + payload_size = sizeof(rsi_ble_set_local_irk_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_CMD_SET_BLE_TX_POWER: { + payload_size = sizeof(rsi_ble_set_ble_tx_power_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + case RSI_BLE_CMD_INDICATE_SYNC: { + payload_size = sizeof(rsi_ble_notify_att_value_t); + memcpy(pkt->data, cmd_struct, payload_size); + le_cb->sync_rsp = 0; + } break; + + //AE ENABLE + case RSI_BLE_CMD_AE: { + payload_size = sizeof(rsi_ble_ae_pdu_t); + memcpy(pkt->data, cmd_struct, payload_size); + + if (le_cb->state & RSI_BLE_LEGACY_CMD_USED) { + le_cb->state |= RSI_BLE_CHECK_CMD; + } else { + le_cb->state |= RSI_BLE_ADV_EXT_CMD_USED; + } + } break; + + case RSI_BLE_CMD_READ_TRANSMIT_POWER: { + // No TX payload + } break; + + case RSI_BLE_CMD_READ_RF_PATH_COMP: { + // No Tx Payload + } break; + + case RSI_BLE_CMD_WRITE_RF_PATH_COMP: { + payload_size = sizeof(rsi_ble_write_rf_path_comp_t); + memcpy(pkt->data, cmd_struct, payload_size); + } break; + + default: + break; + } + + if (le_buf_check || le_cmd_inuse_check || le_buf_in_use_check) { + uint8_t *remote_dev_bd_addr = (uint8_t *)cmd_struct; + for (uint8_t inx = 0; inx < (RSI_BLE_MAX_NBR_PERIPHERALS + RSI_BLE_MAX_NBR_CENTRALS); inx++) { + if (!memcmp(le_cb->remote_ble_info[inx].remote_dev_bd_addr, remote_dev_bd_addr, RSI_DEV_ADDR_LEN)) { + + /* ERROR PRONE : Do not changes if else checks order */ + if (le_buf_config_check) { + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexAcquire(le_cb->remote_ble_info[inx].ble_buff_mutex, 0xFFFFFFFFUL); + } + if ((le_cb->remote_ble_info[inx].avail_buf_cnt) != (le_cb->remote_ble_info[inx].max_buf_cnt)) { + le_cb->buf_status = 2; //return error based on the status + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexRelease(le_cb->remote_ble_info[inx].ble_buff_mutex); + } + break; + } + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexRelease(le_cb->remote_ble_info[inx].ble_buff_mutex); + } + } + + if (le_buf_in_use_check) { + le_cb->remote_ble_index = inx; + le_buf_in_use_check = RSI_FALSE; + break; + } else if (le_buf_check) { + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexAcquire(le_cb->remote_ble_info[inx].ble_buff_mutex, 0xFFFFFFFFUL); + } + if (le_cb->remote_ble_info[inx].avail_buf_cnt == 0) { + le_cb->buf_status = SI_LE_BUFFER_FULL; + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexRelease(le_cb->remote_ble_info[inx].ble_buff_mutex); + } + break; + } else { + le_cb->buf_status = SI_LE_BUFFER_AVL; + le_cb->remote_ble_info[inx].avail_buf_cnt -= 1; + if (le_cb->remote_ble_info[inx].ble_buff_mutex) { + osMutexRelease(le_cb->remote_ble_info[inx].ble_buff_mutex); + } + break; + } + } else if (le_cmd_inuse_check) { + if (le_cb->remote_ble_info[inx].cmd_in_use) { + le_cb->cmd_status = RSI_TRUE; + } else { + le_cb->cmd_status = RSI_FALSE; + le_cb->remote_ble_info[inx].cmd_in_use = RSI_TRUE; + le_cb->remote_ble_info[inx].expected_resp = expected_resp; + } + } + break; + } + } + } + + if (is_it_legacy_cmd) { + if (le_cb->state & RSI_BLE_ADV_EXT_CMD_USED) { + le_cb->state |= RSI_BLE_CHECK_CMD; //bt_cb->state + } else { + le_cb->state |= RSI_BLE_LEGACY_CMD_USED; //bt_cb->state + } + } + // Return payload_size + return payload_size; +} + +/** + * @brief Fill commands and places into Bt TX queue + * @param[in] cmd - Type of the command to send + * @param[in] cmd_stuct - Pointer of the packet structure to send + * @param[in] resp - Pointer of the packet to fill the contents of the payload + * @return 0 - Success \n + * Non-Zero Value - Failure + */ + +int32_t rsi_bt_driver_send_cmd(uint16_t cmd, void *cmd_struct, void *resp) +{ + + SL_PRINTF(SL_RSI_BT_SEND_CMD_TRIGGER, BLUETOOTH, LOG_INFO, "COMMAND: %2x", cmd); + uint16_t payload_size = 0; + uint16_t protocol_type = 0; + int32_t status = RSI_SUCCESS; + sl_si91x_packet_t *pkt = NULL; + uint8_t *host_desc = NULL; + rsi_bt_cb_t *bt_cb = NULL; + uint32_t calculate_timeout_ms = 0; + + sl_wifi_buffer_t *buffer = NULL; + + protocol_type = rsi_bt_get_proto_type(cmd, &bt_cb); + + SL_PRINTF(SL_RSI_BT_SEND_CMD_PROTOCOL_TYPE, BLUETOOTH, LOG_INFO, "PROTOCOL_TYPE: %2x", protocol_type); + if (protocol_type == 0xFF) { + // Return packet allocation failure error + SL_PRINTF(SL_RSI_ERROR_PACKET_ALLOCATION_FAILURE, + BLUETOOTH, + LOG_ERROR, + "COMMAND: %2x , PROTOCOL_TYPE: %2x", + protocol_type, + cmd); + + return RSI_ERROR_PKT_ALLOCATION_FAILURE; + } + + if ((cmd == RSI_BT_SET_BD_ADDR_REQ) && (rsi_driver_cb->bt_common_cb->state != RSI_BT_STATE_OPERMODE_DONE)) { + SL_PRINTF(SL_RSI_ERROR_COMMAND_GIVEN_IN_WORNG_STATE, BLUETOOTH, LOG_ERROR, "COMMAND: %2x", cmd); + + return RSI_ERROR_COMMAND_GIVEN_IN_WRONG_STATE; + } + // Get timeout based on cmd + calculate_timeout_ms = rsi_bt_get_timeout(cmd, protocol_type); + if (bt_cb->bt_cmd_sem == NULL || (osSemaphoreAcquire(bt_cb->bt_cmd_sem, calculate_timeout_ms) != osOK)) { + // LOG_PRINT("%s: Command ID:0x%x Command timed-out with:%d\n",__func__, cmd, calculate_timeout_ms); + SL_PRINTF(SL_RSI_ERROR_BT_BLE_CMD_IN_PROGRESS, + BLUETOOTH, + LOG_ERROR, + "COMMAND: %2x, Calculate_timeout_ms: %4x", + cmd, + calculate_timeout_ms); + + return RSI_ERROR_BT_BLE_CMD_IN_PROGRESS; + } + + // Allocate command buffer from ble pool + status = sli_si91x_allocate_command_buffer(&buffer, + (void **)&pkt, + sizeof(sl_si91x_packet_t) + RSI_BT_COMMON_CMD_LEN, + calculate_timeout_ms); + // If allocation of packet fails + if (pkt == NULL) { + osSemaphoreRelease(bt_cb->bt_cmd_sem); + + // Return packet allocation failure error + SL_PRINTF(SL_RSI_ERROR_PKT_ALLOCATION_FAILURE, BLUETOOTH, LOG_ERROR, "COMMAND: %2x", cmd); + + return RSI_ERROR_PKT_ALLOCATION_FAILURE; + } + + // Memset host descriptor + memset(pkt->desc, 0, sizeof(pkt->desc)); + + // Get host descriptor pointer + host_desc = (pkt->desc); + + bt_cb->sync_rsp = 1; + payload_size = 0; + + if (protocol_type == RSI_PROTO_BT_COMMON) { + // Memset data + memset(pkt->data, 0, (RSI_BT_COMMON_CMD_LEN - sizeof(sl_si91x_packet_t))); + payload_size = rsi_bt_prepare_common_pkt(cmd, cmd_struct, pkt); + } else if (protocol_type == RSI_PROTO_BLE) { + // Memset data + memset(pkt->data, 0, (RSI_BLE_CMD_LEN - sizeof(sl_si91x_packet_t))); + payload_size = rsi_bt_prepare_le_pkt(cmd, cmd_struct, pkt); + if (cmd == RSI_BLE_REQ_CONN_ENHANCE) { + cmd = RSI_BLE_REQ_CONN; + } + } + + if (bt_cb->buf_status || bt_cb->cmd_status || (bt_cb->state & RSI_BLE_CHECK_CMD)) { + sl_si91x_host_free_buffer(buffer); + + if (bt_cb->buf_status == SI_LE_BUFFER_IN_PROGRESS) { + status = RSI_ERROR_BLE_DEV_BUF_IS_IN_PROGRESS; + } else if (bt_cb->buf_status == SI_LE_BUFFER_FULL) { + status = RSI_ERROR_BLE_DEV_BUF_FULL; + } else if (bt_cb->cmd_status) { + status = RSI_ERROR_BLE_ATT_CMD_IN_PROGRESS; + } + + if (bt_cb->state & RSI_BLE_CHECK_CMD) { + if (bt_cb->state & RSI_BLE_LEGACY_CMD_USED) { + status = RSI_ERROR_BLE_ADV_EXT_COMMAND_NOT_ALLOWED; + } else if (bt_cb->state & RSI_BLE_ADV_EXT_CMD_USED) { + status = RSI_ERROR_BLE_LEGACY_COMMAND_NOT_ALLOWED; + } + } + + bt_cb->buf_status = SI_LE_BUFFER_AVL; + bt_cb->cmd_status = 0; + osSemaphoreRelease(bt_cb->bt_cmd_sem); + SL_PRINTF(SL_RSI_BLE_ERROR, BLUETOOTH, LOG_ERROR, "Status: %4x", status); + + return status; + } + if (cmd == RSI_BLE_REQ_HCI_RAW) { + host_desc[14] = *(uint8_t *)cmd_struct; + } + + rsi_uint16_to_2bytes(host_desc, (payload_size & 0xFFF)); + rsi_uint16_to_2bytes(&host_desc[2], cmd); + + // Save expected response type + bt_cb->expected_response_type = cmd; + + // Save expected response type + bt_cb->expected_response_buffer = resp; + + if (cmd == RSI_BLE_ONLY_OPER_MODE) { + // Save expected response type + bt_cb->expected_response_type = RSI_BT_EVENT_CARD_READY; + bt_cb->sync_rsp = 1; + } + + sl_si91x_driver_send_bt_command(cmd, SI91X_BT_CMD, buffer, bt_cb->sync_rsp); + + if (bt_cb->bt_sem == NULL || (osSemaphoreAcquire(bt_cb->bt_sem, calculate_timeout_ms) != osOK)) { + rsi_bt_set_status(bt_cb, RSI_ERROR_RESPONSE_TIMEOUT); + SL_PRINTF(SL_RSI_SEMAPHORE_TIMEOUT, + BLUETOOTH, + LOG_ERROR, + " Command: %2x , Calculate_timeout_ms: %4x", + cmd, + calculate_timeout_ms); + } + // Get command response status + status = rsi_bt_get_status(bt_cb); + + SL_PRINTF(SL_RSI_BT_COMMAND_RESPONSE_STATUS, BLUETOOTH, LOG_INFO, "STATUS: %4x", status); + // Clear sync rsp variable + bt_cb->sync_rsp = 0; + + // Post the semaphore which is waiting on driver_send API + osSemaphoreRelease(bt_cb->bt_cmd_sem); + + // Return status + return status; +} +/** @} */ + +/*==============================================*/ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c b/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c new file mode 100644 index 000000000..2e1c54daa --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c @@ -0,0 +1,212 @@ +/******************************************************************************* + * @file rsi_common_apis.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "rsi_common.h" + +#include "rsi_ble.h" + +#include "sl_si91x_status.h" + +/* + Global Variables + * */ +rsi_driver_cb_t *rsi_driver_cb = NULL; + +int32_t rsi_driver_memory_estimate(void); + +/** @addtogroup COMMON +* @{ +*/ +/*==============================================*/ +/** + * + * @brief Provide the memory required by the application. This is a non-blocking API. + * @param[in] Void + * @return Driver pool size + * + */ + +int32_t rsi_driver_memory_estimate(void) +{ + uint32_t actual_length = 0; + + // Calculate the Memory length of the application + actual_length += RSI_DRIVER_POOL_SIZE; + return actual_length; +} + +/*==============================================*/ +/** + * + * @brief Initialize WiSeConnect ble driver. This is a non-blocking API. + * Designate memory to all driver components from the buffer provided by the application. + * @param[in] buffer - Pointer to buffer from application. \n Driver uses this buffer to hold driver control for its operation. + * @param[in] length - Length of the buffer. + * @return **Success** - Returns the memory used, which is less than or equal to buffer length provided. \n + * **Failure** - Non-Zero values\n + * + * **RSI_ERROR_TIMEOUT** - If UART initialization fails in SPI / UART mode \n + */ + +/** @} */ +uint8_t *buffer_addr = NULL; +int32_t rsi_ble_driver_init(uint8_t *buffer, uint32_t length) +{ + uint32_t actual_length = 0; + + if (((uintptr_t)buffer & 3) != 0) // To avoid compiler warning, replace uint32_t with uintptr_t + { + // Making buffer 4 byte aligned + // Length -= (4 - ((uint32_t)buffer & 3)); + // To avoid compiler warning, replace uint32_t with uintptr_t + length -= (4 - ((uintptr_t)buffer & 3)); + buffer = (uint8_t *)(((uintptr_t)buffer + 3) & ~3); + } + + // Memset user buffer + memset(buffer, 0, length); + + actual_length += rsi_driver_memory_estimate(); + // If length is not sufficient + if (length < actual_length) { + return actual_length; + } + buffer_addr = buffer; + + // Store length minus any alignment bytes to first 32-bit address in buffer. + *(uint32_t *)buffer = length; + buffer += sizeof(uint32_t); + + // Designate memory for driver cb + rsi_driver_cb = (rsi_driver_cb_t *)buffer; + buffer += sizeof(rsi_driver_cb_t); + +#ifdef SL_SI91X_ENABLE_LITTLE_ENDIAN + rsi_driver_cb->endian = IS_LITTLE_ENDIAN; +#else + rsi_driver_cb->endian = IS_BIG_ENDIAN; +#endif + +#if defined(SL_SI91X_PRINT_DBG_LOG) + // Creates debug prints mutex + rsi_driver_cb->debug_prints_mutex = osMutexNew(NULL); +#endif + + // Designate memory for bt_common_cb + rsi_driver_cb->bt_common_cb = (rsi_bt_cb_t *)buffer; + buffer += ((sizeof(rsi_bt_cb_t) + 3) & ~3); + + // Initialize bt_common_cb + rsi_bt_cb_init(rsi_driver_cb->bt_common_cb, RSI_PROTO_BT_COMMON); + + // Save the expected response type for BLE card ready event from NWP + rsi_driver_cb->bt_common_cb->expected_response_type = RSI_BT_EVENT_CARD_READY; + rsi_driver_cb->bt_common_cb->sync_rsp = 1; + + // Designate memory for ble_cb + rsi_driver_cb->ble_cb = (rsi_bt_cb_t *)buffer; + buffer += ((sizeof(rsi_bt_cb_t) + 3) & ~3); + + // Initialize ble_cb + rsi_bt_cb_init(rsi_driver_cb->ble_cb, RSI_PROTO_BLE); + + // Designate memory for bt_common_cb + rsi_driver_cb->bt_global_cb = (rsi_bt_global_cb_t *)buffer; + buffer += sizeof(rsi_bt_global_cb_t); + + // Fill in bt_global_cb + buffer += rsi_bt_global_cb_init(rsi_driver_cb, buffer); + + if (length < (uint32_t)(buffer - buffer_addr)) { + SL_PRINTF(SL_DRIVER_INIT_INSUFFICIENT_BUFFER_2, COMMON, LOG_ERROR, "length: %4x", (uint32_t)(buffer - buffer_addr)); + return buffer - buffer_addr; + } + + // Update state + rsi_driver_cb->device_state = RSI_DRIVER_INIT_DONE; + + SL_PRINTF(SL_DRIVER_INIT_EXIT, COMMON, LOG_INFO, "actual_length=%4x", actual_length); + return actual_length; +} + +//====================================================== +/** + * + * @brief De-Initialize driver components. Clear all the memory given for driver operations in \ref rsi_ble_driver_init() API. + * In OS case, User need to take care of OS variables initialized in \ref rsi_ble_driver_init(). This is a non-blocking API. + * This API must be called by the thread/task/Master thread that it is not dependent on. + * OS variables allocated/initialized in \ref rsi_ble_driver_init() API. + * @pre Need to call after the driver initialization + * @param[in] Void + * @return 0 - Success \n + * Non-Zero Value - Failure + */ + +int32_t rsi_ble_driver_deinit(void) +{ + SL_PRINTF(SL_DRIVER_DEINIT_ENTRY, COMMON, LOG_INFO); + + if (rsi_driver_cb->device_state < RSI_DRIVER_INIT_DONE) { + // Command given in wrong state + return RSI_ERROR_COMMAND_GIVEN_IN_WRONG_STATE; + } + // Check if buffer is enough for driver components + if (buffer_addr == NULL) { + return RSI_FAILURE; + } + +#if defined(SL_SI91X_PRINT_DBG_LOG) + if (rsi_driver_cb->debug_prints_mutex) { + osMutexDelete(rsi_driver_cb->debug_prints_mutex); + } +#endif + + // Delete BT semaphore + if (rsi_driver_cb->bt_common_cb->bt_cmd_sem) { + osSemaphoreDelete(rsi_driver_cb->bt_common_cb->bt_cmd_sem); + } + + if (rsi_driver_cb->bt_common_cb->bt_sem) { + osSemaphoreDelete(rsi_driver_cb->bt_common_cb->bt_sem); + } + + if (rsi_driver_cb->ble_cb->bt_cmd_sem) { + osSemaphoreDelete(rsi_driver_cb->ble_cb->bt_cmd_sem); + } + + if (rsi_driver_cb->ble_cb->bt_sem) { + osSemaphoreDelete(rsi_driver_cb->ble_cb->bt_sem); + } + + rsi_driver_cb->device_state = RSI_DEVICE_STATE_NONE; + SL_PRINTF(SL_DRIVER_DEINIT_SEMAPHORE_DESTROY_FAILED_26, COMMON, LOG_INFO); + return RSI_SUCCESS; +} + +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c b/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c new file mode 100644 index 000000000..5321777b0 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c @@ -0,0 +1,499 @@ +/******************************************************************************* + * @file rsi_utils.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +/* + Include files + */ + +#include "rsi_common.h" +#include + +#define MAX_MAC_ADDRESS_STRING_LENGTH 17 +#define MAX_IPV4_ADDRESS_STRING_LENGTH 15 + +/* + Global defines + */ +/** @addtogroup DRIVER12 +* @{ +*/ +/*=============================================================================*/ +/** + * @fn void rsi_uint16_to_2bytes(uint8_t *dBuf, uint16_t val) + * @brief Convert uint16 to two byte array. + * @param[in] dBuf - Pointer to buffer to put the data in + * @param[in] val - Data to convert + * @return void + */ +void rsi_uint16_to_2bytes(uint8_t *dBuf, uint16_t val) +{ + if (rsi_driver_cb->endian == IS_LITTLE_ENDIAN) { + dBuf[0] = val & 0x00ff; + dBuf[1] = (val >> 8) & 0x00ff; + } else { + dBuf[1] = val & 0x00ff; + dBuf[0] = (val >> 8) & 0x00ff; + } +} + +/*=============================================================================*/ +/** + * @fn void rsi_uint32_to_4bytes(uint8_t *dBuf, uint32_t val) + * @brief Convert uint32 to four byte array. + * @param[in] dBuf - Pointer to buffer to put the data in + * @param[in] val - Data to convert + * @return void + */ + +void rsi_uint32_to_4bytes(uint8_t *dBuf, uint32_t val) +{ + if (rsi_driver_cb->endian == IS_LITTLE_ENDIAN) { + dBuf[0] = val & 0x000000ff; + dBuf[1] = (val >> 8) & 0x000000ff; + dBuf[2] = (val >> 16) & 0x000000ff; + dBuf[3] = (val >> 24) & 0x000000ff; + } else { + dBuf[3] = val & 0x000000ff; + dBuf[2] = (val >> 8) & 0x000000ff; + dBuf[1] = (val >> 16) & 0x000000ff; + dBuf[0] = (val >> 24) & 0x000000ff; + } +} + +/*=============================================================================*/ +/** + * @fn uint16_t rsi_bytes2R_to_uint16(uint8_t *dBuf) + * @brief Convert a 2 byte array to uint16, first byte in array is LSB. + * @param[in] dBuf - Pointer to a buffer to get the data from + * @return Converted 16 bit data + */ +uint16_t rsi_bytes2R_to_uint16(const uint8_t *dBuf) +{ + uint16_t val; + if (rsi_driver_cb->endian == IS_LITTLE_ENDIAN) { + val = dBuf[1]; + val <<= 8; + val |= dBuf[0] & 0x000000ff; + } else { + val = dBuf[0]; + val <<= 8; + val |= dBuf[1] & 0x000000ff; + } + return val; +} + +/*=============================================================================*/ +/** + * @fn uint32_t rsi_bytes4R_to_uint32(uint8_t *dBuf) + * @brief Convert a 4 byte array to uint32, first byte in array is LSB. + * @param[in] dBuf - Pointer to a buffer to get the data from + * @return Converted 32 bit data + */ + +uint32_t rsi_bytes4R_to_uint32(const uint8_t *dBuf) +{ + // the 32-bit value to return + uint32_t val; + + if (rsi_driver_cb->endian == IS_LITTLE_ENDIAN) { + val = dBuf[3]; + val <<= 8; + val |= dBuf[2] & 0x000000ff; + val <<= 8; + val |= dBuf[1] & 0x000000ff; + val <<= 8; + val |= dBuf[0] & 0x000000ff; + } else { + val = dBuf[0]; + val <<= 8; + val |= dBuf[1] & 0x000000ff; + val <<= 8; + val |= dBuf[2] & 0x000000ff; + val <<= 8; + val |= dBuf[3] & 0x000000ff; + } + + return val; +} + +/*==============================================*/ +/** + * @fn int8_t rsi_ascii_hex2num(int8_t ascii_hex_in) + * @brief ASCII to hex conversion. + * @param[in] ascii_hex_in - ASCII hex input + * @return hex number + */ + +int8_t rsi_ascii_hex2num(int8_t ascii_hex_in) +{ + if ((ascii_hex_in >= '0') && (ascii_hex_in <= '9')) + return (ascii_hex_in - '0'); + if ((ascii_hex_in >= 'A') && (ascii_hex_in <= 'F')) + return (ascii_hex_in - 'A' + 10); + if ((ascii_hex_in >= 'a') && (ascii_hex_in <= 'f')) + return (ascii_hex_in - 'a' + 10); + + return RSI_SUCCESS; +} + +/*=============================================================================*/ +/** + * @fn int8 rsi_char_hex2dec(int8_t *cBuf) + * @brief Convert given ASCII hex notation to decimal notation (used for mac address). + * @param[in] cBuf - ASCII hex notation string + * @return Integer Value + */ +int8_t rsi_char_hex2dec(int8_t *cBuf) +{ + int8_t k = 0; + size_t buf_len = strlen((char *)cBuf); + for (uint8_t i = 0; i < buf_len; i++) { + k = ((k * 16) + rsi_ascii_hex2num(cBuf[i])); + } + return k; +} + +/*=============================================================================*/ +/** + * @fn uint8_t *rsi_ascii_dev_address_to_6bytes_rev(uint8_t *hex_addr, int8_t *ascii_mac_address) + * @brief Convert notation MAC address to a 6-byte hex address. + * @param[in] asciiMacFormatAddress - Source address to convert, must be a null terminated string. + * @param[out] hex_addr - Converted hex address is returned here. + * @return Hex address + */ + +uint8_t *rsi_ascii_dev_address_to_6bytes_rev(uint8_t *hex_addr, int8_t *ascii_mac_address) +{ + uint8_t cBufPos; // which char in the ASCII representation + uint8_t byteNum; // which byte in the 32Bithex_address + int8_t cBuf[6]; // temporary buffer + + byteNum = 5; + cBufPos = 0; + size_t buf_len = strnlen((char *)ascii_mac_address, MAX_MAC_ADDRESS_STRING_LENGTH); + for (uint8_t i = 0; i < buf_len; i++) { + // this will take care of the first 5 octets + if (ascii_mac_address[i] == ':') { // we are at the end of the address octet + cBuf[cBufPos] = 0; // terminate the string + cBufPos = 0; // reset for the next char + hex_addr[byteNum--] = (uint8_t)rsi_char_hex2dec((int8_t *)cBuf); // convert the strint to an integer + } else { + cBuf[cBufPos++] = ascii_mac_address[i]; + } + } + // handle the last octet // we are at the end of the string with no . + cBuf[cBufPos] = 0x00; // terminate the string + hex_addr[byteNum] = (uint8_t)rsi_char_hex2dec((int8_t *)cBuf); // convert the strint to an integer + + return hex_addr; +} + +/*=============================================================================*/ +/** + * @fn int8_t hex_to_ascii(uint8_t hex_num) + * @brief Hex to ascii conversion. + * @param[in] hex_num - hex number + * @return Ascii value for given hex value + */ + +int8_t hex_to_ascii(uint8_t hex_num) +{ + uint8_t ascii = 0; + + switch (hex_num & 0x0F) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + ascii = (hex_num & 0x0F) + '0'; + return ascii; + + case 0xa: + case 0xb: + case 0xc: + case 0xd: + case 0xe: + case 0xf: + ascii = (hex_num & 0x0F) - 10 + 'A'; + return ascii; + default: + break; + } + + return ascii; +} + +/*=============================================================================*/ +/** + * @fn int8_t *rsi_6byte_dev_address_to_ascii(uint8_t *ascii_mac_address, uint8_t *hex_addr) + * @brief Convert given 6-byte hex address to ASCII Mac address. + * @param[in] hex_addr - Hex address input. + * @param[out] asciiMacFormatAddress - Converted ASCII mac address is returned here. + * @return Converted ASCII mac address + */ + +uint8_t *rsi_6byte_dev_address_to_ascii(uint8_t *ascii_mac_address, const uint8_t *hex_addr) +{ + uint8_t cBufPos; // which char in the ASCII representation + + cBufPos = 0; + for (int8_t i = 5; i >= 0; i--) { + ascii_mac_address[cBufPos++] = hex_to_ascii(hex_addr[i] >> 4); + ascii_mac_address[cBufPos++] = hex_to_ascii(hex_addr[i]); + if (i != 0) { + ascii_mac_address[cBufPos++] = ':'; + } + } + return ascii_mac_address; +} + +/*=========================================================================*/ +/** + * @fn uint8_t convert_lower_case_to_upper_case(uint8_t lwrcase) + * @brief Convert the given lower-case character to upper case. + * @param[in] lwrcase - Lower case character to convert + * @return Converted Upper case character + */ + +uint8_t convert_lower_case_to_upper_case(uint8_t lwrcase) +{ + uint8_t digit = (lwrcase >= 'a' && lwrcase <= 'f') ? (lwrcase - 0x20) : lwrcase; + return (digit >= 'A' && digit <= 'F') ? digit - 0x37 : digit - '0'; +} + +/*=========================================================================*/ +/** + * @fn void string2array(uint8_t *dst, uint8_t *src, uint32_t length) + * @brief Convert the given string to destination array. + * @param[in] dst - Pointer to destination array + * @param[in] src - Pointer to source string + * @param[in] length - Length of the string + * @return void + */ + +void string2array(uint8_t *dst, const uint8_t *src, uint32_t length) +{ + for (uint32_t i = 0, j = 0; i < (length * 2) && j < length; i += 2, j++) + if (src[i] && src[i + 1]) { + dst[j] = (uint8_t)((convert_lower_case_to_upper_case(src[i])) * 16); + dst[j] += convert_lower_case_to_upper_case(src[i + 1]); + } else { + dst[j] = 0; + } +} +/*=========================================================================*/ +/** + * @fn uint8_t *rsi_itoa(uint32_t val, uint8_t *str) + * @brief Convert integer value into null-terminated string and stores the result in the array given by str parameter. + * @param[in] val - Value to be converted to a string + * @param[in] str - Array in memory where to store the resulting null-terminated string + * @return String + */ + +uint8_t *rsi_itoa(uint32_t val, uint8_t *str) +{ + int16_t ii = 0; + int16_t jj = 0; + uint8_t tmp[10]; + if (val == 0) { + // if value is zero then handling + str[jj] = '0'; + jj++; + str[jj] = '\0'; + return str; + } + + while (val) { + tmp[ii] = '0' + (val % 10); + val /= 10; + ii++; + } + + for (jj = 0, ii--; ii >= 0; ii--, jj++) { + str[jj] = tmp[ii]; + } + str[jj] = '\0'; + + return str; +} + +/*=========================================================================*/ +/** + * @fn int32_t rsi_atoi(const int8_t *str) + * @brief Convert string to an integer. + * @param[in] str - This is the string representation of an integral number + * @return Converted Integer + */ +int32_t rsi_atoi(const int8_t *str) +{ + int32_t res = 0; + int32_t i = 0; + uint32_t negative_number = 0; + + if (str[i] == '-') { + negative_number = 1; + i++; + } + for (; (str[i] >= '0') && (str[i] <= '9'); ++i) + res = res * 10 + str[i] - '0'; + + if (negative_number) { + res *= -1; + } + return res; +} + +/*=============================================================================*/ +/** + * @fn int8_t asciihex_2_num(int8_t ascii_hex_in) + * @brief ASCII to hex conversion. + * @param[in] ascii_hex_in - ASCII hex input + * @return hex num + */ +int8_t asciihex_2_num(int8_t ascii_hex_in) +{ + if ((ascii_hex_in >= '0') && (ascii_hex_in <= '9')) + return (ascii_hex_in - '0'); + if ((ascii_hex_in >= 'A') && (ascii_hex_in <= 'F')) + return (ascii_hex_in - 'A' + 10); + if ((ascii_hex_in >= 'a') && (ascii_hex_in <= 'f')) + return (ascii_hex_in - 'a' + 10); + + return RSI_SUCCESS; +} + +/*=============================================================================*/ +/** + * @fn int8_t rsi_charhex_2_dec(int8_t *cBuf) + * @brief Convert given ASCII hex notation to decimal notation (used for mac address). + * @param[in] cBuf - ASCII hex notation string. + * @return value in integer + */ +int8_t rsi_charhex_2_dec(int8_t *cBuf) +{ + int8_t k = 0; + size_t buf_len = sl_strlen((char *)cBuf); + for (uint8_t i = 0; i < buf_len; i++) { + k = ((k * 16) + asciihex_2_num(cBuf[i])); + } + return k; +} + +/*=============================================================================*/ +/** + * @fn void rsi_ascii_mac_address_to_6bytes(uint8_t *hexAddr, int8_t *asciiMacAddress) + * @brief Convert notation MAC address to a 6-byte hex address. + * @param[in] asciiMacFormatAddress - source address to convert, must be a null terminated string. + * @param[out] hexAddr - Converted hex address is returned here. + * @return void + */ +void rsi_ascii_mac_address_to_6bytes(uint8_t *hexAddr, int8_t *asciiMacAddress) +{ + uint8_t cBufPos; // which char in the ASCII representation + uint8_t byteNum; // which byte in the 32BitHexAddress + int8_t cBuf[6]; // temporary buffer + + byteNum = 0; + cBufPos = 0; + size_t buf_len = sl_strnlen((char *)asciiMacAddress, MAX_MAC_ADDRESS_STRING_LENGTH); + for (uint8_t i = 0; i < buf_len; i++) { + // this will take care of the first 5 octets + if (asciiMacAddress[i] == ':') { // we are at the end of the address octet + cBuf[cBufPos] = 0; // terminate the string + cBufPos = 0; // reset for the next char + hexAddr[byteNum++] = (uint8_t)rsi_charhex_2_dec((int8_t *)cBuf); // convert the strint to an integer + } else { + cBuf[cBufPos++] = asciiMacAddress[i]; + } + } + // handle the last octet // we are at the end of the string with no . + cBuf[cBufPos] = 0x00; // terminate the string + hexAddr[byteNum] = (uint8_t)rsi_charhex_2_dec((int8_t *)cBuf); // convert the strint to an integer +} + +/*=============================================================================*/ +/** + * @fn void rsi_ascii_dot_address_to_4bytes(uint8_t *hexAddr, int8_t *asciiDotAddress) + * @brief Convert notation network address to 4-byte hex address. + * @param[in] asciiDotAddress - source address to convert, must be a null terminated string. + * @param[out] hexAddr - Output value is passed back in the 4-byte Hex Address. + * @return void + */ +void rsi_ascii_dot_address_to_4bytes(uint8_t *hexAddr, int8_t *asciiDotAddress) +{ + uint8_t cBufPos; + // which char in the ASCII representation + uint8_t byteNum; + // which byte in the 32BitHexAddress + int8_t cBuf[4]; + // character buffer + + byteNum = 0; + cBufPos = 0; + size_t buf_len = sl_strnlen((char *)asciiDotAddress, MAX_IPV4_ADDRESS_STRING_LENGTH); + for (uint8_t i = 0; i < buf_len; i++) { + // this will take care of the first 3 octets + if (asciiDotAddress[i] == '.') { + // we are at the end of the address octet + cBuf[cBufPos] = 0; + // terminate the string + cBufPos = 0; + // reset for the next char + hexAddr[byteNum++] = (uint8_t)rsi_atoi(cBuf); + // convert the strint to an integer + } else { + cBuf[cBufPos++] = asciiDotAddress[i]; + } + } + // handle the last octet + // we are at the end of the string with no . + cBuf[cBufPos] = 0x00; + // terminate the string + // convert the strint to an integer + hexAddr[byteNum] = (uint8_t)rsi_atoi(cBuf); +} +/*=============================================================================*/ +/** + * @fn uint32_t rsi_ntohl(uint32_t a) + * @brief Converts the unsigned integer from network byte order to host byte order. + * @param[in] a - Unsigned integer to convert. + * @return Unsigned integer in host byte order + */ +// network to host long +uint32_t rsi_ntohl(uint32_t a) +{ + return (((a & 0xff000000) >> 24) | ((a & 0x00ff0000) >> 8) | ((a & 0x0000ff00) << 8) | ((a & 0x000000ff) << 24)); +} + +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c b/wiseconnect/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c new file mode 100644 index 000000000..17287f627 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c @@ -0,0 +1,137 @@ +/***************************************************************************/ /** + * @file siwx917_soc_ncp_host.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_wifi_constants.h" +#include "sl_si91x_host_interface.h" +#include "sl_board_configuration.h" +#include "sl_status.h" +#include "sl_constants.h" +#include "cmsis_os2.h" // CMSIS RTOS2 +#include "sl_si91x_types.h" +#include +#include +#include "rsi_m4.h" +#include "sl_common.h" +#include "si91x_device.h" +#include "core_cm4.h" + +extern int16_t rsi_mem_rd(uint32_t addr, uint16_t len, uint8_t *dBuf); +void sl_si91x_ta_events_init(void); +sl_status_t sl_si91x_bus_set_interrupt_mask(uint32_t mask); +sl_status_t sl_si91x_bus_enable_high_speed(void); +sl_status_t sl_si91x_bus_write_memory(uint32_t addr, uint16_t length, const uint8_t *buffer); +sl_status_t sl_si91x_bus_read_memory(uint32_t addr, uint16_t length, uint8_t *buffer); + +void sl_si91x_host_enable_high_speed_bus() +{ + //! Sets specific control register bits + //! Sets the baud rate +} + +sl_status_t sl_si91x_bus_rx_irq_handler(void) +{ + return SL_STATUS_OK; +} + +void sl_si91x_bus_rx_done_handler(void) +{ + return; +} + +sl_status_t sl_si91x_bus_set_interrupt_mask(uint32_t mask) +{ + UNUSED_PARAMETER(mask); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_bus_enable_high_speed(void) +{ + return SL_STATUS_OK; +} + +void sl_si91x_host_set_sleep_indicator(void) +{ + // sets a sleep indicator by activating a specific GPIO pin +} + +uint32_t sl_si91x_host_get_wake_indicator(void) +{ + return 1; +} + +sl_status_t sl_si91x_host_init(const sl_si91x_host_init_configuration *config) +{ + UNUSED_PARAMETER(config); + // Initialize SI91X NWP events + sl_si91x_ta_events_init(); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_host_deinit(void) +{ + return SL_STATUS_OK; +} + +void sl_si91x_host_hold_in_reset(void) +{ + // initializes and activates a GPIO pin to forcefully reset or disable a connected device. +} + +void sl_si91x_host_release_from_reset(void) +{ + // Release the reset state of a connected device +} + +void sl_si91x_host_enable_bus_interrupt(void) +{ + // allowing the system to respond to specific events +} + +void sl_si91x_host_disable_bus_interrupt(void) +{ + // Preventing the system from responding to events +} + +sl_status_t sl_si91x_bus_write_memory(uint32_t addr, uint16_t length, const uint8_t *buffer) +{ + UNUSED_PARAMETER(length); + *(uint32_t *)addr = *(const uint32_t *)buffer; + return 0; +} + +sl_status_t sl_si91x_bus_read_memory(uint32_t addr, uint16_t length, uint8_t *buffer) +{ + // Read memory + rsi_mem_rd(addr, length, buffer); + return 0; +} +bool sl_si91x_host_is_in_irq_context(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h new file mode 100644 index 000000000..ca17a82ca --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_rsi_utility.h @@ -0,0 +1,523 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#ifndef _SL_RSI_UTILITY_H_ +#define _SL_RSI_UTILITY_H_ + +#include +#include +#include +#include "sl_status.h" +#include "sl_constants.h" +#include "sl_wifi_constants.h" +#include "sl_si91x_host_interface.h" +#include "sl_si91x_protocol_types.h" +#include "sl_utility.h" +#include "sl_si91x_driver.h" +#include "sl_wifi_device.h" +#include "sl_si91x_types.h" + +//! @cond Doxygen_Suppress + +/// Low Transmit Power Threshold for Wi-Fi. +#define SI91X_LOW_TRANSMIT_POWER_THRESHOLD 6 + +/// Medium Transmit Power Threshold for Wi-Fi. +#define SI91X_MEDIUM_TRANSMIT_POWER_THRESHOLD 4 + +/** + * Stack size of the event handler thread that processes all Wi-Fi and networking callbacks. + * This value can be overridden by defining a new value for SL_SI91X_EVENT_HANDLER_STACK_SIZE in your project or + * adding -DSL_SI91X_EVENT_HANDLER_STACK_SIZE= to your compiler command line options. + */ +#ifndef SL_SI91X_EVENT_HANDLER_STACK_SIZE +#define SL_SI91X_EVENT_HANDLER_STACK_SIZE 1536 +#endif +typedef bool (*sli_si91x_wifi_buffer_comparator)(const sl_wifi_buffer_t *buffer, const void *userdata); + +typedef struct { + sl_wifi_performance_profile_t wifi_performance_profile; + sl_bt_performance_profile_t bt_performance_profile; + sl_si91x_coex_mode_t coex_mode; +} sli_si91x_performance_profile_t; + +/// Efuse data information +typedef union { + uint8_t mfg_sw_version; ///< Manufacturing PTE software version + uint16_t pte_crc; ///< PTE CRC value +} sl_si91x_efuse_data_t; + +typedef uint32_t sl_si91x_host_timestamp_t; + +void sli_handle_wifi_beacon(sl_si91x_packet_t *packet); +sl_status_t sli_wifi_get_stored_scan_results(sl_wifi_interface_t interface, + sl_wifi_extended_scan_result_parameters_t *extended_scan_parameters); +void sli_wifi_flush_scan_results_database(void); + +typedef void (*sl_si91x_host_atomic_action_function_t)(void *user_data); +typedef uint8_t (*sl_si91x_compare_function_t)(sl_wifi_buffer_t *node, void *user_data); +typedef void (*sl_si91x_node_free_function_t)(sl_wifi_buffer_t *node); + +/* Indicates the current performance profile */ +extern sl_si91x_performance_profile_t current_performance_profile; +extern volatile uint32_t tx_command_queues_status; +extern volatile uint32_t tx_socket_command_queues_status; +extern volatile uint32_t tx_socket_data_queues_status; +extern volatile uint32_t tx_generic_socket_data_queues_status; + +extern volatile uint32_t tx_command_queues_command_in_flight_status; +extern volatile uint8_t tx_socket_command_command_in_flight_queues_status; + +/* Function converts NWP client info to SDK client info */ +sl_status_t convert_si91x_wifi_client_info(sl_wifi_client_info_response_t *client_info_response, + const sl_si91x_client_info_response *sl_si91x_client_info_response); + +/* Function converts NWP events to SDK events */ +sl_wifi_event_t convert_si91x_event_to_sl_wifi_event(rsi_wlan_cmd_response_t command, uint16_t frame_status); + +/* Function used to update the variable that stores the wifi rate */ +sl_status_t save_sl_wifi_rate(sl_wifi_rate_t transfer_rate); + +/* Function used to retrieve the wifi rate */ +sl_status_t get_saved_sl_wifi_rate(sl_wifi_rate_t *transfer_rate); + +/* Function used to set wifi rate to default value of 1 Mbps */ +void reset_sl_wifi_rate(); + +/* Function used to retrieve protocol and transfer rate */ +sl_status_t get_rate_protocol_and_data_rate(const uint8_t data_rate, + sl_wifi_rate_protocol_t *rate_protocol, + sl_wifi_rate_t *transfer_rate); + +/* Function used to update the access point configuration */ +sl_status_t save_ap_configuration(const sl_wifi_ap_configuration_t *wifi_ap_configuration); + +/* Function used to retrieve the access point configuration */ +sl_status_t get_saved_ap_configuration(sl_wifi_ap_configuration_t *wifi_ap_confuguration); + +/* Function used to destroy the current access point configuration */ +void reset_ap_configuration(); + +/* Function used to set whether tcp auto close is enabled or disabled */ +void save_tcp_auto_close_choice(bool is_tcp_auto_close_enabled); + +/* Function used to check whether tcp auto close is enabled or disabled */ +bool is_tcp_auto_close_enabled(); +void sli_si91x_save_tcp_ip_total_config_select_request(uint8_t tcp_ip_total_select); +uint8_t sli_si91x_get_tcp_ip_total_config_select_request(); + +/* Function used to set whether card ready is required or not */ +void set_card_ready_required(bool card_ready_required); + +/* Function used to check whether card ready is required or not */ +bool get_card_ready_required(); + +/* Function used to set the maximum transmission power */ +void save_max_tx_power(uint8_t max_scan_tx_power, uint8_t max_join_tx_power); + +/* Function used to get maximum transmission power */ +sl_wifi_max_tx_power_t get_max_tx_power(); + +/* Function used to set maximum transmission power to default value(31 dBm) */ +void reset_max_tx_power(); + +/* Function used to set the current performance profile */ +void save_wifi_current_performance_profile(const sl_wifi_performance_profile_t *profile); + +/* Function used to get current wifi performance profile */ +void get_wifi_current_performance_profile(sl_wifi_performance_profile_t *profile); + +/* Function used to set the bluetooth performance profile */ +void save_bt_current_performance_profile(const sl_bt_performance_profile_t *profile); + +/* Function used to retrieve bluetooth performance profile */ +void get_bt_current_performance_profile(sl_bt_performance_profile_t *profile); + +/* Function used to retrieve the coex performance profile */ +void get_coex_performance_profile(sl_si91x_performance_profile_t *profile); + +/* Function used to zero out the coex performance profile */ +void reset_coex_current_performance_profile(void); + +/* Function used to update the boot configuration */ +void save_boot_configuration(const sl_si91x_boot_configuration_t *boot_configuration); + +/* Function used to retrieve the boot configuration */ +void get_saved_boot_configuration(sl_si91x_boot_configuration_t *boot_configuration); + +/* Function used to update the coex mode */ +void save_coex_mode(sl_si91x_coex_mode_t coex_mode); + +/* Function used to retrieve the coex mode */ +sl_si91x_coex_mode_t get_coex_mode(void); + +/* Function converts SDK encryption mode to NWP supported mode */ +sl_status_t convert_sl_wifi_to_sl_si91x_encryption(sl_wifi_encryption_t encryption_mode, uint8_t *encryption_request); + +/***************************************************************************/ /** + * @brief + * Initializes new task register index for storing firmware status. + * + * @details + * This function sets up the task register index to store the firmware status in thread-specific storage. + * For all the threads at this index of the thread local array firmware status will be stored. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sli_fw_status_storage_index_init(void); + +/***************************************************************************/ /** + * @brief + * Get the Efuse Data content from flash. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] efuse_data + * @ref sl_si91x_efuse_data_t object that contains the Manufacturing software version. + * efuse_data_type which holds the type of efuse data to be read. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not supported in the current release. + ******************************************************************************/ +sl_status_t sl_si91x_get_flash_efuse_data(sl_si91x_efuse_data_t *efuse_data, uint8_t efuse_data_type); + +/***************************************************************************/ /** + * @brief + * Get the Efuse Data content from driver context. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] efuse_data + * @ref sl_si91x_efuse_data_t object that contains the Manufacturing software version. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +void sl_si91x_get_efuse_data(sl_si91x_efuse_data_t *efuse_data); + +/***************************************************************************/ /** + * @brief + * Set the Efuse Data content in driver context. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] efuse_data + * @ref sl_si91x_efuse_data_t object that contains the Manufacturing software version. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +void sl_si91x_set_efuse_data(const sl_si91x_efuse_data_t *efuse_data); + +/** + * A utility function to convert dBm value to si91x specific power value + * @param wifi_max_tx_power which holds the join power value with dBm as units. + * @return si91x power level + */ +static inline uint8_t convert_dbm_to_si91x_power_level(sl_wifi_max_tx_power_t wifi_max_tx_power) +{ + uint8_t power_value_in_dBm = wifi_max_tx_power.join_tx_power; + if (power_value_in_dBm >= SI91X_LOW_TRANSMIT_POWER_THRESHOLD) { + return SL_SI91X_LOW_POWER_LEVEL; + } else if (power_value_in_dBm >= SI91X_MEDIUM_TRANSMIT_POWER_THRESHOLD) { + return SL_SI91X_MEDIUM_POWER_LEVEL; + } else { + return SL_SI91X_HIGH_POWER_LEVEL; + } +} + +sl_status_t sl_si91x_platform_init(void); +sl_status_t sl_si91x_platform_deinit(void); + +// Event API +/* Function used to set specified flags for event */ +void sli_si91x_set_event(uint32_t event_mask); +void sl_si91x_host_set_bus_event(uint32_t event_mask); + +/* Function used to set specified flags for async event */ +void sl_si91x_host_set_async_event(uint32_t event_mask); + +uint32_t sli_si91x_wait_for_event(uint32_t event_mask, uint32_t timeout); +uint32_t si91x_host_wait_for_bus_event(uint32_t event_mask, uint32_t timeout); + +/* Function used to clear flags for specific event */ +uint32_t sli_si91x_clear_event(uint32_t event_mask); + +/* Function to send the requested Wi-Fi and BT/BLE performance profile to firmware */ +sl_status_t sli_si91x_send_power_save_request(const sl_wifi_performance_profile_t *wifi_profile, + const sl_bt_performance_profile_t *bt_profile); + +sl_status_t sl_si91x_host_init_buffer_manager(const sl_wifi_buffer_configuration_t *config); +sl_status_t sl_si91x_host_deinit_buffer_manager(void); + +/* Function used to allocate memory */ +sl_status_t sl_si91x_host_allocate_buffer(sl_wifi_buffer_t **buffer, + sl_wifi_buffer_type_t type, + uint32_t buffer_size, + uint32_t wait_duration_ms); + +/* Function used to obtain pointer to a specified location in the buffer */ +void *sl_si91x_host_get_buffer_data(sl_wifi_buffer_t *buffer, uint16_t offset, uint16_t *data_length); + +/* Function used to deallocate the memory associated with buffer */ +void sl_si91x_host_free_buffer(sl_wifi_buffer_t *buffer); + +/* Function enqueues response into corresponding response queue */ +sl_status_t sli_si91x_add_to_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t *buffer); + +/* Function dequeues responses from Asynch response queues */ +sl_status_t sli_si91x_remove_from_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t **buffer); + +/* Function used to flush the pending TX packets from the specified queue */ +sl_status_t sli_si91x_flush_nodes_from_queue(sli_si91x_command_queue_t *queue, + sl_si91x_node_free_function_t node_free_function); + +/* Function used to remove the buffer from the specified queue by using comparator */ +sl_status_t sli_si91x_remove_buffer_from_queue_by_comparator(sl_si91x_buffer_queue_t *queue, + const void *user_data, + sli_si91x_wifi_buffer_comparator comparator, + sl_wifi_buffer_t **buffer); + +sl_status_t sli_si91x_flush_all_tx_wifi_queues(uint16_t frame_status); + +/* Function used to flush all the pending TX packets from the specified queue */ +sl_status_t sli_si91x_flush_queue_based_on_type(sli_si91x_command_queue_t *queue, + uint32_t event_mask, + uint16_t frame_status, + sl_si91x_compare_function_t compare_function, + void *user_data); + +/* Function used to check whether queue is empty or not */ +uint32_t sl_si91x_host_queue_status(sl_si91x_buffer_queue_t *queue); + +// These aren't host APIs. These should go into a wifi bus API header +/* Function used to set buffer pointer to point to specified memory address */ +sl_status_t sl_si91x_bus_read_memory(uint32_t addr, uint16_t length, uint8_t *buffer); + +/* Function used to set specified memory address to point to buffer */ +sl_status_t sl_si91x_bus_write_memory(uint32_t addr, uint16_t length, const uint8_t *buffer); + +/*==============================================*/ +/** + * @brief Send chunk of data from Host to Si91x using SPI slave mode. + * @param[in] data_length - Actual data length to send + * @param[in] buffer - Pointer to data + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * + */ +sl_status_t sli_si91x_bus_write_slave(uint32_t data_length, const uint8_t *buffer); + +/* Function used to read contents of the register */ +sl_status_t sl_si91x_bus_read_register(uint8_t address, uint8_t register_size, uint16_t *output); + +/* Function used to write data into register */ +sl_status_t sl_si91x_bus_write_register(uint8_t address, uint8_t register_size, uint16_t data); + +/* Function used to read frame */ +sl_status_t sl_si91x_bus_read_frame(sl_wifi_buffer_t **buffer); + +/* Function used to write frames */ +sl_status_t sl_si91x_bus_write_frame(sl_si91x_packet_t *packet, const uint8_t *payloadparam, uint16_t size_param); + +/* Function used to check the bus availability */ +sl_status_t sl_si91x_bus_init(); + +/* Function used to check the bus availability */ +sl_status_t sl_si91x_bus_rx_irq_handler(void); + +/* Function used to check the bus availability */ +void sl_si91x_bus_rx_done_handler(void); + +/*==============================================*/ +/** + * @brief Calculate crc for a given byte and accumulate crc. + * @param[in] crc8_din - crc byte input + * @param[in] crc8_state - accumulated crc + * @param[in] end - last byte crc + * @return crc value + * + */ +uint8_t sli_lmac_crc8_c(uint8_t crc8_din, uint8_t crc8_state, uint8_t end); + +/*==============================================*/ +/** + * @brief Calculate 6-bit hash value for given mac address. + * @param[in] mac - pointer to mac address + * @return 6-bit Hash value + * + */ +uint8_t sli_multicast_mac_hash(const uint8_t *mac); + +/*==============================================*/ +/** + * @brief Sends boot instructions to WiFi module + * @param[in] uint8 type, type of the insruction to perform + * @param[in] uint32 *data, pointer to data which is to be read/write + * @param[out] none + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @section description + * This API is used to send boot instructions to WiFi module. + **************************************************/ +sl_status_t sl_si91x_boot_instruction(uint8_t type, uint16_t *data); + +/***************************************************************************/ /** + * @brief + * The @ref sl_si91x_bus_enable_high_speed() should be called only if the SPI clock frequency is more than 25 MHz. + * @note + * SPI initialization has to be done in low-speed mode only. + * After device SPI is configured, this API is used for high-speed mode (>25 MHz). + * In addition to this API, the following API sl_si91x_host_enable_high_speed_bus has to be ported by the user to implement the host clock switch. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_bus_enable_high_speed(); + +/* Function used to read the interrupt register */ +sl_status_t sl_si91x_bus_read_interrupt_status(uint16_t *interrupt_status); + +/* Function used to block specified interrupts */ +sl_status_t sl_si91x_bus_set_interrupt_mask(uint32_t mask); + +/* Function used to initialize SPI interface on ULP wakeup */ +void sl_si91x_ulp_wakeup_init(void); + +/** + * @brief + * Function used to obtain wifi credential type like EsAP,PMK,etc.. + * @param id + * Credential ID as identified by [sl_wifi_credential_id_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-types#sl-wifi-credential-id-t). + * @param type + * It specifies type of credential. + * @param cred + * Pointer to store the wifi credential information of type [sl_wifi_credential_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-credential-t) + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + */ +sl_status_t sl_si91x_host_get_credentials(sl_wifi_credential_id_t id, uint8_t type, sl_wifi_credential_t *cred); + +sli_si91x_command_queue_t *sli_si91x_get_command_queue(sl_si91x_command_type_t type); + +bool sli_si91x_get_flash_command_status(); + +void sli_si91x_update_flash_command_status(bool flag); + +bool sli_si91x_is_sdk_ok_to_sleep(); +//! @endcond + +/** +* @addtogroup EXTERNAL_HOST_INTERFACE_FUNCTIONS +* @{ +*/ + +/***************************************************************************/ +/** + * @brief + * Delay execution for a specified number of milliseconds. + * + * @details + * This function introduces a delay for the specified amount of time in milliseconds. It uses the underlying OS + * delay function (`osDelay`) to yield the CPU, allowing other tasks to execute during the delay period. This + * ensures that the delay does not block the execution flow. + * + * @param[in] delay_milliseconds + * The time delay in milliseconds. + *****************************************************************************/ +void sl_si91x_host_delay_ms(uint32_t delay_milliseconds); + +/** + * @brief + * Retrieves the current timestamp. + * + * @details + * This function retrieves the current timestamp from the host system. The timestamp can be used for various purposes such as logging, time measurements, and synchronization. + * + * @return + * The current timestamp of type sl_si91x_host_timestamp_t. + */ +sl_si91x_host_timestamp_t sl_si91x_host_get_timestamp(void); + +/** + * @brief + * Calculates the elapsed time since a given starting timestamp. + * + * @details + * This function calculates the difference between the current timestamp and a provided starting timestamp. It is useful for measuring the time elapsed during operations. + * + * @param[in] starting_timestamp + * The starting timestamp from which the elapsed time is calculated. + * + * @return + * The elapsed time in milliseconds of type sl_si91x_host_timestamp_t. + */ +sl_si91x_host_timestamp_t sl_si91x_host_elapsed_time(uint32_t starting_timestamp); + +/** + * @brief + * Checks if the device is initialized. + * + * @details + * This function verifies whether the device has been properly initialized. It is typically used to ensure that the device is ready for operation before performing any further actions. + * + * @return + * Returns `true` if the device is initialized, `false` otherwise. + */ +bool sl_si91x_is_device_initialized(void); + +/** @} */ +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +sl_status_t sli_si91x_flush_all_socket_command_queues(uint16_t frame_status, uint8_t vap_id); + +sl_status_t sli_si91x_flush_socket_command_queues_based_on_queue_type(uint8_t index, uint16_t frame_status); + +sl_status_t sli_si91x_flush_all_socket_data_queues(uint8_t vap_id); + +sl_status_t sli_si91x_flush_socket_data_queues_based_on_queue_type(uint8_t index); +#endif + +/** + * @brief Flushes all packets from the specified data transmission queue. + * @details This function removes all packets from the provided transmission queue (`tx_data_queue`) and frees the associated memory. It ensures thread-safe operation by preventing race conditions during the process. + * + * @param[in, out] tx_data_queue Pointer to the transmission data queue to be flushed. + * The queue will be reset to an empty state after the function completes. + * + * @return + * - `SL_STATUS_OK`: The operation was successful, and the queue has been flushed. + * - `SL_STATUS_FAIL`: The provided queue pointer is NULL. + * + * @note + * - This function is typically used to clear transmission buffers in scenarios such as error recovery or reinitialization. + * - The function uses atomic operations to ensure that the queue is safely manipulated in multi-threaded environments. + * - The function resets the queue to an empty state after flushing all packets. + */ +sl_status_t sli_si91x_flush_generic_data_queues(sl_si91x_buffer_queue_t *tx_data_queue); + +#endif // _SL_RSI_UTILITY_H_ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h new file mode 100644 index 000000000..2aa2f1e4f --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_constants.h @@ -0,0 +1,759 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#pragma once + +/** \addtogroup SI91X_LOAD_IMAGE_TYPES + * @{ */ +/// Load NWP firmware. +#define LOAD_NWP_FW '1' + +/// Load default NWP firmware active low. +/// @note This is ONLY applicable in Network Co-Processor (NCP) mode for Si91x devices. +#define LOAD_DEFAULT_NWP_FW_ACTIVE_LOW 0x71 +/** @} */ + +/** \addtogroup SI91X_TLS_DEFINE + * \ingroup SL_SI91X_CONSTANTS + * @{ */ +/*=========================================================================*/ +// TLS feature parameters description !// +/*=========================================================================*/ +/// Bit to enable SSL feature +#define SL_SI91X_ENABLE_TLS BIT(0) + +/// Bitmap to enable TLS version 1.0 +#define SL_SI91X_TLS_V_1_0 BIT(2) + +/// Bitmap to enable TLS version 1.2 +#define SL_SI91X_TLS_V_1_2 BIT(3) + +/// Bitmap to enable TLS version 1.1 +#define SL_SI91X_TLS_V_1_1 BIT(4) + +#if defined(SLI_SI917) || defined(DOXYGEN) || defined(SLI_SI915) +/// Bitmap to enable TLS version 1.3 +#define SL_SI91X_TLS_V_1_3 BIT(8) +#endif +/** @} */ + +/** \addtogroup SI91X_HTTP_CLIENT_DEFINE + * \ingroup SL_SI91X_CONSTANTS + * @{ */ +/*=========================================================================*/ +// HTTP Client feature parameters description !// +/*=========================================================================*/ +/// Bit to enable NULL delimiter for HTTP buffer instead of comma +#define SL_SI91X_ENABLE_NULL_DELIMETER BIT(1) + +/// HTTP client post big data support feature bitmap +#define SL_SI91X_SUPPORT_HTTP_POST_DATA BIT(5) + +/// HTTP version 1.1 support feature bitmap +#define SL_SI91X_HTTP_V_1_1 BIT(6) + +/// Bit to enable user given content type in extended header +#define SL_SI91X_HTTP_USER_DEFINED_CONTENT_TYPE BIT(7) + +/// To specify index of SSL cert to be used for HTTPS, for index 0 leave them unset +#define SL_SI91X_HTTPS_CERTIFICATE_INDEX_1 BIT(9) +/// To specify index of SSL cert to be used for HTTPS, for index 0 leave them unset +#define SL_SI91X_HTTPS_CERTIFICATE_INDEX_2 BIT(10) + +/// To enable SNI +#define SL_SI91X_HTTPS_USE_SNI BIT(11) +/** @} */ + +//! @cond Doxygen_Suppress +// Upgrade images +#define BURN_NWP_FW 'B' +#define BURN_M4_FW '4' + +// M4 FW image number for Bootloader +#define M4_FW_IMAGE_NUMBER (1 << 8) + +// Bootloader selects default NWP FW image number +#define SELECT_DEFAULT_NWP_FW_IMAGE_NUMBER '5' + +#define RSI_PING_PONG_CHUNK_SIZE 4096 +#define RSI_REG_READ 0xD1 +#define RSI_REG_WRITE 0xD2 +#define RSI_SEND_RPS_FILE '2' +#define RSI_FWUP_SUCCESSFUL 'S' +#define RSI_EOF_REACHED 'E' +#define RSI_PONG_VALID 'O' +#define RSI_PING_VALID 'I' +#define RSI_PONG_WRITE 0xD4 +#define RSI_PING_WRITE 0xD5 +#define RSI_PONG_AVAIL 'O' +#define RSI_PING_AVAIL 'I' + +#define RSI_PING_BUFFER_ADDR 0x418000 +#define RSI_PONG_BUFFER_ADDR 0x419000 + +#define RSI_ACTIVE_LOW_INTR 0x2 +#define RSI_ACTIVE_HIGH_INTR 0x0 + +#define RSI_OPERMODE_RESPONSE_WAIT_TIME (1000) // Milliseconds +#define RSI_SEND_RAW_DATA_RESPONSE_WAIT_TIME (1000) // Milliseconds + +#ifndef SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME +#define SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME 1000 // 1 second to wait for a command buffer +#endif + +//STM 32 Init Sequence +#define SL_SI91X_INIT_CMD 0x005c4a12 + +// SPI transfer type (8 BIT/32 BIT) +#define RSI_MODE_8BIT 0 +#define RSI_MODE_32BIT 1 + +// frame descriptor length +#define RSI_FRAME_DESC_LEN 16 + +// SPI interrupt register values +// Are these the same as other buses? +// buffer full indication register value from module +#ifndef RSI_BUFFER_FULL +#define RSI_BUFFER_FULL 0x01 +#endif +// buffer empty indication register value from module +#define RSI_BUFFER_EMPTY 0x02 +// RX packet pending register value from module +#define RSI_RX_PKT_PENDING 0x08 +// Assertion Interrupt indication from module +#define RSI_ASSERT_INTR 0x80 + +//Bootloader defines +#define SL_SI91X_SAFE_UPGRADE_ADDR 0x55408 +#define SL_SI91X_SAFE_UPGRADE BIT(12) +#define SL_SI91X_FW_START_OF_FILE BIT(0) +#define SL_SI91X_FW_END_OF_FILE BIT(1) +#define SL_SI91X_MIN_CHUNK_SIZE 4096 +#define SL_SI91X_LOOP_COUNT_UPGRADE_IMAGE 0xFFFF +#define SL_SI91X_RESET_LOOP_COUNTER(X) X = 0; +#define SL_SI91X_WHILE_LOOP(X, Y) while ((X++) < (int32_t)Y) +#define SL_SI91X_CHECK_LOOP_COUNTER(X, Y) \ + { \ + if (X >= Y) \ + return -1; \ + } + +//***************************** Macros for Crypto Start **********************************/ + +#define SL_SI91X_KEY_BUFFER_SIZE 32 +#define SL_SI91X_TAG_SIZE 16 +#define SL_SI91X_IV_SIZE 16 + +// ECDH defines +#define ECDH_BUFFER_SIZE 32 + +// TRNG defines +#define TRNG_INIT 1 +#define TRNG_ENTROPY 2 +#define TRNG_KEY 3 +#define TRNG_GENERATION 4 + +#define TRNG_INIT_MSG_LENGTH 16 +#define TRNG_KEY_SIZE 4 +#define TRNG_TEST_DATA_SIZE 64 + +// CCM defines +#define SL_SI91X_CCM_IV_MIN_SIZE 7 +#define SL_SI91X_CCM_IV_MAX_SIZE 13 +#define SL_SI91X_CCM_IV_BUFF_LEN 16 // SL_SI91X_CCM_IV_MAX_SIZE + 3 Bytes for Padding. +#define SL_SI91X_CCM_AD_MAX_SIZE 128 // Limiting header length to 128. +#define SL_SI91X_CCM_MSG_MAX_SIZE 1200 + +// GCM defines +#define SL_SI91X_GCM_IV_SIZE 12 +#define SL_SI91X_GCM_AD_MAX_SIZE 128 +#define SL_SI91X_GCM_MSG_MAX_SIZE 1400 + +// Chachapoly defines +#define SL_SI91X_KEYR_SIZE 16 +#define SL_SI91X_KEYS_SIZE 16 +#define SL_SI91X_CHACHAPOLY_IV_SIZE 12 +#define SL_SI91X_CHACHAPOLY_MSG_MAX_SIZE 1200 + +//ECDSA defines +#define SL_SI91X_PRIVATE_KEY_MAX_SIZE 64 +#define SL_SI91X_PUBLIC_KEY_MAX_SIZE 136 +#define SL_SI91X_SIGNATURE_MAX_SIZE 128 +#define SL_SI91X_ECDSA_MSG_MAX_SIZE 1000 + +// NWP Configuration defines +#define SL_SI91X_XO_CTUNE_FROM_HOST BIT(0) +#define SL_SI91X_ENABLE_NWP_WDT_FROM_HOST BIT(1) +#define SL_SI91X_DISABLE_NWP_WDT_FROM_HOST BIT(2) + +//NWP Get configuration defines +#define GET_OPN_BOARD_CONFIG 1 + +//***************************** Macros for Crypto End **********************************/ + +// Command packet 'unused' bytes +#define SLI_SI91X_COMMAND_FLAGS_INDEX 10 +#define SLI_SI91X_COMMAND_RESPONSE_INDEX 11 + +typedef struct { + uint32_t buffer_full : 1; + uint32_t ready_to_transmit : 1; + uint32_t _reserved2 : 1; + uint32_t rx_packet_pending : 1; + uint32_t _reserved4 : 1; + uint32_t _reserved5 : 1; + uint32_t _reserved6 : 1; + uint32_t _reserved7 : 1; +} sl_si91x_interrupt_status_t; + +// Timeout used in get_channel API +#define SL_SI91X_GET_CHANNEL_TIMEOUT 30200 +//! @endcond + +/** \addtogroup SL_SI91X_CONSTANTS + * @{ */ +/// Si91x specific keepalive types. +typedef enum { + SL_SI91X_AP_KEEP_ALIVE_DISABLE = 0, ///< Disable keepalive functionality. + SL_SI91X_AP_DEAUTH_BASED_KEEP_ALIVE = + 1, ///< AP performs keepalive functionality based on the RX packets received from its stations. + ///< If no packet is received from the station within the AP keep alive timeout period, the AP disconnects the station. + SL_SI91X_AP_NULL_BASED_KEEP_ALIVE = + 3 ///< AP performs keepalive functionality by sending a NULL DATA packet to the station. + ///< If no ACK is received from the station after a specific number of retries, the AP discards the station. +} sl_si91x_ap_keepalive_type_t; + +/// Assertion type must be in the range of 0 to 15 (both included) +typedef enum { + SL_SI91X_ASSERTION_TYPE_LMAC = 0, ///< Assertion type specific to the LMAC core. + SL_SI91X_ASSERTION_TYPE_SME = 1, ///< Assertion type specific to the SME (Station Management Entity) core. + SL_SI91X_ASSERTION_TYPE_UMAC = 2, ///< Assertion type specific to the UMAC core. + SL_SI91X_ASSERTION_TYPE_NETX = 4, ///< Assertion type specific to the NETX (Networking Stack) core. + SL_SI91X_ASSERTION_TYPE_CA = + 8, ///< Enables critical assertion indication and provides a RAM dump during critical assertions. + SL_SI91X_ASSERTION_TYPE_ALL = 15 ///< Enables assertion for all cores. +} sl_si91x_assertion_type_t; + +/// Assertion level must be in the range of 0 to 15 (both included) +typedef enum { + SL_SI91X_ASSERTION_LEVEL_MIN = 0, ///< Minimum assertion level. Indicates that an assertion is mandatory. + SL_SI91X_ASSERTION_LEVEL_SP = 1, ///< Assertion for specific print messages, used for debugging or analysis. + SL_SI91X_ASSERTION_LEVEL_REC = + 2, ///< Recoverable assertion level. Indicates that the system can recover from the assertion. + SL_SI91X_ASSERTION_LEVEL_INFO = 4, ///< Informational assertion level, used to log general information. + SL_SI91X_ASSERTION_LEVEL_MAX = 15 ///< Maximum assertion level. Enables all types of print statements. +} sl_si91x_assertion_level_t; +/** @} */ + +//! @cond Doxygen_Suppress +typedef enum { + SL_SI91X_RETURN_IMMEDIATELY = 0, + SL_SI91X_WAIT_FOR_RESPONSE_BIT = (1UL << 30), + SL_SI91X_WAIT_FOR_EVER = (1UL << 31), + SL_SI91X_WAIT_FOR_OTAF_RESPONSE = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | SL_SI91X_WAIT_FOR_EVER), + SL_SI91X_WAIT_FOR_SYNC_SCAN_RESULTS = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 12000), + SL_SI91X_WAIT_FOR_COMMAND_RESPONSE = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 1000), + SL_SI91X_WAIT_FOR_SOCKET_ACCEPT_RESPONSE = (SL_SI91X_WAIT_FOR_RESPONSE_BIT | 5000), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS = 3000, + SL_SI91X_WAIT_FOR_DNS_RESOLUTION = 20000, +} sl_si91x_wait_period_t; + +#define SL_SI91X_WAIT_FOR(x) (sl_si91x_wait_period_t)(x) +#define SL_SI91X_WAIT_FOR_RESPONSE(x) (sl_si91x_wait_period_t)(SL_SI91X_WAIT_FOR_RESPONSE_BIT | (x)) + +typedef enum { + // (7+/-1)dBm in 2.4GHz band + // (5+/-1)dBm in 5GHz band + SL_SI91X_LOW_POWER_LEVEL, + + // (5+/-1)dBm in 2.4GHz band + // (7+/-1)dBm in 5GHz band + SL_SI91X_MEDIUM_POWER_LEVEL, + + SL_SI91X_HIGH_POWER_LEVEL +} sl_si91x_transmit_power_level; + +/*====================================================*/ +// Constant Defines +// SPI Status +#define RSI_SPI_SUCCESS 0x58 +#define RSI_SPI_BUSY 0x54 +#define RSI_SPI_FAIL 0x52 +#define RSI_SUCCESS 0 +#define RSI_ERROR_BUFFER_FULL -3 // module buffer full error code +#define RSI_ERROR_IN_SLEEP -4 // module in sleep error code + +//SPI Internal Register Offset +#define RSI_SPI_INT_REG_ADDR 0x00 //@ register access method +#define RSI_SPI_MODE_REG_ADDR 0x08 //@ register access method +#define RSI_SPI_LENGTH_REG_ADDR 0x20 + +#define RSI_INT_MASK_REG_ADDR 0x41050000 // Interrupt mask register +#define RSI_INT_CLR_REG_ADDR 0x22000010 // Interrupt clear register + +// Packet queue identifiers +#define RSI_COMMON_Q 0 +#define RSI_ZB_Q 1 +#define RSI_BT_Q 2 +#define RSI_WLAN_MGMT_Q 4 +#define RSI_WLAN_DATA_Q 5 +#ifdef SAPIS_BT_STACK_ON_HOST +#define RSI_BT_INT_MGMT_Q 6 +#define RSI_BT_HCI_Q 7 +#endif + +// Event IDs +#define RSI_RX_EVENT 0 // RX event number used in the driver +#define RSI_TX_EVENT 1 // TX event number used in the driver +#define RSI_SOCKET_EVENT 2 // Socket event number used in the driver +#define RSI_MAX_NUM_EVENTS 3 // Max number events used in the driver + +#define RSI_HOST_INTF_REG_OUT 0x4105003C +#define RSI_HOST_INTF_REG_IN 0x41050034 +#define RSI_HOST_INTF_STATUS_REG 0x41050004 + +// si91x boot results +#define RSI_EOF_REACHED 'E' +#define RSI_BOOTUP_OPTIONS_LAST_CONFIG_NOT_SAVED 0xF1 +#define RSI_BOOTUP_OPTIONS_CHECKSUM_FAIL 0xF2 +#define RSI_INVALID_OPTION 0xF3 +#define RSI_CHECKSUM_SUCCESS 0xAA +#define RSI_CHECKSUM_FAILURE 0xCC +#define RSI_CHECKSUM_INVALID_ADDRESS 0x4C +#define VALID_FIRMWARE_NOT_PRESENT 0x23 +#define RSI_BOOTLOADER_VERSION_1P0 0x10 +#define RSI_BOOTLOADER_VERSION_1P1 0x11 +#define RSI_ROM_VERSION_1P0 1 +#define RSI_ROM_VERSION_1P1 2 + +#define SLI_WIFI_REGISTER_VALID (0xAB) + +#define RSI_HOST_INTERACT_REG_VALID (0xAB << 8) +#define RSI_HOST_INTERACT_REG_VALID_FW (0xA0 << 8) + +#define CONFIG_RTSTHRESHOLD 1 +#define RSI_RTS_THRESHOLD 2346 + +#define RSI_SEND_RAW_DATA 0x1 +#define RSI_RECEIVE_RAW_DATA 0x0 + +// enumeration for command request used in common control block +typedef enum { + // Common command requests + RSI_COMMON_REQ_OPERMODE = 0x10, + RSI_COMMON_REQ_ANTENNA_SELECT = 0x1B, + RSI_COMMON_REQ_FEATURE_FRAME = 0xC8, + RSI_COMMON_REQ_PWRMODE = 0x15, + // Reusing RSI_WLAN_REQ_FW_VERSION as RSI_COMMON_REQ_FW_VERSION + RSI_COMMON_REQ_FW_VERSION = 0x49, + RSI_COMMON_REQ_GET_EFUSE_DATA = 0xA0, + + // Unimplemented common command requests + RSI_COMMON_REQ_SOFT_RESET = 0x1C, + RSI_COMMON_REQ_ENCRYPT_CRYPTO = 0x76, + RSI_COMMON_REQ_UART_FLOW_CTRL_ENABLE = 0xA4, + RSI_COMMON_REQ_TA_M4_COMMANDS = 0xB0, + RSI_COMMON_REQ_DEBUG_LOG = 0x26 +#ifdef RSI_WAC_MFI_ENABLE + , + RSI_COMMON_REQ_IAP_GET_CERTIFICATE = 0xB6, + RSI_COMMON_REQ_IAP_INIT = 0xB7, + RSI_COMMON_REQ_IAP_GENERATE_SIGATURE = 0xB8 +#endif + +#ifdef SLI_PUF_ENABLE + , + RSI_COMMON_REQ_PUF_ENROLL = 0xD0, + RSI_COMMON_REQ_PUF_DIS_ENROLL = 0xD1, + RSI_COMMON_REQ_PUF_START = 0xD2, + RSI_COMMON_REQ_PUF_SET_KEY = 0xD3, + RSI_COMMON_REQ_PUF_DIS_SET_KEY = 0xD4, + RSI_COMMON_REQ_PUF_GET_KEY = 0xD5, + RSI_COMMON_REQ_PUF_DIS_GET_KEY = 0xD6, + RSI_COMMON_REQ_PUF_LOAD_KEY = 0xD7, + RSI_COMMON_REQ_AES_ENCRYPT = 0xD8, + RSI_COMMON_REQ_AES_DECRYPT = 0xD9, + RSI_COMMON_REQ_AES_MAC = 0xDA, + RSI_COMMON_REQ_PUF_INTR_KEY = 0xCE +#endif + , + RSI_COMMON_REQ_SWITCH_PROTO = 0x77, + RSI_COMMON_REQ_GET_RAM_DUMP = 0x92, + RSI_COMMON_REQ_ASSERT = 0xE1, + RSI_COMMON_REQ_SET_RTC_TIMER = 0xE9, + RSI_COMMON_REQ_GET_RTC_TIMER = 0xF2, + RSI_COMMON_REQ_SET_CONFIG = 0xBA, + RSI_COMMON_REQ_GET_CONFIG = 0x0C +#ifdef CONFIGURE_GPIO_FROM_HOST + , + RSI_COMMON_REQ_GPIO_CONFIG = 0x28 +#endif +#ifdef FW_LOGGING_ENABLE + , + RSI_COMMON_REQ_DEVICE_LOGGING_INIT = 0x82 +#endif +} rsi_common_cmd_request_t; + +typedef enum { + // Common command responses + RSI_COMMON_RSP_OPERMODE = 0x10, + RSI_COMMON_RSP_ANTENNA_SELECT = 0x1B, + RSI_COMMON_RSP_FEATURE_FRAME = 0xC8, + RSI_COMMON_RSP_CARDREADY = 0x89, + RSI_COMMON_RSP_PWRMODE = 0x15, + + // Unimplemented common command responses + RSI_COMMON_RSP_CLEAR = 0x00, + RSI_COMMON_RSP_SOFT_RESET = 0x1C, + RSI_COMMON_RSP_ULP_NO_RAM_RETENTION = 0xCD, + RSI_COMMON_RSP_ASYNCHRONOUS = 0xFF, + RSI_COMMON_RSP_ENCRYPT_CRYPTO = 0x76, + RSI_COMMON_RSP_UART_FLOW_CTRL_ENABLE = 0xA4, + RSI_COMMON_RSP_TA_M4_COMMANDS = 0xB0, + RSI_COMMON_RSP_DEBUG_LOG = 0x26 +#ifdef SLI_PUF_ENABLE + , + RSI_COMMON_RSP_PUF_ENROLL = 0xD0, + RSI_COMMON_RSP_PUF_DIS_ENROLL = 0xD1, + RSI_COMMON_RSP_PUF_START = 0xD2, + RSI_COMMON_RSP_PUF_SET_KEY = 0xD3, + RSI_COMMON_RSP_PUF_DIS_SET_KEY = 0xD4, + RSI_COMMON_RSP_PUF_GET_KEY = 0xD5, + RSI_COMMON_RSP_PUF_DIS_GET_KEY = 0xD6, + RSI_COMMON_RSP_PUF_LOAD_KEY = 0xD7, + RSI_COMMON_RSP_AES_ENCRYPT = 0xD8, + RSI_COMMON_RSP_AES_DECRYPT = 0xD9, + RSI_COMMON_RSP_AES_MAC = 0xDA, + RSI_COMMON_RSP_PUF_INTR_KEY = 0xCE +#endif + +#ifdef RSI_WAC_MFI_ENABLE + , + RSI_COMMON_RSP_IAP_GET_CERTIFICATE = 0xB6, + RSI_COMMON_RSP_IAP_INIT = 0xB7, + RSI_COMMON_RSP_IAP_GENERATE_SIGATURE = 0xB8 +#endif + // Reusing RSI_WLAN_REQ_FW_VERSION as RSI_COMMON_REQ_FW_VERSION + , + RSI_COMMON_RSP_GET_EFUSE_DATA = 0xA0, + RSI_COMMON_RSP_FW_VERSION = 0x49, + RSI_COMMON_RSP_SWITCH_PROTO = 0x77, + RSI_COMMON_RSP_GET_RAM_DUMP = 0x92, + RSI_COMMON_RSP_ASSERT = 0xE1, + RSI_COMMON_RSP_SET_RTC_TIMER = 0xE9, + RSI_COMMON_RSP_GET_RTC_TIMER = 0xF2, + RSI_COMMON_RSP_SET_CONFIG = 0xBA, + RSI_COMMON_RSP_GET_CONFIG = 0x0C +#ifdef CONFIGURE_GPIO_FROM_HOST + , + RSI_COMMON_RSP_GPIO_CONFIG = 0x28 +#endif +#ifdef FW_LOGGING_ENABLE + , + RSI_COMMON_RSP_DEVICE_LOGGING_INIT = 0x82 +#endif +} rsi_common_cmd_response_t; + +// enumeration for WLAN command request codes +typedef enum { + // Wi-Fi commands + RSI_WLAN_REQ_CONFIG = 0xBE, + RSI_WLAN_REQ_BAND = 0x11, + RSI_WLAN_REQ_INIT = 0x12, + RSI_WLAN_REQ_SCAN = 0x13, + RSI_WLAN_REQ_JOIN = 0x14, + RSI_WLAN_REQ_SET_MAC_ADDRESS = 0x17, + RSI_WLAN_REQ_DISCONNECT = 0x19, + RSI_WLAN_REQ_AP_STOP = 0xAE, + RSI_WLAN_REQ_SET_REGION = 0x1D, + RSI_WLAN_REQ_QUERY_NETWORK_PARAMS = 0x18, + RSI_WLAN_REQ_AP_CONFIGURATION = 0x24, + RSI_WLAN_REQ_EVM_OFFSET = 0x36, + RSI_WLAN_REQ_EVM_WRITE = 0x37, + RSI_WLAN_REQ_RSSI = 0x3A, + RSI_WLAN_REQ_EAP_CONFIG = 0x4C, + RSI_WLAN_REQ_FW_VERSION = 0x49, + RSI_WLAN_REQ_MAC_ADDRESS = 0x4A, + RSI_WLAN_REQ_QUERY_GO_PARAMS = 0x4E, + RSI_WLAN_REQ_SET_CERTIFICATE = 0x4D, + RSI_WLAN_REQ_BG_SCAN = 0x6A, + RSI_WLAN_REQ_BEACON_STOP = 0x63, + RSI_WLAN_REQ_WPS_METHOD = 0x72, + RSI_WLAN_REQ_EFUSE_READ = 0x73, + RSI_WLAN_REQ_ROAM_PARAMS = 0x7B, + RSI_WLAN_REQ_RX_STATS = 0xA2, + RSI_WLAN_REQ_RADIO = 0x81, + RSI_WLAN_REQ_EXT_STATS = 0x68, + RSI_WLAN_REQ_TWT_AUTO_CONFIG = 0x2E, + RSI_WLAN_REQ_TWT_PARAMS = 0x2F, + SL_WIFI_REQ_RESCHEDULE_TWT = 0x3F, + RSI_WLAN_REQ_GAIN_TABLE = 0x47, + RSI_WLAN_REQ_TX_TEST_MODE = 0x7C, + RSI_WLAN_REQ_HOST_PSK = 0xA5, + RSI_WLAN_REQ_SET_REGION_AP = 0xBD, + RSI_WLAN_REQ_CALIB_WRITE = 0xCA, + RSI_WLAN_REQ_FILTER_BCAST_PACKETS = 0xC9, + RSI_WLAN_REQ_CALIB_READ = 0xCF, + RSI_WLAN_REQ_FULL_FW_VERSION = 0xE0, + RSI_WLAN_REQ_HTTP_OTAF = 0xF4, + RSI_WLAN_REQ_11AX_PARAMS = 0xFF, + + // Network commands + RSI_WLAN_REQ_PING_PACKET = 0x29, + RSI_WLAN_REQ_IPCONFV4 = 0x41, + RSI_WLAN_REQ_DNS_QUERY = 0x44, + RSI_WLAN_REQ_HTTP_CLIENT_GET = 0x51, + RSI_WLAN_REQ_HTTP_CLIENT_POST = 0x52, + RSI_WLAN_REQ_HTTP_CLIENT_PUT = 0x53, + RSI_WLAN_REQ_IPCONFV6 = 0x90, + RSI_WLAN_REQ_MULTICAST = 0xB1, + RSI_WLAN_REQ_HTTP_ABORT = 0xB3, + RSI_WLAN_REQ_HTTP_CREDENTIALS = 0xB4, + RSI_WLAN_REQ_EMB_MQTT_CLIENT = 0xCB, + RSI_WLAN_REQ_SNTP_CLIENT = 0xE4, + RSI_WLAN_REQ_HTTP_CLIENT_POST_DATA = 0xEB, + + // Socket commands + RSI_WLAN_REQ_SOCKET_CREATE = 0x42, + RSI_WLAN_REQ_SOCKET_CLOSE = 0x43, + RSI_WLAN_REQ_SOCKET_READ_DATA = 0x6B, + RSI_WLAN_REQ_SOCKET_ACCEPT = 0x6C, + RSI_WLAN_REQ_SOCKET_CONFIG = 0xA7, + RSI_WLAN_REQ_SELECT_REQUEST = 0x74, + RSI_WLAN_REQ_SET_SNI_EMBEDDED = 0x6E, + + // Unimplemented commands + RSI_WLAN_REQ_SET_SLEEP_TIMER = 0x16, + RSI_WLAN_REQ_CFG_SAVE = 0x20, + RSI_WLAN_REQ_AUTO_CONFIG_ENABLE = 0x21, + RSI_WLAN_REQ_GET_CFG = 0x22, + RSI_WLAN_REQ_USER_STORE_CONFIG = 0x23, + RSI_WLAN_REQ_SET_WEP_KEYS = 0x25, + RSI_WLAN_REQ_SET_PROFILE = 0x31, + RSI_WLAN_REQ_GET_PROFILE = 0x32, + RSI_WLAN_REQ_DELETE_PROFILE = 0x33, + RSI_WLAN_REQ_SET_MULTICAST_FILTER = 0x40, + RSI_WLAN_REQ_CONNECTION_STATUS = 0x48, + RSI_WLAN_REQ_CONFIGURE_P2P = 0x4B, + RSI_WLAN_REQ_WIRELESS_FWUP = 0x59, + RSI_WLAN_REQ_HT_CAPABILITIES = 0x6D, + RSI_WLAN_REQ_REJOIN_PARAMS = 0x6F, + RSI_WLAN_REQ_WMM_PS = 0x97, + RSI_WLAN_REQ_FWUP = 0x99, +#ifdef RSI_WAC_MFI_ENABLE + RSI_WLAN_REQ_ADD_MFI_IE = 0xB5, +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + RSI_WLAN_REQ_CERT_VALID = 0xBC, +#endif + RSI_WLAN_REQ_FREQ_OFFSET = 0xF3, + RSI_WLAN_REQ_DYNAMIC_POOL = 0xC7, + RSI_WLAN_REQ_MDNSD = 0xDB, + RSI_WLAN_REQ_GET_DPD_DATA = 0xDC, + RSI_WLAN_REQ_FTP = 0xE2, + RSI_WLAN_REQ_FTP_FILE_WRITE = 0xE3, + RSI_WLAN_REQ_SMTP_CLIENT = 0xE6, + RSI_WLAN_REQ_OTA_FWUP = 0xEF, + RSI_WLAN_REQ_WEBPAGE_LOAD = 0x50, + RSI_WLAN_REQ_JSON_LOAD = 0x9c, + RSI_WLAN_REQ_WEBPAGE_ERASE = 0x9A, + RSI_WLAN_REQ_JSON_OBJECT_ERASE = 0x9B, + RSI_WLAN_REQ_WEBPAGE_CLEAR_ALL = 0x7F, + RSI_WLAN_REQ_HOST_WEBPAGE_SEND = 0x56, + RSI_WLAN_REQ_GET_RANDOM = 0xF8, + RSI_WLAN_REQ_POP3_CLIENT = 0xE7, + RSI_WLAN_REQ_DHCP_USER_CLASS = 0xEC, + RSI_WLAN_REQ_TIMEOUT = 0xEA, + RSI_WLAN_REQ_GET_STATS = 0xF1, + RSI_WLAN_REQ_UPDATE_TCP_WINDOW = 0xF5, + RSI_WLAN_REQ_DNS_UPDATE = 0xED, + RSI_WLAN_REQ_DNS_SERVER_ADD = 0x55, + RSI_WLAN_REQ_TSF = 0x65, + RSI_WLAN_REQ_SET_TRANSCEIVER_CHANNEL = 0x7A, + RSI_WLAN_REQ_TRANSCEIVER_PEER_LIST_UPDATE = 0x8B, + RSI_WLAN_REQ_TRANSCEIVER_CONFIG_PARAMS = 0x8C, + RSI_WLAN_REQ_SET_TRANSCEIVER_MCAST_FILTER = 0x8D, + RSI_WLAN_REQ_TRANSCEIVER_FLUSH_DATA_Q = 0x8E, +} rsi_wlan_cmd_request_t; + +// enumeration for WLAN command response codes +typedef enum { + // Wi-Fi command response + RSI_WLAN_RSP_BAND = 0x11, + RSI_WLAN_RSP_INIT = 0x12, + RSI_WLAN_RSP_SCAN = 0x13, + RSI_WLAN_RSP_JOIN = 0x14, + RSI_WLAN_RSP_SET_MAC_ADDRESS = 0x17, + RSI_WLAN_RSP_QUERY_NETWORK_PARAMS = 0x18, + RSI_WLAN_RSP_DISCONNECT = 0x19, + RSI_WLAN_RSP_AP_STOP = 0xAE, + RSI_WLAN_RSP_SET_REGION = 0x1D, + RSI_WLAN_RSP_AP_CONFIGURATION = 0x24, + RSI_WLAN_RSP_TWT_AUTO_CONFIG = 0x2E, + RSI_WLAN_RSP_TWT_PARAMS = 0x2F, + SL_WIFI_RSP_RESCHEDULE_TWT = 0x3F, + RSI_WLAN_RSP_EVM_OFFSET = 0x36, + RSI_WLAN_RSP_EVM_WRITE = 0x37, + RSI_WLAN_RSP_RSSI = 0x3A, + RSI_WLAN_RSP_GAIN_TABLE = 0x47, + RSI_WLAN_RSP_FW_VERSION = 0x49, + RSI_WLAN_RSP_MAC_ADDRESS = 0x4A, + RSI_WLAN_RSP_EAP_CONFIG = 0x4C, + RSI_WLAN_RSP_SET_CERTIFICATE = 0x4D, + RSI_WLAN_RSP_QUERY_GO_PARAMS = 0x4E, + RSI_WLAN_RSP_BEACON_STOP = 0x63, + RSI_WLAN_RSP_BG_SCAN = 0x6A, + RSI_WLAN_RSP_EXT_STATS = 0x68, // Neither part 22q2 nor alpha 2 + RSI_WLAN_RSP_EFUSE_READ = 0x73, + RSI_WLAN_RSP_TX_TEST_MODE = 0x7C, + RSI_WLAN_RSP_ROAM_PARAMS = 0x7B, + RSI_WLAN_RSP_RADIO = 0x81, + RSI_WLAN_RSP_RX_STATS = 0xA2, + RSI_WLAN_RSP_HOST_PSK = 0xA5, + RSI_WLAN_RSP_SCAN_RESULTS = 0xAF, + RSI_WLAN_RSP_CONFIG = 0XBE, + RSI_WLAN_RSP_SET_REGION_AP = 0xBD, + RSI_WLAN_RSP_FILTER_BCAST_PACKETS = 0xC9, + RSI_WLAN_RSP_CALIB_READ = 0xCF, + RSI_WLAN_RSP_FULL_FW_VERSION = 0xE0, + RSI_WLAN_RSP_GET_STATS = 0xF1, + RSI_WLAN_RSP_HTTP_OTAF = 0xF4, + RSI_WLAN_RSP_11AX_PARAMS = 0xFF, + + // Network command response + RSI_WLAN_RSP_PING_PACKET = 0x29, + RSI_WLAN_RSP_IPCONFV4 = 0x41, + RSI_WLAN_RSP_DNS_QUERY = 0x44, + RSI_WLAN_RSP_HTTP_CLIENT_GET = 0x51, + RSI_WLAN_RSP_HTTP_CLIENT_POST = 0x52, + RSI_WLAN_RSP_HTTP_CLIENT_PUT = 0x53, + RSI_WLAN_RSP_IPCONFV6 = 0xA1, + RSI_WLAN_RSP_MULTICAST = 0xB1, + RSI_WLAN_RSP_HTTP_ABORT = 0xB3, + RSI_WLAN_RSP_HTTP_CREDENTIALS = 0xB4, + RSI_WLAN_RSP_EMB_MQTT_CLIENT = 0xCB, + RSI_WLAN_RSP_SNTP_CLIENT = 0xE4, + RSI_WLAN_RSP_HTTP_CLIENT_POST_DATA = 0xEB, + + // Socket command response + RSI_WLAN_RSP_SOCKET_CREATE = 0x42, + RSI_WLAN_RSP_SOCKET_CLOSE = 0x43, + RSI_WLAN_RSP_SOCKET_READ_DATA = 0x6B, + RSI_WLAN_RSP_SOCKET_ACCEPT = 0x6C, + RSI_WLAN_RSP_SOCKET_CONFIG = 0xA7, + RSI_WLAN_RSP_SELECT_REQUEST = 0x74, + RSI_WLAN_RSP_SET_SNI_EMBEDDED = 0x6E, + + // Unimplemented command for 22q2 + RSI_WLAN_RSP_CLEAR = 0x00, + RSI_WLAN_RSP_CFG_SAVE = 0x20, + RSI_WLAN_RSP_AUTO_CONFIG_ENABLE = 0x21, + RSI_WLAN_RSP_GET_CFG = 0x22, + RSI_WLAN_RSP_USER_STORE_CONFIG = 0x23, + RSI_WLAN_RSP_SET_WEP_KEYS = 0x25, + RSI_WLAN_RSP_P2P_CONNECTION_REQUEST = 0x30, + RSI_WLAN_RSP_SET_PROFILE = 0x31, + RSI_WLAN_RSP_GET_PROFILE = 0x32, + RSI_WLAN_RSP_DELETE_PROFILE = 0x33, + RSI_WLAN_RSP_CONN_ESTABLISH = 0x61, + RSI_WLAN_RSP_REMOTE_TERMINATE = 0x62, + RSI_WLAN_RSP_IPV4_CHANGE = 0xAA, + RSI_WLAN_RSP_TCP_ACK_INDICATION = 0xAB, + RSI_WLAN_RSP_UART_DATA_ACK = 0xAC, + RSI_WLAN_RSP_SET_MULTICAST_FILTER = 0x40, + RSI_WLAN_RSP_DNS_UPDATE = 0xED, + RSI_WLAN_RSP_CONNECTION_STATUS = 0x48, + RSI_WLAN_RSP_CONFIGURE_P2P = 0x4B, + RSI_WLAN_RSP_WFD_DEVICE = 0x54, + RSI_WLAN_RSP_DNS_SERVER_ADD = 0x55, + RSI_WLAN_RSP_WIRELESS_FWUP_OK = 0x59, + RSI_WLAN_RSP_WIRELESS_FWUP_DONE = 0x5A, + RSI_WLAN_RSP_HT_CAPABILITIES = 0x6D, + RSI_WLAN_RSP_REJOIN_PARAMS = 0x6F, + RSI_WLAN_RSP_WPS_METHOD = 0x72, + RSI_WLAN_RSP_WMM_PS = 0x97, + RSI_WLAN_RSP_FWUP = 0x99, +#ifdef RSI_WAC_MFI_ENABLE + RSI_WLAN_RSP_ADD_MFI_IE = 0xB5, +#endif +#ifndef SLI_SI91X_MCU_INTERFACE + RSI_WLAN_RSP_CERT_VALID = 0xBC, +#endif + RSI_WLAN_RSP_CLIENT_CONNECTED = 0xC2, + RSI_WLAN_RSP_CLIENT_DISCONNECTED = 0xC3, + RSI_WLAN_RSP_FREQ_OFFSET = 0xF3, + RSI_WLAN_RSP_CALIB_WRITE = 0xCA, + RSI_WLAN_RSP_DYNAMIC_POOL = 0xC7, + RSI_WLAN_RSP_EMB_MQTT_PUBLISH_PKT = 0xCC, + RSI_WLAN_RSP_MQTT_REMOTE_TERMINATE = 0xF0, + RSI_WLAN_RSP_MDNSD = 0xDB, + RSI_WLAN_RSP_GET_DPD_DATA = 0xDC, + RSI_WLAN_RSP_FTP = 0xE2, + RSI_WLAN_RSP_FTP_FILE_WRITE = 0xE3, + RSI_WLAN_RSP_SNTP_SERVER = 0xE5, + RSI_WLAN_RSP_SMTP_CLIENT = 0xE6, + RSI_WLAN_RSP_OTA_FWUP = 0xEF, + RSI_WLAN_RSP_WEBPAGE_LOAD = 0x50, + RSI_WLAN_RSP_JSON_LOAD = 0x9c, + RSI_WLAN_RSP_WEBPAGE_ERASE = 0x9A, + RSI_WLAN_RSP_JSON_OBJECT_ERASE = 0x9B, + RSI_WLAN_RSP_WEBPAGE_CLEAR_ALL = 0x7F, + RSI_WLAN_RSP_HOST_WEBPAGE_SEND = 0x56, + RSI_WLAN_RSP_JSON_UPDATE = 0x9D, + RSI_WLAN_RSP_GET_RANDOM = 0xF8, + RSI_WLAN_RSP_ASYNCHRONOUS = 0xFF, + RSI_WLAN_RSP_JSON_EVENT = 0xEE, + RSI_WLAN_RSP_POP3_CLIENT = 0xE7, + RSI_WLAN_RSP_POP3_CLIENT_TERMINATE = 0xE8, + RSI_WLAN_RSP_DHCP_USER_CLASS = 0xEC, + RSI_WLAN_RSP_TIMEOUT = 0xEA, + RSI_WLAN_RSP_URL_REQUEST = 0x64, + RSI_WLAN_RSP_MODULE_STATE = 0x70, + RSI_WLAN_RSP_TWT_ASYNC = 0x71, + RSI_WLAN_RSP_UPDATE_TCP_WINDOW = 0xF5, + RSI_WLAN_RSP_TSF = 0x65, + RSI_WLAN_RSP_TRANSCEIVER_SET_CHANNEL = 0x7A, + RSI_WLAN_RSP_TRANSCEIVER_PEER_LIST_UPDATE = 0x8B, + RSI_WLAN_RSP_TRANSCEIVER_CONFIG_PARAMS = 0x8C, + RSI_WLAN_RSP_TRANSCEIVER_SET_MCAST_FILTER = 0x8D, + RSI_WLAN_RSP_TRANSCEIVER_FLUSH_DATA_Q = 0x8E, + RSI_WLAN_RSP_TRANSCEIVER_TX_DATA_STATUS = 0x3D, + SL_SI91X_WIFI_RX_DOT11_DATA = 0x03, + // Unimplemented commands after 22Q2 + RSI_WLAN_RATE_RSP_STATS = 0x88 +} rsi_wlan_cmd_response_t; + +typedef enum { SET_REGION_CODE_FROM_BEACONS, SET_REGION_CODE_FROM_USER } si91x_set_region_code_command_t; + +typedef enum { SL_SI91X_SOCKET_REMOTE_TERMINATED_EVENT, SL_SI91X_SOCKET_EVENT_COUNT } sl_si91x_socket_event_t; + +typedef enum { SL_SI91X_NO_ENCRYPTION, SL_SI91X_TKIP_ENCRYPTION, SL_SI91X_CCMP_ENCRYPTION } sl_si91x_encryption_t; +//! @endcond \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h new file mode 100644 index 000000000..a59e30889 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_core_utilities.h @@ -0,0 +1,163 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once +#include "sl_si91x_types.h" +#include "sl_wifi_device.h" +#include "sl_additional_status.h" + +/****************************************************************************** + * A utility function to extract firmware status from RX packet. + * The extracted firmware status can be given to convert_and_save_firmware_status() to get sl_status equivalent. + * @param packet packet that contains the frame status which needs to be extracted. + * @return frame status + *****************************************************************************/ +static inline uint16_t get_si91x_frame_status(const sl_si91x_packet_t *packet) +{ + return (uint16_t)(packet->desc[12] + (packet->desc[13] << 8)); +} + +/****************************************************************************** + * @brief + * A utility function that converts frame status sent by firmware to sl_status_t and stores in thread local storage of caller thread. + * @param[in] si91x_firmware_status + * si91x_firmware_status that needs to be converted to sl_status_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + *****************************************************************************/ +static inline sl_status_t convert_and_save_firmware_status(uint16_t si91x_firmware_status) +{ + sl_status_t converted_firmware_status = (si91x_firmware_status == SL_STATUS_OK) ? SL_STATUS_OK + : (si91x_firmware_status | BIT(16)); + return converted_firmware_status; +} +/****************************************************************************** + * @brief + * A utility function that converts si91x_status_t to sl_status_t + * @param[in] si91x_status + * si91x_status that needs to be converted to sl_status_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + *****************************************************************************/ +static inline sl_status_t convert_si91x_status_to_sl_status(si91x_status_t si91x_status) +{ + switch (si91x_status) { + case RSI_ERROR_NONE: + return SL_STATUS_OK; + case RSI_ERROR_TIMEOUT: + return SL_STATUS_TIMEOUT; + case RSI_ERROR_INVALID_PARAM: + return SL_STATUS_INVALID_PARAMETER; + case RSI_ERROR_COMMAND_GIVEN_IN_WRONG_STATE: + return SL_STATUS_INVALID_STATE; + case RSI_ERROR_PKT_ALLOCATION_FAILURE: + return SL_STATUS_ALLOCATION_FAILED; + case RSI_ERROR_COMMAND_NOT_SUPPORTED: + return SL_STATUS_NOT_SUPPORTED; + case RSI_ERROR_INSUFFICIENT_BUFFER: + return SL_STATUS_NO_MORE_RESOURCE; + case RSI_ERROR_IN_OS_OPERATION: + return SL_STATUS_OS_OPERATION_FAILURE; + case RSI_ERROR_BOOTUP_OPTIONS_NOT_SAVED: + return SL_STATUS_BOOTUP_OPTIONS_NOT_SAVED; + case RSI_ERROR_BOOTLOADER_VERSION_NOT_MATCHING: + return SL_STATUS_BOOTLOADER_VERSION_MISMATCH; + case RSI_ERROR_WAITING_FOR_BOARD_READY: + return SL_STATUS_WAITING_FOR_BOARD_READY; + case RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT: + return SL_STATUS_VALID_FIRMWARE_NOT_PRESENT; + case RSI_ERROR_INVALID_OPTION: + return SL_STATUS_INVALID_OPTION; + case RSI_ERROR_SPI_BUSY: + return SL_STATUS_SPI_BUSY; + case RSI_ERROR_CARD_READY_TIMEOUT: + return SL_STATUS_CARD_READY_TIMEOUT; + case RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT: + return SL_STATUS_FW_LOAD_OR_UPGRADE_TIMEOUT; + default: + return SL_STATUS_FAIL; + } +} + +/** + * @brief Atomically append a given buffer to the end of a buffer queue. + * + * This function appends a buffer to the end of a specified buffer queue in an atomic operation, + * ensuring thread safety during the append operation. + * + * @param[in] queue Pointer to the destination buffer queue where the buffer will be appended. + * @param[in] buffer Pointer to the buffer that is to be appended to the queue. + */ +void sli_si91x_append_to_buffer_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t *buffer); + +/** + * @brief Atomically remove the head buffer from a buffer queue. + * + * This function removes the buffer at the head of the specified buffer queue in an atomic operation, + * ensuring thread safety during the removal. The removed buffer is then passed back through a pointer + * to the caller. + * + * @param[in] queue Pointer to the source buffer queue from which the head buffer will be removed. + * @param[out] buffer Pointer to a pointer of sl_wifi_buffer_t where the removed buffer's address will be stored. + * @return sl_status_t Returns the status of the operation. A value of 0 (SL_STATUS_OK) indicates success. + * Other values indicate failure. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + */ +sl_status_t sli_si91x_pop_from_buffer_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t **buffer); + +/** + * @brief + * Allocate a buffer to send a command + * @param[out] host_buffer + * Destination buffer object + * @param[out] buffer + * Start of the internal buffer data + * @param[in] requested_buffer_size + * Requested buffer size + * @param[in] wait_duration_ms + * Duration to wait for buffer to become available + * @return sl_status_t Returns the status of the operation. A value of 0 (SL_STATUS_OK) indicates success. + * Other values indicate failure. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + */ +sl_status_t sli_si91x_allocate_command_buffer(sl_wifi_buffer_t **host_buffer, + void **buffer, + uint32_t requested_buffer_size, + uint32_t wait_duration_ms); + +/****************************************************************************** + * @brief + * Check if buffer queue is empty + * @param[in] queue + * Requested buffer size + * @return + * true if empty; false if not empty. + *****************************************************************************/ +static inline bool sli_si91x_buffer_queue_empty(sl_si91x_buffer_queue_t *queue) +{ + return (queue->head == NULL); +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h new file mode 100644 index 000000000..5a8fd1722 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_driver.h @@ -0,0 +1,1292 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_wifi_device.h" +#include "sl_wifi_host_interface.h" +#include "sl_si91x_host_interface.h" +#include "sl_rsi_utility.h" +#include "sl_si91x_constants.h" +#include "cmsis_os2.h" + +//! @cond Doxygen_Suppress +#define VERIFY_STATUS(s) \ + do { \ + if (s != SL_STATUS_OK) \ + return s; \ + } while (0) + +/** + * All flags used in si91x event mask + * There are three main groups of flags, each with SL_SI91X_COMMAND_TYPE_COUNT number of unique flags + */ +#define SL_SI91X_TX_PENDING_FLAG(x) (1 << (x)) +#define SL_SI91X_RESPONSE_FLAG(x) (1 << (SI91X_CMD_MAX + x)) +#define SL_SI91X_EXTRA_EVENT_FLAG(x) (1 << (SI91X_CMD_MAX + SI91X_CMD_MAX + x)) + +//! TX Flags +#define SL_SI91X_COMMON_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_COMMON_CMD) +#define SL_SI91X_WLAN_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_WLAN_CMD) +#define SL_SI91X_NETWORK_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_NETWORK_CMD) +#define SL_SI91X_BT_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_BT_CMD) +#define SL_SI91X_GENERIC_SOCKET_TX_PENDING_EVENT SL_SI91X_TX_PENDING_FLAG(SI91X_SOCKET_CMD) + +// Indicates RX response received for COMMON command type +#define NCP_HOST_COMMON_RESPONSE_EVENT SL_SI91X_RESPONSE_FLAG(SI91X_COMMON_CMD) + +// Indicates synchronous RX response received for WLAN command type +#define NCP_HOST_WLAN_RESPONSE_EVENT SL_SI91X_RESPONSE_FLAG(SI91X_WLAN_CMD) + +// Indicates synchronous RX response received for NETWORK command type +#define NCP_HOST_NETWORK_RESPONSE_EVENT SL_SI91X_RESPONSE_FLAG(SI91X_NETWORK_CMD) + +// Indicates RX response received for SOCKET command type +#define NCP_HOST_SOCKET_RESPONSE_EVENT SL_SI91X_RESPONSE_FLAG(SI91X_SOCKET_CMD) + +// Indicates RX response received for BLE command type +#define NCP_HOST_BT_RESPONSE_EVENT SL_SI91X_RESPONSE_FLAG(SI91X_BT_CMD) + +// Triggered by IRQ to indicate something to read +#define SL_SI91X_NCP_HOST_BUS_RX_EVENT SL_SI91X_EXTRA_EVENT_FLAG(0) +#define SL_SI91X_SOCKET_DATA_TX_PENDING_EVENT SL_SI91X_EXTRA_EVENT_FLAG(1) +#define SL_SI91X_SOCKET_COMMAND_TX_PENDING_EVENT SL_SI91X_EXTRA_EVENT_FLAG(2) +#define SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT SL_SI91X_EXTRA_EVENT_FLAG(3) +#define SL_SI91X_TA_BUFFER_FULL_CLEAR_EVENT SL_SI91X_EXTRA_EVENT_FLAG(4) +#define SL_SI91X_TERMINATE_BUS_THREAD_EVENT (1 << 21) +#define SL_SI91X_TERMINATE_BUS_THREAD_EVENT_ACK (1 << 22) + +#define SL_SI91X_ALL_TX_PENDING_COMMAND_EVENTS \ + (SL_SI91X_COMMON_TX_PENDING_EVENT | SL_SI91X_WLAN_TX_PENDING_EVENT | SL_SI91X_NETWORK_TX_PENDING_EVENT \ + | SL_SI91X_BT_TX_PENDING_EVENT | SL_SI91X_GENERIC_SOCKET_TX_PENDING_EVENT) + +typedef enum { SL_NCP_NORMAL_POWER_MODE, SL_NCP_LOW_POWER_MODE, SL_NCP_ULTRA_LOW_POWER_MODE } sl_si91x_power_mode_t; + +typedef struct sl_si91x_power_configuration sl_si91x_power_configuration_t; +//! @endcond + +/***************************************************************************/ /** + * @brief + * Initialize the driver. + * @param[in] config + * @ref sl_wifi_device_configuration_t Pointer to device configuration. + * @param[in] event_handler + * [sl_wifi_event_handler_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-types#sl-wifi-event-handler-t) Function pointer to receive asynchronous events. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_init(const sl_wifi_device_configuration_t *config, sl_wifi_event_handler_t event_handler); + +/***************************************************************************/ /** + * @brief + * De-initialize the driver. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_deinit(void); + +//! @cond Doxygen_Suppress +/***************************************************************************/ /** + * @brief + * Register a function and optional argument for scan results callback. + * @param[in] command + * Command type to be sent to NWP firmware. + * @param[in] queue_type + * @ref sl_si91x_command_type_t Command type + * @param[in] data + * Command packet to be sent to the NWP firmware. + * @param[in] data_length + * Length of command packet. + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Timeout for the command response. + * @param[in] sdk_context + * Pointer to the context. + * @param[in] data_buffer + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Pointer to a data buffer pointer for the response data to be returned in. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_command(uint32_t command, + sl_si91x_command_type_t queue_type, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer); + +/***************************************************************************/ /** + * @brief + * Register a function and optional argument for scan results callback. + * @param[in] command + * Command type to be sent to NWP firmware. + * @param[in] data + * Command packet to be sent to the NWP firmware. + * @param[in] data_length + * Length of command packet. + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Timeout for the command response. + * @pre + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_side_band_crypto(uint32_t command, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period); + +/***************************************************************************/ /** + * @brief + * Send commands to the NWP; whose response needs to be handled asynchronously. + * Note: This function doesn't acquire "command_in_flight" boolean + * @param[in] command + * Command type to be sent to NWP firmware. + * @param[in] queue_type + * @ref sl_si91x_command_type_t Command type + * @param[in] data + * Command packet to be sent to the NWP firmware. + * @param[in] data_length + * Length of the command packet. + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_async_command(uint32_t command, + sl_si91x_command_type_t queue_type, + void *data, + uint32_t data_length); +/***************************************************************************/ /** + * @brief + * Wait for a command response. + * @param[in] command + * @ref rsi_wlan_cmd_request_t Command type to wait . + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Wait time in milliseconds to wait for command response. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_wait_for_response(rsi_wlan_cmd_request_t command, sl_si91x_wait_period_t wait_period); + +/***************************************************************************/ /** + * @brief + * Send a socket command. + * @param[in] request + * @ref sli_si91x_socket_send_request_t Pointer to socket command packet. + * @param[in] data + * Pointer to socket data. + * @param[in] wait_time + * Timeout for the command response. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_socket_data(const sli_si91x_socket_send_request_t *request, + const void *data, + uint32_t wait_time); + +/***************************************************************************/ /** + * @brief + * Send a Bluetooth command. + * @param[in] command + * @ref rsi_wlan_cmd_request_t Command type to be sent. + * @param[in] queue_type + * @ref sl_si91x_command_type_t Command type. + * @param[in] data + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Pointer to Bluetooth data. + * @param[in] sync_command + * Sync or Async command. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_send_bt_command(rsi_wlan_cmd_request_t command, + sl_si91x_command_type_t command_type, + sl_wifi_buffer_t *data, + uint8_t sync_command); +//! @endcond + +/***************************************************************************/ /** + * @brief + * Load a certificate into a specified index. + * @param[in] certificate_type + * Type of certificate being loaded + * @param[in] certificate_index + * Index where the certificate is to be loaded. + * @param[in] buffer + * Pointer to the buffer containing the certificate to be loaded. + * @param[in] certificate_length + * Length of the certificate buffer. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_wifi_set_certificate_index(uint8_t certificate_type, + uint8_t certificate_index, + const uint8_t *buffer, + uint32_t certificate_length); + +/** \addtogroup SL_SI91X_TYPES + * @{ */ +/// Firmware version information +typedef struct { + uint8_t chip_id; ///< Chip ID + uint8_t rom_id; ///< ROM ID + uint8_t major; ///< Major version number + uint8_t minor; ///< Minor version number + uint8_t security_version; ///< Security enabled or disabled + uint8_t patch_num; ///< Patch number + uint8_t customer_id; ///< Customer ID + uint16_t build_num; ///< Build number +} sl_si91x_firmware_version_t; + +/// Network wirless processor (NWP) configuration structure +typedef struct { + uint32_t code; ///< Configuration code. The possible values are: + ///< - SL_SI91X_XO_CTUNE_FROM_HOST + ///< - SL_SI91X_ENABLE_NWP_WDT_FROM_HOST + ///< - SL_SI91X_DISABLE_NWP_WDT_FROM_HOST + union { + uint8_t config_val; ///< Configuration value as per the code selected above. + // Below structure is used in case of SL_SI91X_ENABLE_NWP_WDT_FROM_HOST + struct { + uint8_t wdt_timer_val; ///< Timer value in seconds for the watchdog timer. + uint8_t wdt_enable_in_ps; ///< Enable watchdog timer in power save mode. + }; + } values; ///< Values +} sl_si91x_nwp_configuration_t; + +/// NWP get configuration structure +typedef struct { + uint32_t sub_command_type; ///< Requested configuration. Currently, only `GET_OPN_BOARD_CONFIG` is supported. +} sl_si91x_nwp_get_configuration_t; + +/// Assertion structure +typedef struct { + sl_si91x_assertion_type_t assert_type; ///< Assertion type. It must be in the range of 0 to 15 (both included). + sl_si91x_assertion_level_t assert_level; ///< Assertion level. It must be in the range of 0 to 15 (both included). +} sl_si91x_assertion_t; +/** @} */ + +/** \addtogroup SI91X_DRIVER_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ +/***************************************************************************/ /** + * @brief + * Sets the Real Time Clock (RTC) of the module. + * + * @details + * This function sets the RTC time of the module using the provided @ref sl_si91x_module_rtc_time_t structure. + * It is a blocking call, meaning it will wait until the operation is complete before returning. + * + * @param[in] timer + * Pointer to an @ref sl_si91x_module_rtc_time_t structure that contains the RTC time to be set. + * + * @pre + * Pre-conditions: + * - The [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) API must be called prior to this API. + * - The @ref SL_SI91X_CUSTOM_FEAT_RTC_FROM_HOST bit must be enabled in the @ref SI91X_CUSTOM_FEATURE_BITMAP during the [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) process. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * Ensure that the Real-Time Clock (RTC) timer is configured to enable SSL certificate validation. + ******************************************************************************/ +sl_status_t sl_si91x_set_rtc_timer(const sl_si91x_module_rtc_time_t *timer); + +/***************************************************************************/ /** + * @brief + * Retrieves the current time from the module's Real Time Clock (RTC). + * + * @details + * This function fetches the current time from the module's RTC and stores it in the provided @ref sl_si91x_module_rtc_time_t structure. + * It is a blocking call, meaning it will wait until the operation is complete before returning. + * + * @param[out] response + * Pointer to an @ref sl_si91x_module_rtc_time_t structure where the RTC's current time will be stored. + * @pre + * Pre-conditions: + * - The @ref sl_si91x_set_rtc_timer() API must be called to set the RTC time before attempting to retrieve it. + * - The @ref SL_SI91X_CUSTOM_FEAT_RTC_FROM_HOST bit must be enabled in the @ref SI91X_CUSTOM_FEATURE_BITMAP during the [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) process to allow RTC time setting and retrieval from the host. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_rtc_timer(sl_si91x_module_rtc_time_t *response); + +#if defined(SLI_SI91X_MCU_INTERFACE) || defined(DOXYGEN) +/*==============================================*//** + * @brief + * Sends M4 specific commands to NWP to access shared resources such as flash, XTAL etc. + * + * @details + * This function sends M4 specific commands using the specified sub-command type and input data. + * + * This is a blocking API. + * + * In SoC mode, this API only sends commands from the M4 core to the TA core. + * + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[in] sub_cmd_type + * Specifies the sub-command type for the secure handshake. + * + * @param[in] input_data + * Pointer to the input data that contains the information used during the secure handshake. + * + * @param[in] input_len + * Specifies the length of the input data. + * + * @param[in] output_len + * Specifies the length of the output data. + * + * @param[out] output_data + * Pointer to a buffer where the response data will be stored after the secure handshake process. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * The `output_len` and `output_data` parameters are currently unused and reserved for future use. + * @note + * This API is only applicable in SoC mode. + * @note + * - Currently, only `SL_SI91X_ENABLE_XTAL` is supported for `sub_cmd_type`. + * - `SL_SI91X_ENABLE_XTAL` is of `uint8_t` datatype and user can pass 1 to enable and 0 to disable it. + * - For alarm based sleep wakeup applications, `SL_SI91X_ENABLE_XTAL` is used to enable/disable the XTAL. + ***************************************************/ +sl_status_t sl_si91x_m4_ta_secure_handshake(uint8_t sub_cmd_type, + uint8_t input_len, + const uint8_t *input_data, + uint8_t output_len, + const uint8_t *output_data); +#endif + +/***************************************************************************/ /** + * @brief + * Sets different timeouts given by sl_si91x_timeout_type_t for the Si91x device. + * + * @details + * This API configures various timeout settings such as authentication, association, channel active scan, + * channel passive scan timeout, and keep-alive timeout for the module. + * The timeout type determines the specific timeout being set, and the timeout value specifies the duration. + * + * @pre + * This API should be called after [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init). + * + * @param[in] timeout_type + * Identifies which timeout type to set. Possible values are defined in @ref sl_si91x_timeout_type_t. + * + * @param[in] timeout_value + * The timeout value to set. The time resolution depends on the timeout_type. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * - After a successful IP configuration, Gratuitous ARP is used as the periodic WLAN Keep-Alive packet with the configured keep_alive_timeout interval. + * - If there is no IP configuration, NULL Data Packets are used as the WLAN Keep-Alive packet. + * - As an alternative, users can use @ref sl_si91x_set_timeout to set all timeouts before calling `sl_wifi_init()`. + *******************************************************************************/ +sl_status_t sl_si91x_configure_timeout(sl_si91x_timeout_type_t timeout_type, uint16_t timeout_value); + +/***************************************************************************/ /** + * @brief + * Sets different module timeouts in a single call for the Si91X device. + * + * @details + * This API sets all the timeout configurations in a single call. + * It includes settings for the active channel scan timeout, authentication association timeout, and keep-alive timeout for the module. + * + * @param[in] timeout_config + * Timeout configuration of type @ref sl_si91x_timeout_t. + * + * @note + * - This API should ONLY be called before [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init). + * - Repeated calls to this API will overwrite the timeout values stored in the SDK and will be applied on the next call to [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init). + * - As an alternative, users can set individual timeouts using @ref sl_si91x_configure_timeout() after calling `sl_wifi_init()`. +*******************************************************************************/ +void sl_si91x_set_timeout(const sl_si91x_timeout_t *timeout_config); + +/***************************************************************************/ /** + * @brief + * Retrieves TA RAM log/dump via Si91x UART/UART2. + * + * @details + * This function reads a chunk of data from the specified address in the Si91x module's RAM via UART or UART2. + * It is useful for debugging purposes by allowing access to the RAM log or dump. + * + * Selection of debug UART can be done by using @ref SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS + * + * @param[in] address + * Address in Si91x module from which to start reading. + * + * @param[in] length + * Length of the chunk to read from the Si91x module. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_ram_log(uint32_t address, uint32_t length); + +/***************************************************************************/ +/** + * @brief + * Allows the Network Processor (NWP) to write content to the common flash from M4. + * + * @details + * This function enables the NWP to write data to the common flash memory from the M4 core. It is a blocking API. + * + * @param[in] write_address + * The address in the common flash memory where the write operation should begin. + * - For the M4 region, the write address should start from 0x8000000. Possible values range from the M4 image end address to the M4 region end address. + * - For the NWP region, the write address should range from 0 to (20K-1). + * - For sector erase, it should be multiples of 4K. + * + * @param[in] write_data + * Pointer to the data to be written. + * + * @param[in] write_data_length + * The total length of the data, which should be multiples of 4K for sector erase. + * + * @param[in] flash_sector_erase_enable + * Enable or disable sector erase. + * - 1: Erases multiples of 4 KB of data. + * - 0: Disable, allows writing data onto flash. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_command_to_write_common_flash(uint32_t write_address, + const uint8_t *write_data, + uint16_t write_data_length, + uint8_t flash_sector_erase_enable); + +/***************************************************************************/ /** + * @brief + * Sends a command to read data from the NWP flash memory of the SI91x wireless device. + * + * @details + * This function sends a command to the SI91x wireless device to read data from the NWP flash memory at the specified address. The read data is stored in the provided output buffer. + * + * This is a blocking API. + * + * @param[in] read_address + * The address in the NWP flash memory to read from. The address should range from 0 to (20K-1). + * + * @param[in] length + * The number of bytes to read from the NWP flash memory. + * + * @param[out] output_buffer + * Pointer to the buffer where the read data will be stored. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_command_to_read_common_flash(uint32_t read_address, size_t length, uint8_t *output_buffer); + +/***************************************************************************/ /** + * @brief + * Retrieve the firmware version currently installed on the SiWx91x device. + * + * @details + * This function retrieves the firmware version currently installed on the SiWx91x device. The version information is stored in the provided `sl_si91x_firmware_version_t` object. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[out] version + * Pointer to an `sl_si91x_firmware_version_t` object that will be populated with the firmware version information. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_firmware_version(sl_si91x_firmware_version_t *version); + +/***************************************************************************/ /** + * @brief + * Retrieve the firmware image size from the firmware image file. + * + * @details + * This function reads the firmware image file from the provided buffer and returns the size of the firmware image. + * + * This is a non-blocking API. + * + * @param[in] buffer + * Pointer to the buffer containing the firmware image file. + * + * @param[out] fw_image_size + * Pointer to a variable where the size of the firmware image will be stored. The value returned in this parameter is valid only if this API returns SL_STATUS_OK (0). + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_firmware_size(void *buffer, uint32_t *fw_image_size); + +/***************************************************************************/ +/** + * @brief + * Set configuration to NWP. + * + * @details + * This function sets the configuration for the Network Processor (NWP) based on the provided `sl_si91x_nwp_configuration_t` structure. + * + * The configuration values are determined by the `code` element of the structure. + * + * @pre Pre-conditions: + * - [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[in] nwp_config + * Configuration as identified by @ref sl_si91x_nwp_configuration_t. + * Possible values for `config.code` are defined below: + * - For `SL_SI91X_XO_CTUNE_FROM_HOST`: + * - `nwp_config.values.config_val` is used to configure NWP's XO Ctune value. + * - For `SL_SI91X_ENABLE_NWP_WDT_FROM_HOST`: + * - `nwp_config.values.wdt_timer_val` is used to configure the NWP WDT ISR timer, currently set to 32 seconds. + * - `nwp_config.values.wdt_enable_in_ps` is used to enable WDT in powersave mode. + * - For `SL_SI91X_DISABLE_NWP_WDT_FROM_HOST`: + * - Disables NWP WDT ISR timer. `nwp_config.values.config_val` is not utilized by the NWP. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_nwp_config_request(sl_si91x_nwp_configuration_t nwp_config); + +/***************************************************************************/ /** + * @brief + * Retrieve the configuration value from the firmware based on the requested sub_command_type element of `sl_si91x_nwp_get_configuration_t` structure. + * @pre Pre-conditions: + * - + * [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] nwp_config + * Configuration as identified by @ref sl_si91x_nwp_get_configuration_t. + * Possible values for nwp_config.sub_command_type are defined below: + * - For GET_OPN_BOARD_CONFIG: + * - nwp_config.sub_command_type is used to get board OPN part number. + * - OTP bits should be programmed with the board OPN part number otherwise the API will return NULL characters for OTP bits. + * - Currently, all other values are NOT SUPPORTED. + * @param[out] response + * Buffer to hold board OPN part number. The value returned in this param is valid only if this API returns SL_STATUS_OK(0). + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_get_nwp_config(const sl_si91x_nwp_get_configuration_t *nwp_config, uint8_t *response); + +/***************************************************************************/ /** + * @brief + * Debug prints on UART interfaces 1 and 2. Host can get 5 types of debug prints based on the assertion level and assertion type. This is a blocking API. + * @pre Pre-conditions: + * - + * [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] assertion + * Configuration as identified by @ref sl_si91x_assertion_t. + * - Assertion type (Possible values are 0 - 15): + * - 0000 (LMAC core) + * - 0001 (SME) + * - 0010 (UMAC) + * - 0100 (NETX) + * - 1000 (Enables assertion indication and provides ram dump in critical assertion) + * - Assertion level (Possible values are 0 - 15): + * - 0 is only for specific prints & 15 is to enable all prints. + * - 0000 (Assertion required) + * - 0010 (Recoverable) + * - 0100 (Information) + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + ******************************************************************************/ +sl_status_t sl_si91x_debug_log(sl_si91x_assertion_t *assertion); +/** @} */ + +/***************************************************************************/ /** + * @brief + * Configures the join feature bitmap for the Si91X device. + * + * @details + * This function sets the join feature bitmap configuration for the specified Wi-Fi interface. + * + * The join feature bitmap determines various connection parameters and behaviors. + * + * By default, the `SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID` bitmap is enabled. + * + * Users can call this API before calling [sl_wifi_connect](../wiseconnect-api-reference-guide-wi-fi/wifi-client-api#sl-wifi-connect), [sl_wifi_start_ap](../wiseconnect-api-reference-guide-wi-fi/wifi-ap-api#sl-wifi-start-ap), [sl_wifi_start_wps](../wiseconnect-api-reference-guide-wi-fi/wifi-wps-api#sl-wifi-start-wps) to overwrite the join feature bitmap. + * + * @param[in] interface + * The selected Wi-Fi interface. Refer to [sl_wifi_interface_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-constants#sl-wifi-interface-t) for possible values. + * + * @param[in] join_feature_bitmap + * The join feature bitmap configuration. One of the values from @ref SI91X_JOIN_FEATURE_BIT_MAP. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + *******************************************************************************/ +sl_status_t sl_si91x_set_join_configuration(sl_wifi_interface_t interface, uint8_t join_feature_bitmap); + +/***************************************************************************/ /** + * @brief + * Retrieves the join feature bitmap configuration for the Si91X device. + * + * @details + * This function gets the current join feature bitmap configuration for the specified Wi-Fi interface. + * The join feature bitmap determines various connection parameters and behaviors. + * + * By default, the `SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID` bitmap is enabled. + * + * @param[in] interface + * The selected Wi-Fi interface. Refer to [sl_wifi_interface_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-constants#sl-wifi-interface-t) for possible values. + * + * @param[out] join_feature_bitmap + * Pointer to a variable where the current join feature bitmap configuration will be stored. One or more values from @ref SI91X_JOIN_FEATURE_BIT_MAP. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + *******************************************************************************/ +sl_status_t sl_si91x_get_join_configuration(sl_wifi_interface_t interface, uint8_t *join_feature_bitmap); + +/***************************************************************************/ /** + * @brief + * Trigger an assert in firmware. + * + * @details + * This function is used to signal that an assertion has occurred in the firmware. It helps in debugging by indicating that a specific condition has failed. + * + * This is blocking API. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + *******************************************************************************/ +sl_status_t sl_si91x_assert(void); + +/***************************************************************************/ /** + * @brief + * Writes calibration data to non-volatile device memory. + * @param[in] data + * @ref si91x_calibration_data_t Pointer to buffer containing calibration data. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_write_calibration_data(const si91x_calibration_data_t *data); + +/** \addtogroup SI91X_RADIO_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ + +/***************************************************************************/ /** + * @brief + * Start the transmit test. + * + * @details + * This function starts the transmit test using the provided configuration. + * + * This is a blocking API. + * + * This API is relevant in PER mode + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[in] tx_test_info + * Pointer to an @ref sl_si91x_request_tx_test_info_t structure containing the configuration for the transmit test. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note Before starting Continuous Wave mode, user must start Continuous mode with power and channel values that are intended to be used in Continuous Wave mode i.e. \n + * - Start Continuous mode with intended power value and channel values - Pass any valid values for rate and length. + * - Stop Continuous mode + * - Start Continuous Wave mode + * @note If user wants to switch continuous wave mode, first need to stop the per mode and again need to give continous wave mode which user wants to switch. + ******************************************************************************/ +sl_status_t sl_si91x_transmit_test_start(const sl_si91x_request_tx_test_info_t *tx_test_info); + +/***************************************************************************/ +/** + * @brief + * Stop the transmit test. + * + * @details + * This function stops the ongoing transmit test on the Si91x device. + * + * This is a blocking API. + * + * This API is relevant in PER mode. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * User should configure a minimum delay (approx. 10 milliseconds) before and after @ref sl_si91x_transmit_test_start API to observe a stable output at requested dBm level. + ******************************************************************************/ +sl_status_t sl_si91x_transmit_test_stop(void); + +/***************************************************************************/ /** + * @brief + * Provide feedback of frequency error in KHz. + * + * @details + * This function provides feedback of the frequency error in KHz. The frequency error is specified using the `sl_si91x_freq_offset_t` structure. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[in] frequency_calibration + * Pointer to an @ref sl_si91x_freq_offset_t structure containing the frequency error in KHz. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + *******************************************************************************/ +sl_status_t sl_si91x_frequency_offset(const sl_si91x_freq_offset_t *frequency_calibration); + +/***************************************************************************/ /** + * @brief + * Set the device region. + * + * @details + * This function sets the operational region of the Si91x device. The region is specified using the `sl_si91x_region_code_t` enumeration. + * + * @param[in] operation_mode + * Operation mode of the device, specified by @ref sl_si91x_operation_mode_t. + * + * @param[in] band + * Operational band of the device, specified by @ref sl_si91x_band_mode_t. + * + * @param[in] region_code + * Region code to be set in the device, specified by @ref sl_si91x_region_code_t. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In FCC-certified SiWx91x ACx modules the behavior is as follows + * 1. For FCC-certified modules, using this API will result in an SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE error unless the module is in SL_SI91X_TRANSMIT_TEST_MODE. + * 2. STA mode channels 1 to 11 are actively scanned and 12,13,14 are passively scanned. + * 3. AP mode and Concurrent mode supports only 1 to 11 channels. + * 4. The AP will not broadcast the Country Information Element (IE). + ******************************************************************************/ +sl_status_t sl_si91x_set_device_region(sl_si91x_operation_mode_t operation_mode, + sl_si91x_band_mode_t band, + sl_si91x_region_code_t region_code); + +/***************************************************************************/ /** + * @brief + * Command the firmware to update the existing Flash/EFuse calibration data. + * + * @details + * This function commands the firmware to update the existing Flash/EFuse calibration data using the provided calibration configuration. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init), `sl_si91x_transmit_test_start`, and `sl_si91x_frequency_offset` should be called before this API. + * + * @param[in] calib_write + * Write calibration configuration of type @ref sl_si91x_calibration_write_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * Executing this API will overwrite calibration values in certified modules. + * In FCC-certified modules, this API will trigger an error SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE if used, except when in SL_SI91X_TRANSMIT_TEST_MODE mode. + ******************************************************************************/ +sl_status_t sl_si91x_calibration_write(sl_si91x_calibration_write_t calib_write); + +/***************************************************************************/ +/** + * @brief + * Read the calibration data from the Flash/EFuse storage. + * + * @details + * This function reads the calibration data from the specified storage (Flash or EFuse) and provides it in the `calibration_read` parameter. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[in] target + * Specifies the storage to read the calibration data from. + * - 0: READ_FROM_EFUSE (read calibration data from the EFuse) + * - 1: READ_FROM_FLASH (read calibration data from the Flash) + * + * @param[out] calibration_read + * Pointer to an @ref sl_si91x_calibration_read_t structure where the read calibration data will be stored. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_calibration_read(sl_si91x_calibration_read_t target, + sl_si91x_calibration_read_t *calibration_read); + +/***************************************************************************/ +/** + * @brief + * Provide feedback on the error caused by the EVM offset. + * + * @details + * This function provides feedback on the error caused by the Error Vector Magnitude (EVM) offset. The EVM offset is specified using the `sl_si91x_evm_offset_t` structure. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[in] evm_offset + * Pointer to an `sl_si91x_evm_offset_t` structure containing the EVM offset. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In FCC-certified modules, this API will trigger an error SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE if used, except when in SL_SI91X_TRANSMIT_TEST_MODE mode. + ******************************************************************************/ +sl_status_t sl_si91x_evm_offset(const sl_si91x_evm_offset_t *evm_offset); + +/***************************************************************************/ +/** + * @brief + * Command the firmware to update the existing Flash/EFuse calibration data. + * + * @details + * This function commands the firmware to update the existing Flash/EFuse calibration data using the provided EVM calibration configuration. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init), @ref sl_si91x_evm_offset, and @ref sl_si91x_transmit_test_start should be called before this API. + * + * @param[in] evm_write + * Pointer to an @ref sl_si91x_evm_write_t structure containing the EVM calibration configuration. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In FCC-certified modules, this API will trigger an error SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE if used, except when in SL_SI91X_TRANSMIT_TEST_MODE mode. + ******************************************************************************/ +sl_status_t sl_si91x_evm_write(const sl_si91x_evm_write_t *evm_write); + +/***************************************************************************/ /** + * @brief + * Command the firmware to read data from the Efuse memory location. + * + * @details + * This function commands the firmware to read data from the specified Efuse memory location. The data is read into the provided buffer. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @param[in] efuse_read + * Pointer to an `sl_si91x_efuse_read_t` structure, which contains the Efuse read address offset and read data length. + * + * @param[out] efuse_read_buf + * Pointer to a buffer where the read Efuse data will be stored. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + *******************************************************************************/ +sl_status_t sl_si91x_efuse_read(const sl_si91x_efuse_read_t *efuse_read, uint8_t *efuse_read_buf); + +/***************************************************************************/ /** + * @brief + * Update Flash/EFuse DPD data. + * + * @details + * This function updates the Flash/EFuse DPD (Digital Pre-Distortion) data using the provided DPD calibration data. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) and @ref sl_si91x_transmit_test_start should be called before this API. + * + * @param[in] dpd_calib_data + * Pointer to an @ref sl_si91x_get_dpd_calib_data_t structure containing the DPD calibration data. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In FCC-certified modules, this API will trigger an errorSL_STATUS_SI91X_FEATURE_NOT_AVAILABLE if used, except when in SL_SI91X_TRANSMIT_TEST_MODE mode. + ******************************************************************************/ +sl_status_t sl_si91x_dpd_calibration(const sl_si91x_get_dpd_calib_data_t *dpd_calib_data); + +/***************************************************************************/ /** + * @brief + * Enable wireless radio. + * + * @details + * This function enables the wireless radio on the Si91x device. + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_enable_radio(void); + +/***************************************************************************/ +/** + * @brief + * Disable wireless radio. + * + * @details + * This function disables the wireless radio on the Si91x device. + * + * @pre Pre-conditions: + * - [sl_wifi_init](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_disable_radio(void); + +/***************************************************************************/ /** + * @brief + * Set the Wi-Fi listen interval for the Si91x device. + * + * @details + * This function sets the Wi-Fi listen interval for the Si91x device. The listen interval determines how often the device wakes up to listen for beacon frames from the access point. + * + * @param[in] listen_interval + * Wi-Fi listen interval in milli seconds. + ******************************************************************************/ +void sl_si91x_set_listen_interval(uint32_t listen_interval); + +/** @} */ + +/***************************************************************************/ /** + * @brief + * Send a raw command frame. + * @param[in] command + * Command type to be sent. + * @param[in] data + * Pointer to the command data to be sent. + * @param[in] data_length + * Length of the data length + * @param[in] wait_time + * Wait time for the command response. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_driver_raw_send_command(uint8_t command, + const void *data, + uint32_t data_length, + uint32_t wait_time); + +//! @cond Doxygen_Suppress +/***************************************************************************/ /** + * @brief + * Set device power configuration. + * @param[in] mode + * @ref sl_si91x_power_mode_t Power mode to be set to the device. + * @param[in] config + * @ref sl_si91x_power_configuration_t Pointer to structure containing power configuration. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_power_mode(sl_si91x_power_mode_t mode, const sl_si91x_power_configuration_t *config); +//! @endcond + +/** \addtogroup SI91X_FIRMWARE_UPDATE_FROM_HOST_FUNCTIONS + * \ingroup SI91X_FIRMWARE_UPDATE_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Send the RPS header content of the firmware file. + * + * @details + * This function sends the RPS (Remote Programming Service) header content of the firmware file to the Si91x device. + * + * This is a blocking API. + * + * @param[in] rps_header + * Pointer to the RPS header content. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_fwup_start(const uint8_t *rps_header); + +/***************************************************************************/ /** + * @brief + * Send the firmware file content. + * + * @details + * This function sends the content of the firmware file to the Si91x device. + * + * This is a blocking API. + * + * @param[in] content + * Pointer to the firmware file content. + * + * @param[in] length + * Length of the content in bytes. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_fwup_load(const uint8_t *content, uint16_t length); + +/***************************************************************************/ /** + * @brief + * Abort the firmware update process on the SiWx91x device and reset all firmware upgrade helper variables in the NWP. This is a blocking API. + * + * @details + * This function aborts the ongoing firmware update process on the SiWx91x device. It is a blocking API and will not return until the process is aborted. + * + * This is a blocking API. + * + * @pre Pre-conditions: + * - @ref sl_si91x_fwup_load should be called before this API. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * After successful completion of firmware loading using the @ref sl_si91x_fwup_load API, the user can call this abort API. + * @note + * Ensure to call this abort API before performing a soft or hard reset of the SiWx91x device. + ******************************************************************************/ +sl_status_t sl_si91x_fwup_abort(void); + +/***************************************************************************/ /** + * @brief + * Flash firmware to the Wi-Fi module via the bootloader. + * + * @details + * This function flashes the firmware to the Wi-Fi module using the bootloader. The firmware image, its size, and the position flags are provided as parameters. + * + * This is a blocking API. + * + * @param[in] firmware_image + * Pointer to the firmware image. + * + * @param[in] fw_image_size + * Size of the firmware image in bytes. + * + * @param[in] flags + * Flags indicating the chunk position in the file: + * - 0: Middle of the file + * - 1: Start of the file + * - 2: End of the file + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_bl_upgrade_firmware(uint8_t *firmware_image, uint32_t fw_image_size, uint8_t flags); + +/***************************************************************************/ /** + * @brief + * Enable fast firmware upgrade mode. + * + * @details + * This function enables the fast firmware upgrade mode on the Si91x device. It optimizes the firmware upgrade process for speed. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_si91x_set_fast_fw_up(void); + +/** @} */ + +/** \addtogroup SI91X_FIRMWARE_UPDATE_FROM_MODULE_FUNCTIONS + * \ingroup SI91X_FIRMWARE_UPDATE_FUNCTIONS + * @{ */ +/***************************************************************************/ /** + * @brief + * Create an OTAF client and initialize it with a given configuration. + * + * @details + * This function creates an OTAF (Over-The-Air Firmware) client and initializes it with the provided configuration parameters. + * + * It supports both synchronous and asynchronous firmware upgrades. + * + * In synchronous mode, the response is received via [sl_net_event_handler_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-net-event-handler-t) with [SL_NET_OTA_FW_UPDATE_EVENT](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-constants#sl-net-event-t) as the event. + * + * @pre Pre-conditions: + * - [sl_net_up](../wiseconnect-api-reference-guide-nwk-mgmt/net-interface-functions#sl-net-up) API needs to be called before this API. + * + * @param[in] server_ip + * OTAF server IP address of type [sl_ip_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ip-address-t). + * + * @param[in] server_port + * OTAF server port number. + * + * @param[in] chunk_number + * Firmware content request chunk number. + * + * @param[in] timeout + * TCP receive packet timeout. + * + * @param[in] tcp_retry_count + * TCP retransmissions count. + * + * @param[in] asynchronous + * OTAF upgrade done asynchronously when this is set to true, else synchronous upgrade. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * For a safe firmware upgrade via TCP server, it will take approximately 65 seconds to upgrade the firmware of a 1.5 MB file. + ******************************************************************************/ +sl_status_t sl_si91x_ota_firmware_upgradation(sl_ip_address_t server_ip, + uint16_t server_port, + uint16_t chunk_number, + uint16_t timeout, + uint16_t tcp_retry_count, + bool asynchronous); + +/** @} */ + +/***************************************************************************/ /** + * @brief + * Get the current Opermode of the module. + * @return + * sl_si91x_operation_mode_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_si91x_operation_mode_t get_opermode(void); + +/***************************************************************************/ /** + * @brief + * Si91X specific get listen interval + * @return uint32_t + * Wi-Fi Listen interval + *******************************************************************************/ +uint32_t sl_si91x_get_listen_interval(void); + +/***************************************************************************/ /** + * @brief Si91X specific Wi-Fi transceiver mode driver function to send Tx data + * @param[in] control - Meta data for the payload. + * @param[in] payload - Pointer to payload to be sent to LMAC. + * @param[in] payload_len - Length of the payload. + * @param[in] wait_time - Wait time for the command response. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + *******************************************************************************/ +sl_status_t sl_si91x_driver_send_transceiver_data(sl_wifi_transceiver_tx_data_control_t *control, + const uint8_t *payload, + uint16_t payload_len, + uint32_t wait_time); + +//! @cond Doxygen_Suppress +/***************************************************************************/ /** + * @brief + * Register a function and optional argument for scan results callback. + * @param[in] command + * Command type to be sent to NWP firmware. + * @param[in] queue_type + * @ref sl_si91x_command_type_t Command type + * @param[in] data + * Command packet to be sent to the NWP firmware. + * @param[in] data_length + * Length of command packet. + * @param[in] wait_period + * @ref sl_si91x_wait_period_t Timeout for the command response. + * @param[in] sdk_context + * Pointer to the context. + * @param[in] data_buffer + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Pointer to a data buffer pointer for the response data to be returned in. + * @param[in] custom_host_desc + * Custom Variable to send additional data to the firmware through the host descriptor. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_custom_driver_send_command(uint32_t command, + sl_si91x_command_type_t command_type, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer, + uint8_t custom_host_desc); +//! @endcond + +/***************************************************************************/ /** + * @brief + * Wait for response packet + * @pre Pre-conditions: + * - + * [sl_wifi_init()](../wiseconnect-api-reference-guide-wi-fi/wifi-common-api#sl-wifi-init) should be called before this API. + * @param[in] queue + * Buffer queue + * @param[in] event_flag + * Event flags + * @param[in] event_mask + * Packet id + * @param[in] packet_id + * Packet id + * @param[in] wait_period + * Wait period + * @param[out] packet_buffer + * Pointer that will contain the response packet buffer when the function successfully returns. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sli_si91x_driver_wait_for_response_packet(sl_si91x_buffer_queue_t *queue, + osEventFlagsId_t event_flag, + uint32_t event_mask, + uint16_t packet_id, + sl_si91x_wait_period_t wait_period, + sl_wifi_buffer_t **packet_buffer); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h new file mode 100644 index 000000000..0eb170b00 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_host_interface.h @@ -0,0 +1,154 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_wifi_types.h" +#include "sl_wifi_host_interface.h" +#include "sl_si91x_types.h" +#include "sl_wifi_device.h" +#include +#include + +typedef sl_status_t (*sl_si91x_host_rx_irq_handler)(void); +typedef void (*sl_si91x_host_rx_done_handler)(void); + +typedef struct { + sl_si91x_host_rx_irq_handler rx_irq; + sl_si91x_host_rx_done_handler rx_done; + uint8_t boot_option; +} sl_si91x_host_init_configuration; + +/** + * @brief + * This API will make RST GPIO to low. + */ +void sl_si91x_host_hold_in_reset(void); + +/** + * @brief + * This API used to release the device from reset state. + */ +void sl_si91x_host_release_from_reset(void); + +/** + * @brief + * This API used to allocate all threads, mutexes and event handlers + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + */ +sl_status_t sl_si91x_host_init(const sl_si91x_host_init_configuration *config); + +/** + * @brief + * This API used to deallocate all threads, mutexes and event handlers. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + */ +sl_status_t sl_si91x_host_deinit(void); + +// --------------- +/** + * @brief + * This API is responsible for configuring a high speed communication bus. + */ +void sl_si91x_host_enable_high_speed_bus(); + +/** + * @brief + * This API is used for processing the data frames. + * @param interface + * [sl_wifi_interface_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-constants#sl-wifi-interface-t) Wi-Fi interface on which the data frame needs to be processed. + * @param buffer + * pointer to a structure of type [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) containing the data frame to be processed. + * @return sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + */ +sl_status_t sl_si91x_host_process_data_frame(sl_wifi_interface_t interface, sl_wifi_buffer_t *buffer); + +/** + * @brief + * Enable interrupts + * + */ +void sl_si91x_host_enable_bus_interrupt(void); + +/** + * @brief + * Disable interrupts + */ +void sl_si91x_host_disable_bus_interrupt(void); + +/** + * @brief + * Sets sleep Indication GPIO to HIGH. + * + */ +void sl_si91x_host_set_sleep_indicator(void); + +/** +* @addtogroup EXTERNAL_HOST_INTERFACE_FUNCTIONS +* @{ +*/ + +/** + * @brief + * Sets sleep Indication GPIO to LOW + */ +void sl_si91x_host_clear_sleep_indicator(void); + +/** @} */ + +/** + * @brief + * Reads Wakeup Indication GPIO value + * + * @return uint32_t + */ +uint32_t sl_si91x_host_get_wake_indicator(void); + +sl_status_t sl_si91x_host_spi_transfer( + const void *tx_buffer, + void *rx_buffer, + uint16_t buffer_length); /*Function used for data transfer between NWP and MCU over SPI*/ + +sl_status_t sl_si91x_host_uart_transfer( + const void *tx_buffer, + void *rx_buffer, + uint16_t buffer_length); /*Function used for data transfer between NWP and MCU over UART/USART*/ + +void sl_si91x_host_flush_uart_rx(void); /*Function used to flush all the old data in the uart/usart rx stream*/ + +void sl_si91x_host_uart_enable_hardware_flow_control(void); /*Function to enable Hardware Flow Control on host*/ + +/** + * @brief Check whether the current CPU operation mode is handler mode + * + * @return true + * @return false + */ +bool sl_si91x_host_is_in_irq_context(void); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h new file mode 100644 index 000000000..caf72edad --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_protocol_types.h @@ -0,0 +1,2167 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include +#include "sl_ieee802_types.h" +#include "sl_ip_types.h" +#include "sl_wifi_constants.h" +#include "sl_si91x_constants.h" +#include "sl_common.h" + +//! @cond Doxygen_Suppress +// below defines and structure for CFG_GET: Getting user store configuration. +#define IP_ADDRESS_SZ 4 +#define RSI_SSID_LEN 34 +#define WISE_PMK_LEN 32 +#define MAX_HTTP_SERVER_USERNAME 31 +#define MAX_HTTP_SERVER_PASSWORD 31 +#define RSI_PSK_LEN 64 +#define RSI_MAC_ADDR_LEN 6 + +// A macro to define the size of array in sl_si91x_socket_info_response_t to hold socket data. +#define SL_SI91X_SOCKET_INFO_RESPONSE_SOCKETS_COUNT 10 + +// Maximum Access points that can be scanned +#define RSI_AP_SCANNED_MAX 11 + +// Maximum number of stations associated when running as an AP +#define SI91X_MAX_STATIONS 16 + +// Quick reference: Bit 3 -> DHCPv6 client, Bit 5 -> DHCPv6 server, Bit 17 -> TCP_IP_FEAT_IPV6 +// Details: https://docs.silabs.com/rs9116-wiseconnect/latest/wifibt-wc-sapi-reference/opermode#rsi-tcp-ip-feature-bit-map +#define SI91X_IPV6_MODE (1 << 3) | (1 << 5) | (1 << 17) +#define RSI_IP_ADDRESS_LEN 4 +// Maximum payload size +#define RSI_MAX_PAYLOAD_SIZE 1500 + +#define SL_MAX_FWUP_CHUNK_SIZE 1024 +#define SL_RPS_HEADER_SIZE 64 + +// Firmware upgrade packet types +#define SL_FWUP_ABORT 2 +#define SL_FWUP_RPS_HEADER 1 +#define SL_FWUP_RPS_CONTENT 0 + +// Websocket max url length +#define RSI_WEBS_MAX_URL_LENGTH 51 + +// Websocket max host length +#define RSI_WEBS_MAX_HOST_LENGTH 51 + +#if defined(SLI_SI917) || defined(SLI_SI915) +#define SI91X_MAX_SIZE_OF_EXTENSION_DATA 256 +#else +#define SI91X_MAX_SIZE_OF_EXTENSION_DATA 64 +#endif + +#define SI91X_DNS_REQUEST_MAX_URL_LEN 90 + +#define SI91X_DNS_RESPONSE_MAX_ENTRIES 10 + +#define SI91X_MAX_CERT_SEND_SIZE 1400 + +/** NOTE: For power save related info + * https://confluence.silabs.com/pages/viewpage.action?spaceKey=RPD&title=Master+++Power+Save+modes + * https://confluence.silabs.com/display/RPD/Master+WLAN+APIs#MasterWLANAPIs-rsi_wlan_power_save_profile + * https://docs.silabs.com/rs9116/wiseconnect/rs9116w-wifi-at-command-prm/latest/wlan-commands#rsi-pwmode----power-mode + * NOTE: Wake up procedure provided in Confluence is outdated, Please refer AT PRM for it. + * ****************************** POWER RELATED DEFINES START *******************************/ +#define SL_POWER_MODE_DISABLE 0 +#define SL_CONNECTED_SLEEP_PS 1 +#define SL_CONNECTED_GPIO_BASED_PS 2 +#define SL_CONNECTED_MSG_BASED_PS 3 + +#ifdef SLI_SI91X_MCU_INTERFACE +#define SL_CONNECTED_M4_BASED_PS 4 +#endif + +#define SL_GPIO_BASED_DEEP_SLEEP 8 +#define SL_MSG_BASED_DEEP_SLEEP 9 + +#ifdef SLI_SI91X_MCU_INTERFACE +#define SL_M4_BASED_DEEP_SLEEP 10 +#endif + +#define DEFAULT_MONITOR_INTERVAL 50 +#define DEFAULT_DTIM_SKIP 0 +#define DEFAULT_DTIM_ALIGNMENT 0 + +#define SL_LP_MODE 0 +#define SL_ULP_WITH_RAM_RETENTION 1 +#define SL_ULP_WITHOUT_RAM_RET_RETENTION 2 + +#define SL_MAX_PSP 0 +#define SL_FAST_PSP 1 + +/****************************** POWER RELATED DEFINES END ***********************************/ + +// **************************** Macros for BG scan **************************************/ +#define SI91X_BG_SCAN_DISABLE 0 +#define SI91X_BG_SCAN_ENABLE 1 + +//**************************** Macros for BG end *********************************/ +#define NUMBER_OF_SOCKETS 20 + +//**************************** Macros for WPS Method request START *********************************/ + +#define SI91X_SET_WPS_METHOD_PUSH_BUTTON 0 +#define SI91X_SET_WPS_METHOD_PIN 1 +#define Si91X_SET_WPS_VALIDATE_PIN 0 +#define SI91X_SET_WPS_GENERATE_PIN 1 +#define SI91X_WPS_PIN_LEN 8 + +//**************************** Macros for WPS Method request END ***********************************/ +//! @endcond + +/** \addtogroup SI91X_JOIN_FEATURE_BIT_MAP + * @{ */ +/*=========================================================================*/ +// Join feature bit map parameters description !// +/*=========================================================================*/ +/// To enable b/g only mode in station mode +#define SL_SI91X_JOIN_FEAT_STA_BG_ONLY_MODE_ENABLE (1 << 0) + +/// To take listen interval from join command. +#define SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID (1 << 1) + +/// To enable quick join feature +#define SL_SI91X_JOIN_FEAT_QUICK_JOIN (1 << 2) + +/// To enable CCXV2 feature +#define SL_SI91X_JOIN_FEAT_CCXV2_FEATURE (1 << 3) + +/// To connect to AP based on BSSID together with configured SSID +#define SL_SI91X_JOIN_FEAT_BSSID_BASED (1 << 4) + +/// MFP Capable only +#define SL_SI91X_JOIN_FEAT_MFP_CAPABLE_ONLY (1 << 5) + +/// MFP Capable required +#define SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED ((1 << 5) | (1 << 6)) + +/// Listen interval from power save command +#define SL_SI91X_JOIN_FEAT_PS_CMD_LISTEN_INTERVAL_VALID (1 << 7) +/** @} */ + +//! @cond Doxygen_Suppress +//**************************** Macros for FEATURE frame Method request START *********************************/ +#define SI91X_FEAT_FRAME_PREAMBLE_DUTY_CYCLE (1 << 0) +#define SI91X_FEAT_FRAME_PERMIT_UNDESTINED_PACKETS (1 << 1) +#define SI91X_FEAT_FRAME_LP_CHAIN (1 << 4) +#define SI91X_FEAT_FRAME_IN_PACKET_DUTY_CYCLE (1 << 5) + +#define PLL_MODE 0 +#define RF_TYPE 1 // 0 - External RF 1- Internal RF +#define WIRELESS_MODE 0 +#define ENABLE_PPP 0 +#define AFE_TYPE 1 +#ifndef FEATURE_ENABLES +#define FEATURE_ENABLES \ + (SI91X_FEAT_FRAME_PREAMBLE_DUTY_CYCLE | SI91X_FEAT_FRAME_LP_CHAIN | SI91X_FEAT_FRAME_IN_PACKET_DUTY_CYCLE) +#endif + +//**************************** Macros for FEATURE frame Method request END *********************************/ + +//**************************** Macros for HTTP Client START *********************************/ + +#define SI91X_HTTP_BUFFER_LEN 2400 +#define SI91X_MAX_HTTP_URL_SIZE 2048 +#define SI91X_MAX_HTTP_CHUNK_SIZE 900 +#define HTTP_GET_FIRST_PKT BIT(0) +#define HTTP_GET_MIDDLE_PKT BIT(1) +#define HTTP_GET_LAST_PKT BIT(2) + +#define SI91X_HTTP_CLIENT_MAX_WRITE_BUFFER_LENGTH 900 +#define SI91X_HTTP_CLIENT_PUT_MAX_BUFFER_LENGTH 900 +#define SI91X_HTTP_CLIENT_POST_MAX_BUFFER_LENGTH 900 + +// HTTP client PUT create command +#define SI91X_HTTP_CLIENT_PUT_CREATE 1 + +// HTTP client PUT START command +#define SI91X_HTTP_CLIENT_PUT_START 2 + +// HTTP client PUT PKT command +#define SI91X_HTTP_CLIENT_PUT_PKT 3 + +// HTTP client PUT DELETE command +#define SI91X_HTTP_CLIENT_PUT_DELETE 4 + +// HTTP client PUT PKT OFFSET command +#define SI91X_HTTP_CLIENT_PUT_OFFSET_PKT 5 + +//***************************** Macros for HTTP Client End **********************************/ + +#define SI91X_COUNTRY_CODE_LENGTH 3 +#define SI91X_MAX_POSSIBLE_CHANNEL 24 + +#define ATTESTATION 30 + +#define NONCE_DATA_SIZE 32 + +typedef enum { RSI_NONE, RSI_TKIP, RSI_CCMP } sl_si91x_encryption_mode_t; +//! @endcond + +/// Set region command request structure +typedef struct { + /// Enable or disable set region from user: 1-take from user configuration,0-Take from Beacons + uint8_t set_region_code_from_user_cmd; + + /// region code(1-US,2-EU,3-JP,4-World Domain,5-KR) + uint8_t region_code; + + /// module type (0- Without on board antenna, 1- With on board antenna) + uint16_t module_type; +} sl_si91x_set_region_request_t; + +/// Set region in AP mode command request structure +typedef struct { + /// Enable or disable set region from user: 1-take from user configuration, 0-Take US or EU or JP + uint8_t set_region_code_from_user_cmd; + + /// region code(1-US,2-EU,3-JP) + uint8_t country_code[SI91X_COUNTRY_CODE_LENGTH]; + + /// No of rules + uint32_t no_of_rules; + + /// Channel information + struct { + uint8_t first_channel; ///< First channel + uint8_t no_of_channels; ///< Number of channels + uint8_t max_tx_power; ///< Max Tx power + } channel_info[SI91X_MAX_POSSIBLE_CHANNEL]; +} sl_si91x_set_region_ap_request_t; + +/// Scan command request structure +typedef struct { + uint8_t channel[4]; ///< RF channel to scan, 0=All, 1-14 for 2.4 GHz channels 1-14 + uint8_t ssid[RSI_SSID_LEN]; ///< SSID to scan, 0=All + uint8_t pscan_bitmap[4]; ///< Pscan bitmap + uint8_t _reserved; ///< Reserved + uint8_t scan_feature_bitmap; ///< Scan feature bitmap + uint8_t channel_bit_map_2_4[2]; ///< Channel bit map for 2.4GHz + uint8_t channel_bit_map_5[4]; ///< Channel bit map for 5GHz +} sl_si91x_req_scan_t; + +/// bg scan command request structure +typedef struct { + /// enable or disable BG scan + uint16_t bgscan_enable; + + /// Is it instant bgscan or normal bgscan + uint16_t enable_instant_bgscan; + + /// bg scan threshold value + uint16_t bgscan_threshold; + + /// tolerance threshold + uint16_t rssi_tolerance_threshold; + + /// periodicity + uint16_t bgscan_periodicity; + + /// active scan duration + uint16_t active_scan_duration; + + /// passive scan duration + uint16_t passive_scan_duration; + + /// multi probe + uint8_t multi_probe; +} sl_si91x_req_bg_scan_t; + +/// Scan information response structure +typedef struct { + uint8_t rf_channel; ///< channel number of the scanned AP + uint8_t security_mode; ///< security mode of the scanned AP + uint8_t rssi_val; ///< rssi value of the scanned AP + uint8_t network_type; ///< network type of the scanned AP + uint8_t ssid[RSI_SSID_LEN]; ///< SSID of the scanned AP + uint8_t bssid[RSI_MAC_ADDR_LEN]; ///< BSSID of the scanned AP + uint8_t reserved[2]; ///< Reserved +} sl_si91x_scan_info_t; + +/// Scan command response structure +typedef struct { + uint8_t scan_count[4]; ///< number of access points scanned + uint8_t reserved[4]; ///< Reserved + sl_si91x_scan_info_t scan_info[RSI_AP_SCANNED_MAX]; ///< scanned access points information +} sl_si91x_rsp_scan_t; + +/// Antenna select command request structure +typedef struct { + uint8_t antenna_value; ///< Antenna value to set + + uint8_t gain_2g; ///< Antenna 2G gain value + + uint8_t gain_5g; ///< Antenna 5G gain value + +} sl_si91x_antenna_select_t; + +/// PSK command request structure +typedef struct { + uint8_t type; ///< psk type , 1-psk alone, 2-pmk, 3-generate pmk from psk + uint8_t psk_or_pmk[RSI_PSK_LEN]; ///< psk or pmk + uint8_t ap_ssid[RSI_SSID_LEN]; ///< access point ssid: used for generation pmk +} sl_si91x_req_psk_t; + +/// Enterprise configuration command request structure +typedef struct { + uint8_t eap_method[32]; ///< EAP method + + uint8_t inner_method[32]; ///< Inner method + + uint8_t user_identity[64]; ///< Username + + uint8_t password[128]; ///< Password + + int8_t okc_enable[4]; ///< Opportunistic key caching enable + + uint8_t private_key_password[82]; ///< Private key password for encrypted private keys + +} sl_si91x_req_eap_config_t; + +/// Set certificate information structure +typedef struct { + uint16_t total_len; ///< total length of the certificate + uint8_t certificate_type; ///< type of certificate + uint8_t more_chunks; ///< more chunks flag + uint16_t certificate_length; ///< length of the current segment + uint8_t certificate_inx; ///< index of certificate + uint8_t key_password[127]; ///< reserved +} sl_si91x_cert_info_t; + +/// Si91x specific certificate validation +typedef struct { + uint16_t socket_id; ///< Socket ID + volatile uint16_t status; ///< certificate valid status +} sl_si91x_req_cert_valid_t; + +/// Set certificate command request structure +typedef struct { + sl_si91x_cert_info_t cert_info; ///< certificate information structure + uint8_t certificate[SI91X_MAX_CERT_SEND_SIZE]; ///< certificate +} sl_si91x_req_set_certificate_t; + +/// join command request structure +#pragma pack(1) +typedef struct { + /// reserved bytes:Can be used for security Type + uint8_t reserved1; + + /// 0- Open, 1-WPA, 2-WPA2,6-MIXED_MODE, 7-WPA3, 8-WP3_Transition + uint8_t security_type; + + /// data rate, 0=auto, 1=1 Mbps, 2=2 Mbps, 3=5.5Mbps, 4=11 Mbps, 12=54 Mbps + uint8_t data_rate; + + /// transmit power level, 0=low (6-9 dBm), 1=medium (10-14 dBm, 2=high (15-17 dBm) + uint8_t power_level; + + /// pre-shared key, 63-byte string , last character is NULL + uint8_t psk[RSI_PSK_LEN]; + + /// ssid of access point to join to, 34-byte string + uint8_t ssid[RSI_SSID_LEN]; + + /// feature bitmap for join + uint8_t join_feature_bitmap; + + /// reserved bytes + uint8_t reserved2[2]; + + /// length of ssid given + uint8_t ssid_len; + + /// listen interval + uint32_t listen_interval; + + /// vap id, 0 - station mode, 1 - AP mode + uint8_t vap_id; + + /// join bssid for mac based join + uint8_t join_bssid[6]; +} sl_si91x_join_request_t; +#pragma pack() + +/// IPV4 ipconfig command request structure +typedef struct { + /// 0=Manual, 1=Use DHCP + uint8_t dhcp_mode; + + /// IP address of this module if in manual mode + uint8_t ipaddress[4]; + + /// Netmask used if in manual mode + uint8_t netmask[4]; + + /// IP address of default gateway if in manual mode + uint8_t gateway[4]; + + /// DHCP client host name + uint8_t hostname[31]; + + /// vap id, 0 - station and 1 - AP + uint8_t vap_id; + + /// FQDN flag + uint8_t fqdn_flag[4]; + + /// minimum interval for DHCP discover retries + uint16_t dhcp_discover_rtr_interval_min; + + /// minimum interval for DHCP request retries + uint16_t dhcp_request_rtr_interval_min; + + /// maximum interval for DHCP discover retries + uint16_t dhcp_discover_rtr_interval_max; + + /// maximum interval for DHCP request retries + uint16_t dhcp_request_rtr_interval_max; + + /// maximum number of DHCP discover retries + uint8_t dhcp_discover_max_retries; + + /// maximum number of DHCP request retries + uint8_t dhcp_request_max_retries; +} SL_ATTRIBUTE_PACKED sl_si91x_req_ipv4_params_t; + +/// IPV4 ipconfig command response structure +typedef struct { + /// MAC address of this module + uint8_t macAddr[6]; + + /// Configured IP address + uint8_t ipaddr[4]; + + /// Configured netmask + uint8_t netmask[4]; + + /// Configured default gateway + uint8_t gateway[4]; +} sl_si91x_rsp_ipv4_params_t; + +/// IPV6 ipconfig command request structure +typedef struct { + /// 0=Manual, 1=Use DHCP + uint8_t mode[2]; + + /// prefix length + uint8_t prefixLength[2]; + + /// IPV6 address of the module + uint8_t ipaddr6[16]; + + /// address of gateway + uint8_t gateway6[16]; + + /// vap id, 0 - station and 1 - AP + uint8_t vap_id; +} sl_si91x_req_ipv6_params_t; + +/// IPV6 ipconfig command response structure +typedef struct { + /// prefix length + uint16_t prefixLength; + + /// reserved bytes + uint16_t reserved; + + /// Link local address + uint32_t link_local_address[4]; + + /// Global address + uint32_t global_address[4]; + + /// Gateway address + uint32_t gateway_address[4]; + + /// Mac address + uint8_t mac_address[6]; + +} SL_ATTRIBUTE_PACKED sl_si91x_rsp_ipv6_params_t; + +/// Structure for firmware upgradation +typedef struct { + /// Type of the packet + uint16_t type; + + /// Length of the packet + uint16_t length; + + /// RPS content + uint8_t content[SL_MAX_FWUP_CHUNK_SIZE]; +} sl_si91x_req_fwup_t; + +/// Si91x specific module RTC time +typedef struct { + uint32_t tm_sec; ///< Seconds [0-59] + uint32_t tm_min; ///< Minutes [0-59] + uint32_t tm_hour; ///< Hours since midnight [0-23] + uint32_t tm_mday; ///< Day of the month [1-31] + uint32_t tm_mon; ///< Months since January [0-11] + uint32_t tm_year; ///< Years since 1990 + uint32_t tm_wday; ///< Weekday from Sunday to Saturday [1-7] +} sl_si91x_module_rtc_time_t; + +/** \addtogroup SL_SI91X_TYPES + * @{ + * */ +/// Si91x specific Wireless information +typedef struct { + + uint16_t + wlan_state; ///< WLAN state: connected or disconnected in station mode; number of stations connected in AP mode. + + uint16_t channel_number; ///< Channel number of connected AP + + uint8_t ssid[RSI_SSID_LEN]; ///< SSID of connected access point + + uint8_t mac_address[6]; ///< MAC address + + uint8_t sec_type; ///< Security type + + uint8_t psk_pmk[64]; ///< PSK for AP mode, PMK for Client mode + + uint8_t ipv4_address[4]; ///< Module IP Address + + uint8_t ipv6_address[16]; ///< Module IPv6 Address + + uint8_t reserved1[2]; ///< Reserved1 + + uint8_t reserved2[2]; ///< Reserved2 + +} sl_si91x_rsp_wireless_info_t; +/** @} */ + +///< socket create command request structure +#pragma pack(1) +typedef struct { + uint16_t ip_version; ///< ip version4 or 6 + uint16_t socket_type; ///< 0= TCP Client, 1= UDP Client, 2= TCP Server (Listening TCP) + uint16_t local_port; ///< Our local module port number + uint16_t remote_port; ///< Port number of what we are connecting to + union { + uint8_t ipv4_address[4]; ///< remote IPv4 Address + uint8_t ipv6_address[16]; ///< remote IPv6 Address + } dest_ip_addr; ///< Destination IP address + uint16_t max_count; ///< maximum no of LTCP sockets on same port +#if defined(SLI_SI917) || defined(SLI_SI915) + uint16_t tos; ///< type of service + +#else + uint32_t tos; ///< type of service + +#endif + +#if defined(SLI_SI917) || defined(SLI_SI915) + uint32_t ssl_bitmap; ///< ssl version select bit map + +#else + uint8_t ssl_bitmap; ///< ssl version select bit map + uint8_t ssl_ciphers; ///< ssl ciphers bitmap +#endif + uint8_t webs_resource_name[RSI_WEBS_MAX_URL_LENGTH]; ///< web socket resource name + uint8_t webs_host_name[RSI_WEBS_MAX_HOST_LENGTH]; ///< web socket host name + uint8_t max_tcp_retries_count; ///< TCP retries + uint8_t socket_bitmap; ///< Socket bitmap + uint8_t rx_window_size; ///< RX window size + uint16_t tcp_keepalive_initial_time; ///< TCP keepalive initial timeout + uint8_t vap_id; ///< VAPID + uint8_t socket_cert_inx; ///< socket cert inx + uint32_t ssl_ciphers_bitmap; ///< ssl ciphers bitmap +#if defined(SLI_SI917) || defined(SLI_SI915) + uint32_t ssl_ext_ciphers_bitmap; ///< ssl extended ciphers bitmap + uint8_t max_retransmission_timeout_value; ///< max retransmission timeout value +#endif + uint8_t tcp_retry_transmit_timer; ///< tcp retry transmission timer + uint16_t tcp_mss; ///< TCP MSS + uint16_t no_of_tls_extensions; ///< number of TLS extensions + uint16_t total_extension_length; ///< total extension length + uint8_t tls_extension_data[SI91X_MAX_SIZE_OF_EXTENSION_DATA]; ///< TLS extension data +#if defined(SLI_SI917) || defined(SLI_SI915) + uint16_t recv_buff_len; ///< receive buffer length +#endif + +} sl_si91x_socket_create_request_t; +#pragma pack() + +/// socket create command response structure +typedef struct { + uint8_t ip_version[2]; ///< ip version 4 or 6 + uint8_t socket_type[2]; ///< 2 bytes, type of socket created + uint8_t socket_id[2]; ///< 2 bytes socket descriptor, like a file handle, usually 0x00 + uint8_t module_port[2]; ///< 2 bytes, Port number of our local socket + uint8_t dst_port[2]; ///< Destination port number + union { + uint8_t ipv4_addr[4]; ///< 4 bytes, Our (module) IPv4 Address + uint8_t ipv6_addr[16]; ///< 4 bytes, Our (module) IPv6 Address + } module_ip_addr; ///< Module IP address + union { + uint8_t ipv4_addr[4]; ///< 4 bytes, Our (module) IPv4 Address + uint8_t ipv6_addr[16]; ///< 4 bytes, Our (module) IPv6 Address + } dest_ip_addr; ///< Destrination IP address + uint8_t mss[2]; ///< 2 bytes, Remote peer MSS size + uint8_t window_size[4]; ///< 4 bytes, Remote peer Window size +} sl_si91x_socket_create_response_t; +#pragma pack() + +#pragma pack(1) +/// Socket close command request structure +typedef struct { + uint16_t socket_id; ///< 2 bytes, socket that was closed + uint16_t port_number; ///< 4 bytes, port number +} sl_si91x_socket_close_request_t; +#pragma pack() + +#pragma pack(1) +/// Socket close command response structure + +typedef struct { + uint16_t socket_id; ///< 2 bytes, socket that was closed + uint32_t sent_bytes_count; ///< 4 bytes, sent bytes count + uint16_t port_number; ///< 2 bytes, port number +} sl_si91x_socket_close_response_t; +#pragma pack() + +#pragma pack(1) +/// Si91x specifc send data on socket request structure +typedef struct { + uint16_t ip_version; ///< ip version 4 or 6 + uint16_t socket_id; ///< socket descriptor of the already opened socket connection + uint32_t length; ///< length of the data to be sent + uint16_t data_offset; ///< Data Offset + uint16_t dest_port; ///< destination port + union { + uint8_t ipv4_address[RSI_IP_ADDRESS_LEN]; ///< 4 bytes, IPv4 Address of the remote device + uint8_t ipv6_address[RSI_IP_ADDRESS_LEN * 4]; ///< 16 bytes, IPv6 Address of the remote device + } dest_ip_addr; ///< IP address of the remote device + uint8_t send_buffer[]; ///< data buffer to send +} sli_si91x_socket_send_request_t; +#pragma pack() + +/// socket accept request structure +#pragma pack(1) +typedef struct { + uint8_t socket_id; ///< Socket ID + uint16_t source_port; ///< Local port number +} sl_si91x_socket_accept_request_t; +#pragma pack() + +/// LTCP socket establish request structure +#pragma pack(1) +typedef struct { + /// IP version + uint16_t ip_version; + + /// 2 bytes, socket handle + uint16_t socket_id; + + /// 2 bytes, remote port number + uint16_t dest_port; + + union { + + /// remote IPv4 Address + uint8_t ipv4_address[4]; + + /// remote IPv6 Address + uint8_t ipv6_address[16]; + } dest_ip_addr; ///< Destination IP address + + /// 2 bytes, remote peer MSS size + uint16_t mss; + + /// 4 bytes, remote peer Window size + uint32_t window_size; + + /// source port number + uint16_t src_port_num; +} sl_si91x_rsp_ltcp_est_t; +#pragma pack() + +/// disassociate command request structure +#pragma pack(1) +typedef struct { + // FIXME: Enumerate + /// 0- Module in Client mode, 1- AP mode + uint16_t mode_flag; + + /// client MAC address, Ignored/Reserved in case of client mode + sl_mac_address_t client_mac_address; +} sl_si91x_disassociation_request_t; +#pragma pack() + +/// Access point configuration parameters +#pragma pack(1) +typedef struct { + /// channel number of the access point + uint16_t channel; + + /// ssid of the AP to be created + uint8_t ssid[RSI_SSID_LEN]; + + /// security type of the Access point + uint8_t security_type; + + /// encryption mode + uint8_t encryption_mode; + + /// password in case of security mode + uint8_t psk[SL_WIFI_MAX_PMK_LENGTH]; + + /// Beacon interval of the access point in milliseconds. Allowed values are integers in the range of 100 to 1000 in multiples of 100. + uint16_t beacon_interval; + + /// DTIM period of the access point + uint16_t dtim_period; + + /// This is the bitmap to enable AP keep alive functionality and to select the keep alive type. + uint8_t ap_keepalive_type; + + /// Keep alive time after which AP will disconnect the station if there are no wireless exchanges from station to AP. + uint8_t ap_keepalive_period; + + /// Number of clients supported + uint16_t max_sta_support; +} sl_si91x_ap_config_request; +#pragma pack() + +/// Internal SiWx91x Socket information query +/// @note: This is internal structure and should not be used by the applicatiom. This is identical to sl_si91x_sock_info_query_t and, would be cleaned to have single structure in future. +typedef struct { + uint8_t sock_id[2]; ///< Identifier for the socket + + uint8_t sock_type[2]; ///< Type of the socket (TCP, UDP, and so on.) + + uint8_t source_port[2]; ///< Port number used by the source + + uint8_t dest_port[2]; ///< Port number used by the destination + + union { + uint8_t ipv4_address[4]; ///< IPv4 address of the remote host + + uint8_t ipv6_address[16]; ///< IPv6 address of the remote host + + } dest_ip_address; ///< IP address of the destination host +} sli_sock_info_query_t; + +/// Network params command response structure +#pragma pack(1) +typedef struct { + /// uint8, 0= NOT Connected, 1= Connected + uint8_t wlan_state; + + /// channel number of connected AP + uint8_t channel_number; + + /// PSK + uint8_t psk[64]; + + /// Mac address + uint8_t mac_address[6]; + + /// uint8[32], SSID of connected access point + uint8_t ssid[RSI_SSID_LEN]; + + /// 2 bytes, 0= AdHoc, 1= Infrastructure + uint8_t connType[2]; + + /// security type + uint8_t sec_type; + + /// uint8, 0= Manual IP Configuration,1= DHCP + uint8_t dhcpMode; + + /// uint8[4], Module IP Address + uint8_t ipv4_address[4]; + + /// uint8[4], Module Subnet Mask + uint8_t subnetMask[4]; + + /// uint8[4], Gateway address for the Module + uint8_t gateway[4]; + + /// number of sockets opened + uint8_t num_open_socks[2]; + + /// prefix length for ipv6 address + uint8_t prefix_length[2]; + + /// modules ipv6 address + uint8_t ipv6_address[16]; + + /// router ipv6 address + uint8_t defaultgw6[16]; + + /// BIT(0) =1 - ipv4, BIT(1)=2 - ipv6, BIT(0) & BIT(1)=3 - BOTH + uint8_t tcp_stack_used; + + /// sockets information array + sli_sock_info_query_t socket_info[10]; +} sl_si91x_network_params_response_t; +#pragma pack() + +/// Si91x specific station information +typedef struct { + uint8_t ip_version[2]; ///< IP version if the connected client + uint8_t mac[6]; ///< Mac Address of the connected client + union { + uint8_t ipv4_address[4]; ///< IPv4 address of the connected client + uint8_t ipv6_address[16]; ///< IPv6 address of the connected client + + } ip_address; ///< IP address +} sl_si91x_station_info_t; + +/// go paramas response structure +#pragma pack(1) +typedef struct { + /// SSID of the P2p GO + uint8_t ssid[RSI_SSID_LEN]; + + /// BSSID of the P2p GO + uint8_t mac_address[6]; + + /// Operating channel of the GO + uint8_t channel_number[2]; + + /// PSK of the GO + uint8_t psk[64]; + + /// IPv4 Address of the GO + uint8_t ipv4_address[4]; + + /// IPv6 Address of the GO + uint8_t ipv6_address[16]; + + /// Number of stations Connected to GO + uint8_t sta_count[2]; + + /// Station information + sl_si91x_station_info_t sta_info[SI91X_MAX_STATIONS]; +} sl_si91x_client_info_response; +#pragma pack() + +/// Wi-Fi statistics report +typedef enum { + START_STATISTICS_REPORT, ///< Start statistics report + STOP_STATISTICS_REPORT, ///< Stop statistics report +} sl_wifi_statistics_report_t; + +/// per stats command request structure +typedef struct { + /// 0 - start , 1 -stop + uint8_t start[2]; + + /// channel number + uint8_t channel[2]; +} sl_si91x_req_rx_stats_t; + +/// wlan per stats structure +typedef struct { + uint8_t tx_pkts[2]; ///< Number of transmitted packets + uint8_t reserved_1[2]; ///< Reserved + uint8_t tx_retries[2]; ///< Number of transmitted packets + uint16_t crc_pass; ///< Number of packets passed CRC + uint16_t crc_fail; ///< Number of packets failed CRC + uint8_t cca_stk[2]; ///< CCA stuck count + uint8_t cca_not_stk[2]; ///< CCA not stuck count + uint8_t pkt_abort[2]; ///< Packet abort count + uint8_t fls_rx_start[2]; ///< FLS RX start count + uint8_t cca_idle[2]; ///< CCA idle count + uint8_t reserved_2[26]; ///< Reserved + uint8_t rx_retries[2]; ///< Number of received packets + uint8_t reserved_3[2]; ///< Reserved + uint16_t cal_rssi; ///< RSSI value + uint8_t reserved_4[4]; ///< Reserved + uint8_t xretries[2]; ///< Number of retries + uint8_t max_cons_pkts_dropped[2]; ///< Maximum consecutive packets dropped + uint8_t reserved_5[2]; ///< Reserved + uint8_t bss_broadcast_pkts[2]; ///< BSS broadcast packets + uint8_t bss_multicast_pkts[2]; ///< BSS multicast packets + uint8_t bss_filter_matched_multicast_pkts[2]; ///< BSS filter matched multicast packets +} sl_si91x_per_stats_rsp_t; + +/// Si91x specific sockt send data parameters +typedef struct { + uint8_t sock_fd; ///< Socket identifier + uint32_t length; ///< Length of data + // Need to discuss and increase data size + uint8_t data[50]; ///< Data +} sl_si91x_socket_send_data_parameters_t; + +/// Si91x specific sockt receive data parameters +typedef struct { + uint8_t new_sock_fd; ///< New socket identifier + uint32_t length; ///< Length of data + uint8_t data[1460]; ///< Data +} sl_si91x_socket_receive_data_parameters_t; + +/// Si91x specific socket create parameters +typedef struct { + uint8_t domain; ///< Domain + uint8_t type; ///< Socket protocol types (TCP/UDP/RAW) :: 1(SOCK_STREAM), 2(SOCK_DGRAM), 3(SOCK_RAW) + uint8_t protocol; ///< Protocol default : 0(IPPROTO_IP) +} sl_si91x_socket_create_parameters_t; + +/// Socket connection parameters +typedef struct { + uint8_t domain; ///< Domain + int8_t sock_fd; ///< Socket identifier + uint32_t port; ///< Port number + uint32_t remote_ip_addr; ///< Remote IP address +} sl_si91x_socket_connect_or_listen_parameters_t; + +/// Si91x specific feature frame request +typedef struct { + uint8_t + pll_mode; ///< PLL Mode. 0 - less than 120 Mhz NWP SoC clock; 1 - greater than 120 Mhz NWP SoC clock (Mode 1 is not currently supported for coex) + uint8_t rf_type; ///< RF Type. + uint8_t wireless_mode; ///< Wireless Mode. + uint8_t enable_ppp; ///< Enable PPP. + uint8_t afe_type; ///< AFE Type. + uint32_t feature_enables; ///< Feature Enables. +} sl_si91x_feature_frame_request; + +/// structure for power save request +typedef struct { + /// power mode to set + uint8_t power_mode; + + /// set LP/ULP/ULP-without RAM retention + uint8_t ulp_mode_enable; + + /// set DTIM aligment required + // 0 - module wakes up at beacon which is just before or equal to listen_interval + // 1 - module wakes up at DTIM beacon which is just before or equal to listen_interval + uint8_t dtim_aligned_type; + + /// Set PSP type, 0-Max PSP, 1- FAST PSP, 2-APSD + uint8_t psp_type; + + /// Monitor interval for the FAST PSP mode + // default is 50 ms, and this parameter is valid for FAST PSP only + uint16_t monitor_interval; + /// Number of DTIMs to skip + uint8_t num_of_dtim_skip; + /// Listen interval + uint16_t listen_interval; +} sl_si91x_power_save_request_t; + +/// DNS query request structure +typedef struct { + //! Ip version value + uint8_t ip_version[2]; + + //! URL name + uint8_t url_name[SI91X_DNS_REQUEST_MAX_URL_LEN]; + + //! DNS servers count + uint8_t dns_server_number[2]; +} sl_si91x_dns_query_request_t; + +/// DNS query response structure +typedef struct { + //! Ip version of the DNS server + uint8_t ip_version[2]; + + //! DNS response count + uint8_t ip_count[2]; + + //! DNS address responses + union { + uint8_t ipv4_address[4]; + uint8_t ipv6_address[16]; + } ip_address[SI91X_DNS_RESPONSE_MAX_ENTRIES]; +} sl_si91x_dns_response_t; + +/** + * @brief DNS Server add request structure. + * + * This structure holds the information needed to add DNS servers, supporting both IPv4 and IPv6 addresses. + */ +typedef struct { + uint8_t ip_version[2]; ///< IP version value. The second byte is reserved for future use. + uint8_t dns_mode[2]; ///< DNS mode to use. The second byte is reserved for future use. + + union { + uint8_t primary_dns_ipv4[4]; ///< Primary DNS address in IPv4 format. + uint8_t primary_dns_ipv6[16]; ///< Primary DNS address in IPv6 format. + } sli_ip_address1; ///< Primary DNS address. + + union { + uint8_t secondary_dns_ipv4[4]; ///< Secondary DNS address in IPv4 format. + uint8_t secondary_dns_ipv6[16]; ///< Secondary DNS address in IPv6 format. + } sli_ip_address2; ///< Secondary DNS address. +} sli_dns_server_add_request_t; + +/// Structure for TCP ACK indication +typedef struct { + /// Socket ID + uint8_t socket_id; + + /// Length + uint8_t length[2]; + +} sl_si91x_rsp_tcp_ack_t; + +/// Config command request structure +typedef struct { + /// config type + uint16_t config_type; + + /// value to set + uint16_t value; +} sl_si91x_config_request_t; + +/// read bytes coming on socket request structure +typedef struct { + /// socket id + uint8_t socket_id; + + /// requested bytes + uint8_t requested_bytes[4]; + + /// Timeout for read + uint8_t read_timeout[2]; +} sl_si91x_req_socket_read_t; + +/// Si91x specific time value +typedef struct { + uint32_t tv_sec; ///< Time in Seconds + uint32_t tv_usec; ///< Time in microseconds +} sl_si91x_time_value; + +/// The select socket array manager. */ +typedef struct { + uint32_t fd_array[(NUMBER_OF_SOCKETS + 31) / 32]; ///< Bit map of SOCKET Descriptors. + int32_t fd_count; ///< How many are SET +} sl_si91x_fd_set_t; + +/// Si91x specifc socket select request structure +typedef struct { + uint8_t num_fd; ///< Number of file descriptors + uint8_t select_id; ///< Select ID + sl_si91x_fd_set_t read_fds; ///< Read file descriptors + sl_si91x_fd_set_t write_fds; ///< Write file descriptors + sl_si91x_time_value select_timeout; ///< Select timeout + uint8_t no_timeout; ///< No timeout +} sl_si91x_socket_select_req_t; + +/// Si91x specific socket select response structure +typedef struct { + uint8_t select_id; ///< Select ID + sl_si91x_fd_set_t read_fds; ///< Read file descriptors + sl_si91x_fd_set_t write_fds; ///< Write file descriptors + uint32_t socket_terminate_bitmap; ///< Socket terminate bitmap +} sl_si91x_socket_select_rsp_t; + +/// Structure for OTA firmware upgradation +typedef struct { + /// Type of the packet + uint8_t ip_version; + + union { + /// 4 bytes, IPv4 Address of the server + uint8_t ipv4_address[4]; + + /// 16 bytes, IPv6 Address of the server + uint8_t ipv6_address[16]; + + } server_ip_address; ///< Server IP address + + /// server port + uint8_t server_port[4]; + + /// Chunk number + uint8_t chunk_number[2]; + + /// Timeout + uint8_t timeout[2]; + + /// TCP retry count + uint8_t retry_count[2]; + +} sl_si91x_ota_firmware_update_request_t; + +/// Multicast request structure +typedef struct { + /// IP version + uint8_t ip_version[2]; + + /// command type + uint8_t type[2]; + + union { + uint8_t ipv4_address[4]; ///< IPv4 address + uint8_t ipv6_address[16]; ///< IPv6 address + } multicast_address; ///< Multicast address +} si91x_req_multicast_t; + +/// Si91x specific WPS method request +typedef struct { + /// wps method: 0 - push button, 1 - pin method + uint16_t wps_method; + + /// If 0 - validate given pin, 1 - generate new pin + uint16_t generate_pin; + + /// wps pin for validation + uint8_t wps_pin[SI91X_WPS_PIN_LEN]; +} sl_si91x_wps_method_request_t; + +/// Si91x specific roam parameters request +typedef struct { + uint32_t roam_enable; ///< Enable or disable roaming + uint32_t roam_threshold; ///< roaming threshold + uint32_t roam_hysteresis; ///< roaming hysteresis +} sl_si91x_req_roam_params_t; + +/// Ping Request Frame +typedef struct { + /// ip version + uint16_t ip_version; + + /// ping size + uint16_t ping_size; + + union { + /// ipv4 address + uint8_t ipv4_address[4]; + + /// ipv6 address + uint8_t ipv6_address[16]; + + } ping_address; ///< Ping address + + /// ping request timeout + uint16_t timeout; +} sl_si91x_ping_request_t; + +//! HTTP Get/Post request structure +typedef struct { + //! ip version + uint16_t ip_version; + + //! https enable + uint16_t https_enable; + + //! port number + uint16_t port_number; + + //! buffer + uint8_t buffer[SI91X_HTTP_BUFFER_LEN]; +} sl_si91x_http_client_request_t; + +//! SNI for embedded sockets structure +#define SI91X_SNI_FOR_HTTPS 1 + +/// Si91x specific SNI for embedded socket request +typedef struct si91x_sni_for_embedded_socket_request_s { + //! offset from which hostname starts + uint16_t offset; + + //! application protocol + uint16_t protocol; + + //! sni extension data + uint8_t tls_extension_data[SI91X_MAX_SIZE_OF_EXTENSION_DATA]; +} si91x_sni_for_embedded_socket_request_t; + +//! HTTP client PUT START create structure +typedef struct { + //! HTTP server ip version + uint8_t ip_version; + + //! HTTPS bit map + uint16_t https_enable; + + //! HTTP server port number + uint32_t port_number; + + //! HTTP Content Length + uint32_t content_length; +} SL_ATTRIBUTE_PACKED sl_si91x_http_client_put_start_t; + +typedef struct { + //! Current chunk length + uint16_t current_length; +} SL_ATTRIBUTE_PACKED sl_si91x_http_client_put_data_request_t; + +//! @cond Doxygen_Suppress +//! HTTP client PUT request structure +typedef struct { + //! Command type + uint8_t command_type; + + union http_client_put_s { + //! HTTP PUT START command structure + sl_si91x_http_client_put_start_t http_client_put_start; + + //! HTTP PUT PACKET command structure + sl_si91x_http_client_put_data_request_t http_client_put_data_req; + + } SL_ATTRIBUTE_PACKED http_client_put_struct; + + //! HTTP PUT buffer + uint8_t http_put_buffer[SI91X_HTTP_CLIENT_PUT_MAX_BUFFER_LENGTH]; +} SL_ATTRIBUTE_PACKED sl_si91x_http_client_put_request_t; +//! @endcond + +//! HTTP Client POST DATA PKT request structure +typedef struct { + //! Current http data chunk length + uint16_t current_length; + + //! HTTP POST buffer + uint8_t http_post_data_buffer[SI91X_HTTP_CLIENT_POST_MAX_BUFFER_LENGTH]; +} sl_si91x_http_client_post_data_request_t; + +//! HTTP Client PUT PKT response structure +typedef struct { + //! Receive HTTP client PUT command type + uint8_t command_type; + + //! End of resource content file + uint8_t end_of_file; +} sl_si91x_http_client_put_pkt_rsp_t; + +//! HTTP Client PUT pkt server response structure +typedef struct { + uint32_t command_type; ///< Command type + uint32_t more; ///< More + uint32_t offset; ///< Offset + uint32_t data_len; ///< Data length +} sl_si91x_http_put_pkt_server_rsp_t; + +/// Si91x specific WLAN filter broadcast request +typedef struct { + uint8_t beacon_drop_threshold[2]; ///< Beacon drop threshold + uint8_t filter_bcast_in_tim; ///< Filter broadcast in TIM + uint8_t filter_bcast_tim_till_next_cmd; ///< Filter broadcast TIM till next command +} sl_si91x_request_wlan_filter_broadcast_t; + +//! user configurable gain table structure +typedef struct { + uint8_t band; ///< band value + uint8_t bandwidth; ///< bandwidth value + uint16_t size; ///< payload size + uint32_t reserved; ///< Reserved + uint8_t gain_table[]; ///< payload +} sl_si91x_gain_table_info_t; + +/// Si91x specific 11AX configuration parameters +typedef struct { + uint8_t guard_interval; ///< Period of time inserted between two packets in wireless transmission. Range : 0 - 3 + uint8_t nominal_pe; ///< Nominal Packet extension Range: 0 - 2 + uint8_t dcm_enable; ///< Enable or disable dual carrier modulation (DCM). 0 - Disable DCM, 1 - Enable DCM + uint8_t ldpc_enable; ///< Enable or disable low-density parity-check (LDPC). 0 - Disable LDPC, 1 - Enable LDPC + uint8_t + ng_cb_enable; ///< Enable or disable non-contiguous channel bonding (NG CB). 0 - Disable NG CB, 1 - Enable NG CB + uint8_t ng_cb_values; ///< Values of non-contiguous channel bonding (NG CB). Range: 0x00 - 0x11 + uint8_t + uora_enable; ///< Enable or disable uplink orthogonal frequency division multiple random access (UORA). 0 - Disable uora, 1 - Enable uora. + uint8_t + trigger_rsp_ind; ///< Trigger_Response_Indication. BIT(0) ? Trigger Response For BE, BIT(1) ? Trigger Response For BK, BIT(2) ? Trigger Response For VI, BIT(3) ? Trigger Response For VO + uint8_t ipps_valid_value; ///< IPPS valid value + uint8_t tx_only_on_ap_trig; ///< Reserved for future use + uint8_t twt_support; ///< Enable or Disable TWT. 0 - Disable TWT, 1 - Enable TWT. + uint8_t + config_er_su; ///< Extended Range Single User. 0 - NO ER_SU support, 1 - Use ER_SU rates along with Non_ER_SU rates, 2 - Use ER_SU rates only + uint8_t disable_su_beamformee_support; ///< Flag indicating whether Single User Beamformee support is disabled. + /// * 0: Enabled, 1: Disabled. +} sl_si91x_11ax_config_params_t; + +/// Si91x specific ram dump +typedef struct { + uint32_t address; ///< Address + uint32_t length; ///< Length +} sl_si91x_ram_dump_t; + +#ifdef SLI_SI91X_MCU_INTERFACE +typedef enum { + SL_SI91X_TAKE_M4_64K = 1, + SL_SI91X_GET_IPMU_PROGRAMMING_VALUES = 2, + SL_SI91X_READ_TA_REGISTER = 3, + SL_SI91X_WRITE_TA_REGISTER = 4, + // This enum varibale added for M4 has to give indication to NWP, for configuring the clock switching between 1.3 to 3.3 V .For more details, check Jira Ticket RSC-3802. + SL_SI91X_ENABLE_XTAL = 5, + SL_SI91X_WRITE_TO_COMMON_FLASH = 6, +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + SL_SI91X_ENABLE_SIDE_BAND = 7, +#endif + SL_SI91X_READ_FROM_COMMON_FLASH = 8, +} sl_si91x_ta_m4_commands_t; + +// M4 and NWP secure handshake request structure. +typedef struct { + // sub_cmd form the enum ta_m4_commands_e(Main command type is RSI_COMMON_REQ_TA_M4_COMMANDS) + sl_si91x_ta_m4_commands_t sub_cmd; + // length of input_data + uint8_t input_data_size; + // Input data. In this input data first byte is reserved for enable(1) or Disable(0) sub_cmd of this structure. + uint8_t input_data[]; +} sl_si91x_ta_m4_handshake_parameters_t; + +#define MAX_CHUNK_SIZE 1400 +#define FLASH_SECTOR_SIZE 4096 +// TA2M4 handshake request structure. +typedef struct { + // sub_cmd + uint8_t sub_cmd; + + // NWP flash location + uint32_t addr; + + // total length of input data + uint16_t input_buffer_length; + + // erases multiples of 4kbytes + uint8_t flash_sector_erase_enable; + + //data + uint8_t input_data[MAX_CHUNK_SIZE]; +} SL_ATTRIBUTE_PACKED sl_si91x_request_ta2m4_t; + +typedef struct { + // sub_cmd + uint8_t sub_cmd; + + // nwp flash location + uint32_t nwp_address; + + // total length of output data + uint16_t output_buffer_length; + +} SL_ATTRIBUTE_PACKED sl_si91x_read_flash_request_t; + +#endif // SLI_SI91X_MCU_INTERFACE + +/** \addtogroup SL_SI91X_TYPES + * @{ + * */ +/// Si91x specific TWT response +typedef struct { + uint8_t wake_duration; ///< Wake duration + uint8_t wake_duration_unit; ///< Wake duration unit + uint8_t wake_int_exp; ///< Wake interval exponent + uint8_t negotiation_type; ///< Negotiation type + uint16_t wake_int_mantissa; ///< Wake interval mantissa + uint8_t implicit_twt; ///< Impilcit TWT + uint8_t un_announced_twt; ///< Unannounced TWT + uint8_t triggered_twt; ///< Triggered TWT + uint8_t twt_channel; ///< TWT channel + uint8_t twt_protection; ///< TWT Protection + uint8_t twt_flow_id; ///< TWT flow ID +} sl_si91x_twt_response_t; + +/// Si91x specific TX test info +typedef struct { + uint16_t enable; ///< Enable/disable TX test mode + uint16_t power; ///< TX power in dBm. Range : 2 - 18 dBm. + ///< + ///< @note 1. User can configure the maximum power level allowed for the given frequncey in the configured region by providing 127 as power level. + ///< @note 2. User should configure a minimum delay (approx. 10 milliseconds) before and after \ref sl_si91x_transmit_test_start API to observe a stable output at requested dBm level. + uint32_t rate; ///< Transmit data rate + ///< ### Data Rates ### + ///< Data rate(Mbps) | Value of rate + ///< :--------------:|:-------------------: + ///< 1 | 0 + ///< 2 | 2 + ///< 5.5 | 4 + ///< 11 | 6 + ///< 6 | 139 + ///< 9 | 143 + ///< 12 | 138 + ///< 18 | 142 + ///< 24 | 137 + ///< 36 | 141 + ///< 48 | 136 + ///< 54 | 140 + ///< MCS0 | 256 + ///< MCS1 | 257 + ///< MCS2 | 258 + ///< MCS3 | 259 + ///< MCS4 | 260 + ///< MCS5 | 261 + ///< MCS6 | 262 + ///< MCS7 | 263 + uint16_t length; ///< TX packet length. Range: [24 - 1500] bytes in Burst mode and [24 - 260] bytes in Continuous mode + uint16_t mode; ///< TX test mode mode. + ///< + ///< 0 - Burst Mode. + ///< + ///< 1 - Continuous Mode. + ///< + ///< 2 - Continuous wave Mode (non modulation) in DC mode. + ///< + ///< 3 - Continuous wave Mode (non modulation) in single tone mode (center frequency -2.5 MHz). + ///< + ///< 4 - Continuous wave Mode (non modulation) in single tone mode (center frequency +5 MHz). + ///< + ///< `Burst mode`: DUT transmits a burst of packets with the given power, rate, length in the channel configured. + ///< The burst size will be determined by the number of packets and if its zero, then DUT keeps transmitting till a @ref sl_si91x_transmit_test_stop API is called. + ///< + ///< `Continuous Mode`: The DUT transmits a unmodulated waveform continuously + ///< + ///< `Continuous Wave Mode (Non-Modulation) in DC Mode`: The DUT transmits a spectrum only at the center frequency of the channel. + ///< A basic signal with no modulation is that of a sine wave and is usually referred to as a continuous wave (CW) signal. + ///< A basic signal source produces sine waves. Ideally, the sine wave is perfect. In the frequency domain, it is viewed as a single line at some specified frequency. + ///< + ///< `Continuous Wave Mode (Non-Modulation) in single tone Mode (Center frequency -2.5 MHz)`: The DUT transmits a spectrum that is generated at -2.5MHz from the center frequency of the channel selected. + ///< Some amount of carrier leakage will be seen at Center Frequency. For example, for 2412 MHz, the output would be seen at 2409.5 MHz. + ///< + ///< `Continuous Wave Mode (Non-Modulation) in single tone Mode (Center frequency +5 MHz)`: The DUT transmits a spectrum that is generated at 5MHz from the center frequency of the channel selected. + ///< Some amount of carrier leakage will be seen at Center Frequency. For example, for 2412MHz, the output would be seen at 2417 MHz. + uint16_t channel; ///< Channel number in 2.4 GHZ / 5 GHZ. + ///< ###The following table maps the channel number to the actual radio frequency in the 2.4 GHz spectrum. ### + ///< Channel numbers (2.4GHz)| Center frequencies for 20 MHz channel width + ///< :----------------------:|:-----------------------------------------------: + ///< 1 | 2412 + ///< 2 | 2417 + ///< 3 | 2422 + ///< 4 | 2427 + ///< 5 | 2432 + ///< 6 | 2437 + ///< 7 | 2442 + ///< 8 | 2447 + ///< 9 | 2452 + ///< 10 | 2457 + ///< 11 | 2462 + ///< 12 | 2467 + ///< 13 | 2472 + ///< @note To start transmit test in 12,13 channels, configure set region parameters in @ref sl_si91x_set_device_region + ///< ### The following table maps the channel number to the actual radio frequency in the 5 GHz spectrum for 20MHz channel bandwidth. The channel numbers in 5 GHz range is from 36 to 165. ### + ///< Channel Numbers(5GHz) | Center frequencies for 20MHz channel width + ///< :--------------------:|:------------------------------------------: + ///< 36 |5180 + ///< 40 |5200 + ///< 44 |5220 + ///< 48 |5240 + ///< 52 |5260 + ///< 56 |5280 + ///< 60 |5300 + ///< 64 |5320 + ///< 149 |5745 + ///< 153 |5765 + ///< 157 |5785 + ///< 161 |5805 + ///< 165 |5825 + uint16_t rate_flags; ///< Rate flags + ///< BIT(6) - Immediate Transfer, set this bit to transfer packets immediately ignoring energy/traffic in channel. + uint16_t channel_bw; ///< Channel Bandwidth + uint16_t aggr_enable; ///< tx test mode aggr_enable + uint16_t reserved; ///< Reserved + uint16_t no_of_pkts; ///< Number of packets + uint32_t delay; ///< Delay +#if defined(SLI_SI917) || defined(DOXYGEN) || defined(SLI_SI915) + uint8_t enable_11ax; ///< 11AX_ENABLE 0-disable, 1-enable + uint8_t coding_type; ///< Coding_type 0-BCC 1-LDPC + uint8_t nominal_pe; ///< Indicates Nominal T-PE value. 0-0Us 1-8Us 2-16Us + uint8_t + ul_dl; ///< Indicates whether the PPDU is UL/DL. Set it to 1 if PPDU is to be sent by station to AP; 0 if PPDU is to be sent by AP to station. + uint8_t he_ppdu_type; ///< he_ppdu_type 0-HE SU PPDU, 1-HE ER SU PPDU, 2-HE TB PPDU, 3-HE MU PPDU + uint8_t + beam_change; ///< Indicates the spatial mapping of pre-HE and HE fields. Enter 0 for pre-HE and HE fields are spatially mapped in the same way and 1 for pre-HE and HE fields are spatially mapped differently. + uint8_t bw; ///< Indicates the BW for the PPDU: 0 for 242-tone RU, 1 for upper 106-tone RU. + uint8_t + stbc; ///< Indicates whether STBC is used for PPDU transmission. Set to 0 for no STBC and 1 for STBC (only if DCM field is set to 0). + uint8_t + tx_bf; ///< Indicates whether beamforming matrix is applied to the transmission. 0 - no beamforming matrix, 1 - beamforming matrix. + uint8_t gi_ltf; ///< Indicates the GI and LTF size. GI_LTF shall be in the range 0-3 + uint8_t dcm; ///< Indicates whether DCM is applied to Data Symbols. 0 - No DCM, 1 - DCM. + uint8_t nsts_midamble; ///< Indicates the NSTS and Midamble Periodicity. NSTS_MIDAMBLE shall be in the range 0-7 + uint8_t + spatial_reuse; ///< spatial_reuse shall be in the range 0-15. 4 indicates that spatial reuse is allowed during the transmission of PPDU. + uint8_t bss_color; ///< Color value of BSS. Must be in the range 0 to 63 + uint16_t he_siga2_reserved; ///< HE_SIGA2_RESERVED shall be in the range 0-511 + uint8_t ru_allocation; ///< Indicates the RU Allocation Subfield for 20MHz BW. Must be in the range 0-255. + uint8_t n_heltf_tot; ///< Indicates the number of HE-LTF to be transmitted. Can be in the range 0-7. + uint8_t sigb_dcm; ///< Indicates whether DCM is applied to SIG-B Symbols. 0-disable, 1-enable + uint8_t sigb_mcs; ///< Indicates the MCS for SIG-B Symbols. Allowed range is 0-5. + uint16_t user_sta_id; ///< Indicates the Station ID of the intended user. Allowed range is 0-2047. + uint8_t user_idx; ///< USER_IDX shall be in the range 0-8 + uint8_t sigb_compression_field; ///< SIGB_COMPRESSION_FIELD shall be 0/1 +#endif +} sl_si91x_request_tx_test_info_t; +/** @} */ + +/// Si91x specific calibration write +typedef struct { + /* Target + * 0 - BURN_INTO_EFUSE (Burns calibration data to EFuse) + - + * 1 - BURN_INTO_FLASH (Burns calibration data to Flash) + - + **/ + uint8_t target; ///< Target + uint8_t reserved0[3]; ///< Reserved + /* Flags - Validate information + * Bit | MACRO | Description + * :---|:---------------------:|:--------------------------------------------------- + * 0 | RESERVED_0 | Reserved + * 1 | BURN_FREQ_OFFSET | 1 - Update XO Ctune to calibration data + - 0 - Skip XO Ctune update + * 2 | SW_XO_CTUNE_VALID | 1 - Use XO Ctune provided as argument to update calibration data + - 0 - Use XO Ctune value as read from hardware register + * 3 | BURN_XO_FAST_DISABLE | Used to apply patch for cold temperature issue(host interface detection) observed on CC0/CC1 modules. \ref appendix + * 4 | BURN_GAIN_OFFSET_LOW | 1 - Update gain offset for low sub-band (2 GHz) + - 0 - Skip low sub-band gain-offset update + * 5 | BURN_GAIN_OFFSET_MID | 1 - Update gain offset for mid sub-band (2 GHz) + - 0 - Skip mid sub-band gain-offset update + * 6 | BURN_GAIN_OFFSET_HIGH | 1 - Update gain offset for high sub-band (2 GHz) + - 0 - Skip high sub-band gain-offset update + * 8 | ENABLE_DPD_CALIB | 1 - Collect dpd coefficients data + - 0 - Skip dpd coefficients calibration + * 9 | BURN_DPD_COEFFICIENTS | 1 - Burn dpd coefficients data + - 0 - Skip dpd coefficients calibration + * 10 | BURN_GAIN_OFFSET_CHANNEL-14 | 1 - Update gain offset for channel-14 sub-band (2 GHz) + - 0 - Skip channel-14 sub-band gain-offset update + * 31-4 | | Reserved + **/ + uint32_t flags; ///< flags + /* +gain_offset_low - gain_offset as observed in dBm in channel-1 +gain_offset_mid - gain_offset as observed in dBm in channel-6 +gain_offset_high - gain_offset as observed in dBm in channel-11 +*/ + int8_t gain_offset[3]; ///< Gain offset + /*xo_ctune - Allow user to directly update xo_ctune value to calibration data bypassing the freq offset loop, + *valid only when BURN_FREQ_OFFSET & SW_XO_CTUNE_VALID of flags is set. The range of xo_ctune is [0, 255], and the typical value is 80 + */ + int8_t xo_ctune; ///< XO Ctune + /*gain_offset_channel-14 - gain_offset as observed in dBm in channel-14 */ + int8_t gain_offset_ch14; ///< Gain offset channel 14 +} sl_si91x_calibration_write_t; + +/// Si91x specific calibration read +typedef struct { + + /* target +* 0 - READ_FROM_EFUSE (read calibration data from the EFuse) +* 1 - READ_FROM_FLASH (read calibration data from the Flash) +*/ + uint8_t target; ///< target + uint8_t reserved0[3]; ///< Reserved + /* + gain_offset_low - gain_offset in dBm that is applied for transmissions in channel-1. + gain_offset_mid - gain_offset in dBm that is applied for transmissions in channel-6. + gain_offset_high -gain_offset in dBm that is applied for transmissions in channel-11. + */ + int8_t gain_offset[3]; ///< gain offset + + int8_t xo_ctune; ///< xo_ctune - xo_ctune value as read from the target memory. + + int8_t + gain_offset_ch14; ///< gain_offset_channel-14 - gain_offset in dBm that is applied for transmissions in channel-14. + +#if !defined(SLI_SI917) && !defined(SLI_SI915) + /// RSI EVM Data + struct rsi_evm_data_t { + int8_t evm_offset[5]; ///< Evm offset + } rsi_evm_data_t; ///< Evm data +#endif +} sl_si91x_calibration_read_t; + +/// Si91x specific frequency offset +typedef struct { + int32_t frequency_offset_in_khz; ///< Frequency offset in KHZ +} sl_si91x_freq_offset_t; + +/// Si91x specific get DPD calibration data +typedef struct { + int8_t dpd_power_index; ///< Dpd power index given by the user +} sl_si91x_get_dpd_calib_data_t; + +/// Si91x specific EVM offset +typedef struct { + int8_t evm_offset_val; /// 4 | Reserved + * */ + uint8_t evm_index; ///< EVM index +} sl_si91x_evm_offset_t; + +/// Si91x Specific EVM write +typedef struct { + /* + *Target + * 0 - BURN_INTO_EFUSE (Burns calibration data to EFuse)(Not supported) + * 1 - BURN_INTO_FLASH (Burns calibration data to Flash) + **/ + uint8_t target; ///< Target + /* + * Flags - Validate information + - + * Bit | MACRO | Description + * :---|:---------------------:|:--------------------------------------------------- + * 0 | EVM_OFFSET_CUST_0 | 1 - Update evm_offset_11B rate calibration data + - 0 - Skip evm_offset update + * 1 | EVM_OFFSET_CUST_1 | 1 - Update evm_offset_11G_6M_24M_11N_MCS0_MCS2 rate calibration data + - 0 - Skip evm_offset update + * 2 | EVM_OFFSET_CUST_2 | 1 - Update evm_offset_11G_36M_54M_11N_MCS3_MCS7 rate calibration data + - 0 - Skip evm_offset update + * 3 | EVM_OFFSET_CUST_3 | 1 - Update evm_offset_11N_MCS0 rate calibration data + - 0 - Skip evm_offset update + * 4 | EVM_OFFSET_CUST_4 | 1 - Update evm_offset_11N_MCS7 rate calibration data + - 0 - Skip evm_offset update + * 31-5| Reserved + */ + uint32_t flags; ///< Flags + uint8_t evm_offset_11B; ///< evm_offset for 11B rate + uint8_t evm_offset_11G_6M_24M_11N_MCS0_MCS2; ///< evm_offset for 11G_6M_24M_11N_MCS0_MCS2 rate + uint8_t evm_offset_11G_36M_54M_11N_MCS3_MCS7; ///< evm_offset for 11G_36M_54M_11N_MCS3_MCS7 rate + uint8_t evm_offset_11N_MCS0; ///< evm_offset for 11N_MCS0 rate + uint8_t evm_offset_11N_MCS7; ///< evm_offset for 11N_MCS7 rate +} sl_si91x_evm_write_t; + +/// Si91x specific efuse read +typedef struct { + /// Efuse read addr offset + /** + * + * |efuse_read_addr_offset | Component | Parameter | Size in bytes| Description | + * |-----------------------|---------------------|---------------------------------------|--------------|------------------------------------------------------------------------------------------------------------------------------------------------| + * | 144 | Wlan info-Cust | Magic byte |1 |Magic byte for Wlan Customer info | + * | 145 | | Reserved |1 |Reserved | + * | 146 | | Mac address |6 |If this MAC address is set, it overrides the Wlan MAC address set by Silabs. | + * | 152 | BT/BLE info-Cust | Magic byte |1 |Magic byte for BLE Customer info | + * | 153 | | Reserved |1 |Reserved | + * | 154 | | Mac address |6 |If this MAC address is set, it overrides the BLE MAC address set by Silabs. | + * | 160 | XO_offset_cust | Magic byte |1 |0x000B => XO_offset is set by customer. | + * | 161 | | XO_offset |1 |If a valid XO_OFFSET is programmed here, the one in location 259 is ignored, and this one is taken; otherwise, the one in location 259 is taken.| + * | 162 | Gain_offset_cust | cusotmer_gain_offset_1_3p3 |1 |Channel 1,2,3 | + * | 163 | | cusotmer_gain_offset_6_3p3 |1 |Channel 4,5,6,7,8 | + * | 164 | | cusotmer_gain_offset_11_3p3 |1 |Channel 9,10,11,12,13, optional 14 (this is used if 168 magic byte is not set) | + * | 165 | | cusotmer_gain_offset_1_1p8 |1 | | + * | 166 | | cusotmer_gain_offset_6_1p8 |1 | | + * | 167 | | cusotmer_gain_offset_11_1p8 |1 | | + * | 168 | | cusotmer_gain_offset_14_3p3_magic_byte|1 |Magic byte for customer gain offset CH14 0xAB | + * | 169 | | cusotmer_gain_offset_14_3p3 |1 |Customer gain offset for CH14, this is valid only when the Magic byte is valid when 168 Location. | + * | 170 | | AntiRollback space for M4 image |8 |Anti-Rollback bit map. 64 bits represent theversion numbers for Anti-rollback base. | + * | 178 | Customer EVM Offset | Magic byte |1 |0xAB => Magic byte set by customer while loading the offset | + * | 179 | | evm_offset_11B |1 | | + * | 180 | | evm_offset_11G_6M_24M_11N_MCS0_MSC2 |1 | | + * | 181 | | evm_offset_11G_36M_54M_11N_MCS3_MSC7 |1 | | + * | 182 | | evm_offset_11N_MCS0 |1 | | + * | 183 | | evm_offset_11N_MCS7 |1 | | + * | 184 | | Reserved for Customer |71 |Reserved for future use | + * | 255 | | OTP_Lock_1 |1 |Bit 0 : Lock 128-255 1 ->Lock, 0 -> Unlocked Bit 1 : Debug port was opened Bit 2 -7 : Reserved | + * */ + uint32_t efuse_read_addr_offset; + /// Efuse read data length + uint16_t efuse_read_data_len; +} sl_si91x_efuse_read_t; + +/// Si91x specific rejoin parameters +typedef struct { + uint32_t max_retry_attempts; ///< Maximum number of retries before indicating join failure. + uint32_t scan_interval; ///< Scan interval between each retry. + uint32_t + beacon_missed_count; ///< Number of missed beacons that will trigger rejoin. Minimum value of beacon_missed_count is 40. + uint32_t first_time_retry_enable; ///< Retry enable or disable for first time joining. +} sl_si91x_rejoin_params_t; + +/** \addtogroup SL_SI91X_TYPES + * @{ + * */ +/// Si917 specific Wi-Fi asynchronous statistics +typedef struct { + uint16_t tx_pkts; ///< Number of transmitted packets + uint8_t reserved_1[2]; ///< Reserved fields + uint16_t tx_retries; ///< Number of transmission retries + uint16_t crc_pass; ///< Number of packets that passed CRC check + uint16_t crc_fail; ///< Number of packets that failed CRC check + uint16_t cca_stk; ///< Number of times CCA got stuck + uint16_t cca_not_stk; ///< Number of times CCA didn't get stuck + uint16_t pkt_abort; ///< Number of packet aborts + uint16_t fls_rx_start; ///< Number of false RX starts + uint16_t cca_idle; ///< CCA idle time + uint8_t reserved_2[26]; ///< Reserved fields + uint16_t rx_retries; ///< Number of reception retries + uint8_t reserved_3[2]; ///< Reserved fields + uint16_t cal_rssi; ///< Calibrated RSSI + uint8_t reserved_4[4]; ///< Reserved fields + uint16_t xretries; ///< Number of transmitted packets dropped after maximum retries + uint16_t max_cons_pkts_dropped; ///< Maximum consecutive packets dropped + uint8_t reserved_5[2]; ///< Reserved fields + uint16_t bss_broadcast_pkts; ///< BSSID matched broadcast packets count + uint16_t bss_multicast_pkts; ///< BSSID matched multicast packets count + uint16_t bss_filter_matched_multicast_pkts; ///< BSSID & multicast filter matched packets count +} sl_si91x_async_stats_response_t; + +/// Si917 specific Wi-Fi advance statistics +typedef struct { + uint32_t beacon_lost_count; ///< Number of missed beacons + uint32_t beacon_rx_count; ///< Number of received beacons + uint32_t mcast_rx_count; ///< Multicast packets received + uint32_t mcast_tx_count; ///< Multicast packets transmitted + uint32_t ucast_rx_count; ///< Unicast packets received + uint32_t ucast_tx_count; ///< Unicast packets transmitted + uint32_t + overrun_count; ///< Number of packets dropped either at ingress or egress, due to lack of buffer memory to retain all packets. +} sl_si91x_advance_stats_response_t; +/** @} */ + +/// Debug log structure +typedef struct { + uint32_t assertion_type; ///< Assertion type. It must be in the range of 0 to 15 (both included). + uint32_t assertion_level; ///< Assertion level. It must be in the range of 0 to 15 (both included). +} sl_si91x_debug_log_t; + +//! @cond Doxygen_Suppress +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +typedef struct crypto_key_s { + uint32_t key_slot; ///< For built-in key + uint32_t wrap_iv_mode; ///< IV mode 0-> ECB; 1-> CBC + uint8_t wrap_iv[16]; ///< IV for CBC mode + uint8_t key_buffer[32]; ///< Key data wrapped/ Plain text +} sl_si91x_crypto_key_t; + +typedef struct { + uint32_t key_size; + sl_si91x_crypto_key_t key_spec; +} sl_si91x_key_info_t; + +typedef struct { + uint32_t key_type; + uint32_t reserved; + sl_si91x_key_info_t key_detail; +} sl_si91x_key_descriptor_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint16_t total_msg_length; + uint16_t encrypt_decryption; + uint16_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *IV; + uint8_t *msg; + uint8_t *output; +} sl_si91x_aes_request_t; + +typedef struct { + uint32_t key_type; + uint16_t padding; + uint16_t hmac_sha_mode; + uint32_t key_size; + uint32_t wrap_iv_mode; + uint8_t *wrap_iv; + uint8_t *key_buffer; +} sl_si91x_wrap_key_descriptor_t; + +typedef struct { + uint16_t algorithm_type; + uint16_t output_length; + sl_si91x_wrap_key_descriptor_t key_info; + uint8_t *output; +} sl_si91x_wrap_request_t; + +typedef struct { + uint16_t algorithm_type; + uint16_t algorithm_sub_type; + uint16_t total_length; + uint16_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *hmac_data; + uint8_t *output; +} sl_si91x_hmac_sha_request_t; + +typedef struct { + uint16_t algorithm_type; + uint16_t algorithm_sub_type; + uint16_t total_msg_length; + uint16_t output_length; + uint8_t *msg; + uint8_t *output; +} sl_si91x_sha_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t nonce_length; + uint16_t encrypt_decryption; + uint16_t total_msg_length; + uint16_t ad_length; + uint16_t tag_length; + uint16_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *nonce; + uint8_t *ad; + uint8_t *tag; // tag size = 16 + uint8_t *msg; + uint8_t *output; +} sl_si91x_ccm_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t dma_use; + uint8_t gcm_mode; + uint8_t encrypt_decryption; + uint16_t total_msg_length; + uint16_t ad_length; + uint32_t output_length; + sl_si91x_key_descriptor_t key_info; + uint8_t *nonce; // iv length = 12 bytes + uint8_t *ad; + uint8_t *msg; + uint8_t *output; +} sl_si91x_gcm_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t encrypt_decryption; + uint8_t dma_use; + uint16_t total_msg_length; + uint16_t header_length; + uint32_t output_length; + uint8_t *nonce; + sl_si91x_key_descriptor_t key_info; + uint8_t *header_input; + uint8_t *msg; + uint8_t *output; +} sl_si91x_chachapoly_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *tx; + uint8_t *ty; + uint8_t *tz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_add_sub_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint32_t affinity; + uint8_t *d; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_mul_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_double_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint8_t *sx; + uint8_t *sy; + uint8_t *sz; + uint8_t *rx; + uint8_t *ry; + uint8_t *rz; +} sl_si91x_ecdh_affine_request_t; + +/// Si91x Specific TRNG request +typedef struct { + uint8_t algorithm_type; ///< Algorithm type + uint8_t algorithm_sub_type; ///< Algorithm sub type + uint16_t total_msg_length; ///< Total message length + uint8_t *trng_key; ///< TRNG key + uint8_t *msg; ///< Message + uint8_t *output; ///< Output +} sl_si91x_trng_request_t; + +/// Attestation token Request Frames Structures +typedef struct { + uint16_t algorithm_type; ///< Algorithm type + uint16_t total_msg_length; ///< Total message length + uint32_t *msg; ///< Message + uint8_t *token_buf; ///< Token buffer +} sl_si91x_rsi_token_req_t; +#else +typedef struct crypto_key_s { + uint32_t key_slot; ///< For built-in key + uint32_t wrap_iv_mode; ///< IV mode 0-> ECB; 1-> CBC + uint8_t wrap_iv[16]; ///< IV for CBC mode + uint8_t key_buffer[32]; ///< Key data wrapped/ Plain text +} sl_si91x_crypto_key_t; + +typedef struct { + uint32_t key_size; + sl_si91x_crypto_key_t key_spec; +} sl_si91x_key_info_t; + +typedef struct { + uint32_t key_type; + uint32_t reserved; + sl_si91x_key_info_t key_detail; +} sl_si91x_key_descriptor_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t aes_flags; + uint16_t total_msg_length; + uint16_t current_chunk_length; + uint32_t encrypt_decryption; +#if defined(SLI_SI917B0) || defined(SLI_SI915) + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; + uint8_t key[32]; +#endif + uint8_t IV[16]; + uint8_t msg[1400]; +} sl_si91x_aes_request_t; + +typedef struct { + uint32_t key_type; + uint16_t padding; + uint16_t hmac_sha_mode; + uint32_t key_size; + uint32_t wrap_iv_mode; + uint8_t wrap_iv[16]; + uint8_t key_buffer[1400]; +} sl_si91x_wrap_key_descriptor_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t wrap_flags; + uint16_t current_chunk_length; + sl_si91x_wrap_key_descriptor_t key_info; +} sl_si91x_wrap_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t hmac_sha_flags; + uint16_t total_length; + uint16_t current_chunk_length; +#if defined(SLI_SI917B0) || defined(SLI_SI915) + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; +#endif + uint8_t hmac_data[1400]; +} sl_si91x_hmac_sha_request_t; + +/// Si91x specific SHA request +typedef struct { + uint16_t algorithm_type; ///< Algorithm type + uint8_t algorithm_sub_type; ///< Algorithm sub type + uint8_t sha_flags; ///< SHA flags + uint16_t total_msg_length; ///< Total message length + uint16_t current_chunk_length; ///< Current chunk length + uint8_t msg[1400]; ///< Message +} sl_si91x_sha_request_t; + +/// Si91x specific CCM request +typedef struct { + uint16_t algorithm_type; ///< Algorithm type + uint8_t ccm_flags; ///< CCM flags + uint8_t nonce_length; ///< Nonce length + uint16_t encrypt_decryption; ///< Encrypt/Decrypt + uint16_t total_msg_length; ///< Total message length + uint16_t current_chunk_length; ///< Current chunk length + uint16_t ad_length; ///< AD length + uint32_t tag_length; ///< Tag length +#if defined(SLI_SI917B0) || defined(SLI_SI915) + sl_si91x_key_descriptor_t key_info; ///< Key info +#else + uint32_t key_length; ///< Key length + uint8_t key[SL_SI91X_KEY_BUFFER_SIZE]; ///< Key +#endif + uint8_t nonce[SL_SI91X_CCM_IV_BUFF_LEN]; ///< Nonce + uint8_t ad[SL_SI91X_CCM_AD_MAX_SIZE]; ///< AD + uint8_t tag[SL_SI91X_TAG_SIZE]; ///< tag size = 16 + uint8_t msg[SL_SI91X_CCM_MSG_MAX_SIZE]; ///< max msg size = 1200 bytes +} sl_si91x_ccm_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t gcm_flags; + uint8_t encrypt_decryption; + uint16_t total_msg_length; + uint16_t current_chunk_length; + uint16_t ad_length; + uint16_t dma_use; +#if defined(SLI_SI917B0) || defined(SLI_SI915) + uint32_t gcm_mode; + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; + uint8_t key[SL_SI91X_KEY_BUFFER_SIZE]; +#endif + uint8_t nonce[SL_SI91X_GCM_IV_SIZE]; // iv length = 12 bytes + uint8_t ad[SL_SI91X_GCM_AD_MAX_SIZE]; + uint8_t msg[SL_SI91X_GCM_MSG_MAX_SIZE]; +} sl_si91x_gcm_request_t; + +typedef struct { + uint16_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t chachapoly_flags; + uint16_t total_msg_length; + uint16_t header_length; + uint16_t current_chunk_length; + uint16_t encrypt_decryption; + uint32_t dma_use; + uint8_t nonce[SL_SI91X_IV_SIZE]; +#if defined(SLI_SI917B0) || defined(SLI_SI915) + sl_si91x_key_descriptor_t key_info; +#else + uint8_t key_chacha[SL_SI91X_KEY_BUFFER_SIZE]; + uint8_t keyr_in[SL_SI91X_KEYR_SIZE]; + uint8_t keys_in[SL_SI91X_KEYS_SIZE]; +#endif + uint8_t header_input[SL_SI91X_GCM_AD_MAX_SIZE]; + uint8_t msg[SL_SI91X_CHACHAPOLY_MSG_MAX_SIZE]; +} sl_si91x_chachapoly_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t algorithm_sub_type; + uint8_t ecdsa_flags; + uint8_t curve_id; + uint8_t sha_mode; + uint8_t private_key_length; + uint8_t public_key_length; + uint8_t signature_length; + uint16_t current_chunk_length; + uint16_t msg_len; +#if defined(SLI_SI917B0) || defined(SLI_SI915) + sl_si91x_key_descriptor_t key_info; +#else + uint32_t key_length; +#endif + uint8_t private_key[SL_SI91X_PRIVATE_KEY_MAX_SIZE]; + uint8_t public_key[SL_SI91X_PUBLIC_KEY_MAX_SIZE]; + uint8_t signature[SL_SI91X_SIGNATURE_MAX_SIZE]; + uint8_t msg[SL_SI91X_ECDSA_MSG_MAX_SIZE]; +} sl_si91x_ecdsa_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; + uint8_t tx[ECDH_BUFFER_SIZE]; + uint8_t ty[ECDH_BUFFER_SIZE]; + uint8_t tz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_add_sub_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint32_t affinity; + uint8_t d[ECDH_BUFFER_SIZE]; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_mul_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_double_request_t; + +typedef struct { + uint8_t algorithm_type; + uint8_t ecdh_mode; + uint8_t ecdh_sub_mode; + uint8_t ecdh_curve_type; + uint8_t sx[ECDH_BUFFER_SIZE]; + uint8_t sy[ECDH_BUFFER_SIZE]; + uint8_t sz[ECDH_BUFFER_SIZE]; +} sl_si91x_ecdh_affine_request_t; + +/// Si91x specific TRNG request +typedef struct { + uint8_t algorithm_type; ///< Algorithm type + uint8_t algorithm_sub_type; ///< Algorithm sub type + uint16_t total_msg_length; ///< Total message length + uint32_t trng_key[TRNG_KEY_SIZE]; ///< TRNG key + uint32_t msg[TRNG_TEST_DATA_SIZE]; ///< Message +} sl_si91x_trng_request_t; + +/// Attestation token Request Frames Structures +typedef struct { + uint8_t algorithm_type; ///< Algorithm type + uint16_t total_msg_length; ///< Total message length + uint32_t msg[NONCE_DATA_SIZE]; ///< Message +} sl_si91x_rsi_token_req_t; + +#endif +//! @endcond + +/// Request timeout Structure +typedef struct { + uint32_t timeout_bitmap; ///< Timeout bitmap + uint16_t timeout_value; ///< Timeout value +} sl_si91x_request_timeout_t; + +/// High throughputs enable command +typedef struct { + uint16_t mode_11n_enable; ///< 11n mode enable + uint16_t ht_caps_bitmap; ///< HT caps bitmap +} sl_si91x_request_ap_high_throughput_capability_t; diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_status.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_status.h new file mode 100644 index 000000000..19804bacf --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_status.h @@ -0,0 +1,89 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once +typedef enum { + RSI_ERROR_NONE = 0, + RSI_ERROR_TIMEOUT = -1, + RSI_ERROR_INVALID_PARAM = -2, + RSI_ERROR_COMMAND_GIVEN_IN_WRONG_STATE = -3, + RSI_ERROR_PKT_ALLOCATION_FAILURE = -4, + RSI_ERROR_COMMAND_NOT_SUPPORTED = -5, + RSI_ERROR_INSUFFICIENT_BUFFER = -6, + RSI_ERROR_IN_OS_OPERATION = -7, + RSI_ERROR_INVALID_MEMORY = -8, + RSI_ERROR_BOOTUP_OPTIONS_NOT_SAVED = -9, + RSI_ERROR_BOOTUP_OPTIONS_CHECKSUM_FAIL = -10, + RSI_ERROR_BOOTLOADER_VERSION_NOT_MATCHING = -11, + RSI_ERROR_WAITING_FOR_BOARD_READY = -12, + RSI_ERROR_INVALID_ADDRESS = -13, + RSI_ERROR_VALID_FIRMWARE_NOT_PRESENT = -14, + RSI_ERROR_INVALID_OPTION = -15, + RSI_ERROR_EXCEEDS_MAX_CALLBACKS = -16, + RSI_ERROR_SET_ITIMER = -17, + RSI_ERROR_SIG_ACTION = -18, + RSI_ERROR_NOT_IN_CONNECTED_STATE = -19, + RSI_ERROR_NOT_IN_IPCONFIG_STATE = -20, + RSI_ERROR_SPI_BUSY = -21, + RSI_ERROR_SPI_FAIL = -22, + RSI_ERROR_SPI_TIMEOUT = -23, + RSI_ERROR_CARD_READY_TIMEOUT = -24, + RSI_ERROR_BOARD_READY_TIMEOUT = -25, + RSI_ERROR_INVALID_PACKET = -26, + RSI_ERROR_FW_UPGRADE_TIMEOUT = -27, + RSI_ERROR_FW_LOAD_OR_UPGRADE_TIMEOUT = -28, + RSI_ERROR_GPIO_WAKEUP_TIMEOUT = -29, + RSI_ERROR_RESPONSE_TIMEOUT = -30, + RSI_ERROR_BLE_DEV_BUF_FULL = -31, + RSI_ERROR_NWK_CMD_IN_PROGRESS = -32, + RSI_ERROR_SOCKET_CMD_IN_PROGRESS = -33, + RSI_ERROR_WLAN_CMD_IN_PROGRESS = -34, + RSI_ERROR_COMMON_CMD_IN_PROGRESS = -35, + RSI_ERROR_ANT_DEV_BUF_FULL = -36, + RSI_ERROR_BT_BLE_CMD_IN_PROGRESS = -37, + RSI_ERROR_ANT_CMD_IN_PROGRESS = -38, + RSI_ERROR_BLE_ATT_CMD_IN_PROGRESS = -39, + RSI_ERROR_MEMORY_NOT_ALIGNED = -40, + RSI_ERROR_SEMAPHORE_CREATE_FAILED = -41, + RSI_ERROR_SEMAPHORE_DESTROY_FAILED = -42, + RSI_ERROR_IN_WLAN_CMD = -43, + RSI_ERROR_RX_BUFFER_CHECK = -44, + RSI_ERROR_PARAMETER_LENGTH_EXCEEDS_MAX_VAL = -45, + RSI_ERROR_IN_COMMON_CMD = -46, + RSI_ERROR_TX_BUFFER_FULL = -47, + RSI_ERROR_SDIO_TIMEOUT = -48, + RSI_ERROR_SDIO_WRITE_FAIL = -49, + RSI_ERROR_INVALID_SET_CONFIG_FLAG = -50, + RSI_ERROR_BLE_DEV_BUF_IS_IN_PROGRESS = -51, + RSI_ERROR_SET_REGION_NOT_ENABLED = -52, + RSI_ERROR_BLE_INVALID_CALLBACK_CNT = -53, + RSI_ERROR_BLE_ADV_EXT_COMMAND_NOT_ALLOWED = -54, + RSI_ERROR_BLE_LEGACY_COMMAND_NOT_ALLOWED = -55, + RSI_ERROR_TRNG_DUPLICATE_ENTROPY = -56 +} si91x_status_t; diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h new file mode 100644 index 000000000..e69292888 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_si91x_types.h @@ -0,0 +1,252 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_si91x_constants.h" +#include "sl_wifi_host_interface.h" +#include + +/* NUMBER_OF_BSD_SOCKETS must be < 32 (sizeof(unsigned) * 8) */ +typedef struct sl_si91x_fd_set { + unsigned int __fds_bits; +} sl_si91x_fd_set; + +/// Flag to indicate that the response status of the command is expected. +#define SI91X_PACKET_RESPONSE_STATUS (1 << 0) + +/// Flag to indicate that the response packet of the command is expected. +#define SI91X_PACKET_RESPONSE_PACKET (1 << 1) + +/// Flag to indicate that all the packet tx has to be suspended until the corresponding command response is received. +#define SI91X_PACKET_GLOBAL_QUEUE_BLOCK (1 << 3) + +/// Flag to indicate that host would receive the response from firmware in asynchronous manner. +#define SI91X_PACKET_WITH_ASYNC_RESPONSE (1 << 4) + +/// Si91x specific command type +typedef enum { + SI91X_COMMON_CMD = 0, ///< SI91X Common Command + SI91X_WLAN_CMD = 1, ///< SI91X Wireless LAN Command + SI91X_NETWORK_CMD = 2, ///< SI91X Network Command + SI91X_BT_CMD = 3, ///< SI91X Bluetooth Command + SI91X_SOCKET_CMD = 4, ///< SI91X Socket Command + SI91X_CMD_MAX, ///< SI91X Maximum Command value +} sl_si91x_command_type_t; + +/** \addtogroup SL_SI91X_CONSTANTS + * @{ + * */ +/// Si91x band mode. +/// @note Only 2.4 GHz is currently supported. +typedef enum { + SL_SI91X_WIFI_BAND_2_4GHZ = 0, ///< 2.4 GHz Wi-Fi band + SL_SI91X_WIFI_BAND_5GHZ = 1, ///< 5 GHz Wi-Fi band (not currently supported) + SL_SI91X_WIFI_DUAL_BAND = 2 ///< Both 2.4 GHz and 5 GHZ WiFi band (not currently supported) +} sl_si91x_band_mode_t; + +/// Si91x region code. +/// @note Singapore region not currently supported. +typedef enum { + DEFAULT_REGION, ///< Factory default region + US, ///< United States + EU, ///< European Union + JP, ///< Japan + WORLD_DOMAIN, ///< Worldwide domain + KR, ///< Korea + SG, ///< Singapore (not currently supported) + CN, ///< China + IGNORE_REGION ///< Do not update region code during initialization +} sl_si91x_region_code_t; + +/// Si91x Timeout types +typedef enum { + SL_SI91X_AUTHENTICATION_ASSOCIATION_TIMEOUT = + 0, ///< Used for setting association and authentication timeout request in milliseconds + SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT, ///< Used for setting dwell time per channel in milliseconds during active scan + SL_SI91X_KEEP_ALIVE_TIMEOUT, ///< Used for setting WLAN keep alive time in seconds + SL_SI91X_CHANNEL_PASSIVE_SCAN_TIMEOUT ///< Used for setting dwell time per channel in milliseconds during passive scan +} sl_si91x_timeout_type_t; + +/// Si91x Wi-Fi VAP ID +typedef enum { + SL_SI91X_WIFI_CLIENT_VAP_ID, ///< Wi-Fi Client VAP ID + SL_SI91X_WIFI_AP_VAP_ID, ///< Wi-Fi Access Point VAP ID +} sl_si91x_wifi_vap_id_t; +/** @} */ + +/** \addtogroup SL_SI91X_TYPES + * @{ + * */ +// NWP RSI_COMMON_REQ_OPERMODE command request structure +// Note: refer sl_wifi_device.h for complete bit map details +/// Si91x boot configuration structure +typedef struct { + uint16_t oper_mode; ///< Operation mode, one of the values from @ref sl_si91x_operation_mode_t. + uint16_t coex_mode; ///< Coexistence mode, one of the values from @ref sl_si91x_coex_mode_t. + uint32_t feature_bit_map; ///< Feature bit map, @ref SI91X_FEATURE_BITMAP + uint32_t tcp_ip_feature_bit_map; ///< TCP/IP feature bit map, @ref SI91X_TCP_IP_FEATURE_BITMAP + uint32_t custom_feature_bit_map; ///< Custom feature bit map, @ref SI91X_CUSTOM_FEATURE_BITMAP + uint32_t ext_custom_feature_bit_map; ///< Extended custom feature bit map, @ref SI91X_EXTENDED_CUSTOM_FEATURE_BITMAP + uint32_t bt_feature_bit_map; ///< BT featured bit map, @ref SI91X_BT_FEATURE_BITMAP + uint32_t ext_tcp_ip_feature_bit_map; ///< Extended TCP/IP feature bit map, @ref SI91X_EXTENDED_TCP_IP_FEATURE_BITMAP + uint32_t ble_feature_bit_map; ///< BLE feature bitmap, @ref SI91X_BLE_FEATURE_BITMAP + uint32_t ble_ext_feature_bit_map; ///< BLE extended feature bitmap, @ref SI91X_EXTENDED_BLE_CUSTOM_FEATURE_BITMAP + uint32_t config_feature_bit_map; ///< Config feature bitmap, @ref SI91X_CONFIG_FEATURE_BITMAP +} sl_si91x_boot_configuration_t; + +/// Timeout Configuration Structure +typedef struct { + uint16_t + active_chan_scan_timeout_value; ///< Time spent on each channel when performing active scan (milliseconds). Default value of 100 millisecs is used when SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME is passed. + uint16_t + auth_assoc_timeout_value; ///< Authentication and association timeout value. Default value of 300 millisecs is used when SL_WIFI_DEFAULT_AUTH_ASSOCIATION_TIMEOUT is passed. + uint16_t + keep_alive_timeout_value; ///< Keep Alive Timeout value. Default value of 30 seconds is used when SL_WIFI_DEFAULT_KEEP_ALIVE_TIMEOUT is passed. + uint16_t + passive_scan_timeout_value; ///< Time spent on each channel when performing passive scan (milliseconds). The minimum passive_scan_timeout_value is 5 millisecs, and maximum is 1000 milliseconds. Default value of 400 milliseconds is used when SL_WIFI_DEFAULT_PASSIVE_CHANNEL_SCAN_TIME is passed. +} sl_si91x_timeout_t; + +/// Si917 specific Wi-Fi module state statistics +#pragma pack(1) +typedef struct { + uint32_t + timestamp; ///< Timestamp. This is value of counter at the time of message. This counter is continuously incremented by one per 100ms time. + uint8_t + state_code; ///< State code. This field indicates state of the module. state code contain two parts (upper and lower nibbles). Upper nibble represent the state of rejoin process and StateCode represented by the lower nibble of state code. + uint8_t reason_code; ///< Reason code. This is used to get the reason code from firmware point of view. + uint8_t + channel; ///< Channel number. If value of channel is 0, it means channel information is not available. In State-I, channel of association or Invalid if it is startup. In State-II, channel of next association if module finds better AP in bgscan result. In State-III, Channel at the time of association. + uint8_t + rssi; ///< RSSI VALUE. If value of rssi is 100, it means RSSI information is not available. In State-I it is RSSI of AP at the time of trigger. In State-II it is RSSI of next association. In State-III it is RSSI at the time of final association. + uint8_t bssid + [6]; ///< BSSID of AP. If the value of AP BSSID is 00:00:00:00:00:00,it means MAC information is not available. In State-I it is MAC of AP at the time of scan trigger. In State-II it is MAC of next association. In State-III it is MAC at the time of association. +} sl_si91x_module_state_stats_response_t; +#pragma pack() + +/// Firmware version information +typedef struct { + uint8_t build_num; ///< Build number of the firmware + uint8_t security_version; ///< Security version indicating if security is enabled or disabled + uint8_t minor; ///< Minor version number of the firmware + uint8_t major; ///< Major version number of the firmware +} sl_si91x_fw_version_info_t; + +/// Firmware version extended information +typedef struct { + uint8_t patch_num; ///< Patch number of the firmware + uint8_t customer_id : 4; ///< Customer ID + uint8_t build_number_extension : 4; ///< Build number extension + uint8_t rom_id; ///< ROM ID of the firmware + uint8_t chip_id; ///< Chip ID of the device +} sl_si91x_fw_version_ext_info_t; + +/// Firmware header information +typedef struct { + uint16_t control_flags; ///< Control flags for the firmware image. + uint16_t sha_type; ///< SHA type used for the firmware image. + uint32_t magic_no; ///< Magic number identifying the firmware image. + uint32_t image_size; ///< Size of the firmware image in bytes. + sl_si91x_fw_version_info_t fw_version_info; ///< Firmware version information. + uint32_t flash_location; ///< Address location in flash memory where the firmware image is stored. + uint32_t crc; ///< Cyclic Redundancy Check (CRC) value of the firmware image. + uint32_t mic[4]; ///< Message Integrity Code (MIC) of the firmware image. + uint32_t reserved; ///< Reserved fields for future use. + sl_si91x_fw_version_ext_info_t fw_version_ext_info; ///< Firmware version extended information. + uint32_t reserved1[4]; ///< Reserved fields for future use. +} sl_si91x_firmware_header_t; + +/** @} */ + +#if defined(__Keil) +#pragma anon_unions +#endif + +// driver TX/RX packet structure +/// Si91x packet structure +typedef struct { + union { + struct { + uint16_t length; ///< Length of data + uint16_t command; ///< Si91x command type + uint8_t unused + [12]; ///< Contains command status and other additional information. Unused for TX and only used for rx packets. + }; + uint8_t desc[16]; ///< Si91x packet header + }; ///< Command header + + uint8_t data[]; ///< Data to be transmitted or received +} sl_si91x_packet_t; + +/// Si91x queue packet structure +typedef struct { + sl_wifi_buffer_t *host_packet; ///< Si91x host buffer + uint8_t firmware_queue_id; ///< Si91x firmware queue id + sl_si91x_command_type_t command_type; ///< Si91x command type + // uint16_t packet_id; ///< Packet id, used internally to track packets + uint8_t flags; ///< One of the values from Si91x packet response flags + uint16_t frame_status; ///< Si91x command status + void *sdk_context; ///< SDK context, unused internally to invoke user callbacks + uint32_t command_timeout; ///< Si91x command timeout + uint32_t command_tickcount; ///< command_tickcount stores the tickcount when the command is given to the bus thread. +} sli_si91x_queue_packet_t; + +/// Si91x specific buffer queue structure +typedef struct { + sl_wifi_buffer_t *head; ///< Head + sl_wifi_buffer_t *tail; ///< Tail +} sl_si91x_buffer_queue_t; + +/// NWP buffer allocation command parameters +/// The summation of all three ratios should max 10 and the ratio should be in decimal value. +typedef struct { + uint8_t tx_ratio_in_buffer_pool; ///< tx ratio + uint8_t rx_ratio_in_buffer_pool; ///< rx ratio + uint8_t global_ratio_in_buffer_pool; ///< global ratio +} sl_si91x_dynamic_pool; + +/// Structure to represent a command queue +typedef struct { + sl_si91x_buffer_queue_t tx_queue; ///< TX queue + sl_si91x_buffer_queue_t rx_queue; ///< RX queue + sl_si91x_buffer_queue_t event_queue; ///< Event queue + void *mutex; ///< Pointer to mutex + uint32_t flag; ///< Flags + bool sequential; ///< Indicates if the commands are sequential + bool command_in_flight; ///< Indicates if a command is currently being processed + uint16_t frame_type; ///< Type of the frame associated with the command + uint8_t firmware_queue_id; ///< ID of the firmware queue for the command + uint32_t rx_counter; ///< Counter for received packets + uint32_t tx_counter; ///< Counter for transmitted packets + uint16_t packet_id; ///< ID of the packet associated with the command + uint8_t flags; ///< Flags associated with the command + uint32_t command_tickcount; ///< Command tick count + uint32_t command_timeout; ///< Command timeout + void *sdk_context; ///< Context data associated with the command +} sli_si91x_command_queue_t; diff --git a/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_wifi_device.h b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_wifi_device.h new file mode 100644 index 000000000..81c20493a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/inc/sl_wifi_device.h @@ -0,0 +1,2336 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_si91x_status.h" +#include "sl_si91x_types.h" +#include "sl_si91x_protocol_types.h" +#include "sl_bit.h" +#include "sl_wifi_types.h" +#include +#include + +//! @cond Doxygen_Suppress +#ifndef BIT +#define BIT(a) ((uint32_t)1U << a) +#endif + +#define NETWORK_INTERFACE_VALID(x) (x == SL_NET_WIFI_CLIENT_INTERFACE) || (x == SL_NET_WIFI_AP_INTERFACE) + +// NOTE: The value for SL_SI91X_SI917_RAM_MEM_CONFIG will be fetched from respective si91x_mem_config_1/2/3.slcc +#ifdef SLI_SI91X_MCU_INTERFACE +#if SL_SI91X_SI917_RAM_MEM_CONFIG == 1 +#define MEMORY_CONFIG SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC +#elif SL_SI91X_SI917_RAM_MEM_CONFIG == 2 +#define MEMORY_CONFIG SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM +#elif SL_SI91X_SI917_RAM_MEM_CONFIG == 3 +#define MEMORY_CONFIG SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV +#endif +#else +#define MEMORY_CONFIG SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE +#endif + +//! @endcond + +/** \addtogroup SI91X_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// feature bit map parameters description !// +/*=========================================================================*/ +/** + * @def SL_SI91X_FEAT_SECURITY_OPEN + * @brief Security type: Open. + * @details + * This feature supports open security type in client mode. + * + * @note It is recommended to enable this macro when configuring the security type as open mode. + */ +#define SL_SI91X_FEAT_SECURITY_OPEN BIT(0) + +/** + * @def SL_SI91X_FEAT_SECURITY_PSK + * @brief Security type: WPA/WPA2. + * @details + * This feature supports WPA/WPA2 security type in client mode. + * + * @note It is recommended to enable this macro when configuring the security type as WPA, WPA2, or any other security modes. + */ +#define SL_SI91X_FEAT_SECURITY_PSK BIT(1) + +/** + * @def SL_SI91X_FEAT_AGGREGATION + * @brief Aggregation support. + * @details + * Enables support for packet aggregation. + * + * @note Supports AMPDU for both TX and RX. + */ +#define SL_SI91X_FEAT_AGGREGATION BIT(2) + +/** + * @def SL_SI91X_FEAT_LP_GPIO_BASED_HANDSHAKE + * @brief Low Power (LP) mode GPIO handshake. + * @details + * Enables GPIO-based handshake for low power mode. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_LP_GPIO_BASED_HANDSHAKE BIT(3) + +/** + * @def SL_SI91X_FEAT_ULP_GPIO_BASED_HANDSHAKE + * @brief Ultra Low Power (ULP) mode GPIO handshake. + * @details + * Enables GPIO-based handshake for ultra low power mode. + * + * @note Not applicable for SoC + */ +#define SL_SI91X_FEAT_ULP_GPIO_BASED_HANDSHAKE BIT(4) + +/** + * @def SL_SI91X_FEAT_DEV_TO_HOST_ULP_GPIO_1 + * @brief ULP GPIO 1 wake-up indication. + * @details + * Configures ULP GPIO 1 for wake-up indication. + */ +#define SL_SI91X_FEAT_DEV_TO_HOST_ULP_GPIO_1 BIT(5) + +/** + * @def SL_SI91X_FEAT_RF_SUPPLY_VOL_3_3_VOLT + * @brief 3.3V RF supply. + * @details + * Configures the device to use a 3.3V power supply for RF. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_RF_SUPPLY_VOL_3_3_VOLT BIT(6) + +/** + * @def SL_SI91X_FEAT_WPS_DISABLE + * @brief Disable WPS in AP mode. + * @details + * Disables Wi-Fi Protected Setup (WPS) functionality in Client and Access Point (AP) mode. + */ +#define SL_SI91X_FEAT_WPS_DISABLE BIT(7) + +/** + * @def SL_SI91X_FEAT_EAP_LEAP_IN_COEX + * @brief Enable EAP-LEAP mode. + * @details + * Enables Extensible Authentication Protocol - Lightweight Extensible Authentication Protocol (EAP-LEAP) in coexistence mode. + */ +#define SL_SI91X_FEAT_EAP_LEAP_IN_COEX BIT(8) + +/** + * @def SL_SI91X_FEAT_HIDE_PSK_CREDENTIALS + * @brief Hide sensitive credentials. + * @details + * Hides sensitive information such as Pre-Shared Key (PSK), Pairwise Master Key (PMK), and EAP credentials. + */ +#define SL_SI91X_FEAT_HIDE_PSK_CREDENTIALS BIT(9) + +/** + * @def SL_SI91X_FEAT_SSL_HIGH_STREAMING_BIT + * @brief High SSL streaming throughput. + * @details + * Enables high throughput for Secure Sockets Layer (SSL) streaming. + */ +#define SL_SI91X_FEAT_SSL_HIGH_STREAMING_BIT BIT(10) + +/** + * @def SL_SI91X_FEAT_LONG_ICMP_PACKET + * @brief Support for long-sized ICMP packets. + * @details + * Enables support for long-sized Internet Control Message Protocol (ICMP) packets. Maximum 1472 bytes for IPv4 and 1452 bytes for IPv6. + * + * @note Bit 11 are reserved. + */ +#define SL_SI91X_FEAT_LONG_ICMP_PACKET BIT(12) + +/** + * @def SL_SI91X_FEAT_TRANSCEIVER_MAC_PEER_DS_SUPPORT + * @brief MAC layer peer information storage. + * @details + * Enables support to store peer information in the MAC layer in Transceiver mode of operation. + */ +#define SL_SI91X_FEAT_TRANSCEIVER_MAC_PEER_DS_SUPPORT BIT(13) + +/** + * @def SL_SI91X_FEAT_LONG_HTTP_URL + * @brief Support for long HTTP GET URLs. + * @details + * Enables support for long HTTP GET URLs. The maximum URL length supported is 2048 bytes. + */ +#define SL_SI91X_FEAT_LONG_HTTP_URL BIT(14) + +/** + * @def SL_SI91X_FEAT_DISABLE_11AX_SUPPORT + * @brief Disable 11ax connections. + * @details + * Force DUT connection (in station mode) to use 11n, disabling 11ax connections. + */ +#define SL_SI91X_FEAT_DISABLE_11AX_SUPPORT BIT(15) +/** @} */ + +/** + * @def SLI_SI91X_FEAT_FW_UPDATE_NEW_CODE + * @brief Indicates support for a new set of firmware update result codes. This bit is used for internal purpose. + * @details + * This bit in the feature bitmap is used to inform the NWP firmware whether + * the host supports a new set of result codes to differentiate firmware update + * results from other non-firmware-related results. If this bit is set, + * the NWP firmware will send result codes from the new set after a firmware update. + * If the bit is not set, the legacy result codes will be used. + */ +#define SLI_SI91X_FEAT_FW_UPDATE_NEW_CODE BIT(16) + +/** \addtogroup SI91X_FEATURE_BITMAP + * @{ */ +/** + * @def SL_SI91X_FEAT_SECURE_ATTESTATION + * @brief Secure attestation. + * @details + * Enables secure attestation functionality. + * + * @note Bit(16) is used internally by SDK. Bit 17-29 and Bit 31 is reserved. + */ +#define SL_SI91X_FEAT_SECURE_ATTESTATION BIT(30) +/** @} */ + +/** \addtogroup SI91X_TCP_IP_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// TCP/IP feature bit map parameters description !// +/*=========================================================================*/ +/** + * @def SL_SI91X_TCP_IP_FEAT_BYPASS + * @brief Enables the TCP/IP bypass feature. + * + * @details + * When this feature is enabled, the TCP/IP stack processing is bypassed, + * allowing raw Ethernet frames to be sent and received. This is useful + * for applications that require direct control over Ethernet frames or + * for implementing custom network protocols. + * + * This is defined as a bit flag that can be set in the feature configuration + * to enable the TCP/IP bypass. + */ + +#define SL_SI91X_TCP_IP_FEAT_BYPASS BIT(0) + +/// @note Bit 1 is reserved + +/** + * @def SL_SI91X_TCP_IP_FEAT_DHCPV4_CLIENT + * @brief Enables the DHCPv4 client feature. + * + * @details + * This feature allows the device to obtain an IPv4 address, + * subnet mask, default gateway, and DNS server from a DHCP server. + */ +#define SL_SI91X_TCP_IP_FEAT_DHCPV4_CLIENT BIT(2) + +/** + * @def SL_SI91X_TCP_IP_FEAT_DHCPV6_CLIENT + * @brief Enables the DHCPv6 client feature. + * + * @details + * This feature allows the device to obtain an IPv6 address + * and other network configuration details from a DHCPv6 server. + */ +#define SL_SI91X_TCP_IP_FEAT_DHCPV6_CLIENT BIT(3) + +/** + * @def SL_SI91X_TCP_IP_FEAT_DHCPV4_SERVER + * @brief Enables the DHCPv4 server feature. + * + * @details + * This feature allows the device to act as a DHCPv4 server, providing IPv4 + * addresses and network configuration to DHCPv4 clients on the network. + */ +#define SL_SI91X_TCP_IP_FEAT_DHCPV4_SERVER BIT(4) + +/** + * @def SL_SI91X_TCP_IP_FEAT_DHCPV6_SERVER + * @brief Enables the DHCPv6 server feature. + * + * @details + * This feature allows the device to act as a DHCPv6 server, providing IPv6 + * addresses and network configuration to DHCPv6 clients on the network. + */ +#define SL_SI91X_TCP_IP_FEAT_DHCPV6_SERVER BIT(5) + +/** + * @def SL_SI91X_TCP_IP_FEAT_JSON_OBJECTS + * @brief Enables support for JSON objects. + * + * @details + * This feature allows the device to handle JSON (JavaScript Object Notation) + * objects, which can be used for data interchange in web applications. + */ +#define SL_SI91X_TCP_IP_FEAT_JSON_OBJECTS BIT(6) + +/** + * @def SL_SI91X_TCP_IP_FEAT_HTTP_CLIENT + * @brief Enables the HTTP client feature. + * + * @details + * This feature allows the device to send HTTP requests and receive HTTP + * responses from web servers, enabling web-based communication. + */ +#define SL_SI91X_TCP_IP_FEAT_HTTP_CLIENT BIT(7) + +/** + * @def SL_SI91X_TCP_IP_FEAT_DNS_CLIENT + * @brief Enables the DNS client feature. + * + * @details + * This feature allows the device to resolve domain names to IP addresses + * using the Domain Name System (DNS), enabling communication with servers + * by hostname. + */ +#define SL_SI91X_TCP_IP_FEAT_DNS_CLIENT BIT(8) + +/** + * @def SL_SI91X_TCP_IP_FEAT_SNMP_AGENT + * @brief Enables the SNMP agent feature. + * + * @details + * This feature allows the device to act as an SNMP (Simple Network Management + * Protocol) agent, enabling network management and monitoring. + */ +#define SL_SI91X_TCP_IP_FEAT_SNMP_AGENT BIT(9) + +/** + * @def SL_SI91X_TCP_IP_FEAT_SSL + * @brief Enables the SSL feature. + * + * @details + * This feature allows the device to use SSL (Secure Sockets Layer) for secure + * communication over the network, providing encryption and authentication. + */ +#define SL_SI91X_TCP_IP_FEAT_SSL BIT(10) + +/** + * @def SL_SI91X_TCP_IP_FEAT_ICMP + * @brief Enables the ICMP feature (ping). + * + * @details + * This feature allows the device to use ICMP (Internet Control Message + * Protocol) for network diagnostics, such as sending ping requests. + */ +#define SL_SI91X_TCP_IP_FEAT_ICMP BIT(11) + +/// @note Bit 12 is reserved + +/// @note Bit 13 is reserved + +/** + * @def SL_SI91X_TCP_IP_FEAT_SEND_CONFIGS_TO_HOST + * @brief Enables sending configuration data to the host. + * + * @details + * This feature allows the device to send web page configuration data to the + * host system from the wireless configuration page. + */ +#define SL_SI91X_TCP_IP_FEAT_SEND_CONFIGS_TO_HOST BIT(14) + +/** + * @def SL_SI91X_TCP_IP_FEAT_FTP_CLIENT + * @brief Enables the FTP client feature. + * + * @details + * This feature allows the device to act as an FTP (File Transfer Protocol) + * client, enabling file transfers to and from FTP servers. + */ +#define SL_SI91X_TCP_IP_FEAT_FTP_CLIENT BIT(15) + +/** + * @def SL_SI91X_TCP_IP_FEAT_SNTP_CLIENT + * @brief Enables the SNTP client feature. + * + * @details + * This feature allows the device to synchronize its clock with an SNTP + * (Simple Network Time Protocol) server, ensuring accurate timekeeping. + */ +#define SL_SI91X_TCP_IP_FEAT_SNTP_CLIENT BIT(16) + +/** + * @def SL_SI91X_TCP_IP_FEAT_IPV6 + * @brief Enables IPv6 support. + * + * @details + * This feature allows the device to use IPv6 (Internet Protocol version 6), + * providing a larger address space and improved routing capabilities. + * + * @note IPv6 will also be enabled if the DHCPv6 client or DHCPv6 server + * feature is enabled, regardless of the tcp_ip_feature_bit_map[17] setting. + */ +#define SL_SI91X_TCP_IP_FEAT_IPV6 BIT(17) + +/** + * @def SL_SI91X_TCP_IP_FEAT_RAW_DATA + * @brief Enables raw data support. + * + * @details + * This feature allows the device to handle raw data frames, bypassing the + * TCP/IP stack. It is supported only in AP mode and requires the TCP_BYPASS + * feature to be disabled. If any packet from the host with frame type 0x1 + * is received by the firmware, the packet will be sent on air without + * TCP/IP stack processing. ARP and broadcast packets (other than DHCP + * packets) received on air will be sent to the host. + */ +#define SL_SI91X_TCP_IP_FEAT_RAW_DATA BIT(18) + +/** + * @def SL_SI91X_TCP_IP_FEAT_MDNSD + * @brief Enables the MDNSD feature. + * + * @details + * This feature allows the device to use Multicast DNS (mDNS) for local + * network service discovery, enabling devices to find each other without + * a central DNS server. + * + * @note This feature is not supported in AP mode. + */ +#define SL_SI91X_TCP_IP_FEAT_MDNSD BIT(19) + +/** + * @def SL_SI91X_TCP_IP_FEAT_SMTP_CLIENT + * @brief Enables the SMTP client feature. + * + * @details + * This feature allows the device to act as an SMTP (Simple Mail Transfer + * Protocol) client, enabling it to send emails. + */ +#define SL_SI91X_TCP_IP_FEAT_SMTP_CLIENT BIT(20) + +/** + * @def SL_SI91X_TCP_IP_TOTAL_SOCKETS + * @brief Selects the number of sockets. + * + * @details + * This macro allows the configuration of the total number of sockets + * available. A maximum of 10 sockets are allowed. Bits 21-24 are used + * to set the TOTAL_SOCKETS. + * @param total_sockets The total number of sockets to be configured. + */ +#define SL_SI91X_TCP_IP_TOTAL_SOCKETS(total_sockets) (total_sockets << 21) + +/** + * @def SL_SI91X_TCP_IP_FEAT_SINGLE_SSL_SOCKET + * @brief Enables a single SSL socket. + * + * @details + * This feature allows the device to use a single SSL socket for secure + * communication. + */ +#define SL_SI91X_TCP_IP_FEAT_SINGLE_SSL_SOCKET BIT(25) + +/** + * @def SL_SI91X_TCP_IP_FEAT_LOAD_PUBLIC_PRIVATE_CERTS + * @brief Enables loading of public and private keys for TLS/SSL handshake. + * + * @details + * This feature allows the device to load public and private keys for use + * in TLS/SSL handshakes. + * + * @note If a secure handshake is to be done using only + * a CA-certificate, then loading of private and public keys can be + * disabled, and these certificates can be erased from the flash using + * the load_cert API. If secure handshake verification of private and + * public keys is needed, then loading of these keys must be enabled. + */ +#define SL_SI91X_TCP_IP_FEAT_LOAD_PUBLIC_PRIVATE_CERTS BIT(26) + +/** + * @def SL_SI91X_TCP_IP_FEAT_LOAD_CERTS_INTO_RAM + * @brief Enables loading of SSL certificates into RAM. + * + * @details + * This feature allows the device to load SSL certificates into RAM for + * faster access during secure communications. + */ +#define SL_SI91X_TCP_IP_FEAT_LOAD_CERTS_INTO_RAM BIT(27) + +/// @note Bit 28 is reserved + +/** + * @def SL_SI91X_TCP_IP_FEAT_POP3_CLIENT + * @brief Enables the POP3 client feature. + * + * @details + * This feature allows the device to act as a POP3 (Post Office Protocol + * version 3) client, enabling it to retrieve emails from a POP3 server. + */ +#define SL_SI91X_TCP_IP_FEAT_POP3_CLIENT BIT(29) + +/** + * @def SL_SI91X_TCP_IP_FEAT_OTAF + * @brief Enables the OTAF client feature. + * + * @details + * This feature allows the device to perform over-the-air firmware (OTAF) + * updates, enabling it to download and install firmware updates remotely. + */ +#define SL_SI91X_TCP_IP_FEAT_OTAF BIT(30) + +/** + * @def SL_SI91X_TCP_IP_FEAT_EXTENSION_VALID + * @brief Enables TCP/IP extension support. + * + * @details + * This feature allows the device to use extended TCP/IP features, + * If this bit is enabled then only, the features present in the ext_tcp ip feature bitmap can be used. + */ +#define SL_SI91X_TCP_IP_FEAT_EXTENSION_VALID BIT(31) +/** @} */ + +/** \addtogroup SI91X_CUSTOM_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// Custom feature bit map parameters description !// +/*=========================================================================*/ +/** + * @def SL_SI91X_CUSTOM_FEAT_DISABLE_GATEWAY_IN_RSI_AP + * @brief Disables gateway configuration sent to STA from RSI AP. + * @details If this bit is set to 1, the DHCP server behavior changes when the device is in Access Point (AP) mode. + * The DHCP server will assign IP addresses to client nodes without sending out a Gateway address, providing only the assigned IP and Subnet values. + * It is highly recommended to keep this value at '0' for standard AP functionality, + * as disabling the gateway address is typically needed only for very specialized use cases. The default value of this bit is '0' + * + * @note Bits 0 - 1 are reserved. + */ +#define SL_SI91X_CUSTOM_FEAT_DISABLE_GATEWAY_IN_RSI_AP BIT(2) + +/** + * @def SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_160MHZ + * @brief Configures the clock for NWP SOC to 160 MHz. + * @details If higher performance, such as increased throughput, is required this configuration sets the System-on-Chip (SoC) clock to 160 MHz. + * + * @note Ensure to set `pll_mode` to 1 in the feature frame command for this configuration to take effect. + * @note Bit 3 is reserved. + */ +#define SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_160MHZ BIT(4) + +/** + * @def SL_SI91X_CUSTOM_FEAT_AP_IN_HIDDEN_MODE + * @brief Configures the Access Point (AP) to operate in hidden mode. + * @details If this bit is set, the AP is created in a hidden mode where its SSID is not broadcasted, making the AP less visible to clients. + * This feature is valid only when the device is in AP mode. + */ +#define SL_SI91X_CUSTOM_FEAT_AP_IN_HIDDEN_MODE BIT(5) + +/** + * @def SL_SI91X_CUSTOM_FEAT_DNS_SERVER_IN_DHCP_OFFER + * @brief Includes DNS server IP address in DHCP offer response when in AP mode. + * @details When this bit is set, the DHCP server running in AP mode will include the DNS server IP address in the DHCP offer response sent to clients. + */ +#define SL_SI91X_CUSTOM_FEAT_DNS_SERVER_IN_DHCP_OFFER BIT(6) + +/** + * @def SL_SI91X_CUSTOM_FEAT_DFS_CHANNEL_SUPPORT + * @brief Enables scanning of DFS channels in the 5 GHz band. + * @details This bit enables the support for scanning Dynamic Frequency Selection (DFS) channels in the 5 GHz band. + * It is valid only in Wi-Fi client mode. Ensure to set the region configuration before scanning DFS channels. + * + * @note Bit 7 is reserved. + * @note 5Gz is not supported in SI917. + */ +#define SL_SI91X_CUSTOM_FEAT_DFS_CHANNEL_SUPPORT BIT(8) + +/** + * @def SL_SI91X_CUSTOM_FEAT_LED_FEATURE + * @brief Enables LED blinking feature to indicate network activity. + * @details When this bit is set, the LED (GPIO_16) will blink to indicate network activity. + * The LED blinks when a TX packet is sent or when a unicast packet addressed to the device’s MAC is received. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_CUSTOM_FEAT_LED_FEATURE BIT(9) + +/** + * @def SL_SI91X_CUSTOM_FEAT_ASYNC_CONNECTION_STATUS + * @brief Enables asynchronous WLAN connection status indication to the host. + * @details If this bit is enabled, the module will asynchronously notify the host of WLAN connection status changes. + * This feature is valid only in Wi-Fi client mode. + */ +#define SL_SI91X_CUSTOM_FEAT_ASYNC_CONNECTION_STATUS BIT(10) + +/** + * @def SL_SI91X_CUSTOM_FEAT_WAKE_ON_WIRELESS + * @brief Enables wake-on-wireless functionality in UART mode. + * @details This bit enables the wake-on-wireless feature when operating in UART mode, allowing the module to wake up in response to wireless events. + * + * @note applicable only for NCP. + */ +#define SL_SI91X_CUSTOM_FEAT_WAKE_ON_WIRELESS BIT(11) + +/** + * @def SL_SI91X_CUSTOM_FEAT_ENABLE_AP_BLACKLIST + * @brief Enables AP blacklisting in Station (STA) mode. + * @details By default, the client maintains an AP blacklist to avoid specific access points. + * Enabling this feature allows the client to bypass the AP blacklist during roaming or rejoin, if needed. + */ +#define SL_SI91X_CUSTOM_FEAT_ENABLE_AP_BLACKLIST BIT(12) + +/** + * @def SL_SI91X_CUSTOM_FEAT_MAX_NUM_OF_CLIENTS + * @brief Sets the maximum number of clients supported in AP mode. + * @details This bit field sets the maximum number of clients that can be supported in Access Point (AP) mode. + * The value for this field should be provided in the range specified by bits 13 - 16. + * @param max_num_of_clients Number of clients to be supported (1 to 15). + */ +#define SL_SI91X_CUSTOM_FEAT_MAX_NUM_OF_CLIENTS(max_num_of_clients) (max_num_of_clients << 13) + +/** + * @def SL_SI91X_CUSTOM_FEAT_ROAM_WITH_DEAUTH_OR_NULL_DATA + * @brief Selects between de-authentication or null data (with power management bit set) for roaming. + * @details If this bit is enabled then roam through DEAUTH, or roam through NULL. + */ +#define SL_SI91X_CUSTOM_FEAT_ROAM_WITH_DEAUTH_OR_NULL_DATA BIT(17) + +/** + * @def SL_SI91X_CUSTOM_FEAT_TRIGGER_AUTO_CONFIG + * @brief Triggers automatic configuration. + * @details This bit enables the auto-configuration feature, which allows the module to automatically configure itself based on predefined parameters. + * + * @note Bits 18 - 19 are reserved. + * @note Not applicable for SI917. + */ +#define SL_SI91X_CUSTOM_FEAT_TRIGGER_AUTO_CONFIG BIT(20) + +/** + * @def SL_SI91X_CUSTOM_FEAT_LIMIT_PACKETS_PER_STA + * @brief Limits the number of packets buffered per STA in AP mode. + * @details In Access Point (AP) mode, if this bit is set, only two packets per Station (STA) will be buffered when the STA is in Power Save (PS) mode. + * This helps manage buffer usage and ensures efficient packet handling. + * + * @note Bit 21 is reserved. + */ +#define SL_SI91X_CUSTOM_FEAT_LIMIT_PACKETS_PER_STA BIT(22) + +/** + * @def SL_SI91X_CUSTOM_FEAT_HTTP_HTTPS_AUTH + * @brief Enables HTTP/HTTPS authentication. + * @details This bit enables authentication for HTTP and HTTPS connections, adding an extra layer of security for web-based communications. + */ +#define SL_SI91X_CUSTOM_FEAT_HTTP_HTTPS_AUTH BIT(23) + +/** + * @def SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_120MHZ + * @brief Configures the clock for NWP SOC to 120 MHz. + * @details This configuration sets the System-on-Chip (SoC) clock to 120 MHz. This may be required for certain performance needs. + * Ensure to set `pll_mode` to 1 in the feature frame command for this configuration to take effect. + * + * @note This configuration is necessary for high throughput scenarios. + */ +#define SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_120MHZ BIT(24) + +/** + * @def SL_SI91X_CUSTOM_FEAT_REJECT_CONNECT_REQ_IMMEDIATELY + * @brief Rejects new LTCP connection requests immediately when maximum clients are connected. + * @details When this bit is set, any new connection request for an LTCP socket will be rejected immediately if the maximum number of clients is already connected. + * By default, such requests are maintained in a pending list until an existing client disconnects. + * + * @note When BIT[26] = 0: New connection requests are held in a pending list. When BIT[26] = 1: New connection requests are immediately rejected. + */ +#define SL_SI91X_CUSTOM_FEAT_REJECT_CONNECT_REQ_IMMEDIATELY BIT(26) + +/** + * @def SL_SI91X_CUSTOM_FEAT_DUAL_BAND_ROAM_VCSAFD + * @brief Enables dual-band roaming and VCSAFD feature (currently not supported). + * @details This bit enables support for dual-band roaming and VCSAFD (Virtual Channel Scan and Frequency Avoidance Detection), + * which enhances the module’s ability to switch between different frequency bands and avoid interference. + */ +#define SL_SI91X_CUSTOM_FEAT_DUAL_BAND_ROAM_VCSAFD BIT(27) + +/** + * @def SL_SI91X_CUSTOM_FEAT_RTC_FROM_HOST + * @brief Enables Real-Time Clock (RTC) synchronization from the host. + * @details When this bit is set, the module will use the Real-Time Clock (RTC) provided by the host system for timekeeping. + * + * @note + * Ensure that the Real-Time Clock (RTC) timer is configured to enable certificate validation. + */ +#define SL_SI91X_CUSTOM_FEAT_RTC_FROM_HOST BIT(28) + +/** + * @def SL_SI91X_CUSTOM_FEAT_BT_IAP + * @brief Enables Bluetooth In-App Programming (IAP) feature. + * @details This bit enables the Bluetooth In-App Programming (IAP) feature, allowing the module to support Bluetooth-related in-app programming functionalities. + */ +#define SL_SI91X_CUSTOM_FEAT_BT_IAP BIT(29) + +/** + * @def SL_SI91X_CUSTOM_FEAT_EXTENTION_VALID + * @brief Validates the use of extended custom feature bitmap. + * @details This bit indicates that the extended custom feature bitmap is valid. + * If this bit is enabled then only, the features present in the extended custom feature bitmap can be used. + */ +#define SL_SI91X_CUSTOM_FEAT_EXTENSION_VALID BIT(31) +/** @} */ + +/** \addtogroup SI91X_EXTENDED_CUSTOM_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ + +// Extended custom feature bitmap !// +/*=========================================================================*/ + +/** + * @def SL_SI91X_EXT_FEAT_RSA_KEY_WITH_4096_SUPPORT + * @brief Supports 4096 size RSA KEY certificate. + * @details Enabling this bit allows the device to support 4096-bit RSA keys. Recommended only if 4096-bit keys are required. + * + * @note Bit 0 is reserved. + */ +#define SL_SI91X_EXT_FEAT_RSA_KEY_WITH_4096_SUPPORT BIT(1) + +/** + * @def SL_SI91X_EXT_FEAT_SSL_CERT_WITH_4096_KEY_SUPPORT + * @brief Supports 4096 size KEY SSL certificate. + * @details Enabling this bit allows the device to support SSL certificates with 4096-bit keys. Recommended only if 4096-bit keys are required. + * + * @note Bit 2 is reserved. + */ +#define SL_SI91X_EXT_FEAT_SSL_CERT_WITH_4096_KEY_SUPPORT BIT(3) + +/** + * @def SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_B4_DTIM + * @brief Extended custom bitmap for AP Broadcast customization. + * @details Enabling this bit configures the Access Point to send broadcast packets before the DTIM (Delivery Traffic Indication Message) interval. + * + * @note If this bit is enabled, connected clients in power save mode may miss the packet. + */ +#define SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_B4_DTIM BIT(4) + +/** + * @def SL_SI91X_EXT_FEAT_FCC_LOW_PWR + * @brief Extended custom bitmap to support FCC (currently not supported). + * @details Enabling this bit allows the device to operate in a mode that complies with FCC (Federal Communications Commission) regulations for low power operation. + */ +#define SL_SI91X_EXT_FEAT_FCC_LOW_PWR BIT(5) + +/** + * @def SL_SI91X_EXT_FEAT_PUF + * @brief To enable PUF (Physical Unclonable Function). + * @details Enabling this bit activates the Physical Unclonable Function feature, which provides a unique identifier for each device based on its physical characteristics. + * + * @note Bit 6 is reserved. + * @note Currently this feature is not supported for SI917. + */ +#define SL_SI91X_EXT_FEAT_PUF BIT(7) + +/** + * @def SL_SI91X_EXT_FEAT_SPECTRAL_MASK_NOKIA + * @brief Nokia Spectral mask extended custom bitmap (currently not supported). + * @details Enabling this bit allows the device to support the Nokia Spectral mask for extended custom bitmap configurations. + */ +#define SL_SI91X_EXT_FEAT_SPECTRAL_MASK_NOKIA BIT(8) + +/** + * @def SL_SI91X_EXT_HTTP_SKIP_DEFAULT_LEADING_CHARACTER + * @brief Extended feature bitmap to skip default leading character '\' in HTTP header. + * @details Enabling this bit configures the device to omit the default leading character '\' in HTTP headers, allowing for custom header formatting. + */ +#define SL_SI91X_EXT_HTTP_SKIP_DEFAULT_LEADING_CHARACTER BIT(9) + +/** + * @def SL_SI91X_EXT_FEAT_PUF_PRIVATE_KEY + * @brief To enable PUF (Physical Unclonable Function) private key. + * @details Enabling this bit activates the use of a private key associated with the Physical Unclonable Function feature for enhanced security. + * + * @note Currently this feature is not supported for SI917. + */ +#define SL_SI91X_EXT_FEAT_PUF_PRIVATE_KEY BIT(10) + +/** + * @def SL_SI91X_EXT_FEAT_ENABLE_11R_OTA + * @brief To enable 802.11R Over The Air Roaming (currently not supported). + * @details Enabling this bit activates support for 802.11R (Fast BSS Transition) Over The Air Roaming, which improves the handoff experience between access points. + * + * @note Resource Request Support is not present. + * @note If both BIT[11] and BIT[16] are not enabled, the device will default to Legacy Roaming. + */ +#define SL_SI91X_EXT_FEAT_ENABLE_11R_OTA BIT(11) + +/** + * @def SL_SI91X_EXT_FEAT_IEEE_80211J + * @brief To enable 802.11J protocol (currently not supported). + * @details Enabling this bit activates support for the 802.11J protocol, which is used for wireless communication in Japan. + * + * @note If this bit is enabled, the set region command is mandatory with the region set to Japan and the band value must be 1. + */ +#define SL_SI91X_EXT_FEAT_IEEE_80211J BIT(12) + +/** + * @def SL_SI91X_EXT_FEAT_IEEE_80211W + * @brief To enable 802.11W protocol. + * @details Enabling this bit activates support for the 802.11W protocol, which provides management frame protection. + * + * @note This bit must be set to enable WPA3 Personal Mode and WPA3 Personal Transition mode. + */ +#define SL_SI91X_EXT_FEAT_IEEE_80211W BIT(13) + +/** + * @def SL_SI91X_EXT_FEAT_SSL_VERSIONS_SUPPORT + * @brief To enable the Multi-version TCP over SSL support. + * @details Enabling this bit allows the device to support multiple versions of SSL/TLS over TCP, providing flexibility in handling different SSL/TLS versions. + */ +#define SL_SI91X_EXT_FEAT_SSL_VERSIONS_SUPPORT BIT(14) + +/** + * @def SL_SI91X_EXT_FEAT_16th_STATION_IN_AP_MODE + * @brief To enable 16 client support in Access Point (AP) mode. + * @details Enabling this bit allows up to 16 stations to connect to the device when it is operating in AP mode. + * + * @note If this bit is enabled, up to 16 stations can connect; otherwise, a maximum of 8 stations can connect. + */ +#define SL_SI91X_EXT_FEAT_16th_STATION_IN_AP_MODE BIT(15) + +/** + * @def SL_SI91X_EXT_FEAT_ENABLE_11R_ODS + * @brief To enable 802.11R Over the Distribution System Roaming. + * @details Enabling this bit activates support for 802.11R (Fast BSS Transition) Over the Distribution System Roaming, which enhances roaming performance across different access points in the distribution system. + * + * @note 1. Resource Request Support is not present. + * @note 2. If both BIT[11] and BIT[16] are not enabled, the device will default to Legacy Roaming. + */ +#define SL_SI91X_EXT_FEAT_ENABLE_11R_ODS BIT(16) + +/** + * @def SL_SI91X_EXT_FEAT_WOWLAN_DISABLE + * @brief To disable the WoWLAN (Wake-on-Wireless-LAN) feature. + * @details Enabling this bit disables the WoWLAN feature, which is used for waking the device from a low-power state through wireless network activity. + * By default WOW LAN Is enabled to maintain backward compatibility. So given option to disable this feature. + * + * @note This only valid in NCP mode. + */ +#define SL_SI91X_EXT_FEAT_WOWLAN_DISABLE BIT(17) + +/** + * @def SL_SI91X_EXT_FEAT_DISABLE_XTAL_CORRECTION + * @brief To disable auto correction of XTAL (40MHz crystal) + * @details Enabling this bit will disable the automatic compensation for frequency offsets, ensuring error-free calibration. + * + * @note This bit should be enabled in the following cases: + * @note 1. Always enable it in the Calibration application. + * @note 2. Enable it for all applications for the customer hardware with an XTAL part number other than 8Y40070013. + */ +#define SL_SI91X_EXT_FEAT_DISABLE_XTAL_CORRECTION BIT(18) + +/** + * @def SL_SI91X_EXT_FEAT_LOW_POWER_MODE + * @brief To enable low power mode in WLAN. + * @details Enabling this bit activates low power mode for WLAN, Active current will also be reduced. + * As most of the code which is needed to maintain connection is kept in RAM. + * There will be minimal execution of code from Flash which in turn results in low average current. + */ +#define SL_SI91X_EXT_FEAT_LOW_POWER_MODE BIT(19) + +#if defined(SLI_SI917) || defined(DOXYGEN) || defined(SLI_SI915) + +// For SoC +#if defined(SLI_SI91X_MCU_INTERFACE) || defined(DOXYGEN) +/** + * @def SL_SI91X_EXT_FEAT_352K_M4SS_320K + * @brief To enable 352K memory for NWP and 320K memory for M4. + * @details This configuration allocates 352K memory to the Network Processor (NWP) and 320K memory to the M4 core. + */ +#define SL_SI91X_EXT_FEAT_352K_M4SS_320K 0 + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV + * @brief To enable basic NWP and advanced MCU RAM level configuration. + * @details This setting configures the NWP with a basic memory level while providing the MCU with an advanced memory configuration. + * + * @note This configuration uses SL_SI91X_EXT_FEAT_352K_M4SS_320K. + */ +#define SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV SL_SI91X_EXT_FEAT_352K_M4SS_320K + +/** + * @def SL_SI91X_EXT_FEAT_416K_M4SS_256K + * @brief To enable 416K memory for NWP and 256K memory for M4. + * @details This configuration allocates 416K memory to the Network Processor (NWP) and 256K memory to the M4 core. + */ +#define SL_SI91X_EXT_FEAT_416K_M4SS_256K BIT(21) + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM + * @brief To enable medium NWP and medium MCU RAM level configuration. + * @details This setting configures both the NWP and the MCU with medium memory levels. + * + * @note This configuration uses SL_SI91X_EXT_FEAT_416K_M4SS_256K. + */ +#define SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM SL_SI91X_EXT_FEAT_416K_M4SS_256K + +/** + * @def SL_SI91X_EXT_FEAT_480K_M4SS_192K + * @brief To enable 480K memory for NWP and 192K memory for M4. + * @details This configuration allocates 480K memory to the Network Processor (NWP) and 192K memory to the M4 core. + */ +#define SL_SI91X_EXT_FEAT_480K_M4SS_192K BIT(20) + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC + * @brief To enable advanced NWP and basic MCU RAM level configuration. + * @details This setting configures the NWP with an advanced memory level while providing the MCU with a basic memory configuration. + * + * @note This configuration uses SL_SI91X_EXT_FEAT_480K_M4SS_192K. + */ +#define SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC SL_SI91X_EXT_FEAT_480K_M4SS_192K +#endif + +// For NCP +#if (!defined(SLI_SI91X_MCU_INTERFACE)) || defined(DOXYGEN) +/** + * @def SL_SI91X_EXT_FEAT_352K + * @brief To enable 352K memory for NWP. + */ +#define SL_SI91X_EXT_FEAT_352K 0 + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_BASIC + * @brief To enable basic NWP RAM level configuration. + * @details This setting configures the Network Processor (NWP) with 352K of memory. + */ +#define SL_SI91X_RAM_LEVEL_NWP_BASIC SL_SI91X_EXT_FEAT_352K + +/** + * @def SL_SI91X_EXT_FEAT_672K + * @brief To enable 672K memory for NWP. + */ +#define SL_SI91X_EXT_FEAT_672K (BIT(20) | BIT(21)) + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE + * @brief To enable full NWP RAM level configuration. + * @details This setting configures the Network Processor (NWP) with 672K of memory. + */ +#define SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE SL_SI91X_EXT_FEAT_672K + +/** + * @def SL_SI91X_EXT_FEAT_352K_M4SS_320K + * @brief To enable 352K memory for NWP (For NCP mode ONLY, to be deprecated soon). + * @details This setting is soon to be deprecated and should only be used for NCP mode. + * + * @note For NCP mode ONLY, to be deprecated soon. + */ +#define SL_SI91X_EXT_FEAT_352K_M4SS_320K SL_SI91X_EXT_FEAT_352K + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV + * @brief To enable basic NWP RAM level configuration (For NCP mode ONLY, to be deprecated soon). + * @details This setting configures the Network Processor (NWP) with 352K of memory in NCP mode. + * + * @note For NCP mode ONLY, to be deprecated soon. + */ +#define SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV SL_SI91X_EXT_FEAT_352K + +/** + * @def SL_SI91X_EXT_FEAT_672K_M4SS_0K + * @brief To enable 672K memory for NWP and 0K memory for M4 (For NCP mode ONLY, to be deprecated soon). + * @details This setting configures the Network Processor (NWP) with 672K of memory and allocates no memory to the M4 core in NCP mode. + * + * @note For NCP mode ONLY, to be deprecated soon. + */ +#define SL_SI91X_EXT_FEAT_672K_M4SS_0K SL_SI91X_EXT_FEAT_672K + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO + * @brief To enable full NWP RAM level configuration (For NCP mode ONLY, to be deprecated soon). + * @details This setting configures the Network Processor (NWP) with 672K of memory and allocates no memory to the M4 core in NCP mode. + * + * @note For NCP mode ONLY, to be deprecated soon. + */ +#define SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO SL_SI91X_EXT_FEAT_672K + +#endif + +#elif defined(SLI_SI917) || defined(SLI_SI915) + +#define SL_SI91X_EXT_FEAT_384K_M4SS_320K 0 +#define SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV SL_SI91X_EXT_FEAT_384K_M4SS_320K + +/// To enable 448K memory for NWP +/// To enable 448K memory for NWP +#define SL_SI91X_EXT_FEAT_448K_M4SS_256K BIT(21) +#define SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM SL_SI91X_EXT_FEAT_448K_M4SS_256K + +/// To enable 512K memory for NWP +#define SL_SI91X_EXT_FEAT_512K_M4SS_192K BIT(20) +#define SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC SL_SI91X_EXT_FEAT_512K_M4SS_192K + +#ifndef SLI_SI91X_MCU_INTERFACE +// To enable 704K memory for NWP; only supported in NCP +#define SL_SI91X_EXT_FEAT_704K_M4SS_0K (BIT(20) | BIT(21)) +#define SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO SL_SI91X_EXT_FEAT_704K_M4SS_0K +#define SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO +#endif + +#endif // SLI_SI917 + +/// For 9116 chipsets +#if !(defined(SLI_SI917) || defined(SLI_SI915)) // defaults + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM + * @brief RAM level configuration: Medium NWP and Medium MCU memory. + * @details This macro sets the RAM level to Medium for both NWP (Network Processor) and MCU (Microcontroller) memory. + */ +#define SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM SL_SI91X_EXT_FEAT_256K_MODE + +/** + * @def SL_SI91X_EXT_FEAT_320K_MODE + * @brief To enable 320K memory for NWP. + * @details Enabling this bit sets the memory configuration to 320KB for the NWP. + */ +#define SL_SI91X_EXT_FEAT_320K_MODE BIT(20) + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC + * @brief RAM level configuration: Advanced NWP and Basic MCU memory. + * @details This macro sets the RAM level to Advanced for NWP (Network Processor) and Basic for MCU (Microcontroller) memory, equivalent to enabling 320KB memory. + */ +#define SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC SL_SI91X_EXT_FEAT_320K_MODE + +/** + * @def SL_SI91X_EXT_FEAT_256K_MODE + * @brief To enable 256K memory for NWP. + * @details Enabling this bit sets the memory configuration to 256KB for the NWP. The default memory configuration is 192KB. The memory configuration can be changed as follows: + * + * | Mode(KB) | BIT[20] | BIT[21] | + * |:---------|:--------|:--------| + * | 192 | 0 | 0 | + * | 256 | 0 | 1 | + * | 320 | 1 | 0 | + * | 384 | 1 | 1 | + * + * @note Default memory configuration (RAM) is 192KB. User can set these bits to change the memory configuration as described. + */ +#define SL_SI91X_EXT_FEAT_256K_MODE BIT(21) + +/** + * @def SL_SI91X_EXT_FEAT_384K_MODE + * @brief To enable 384K memory. + * @details Enabling this bit sets the memory configuration to 384KB. This configuration is achieved by setting both BIT(20) and BIT(21). + */ +#define SL_SI91X_EXT_FEAT_384K_MODE (BIT(20) | BIT(21)) + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO + * @brief RAM level configuration: All NWP and Zero MCU memory. + * @details This macro sets the RAM level to 384KB for NWP (Network Processor) memory with zero configuration for MCU (Microcontroller) memory, equivalent to enabling 384KB memory. + */ +#define SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO SL_SI91X_EXT_FEAT_384K_MODE + +/** + * @def SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE + * @brief RAM level configuration: All available NWP memory. + * @details This macro sets the RAM level to the maximum available memory configuration for NWP (Network Processor), which is equivalent to the configuration set by `SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO`. + */ +#define SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO + +#endif // defaults + +/** + * @def SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE + * @brief To enable crystal clock for NWP. + * @details This macro configures the sleep clock source selection for the NWP. The options are as follows: + * + * | Selection | BIT[23] | BIT[22] | + * |:----------------------------------------------|:--------|:--------| + * | Use RC clock as sleep clock | 0 | 0 | + * | Use 32KHz clock from external XTAL OSCILLATOR | 0 | 1 | + * | Use 32KHz bypass clock on UULP_GPIO_3 | 1 | 0 | + * | Use 32KHz bypass clock on UULP_GPIO_4 | 1 | 1 | + * + * @note For 917 radio boards, set `SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE` to 1. For other variants, a value of 2 is recommended. + */ + +#ifdef SI91X_32kHz_EXTERNAL_OSCILLATOR +#define SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE(xtal_clk_enable) (xtal_clk_enable << 23) +#else +#define SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE(xtal_clk_enable) (xtal_clk_enable << 22) +#endif + +// Determine the XTAL clock enable value +#if defined(SLI_SI917) || defined(SLI_SI915) && defined(SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2) +/// To enable crystal clock for NWP +#define SL_SI91X_EXT_FEAT_XTAL_CLK SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE(1) +#else +/** + * @def SL_SI91X_EXT_FEAT_XTAL_CLK + * @brief Define to enable 32KHz crystal clock using the external XTAL OSCILLATOR. + * @details This macro sets the `SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE` with a value of 2, which configures the sleep clock source to use the 32KHz clock from the external XTAL OSCILLATOR. + */ +#define SL_SI91X_EXT_FEAT_XTAL_CLK SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE(2) +#endif + +/** + * @def SL_SI91X_EXT_FEAT_HOMEKIT_WAC_ENABLED + * @brief To inform firmware not to modify mDNS text records. + * @details Enabling this bit indicates that the firmware should not alter mDNS (Multicast DNS) text records. + */ +#define SL_SI91X_EXT_FEAT_HOMEKIT_WAC_ENABLED BIT(24) + +/** + * @def SL_SI91X_EXT_FEAT_1P8V_SUPPORT + * @brief To enable 1.8V support for NWP. + * @details Enabling this bit activates support for 1.8V operation. + */ +#define SL_SI91X_EXT_FEAT_1P8V_SUPPORT BIT(25) + +/** + * @def SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS + * @brief To select UART for debug prints pin selection. + * @details If BIT(27) is enabled, debug prints are supported on UART1. If BIT(27) is disabled, debug prints are supported on UART2. + * + * @note Bit 26 is reserved. + * @note By default, all debug prints from the device network processor will be sent to UART2 if this bit is not enabled. UART1 pins are mapped as follows: + * - UART1-TX: GPIO_9 + * - UART1-RX: GPIO_8 + * - UART2-TX: GPIO_6 + * - UART2-RX: GPIO_10 + * + * Ensure these pins are not used in MCU applications in SoC mode to avoid pin usage conflicts. This bit is valid only if BIT[28] in the ext_custom_feature_bit_map is set to 0. There is no functionality on RX pins for debug prints. + */ +#define SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS BIT(27) + +/** + * @def SL_SI91X_EXT_FEAT_DISABLE_DEBUG_PRINTS + * @brief To disable debug prints support in NWP (Network Processor). + * @details By default the prints will be coming on UART2. If this bit is enabled, disable debug prints. + * To enable prints on UART 1 @ref SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS bit needs to set. + */ +#define SL_SI91X_EXT_FEAT_DISABLE_DEBUG_PRINTS BIT(28) + +#if defined(SLI_SI917) || defined(DOXYGEN) || defined(SLI_SI915) +/** + * @def SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0 + * @brief To configure frontend with selection BIT[30:29] for 917B0. + * @details This bit configures the frontend switch pins based on the following table: + * + * | Bit[30] | BIT[29] | ANT_SEL_1 (VC3) | ANT_SEL_2 (VC2) | ANT_SEL_3 (VC1) | + * |:--------|:--------|:-----------------|:-----------------|:-----------------| + * | 0 | 0 | Reserved | Reserved | Reserved | + * | 0 | 1 | ULP_GPIO 4 | ULP_GPIO 5 | ULP_GPIO 0 | + * | 1 | 0 | Internal Switch | Internal Switch | Internal Switch | + * | 1 | 1 | Reserved | Reserved | Reserved | + * + * @note SiWx917 has an integrated on-chip transmit/receive (T/R) switch. This internal RF switch configuration uses internal logic present in the IC, and GPIOs are not needed. RF_BLE_TX (8dBm) mode is not supported in this configuration. + * @note VC1, VC2, and VC3 are control voltage pins of the RF switch. + */ +#define SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0 BIT(29) + +/** + * @def SL_SI91X_EXT_FEAT_FRONT_END_INTERNAL_SWITCH + * @brief To enable the internal front-end switch configuration. + * @details Enabling this bit selects the internal front-end switch configuration for the frontend. This configuration uses internal logic present in the IC, eliminating the need for external GPIOs. + */ +#define SL_SI91X_EXT_FEAT_FRONT_END_INTERNAL_SWITCH BIT(30) + +#else +/** + * @brief For 917A0 + * + * | Bit[30] | BIT[29] | ANT_SEL_1(VC3) | ANT_SEL_2(VC2) | ANT_SEL_3(VC1) | + * |:--------|:--------|:---------------|:---------------|:---------------| + * | 0 | 0 | GPIO 46 | GPIO 47 | GPIO 48 | + * | 0 | 1 | Reserved | Reserved | Reserved | + * | 1 | 0 | UILP_GPIO 4 | ULP_GPIO 5 | ULP_GPIO 0 | + * | 1 | 1 | UILP_GPIO 4 | ULP_GPIO 5 | ULP_GPIO 7 | + */ +#define SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_GPIO_46_47_48 0 +#define SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0 BIT(30) +#define SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_7 (BIT(30) | BIT(29)) +#endif + +/** + * @def SL_SI91X_EXT_FEAT_BT_CUSTOM_FEAT_ENABLE + * @brief To enable Bluetooth custom features. + * @details Enabling this bit activates Bluetooth custom features. + * If this bit is enabled then only, the features present in the Bluetooth custom feature can be used. + */ +#define SL_SI91X_EXT_FEAT_BT_CUSTOM_FEAT_ENABLE BIT(31) +/** @} */ + +/** \addtogroup SI91X_EXTENDED_TCP_IP_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// Extended TCP/IP feature bit map parameters description !// +/*=========================================================================*/ +/** + * @def SL_SI91X_EXT_TCP_FEAT_DHCP_OPT77 + * @brief DHCP USER CLASS. + * @details + * This feature enables DHCP Option 77, which allows the device to specify user class information in DHCP requests. + * + * @note Bit 0 is reserved. + */ +#define SL_SI91X_EXT_TCP_FEAT_DHCP_OPT77 BIT(1) + +/** + * @def SL_SI91X_EXT_TCP_IP_BI_DIR_ACK_UPDATE + * @brief TCP bi-directional acknowledgment update. + * @details + * This feature enables bi-directional data transfer by updating TCP acknowledgment handling. + * + * @note Need to enable this bit if user wants to run the bi-directional data transfer. + * @note Bit 2 is reserved. + */ +#define SL_SI91X_EXT_TCP_IP_BI_DIR_ACK_UPDATE BIT(3) + +/** + * @def SL_SI91X_EXT_TCP_IP_WINDOW_DIV + * @brief TCP RX window division. + * @details + * This feature allows the division of the TCP receive window, enabling + * more granular control over the window size. + */ +#define SL_SI91X_EXT_TCP_IP_WINDOW_DIV BIT(4) + +/** + * @def SL_SI91X_EXT_TCP_IP_CERT_BYPASS + * @brief SSL server certificate bypass. + * @details + * This feature allows the device to bypass SSL server certificate + * validation, with validation being performed by the host instead. + */ +#define SL_SI91X_EXT_TCP_IP_CERT_BYPASS BIT(5) + +/** + * @def SL_SI91X_EXT_TCP_IP_SSL_16K_RECORD + * @brief SSL 16K record size support. + * @details + * This feature enables support for 16K SSL record sizes, improving + * performance for SSL connections that use larger record sizes. + */ +#define SL_SI91X_EXT_TCP_IP_SSL_16K_RECORD BIT(6) + +/** + * @def SL_SI91X_EXT_TCP_IP_DNS_CLIENT_BYPASS + * @brief Enable DNS client bypass. + * @details + * This feature allows the device to bypass the internal DNS client, + * using the host for DNS resolution instead. + */ +#define SL_SI91X_EXT_TCP_IP_DNS_CLIENT_BYPASS BIT(7) + +/** + * @def SL_SI91X_EXT_TCP_IP_WINDOW_SCALING + * @brief Enable TCP window scaling feature. + * @details + * This feature enables TCP window scaling, allowing the device to use + * receive window sizes larger than 64 KB. + * + * @note If this feature is not enabled, then the maximum possible RX window size is 64 KB. + * If user wants to use more than 64KB window size, tcp_rx_window_size_cap in socket configuration is used to increase the window size. + */ +#define SL_SI91X_EXT_TCP_IP_WINDOW_SCALING BIT(8) + +/** + * @def SL_SI91X_EXT_TCP_IP_DUAL_MODE_ENABLE + * @brief Enable both TCP/IP bypass mode and embedded modes. + * @details + * This feature allows the device to use both bypass and non-bypass modes + * simultaneously, providing flexibility in network communication. + * + * @note Enabling this feature allows to use both bypass and non-bypass modes simultaneously. + */ +#define SL_SI91X_EXT_TCP_IP_DUAL_MODE_ENABLE BIT(9) + +/** + * @def SL_SI91X_EXT_TCP_IP_ETH_WIFI_BRIDGE + * @brief Enable Ethernet to WiFi bridge. + * @details + * This feature enables the device to act as a bridge between Ethernet and + * WiFi networks, facilitating communication between the two. + */ +#define SL_SI91X_EXT_TCP_IP_ETH_WIFI_BRIDGE BIT(10) + +/** + * @def SL_SI91X_EXT_DYNAMIC_COEX_MEMORY + * @brief Enable dynamic coexistence memory. + * @details + * This feature dynamically adjusts the TCP receive window size based on + * coexistence requirements, improving network performance in coexistence + * scenarios. + * + * @note To enable or disable the coexistence and update TCP RX window accordingly. + */ +#define SL_SI91X_EXT_DYNAMIC_COEX_MEMORY BIT(11) + +/** + * @def SL_SI91X_EXT_TCP_IP_TOTAL_SELECTS + * @brief Configure the number of selects. + * @details + * This feature configures the number of select operations the device can + * handle, with a maximum value of 10. + * + * @note Bits 12 - 15 are used for TOTAL_SELECTS. + */ +#define SL_SI91X_EXT_TCP_IP_TOTAL_SELECTS(total_selects) (total_selects << 12) + +/** + * @def SL_SI91X_EXT_TCP_IP_WAIT_FOR_SOCKET_CLOSE + * @brief Enable socket wait close. + * @details + * This feature ensures that a socket is not closed until close() is called + * from the host, which is recommended for use with TCP sockets. + * + * @note If it is set socket will not be closed until close() is called from host. It is recommended to enable this bit when using TCP sockets. + * @note This is always set internally for Si91x chips. + */ +#define SL_SI91X_EXT_TCP_IP_WAIT_FOR_SOCKET_CLOSE BIT(16) + +/** + * @def SL_SI91X_EXT_EMB_MQTT_ENABLE + * @brief Enable embedded/internal MQTT. + * @details + * This feature enables support for embedded MQTT (Message Queuing + * Telemetry Transport) functionality, allowing the device to use MQTT + * without external libraries. + * + * @note If user wants to use AT command for MQTT, enable this bit in the Opermode Command. + */ +#define SL_SI91X_EXT_EMB_MQTT_ENABLE BIT(17) + +/** + * @def SL_SI91X_EXT_FEAT_HTTP_OTAF_SUPPORT + * @brief Enable HTTP OTAF support. + * @details + * This feature enables support for HTTP-based over-the-air firmware (OTAF) + * updates, allowing the device to download and install firmware updates + * via HTTP. + * + * @note To do firmware upgrade with HTTP this bit should be enabled. + */ +#define SL_SI91X_EXT_FEAT_HTTP_OTAF_SUPPORT BIT(18) + +/** + * @def SL_SI91X_EXT_TCP_DYNAMIC_WINDOW_UPDATE_FROM_HOST + * @brief Enable to update TCP window from host. + * @details + * This feature allows the TCP window size to be dynamically updated from + * the host, providing more control over TCP flow management. + */ +#define SL_SI91X_EXT_TCP_DYNAMIC_WINDOW_UPDATE_FROM_HOST BIT(19) + +/** + * @def SL_SI91X_EXT_TCP_MAX_RECV_LENGTH + * @brief Enable to update max receive length for TCP. + * @details + * This feature allows the maximum receive length for TCP connections to be + * updated, accommodating different application requirements. + */ +#define SL_SI91X_EXT_TCP_MAX_RECV_LENGTH BIT(20) + +/** + * @def SL_SI91X_EXT_TCP_IP_FEAT_SSL_THREE_SOCKETS + * @brief Enable three SSL/TLS sockets. + * @details + * This feature allows the device to support up to three simultaneous + * SSL/TLS connections. + * + * @note Set tcp_ip_feature_bit_map[31] and ext_tcp_ip_feature_bit_map[29] to open 3 TLS sockets. + * @note Bits 21-28 are reserved. + */ +#define SL_SI91X_EXT_TCP_IP_FEAT_SSL_THREE_SOCKETS BIT(29) + +/** + * @def SL_SI91X_EXT_TCP_IP_FEAT_SSL_MEMORY_CLOUD + * @brief Configure additional memory for SSL/TLS connections to cloud servers. + * @details + * This feature allocates additional memory for SSL/TLS connections, + * typically required for connections to cloud servers, to avoid 0xD2 error. + * + * @note If user connects to a cloud server using two SSL/TLS connections then it is required to set this bit to avoid 0xD2 error. + */ +#define SL_SI91X_EXT_TCP_IP_FEAT_SSL_MEMORY_CLOUD BIT(30) + +/** + * @def SL_SI91X_CONFIG_FEAT_EXTENTION_VALID + * @brief Config feature bit map validity. + * @details + * This feature validates the configuration feature bit map. + * If this bit is enabled then only, the features present in the configuration feature bitmap can be used. + */ +#define SL_SI91X_CONFIG_FEAT_EXTENSION_VALID BIT(31) +/** @} */ + +/** \addtogroup SI91X_BT_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// BT feature bit map parameters description !// +/*=========================================================================*/ +/** + * @def SL_SI91X_BT_RF_TYPE + * @brief Macro to specify the BT RF type for the SI91X wireless device. + * + * This macro is used to specify the BT RF type for the SI91X wireless device. + * It is defined as BIT(30). + * 0 - RF_TYPE_EXTERNAL + * 1 - RF_TYPE_INTERNAL + */ +#define SL_SI91X_BT_RF_TYPE BIT(30) +/** + * @def SL_SI91X_ENABLE_BLE_PROTOCOL + * @brief Macro to enable the BLE protocol. + * + * This macro is used to enable the BLE (Bluetooth Low Energy) protocol. + * The BLE protocol can be enabled by setting the bit 31 of the corresponding register. + * + */ +#define SL_SI91X_ENABLE_BLE_PROTOCOL BIT(31) +/** @} */ + +/** \addtogroup SI91X_BLE_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// BLE feature bit map +/*=========================================================================*/ +/** + * @def SL_SI91X_BLE_MAX_NBR_ATT_REC + * @brief BLE number of attributes. + * @details + * Sets the maximum number of BLE attributes. + + * @note Maximum number of BLE attributes is 124. + * @note Bits 0 - 7 are used to set MAX_NBR_ATT_REC. + */ +#define SL_SI91X_BLE_MAX_NBR_ATT_REC(max_num_of_att_rec) (max_num_of_att_rec << 0) +/** + * @def SL_SI91X_BLE_MAX_NBR_ATT_SERV + * @brief BLE number of GATT services. + * @details + * Sets the maximum number of BLE GATT services. + + * @note Maximum number of services is 10. + * @note Bits 8 - 11 are used to set MAX_NBR_ATT_SERV. + */ +#define SL_SI91X_BLE_MAX_NBR_ATT_SERV(max_num_of_att_serv) (max_num_of_att_serv << 8) +/** + * @def SL_SI91X_BLE_MAX_NBR_PERIPHERALS + * @brief BLE number of peripherals. + * @details + * Sets the maximum number of BLE peripherals. + + * @note Maximum number of BLE peripherals is 8. + * @note Bits 12 - 15 are used to set MAX_NBR_PERIPHERALS. + */ +#define SL_SI91X_BLE_MAX_NBR_PERIPHERALS(max_num_of_peripherals) (max_num_of_peripherals << 12) +/** + * @def SL_SI91X_BLE_PWR_INX + * @brief BLE Tx power index. + * @details + * Sets the BLE Tx power index value. + * - Default value for BLE Tx Power Index is 31. + * - Range for the BLE Tx Power Index is 1 to 127 (0, 32 index is invalid). + * - 1 - 31: BLE - 0dBm Mode + * - 33 - 63: BLE - 10dBm Mode + * - 64 - 127: BLE - HP Mode + + * @note Bits 16 - 23 are used to set PWR_INX. + */ +#define SL_SI91X_BLE_PWR_INX(power_index) (power_index << 16) +/** + * @def SL_SI91X_BLE_PWR_SAVE_OPTIONS + * @brief BLE power save options. + * @details + * Configures BLE power save options. + * - Bit 24: BLE_DUTY_CYCLING + * - Bit 25: BLR_DUTY_CYCLING + * - Bit 26: BLE_4X_PWR_SAVE_MODE + * - For BLE_DISABLE_DUTY_CYCLING, bits 24-26 are set to zero. + + * @note This feature is not supported in the current release. + */ +#define SL_SI91X_BLE_PWR_SAVE_OPTIONS(duty_cycle) (duty_cycle << 24) +/** + * @def SL_SI91X_BLE_MAX_NBR_CENTRALS + * @brief Number of Centrals. + * @details + * Sets the maximum number of BLE Central devices. + + * @note Maximum number of BLE Centrals is 2. + * @note Bits 27 - 28 are used to set BLE_PWR_INX. + */ +#define SL_SI91X_BLE_MAX_NBR_CENTRALS(max_num_of_centrals) (max_num_of_centrals << 27) +/** + * @def SL_SI91X_BLE_GATT_ASYNC_ENABLE + * @brief GATT ASYNC BIT. + * @details + * Enables asynchronous GATT operations. + + * @note Default is disabled. When enabled, the response structure will be filled in the Event, which will come later, not in sync with the response for the query command. + */ +#define SL_SI91X_BLE_GATT_ASYNC_ENABLE BIT(29) +/** + * @def SL_SI91X_916_BLE_COMPATIBLE_FEAT_ENABLE + * @brief BLE feature compatibility. + * @details + * Enables new feature compatible. + * + * @note This bit should be enable to get the set of events from controller for the new features. + */ +#define SL_SI91X_916_BLE_COMPATIBLE_FEAT_ENABLE BIT(30) +/** + * @def SL_SI91X_FEAT_BLE_CUSTOM_FEAT_EXTENTION_VALID + * @brief Extension validity for custom feature bitmap. + * @details + * Validates the use of an extended custom feature bitmap for BLE. + */ +#define SL_SI91X_FEAT_BLE_CUSTOM_FEAT_EXTENSION_VALID BIT(31) +/** @} */ + +/** \addtogroup SI91X_EXTENDED_BLE_CUSTOM_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// Extended BLE custom feature bit map parameters description !// +/*=========================================================================*/ +/** + * @def SL_SI91X_BLE_NUM_CONN_EVENTS + * @brief BLE number of connection events. + * @details + * Describes the number of buffers that need to be allocated for BLE on the opermode. + * - By default, each role (central/peripheral) will be allocated with 1 buffer for the notify/write command. + * - Increasing the buffer capacity for the notify/write commands helps achieve the best throughput. + * - See rsi_ble_set_wo_resp_notify_buf_info() to set more buffers for the notify/write commands. + + * @note Bits 0 - 4 are used to set NUM_CONN_EVENTS. + */ +#define SL_SI91X_BLE_NUM_CONN_EVENTS(num_conn_events) (num_conn_events << 0) +/** + * @def SL_SI91X_BLE_NUM_REC_BYTES + * @brief BLE number of record size in bytes. + * @details + * Specifies the number of record bytes in multiples of 16. + * - n*16 : (n=60, Default 1024 bytes (1K)). + + * @note Bits 5 - 12 are used to set NUM_REC_BYTES. + */ +#define SL_SI91X_BLE_NUM_REC_BYTES(num_rec_bytes) (num_rec_bytes << 5) +/** + * @def SL_SI91X_BLE_GATT_INIT + * @brief GATT initialization mode. + * @details + * Specifies whether the GATT is initialized in firmware or by the host. + * - 0: GATT Init in Firmware. Both the GAP service and GATT service will be maintained by the firmware. + * - 1: GATT Init in Host. The GAP service and GATT service should be created by the APP/Host/User, and the ATT transactions like read, write, notify, and indicate shall be handled by the APP/Host/User. + * - Default: GATT Init in Firmware. + */ +#define SL_SI91X_BLE_GATT_INIT BIT(13) +/** + * @def SL_SI91X_BLE_INDICATE_CONFIRMATION_FROM_HOST + * @brief Acknowlegment of the indication from the client. + * @details + * As per the ATT protocol, every indication received from the server should be acknowledged (indication response) by the client. + * - If this bit is disabled, the firmware will send the acknowledgment (indication response). + * - If this bit is enabled, the APP/Host/User needs to send the acknowledgment (indication response). + */ +#define SL_SI91X_BLE_INDICATE_CONFIRMATION_FROM_HOST BIT(14) +/** + * @def SL_SI91X_BLE_MTU_EXCHANGE_FROM_HOST + * @brief MTU exchange request initiation from APP. + * @details + * - If this bit is disabled, the firmware will initiate the MTU request to the remote device on a successful connection. + * - If the peer initiates an MTU exchange request, the firmware will send an Exchange MTU Response in reply to the received Exchange MTU Request. + * - If this bit is enabled, the APP/Host/User needs to initiate the MTU request using the rsi_ble_mtu_exchange_event API. + * - If the peer initiates an MTU exchange request, the APP/Host/User shall send an Exchange MTU Response using the rsi_ble_mtu_exchange_resp API. + */ +#define SL_SI91X_BLE_MTU_EXCHANGE_FROM_HOST BIT(15) +/** + * @def SL_SI91X_BLE_SET_SCAN_RESP_DATA_FROM_HOST + * @brief Set scan response data from host. + * @details + * The device will maintain some default scan response data to be used in the scan_response controller frame. + * - Enabling this bit will make the default data Null (empty). + */ +#define SL_SI91X_BLE_SET_SCAN_RESP_DATA_FROM_HOST BIT(16) +/** + * @def SL_SI91X_BLE_DISABLE_CODED_PHY_FROM_HOST + * @brief Disable coded PHY from APP. + * @details + * The device supports the LE-coded PHY feature (i.e., LR - 125kbps and 500kbps) by default. + * - If this bit is enabled, the device will not support the LE-coded PHY rates. + */ +#define SL_SI91X_BLE_DISABLE_CODED_PHY_FROM_HOST BIT(17) +/** + * @def SL_SI91X_BLE_ENABLE_ADV_EXTN + * @brief Enable advertising extensions. + * @details + * Enables or disables advertising extensions. + + * @note Bit 19 is used for enabling advertising extensions. + */ +#define SL_SI91X_BLE_ENABLE_ADV_EXTN BIT(19) +/** + * @def SL_SI91X_BLE_AE_MAX_ADV_SETS + * @brief Maximum number of AE advertising sets. + * @details + * Configures the maximum number of AE advertising sets. + * - Maximum number of AE advertising sets is 2. + + * @note Bits 20 - 23 are used to set the number of AE advertising sets. + */ +#define SL_SI91X_BLE_AE_MAX_ADV_SETS(num_adv_sets) (num_adv_sets << 20) + +/// @note Bits 24 -31 are reserved +/** @} */ + +/** \addtogroup SI91X_CONFIG_FEATURE_BITMAP + * @{ */ +/*=========================================================================*/ +// Config feature bitmap parameters description !// +/*=========================================================================*/ +/** + * @def SL_SI91X_FEAT_SLEEP_GPIO_SEL_BITMAP + * @brief Selects the GPIO for wakeup indication to the host. + * @details When this bit is disabled, UULP_GPIO_3 is used as the wakeup indication. When enabled, UULP_GPIO_0 is used instead. + * + * @note Bit 1 is reserved and should not be used. + */ +#define SL_SI91X_FEAT_SLEEP_GPIO_SEL_BITMAP BIT(0) + +/** + * @def SL_SI91X_FEAT_DVS_SEL_CONFIG_1 + * @brief Enables Dynamic Voltage Selection (DVS) Configuration 1. + * @details This bit configures the dynamic voltage selection for the system. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_DVS_SEL_CONFIG_1 BIT(2) + +/** + * @def SL_SI91X_FEAT_DVS_SEL_CONFIG_2 + * @brief Enables Dynamic Voltage Selection (DVS) Configuration 2. + * @details This bit configures the dynamic voltage selection for the system. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_DVS_SEL_CONFIG_2 BIT(3) + +/** + * @def SL_SI91X_FEAT_DVS_SEL_CONFIG_3 + * @brief Enables Dynamic Voltage Selection (DVS) Configuration 3. + * @details This bit configures the dynamic voltage selection for the system. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_DVS_SEL_CONFIG_3 BIT(4) + +/** + * @def SL_SI91X_FEAT_DVS_SEL_CONFIG_4 + * @brief Enables Dynamic Voltage Selection (DVS) Configuration 4. + * @details This bit configures the dynamic voltage selection for the system. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_DVS_SEL_CONFIG_4 BIT(5) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_100us + * @brief Configures External PMU good time to 100 µs. + * @details This bit selects an external PMU good time of 100 microseconds. + * + * @note These bits are used to select external PMU good time. 1 to 15 means 100 usec to 1500 usec (in 100 usec granularity) + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_100us BIT(6) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_200us + * @brief Configures External PMU good time to 200 µs. + * @details This bit selects an external PMU good time of 200 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_200us BIT(7) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_300us + * @brief Configures External PMU good time to 300 µs. + * @details This is a combination of 100 µs and 200 µs good times, totaling 300 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_300us (BIT(6) | BIT(7)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_400us + * @brief Configures External PMU good time to 400 µs. + * @details This bit selects an external PMU good time of 400 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_400us BIT(8) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_500us + * @brief Configures External PMU good time to 500 µs. + * @details This is a combination of 100 µs and 400 µs good times, totaling 500 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_500us (BIT(6) | BIT(8)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_600us + * @brief Configures External PMU good time to 600 µs. + * @details This is a combination of 200 µs and 400 µs good times, totaling 600 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_600us (BIT(7) | BIT(8)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_700us + * @brief Configures External PMU good time to 700 µs. + * @details This is a combination of 100 µs, 200 µs, and 400 µs good times, totaling 700 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_700us (BIT(6) | BIT(7) | BIT(8)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_800us + * @brief Configures External PMU good time to 800 µs. + * @details This bit selects an external PMU good time of 800 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_800us BIT(9) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_900us + * @brief Configures External PMU good time to 900 µs. + * @details This is a combination of 100 µs and 800 µs good times, totaling 900 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_900us (BIT(6) | BIT(9)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1000us + * @brief Configures External PMU good time to 1000 µs. + * @details This is a combination of 200 µs and 800 µs good times, totaling 1000 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1000us (BIT(7) | BIT(9)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1100us + * @brief Configures External PMU good time to 1100 µs. + * @details This is a combination of 100 µs, 200 µs, and 800 µs good times, totaling 1100 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1100us (BIT(6) | BIT(7) | BIT(9)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1200us + * @brief Configures External PMU good time to 1200 µs. + * @details This is a combination of 400 µs and 800 µs good times, totaling 1200 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1200us (BIT(8) | BIT(9)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1300us + * @brief Configures External PMU good time to 1300 µs. + * @details This is a combination of 100 µs, 400 µs, and 800 µs good times, totaling 1300 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1300us (BIT(6) | BIT(8) | BIT(9)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1400us + * @brief Configures External PMU good time to 1400 µs. + * @details This is a combination of 200 µs, 400 µs, and 800 µs good times, totaling 1400 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1400us (BIT(7) | BIT(8) | BIT(9)) + +/** + * @def SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1500us + * @brief Configures External PMU good time to 1500 µs. + * @details This is a combination of 100 µs, 200 µs, 400 µs, and 800 µs good times, totaling 1500 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_EXTERNAL_PMU_GOOD_TIME_1500us (BIT(6) | BIT(7) | BIT(8) | BIT(9)) + +/** + * @def SL_SI91X_FEAT_EXTERNAL_LDO_SEL + * @brief Enables selection of external LDO voltage. + * @details When enabled, this bit allows the selection between using an external LDO or an internal PMU. + * If both the external LDO selection and the LDO voltage are configured, the system uses the external LDO. + * If this bit is cleared, the internal PMU is used. + * + * @note These bits are used for External LDO selection External PMU: + * 1. Incase of External PMU, User has to set EXTERNAL_PMU_GOOD_TIME_CONFIGURATION value to external PMU good time, If this is zero then it indicates using Internal PMU. + * 2. Incase of External PMU 1.0v or 1.05v, User has to set both the bits config_feature_bit_map[11] & config_feature_bit_map[10]. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_EXTERNAL_LDO_SEL BIT(10) + +/** + * @def SL_SI91X_FEAT_EXTERNAL_LDO_VOL + * @brief Selects the external LDO voltage. + * @details This field is relevant only if SL_SI91X_FEAT_EXTERNAL_LDO_SEL is enabled (i.e., BIT(10) is set). + * If this bit is set, the LDO voltage is configured to 1.0V; if cleared, it is set to 1.1V. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_FEAT_EXTERNAL_LDO_VOL BIT(11) + +/** + * @def SL_SI91X_FEAT_EAP_TLS_V1P0 + * @brief Enables TLS version 1.0 for enterprise security. + * + * @note Bit 12 -13 are reserved + */ +#define SL_SI91X_FEAT_EAP_TLS_V1P0 BIT(14) + +/** + * @def SL_SI91X_FEAT_EAP_TLS_V1P2 + * @brief Enables TLS version 1.2 for enterprise security. + */ +#define SL_SI91X_FEAT_EAP_TLS_V1P2 BIT(15) + +/** + * @def SL_SI91X_FEAT_CONC_STA_AP_DYN_SWITCH_SEL + * @brief Configures dynamic switching between STA and AP modes. + * @details This bit enables or disables dynamic switching between Station (STA) and Access Point (AP) modes. + * When enabled, the system can dynamically switch between STA and AP modes based on operational requirements or network conditions. + * This feature is useful for applications requiring flexible mode changes to optimize performance or power consumption. + * + * @note Enabling this feature allows the system to switch modes dynamically, which can improve adaptability in varying network scenarios. + * Make sure to configure the system appropriately for the desired switching behavior. + * @note Bit 16 is reserved + */ +#define SL_SI91X_FEAT_CONC_STA_AP_DYN_SWITCH_SEL BIT(17) + +/** + * @def SL_SI91X_ULP_GPIO9_FOR_UART2_TX + * @brief Selects ULP_GPIO_9 to enable firmware debug prints. + * @details If this bit is not set, the default UART2-TX pin GPIO_6 is used. + * + * @note SI917 supports prints only on ULP_GPIO_9. + */ +#define SL_SI91X_ULP_GPIO9_FOR_UART2_TX BIT(18) + +/** + * @def SL_SI91X_FEAT_DISABLE_MCS_5_6_7_DATARATES + * @brief Disables MCS-5, 6, and 7 data rates. + * @details This bit is used to disable the higher MCS data rates (5, 6, and 7) for reduced data rate requirements. + */ +#define SL_SI91X_FEAT_DISABLE_MCS_5_6_7_DATARATES BIT(19) + +/** + * @def SL_SI91X_FEAT_DISABLE_SHORT_GI + * @brief Disables Short Guard Interval (Short-GI). + * @details This bit disables the use of Short-GI, which may affect the timing and performance of the system. + */ +#define SL_SI91X_FEAT_DISABLE_SHORT_GI BIT(20) + +/** + * @def SL_SI91X_PTA_3WIRE_EN + * @brief Enable PTA 3-Wire feature. + * @details It has three different configurations, which can be chosen in SL_SI91X_PTA_3WIRE_CONFIG_SEL(config_sel)). + */ +#define SL_SI91X_PTA_3WIRE_EN BIT(21) + +/** + * @def SL_SI91X_PTA_3WIRE_CONFIG_SEL + * @brief Option to choose PTA 3-Wire configuration. + * @details It has three different configurations, which can be chosen by enabling or disabling the Bit [23:22]. + * Each of these configurations changes the behavior of how GRANT is asserted in response to REQUEST and PRIORITY signals. + * + * | Configuration | BIT[23] | BIT[22] | + * |:--------------|:--------|:--------| + * | Reserved | 0 | 0 | + * | config1 | 0 | 1 | + * | config2 | 1 | 0 | + * | config3 | 1 | 1 | + * + * | Configuration | Description | + * |:-------------------------|:------------------------------------| + * | Configuration 1 | PTA Main will aggressively assert GRANT if the REQUEST is asserted irrespective of PRIORITY being asserted or not. This will mean any ongoing Wi-Fi transmission will be aborted, and GRANT will be provided to the PTA secondary. | + * | Configuration 2 | PTA Main will aggressively assert GRANT if the REQUEST is asserted irrespective of PRIORITY being asserted or not, with only one exception of an ongoing ACK/Block ACK Transmission in response to a Wi-Fi reception. If there is an ongoing ACK/Block ACK transmission in response to a Wi-Fi Reception, PTA MAIN will GRANT access if PRIORITY is asserted along with REQUEST. | + * | Configuration 3 | If there is an ongoing Wi-Fi Transmission (Including ACK/BLOCK ACK), then PTA MAIN will not assert GRANT to an asserted REQUEST. However, if PRIORITY and REQUEST are asserted, PTA MAIN will assert GRANT. | + * + * The below configuration describes the pin connections between the EFR32MG21 and the SiW91x device that involves the GRANT, REQUEST, and PRIORITY signal. + * 0 kept reserved for future. 3-Wire used at DUT are GPIO_7(Grant pin driven by DUT), ULP_GPIO_1(Request i/p pin for DUT) and ULP_GPIO_6(Priority i/p pin for DUT). + * + * | Pin Description | GPIO | 4338A Radio board | 4002A EFR board | + * |:----------------|:-------------|:-------------------|:----------------| + * | Request | ULP_GPIO_1 | WSTK_P16 | Pin7 | + * | Priority | ULP_GPIO_6 | EXP_HEADER16 | Pin11 | + * | Grant | GPIO_7 | WSTK_P20 | Pin9 | + */ +#define SL_SI91X_PTA_3WIRE_CONFIG_SEL(config_sel) (config_sel << 22) + +/** + * @def SL_SI91X_XTAL_GOODTIME_1000us + * @brief Configures XTAL good time to 1000 µs. + * @details This bit selects a default XTAL good time of 1000 microseconds. This setting is applicable from Release 2.3.0 onward. + * Prior releases have reserved config_feature_bitmap[31:17]. This setting is intended for chip users and not applicable for device users. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_XTAL_GOODTIME_1000us 0 + +/** + * @def SL_SI91X_XTAL_GOODTIME_2000us + * @brief Configures XTAL good time to 2000 µs. + * @details This bit selects an XTAL good time of 2000 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_XTAL_GOODTIME_2000us BIT(24) + +/** + * @def SL_SI91X_XTAL_GOODTIME_3000us + * @brief Configures XTAL good time to 3000 µs. + * @details This bit selects an XTAL good time of 3000 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_XTAL_GOODTIME_3000us BIT(25) + +/** + * @def SL_SI91X_XTAL_GOODTIME_600us + * @brief Configures XTAL good time to 600 µs. + * @details This is a combination of 2000 µs and 3000 µs XTAL good times, totaling 600 microseconds. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_XTAL_GOODTIME_600us (BIT(24) | BIT(25)) + +/** + * @def SL_SI91X_ENABLE_ENHANCED_MAX_PSP + * @brief Enables Enhanced Max PSP. + * @details Set this bit to enable the Enhanced Max PSP feature for improved performance. + */ +#define SL_SI91X_ENABLE_ENHANCED_MAX_PSP BIT(26) + +/** + * @def SL_SI91X_ENABLE_DEBUG_BBP_TEST_PINS + * @brief Enables BBP Test Pins. + * @details Set this bit to enable the use of BBP test pins for debugging and testing purposes. + * + * @note Bits 28 - 31 are reserved for future use. + */ +#define SL_SI91X_ENABLE_DEBUG_BBP_TEST_PINS BIT(27) +/** @} */ + +/** \addtogroup SL_SI91X_CONSTANTS + * @{ */ +/// Si91x operating mode +typedef enum { + SL_SI91X_CLIENT_MODE = 0, ///< Wi-Fi personal client mode + SL_SI91X_ENTERPRISE_CLIENT_MODE = 2, ///< Wi-Fi enterprise client mode + SL_SI91X_ACCESS_POINT_MODE = 6, ///< Wi-Fi access point mode + SL_SI91X_TRANSCEIVER_MODE = 7, ///< Wi-Fi transceiver mode + SL_SI91X_TRANSMIT_TEST_MODE = 8, ///< Wi-Fi transmit test mode + SL_SI91X_CONCURRENT_MODE = 9, ///< Wi-Fi concurrent mode + __FORCE_OPERATION_ENUM_16BIT = 0xFFFF ///< Force the enumeration to be 16-bit +} sl_si91x_operation_mode_t; + +/// Si91x wireless co-existence mode +/// @note Only BLE, WLAN, and WLAN + BLE modes are supported. +typedef enum { + SL_SI91X_WLAN_ONLY_MODE = 0, ///< Wireless local area network (WLAN) only mode + SL_SI91X_WLAN_MODE = 1, ///< WLAN mode (not currently supported) + SL_SI91X_BLUETOOTH_MODE = 4, ///< Bluetooth only mode (not currently supported) + SL_SI91X_WLAN_BLUETOOTH_MODE = 5, ///< WLAN and Bluetooth mode (not currently supported) + SL_SI91X_DUAL_MODE = 8, ///< Dual mode (not currently supported) + SL_SI91X_WLAN_DUAL_MODE = 9, ///< WLAN dual mode (not currently supported) + SL_SI91X_BLE_MODE = 12, ///< Bluetooth Low Energy (BLE) only mode, used when power save mode is not needed. + SL_SI91X_WLAN_BLE_MODE = 13, ///< WLAN and BLE mode + __FORCE_COEX_ENUM_16BIT = 0xFFFF ///< Force the enumeration to be 16-bit +} sl_si91x_coex_mode_t; + +/// Si91x efuse data index +typedef enum { + SL_SI91X_EFUSE_MFG_SW_VERSION = 0, ///< Efuse data index for manufacturing software version + SL_SI91X_EFUSE_PTE_CRC = 1, ///< Efuse data index for PTE CRC +} sl_si91x_efuse_data_type_t; +/** @} */ + +/** \addtogroup SI91X_BURN_TARGET_OPTIONS + * @{ */ +/*=========================================================================*/ +// Burn target options parameters description !// +// This group defines the target options for burning data into different memory types. +//=========================================================================*/ + +/** + * @def SL_SI91X_BURN_INTO_EFUSE + * @brief Option to burn data into EFUSE. + * + * @details This option specifies that the data should be burned into the EFUSE memory. + * EFUSE memory is used for storing critical calibration or configuration data that should not be modified after programming. + * Use this option when permanent storage of data is required. + */ +#define SL_SI91X_BURN_INTO_EFUSE 0 + +/** + * @def SL_SI91X_BURN_INTO_FLASH + * @brief Option to burn data into Flash. + * + * @details This option specifies that the data should be burned into Flash memory. + * Flash memory provides non-volatile storage that can be reprogrammed. + * This is suitable for data that might need to be updated or modified over time. + */ +#define SL_SI91X_BURN_INTO_FLASH 1 +/** @} */ + +/** \addtogroup SI91X_CALIBRATION_FLAGS + * @{ */ +/** + * @def SL_SI91X_BURN_GAIN_OFFSET + * @brief Burn gain offset into the device. + * + * @details + * This macro defines the bit for burning the gain offset into the device. + */ +#define SL_SI91X_BURN_GAIN_OFFSET BIT(0) + +/** + * @def SL_SI91X_BURN_FREQ_OFFSET + * @brief Burn frequency offset into the device. + * + * @details + * This macro defines the bit for burning the frequency offset into the device. + */ +#define SL_SI91X_BURN_FREQ_OFFSET BIT(1) + +/** + * @def SL_SI91X_SW_XO_CTUNE_VALID + * @brief Indicates if the software XO CTUNE is valid. + * + * @details + * This macro defines the bit to indicate that the software XO CTUNE (crystal tuning) value is valid. + */ +#define SL_SI91X_SW_XO_CTUNE_VALID BIT(2) + +/** + * @def SL_SI91X_BURN_XO_FAST_DISABLE + * @brief Burn bit to disable XO fast into the device. + * + * @details + * This macro defines the bit for burning a setting to disable the fast XO (crystal oscillator) into the device. + * + * @note Not applicable for SI917. + */ +#define SL_SI91X_BURN_XO_FAST_DISABLE BIT(3) + +/** @} */ + +/** \addtogroup SI91X_DTIM_ALIGNMENT_TYPES + * @{ */ +/// Module wakes up at beacon which is just before or equal to listen_interval +#define SL_SI91X_ALIGN_WITH_BEACON 0 +/// Module wakes up at DTIM beacon which is just before or equal to listen_interval +#define SL_SI91X_ALIGN_WITH_DTIM_BEACON 1 +/** @} */ + +/** \addtogroup SL_SI91X_TYPES Types + * @{ + * */ +// Device configuration for 911x. This should be in the 911x driver folder +/// Device configuration for Si91x device +typedef struct { + uint8_t boot_option; ///< Boot option. One of the values from @ref SI91X_LOAD_IMAGE_TYPES + sl_mac_address_t * + mac_address; ///< MAC address of type [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t). + sl_si91x_band_mode_t band; ///< Si91x Wi-Fi band of type @ref sl_si91x_band_mode_t. + sl_si91x_region_code_t region_code; ///< Si91x region code of type @ref sl_si91x_region_code_t. + sl_si91x_boot_configuration_t boot_config; ///< Si91x boot configuration. Refer to @ref SL_SI91X_BOOT_CONFIGURATION. + sl_si91x_dynamic_pool ta_pool; ///< TA buffer allocation command parameters of type @ref sl_si91x_dynamic_pool. + uint8_t efuse_data_type; ///Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_host_interface.h" +#include +#include +#include +#include "cmsis_os2.h" +#include +extern osMutexId_t malloc_free_mutex; +sl_status_t sl_si91x_host_init_buffer_manager(void); +sl_status_t sl_si91x_host_deinit_buffer_manager(void); +sl_status_t sl_si91x_host_allocate_buffer(sl_wifi_buffer_t **buffer, + sl_wifi_buffer_type_t type, + uint32_t buffer_size, + uint32_t wait_duration_ms); +void *sl_si91x_host_get_buffer_data(sl_wifi_buffer_t *buffer, uint16_t offset, uint16_t *data_length); +void sl_si91x_host_free_buffer(sl_wifi_buffer_t *buffer); + +sl_status_t sl_si91x_host_init_buffer_manager(void) +{ + if (malloc_free_mutex == NULL) { + malloc_free_mutex = osMutexNew(NULL); + } + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_host_deinit_buffer_manager(void) +{ + if (malloc_free_mutex != NULL) { + osMutexDelete(malloc_free_mutex); + malloc_free_mutex = NULL; + } + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_host_allocate_buffer(sl_wifi_buffer_t **buffer, + sl_wifi_buffer_type_t type, + uint32_t buffer_size, + uint32_t wait_duration_ms) +{ + (void)type; + osMutexAcquire(malloc_free_mutex, 0xFFFFFFFFUL); + uint32_t start = osKernelGetTickCount(); + sl_wifi_buffer_t *temp = NULL; + do { + temp = (sl_wifi_buffer_t *)malloc(buffer_size + sizeof(*temp)); + if (temp != NULL) { + break; + } else { + osDelay(1); + } + } while ((osKernelGetTickCount() - start) < wait_duration_ms); + + osMutexRelease(malloc_free_mutex); + if (temp == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + temp->length = buffer_size; + temp->node.node = NULL; + *buffer = temp; + return SL_STATUS_OK; +} + +void *sl_si91x_host_get_buffer_data(sl_wifi_buffer_t *buffer, uint16_t offset, uint16_t *data_length) +{ + if (offset >= buffer->length) { + return NULL; + } + if (data_length) { + *data_length = (uint16_t)(buffer->length) - offset; + } + return (void *)&buffer->data[offset]; +} + +void sl_si91x_host_free_buffer(sl_wifi_buffer_t *buffer) +{ + if (buffer == NULL) { + return; + } + osMutexAcquire(malloc_free_mutex, 0xFFFFFFFFUL); + free((void *)buffer); + osMutexRelease(malloc_free_mutex); +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_rsi_utility.h b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_rsi_utility.h new file mode 100644 index 000000000..49a5cf25f --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_rsi_utility.h @@ -0,0 +1,55 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include +#include +#include +#include "sl_status.h" +#include "sl_si91x_host_interface.h" +#include "sl_si91x_protocol_types.h" +#include "sl_net_constants.h" +#include "sl_net_ip_types.h" +#ifdef SLI_SI91X_INTERNAL_HTTP_CLIENT +#include "sl_http_client.h" +#endif + +sl_status_t convert_rsi_ipv4_address_to_sl_ip_address(sl_ip_address_t *ip_address_buffer, + const sl_si91x_rsp_ipv4_params_t *ip_params); +sl_status_t convert_si91x_dns_response(sl_ip_address_t *ip_address, const sl_si91x_dns_response_t *si91x_dns_response); +sl_status_t convert_si91x_event_to_sl_net_event(const uint16_t *event, sl_net_event_t *sl_net_event); +#ifdef SLI_SI91X_INTERNAL_HTTP_CLIENT +void convert_itoa(uint32_t val, uint8_t *str); +sl_status_t convert_si91x_event_to_sl_http_client_event(const uint16_t *event, + sl_http_client_event_t *sl_http_client_event); +#endif +sl_status_t sli_si91x_configure_ip_address(sl_net_ip_configuration_t *address, + uint8_t virtual_ap_id, + const uint32_t timeout); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x.h b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x.h new file mode 100644 index 000000000..73479711c --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x.h @@ -0,0 +1,113 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_net_types.h" +#include "sl_net_ip_types.h" +#include "sl_net_constants.h" +#include "sl_wifi_host_interface.h" + +/** \addtogroup SI91X_NETWORK_FUNCTIONS + * \ingroup SL_SI91X_API + * @{ */ +/***************************************************************************/ +/** + * @brief + * Configure the IP address for the specified virtual AP. + * + * @details + * This function configures the IP address for the specified virtual Access Point (AP) on the Si91x device. The IP address details are provided in the `address` parameter. + * + * Virtual AP ID is used to differentiate between client and AP in concurrent mode. + * + * @param[in] address + * Pointer to an [sl_net_ip_configuration_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-ip-configuration-t) structure where the assigned IP address details will be stored. + * + * @param[in] virtual_ap_id + * Virtual AP ID. One of the values from @ref sl_si91x_wifi_vap_id_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + */ +sl_status_t sl_si91x_configure_ip_address(sl_net_ip_configuration_t *address, uint8_t virtual_ap_id); +/** @} */ + +/***************************************************************************/ /** + * @brief + * Register a event handler for network events. + * @param[in] function + * Function pointer to callback. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_register_event_handler(sl_net_event_handler_t function); + +/***************************************************************************/ /** + * @brief + * Default event handler for all events. + * @param[in] event + * [sl_net_event_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-constants#sl-net-event-t) Asynchronous event received. + * @param[in] buffer + * [sl_wifi_buffer_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-buffer-t) Buffer containing data related to asynchronous event. + * @pre Pre-conditions: + * - + * @ref sl_si91x_driver_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_si91x_default_handler(sl_net_event_t event, sl_wifi_buffer_t *buffer); + +//! @cond Doxygen_Suppress +/// Enumerate multicast address command types +typedef enum { + SL_WIFI_MULTICAST_LEAVE = 0, ///< Wi-Fi multicast leave + SL_WIFI_MULTICAST_JOIN = 1, ///< Wi-Fi mulitcast join +} sl_si91x_multicast_address_command_type_t; + +/// Enumerate IP configuration modes for SI91X module +typedef enum { + SL_SI91X_STATIC = 0, ///< Static + SL_SI91X_DHCP, ///< DHCP + SL_SI91X_DHCP_RESERVED, ///< DHCP Rseserved + SL_SI91X_DHCP_HOSTNAME, ///< DHCP HostName + SL_SI91X_DHCP_OPTION81, ///< DHCP option 81 + SL_SI91X_DHCP_OPTION77 ///< DHCP option 77 +} sl_si91x_ip_config_mode_t; + +sl_status_t sl_si91x_set_credential(sl_net_credential_id_t id, + sl_net_credential_type_t type, + const void *credential, + uint32_t credential_length); + +sl_status_t sl_si91x_delete_credential(sl_net_credential_id_t id, sl_net_credential_type_t type); +//! @endcond diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x_integration_handler.h b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x_integration_handler.h new file mode 100644 index 000000000..8aa64372d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/inc/sl_net_si91x_integration_handler.h @@ -0,0 +1,48 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once +#include "sl_si91x_types.h" + +#define SL_NET_EVENT_DISPATCH_HANDLER(data, packet) sl_net_si91x_event_dispatch_handler(data, packet) + +void sl_net_si91x_event_dispatch_handler(sli_si91x_queue_packet_t *data, sl_si91x_packet_t *packet); + +#define SLI_NETWORK_CLEANUP_HANDLER() sli_si91x_network_cleanup_handler() + +void sli_si91x_network_cleanup_handler(); + +#if defined(SL_WIFI_COMPONENT_INCLUDED) +/* +This function flushes all transmit (TX) command and data queues for sockets that match a given destination IP address. +It iterates through all available sockets, checks if a socket's remote address matches the specified IP address, +and then flushes the command and data queues for that socket based on the provided frame_status*/ +sl_status_t sli_si91x_flush_all_socket_tx_queues_based_on_dest_ip_address(uint16_t frame_status, + const sl_ip_address_t *dest_ip_add); +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c new file mode 100644 index 000000000..f3e4fa97d --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c @@ -0,0 +1,180 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_protocol_types.h" +#include "sl_si91x_constants.h" +#include "sl_net_constants.h" +#include "sl_wifi_constants.h" +#include "sl_status.h" +#include "sl_constants.h" +#include "sl_wifi_types.h" +#include "sl_net_rsi_utility.h" +#include + +sl_status_t convert_rsi_ipv4_address_to_sl_ip_address(sl_ip_address_t *ip_address_buffer, + const sl_si91x_rsp_ipv4_params_t *ip_params) +{ + // Verify input pointers + SL_VERIFY_POINTER_OR_RETURN(ip_address_buffer, SL_STATUS_WIFI_NULL_PTR_ARG); + SL_VERIFY_POINTER_OR_RETURN(ip_params, SL_STATUS_WIFI_NULL_PTR_ARG); + + uint8_t *ip_address; + + ip_address_buffer->type = SL_IPV4; + ip_address = ip_address_buffer->ip.v4.bytes; + + memcpy(ip_address, ip_params->ipaddr, sizeof(sl_ipv4_address_t)); + return SL_STATUS_OK; +} + +sl_status_t convert_si91x_dns_response(sl_ip_address_t *ip_address, const sl_si91x_dns_response_t *si91x_dns_response) +{ + SL_VERIFY_POINTER_OR_RETURN(ip_address, SL_STATUS_WIFI_NULL_PTR_ARG); + SL_VERIFY_POINTER_OR_RETURN(si91x_dns_response, SL_STATUS_WIFI_NULL_PTR_ARG); + + // Check if DNS response has IP addresses + if ((si91x_dns_response->ip_count[0] | (si91x_dns_response->ip_count[1] << 8)) <= 0) { + return SL_STATUS_OK; + } + + // Determine IP address size (IPv4 or IPv6) and copy the address bytes + uint8_t ip_address_size = (si91x_dns_response->ip_version[0] | si91x_dns_response->ip_version[1] << 8) + == SL_IPV4_ADDRESS_LENGTH + ? SL_IPV4_ADDRESS_LENGTH + : SL_IPV6_ADDRESS_LENGTH; + uint8_t *sl_ip_address; + const uint8_t *si91x_ip_address; + + ip_address->type = ip_address_size == SL_IPV4_ADDRESS_LENGTH ? SL_IPV4 : SL_IPV6; + + si91x_ip_address = ip_address_size == SL_IPV4_ADDRESS_LENGTH ? si91x_dns_response->ip_address[0].ipv4_address + : si91x_dns_response->ip_address[0].ipv6_address; + sl_ip_address = ip_address_size == SL_IPV4_ADDRESS_LENGTH ? ip_address->ip.v4.bytes : ip_address->ip.v6.bytes; + + memcpy(sl_ip_address, si91x_ip_address, ip_address_size); + + return SL_STATUS_OK; +} + +sl_status_t convert_si91x_event_to_sl_net_event(const uint16_t *event, sl_net_event_t *sl_net_event) +{ + // Verify input pointers + SL_WIFI_ARGS_CHECK_NULL_POINTER(event); + SL_WIFI_ARGS_CHECK_NULL_POINTER(sl_net_event); + + // Map SI91X events to SimpleLink network events + switch (*event) { + case RSI_WLAN_RSP_DNS_QUERY: { + *sl_net_event = SL_NET_DNS_RESOLVE_EVENT; + return SL_STATUS_OK; + } + case RSI_WLAN_RSP_PING_PACKET: { + *sl_net_event = SL_NET_PING_RESPONSE_EVENT; + return SL_STATUS_OK; + } + case RSI_WLAN_RSP_OTA_FWUP: { + *sl_net_event = SL_NET_OTA_FW_UPDATE_EVENT; + return SL_STATUS_OK; + } + case RSI_WLAN_RSP_IPCONFV4: { + *sl_net_event = SL_NET_DHCP_NOTIFICATION_EVENT; + return SL_STATUS_OK; + } + case RSI_WLAN_RSP_IPV4_CHANGE: + case RSI_WLAN_RSP_IPCONFV6: { + *sl_net_event = SL_NET_IP_ADDRESS_CHANGE_EVENT; + return SL_STATUS_OK; + } + default: + break; + } + + return SL_STATUS_FAIL; +} + +#ifdef SLI_SI91X_INTERNAL_HTTP_CLIENT +// Convert integer to string +void convert_itoa(uint32_t val, uint8_t *str) +{ + int16_t ii = 0; + int16_t jj = 0; + uint8_t tmp[10]; + + if (val == 0) { + // if value is zero then handling + str[jj] = '0'; + jj++; + str[jj] = '\0'; + return; + } + + // Convert the integer to a string + while (val) { + tmp[ii] = '0' + (val % 10); + val /= 10; + ii++; + } + + // Reverse the string + for (jj = 0, ii--; ii >= 0; ii--, jj++) { + str[jj] = tmp[ii]; + } + str[jj] = '\0'; +} + +sl_status_t convert_si91x_event_to_sl_http_client_event(const uint16_t *event, + sl_http_client_event_t *sl_http_client_event) +{ + // Verify input pointer + SL_WIFI_ARGS_CHECK_NULL_POINTER(event); + + // Map SI91X HTTP client events to SimpleLink HTTP client events + switch (*event) { + case RSI_WLAN_RSP_HTTP_CLIENT_GET: { + *sl_http_client_event = SL_HTTP_CLIENT_GET_RESPONSE_EVENT; + return SL_STATUS_OK; + } + + case RSI_WLAN_RSP_HTTP_CLIENT_POST: + case RSI_WLAN_RSP_HTTP_CLIENT_POST_DATA: { + *sl_http_client_event = SL_HTTP_CLIENT_POST_RESPONSE_EVENT; + return SL_STATUS_OK; + } + + case RSI_WLAN_RSP_HTTP_CLIENT_PUT: { + *sl_http_client_event = SL_HTTP_CLIENT_PUT_RESPONSE_EVENT; + return SL_STATUS_OK; + } + default: + break; + } + + return SL_STATUS_FAIL; +} +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_callback_framework.c b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_callback_framework.c new file mode 100644 index 000000000..a9d8d340a --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_callback_framework.c @@ -0,0 +1,118 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_net_types.h" +#include "sl_net_rsi_utility.h" +#include "sl_si91x_core_utilities.h" +#include "sl_si91x_driver.h" +#include "sl_si91x_constants.h" + +// SL_NET_EVENT_COUNT is assumed to be a constant representing the number of network events +static sl_net_event_handler_t net_event_handler = NULL; + +sl_status_t sl_si91x_register_event_handler(sl_net_event_handler_t function) +{ + net_event_handler = function; + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_default_handler(sl_net_event_t event, sl_wifi_buffer_t *buffer) +{ + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + sl_status_t status = convert_and_save_firmware_status(get_si91x_frame_status(packet)); + sl_ip_address_t ip = { 0 }; + sl_net_ip_configuration_t ip_config = { 0 }; + const sl_si91x_rsp_ipv4_params_t *ipv4_parameters = NULL; + const sl_si91x_rsp_ipv6_params_t *ipv6_parameters = NULL; + void *data; + + // Check if there's a valid event handler registered for this event + if (net_event_handler == NULL) { + return SL_STATUS_FAIL; // If no event handler is registered, return failure + } + + // Depending on the event type, prepare data for the event handler + switch (event) { + case SL_NET_DNS_RESOLVE_EVENT: { + data = &ip; + + // Convert the SI91x DNS response to an IP address structure + convert_si91x_dns_response(&ip, (sl_si91x_dns_response_t *)packet->data); + break; + } + case SL_NET_OTA_FW_UPDATE_EVENT: + case SL_NET_PING_RESPONSE_EVENT: + case SL_NET_DHCP_NOTIFICATION_EVENT: { + data = &packet->data; // Use packet data directly for certain events + break; + } + case SL_NET_IP_ADDRESS_CHANGE_EVENT: { + + data = &ip_config; + ip_config.host_name = NULL; + ip_config.mode = SL_IP_MANAGEMENT_DHCP; + + if (packet->command == RSI_WLAN_RSP_IPCONFV6) { + ipv6_parameters = (sl_si91x_rsp_ipv6_params_t *)packet->data; + ip_config.type = SL_IPV6; + + if (NULL != ipv6_parameters) { + memcpy(ip_config.ip.v6.link_local_address.bytes, + (const uint8_t *)ipv6_parameters->link_local_address, + sizeof(ipv6_parameters->link_local_address)); + memcpy(ip_config.ip.v6.global_address.bytes, + (const uint8_t *)ipv6_parameters->global_address, + sizeof(ipv6_parameters->global_address)); + memcpy(ip_config.ip.v6.gateway.bytes, + (const uint8_t *)ipv6_parameters->gateway_address, + sizeof(ipv6_parameters->gateway_address)); + } + + } else { + ipv4_parameters = (sl_si91x_rsp_ipv4_params_t *)packet->data; + ip_config.type = SL_IPV4; + + if (NULL != ipv4_parameters) { + memcpy(ip_config.ip.v4.ip_address.bytes, ipv4_parameters->ipaddr, sizeof(ipv4_parameters->ipaddr)); + memcpy(ip_config.ip.v4.netmask.bytes, ipv4_parameters->netmask, sizeof(ipv4_parameters->netmask)); + memcpy(ip_config.ip.v4.gateway.bytes, ipv4_parameters->gateway, sizeof(ipv4_parameters->gateway)); + } + } + break; + } + default: { + SL_DEBUG_LOG("\r\nUnsupported event\r\n"); + return SL_STATUS_FAIL; // Return failure for unsupported events + } + } + // Call the registered event handler function with event details + net_event_handler(event, status, data, packet->length); + + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c new file mode 100644 index 000000000..aec0eeab0 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c @@ -0,0 +1,339 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_constants.h" +#include "sl_si91x_types.h" +#include "sl_si91x_driver.h" +#include "sl_net_si91x.h" +#include "sl_net_constants.h" +#include "sl_net_rsi_utility.h" +#include "sl_net_si91x_integration_handler.h" +#if defined(SL_WIFI_COMPONENT_INCLUDED) +#include "sl_wifi.h" +#endif +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +#include "sl_si91x_socket_constants.h" +#include "sl_si91x_socket_utility.h" +#include "sl_ip_types.h" +#endif + +extern sli_si91x_command_queue_t cmd_queues[SI91X_CMD_MAX]; + +#ifdef SLI_SI91X_SOCKETS +#include "sl_si91x_socket_utility.h" +#include "sl_si91x_socket_callback_framework.h" +#endif +#include "sl_si91x_core_utilities.h" + +#ifdef SLI_SI91X_EMBEDDED_MQTT_CLIENT +#include "si91x_mqtt_client_callback_framework.h" +#include "si91x_mqtt_client_utility.h" +#endif + +#ifdef SLI_SI91X_INTERNAL_SNTP_CLIENT +#include "si91x_sntp_client_callback_framework.h" +#endif + +#ifdef SLI_SI91X_INTERNAL_HTTP_CLIENT +#include "sl_si91x_http_client_callback_framework.h" +#endif + +#ifdef SLI_SI91X_EMBEDDED_MQTT_CLIENT +/** + * A internal function to handle to asynchronous mqtt client events. + */ +static void handle_mqtt_client_asynch_events(sli_si91x_queue_packet_t *mqtt_asyn_packet) +{ + sl_si91x_packet_t *raw_rx_packet = sl_si91x_host_get_buffer_data(mqtt_asyn_packet->host_packet, 0, NULL); + sl_mqtt_client_t *mqtt_client; + + raw_rx_packet->desc[12] = mqtt_asyn_packet->frame_status & 0xFF; // Lower 8 bits + raw_rx_packet->desc[13] = (mqtt_asyn_packet->frame_status >> 8) & 0xFF; // Upper 8 bits + //Variable to indicate whether a disconnect event is related to a keep-alive terminate error. + bool is_keep_alive_response_related_disconnect = + (raw_rx_packet->command == RSI_WLAN_RSP_EMB_MQTT_CLIENT + && mqtt_asyn_packet->frame_status == (SL_STATUS_SI91X_MQTT_KEEP_ALIVE_TERMINATE_ERROR & ~BIT(16))); + + // Since these responses are unsolicited, We need to create a context for them. + if (raw_rx_packet->command == RSI_WLAN_RSP_MQTT_REMOTE_TERMINATE + || raw_rx_packet->command == RSI_WLAN_RSP_EMB_MQTT_PUBLISH_PKT || raw_rx_packet->command == RSI_WLAN_RSP_JOIN + || is_keep_alive_response_related_disconnect) { + + sli_si91x_get_mqtt_client(&mqtt_client); + + if (mqtt_client == NULL) { + // Drop MQTT client event, if the client is either connecting or disconnected + SL_DEBUG_LOG("Dropping mqtt client event, Si91x Event: %hu", raw_rx_packet->command); + return; + } + + if (mqtt_client->state == SL_MQTT_CLIENT_DISCONNECTED) { + // Drop MQTT client event disconnect, if the client is already in disconnected + // This can happen if MQTT client is already disconnected state and NWP sends a rejoin failure event. + SL_DEBUG_LOG("Dropping mqtt disconnect event: %hu", raw_rx_packet->command); + return; + } + + // Send CONNECT_FAILED_EVENT if JOIN is received during TA_INIT state + if ((raw_rx_packet->command == RSI_WLAN_RSP_JOIN || raw_rx_packet->command == RSI_WLAN_RSP_DISCONNECT) + && mqtt_client->state == SL_MQTT_CLIENT_TA_INIT) { + // Build MQTT SDK context for asynchronous MQTT events + sli_si91x_build_mqtt_sdk_context_if_async(SL_MQTT_CLIENT_CONNECTED_EVENT, + mqtt_client, + NULL, + NULL, + 0, + (sl_si91x_mqtt_client_context_t **)&mqtt_asyn_packet->sdk_context); + } else { + // Build MQTT SDK context for asynchronous MQTT events + sli_si91x_build_mqtt_sdk_context_if_async( + (raw_rx_packet->command == RSI_WLAN_RSP_MQTT_REMOTE_TERMINATE || raw_rx_packet->command == RSI_WLAN_RSP_JOIN + || is_keep_alive_response_related_disconnect) + ? SL_MQTT_CLIENT_DISCONNECTED_EVENT + : SL_MQTT_CLIENT_MESSAGED_RECEIVED_EVENT, + mqtt_client, + NULL, + NULL, + 0, + (sl_si91x_mqtt_client_context_t **)&mqtt_asyn_packet->sdk_context); + } + } + + sl_si91x_mqtt_client_context_t *sdk_context = (sl_si91x_mqtt_client_context_t *)mqtt_asyn_packet->sdk_context; + + if (sdk_context == NULL) { + return; + } + + SL_DEBUG_LOG("handle_mqtt_client_asynch_events: event %x", sdk_context->event); + + uint16_t si91x_event_status = get_si91x_frame_status(raw_rx_packet); + sl_status_t event_status = convert_and_save_firmware_status(si91x_event_status); + + // Handle MQTT events + sli_si91x_mqtt_event_handler(event_status, sdk_context, raw_rx_packet); +} +#endif + +/*static void si91x_node_free_function(sl_wifi_buffer_t *buffer) +{ + sl_si91x_host_free_buffer(buffer); +}*/ + +void sl_net_si91x_event_dispatch_handler(sli_si91x_queue_packet_t *data, sl_si91x_packet_t *packet) +{ + sl_status_t status; + sl_net_event_t service_event; +#ifdef SLI_SI91X_INTERNAL_HTTP_CLIENT + sl_http_client_event_t http_event; +#endif + +#ifdef SLI_SI91X_EMBEDDED_MQTT_CLIENT + // Handle MQTT client-specific events + if (packet->command == RSI_WLAN_REQ_EMB_MQTT_CLIENT || packet->command == RSI_WLAN_RSP_EMB_MQTT_PUBLISH_PKT + || packet->command == RSI_WLAN_RSP_MQTT_REMOTE_TERMINATE) { + handle_mqtt_client_asynch_events(data); + return; + } else if (packet->command == RSI_WLAN_RSP_JOIN) { + handle_mqtt_client_asynch_events(data); + } +#endif + +#ifdef SLI_SI91X_INTERNAL_SNTP_CLIENT + // Handle SNTP client events + if (packet->command == RSI_WLAN_RSP_SNTP_CLIENT) { + sli_si91x_sntp_event_handler(data); + return; + } +#endif + +#ifdef SLI_SI91X_SOCKETS + // Handle SI91X socket-related events + bool is_socket_command = + (packet->command == RSI_WLAN_REQ_SOCKET_ACCEPT || packet->command == RSI_WLAN_RSP_REMOTE_TERMINATE + || packet->command == RSI_RECEIVE_RAW_DATA || packet->command == RSI_WLAN_RSP_TCP_ACK_INDICATION + || packet->command == RSI_WLAN_RSP_SELECT_REQUEST); + if (is_socket_command) { + sl_si91x_packet_t *raw_rx_packet = packet; + uint16_t si91x_event_status = get_si91x_frame_status(raw_rx_packet); + + sl_status_t event_status = convert_and_save_firmware_status(si91x_event_status); + si91x_socket_event_handler(event_status, (sl_si91x_socket_context_t *)data->sdk_context, raw_rx_packet); + } +#endif + +#if defined(SL_WIFI_COMPONENT_INCLUDED) + // Retrieve the current operation mode (e.g., client, AP, concurrent). + sl_si91x_operation_mode_t current_operation_mode = get_opermode(); + + // Determine if a Wi-Fi client is disconnected from the access point. + // This includes cases where the device is operating as an access point (AP mode) + // or in concurrent mode where the AP VAP ID is relevant. + bool is_client_disconnected_from_ap = + (packet->command == RSI_WLAN_RSP_CLIENT_DISCONNECTED + || (packet->command == RSI_WLAN_RSP_DISCONNECT + && (current_operation_mode == SL_SI91X_ACCESS_POINT_MODE + || (current_operation_mode == SL_SI91X_CONCURRENT_MODE && packet->desc[7] == SL_SI91X_WIFI_AP_VAP_ID)))); + + // Determine if a TX flush is required. + // This is true for scenarios such as join failures, IP address changes, and disconnections. + bool is_tx_flush_required = (((packet->command == RSI_WLAN_RSP_JOIN) && (data->frame_status != SL_STATUS_OK)) + || packet->command == RSI_WLAN_RSP_IPV4_CHANGE + || packet->command == RSI_WLAN_RSP_IPCONFV4 || packet->command == RSI_WLAN_RSP_IPCONFV6 + || packet->command == RSI_WLAN_RSP_DISCONNECT + || packet->command == RSI_WLAN_RSP_AP_STOP); + + // Handle the scenario where a Wi-Fi client disconnects from the AP. + if (is_client_disconnected_from_ap) { + sl_mac_address_t mac_address = { 0 }; + + // Extract the MAC address based on the specific disconnection command. + if (packet->command == RSI_WLAN_RSP_CLIENT_DISCONNECTED) { + // For a client disconnection, the MAC address is in the packet data. + memcpy((uint8_t *)&mac_address, (uint8_t *)packet->data, sizeof(sl_mac_address_t)); + } else { + // For a general disconnect, the MAC address is in the SDK context. + memcpy((uint8_t *)&mac_address, (uint8_t *)data->sdk_context, sizeof(sl_mac_address_t)); + } + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + // Retrieve the destination IP address associated with the MAC address. + const sl_ip_address_t *destination_ip_address = sli_si91x_get_ap_client_ip_address_from_mac_address(mac_address); + + // If an IP address is found, flush all socket TX queues for that destination. + if (destination_ip_address != NULL) { + sli_si91x_flush_all_socket_tx_queues_based_on_dest_ip_address(data->frame_status, destination_ip_address); + } +#endif + + // Update AP client information after handling the disconnection. + sli_si91x_update_ap_client_info(); + + } else if (is_tx_flush_required) { + // Handle cases where a general TX flush might be needed due to connection changes. + + // Check if the condition necessitates a general TX Wi-Fi queue flush. + bool is_general_tx_queue_flush_needed = + (packet->command == RSI_WLAN_RSP_JOIN || packet->command == RSI_WLAN_RSP_IPV4_CHANGE + || packet->command == RSI_WLAN_RSP_IPCONFV4 || packet->command == RSI_WLAN_RSP_IPCONFV6 + || (packet->command == RSI_WLAN_RSP_DISCONNECT + && (current_operation_mode == SL_SI91X_CLIENT_MODE + || (current_operation_mode == SL_SI91X_CONCURRENT_MODE + && packet->desc[7] == SL_SI91X_WIFI_CLIENT_VAP_ID)))); + + // If a general flush is required, clear all TX Wi-Fi queues as the connection is lost. + if (is_general_tx_queue_flush_needed) { + sli_si91x_flush_all_tx_wifi_queues(SL_STATUS_WIFI_CONNECTION_LOST); +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + // Flush the select request table based on the provided frame_status + sli_si91x_flush_select_request_table(data->frame_status); +#endif + } + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + // Define the VAP ID for the client (default to client VAP ID). + uint8_t vap_id_for_flush = SL_SI91X_WIFI_CLIENT_VAP_ID; + + // In concurrent mode with an AP stop command, use the AP VAP ID for the flush. + if (current_operation_mode == SL_SI91X_CONCURRENT_MODE && packet->command == RSI_WLAN_RSP_AP_STOP) { + vap_id_for_flush = SL_SI91X_WIFI_AP_VAP_ID; + } + + // Flush all pending socket commands for the determined VAP ID. + sli_si91x_flush_all_socket_command_queues(data->frame_status, vap_id_for_flush); + + // Flush all pending socket data for the determined VAP ID. + sli_si91x_flush_all_socket_data_queues(vap_id_for_flush); + + // Shutdown and update the state of the sockets associated with the VAP ID. + sli_si91x_vap_shutdown(vap_id_for_flush); +#endif + } +#endif + + status = convert_si91x_event_to_sl_net_event(&packet->command, &service_event); + if (status == SL_STATUS_OK) { + SL_DEBUG_LOG("><<<< Got net event : %u\n", service_event); + sl_si91x_default_handler(service_event, data->host_packet); + } +#ifdef SLI_SI91X_INTERNAL_HTTP_CLIENT + // Check for sl_http_client_event_t + else if (convert_si91x_event_to_sl_http_client_event(&packet->command, &http_event) == SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n>>> HTTP Event received: %u <<<\r\n", http_event); + sl_http_client_default_event_handler(http_event, data->host_packet, data->sdk_context); + } +#endif +} + +void sli_si91x_network_cleanup_handler() +{ +#ifdef SLI_SI91X_EMBEDDED_MQTT_CLIENT + sli_mqtt_client_cleanup(); +#endif +} + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +sl_status_t sli_si91x_flush_all_socket_tx_queues_based_on_dest_ip_address(uint16_t frame_status, + const sl_ip_address_t *dest_ip_add) +{ + sl_status_t status; + + // Loop through all sockets + for (uint8_t index = 0; index < NUMBER_OF_SOCKETS; index++) { + // Check if the socket exists and matches the required VAP ID + if (sli_si91x_sockets[index] != NULL) { + bool is_same = 0; + if (dest_ip_add->type == SL_IPV4) { + const struct sockaddr_in *socket_address = (struct sockaddr_in *)&sli_si91x_sockets[index]->remote_address; + is_same = memcmp(dest_ip_add->ip.v4.bytes, &socket_address->sin_addr.s_addr, SL_IPV4_ADDRESS_LENGTH); + } else { + const struct sockaddr_in6 *ipv6_socket_address = &sli_si91x_sockets[index]->remote_address; + is_same = memcmp(dest_ip_add->ip.v6.bytes, + &ipv6_socket_address->sin6_addr.s6_addr, + SL_IPV6_ADDRESS_LENGTH); + } + if (!is_same) { + // Flush the command queues for the current socket based on queue type + status = sli_si91x_flush_socket_command_queues_based_on_queue_type(index, frame_status); + // If flushing fails, return the error status immediately + VERIFY_STATUS_AND_RETURN(status); + + status = sli_si91x_flush_socket_data_queues_based_on_queue_type(index); + // If flushing fails, return the error status immediately + VERIFY_STATUS_AND_RETURN(status); + + // update the socket state to disconnected. + sli_si91x_sockets[index]->state = DISCONNECTED; + } + } + } + // Return SL_STATUS_OK if all sockets were processed successfully + return SL_STATUS_OK; +} +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c new file mode 100644 index 000000000..b71869d5f --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c @@ -0,0 +1,174 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_status.h" +#include "sl_net.h" +#include "sl_si91x_driver.h" +#include "sl_wifi_credentials.h" + +/// Enumerations of TLS certificate types +typedef enum { + SL_SI91X_EAP_CLIENT = 1, ///< SL_SI91X_EAP_CLIENT + SL_SI91X_FAST_PAC_FILE = 2, ///< SL_SI91X_FAST_PAC_FILE + SL_SI91X_TLS_CLIENT = 3, ///< SL_SI91X_TLS_CLIENT + SL_SI91X_TLS_CLIENT_PRIVATE_KEY = 4, ///< SL_SI91X_TLS_CLIENT_PRIVATE_KEY + SL_SI91X_TLS_CA_CERTIFICATE = 5, ///< SL_SI91X_TLS_CA_CERTIFICATE + SL_SI91X_TLS_SERVER_CERTIFICATE = 6, ///< SL_SI91X_TLS_SERVER_CERTIFICATE + SL_SI91X_TLS_SERVER_PRIVATE_KEY = 7, ///< SL_SI91X_TLS_SERVER_PRIVATE_KEY + SL_SI91X_EAP_PRIVATE_KEY = 17, ///< SL_SI91X_EAP_PRIVATE_KEY + SL_SI91X_EAP_PUBLIC_KEY = 33, ///< SL_SI91X_EAP_PUBLIC_KEY + SL_SI91X_EAP_CA_CERTIFICATE = 49, ///< SL_SI91X_EAP_CA_CERTIFICATE +} sl_si91x_cert_type_t; + +/****************************************************** + * Function Declarations + ******************************************************/ +sl_status_t sl_si91x_set_credential(sl_net_credential_id_t id, + sl_net_credential_type_t type, + const void *credential, + uint32_t credential_length); +sl_status_t sl_si91x_get_credential(sl_net_credential_id_t id, + const sl_net_credential_type_t *type, + const void *credential, + const uint32_t *credential_length); +sl_status_t sl_si91x_delete_credential(sl_net_credential_id_t id, sl_net_credential_type_t type); + +static sl_si91x_cert_type_t convert_to_si91x_cert_type(sl_net_credential_id_t id, sl_net_credential_type_t type) +{ + switch (type) { + case SL_NET_SIGNING_CERTIFICATE: + if ((id == SL_NET_WIFI_EAP_SERVER_CREDENTIAL_ID) || (id == SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID)) { + return SL_SI91X_EAP_CA_CERTIFICATE; + } + if ((id & SL_NET_CREDENTIAL_GROUP_MASK) == SL_NET_TLS_SERVER_CREDENTIAL_START) { + return SL_SI91X_TLS_CA_CERTIFICATE; + } + break; + + case SL_NET_CERTIFICATE: + if (id == SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID) { + return SL_SI91X_EAP_CLIENT; + } + + switch (id & SL_NET_CREDENTIAL_GROUP_MASK) { + case SL_NET_TLS_CLIENT_CREDENTIAL_START: + return SL_SI91X_TLS_CLIENT; + case SL_NET_TLS_SERVER_CREDENTIAL_START: + return SL_SI91X_TLS_SERVER_CERTIFICATE; + default: + break; + } + break; + + case SL_NET_PUBLIC_KEY: + if (id == SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID) { + return SL_SI91X_EAP_PUBLIC_KEY; + } + break; + + case SL_NET_PRIVATE_KEY: + if (id == SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID) { + return SL_SI91X_EAP_PRIVATE_KEY; + } + switch (id & SL_NET_CREDENTIAL_GROUP_MASK) { + case SL_NET_TLS_CLIENT_CREDENTIAL_START: + return SL_SI91X_TLS_CLIENT_PRIVATE_KEY; + case SL_NET_TLS_SERVER_CREDENTIAL_START: + return SL_SI91X_TLS_SERVER_PRIVATE_KEY; + default: + break; + } + break; + case SL_NET_PACK_FILE: + if (id == SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID) { + return SL_SI91X_FAST_PAC_FILE; + } + break; + default: + return 0; + } + + return 0; +} + +static uint8_t get_certificate_index(sl_net_credential_id_t id) +{ + if ((id & SL_NET_CREDENTIAL_GROUP_MASK) != 0) { + return ((uint8_t)id & 0xFF); + } + switch (id) { + case SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID: + case SL_NET_WIFI_EAP_SERVER_CREDENTIAL_ID: + return 0; + + default: + break; + } + return -1; +} + +sl_status_t sl_si91x_set_credential(sl_net_credential_id_t id, + sl_net_credential_type_t type, + const void *credential, + uint32_t credential_length) +{ + sl_status_t status; + sl_si91x_cert_type_t cert_type = convert_to_si91x_cert_type(id, type); + uint8_t index = get_certificate_index(id); + + // Clear the certificate + status = sl_si91x_wifi_set_certificate_index((uint8_t)cert_type, index, NULL, 0); + + VERIFY_STATUS_AND_RETURN(status); + // Set the certificate + status = sl_si91x_wifi_set_certificate_index((uint8_t)cert_type, index, credential, credential_length); + + return status; +} + +sl_status_t sl_si91x_get_credential(sl_net_credential_id_t id, + const sl_net_credential_type_t *type, + const void *credential, + const uint32_t *credential_length) +{ + UNUSED_PARAMETER(id); + UNUSED_PARAMETER(type); + UNUSED_PARAMETER(credential); + UNUSED_PARAMETER(credential_length); + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_si91x_delete_credential(sl_net_credential_id_t id, sl_net_credential_type_t type) +{ + sl_si91x_cert_type_t cert_type = convert_to_si91x_cert_type(id, type); + uint8_t index = get_certificate_index(id); + + // Clear the certificate + return sl_si91x_wifi_set_certificate_index((uint8_t)cert_type, index, NULL, 0); +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_internal_stack.c b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_internal_stack.c new file mode 100644 index 000000000..b6cc932bc --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_internal_stack.c @@ -0,0 +1,257 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_status.h" +#include "sl_utility.h" +#include "sl_net.h" +#include "sl_wifi.h" +#include "sl_net_wifi_types.h" +#include "sl_net_si91x.h" +#include "sl_si91x_host_interface.h" +#include "sl_si91x_driver.h" +#include "sl_rsi_utility.h" +#include "sl_net_rsi_utility.h" +#include "sl_si91x_core_utilities.h" +#include +#include + +// Define a bit mask for DHCP unicast offer +#define SL_SI91X_DHCP_UNICAST_OFFER ((uint32_t)1U << 3) + +// Global variable indicating if the device is initialized +extern bool device_initialized; + +sl_status_t sli_si91x_configure_ip_address(sl_net_ip_configuration_t *ip_config, + uint8_t virtual_ap_id, + const uint32_t timeout) +{ + sl_status_t status = SL_STATUS_INVALID_PARAMETER; + sl_si91x_req_ipv4_params_t ip_req = { 0 }; + sl_si91x_req_ipv6_params_t ipv6_request = { 0 }; + sl_si91x_packet_t *packet; + sl_wifi_buffer_t *buffer = NULL; + uint32_t wait_time = (timeout ? SL_SI91X_WAIT_FOR_RESPONSE(timeout) : SL_SI91X_RETURN_IMMEDIATELY); + + // Check if the device is initialized + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + // Check for NULL ip_config pointer + if (NULL == ip_config) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check if timeout is 0 + if (0 == timeout) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (SL_IPV4 & ip_config->type) { + // Initialize the IPv4 request structure and fill fields accordingly + memset(&ip_req, 0, sizeof(ip_req)); + ip_req.vap_id = virtual_ap_id; + + if (SL_IP_MANAGEMENT_STATIC_IP == ip_config->mode) { + ip_req.dhcp_mode = SL_SI91X_STATIC; + // Fill IP address + memcpy(ip_req.ipaddress, ip_config->ip.v4.ip_address.bytes, 4); + + // Fill network mask + memcpy(ip_req.netmask, ip_config->ip.v4.netmask.bytes, 4); + + // Fill gateway + memcpy(ip_req.gateway, ip_config->ip.v4.gateway.bytes, 4); + } else { + ip_req.dhcp_mode = (SL_SI91X_DHCP | SL_SI91X_DHCP_UNICAST_OFFER); + } + + if (NULL != ip_config->host_name) { + // Enable DHCP hostname option and copy the hostname + ip_req.dhcp_mode |= SL_SI91X_DHCP_HOSTNAME; + memcpy(ip_req.hostname, ip_config->host_name, sizeof(ip_req.hostname)); + } + + ip_req.dhcp_discover_rtr_interval_min = ip_config->dhcp_config.min_discover_retry_interval; + ip_req.dhcp_request_rtr_interval_min = ip_config->dhcp_config.min_request_retry_interval; + ip_req.dhcp_discover_rtr_interval_max = ip_config->dhcp_config.max_discover_retry_interval; + ip_req.dhcp_request_rtr_interval_max = ip_config->dhcp_config.max_request_retry_interval; + ip_req.dhcp_discover_max_retries = ip_config->dhcp_config.min_discover_retries; + ip_req.dhcp_request_max_retries = ip_config->dhcp_config.max_request_retries; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_IPCONFV4, + SI91X_NETWORK_CMD, + &ip_req, + sizeof(sl_si91x_req_ipv4_params_t), + wait_time, + NULL, + &buffer); + + // Check if the command failed and free the buffer if it was allocated + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + + // Verify the status and return it + VERIFY_STATUS_AND_RETURN(status); + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + if (SL_IP_MANAGEMENT_DHCP == ip_config->mode) { + // Extract DHCP response data if in DHCP mode + const sl_si91x_rsp_ipv4_params_t *response_data = (sl_si91x_rsp_ipv4_params_t *)packet->data; + memcpy(ip_config->ip.v4.ip_address.bytes, (const uint8_t *)response_data->ipaddr, sizeof(sl_ipv4_address_t)); + memcpy(ip_config->ip.v4.netmask.bytes, (const uint8_t *)response_data->netmask, sizeof(sl_ipv4_address_t)); + memcpy(ip_config->ip.v4.gateway.bytes, (const uint8_t *)response_data->gateway, sizeof(sl_ipv4_address_t)); + } + + // Free the buffer and return success status + sl_si91x_host_free_buffer(buffer); + } + + if (SL_IPV6 & ip_config->type) { + // Initialize the IPv6 request structure + memset(&ipv6_request, 0, sizeof(ipv6_request)); + uint16_t prefix_length = 64; + memcpy(&ipv6_request.prefixLength, &prefix_length, 2); + ipv6_request.vap_id = virtual_ap_id; + + if (SL_IP_MANAGEMENT_STATIC_IP == ip_config->mode) { + // Set IPv6 mode to static + memcpy(&ipv6_request.ipaddr6, ip_config->ip.v6.global_address.bytes, SL_IPV6_ADDRESS_LENGTH); + memcpy(&ipv6_request.gateway6, ip_config->ip.v6.gateway.bytes, SL_IPV6_ADDRESS_LENGTH); + ipv6_request.mode[0] = SL_SI91X_STATIC; + } else { + // Set IPv6 mode to dynamic + ipv6_request.mode[0] = (SL_SI91X_DHCP | SL_SI91X_DHCP_UNICAST_OFFER); + } + + // Send the IPv6 configuration request to SI91X driver + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_IPCONFV6, + SI91X_NETWORK_CMD, + &ipv6_request, + sizeof(sl_si91x_req_ipv6_params_t), + wait_time, + NULL, + &buffer); + + // Check if the command failed and free the buffer if it was allocated + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + + VERIFY_STATUS_AND_RETURN(status); + + // Extract the IPv6 configuration response data + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + const sl_si91x_rsp_ipv6_params_t *ipv6_response = (sl_si91x_rsp_ipv6_params_t *)packet->data; + + // Copy the IPv6 addresses to the address structure + memcpy(&ip_config->ip.v6.link_local_address, + (const uint8_t *)ipv6_response->link_local_address, + sizeof(ipv6_response->link_local_address)); + memcpy(&ip_config->ip.v6.global_address, + (const uint8_t *)ipv6_response->global_address, + sizeof(ipv6_response->global_address)); + memcpy(&ip_config->ip.v6.gateway, + (const uint8_t *)ipv6_response->gateway_address, + sizeof(ipv6_response->gateway_address)); + + // Free the buffer and return success status + sl_si91x_host_free_buffer(buffer); + } + + return status; +} + +sl_status_t sl_si91x_ota_firmware_upgradation(sl_ip_address_t server_ip, + uint16_t server_port, + uint16_t chunk_number, + uint16_t timeout, + uint16_t tcp_retry_count, + bool asynchronous) +{ + sl_wifi_buffer_t *buffer = NULL; + sl_status_t status = SL_STATUS_FAIL; + sl_si91x_wait_period_t wait_period = SL_SI91X_RETURN_IMMEDIATELY; + + // Initialize the OTA firmware update request structure + sl_si91x_ota_firmware_update_request_t otaf_fwup = { 0 }; + + // Determine the wait period based on the 'asynchronous' flag + if (asynchronous == false) { + wait_period = SL_SI91X_WAIT_FOR_OTAF_RESPONSE; + } + + // Check IP version + if (server_ip.type == SL_IPV4) { + // Fill the IP version + otaf_fwup.ip_version = SL_IPV4; + memcpy(otaf_fwup.server_ip_address.ipv4_address, server_ip.ip.v4.bytes, SL_IPV4_ADDRESS_LENGTH); + } else if (server_ip.type == SL_IPV6) { + otaf_fwup.ip_version = SL_IPV6; + memcpy(otaf_fwup.server_ip_address.ipv6_address, server_ip.ip.v6.bytes, SL_IPV6_ADDRESS_LENGTH); + } else { + return SL_STATUS_INVALID_PARAMETER; + } + + // Fill server port number + memcpy(otaf_fwup.server_port, &server_port, sizeof(server_port)); + + // Fill chunk number + memcpy(otaf_fwup.chunk_number, &chunk_number, sizeof(otaf_fwup.chunk_number)); + + // Fill timeout + memcpy(otaf_fwup.timeout, &timeout, sizeof(otaf_fwup.timeout)); + + // Fill TCP retry count + memcpy(otaf_fwup.retry_count, &tcp_retry_count, sizeof(otaf_fwup.retry_count)); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_OTA_FWUP, + SI91X_NETWORK_CMD, + &otaf_fwup, + sizeof(sl_si91x_ota_firmware_update_request_t), + wait_period, + NULL, + &buffer); + + // Check if the command was synchronous and free the buffer if it was allocated + if (asynchronous == false) { + if (status != SL_STATUS_OK && buffer != NULL) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + } + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_si91x_configure_ip_address(sl_net_ip_configuration_t *address, uint8_t virtual_ap_id) +{ + return sli_si91x_configure_ip_address(address, virtual_ap_id, 150000); +} \ No newline at end of file diff --git a/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_bsd_utility.h b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_bsd_utility.h new file mode 100644 index 000000000..e8a2bd551 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_bsd_utility.h @@ -0,0 +1,49 @@ +/***************************************************************************/ /** + * @file + * @brief sl_bsd_utility.h + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include + +/** + * @addtogroup SI91X_SOCKET_FUNCTIONS + * @{ + */ + +/***************************************************************************/ /** + * @brief + * Retrieves the Maximum Segment Size (MSS) for a specific socket. The MSS is the largest amount of data, specified in bytes, that a computer or communications device can handle in a single, unfragmented piece. + * @param[in] socketIndex + * The index of the socket for which the MSS is to be retrieved. This is an integer value that uniquely identifies the socket. + * @return + * Returns an int16_t value representing the MSS of the specified socket in bytes. + ******************************************************************************/ +int16_t sl_si91x_get_socket_mss(int32_t socketIndex); + +/** @} */ diff --git a/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_callback_framework.h b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_callback_framework.h new file mode 100644 index 000000000..2ad8479c3 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_callback_framework.h @@ -0,0 +1,50 @@ +/***************************************************************************/ /** + * @file sl_si91x_socket_callback_framework.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_status.h" +#include "sl_si91x_types.h" + +typedef struct { + void *user_context; + void *socket_context; + int32_t socket_id; //socket_id to update in command trace of bus thread. +} sl_si91x_socket_context_t; + +/** + * This is internal event handler to handle all events of sockets[Including BSD] + * @param status sl_status of rx_packet frame status + * @param sdk_context sl_si91x_socket_context_t that was sent at the time sending the request. + * @param rx_packet Firmware response. + * @return + */ +sl_status_t si91x_socket_event_handler(sl_status_t status, + sl_si91x_socket_context_t *sdk_context, + sl_si91x_packet_t *rx_packet); diff --git a/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_constants.h b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_constants.h new file mode 100644 index 000000000..d15183256 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_constants.h @@ -0,0 +1,185 @@ +/******************************************************************************** + * @file sl_si91x_socket_constants.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include +#include "cmsis_os2.h" + +#ifndef BIT +#define BIT(a) ((uint32_t)1U << a) +#endif + +/****************************************************** + * Socket Configurations + ******************************************************/ +#define SI91X_NO_ERROR 0 // This is returned by socket functions after successful execution +#define SI91X_UNDEFINED_ERROR \ + 0 // This value is set to errno global variable when a socket API failed due to unknown error. + +#define NUMBER_OF_SOCKETS 20 + +#define SI91X_HOST_WAIT_FOR_SELECT_RSP 1000 + +#define TCP_RX_WINDOW_SIZE 10 + +#define DEFAULT_STREAM_MSS_SIZE_IPV4 1460 +#define DEFAULT_DATAGRAM_MSS_SIZE_IPV4 1472 + +#define DEFAULT_STREAM_MSS_SIZE_IPV6 1440 +#define DEFAULT_DATAGRAM_MSS_SIZE_IPV6 1452 + +#define MAX_TCP_RETRY_COUNT 10 +#define DEFAULT_TCP_KEEP_ALIVE_TIME 1200 + +#define SI91X_CERT_INDEX_0 0 +#define SI91X_CERT_INDEX_1 1 +#define SI91X_CERT_INDEX_2 2 + +#define SL_SI91X_TLS_EXTENSION_SNI_TYPE 1 ///< TLS extension for SNI +#define SL_SI91X_TLS_EXTENSION_ALPN_TYPE 2 ///< TLS extension for ALPN + +#define SI91X_SOCKET_TCP_CLIENT 0x0000 +#define SI91X_SOCKET_UDP_CLIENT 0x0001 +#define SI91X_SOCKET_TCP_SERVER 0x0002 +#define SI91X_SOCKET_LUDP 0x0004 + +#define SI91X_SOCKET_FEAT_SSL BIT(0) // SAPI maps both SSL and synchronous to BIT(0) +#define SI91X_SOCKET_FEAT_SYNCHRONOUS BIT(0) +#define SI91X_SOCKET_FEAT_LTCP_ACCEPT BIT(1) +#define SI91X_WEBSOCKET_FEAT BIT(1) +#define SI91X_SOCKET_FEAT_TCP_ACK_INDICATION BIT(2) +#define SI91X_SOCKET_FEAT_TCP_RX_WINDOW BIT(4) +#define SI91X_SOCKET_FEAT_CERT_INDEX BIT(5) +#define SI91X_HIGH_PERFORMANCE_SOCKET BIT(7) + +#define MAX_RETRANSMISSION_TIME_VALUE 32 + +/** + * @addtogroup SI91X_SOCKET_OPTION_NAME SiWx91x Socket Option Name + * @ingroup SI91X_SOCKET_FUNCTIONS + * @{ + */ +#define SL_SI91X_SO_RCVTIME 20 ///< Enable receive timeout +#define SL_SI91X_SO_TCP_KEEPALIVE 26 ///< To configure the TCP keep alive +#define SL_SI91X_SO_HIGH_PERFORMANCE_SOCKET 38 ///< To configure the high performance socket +#define SL_SI91X_SO_CERT_INDEX 46 ///< To enable set certificate index +#define SL_SI91X_SO_SSL_ENABLE 37 ///< To enable SSL +#define SL_SI91X_SO_SSL_V_1_0_ENABLE 42 ///< To enable SSL 1.0 +#define SL_SI91X_SO_SSL_V_1_1_ENABLE 43 ///< To enable SSL 1.1 +#define SL_SI91X_SO_SSL_V_1_2_ENABLE 44 ///< To enable SSL 1.2 +#define SL_SI91x_SO_TCP_ACK_INDICATION 45 ///< To enable TCP ACK indication feature +#define SL_SI91X_SO_MAX_RETRANSMISSION_TIMEOUT_VALUE 48 ///< to configure max retransmission timeout value +#define SL_SI91X_IP_TOS 48 ///< To configure TOS +#define SL_SI91X_SO_SSL_V_1_3_ENABLE 49 ///< To enable SSL 1.3 +#define SL_SI91X_SO_MAXRETRY 24 ///< To enable max TCP retry count +#define SL_SI91X_SO_MSS 40 ///< To configure the TCP MSS +#define SL_SI91X_SO_SOCK_VAP_ID 25 ///< To configure the socket VAP ID +#define SL_SI91X_SO_TLS_SNI 47 ///< To configure the TLS SNI extension +#define SL_SI91X_SO_TLS_ALPN 50 ///< To configure the TLS ALPN extension +/** @} */ + +#define SHUTDOWN_BY_ID 0 +#define SHUTDOWN_BY_PORT 1 +/****************************************************** + * SSL features + ******************************************************/ +//Release 2.0 default ciphers +#define SSL_DEFAULT_CIPHERS \ + (BIT_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 | BIT_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 \ + | BIT_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 | BIT_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 \ + | BIT_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 | BIT_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 \ + | BIT_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA | BIT_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA \ + | BIT_TLS_DHE_RSA_WITH_AES_256_CBC_SHA | BIT_TLS_DHE_RSA_WITH_AES_128_CBC_SHA \ + | BIT_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA | BIT_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA \ + | BIT_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA | BIT_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA) + +//Release 2.0 all configurable ciphers +#define SSL_RELEASE_2_0_ALL_CIPHERS \ + (SSL_DEFAULT_CIPHERS | BIT_TLS_RSA_WITH_AES_256_CBC_SHA256 | BIT_TLS_RSA_WITH_AES_128_CBC_SHA256 \ + | BIT_TLS_RSA_WITH_AES_256_CBC_SHA | BIT_TLS_RSA_WITH_AES_128_CBC_SHA | BIT_TLS_RSA_WITH_AES_128_CCM_8 \ + | BIT_TLS_RSA_WITH_AES_256_CCM_8 | BIT_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 | BIT_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 \ + | BIT_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 | BIT_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 \ + | BIT_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 | BIT_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 \ + | BIT_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256) + +#if defined(SLI_SI917) || defined(SLI_SI915) +#define SSL_EXT_CIPHERS SSL_TLSV1_3_ALL_CIPHERS +#endif + +#define SSL_ALL_CIPHERS SSL_RELEASE_2_0_ALL_CIPHERS + +//TLSv1.3 configurable ciphers +#if defined(SLI_SI917) || defined(SLI_SI915) +#define SSL_TLSV1_3_ALL_CIPHERS \ + (BIT_TLS13_AES_128_GCM_SHA256 | BIT_TLS13_AES_256_GCM_SHA384 | BIT_TLS13_CHACHA20_POLY1305_SHA256 \ + | BIT_TLS13_AES_128_CCM_SHA256 | BIT_TLS13_AES_128_CCM_8_SHA256) +#endif + +#define BIT_TLS_RSA_WITH_AES_256_CBC_SHA256 BIT(0) +#define BIT_TLS_RSA_WITH_AES_128_CBC_SHA256 BIT(1) +#define BIT_TLS_RSA_WITH_AES_256_CBC_SHA BIT(2) +#define BIT_TLS_RSA_WITH_AES_128_CBC_SHA BIT(3) +#define BIT_TLS_RSA_WITH_AES_128_CCM_8 BIT(4) +#define BIT_TLS_RSA_WITH_AES_256_CCM_8 BIT(5) +#define BIT_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 BIT(6) +#define BIT_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 BIT(7) +#define BIT_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 BIT(8) +#define BIT_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 BIT(9) +#define BIT_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 BIT(10) +#define BIT_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 BIT(11) +#define BIT_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 BIT(12) +#define BIT_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 BIT(13) +#define BIT_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 BIT(14) +#define BIT_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 BIT(15) +#define BIT_TLS_DHE_RSA_WITH_AES_256_CBC_SHA BIT(16) +#define BIT_TLS_DHE_RSA_WITH_AES_128_CBC_SHA BIT(17) +#define BIT_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 BIT(18) +#define BIT_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 BIT(19) +#define BIT_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA BIT(20) +#define BIT_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA BIT(21) +#define BIT_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 BIT(22) +#define BIT_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 BIT(23) +#define BIT_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA BIT(24) +#define BIT_TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA BIT(25) +#define BIT_TLS_ECDHE_RSA_WITH_3DES_EDE_CBC_SHA BIT(26) +#define BIT_TLS_ECDHE_ECDSA_WITH_3DES_EDE_CBC_SHA BIT(27) +#define BIT_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 BIT(28) +#define BIT_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 BIT(29) +#define BIT_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 BIT(30) +#define SSL_NEW_CIPHERS BIT(31) + +// TLSv1.3 supported ciphers +#if defined(SLI_SI917) || defined(SLI_SI915) +#define BIT_TLS13_AES_128_GCM_SHA256 BIT(0) +#define BIT_TLS13_AES_256_GCM_SHA384 BIT(1) +#define BIT_TLS13_CHACHA20_POLY1305_SHA256 BIT(2) +#define BIT_TLS13_AES_128_CCM_SHA256 BIT(3) +#define BIT_TLS13_AES_128_CCM_8_SHA256 BIT(4) +#endif diff --git a/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_types.h b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_types.h new file mode 100644 index 000000000..f4a809592 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_types.h @@ -0,0 +1,263 @@ +/******************************************************************************** + * @file sl_si91x_socket_types.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include +#include + +#include "sl_si91x_types.h" +#include "cmsis_os2.h" // CMSIS RTOS2 +#include "sl_si91x_protocol_types.h" + +/** + * @addtogroup SI91X_SOCKET_FUNCTIONS + * @{ + */ +/** + * @brief Structure for socket metadata associated with read event. + * + * @details + * The structure holds the metadata information for the socket's read event. + * It includes the following details such as: IP version, socket ID, length of data received, + * offset within the buffer, destination port, and the IP address of the sender device. + * The IP address can be either IPv4 or IPv6, determined by the + * `ip_version` field. + */ +typedef struct { + uint16_t + ip_version; ///< Two bytes for the IP version of the IP address, four bytes for the IPv4, and six bytes for the IPv6. + + uint16_t socket_id; ///< The socket number associated with the read event is two bytes. + + uint32_t length; ///< Four bytes. Length of received data. + + uint16_t offset; ///< Two bytes. Offset data from the start of the buffer. + + uint16_t dest_port; ///< Two bytes. Port number of the device which sends data to the destination. + + union { + uint8_t ipv4_address[4]; ///< Four bytes. IPv4 address of the device which sends data. Used if ip_version is four. + + uint8_t ipv6_address[16]; ///< 16 bytes. IPv6 address of the device which sends data. Used if ip_version is six. + } dest_ip_addr; ///< Union for IPv4 or IPv6 address, depending on ip_version. +} sl_si91x_socket_metadata_t; + +/** + * @typedef sl_si91x_socket_receive_data_callback_t + * @brief Callback function reads asynchronous data from the socket. + * + * @details + * The callback function reads asynchronous data from the socket when the sl_si91x_socket_async + * API is registered and called. The callback provides the following details: + * socket ID, pointer to the buffer which contains receiver data, size of the buffer, + * and metadata of the receiver packet (such as IP address, and port number). + * + * + * @param socket + * Socket ID. + * + * @param buffer + * Pointer to the buffer which stores the receiver data. + * + * @param length + * Buffer size. + * + * @param firmware_socket_response + * Pointer to sl_si91x_socket_metadata_t structure contains receiver packet metadata information. + * The metadata information consists of IP address (either, Ipv4 or IPV6), and port number. + * + * @return + * N/A + */ +typedef void (*sl_si91x_socket_receive_data_callback_t)(uint32_t socket, + uint8_t *buffer, + uint32_t length, + const sl_si91x_socket_metadata_t *firmware_socket_response); + +/** + * @typedef sl_si91x_socket_accept_callback_t + * @brief Callback functions for new asynchronous accepted connection. + * + * @details + * The callback provides paramenters for new accepted connection when the sl_si91x_accept_async API is registered and called. + * The callback provides the following details: socket ID of the accepted connection, address of remoter peer, + * and IP version of connection. + * + * @param socket + * Socket ID of the accepted connection. + * + * @param addr + * Pointer to `struct sockaddr` contains remote peer address. + * + * @param ip_version + * IP version of the connection (for example, four bytes for IPv4, and six bytes for IPv6). + * + * @return + * N/A + */ +typedef void (*sl_si91x_socket_accept_callback_t)(int32_t socket, struct sockaddr *addr, uint8_t ip_version); + +/** + * @typedef sl_si91x_socket_data_transfer_complete_handler_t + * @brief Callback function indicates data transfer status. + * + * @details + * The callback indicates the data transfer completion status when either of the sl_si91x_send_async or sl_si91x_sendto_async API is registered and called. + * The callback provides the socket ID, and the number of bytes that are successfully transfer. + * + * @param socket + * Socket ID. + * + * @param length + * Number of bytes transferred. + * + * @return + * N/A + */ +typedef void (*sl_si91x_socket_data_transfer_complete_handler_t)(int32_t socket, uint16_t length); + +/** + * @typedef sl_si91x_socket_select_callback_t + * @brief Callback function indicates asynchronous select request result. + * + * @details + * The callback indicates asynchronous response reaches the select request when the sl_si91x_select API is registered and called. + * The callback provides the following details: file descriptor sets for read, write, and exception conditions, and status of the selected request. + * + * @param fd_read + * File descriptor pointer sets for read operations. + * + * @param fd_write + * File descriptor pointer sets for write operations. + * + * @param fd_except + * File descriptor pointer sets for exception condition. + * + * @param status + * Select request status. + * + * @return + * N/A + */ +typedef void (*sl_si91x_socket_select_callback_t)(sl_si91x_fd_set *fd_read, sl_si91x_fd_set *fd_write, sl_si91x_fd_set *fd_except, int32_t status); + +/** + * @typedef sl_si91x_socket_remote_termination_callback_t + * @brief Callback function indicates termination of the remote socket. + * + * @details + * The callback function notifies on the termination of the remote socket when the sl_si91x_set_remote_termination_callback API is registered and called. + * The callback provides the following details: socket ID, remote socket port number, and number of bytes sent before termination of the remote socket. + * + * @param socket + * Socket ID. + * + * @param port + * Remote socket port number. + * + * @param bytes_sent + * Number of bytes sent before termination. + * + * @return + * The callback does not returns value. + */ +typedef void (*sl_si91x_socket_remote_termination_callback_t)(int socket, uint16_t port, uint32_t bytes_sent); + +/** @} */ + +/// Internal si91x BSD socket status +typedef enum { + RESET = 0, // State of unallocated socket. + INITIALIZED, // Socket attains this state when socket() has been executed successfully. + BOUND, // Socket attains this state when bind() has been executed successfully. + LISTEN, // (TCP ONLY STATE) Socket attains this state when listen() has been executed successfully. + UDP_UNCONNECTED_READY, // (UDP ONLY STATE) Socket attains this state when sendto() or recvfrom() has been executed successfully prior connect. + CONNECTED, // Socket attains this state when connect() has been executed successfully. + DISCONNECTED // Socket attains this state when underlying connection is lost +} sli_si91x_bsd_socket_state_t; + +#define SI91X_MAX_SIZE_OF_EXTENSION_DATA 256 + +#pragma pack() +/// Internal si91x TLS extensions +typedef struct { + uint8_t buffer[SI91X_MAX_SIZE_OF_EXTENSION_DATA]; ///< Buffer + uint16_t total_extensions; ///< Total extensions + uint16_t current_size_of_extensions; ///< Current size of extensions +} sli_si91x_tls_extensions_t; + +/// Structure to hold WebSocket host and resource information +typedef struct { + uint8_t host_length; ///< Length of WebSocket host name + uint8_t resource_length; ///< Length of WebSocket resource name + uint8_t websocket_data[]; ///< WebSocket resource name and host name +} sli_si91x_websocket_info_t; + +#pragma pack() + +/// Internal si91x socket handle +typedef struct { + int32_t id; ///< Socket ID + int32_t type; ///< Socket type + int32_t index; ///< Socket index + int role; ///< Socket role + int32_t protocol; ///< Protocol + uint16_t tcp_keepalive_initial_time; ///< TCP keepalive intial time + uint8_t max_tcp_retries; ///< MAX TCOP retries + uint16_t read_timeout; ///< Read timeout + uint8_t certificate_index; ///< Certificate Index + uint8_t vap_id; ///< Virtual AP ID + uint16_t mss; ///< Maximum segment size (MSS) value + struct sockaddr_in6 local_address; ///< Using sockaddr_in6 to hold either IPV4 or IPV6. + struct sockaddr_in6 remote_address; ///< Using sockaddr_in6 to hold either IPV4 or IPV6. + sli_si91x_bsd_socket_state_t state; ///< BSD socket state (used for internal tracking) + sli_si91x_tls_extensions_t tls_extensions; ///< TLS Extension + bool is_waiting_on_ack; ///< Boolean flag to check if socket is waiting for an ack. +#if defined(SLI_SI917) || defined(SLI_SI915) + uint32_t ssl_bitmap; ///< SSL bitmap + uint32_t max_retransmission_timeout_value; ///< Max retransmission timeout value + uint32_t tos; ///< TOS +#else + uint8_t ssl_bitmap; ///< SSL Bitmap +#endif + uint8_t opcode; ///< Opcode used in websocket + sli_si91x_websocket_info_t *websocket_info; ///< Pointer to WebSocket info + sl_si91x_socket_receive_data_callback_t recv_data_callback; ///< Receive data callback + sl_si91x_socket_data_transfer_complete_handler_t data_transfer_callback; ///< Data transfer callback + sl_si91x_socket_accept_callback_t user_accept_callback; ///< Async Accept callback + osEventFlagsId_t socket_events; ///< Event Flags for sockets + int32_t client_id; ///< Client Socket Id for accept + uint8_t socket_bitmap; ///< Socket Bitmap + uint8_t data_buffer_count; ///< Number of queued data buffers allocated by this socket + uint8_t data_buffer_limit; ///< Maximum number of queued data buffers permitted for this socket + sli_si91x_command_queue_t command_queue; ///< Command queue + sl_si91x_buffer_queue_t tx_data_queue; ///< Transmit data queue + sl_si91x_buffer_queue_t rx_data_queue; ///< Receive data queue +} sli_si91x_socket_t; diff --git a/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_utility.h b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_utility.h new file mode 100644 index 000000000..abde31aa8 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/socket/inc/sl_si91x_socket_utility.h @@ -0,0 +1,272 @@ +/******************************************************************************** + * @file sl_si91x_socket_utility.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_si91x_types.h" +#include "sl_si91x_socket_types.h" +#include "sl_si91x_protocol_types.h" +#include "sl_si91x_socket_constants.h" +#include "errno.h" +#include + +#define SET_ERROR_AND_RETURN(error) \ + do { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_ERROR_STATUS(ERROR_TAG, error); \ + } \ + errno = error; \ + return -1; \ + } while (0) + +#define SET_ERRNO_AND_RETURN_IF_TRUE(condition, errno_value) \ + do { \ + if (condition) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_ERROR_STATUS(ERROR_TAG, errno_value); \ + } \ + errno = errno_value; \ + return -1; \ + } \ + } while (0) + +#define SOCKET_VERIFY_STATUS_AND_RETURN(status, expected_status, errno_value) \ + do { \ + if (status != expected_status) { \ + if (PRINT_ERROR_LOGS) { \ + PRINT_ERROR_STATUS(ERROR_TAG, errno_value); \ + } \ + errno = errno_value; \ + return -1; \ + } \ + } while (0) + +#define SLI_SI91X_NULL_SAFE_FD_ZERO(fd_set) \ + do { \ + if (NULL != fd_set) { \ + SL_SI91X_FD_ZERO(fd_set); \ + } \ + } while (0) + +#define GET_SAFE_MEMCPY_LENGTH(destination_size, source_size) \ + source_size > destination_size ? destination_size : source_size + +extern sli_si91x_socket_t *sli_si91x_sockets[NUMBER_OF_SOCKETS]; + +sl_status_t sli_si91x_socket_init(uint8_t max_select_count); + +sl_status_t sli_si91x_socket_deinit(void); + +sl_status_t sli_si91x_vap_shutdown(uint8_t vap_id); + +/** + * @addtogroup SOCKET_CONFIGURATION_FUNCTION + * @{ + */ +/** + * @brief SiWx91x Socket Configuration + * + * The structure defines the configuration parameters for SiWx91x sockets. + * It includes settings for the total number of sockets, TCP and UDP socket + * configurations, and performance-related parameters. + */ +typedef struct { + uint8_t total_sockets; ///< Total number of sockets (that includes BSD, IoT, Si91x) + + uint8_t total_tcp_sockets; ///< Total number of TCP sockets + + uint8_t total_udp_sockets; ///< Total number of UDP sockets + + uint8_t tcp_tx_only_sockets; ///< Number of TCP sockets intended for transmission (TX) + + uint8_t tcp_rx_only_sockets; ///< Number of TCP sockets intended for reception (RX) + + uint8_t udp_tx_only_sockets; ///< Number of UDP sockets intended for transmission (TX) + + uint8_t udp_rx_only_sockets; ///< Number of UDP sockets intended for reception (RX) + + uint8_t tcp_rx_high_performance_sockets; ///< Total number of high-performance TCP RX sockets + + uint8_t + tcp_rx_window_size_cap; ///< TCP RX window size cap, scales window size linearly (TCP MSS * TCP_RX_WINDOW_SIZE_CAP) + + uint8_t tcp_rx_window_div_factor; ///< TCP RX window division factor, increases ACK frequency for asynchronous sockets +} sl_si91x_socket_config_t; + +/// SiWx91x specific socket type length value +typedef struct { + uint16_t type; ///< Socket type + uint16_t length; ///< Data length + uint8_t value[]; ///< Data +} sl_si91x_socket_type_length_value_t; + +/** @} */ + +/** + * @addtogroup SOCKET_CONFIGURATION_FUNCTION + * @{ + */ + +/** + * @brief + * Configures SiWx91x specific socket settings. + * + * @details + * This function sets up the socket configuration specific to the SiWx91x. + * It must be called before invoking @ref sl_si91x_socket_async. + * The configuration includes setting parameters such as socket type, + * protocol, and other options specific to the SiWx91x series. + * + * @pre Pre-conditions: + * - Ensure that the necessary initialization for the SiWx91x module has been completed. + * - This API is called before calling @ref sl_si91x_socket_async. + * + * @param[in] socket_config + * Socket configuration of type @ref sl_si91x_socket_config_t. + * + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * + ******************************************************************************/ +sl_status_t sl_si91x_config_socket(sl_si91x_socket_config_t socket_config); + +/** @} */ + +/** + * A internal function to reset the socket. + * @param socket socket FD which needs to be reset. + */ +void reset_socket_state(int socket); + +/** + * A internal function to get sl_si91x_socket structure based on socket FD sent + * @param socket + * Socket FD whose structure is required. + * @param index + * Socket FD index number. + * @return + * sl_si91x_socket or NULL in case of invalid FD. + */ +void get_free_socket(sli_si91x_socket_t **socket, int *index); + +/** + * A internal function to get free socket. + * @param socket_id + * Socket ID. + */ +sli_si91x_socket_t *get_si91x_socket(int32_t socket_id); + +sl_status_t sli_si91x_add_tls_extension(sli_si91x_tls_extensions_t *socket_tls_extensions, + const sl_si91x_socket_type_length_value_t *tls_extension); + +sl_status_t create_and_send_socket_request(int socketIdIndex, int type, const int *backlog); + +int sli_si91x_socket(int family, int type, int protocol, sl_si91x_socket_receive_data_callback_t callback); + +int sli_si91x_shutdown(int socket, int how); + +int sli_si91x_connect(int socket, const struct sockaddr *addr, socklen_t addr_len); + +int sli_si91x_bind(int socket, const struct sockaddr *addr, socklen_t addr_len); + +int sli_si91x_accept(int socket, + struct sockaddr *addr, + socklen_t *addr_len, + sl_si91x_socket_accept_callback_t callback); + +int sli_si91x_select(int nfds, + sl_si91x_fd_set *readfds, + sl_si91x_fd_set *writefds, + sl_si91x_fd_set *exceptfds, + const struct timeval *timeout, + sl_si91x_socket_select_callback_t callback); + +void handle_accept_response(sli_si91x_socket_t *si91x_client_socket, const sl_si91x_rsp_ltcp_est_t *accept_response); + +int handle_select_response(const sl_si91x_socket_select_rsp_t *response, + sl_si91x_fd_set *readfds, + sl_si91x_fd_set *writefds, + sl_si91x_fd_set *exception_fd); + +uint8_t sli_si91x_socket_identification_function_based_on_socketid(sl_wifi_buffer_t *buffer, void *user_data); + +void set_select_callback(sl_si91x_socket_select_callback_t callback); + +void sli_si91x_set_accept_callback(sli_si91x_socket_t *server_socket, + sl_si91x_socket_accept_callback_t callback, + int32_t client_socket_id); + +void sli_si91x_set_remote_socket_termination_callback(sl_si91x_socket_remote_termination_callback_t callback); + +sl_status_t sli_si91x_send_socket_command(sli_si91x_socket_t *socket, + uint32_t command, + const void *data, + uint32_t data_length, + uint32_t wait_period, + sl_wifi_buffer_t **response_buffer); + +int sli_si91x_get_socket_id(sl_si91x_packet_t *packet); + +/** + * A internal function to find a socket with the matching ID and not in the exlcuded_state + * @param socket_id Socket ID + * @param excluded_state The socket state that the socket must not be + * @param role Socket role + */ +sli_si91x_socket_t *sli_si91x_get_socket_from_id(int socket_id, + sli_si91x_bsd_socket_state_t excluded_state, + int16_t role); + +sl_status_t sli_si91x_send_socket_data(sli_si91x_socket_t *si91x_socket, + const sli_si91x_socket_send_request_t *request, + const void *data); +int32_t sli_get_socket_command_from_host_packet(sl_wifi_buffer_t *buffer); + +void sli_si91x_set_socket_event(uint32_t event_mask); + +sl_status_t sli_si91x_flush_select_request_table(uint16_t error_code); +static inline void SL_SI91X_FD_CLR(unsigned int n, sl_si91x_fd_set *p) +{ + p->__fds_bits &= ~(1U << n); +} + +static inline void SL_SI91X_FD_SET(unsigned int n, sl_si91x_fd_set *p) +{ + p->__fds_bits |= 1U << n; +} + +static inline bool SL_SI91X_FD_ISSET(unsigned int n, sl_si91x_fd_set *p) +{ + return p->__fds_bits & (1U << n); +} + +static inline void SL_SI91X_FD_ZERO(sl_si91x_fd_set *p) +{ + p->__fds_bits = 0; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/socket/src/sl_si91x_socket_utility.c b/wiseconnect/components/device/silabs/si91x/wireless/socket/src/sl_si91x_socket_utility.c new file mode 100644 index 000000000..50e16d906 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/socket/src/sl_si91x_socket_utility.c @@ -0,0 +1,1510 @@ +/***************************************************************************/ /** + * @file sl_si91x_socket_utility.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_si91x_socket_utility.h" +#include "sl_si91x_socket_types.h" +#include "sl_si91x_socket_callback_framework.h" +#include "sl_status.h" +#include "sl_constants.h" +#include "sl_si91x_driver.h" +#include "sl_si91x_protocol_types.h" +#include "sl_si91x_socket_constants.h" +#include "sl_si91x_host_interface.h" +#include "sl_si91x_core_utilities.h" +#include "sl_rsi_utility.h" +#include "em_core.h" +#include +#include + +/****************************************************** + * Macro Definitions + ******************************************************/ +#define SLI_SI91X_SOCKET_ACCEPT_SUCCESS_EVENT (1 << 0) +#define SLI_SI91X_SOCKET_ACCEPT_FAILURE_EVENT (1 << 1) + +#ifndef SL_SOCKET_DEFAULT_BUFFER_LIMIT +#define SL_SOCKET_DEFAULT_BUFFER_LIMIT 3 +#endif + +/****************************************************** + * Structures + ******************************************************/ + +typedef struct { + uint8_t in_use; + uint8_t select_id; + uint16_t frame_status; + union { + sl_si91x_socket_select_callback_t select_callback; + sl_si91x_socket_select_rsp_t *response_data; + }; +} sli_si91x_select_request_t; + +/****************************************************** + * Static Function Declarations + ******************************************************/ + +static void sli_si91x_clear_select_id(uint8_t flag); +static sli_si91x_select_request_t *sli_si91x_get_available_select_id(void); + +/** + * A internal function to check whether a particular port is available or not. + * @param port_number port_number which needs to be verified for availability. + * @return True if available else false. + */ +static bool is_port_available(uint16_t port_number); + +/****************************************************** + * Variable Definitions + ******************************************************/ +sli_si91x_socket_t *sli_si91x_sockets[NUMBER_OF_SOCKETS] = { 0 }; +static sl_si91x_socket_remote_termination_callback_t user_remote_socket_termination_callback = NULL; +static osMutexId_t sli_si91x_socket_mutex = NULL; +static uint8_t sli_si91x_max_select_count = 0; + +static sli_si91x_select_request_t *select_request_table = NULL; +//sl_si91x_buffer_queue_t sli_si91x_select_request_queue; +//sli_si91x_select_request_t *select_request_head = NULL; +sl_si91x_buffer_queue_t sli_si91x_select_response_queue; + +extern sli_si91x_command_queue_t cmd_queues[SI91X_CMD_MAX]; + +osEventFlagsId_t si91x_socket_events = 0; +osEventFlagsId_t si91x_socket_select_events = 0; + +extern volatile uint32_t tx_socket_command_queues_status; + +extern volatile uint32_t tx_socket_data_queues_status; + +/****************************************************** + * Function Definitions + ******************************************************/ + +void handle_accept_response(sli_si91x_socket_t *si91x_client_socket, const sl_si91x_rsp_ltcp_est_t *accept_response) +{ + //Verifying socket existence + if (si91x_client_socket == NULL) + return; + // Update socket parameters based on the accept response + si91x_client_socket->id = accept_response->socket_id; + si91x_client_socket->local_address.sin6_port = accept_response->src_port_num; + si91x_client_socket->remote_address.sin6_port = accept_response->dest_port; + si91x_client_socket->mss = accept_response->mss; + si91x_client_socket->state = CONNECTED; + si91x_client_socket->remote_address.sin6_family = accept_response->ip_version == SL_IPV6_ADDRESS_LENGTH ? AF_INET6 + : AF_INET; + + if (si91x_client_socket->remote_address.sin6_family == AF_INET6) { + memcpy(si91x_client_socket->remote_address.sin6_addr.s6_addr, + accept_response->dest_ip_addr.ipv6_address, + SL_IPV6_ADDRESS_LENGTH); + + } else { + memcpy(&((struct sockaddr_in *)&si91x_client_socket->remote_address)->sin_addr, + accept_response->dest_ip_addr.ipv4_address, + SL_IPV4_ADDRESS_LENGTH); + } +} + +int handle_select_response(const sl_si91x_socket_select_rsp_t *response, + sl_si91x_fd_set *readfds, + sl_si91x_fd_set *writefds, + sl_si91x_fd_set *exception_fd) +{ + // To track of the total number of file descriptors set + int total_fd_set_count = 0; + + // Clear file descriptor sets + SLI_SI91X_NULL_SAFE_FD_ZERO(readfds); + SLI_SI91X_NULL_SAFE_FD_ZERO(writefds); + SLI_SI91X_NULL_SAFE_FD_ZERO(exception_fd); + + // Iterate through all host sockets + for (int host_socket_index = 0; host_socket_index < NUMBER_OF_SOCKETS; host_socket_index++) { + const sli_si91x_socket_t *socket = get_si91x_socket(host_socket_index); + //Verifying socket existence + if (socket == NULL) { + continue; + } + + // Check if the read file descriptor set is provided and if the corresponding bit is set in the response + if (readfds != NULL && (response->read_fds.fd_array[0] & (1 << socket->id))) { + SL_SI91X_FD_SET(host_socket_index, readfds); + total_fd_set_count++; + } + + // Check if the write file descriptor set is provided and if the corresponding bit is set in the response. + if (writefds != NULL && (response->write_fds.fd_array[0] & (1 << socket->id))) { + SL_SI91X_FD_SET(host_socket_index, writefds); + total_fd_set_count++; + } + } + + return total_fd_set_count; +} + +void sli_si91x_set_accept_callback(sli_si91x_socket_t *server_socket, + sl_si91x_socket_accept_callback_t callback, + int32_t client_socket_id) +{ + // Set the user-defined accept callback function and the client socket ID + server_socket->user_accept_callback = callback; + server_socket->client_id = client_socket_id; +} + +void sli_si91x_set_remote_socket_termination_callback(sl_si91x_socket_remote_termination_callback_t callback) +{ + user_remote_socket_termination_callback = callback; +} + +sl_status_t sli_si91x_socket_init(uint8_t max_select_count) +{ + // Check if the mutex for socket operations is already initialized. + // If not, create a new mutex to ensure thread-safe access. + if (sli_si91x_socket_mutex == NULL) { + sli_si91x_socket_mutex = osMutexNew(NULL); // Create a new mutex. + if (sli_si91x_socket_mutex == NULL) { + return SL_STATUS_FAIL; // Return failure if mutex creation fails. + } + } + + // Check if the event flags object for socket events is already initialized. + // If not, create a new event flag set to manage socket events. + if (si91x_socket_events == NULL) { + si91x_socket_events = osEventFlagsNew(NULL); // Create new event flags. + if (si91x_socket_events == NULL) { + return SL_STATUS_FAIL; // Return failure if event flag creation fails. + } + } + + // Check if the event flags object for socket select events is already initialized. + // If not, create a new event flag set to manage socket select events. + if (si91x_socket_select_events == NULL) { + si91x_socket_select_events = osEventFlagsNew(NULL); // Create new event flags. + if (si91x_socket_select_events == NULL) { + return SL_STATUS_FAIL; // Return failure if event flag creation fails. + } + } + + /* + Allocate memory for the select request table based on the number of select instances. + Heap memory is allocated for the number of instances of this structure based on + the number of selects configured by the user during device initialization in opermode. + Each time a sync or async select command is sent to the firmware, the corresponding + structure is updated, and the instance is cleared when the response is received. + */ + + // Check if the select_request_table is uninitialized and max_select_count is valid. + if (select_request_table == NULL && max_select_count != 0 && max_select_count <= 10) { + sli_si91x_max_select_count = max_select_count; // Store the max number of selects. + + // Allocate memory for the select request table based on the max_select_count. + select_request_table = calloc(max_select_count, sizeof(sli_si91x_select_request_t)); + + // If memory allocation fails, return failure. + if (select_request_table == NULL) { + return SL_STATUS_FAIL; // Return failure if memory allocation fails. + } + } + + return SL_STATUS_OK; // Return success if initialization is successful. +} + +sl_status_t sli_si91x_socket_deinit(void) +{ + // free the sli_si91x_socket_mutex + if (sli_si91x_socket_mutex != NULL) { + osMutexDelete(sli_si91x_socket_mutex); + sli_si91x_socket_mutex = NULL; + } + if (si91x_socket_events != NULL) { + osEventFlagsDelete(si91x_socket_events); + si91x_socket_events = NULL; + } + if (si91x_socket_select_events != NULL) { + osEventFlagsDelete(si91x_socket_select_events); + si91x_socket_select_events = NULL; + } + if (select_request_table != NULL) { + free(select_request_table); + select_request_table = NULL; + } + return SL_STATUS_OK; +} + +sl_status_t sli_si91x_vap_shutdown(uint8_t vap_id) +{ + // Iterate through all BSD sockets and modify the state to DISCONNECTED those associated with the given VAP ID + for (uint8_t socket_index = 0; socket_index < NUMBER_OF_SOCKETS; socket_index++) { + if ((sli_si91x_sockets[socket_index] != NULL) && (sli_si91x_sockets[socket_index]->vap_id == vap_id)) { + sli_si91x_sockets[socket_index]->state = DISCONNECTED; + } + } + + return SL_STATUS_OK; +} + +void sli_si91x_handle_websocket(sl_si91x_socket_create_request_t *socket_create_request, + const sli_si91x_socket_t *si91x_bsd_socket) +{ + socket_create_request->ssl_bitmap |= SI91X_WEBSOCKET_FEAT; + + // Copy host name + if (si91x_bsd_socket->websocket_info && si91x_bsd_socket->websocket_info->host_length > 0) { + memcpy(socket_create_request->webs_host_name, + si91x_bsd_socket->websocket_info->websocket_data, + si91x_bsd_socket->websocket_info->host_length); + socket_create_request->webs_host_name[si91x_bsd_socket->websocket_info->host_length] = '\0'; // Null-terminate + } + + // Copy resource name + if (si91x_bsd_socket->websocket_info && si91x_bsd_socket->websocket_info->resource_length > 0) { + memcpy(socket_create_request->webs_resource_name, + si91x_bsd_socket->websocket_info->websocket_data + si91x_bsd_socket->websocket_info->host_length, + si91x_bsd_socket->websocket_info->resource_length); + socket_create_request->webs_resource_name[si91x_bsd_socket->websocket_info->resource_length] = + '\0'; // Null-terminate + } +} + +sl_status_t sl_si91x_config_socket(sl_si91x_socket_config_t socket_config) +{ + sl_status_t status = SL_STATUS_OK; + + // Send the socket configuration command to the SI91X driver + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SOCKET_CONFIG, + SI91X_SOCKET_CMD, + &socket_config, + sizeof(socket_config), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +void reset_socket_state(int socket) +{ + if (sli_si91x_sockets[socket] == NULL) { + return; + } + + if (sli_si91x_sockets[socket]->socket_events != NULL) { + osEventFlagsDelete(sli_si91x_sockets[socket]->socket_events); + sli_si91x_sockets[socket]->socket_events = NULL; + } + + free(sli_si91x_sockets[socket]); + sli_si91x_sockets[socket] = NULL; +} + +// Get the SI91X socket with the specified index, if it is valid and not in RESET state +sli_si91x_socket_t *get_si91x_socket(int32_t socket) +{ + if (socket < 0 || socket >= NUMBER_OF_SOCKETS) { + return NULL; + } + return sli_si91x_sockets[socket]; +} + +sli_si91x_socket_t *sli_si91x_get_socket_from_id(int socket_id, + sli_si91x_bsd_socket_state_t excluded_state, + int16_t role) +{ + sli_si91x_socket_t *possible_socket = NULL; + for (uint8_t index = 0; index < NUMBER_OF_SOCKETS; ++index) { + sli_si91x_socket_t *socket = sli_si91x_sockets[index]; + if (socket != NULL && socket->id == socket_id && socket->state != excluded_state + && (role == -1 || socket->role == role)) { + if (socket->command_queue.command_in_flight == false) { + possible_socket = socket; + } else { + return socket; + } + } + } + return possible_socket; +} + +static sli_si91x_socket_t *sli_si91x_get_socket_from_port(uint16_t src_port) +{ + for (int i = 0; i < NUMBER_OF_SOCKETS; i++) { + if (sli_si91x_sockets[i] == NULL) { + continue; + } + if ((sli_si91x_sockets[i]->role == SI91X_SOCKET_TCP_SERVER) + && (src_port == sli_si91x_sockets[i]->local_address.sin6_port)) { + return sli_si91x_sockets[i]; + } + } + + return NULL; +} + +// Find and return an available socket and its index +void get_free_socket(sli_si91x_socket_t **socket, int *socket_fd) +{ + *socket = NULL; + *socket_fd = -1; + + osMutexAcquire(sli_si91x_socket_mutex, 0xFFFFFFFFUL); + // Iterate through all available sockets to find a free one + for (uint8_t socket_index = 0; socket_index < NUMBER_OF_SOCKETS; socket_index++) { + + // If the socket is in use skip it + if (sli_si91x_sockets[socket_index] != NULL) { + continue; + } + + // Allocate new socket + sli_si91x_sockets[socket_index] = malloc(sizeof(sli_si91x_socket_t)); + if (sli_si91x_sockets[socket_index] == NULL) { + break; + } + memset(sli_si91x_sockets[socket_index], 0, sizeof(sli_si91x_socket_t)); + sli_si91x_sockets[socket_index]->id = -1; + sli_si91x_sockets[socket_index]->index = socket_index; + sli_si91x_sockets[socket_index]->data_buffer_limit = SL_SOCKET_DEFAULT_BUFFER_LIMIT; + + // If a free socket is found, set the socket pointer to point to it + *socket = sli_si91x_sockets[socket_index]; + // Set the socket_fd to the index of the free socket, which can be used as a file descriptor + *socket_fd = socket_index; + // Exit the loop because a free socket has been found. + break; + } + osMutexRelease(sli_si91x_socket_mutex); +} + +static bool is_port_available(uint16_t port_number) +{ + // Check whether local port is already used or not + for (uint8_t socket_index = 0; socket_index < NUMBER_OF_SOCKETS; socket_index++) { + if (sli_si91x_sockets[socket_index] != NULL + && sli_si91x_sockets[socket_index]->local_address.sin6_port == port_number) { + return false; + } + } + + return true; +} + +/** + * @brief This function is responsible to copy the TLS extension information provided by application into socket structure. + * + * @param socket_tls_extensions pointer to TLS extension in socket structure + * @param tls_extension pointer to the TLS information provided by application + * @return sl_status_t possible return values are SL_STATUS_OK and SL_STATUS_SI91X_MEMORY_ERROR + */ +sl_status_t sli_si91x_add_tls_extension(sli_si91x_tls_extensions_t *socket_tls_extensions, + const sl_si91x_socket_type_length_value_t *tls_extension) +{ + // To check if memory available for new extension in buffer of socket, max 256 Bytes only + if (SI91X_MAX_SIZE_OF_EXTENSION_DATA - socket_tls_extensions->current_size_of_extensions + < (int)(sizeof(sl_si91x_socket_type_length_value_t) + tls_extension->length)) { + return SL_STATUS_SI91X_MEMORY_ERROR; + } + + uint8_t extension_size = (uint8_t)(sizeof(sl_si91x_socket_type_length_value_t) + tls_extension->length); + + // copies TLS extension provided by app into SDK socket struct + memcpy(&socket_tls_extensions->buffer[socket_tls_extensions->current_size_of_extensions], + tls_extension, + extension_size); + socket_tls_extensions->current_size_of_extensions += extension_size; + socket_tls_extensions->total_extensions++; + + return SL_STATUS_OK; +} + +int32_t sli_get_socket_command_from_host_packet(sl_wifi_buffer_t *buffer) +{ + sl_si91x_packet_t *packet = (sl_si91x_packet_t *)buffer->data; + return (packet == NULL ? -1 : packet->command); +} + +// Prepare socket request based on socket type and send the request down to the driver. +// socket type : [SL_SOCKET_TCP_SERVER, SL_SOCKET_TCP_CLIENT, SL_SOCKET_LUDP, SL_SOCKET_UDP_CLIENT] +sl_status_t create_and_send_socket_request(int socketIdIndex, int type, const int *backlog) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_socket_create_request_t socket_create_request = { 0 }; + const sl_si91x_socket_create_response_t *socket_create_response = NULL; + sli_si91x_socket_t *si91x_bsd_socket = get_si91x_socket(socketIdIndex); + sl_si91x_wait_period_t wait_period = SL_SI91X_WAIT_FOR_RESPONSE(5000); + //Verifying socket existence + if (si91x_bsd_socket == NULL) { + return -1; + } + if (type == SI91X_SOCKET_TCP_CLIENT) { + wait_period = SL_SI91X_WAIT_FOR_RESPONSE(100000); // timeout is 10 sec + } + + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + + if (si91x_bsd_socket->local_address.sin6_family == AF_INET6) { + socket_create_request.ip_version = SL_IPV6_VERSION; + + memcpy(socket_create_request.dest_ip_addr.ipv6_address, + si91x_bsd_socket->remote_address.sin6_addr.s6_addr, + SL_IPV6_ADDRESS_LENGTH); + } else { + socket_create_request.ip_version = SL_IPV4_ADDRESS_LENGTH; + memcpy(socket_create_request.dest_ip_addr.ipv4_address, + &((struct sockaddr_in *)&si91x_bsd_socket->remote_address)->sin_addr, + SL_IPV4_ADDRESS_LENGTH); + } + + socket_create_request.local_port = si91x_bsd_socket->local_address.sin6_port; + socket_create_request.remote_port = si91x_bsd_socket->remote_address.sin6_port; + + // Fill socket type + socket_create_request.socket_type = (uint16_t)type; + + if (type == SI91X_SOCKET_TCP_SERVER) { + socket_create_request.max_count = (backlog == NULL) ? 0 : (uint16_t)*backlog; + socket_create_request.socket_bitmap |= SI91X_SOCKET_FEAT_LTCP_ACCEPT; + si91x_bsd_socket->socket_events = osEventFlagsNew(NULL); + } else { + socket_create_request.max_count = 0; + } + + if (si91x_bsd_socket->recv_data_callback == NULL) { + socket_create_request.socket_bitmap |= SI91X_SOCKET_FEAT_SYNCHRONOUS; + } + + socket_create_request.socket_bitmap |= SI91X_SOCKET_FEAT_TCP_RX_WINDOW; + + // Set the RX window size + socket_create_request.rx_window_size = TCP_RX_WINDOW_SIZE; + + // Fill VAP_ID + socket_create_request.vap_id = si91x_bsd_socket->vap_id; + socket_create_request.tos = 0; + socket_create_request.max_tcp_retries_count = si91x_bsd_socket->max_tcp_retries ? si91x_bsd_socket->max_tcp_retries + : MAX_TCP_RETRY_COUNT; + socket_create_request.tcp_keepalive_initial_time = si91x_bsd_socket->tcp_keepalive_initial_time + ? si91x_bsd_socket->tcp_keepalive_initial_time + : DEFAULT_TCP_KEEP_ALIVE_TIME; + socket_create_request.tcp_mss = si91x_bsd_socket->mss; + + // Check for SSL feature and fill it in SSL bitmap + if (si91x_bsd_socket->ssl_bitmap & SL_SI91X_ENABLE_TLS) { + socket_create_request.ssl_bitmap = si91x_bsd_socket->ssl_bitmap; + socket_create_request.ssl_ciphers_bitmap = SSL_ALL_CIPHERS; +#if defined(SLI_SI917) || defined(SLI_SI915) + socket_create_request.ssl_ext_ciphers_bitmap = SSL_EXT_CIPHERS; +#endif + // Check if cert index is not default index + if (si91x_bsd_socket->certificate_index > SI91X_CERT_INDEX_0) { + socket_create_request.socket_bitmap |= SI91X_SOCKET_FEAT_CERT_INDEX; + } + + socket_create_request.socket_cert_inx = si91x_bsd_socket->certificate_index; + + // Check if extension is provided my application and memcopy until the provided size of extensions + if (si91x_bsd_socket->tls_extensions.total_extensions > 0) { + memcpy(socket_create_request.tls_extension_data, + si91x_bsd_socket->tls_extensions.buffer, + si91x_bsd_socket->tls_extensions.current_size_of_extensions); + + socket_create_request.total_extension_length = si91x_bsd_socket->tls_extensions.current_size_of_extensions; + socket_create_request.no_of_tls_extensions = si91x_bsd_socket->tls_extensions.total_extensions; + } + wait_period = SL_SI91X_WAIT_FOR_RESPONSE(150000); // timeout is 15 sec + } + + // Check for HIGH_PERFORMANCE feature bit + if (si91x_bsd_socket->ssl_bitmap & SI91X_HIGH_PERFORMANCE_SOCKET) { + socket_create_request.ssl_bitmap |= SI91X_HIGH_PERFORMANCE_SOCKET; + } + + // Check for Websocket feature bit + if (si91x_bsd_socket->ssl_bitmap & SI91X_WEBSOCKET_FEAT) { + sli_si91x_handle_websocket(&socket_create_request, si91x_bsd_socket); + } + + // Check for TCP ACK INDICATION feature bit + if (si91x_bsd_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION) { + socket_create_request.socket_bitmap |= SI91X_SOCKET_FEAT_TCP_ACK_INDICATION; + } +#if defined(SLI_SI917) || defined(SLI_SI915) + // Set socket's max retransmission timeout value and TOS (Type of Service) if applicable + socket_create_request.max_retransmission_timeout_value = (uint8_t)si91x_bsd_socket->max_retransmission_timeout_value; + socket_create_request.tos = (uint16_t)si91x_bsd_socket->tos; +#endif + + // Store socket role for future references. + si91x_bsd_socket->role = type; + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SOCKET_CREATE, + SI91X_SOCKET_CMD, + &socket_create_request, + sizeof(socket_create_request), + wait_period, + NULL, + &buffer); + + // If the status is not OK and there's a buffer, free the buffer + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + // Extract socket creation response information + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + socket_create_response = (sl_si91x_socket_create_response_t *)packet->data; + + si91x_bsd_socket->id = (int32_t)(socket_create_response->socket_id[0] | (socket_create_response->socket_id[1] << 8)); + si91x_bsd_socket->local_address.sin6_port = + (uint16_t)(socket_create_response->module_port[0] | (socket_create_response->module_port[1] << 8)); + + if (type != SI91X_SOCKET_TCP_SERVER) { + si91x_bsd_socket->remote_address.sin6_port = + (uint16_t)(socket_create_response->dst_port[0] | socket_create_response->dst_port[1] << 8); + } + + si91x_bsd_socket->mss = (uint16_t)((socket_create_response->mss[0]) | (socket_create_response->mss[1] << 8)); + + // If socket is already bound to an local address and port, there is no need to copy it again. + if (si91x_bsd_socket->state == BOUND) { + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; + } + + // Copy the local address (IPv4 or IPv6) based on family type + if (si91x_bsd_socket->local_address.sin6_family == AF_INET) { + memcpy(&((struct sockaddr_in *)&si91x_bsd_socket->local_address)->sin_addr.s_addr, + socket_create_response->module_ip_addr.ipv4_addr, + SL_IPV4_ADDRESS_LENGTH); + } else { + memcpy(si91x_bsd_socket->local_address.sin6_addr.s6_addr, + socket_create_response->module_ip_addr.ipv6_addr, + SL_IPV6_ADDRESS_LENGTH); + } + + // Free the buffer + sl_si91x_host_free_buffer(buffer); + + return SL_STATUS_OK; +} + +int sli_si91x_socket(int family, int type, int protocol, sl_si91x_socket_receive_data_callback_t callback) +{ + // Validate the socket parameters + SET_ERRNO_AND_RETURN_IF_TRUE(family != AF_INET && family != AF_INET6, EAFNOSUPPORT); + SET_ERRNO_AND_RETURN_IF_TRUE(type != SOCK_STREAM && type != SOCK_DGRAM, EINVAL); + SET_ERRNO_AND_RETURN_IF_TRUE(protocol != IPPROTO_TCP && protocol != IPPROTO_UDP && protocol != 0, EINVAL); + SET_ERRNO_AND_RETURN_IF_TRUE((type == SOCK_STREAM && (protocol != IPPROTO_TCP && protocol != 0)), EPROTOTYPE); + SET_ERRNO_AND_RETURN_IF_TRUE((type == SOCK_DGRAM && (protocol != IPPROTO_UDP && protocol != 0)), EPROTOTYPE); + + // Initialize a new socket structure + sli_si91x_socket_t *si91x_socket; + int socket_index = -1; + + get_free_socket(&si91x_socket, &socket_index); + + // Check if there is enough memory to create the socket + if (socket_index < 0) { + SET_ERROR_AND_RETURN(ENOMEM); + } + + // Populate the socket structure with provided parameters and callbacks + si91x_socket->type = type; + si91x_socket->local_address.sin6_family = (uint8_t)family; + si91x_socket->protocol = protocol; + si91x_socket->state = INITIALIZED; + si91x_socket->recv_data_callback = callback; + + // Return the socket index + return socket_index; +} + +int sli_si91x_accept(int socket, struct sockaddr *addr, socklen_t *addr_len, sl_si91x_socket_accept_callback_t callback) +{ + sl_status_t status = SL_STATUS_OK; + sli_si91x_socket_t *si91x_client_socket = NULL; + sli_si91x_socket_t *si91x_server_socket = get_si91x_socket(socket); + sl_si91x_socket_accept_request_t accept_request = { 0 }; + int32_t client_socket_id = -1; + sl_wifi_buffer_t *buffer = NULL; + + // Check if the server socket is valid + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_server_socket == NULL, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_server_socket->type != SOCK_STREAM, EOPNOTSUPP); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_server_socket->state != LISTEN, EINVAL); + + // Create a new instance for socket + client_socket_id = sli_si91x_socket(si91x_server_socket->local_address.sin6_family, + si91x_server_socket->type, + si91x_server_socket->protocol, + si91x_server_socket->recv_data_callback); + + si91x_client_socket = get_si91x_socket(client_socket_id); + //Verifying socket existence + if (si91x_client_socket == NULL) + return -1; + memcpy(&si91x_client_socket->local_address, &si91x_server_socket->local_address, sizeof(struct sockaddr_in6)); + + // Create accept request + accept_request.socket_id = (uint8_t)si91x_server_socket->id; + accept_request.source_port = si91x_server_socket->local_address.sin6_port; + + // Set the callback and client socket ID. + sli_si91x_set_accept_callback(si91x_server_socket, callback, client_socket_id); + if (callback != NULL) { + status = sli_si91x_send_socket_command(si91x_client_socket, + RSI_WLAN_REQ_SOCKET_ACCEPT, + &accept_request, + sizeof(accept_request), + SL_SI91X_RETURN_IMMEDIATELY, + NULL); + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + return SL_STATUS_OK; + } else { + status = sli_si91x_send_socket_command(si91x_client_socket, + RSI_WLAN_REQ_SOCKET_ACCEPT, + &accept_request, + sizeof(accept_request), + SL_SI91X_WAIT_FOR_EVER | SL_SI91X_WAIT_FOR_RESPONSE_BIT, + &buffer); + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + } + + // If the accept request fails, clean up allocated memory and return an error + if (status != SL_STATUS_OK) { + sli_si91x_shutdown(client_socket_id, SHUTDOWN_BY_ID); + if (buffer != NULL) { + sl_si91x_host_free_buffer(buffer); + } + SET_ERROR_AND_RETURN(SI91X_UNDEFINED_ERROR); + } + + sli_si91x_queue_packet_t *node = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + sl_wifi_buffer_t *response = node->host_packet; + sl_si91x_host_free_buffer(buffer); + + if (response == NULL) { + SET_ERROR_AND_RETURN(SI91X_UNDEFINED_ERROR); + } + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(response, 0, NULL); + sl_si91x_rsp_ltcp_est_t *ltcp = (sl_si91x_rsp_ltcp_est_t *)packet->data; + + handle_accept_response(si91x_client_socket, ltcp); + + // If addr_len is NULL or invalid value, just return the client socket ID + if (addr != NULL && *addr_len > 0) { + // Copy the remote address to the provided sockaddr structure + memcpy(addr, + &si91x_client_socket->remote_address, + (*addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : *addr_len); + + // Update addr_len based on the family of the local address + *addr_len = si91x_client_socket->local_address.sin6_family == AF_INET ? sizeof(struct sockaddr_in) + : sizeof(struct sockaddr_in6); + } + // Free resources and return the client socket ID + sl_si91x_host_free_buffer(response); + + return client_socket_id; +} + +// Shutdown a socket +int sli_si91x_shutdown(int socket, int how) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_socket_close_request_t socket_close_request = { 0 }; + sl_si91x_socket_close_response_t *socket_close_response = NULL; + sl_si91x_wait_period_t wait_period = SL_SI91X_WAIT_FOR_RESPONSE(SL_SI91X_WAIT_FOR_EVER); + sl_wifi_buffer_t *buffer = NULL; + + sli_si91x_socket_t *si91x_socket = get_si91x_socket(socket); + + // Verify the socket's existence + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + + // The firmware maps server socket and first client socket connected to the server would be assigned same firmware socket ID. + // Therefore, if Dev attempts to close either first client or server, close request type needs to be set to SHUTDOWN_BY_PORT. + int close_request_type = (si91x_socket->state == LISTEN) ? SHUTDOWN_BY_PORT : how; + + // If the socket is in an initial state or marked for auto-close, reset it and return + if (si91x_socket->state == BOUND || si91x_socket->state == INITIALIZED + || (si91x_socket->state == DISCONNECTED && is_tcp_auto_close_enabled())) { + reset_socket_state(socket); + + return SI91X_NO_ERROR; + } + + /*If socket is server socket, SHUTDOWN_BY_PORT is to be used irrespective of 'how' parameter.*/ + socket_close_request.socket_id = (uint16_t)((close_request_type == SHUTDOWN_BY_ID) ? si91x_socket->id : 0); + socket_close_request.port_number = (close_request_type == SHUTDOWN_BY_ID) ? 0 : si91x_socket->local_address.sin6_port; + + status = sli_si91x_send_socket_command(si91x_socket, + RSI_WLAN_REQ_SOCKET_CLOSE, + &socket_close_request, + sizeof(socket_close_request), + wait_period, + &buffer); + + // If the status is not OK and there's a buffer, free the buffer + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + + sli_si91x_queue_packet_t *node = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (node->host_packet == NULL) { + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_FAIL; + } + + sl_wifi_buffer_t *response_buffer = node->host_packet; + sl_si91x_host_free_buffer(buffer); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(response_buffer, 0, NULL); + socket_close_response = (sl_si91x_socket_close_response_t *)packet->data; + + if (close_request_type == SHUTDOWN_BY_ID && si91x_socket->id == socket_close_response->socket_id) { + reset_socket_state(socket); + sl_si91x_host_free_buffer(response_buffer); + return SI91X_NO_ERROR; + } + // Reset sockets that match the close request + for (uint8_t index = 0; index < NUMBER_OF_SOCKETS; index++) { + const sli_si91x_socket_t *socket_id = get_si91x_socket(index); + //Verifying socket existence + if (socket_id == NULL) + continue; + else if (close_request_type == SHUTDOWN_BY_PORT + && socket_id->local_address.sin6_port == socket_close_response->port_number) { + reset_socket_state(index); + } + } + + sl_si91x_host_free_buffer(response_buffer); + + return SI91X_NO_ERROR; +} + +sl_status_t si91x_socket_event_handler(sl_status_t status, + sl_si91x_socket_context_t *sdk_context, + sl_si91x_packet_t *rx_packet) +{ + UNUSED_PARAMETER(status); + + // Handle connection establishment response + if (rx_packet->command == RSI_WLAN_REQ_SOCKET_ACCEPT) { + const sl_si91x_rsp_ltcp_est_t *accept_response = (sl_si91x_rsp_ltcp_est_t *)rx_packet->data; + sli_si91x_socket_t *server_socket = sli_si91x_get_socket_from_port(accept_response->src_port_num); + int32_t client_socket_id = -1; + if (server_socket == NULL) { + return -1; + } + client_socket_id = server_socket->client_id; + server_socket->client_id = -1; + sli_si91x_socket_t *client_socket = get_si91x_socket(client_socket_id); + + handle_accept_response(client_socket, accept_response); + + if (server_socket->user_accept_callback != NULL) { + // Call the accept callback function with relevant socket information + server_socket->user_accept_callback(client_socket_id, + (struct sockaddr *)&server_socket->remote_address, + (uint8_t)server_socket->type); + } + } + // Handle remote socket termination response + else if (rx_packet->command == RSI_WLAN_RSP_REMOTE_TERMINATE) { + + sl_si91x_socket_close_response_t *remote_socket_closure = (sl_si91x_socket_close_response_t *)rx_packet->data; + // Reset sockets that match the close request + for (uint8_t index = 0; index < NUMBER_OF_SOCKETS; index++) { + sli_si91x_socket_t *socket = get_si91x_socket(index); + //Verifying socket existence + if (socket == NULL || remote_socket_closure->socket_id != socket->id || socket->state == LISTEN) + continue; + + socket->state = DISCONNECTED; + uint16_t frame_status = get_si91x_frame_status(rx_packet); + sli_si91x_flush_socket_command_queues_based_on_queue_type(index, frame_status); + sli_si91x_flush_socket_data_queues_based_on_queue_type(index); + + if (user_remote_socket_termination_callback != NULL) { + user_remote_socket_termination_callback(socket->id, + socket->local_address.sin6_port, + remote_socket_closure->sent_bytes_count); + } + break; + } + } else if (rx_packet->command == RSI_RECEIVE_RAW_DATA) { + // Handle the case when raw data is received + const sl_si91x_socket_metadata_t *firmware_socket_response = (sl_si91x_socket_metadata_t *)rx_packet->data; + uint8_t *data = (rx_packet->data + firmware_socket_response->offset); + + int8_t host_socket = -1; + + // Find the host socket corresponding to the received data + for (uint8_t host_socket_index = 0; host_socket_index < NUMBER_OF_SOCKETS; host_socket_index++) { + if ((sli_si91x_sockets[host_socket_index] != NULL) + && (firmware_socket_response->socket_id == sli_si91x_sockets[host_socket_index]->id)) { + host_socket = host_socket_index; + } + } + + // Retrieve the client socket + const sli_si91x_socket_t *client_socket = get_si91x_socket(host_socket); + //Verifying socket existence + if (client_socket == NULL) { + SL_CLEANUP_MALLOC(sdk_context); + return -1; + } + + // Call the user-defined receive data callback + client_socket->recv_data_callback(host_socket, data, firmware_socket_response->length, firmware_socket_response); + } else if (rx_packet->command == RSI_WLAN_RSP_SELECT_REQUEST) { + sl_si91x_socket_select_rsp_t *socket_select_rsp = (sl_si91x_socket_select_rsp_t *)rx_packet->data; + + if (socket_select_rsp->select_id < sli_si91x_max_select_count + && select_request_table[socket_select_rsp->select_id].in_use) { + sli_si91x_select_request_t *select_request = &select_request_table[socket_select_rsp->select_id]; + select_request->frame_status = (uint16_t)(rx_packet->desc[12] + (rx_packet->desc[13] << 8)); + if (select_request->select_callback != NULL) { + sl_si91x_fd_set read_fd; + sl_si91x_fd_set write_fd; + sl_si91x_fd_set exception_fd; + + // This function handles responses received from the SI91X socket driver + handle_select_response((sl_si91x_socket_select_rsp_t *)rx_packet->data, &read_fd, &write_fd, &exception_fd); + + // Call the user-defined select callback function with the updated file descriptor sets and status + select_request->select_callback(&read_fd, &write_fd, &exception_fd, status); + + sli_si91x_clear_select_id(select_request->select_id); + } else { + select_request->response_data = malloc(sizeof(sl_si91x_socket_select_rsp_t)); + if (select_request->response_data == NULL) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + } else { + memcpy(select_request->response_data, rx_packet->data, sizeof(sl_si91x_socket_select_rsp_t)); + osEventFlagsSet(si91x_socket_select_events, BIT(socket_select_rsp->select_id)); + } + } + } else { + SL_DEBUG_LOG("\r\n INVALID SELECT ID\r\n"); + } + } + // This block of code is executed when a TCP acknowledgment indication is received. + else if (rx_packet->command == RSI_WLAN_RSP_TCP_ACK_INDICATION) { + const sl_si91x_rsp_tcp_ack_t *tcp_ack = (sl_si91x_rsp_tcp_ack_t *)rx_packet->data; + + // Initialize a variable to store the host socket ID + int8_t host_socket = -1; + + // Iterate through all host sockets to find a matching socket ID + for (uint8_t host_socket_index = 0; host_socket_index < NUMBER_OF_SOCKETS; host_socket_index++) { + if ((sli_si91x_sockets[host_socket_index] != NULL) + && (tcp_ack->socket_id == sli_si91x_sockets[host_socket_index]->id)) { + host_socket = host_socket_index; + break; + } + } + // Retrieve the SI91X socket associated with the host socket + sli_si91x_socket_t *si91x_socket = get_si91x_socket(host_socket); + //Verifying socket existence + if (si91x_socket == NULL) { + SL_CLEANUP_MALLOC(sdk_context); + return -1; + } + // Check if the SI91X_SOCKET_FEAT_TCP_ACK_INDICATION bit is set move the socket to CONNECTED state. + if (si91x_socket->socket_bitmap & SI91X_SOCKET_FEAT_TCP_ACK_INDICATION) { + si91x_socket->is_waiting_on_ack = false; + } + // Check if the SI91X socket and its data transfer callback function exist + if (si91x_socket != NULL && si91x_socket->data_transfer_callback != NULL) { + si91x_socket->data_transfer_callback(host_socket, (uint8_t)(tcp_ack->length[0] | tcp_ack->length[1] << 8)); + } + } + + // Cleanup any dynamically allocated memory in the SDK context + SL_CLEANUP_MALLOC(sdk_context); + + return SL_STATUS_OK; +} + +sl_status_t sli_si91x_send_socket_command(sli_si91x_socket_t *socket, + uint32_t command, + const void *data, + uint32_t data_length, + uint32_t wait_period, + sl_wifi_buffer_t **response_buffer) + +{ + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sl_wifi_buffer_t *node_buffer; + sli_si91x_queue_packet_t *node; + sl_status_t status; + static uint8_t command_packet_id = 0; + + // Allocate a buffer for the command with appropriate size + status = sli_si91x_allocate_command_buffer(&buffer, + (void **)&packet, + sizeof(sl_si91x_packet_t) + data_length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + VERIFY_STATUS_AND_RETURN(status); + + // Allocate a queue node + status = sli_si91x_allocate_command_buffer(&node_buffer, + (void **)&node, + sizeof(sli_si91x_queue_packet_t), + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + if (status != SL_STATUS_OK) { + sl_si91x_host_free_buffer(buffer); + return status; + } + + // Clear the packet descriptor and copy the command data if available + memset(packet->desc, 0, sizeof(packet->desc)); + if (data != NULL) { + memcpy(packet->data, data, data_length); + } + + // Fill frame type + packet->length = data_length & 0xFFF; + packet->command = command; + + // Set flags +#ifdef TEST_USE_UNUSED_FLAGS + packet->unused[SLI_SI91X_COMMAND_FLAGS_INDEX] = (wait_period & SL_SI91X_WAIT_FOR_RESPONSE_BIT) ? (1 << 0) : 0; + packet->unused[SLI_SI91X_COMMAND_FLAGS_INDEX] |= (response_buffer == NULL) ? (1 << 1) : 0; + if (command == RSI_WLAN_REQ_SOCKET_ACCEPT) { + packet->unused[SLI_SI91X_COMMAND_RESPONSE_INDEX] = RSI_WLAN_RSP_CONN_ESTABLISH; + } else { + packet->unused[SLI_SI91X_COMMAND_RESPONSE_INDEX] = command; + } +#else + node->flags = (wait_period & SL_SI91X_WAIT_FOR_RESPONSE_BIT) ? SI91X_PACKET_RESPONSE_PACKET : 0; +#endif + + wait_period &= ~SL_SI91X_WAIT_FOR_RESPONSE_BIT; + + if (wait_period != 0) { + node->flags |= SI91X_PACKET_RESPONSE_STATUS; + } + + // Set various properties of the node representing the command packet + node->host_packet = buffer; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_SOCKET_CMD; + + if ((node->flags != SI91X_PACKET_WITH_ASYNC_RESPONSE)) { + node->command_tickcount = osKernelGetTickCount(); + // Calculate the wait time based on wait_period + if ((wait_period & SL_SI91X_WAIT_FOR_EVER) == SL_SI91X_WAIT_FOR_EVER) { + node->command_timeout = osWaitForever; + } else { + node->command_timeout = (wait_period & ~SL_SI91X_WAIT_FOR_RESPONSE_BIT); + } + } + node->sdk_context = NULL; + + CORE_irqState_t state = CORE_EnterAtomic(); + uint8_t this_packet_id = command_packet_id++; + buffer->id = this_packet_id; + node_buffer->id = this_packet_id; + sli_si91x_append_to_buffer_queue(&socket->command_queue.tx_queue, node_buffer); + tx_socket_command_queues_status |= (1 << socket->index); + sli_si91x_set_event(SL_SI91X_SOCKET_COMMAND_TX_PENDING_EVENT); + CORE_ExitAtomic(state); + + if (wait_period != 0) { + + uint16_t firmware_status = 0; + sl_si91x_buffer_queue_t *rx_queue; + if (command == RSI_WLAN_REQ_SOCKET_READ_DATA) { + rx_queue = &socket->rx_data_queue; + } else { + rx_queue = &socket->command_queue.rx_queue; + } + + status = sli_si91x_driver_wait_for_response_packet(rx_queue, + si91x_socket_events, + (1 << socket->index), + this_packet_id, + wait_period, + response_buffer); + VERIFY_STATUS_AND_RETURN(status); + + if (command == RSI_WLAN_REQ_SOCKET_READ_DATA) { + sl_si91x_packet_t *packet = (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data(*response_buffer, 0, NULL); + firmware_status = (uint16_t)(packet->desc[12] + (packet->desc[13] << 8)); // Extract the frame status + + } else { + // Process the response packet and return the firmware status + sli_si91x_queue_packet_t *node = + (sli_si91x_queue_packet_t *)sl_si91x_host_get_buffer_data(*response_buffer, 0, NULL); + firmware_status = node->frame_status; + } + return convert_and_save_firmware_status(firmware_status); + } else { + return SL_STATUS_OK; + } +} + +sl_status_t sli_si91x_send_socket_data(sli_si91x_socket_t *si91x_socket, + const sli_si91x_socket_send_request_t *request, + const void *data) +{ + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sli_si91x_socket_send_request_t *send; + + sl_status_t status = SL_STATUS_OK; + uint16_t header_length = (request->data_offset - sizeof(sli_si91x_socket_send_request_t)); + uint32_t data_length = request->length; + + if (data == NULL) { + return SL_STATUS_NULL_POINTER; + } + + uint32_t start = osKernelGetTickCount(); + while (si91x_socket->data_buffer_limit != 0 && si91x_socket->data_buffer_count >= si91x_socket->data_buffer_limit) { + osDelay(2); + if ((osKernelGetTickCount() - start) > SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME) { + return SL_STATUS_WIFI_BUFFER_ALLOC_FAIL; + } + } + + // Allocate a buffer for the socket data with appropriate size + status = sl_si91x_host_allocate_buffer( + &buffer, + SL_WIFI_TX_FRAME_BUFFER, + sizeof(sl_si91x_packet_t) + sizeof(sli_si91x_socket_send_request_t) + header_length + data_length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (packet == NULL) { + return SL_STATUS_WIFI_BUFFER_ALLOC_FAIL; + } + ++si91x_socket->data_buffer_count; + + memset(packet->desc, 0, sizeof(packet->desc)); + + send = (sli_si91x_socket_send_request_t *)packet->data; + memcpy(send, request, sizeof(sli_si91x_socket_send_request_t)); + memcpy((send->send_buffer + header_length), data, data_length); + + // Fill frame type + packet->length = (sizeof(sli_si91x_socket_send_request_t) + header_length + data_length) & 0xFFF; + + // ++data_queue_appended_count; + CORE_irqState_t state = CORE_EnterAtomic(); + sli_si91x_append_to_buffer_queue(&si91x_socket->tx_data_queue, buffer); + tx_socket_data_queues_status |= (1 << si91x_socket->index); + sli_si91x_set_event(SL_SI91X_SOCKET_DATA_TX_PENDING_EVENT); + CORE_ExitAtomic(state); + + return SL_STATUS_OK; +} + +int sli_si91x_get_socket_id(sl_si91x_packet_t *packet) +{ + // Handle connection establishment response + switch (packet->command) { + case RSI_WLAN_RSP_CONN_ESTABLISH: + return ((sl_si91x_rsp_ltcp_est_t *)packet->data)->socket_id; + case RSI_WLAN_RSP_REMOTE_TERMINATE: + return ((sl_si91x_socket_close_response_t *)packet->data)->socket_id; + case RSI_RECEIVE_RAW_DATA: + return *((uint8_t *)&(((sl_si91x_socket_metadata_t *)packet->data)->socket_id)); + case RSI_WLAN_RSP_SOCKET_READ_DATA: + return packet->data[0]; + case RSI_WLAN_RSP_TCP_ACK_INDICATION: + return ((sl_si91x_rsp_tcp_ack_t *)packet->data)->socket_id; + case RSI_WLAN_RSP_SOCKET_CREATE: + return (((sl_si91x_socket_create_response_t *)packet->data)->socket_id[0] + + (((sl_si91x_socket_create_response_t *)packet->data)->socket_id[1] << 8)); + case RSI_WLAN_RSP_SOCKET_CLOSE: + if (((sl_si91x_socket_close_response_t *)packet->data)->socket_id == 0) { + const uint16_t port = ((sl_si91x_socket_close_response_t *)packet->data)->port_number; + for (int i = 0; i < NUMBER_OF_SOCKETS; ++i) { + if (sli_si91x_sockets[i] != NULL && sli_si91x_sockets[i]->local_address.sin6_port == port) { + return sli_si91x_sockets[i]->id; + } + } + return -1; + } else { + return ((sl_si91x_socket_close_response_t *)packet->data)->socket_id; + } + case RSI_WLAN_RSP_SELECT_REQUEST: + default: + return -1; + } + + return -1; +} + +int sli_si91x_connect(int socket, const struct sockaddr *addr, socklen_t addr_len) +{ + errno = 0; + + sl_status_t status = SL_STATUS_FAIL; + sli_si91x_socket_t *si91x_socket; + + // Retrieve the socket using the socket index + si91x_socket = get_si91x_socket(socket); + + // Check if the socket is valid. + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL, EBADF); + + // Check if the socket is already connected + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_STREAM && si91x_socket->state == CONNECTED, EISCONN); + + // Check the socket state based on its type + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_STREAM && si91x_socket->state > BOUND, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->type == SOCK_DGRAM && si91x_socket->state != INITIALIZED + && si91x_socket->state != BOUND && si91x_socket->state != UDP_UNCONNECTED_READY, + EBADF); + + // Check if the provided sockaddr length is sufficient + SET_ERRNO_AND_RETURN_IF_TRUE( + (si91x_socket->local_address.sin6_family == AF_INET && addr_len < sizeof(struct sockaddr_in)) + || (si91x_socket->local_address.sin6_family == AF_INET6 && addr_len < sizeof(struct sockaddr_in6)), + EINVAL); + + // Check if the provided sockaddr pointer is valid + SET_ERRNO_AND_RETURN_IF_TRUE(addr == NULL, EFAULT); + + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket->local_address.sin6_family != addr->sa_family, EAFNOSUPPORT); + + memcpy(&si91x_socket->remote_address, + addr, + (addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : addr_len); + + // Since socket is already created, there is no need to send create request again. + if (si91x_socket->type == SOCK_DGRAM && si91x_socket->state == UDP_UNCONNECTED_READY) { + si91x_socket->state = CONNECTED; + + return SI91X_NO_ERROR; + } + + // Prepare socket request based on socket type and send the request to the bus driver + if (si91x_socket->type == SOCK_STREAM) { + status = create_and_send_socket_request(socket, SI91X_SOCKET_TCP_CLIENT, NULL); + } else if (si91x_socket->type == SOCK_DGRAM) { + status = create_and_send_socket_request(socket, SI91X_SOCKET_UDP_CLIENT, NULL); + } + + // Verify the status of the socket operation and return errors if necessary + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + + // Update the socket state to "CONNECTED" and return success + si91x_socket->state = CONNECTED; + return SI91X_NO_ERROR; +} + +int sli_si91x_bind(int socket_id, const struct sockaddr *addr, socklen_t addr_len) +{ + errno = 0; + + // Retrieve the SI91X socket associated with the given socket ID. + sli_si91x_socket_t *si91x_socket = get_si91x_socket(socket_id); + const struct sockaddr_in *socket_address = (const struct sockaddr_in *)addr; + + // Validate socket, address, and address length + SET_ERRNO_AND_RETURN_IF_TRUE(si91x_socket == NULL || si91x_socket->state != INITIALIZED, EBADF); + SET_ERRNO_AND_RETURN_IF_TRUE( + (si91x_socket->local_address.sin6_family == AF_INET && addr_len < sizeof(struct sockaddr_in)) + || (si91x_socket->local_address.sin6_family == AF_INET6 && addr_len < sizeof(struct sockaddr_in6)), + EINVAL); + + SET_ERRNO_AND_RETURN_IF_TRUE(addr == NULL, EFAULT); + + // Check whether local port is already used or not + if (!is_port_available(socket_address->sin_port)) { + SET_ERROR_AND_RETURN(EADDRINUSE); + } + + // Copy the provided address to the local address structure + memcpy(&si91x_socket->local_address, + addr, + (addr_len > sizeof(struct sockaddr_in6)) ? sizeof(struct sockaddr_in6) : addr_len); + + si91x_socket->state = BOUND; + + // For UDP sockets, create and send a socket request. + if (si91x_socket->type == SOCK_DGRAM) { + sl_status_t socket_create_request_status = create_and_send_socket_request(socket_id, SI91X_SOCKET_UDP_CLIENT, NULL); + SOCKET_VERIFY_STATUS_AND_RETURN(socket_create_request_status, SI91X_NO_ERROR, SI91X_UNDEFINED_ERROR); + + si91x_socket->state = UDP_UNCONNECTED_READY; + } + + return SI91X_NO_ERROR; +} + +int sli_si91x_select(int nfds, + sl_si91x_fd_set *readfds, + sl_si91x_fd_set *writefds, + sl_si91x_fd_set *exceptfds, + const struct timeval *timeout, + sl_si91x_socket_select_callback_t callback) +{ + UNUSED_PARAMETER(exceptfds); // exceptfds is not supported by the firmware, so it is unused + sl_status_t status = SL_STATUS_OK; // Initialize status + uint32_t select_response_wait_time = 0; // Time to wait for the select response + + // Define a structure to hold the select request parameters + sl_si91x_socket_select_req_t request = { 0 }; + + // Check if all file descriptor sets are NULL + if ((readfds == NULL) && (writefds == NULL)) { + SET_ERROR_AND_RETURN(EINVAL); // Invalid argument, no sets specified + } + + // Check if the number of file descriptors (nfds) is within a valid range + if (nfds < 0 || nfds > NUMBER_OF_SOCKETS) { + SET_ERROR_AND_RETURN(EINVAL); // Invalid argument, nfds out of range + } + + // Check if the provided timeout is valid + if ((timeout != NULL) && ((timeout->tv_sec < 0) || (timeout->tv_usec < 0))) { + SET_ERROR_AND_RETURN(EINVAL); // Invalid argument, negative timeout + } + + // Loop through the provided file descriptor sets and populate the select request structure + for (uint8_t host_socket_index = 0; host_socket_index < nfds; host_socket_index++) { + const sli_si91x_socket_t *socket = + get_si91x_socket(host_socket_index); // Retrieve the si91x_socket associated with the index + + // Throw error if the socket file descriptor set is invalid + if (socket == NULL + && ((readfds != NULL && SL_SI91X_FD_ISSET(host_socket_index, readfds)) + || (writefds != NULL && SL_SI91X_FD_ISSET(host_socket_index, writefds)))) { + SET_ERROR_AND_RETURN(EBADF); // Bad file descriptor + } + + // The code will reach this if clause in the case of a socket being NULL and the socket being neither set in readfds nor writefds. + // Continue to next socket if this one is not in use + if (socket == NULL) { + continue; + } + + // Check if the socket is set for read operations in the readfds set + // Set the corresponding bit in the read file descriptor set + if ((readfds != NULL) && (SL_SI91X_FD_ISSET(host_socket_index, readfds))) { + request.read_fds.fd_array[0] |= (1U << socket->id); + } + + // Check if the socket is set for write operations in the writefds set + // Set the corresponding bit in the write file descriptor set + if ((writefds != NULL) && (SL_SI91X_FD_ISSET(host_socket_index, writefds))) { + request.write_fds.fd_array[0] |= (1U << socket->id); + } + + // Update the maximum file descriptor number encountered + if (request.num_fd <= socket->id) { + request.num_fd = (uint8_t)(socket->id + 1); + } + } + + // Handle timeout: If a timeout is provided, calculate the wait time + if (timeout != NULL) { + request.select_timeout.tv_sec = timeout->tv_sec; + request.select_timeout.tv_usec = timeout->tv_usec; + // Convert timeout to milliseconds and add extra wait time for the response + select_response_wait_time = ((request.select_timeout.tv_sec * 1000) + (request.select_timeout.tv_usec / 1000) + + SI91X_HOST_WAIT_FOR_SELECT_RSP); + } else { + // If no timeout is specified, set the request to indicate no timeout and wait indefinitely + request.no_timeout = 1; + select_response_wait_time = osWaitForever; + } + + // Get an available select ID from the internal table + sli_si91x_select_request_t *select_request = sli_si91x_get_available_select_id(); + // If no select ID is available, return an error + SET_ERRNO_AND_RETURN_IF_TRUE((select_request == NULL), EPERM); + // Assign the callback function for this select request + select_request->select_callback = callback; + + // Set the select_id in the request structure + request.select_id = select_request->select_id; + + // Send the select request asynchronously to the firmware + status = sl_si91x_driver_send_async_command(RSI_WLAN_REQ_SELECT_REQUEST, SI91X_SOCKET_CMD, &request, sizeof(request)); + if (status != SL_STATUS_OK) { + // If sending the command fails, clear the select ID and return + sli_si91x_clear_select_id(request.select_id); + } + // Verify that the command was sent successfully + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + + // If a callback was provided, return immediately (non-blocking) + if (callback != NULL) { + return SL_SI91X_RETURN_IMMEDIATELY; + } + + // Start measuring the time for the select operation + uint32_t start_time = osKernelGetTickCount(); + uint32_t elapsed_time = 0; + + do { + // Wait for the select response event (using the select_id) + uint32_t events = osEventFlagsWait(si91x_socket_select_events, + BIT(request.select_id), + osFlagsWaitAny, + (select_response_wait_time - elapsed_time)); + + // Handle cases where the wait times out or resources are unavailable + if (events == (uint32_t)osErrorTimeout || events == (uint32_t)osErrorResource) { + status = SL_STATUS_TIMEOUT; // Set status to timeout if no response was received + break; + } else { + status = SL_STATUS_OK; // Set status to OK if response was received + } + + // Check if the response data for the select request is available + if (select_request_table[request.select_id].response_data != NULL) { + break; // Exit the loop if response is received + } + + // Update the elapsed time + elapsed_time = sl_si91x_host_elapsed_time(start_time); + } while (elapsed_time <= select_response_wait_time); + + // If the select operation timed out or failed, clear the select ID and exit + if (status != SL_STATUS_OK) { + sli_si91x_clear_select_id(request.select_id); + } + // Verify the status and return if an error occurred + SOCKET_VERIFY_STATUS_AND_RETURN(status, SL_STATUS_OK, SI91X_UNDEFINED_ERROR); + + // Convert and save the firmware status from the select request + convert_and_save_firmware_status(select_request_table[request.select_id].frame_status); + + // Initialize the total file descriptor count + int32_t total_fd_set_count = -1; + // If the firmware status is OK, process the select response and update the file descriptor sets + if (select_request_table[request.select_id].frame_status == SL_STATUS_OK) { + total_fd_set_count = + handle_select_response(select_request_table[request.select_id].response_data, readfds, writefds, exceptfds); + } + + // Free the memory allocated for the response data + free(select_request_table[request.select_id].response_data); + // Clear the select ID in the internal table + sli_si91x_clear_select_id(request.select_id); + + // Return the total number of file descriptors set in the read, write, or exception sets + return total_fd_set_count; +} + +static sli_si91x_select_request_t *sli_si91x_get_available_select_id(void) +{ + // Check if there are any available select request entries. + if (sli_si91x_max_select_count == 0) { + return NULL; // Return NULL if no requests can be processed. + } + + // Enter atomic section to ensure thread-safe access to the select_request_table. + CORE_irqState_t state = CORE_EnterAtomic(); + + // Iterate over the select request table to find an available entry. + for (unsigned int i = 0; i < sli_si91x_max_select_count; i++) { + // Check if the current entry is not in use. + if (!select_request_table[i].in_use) { + // Assign the current index as the select ID. + select_request_table[i].select_id = i; + + // Mark the entry as in use. + select_request_table[i].in_use = 1; + + // Exit atomic section after modifying the entry. + CORE_ExitAtomic(state); + + // Return the pointer to the available select request entry. + return &select_request_table[i]; + } + } + + // Exit atomic section if no available entry was found. + CORE_ExitAtomic(state); + + // Return NULL to indicate that no available select ID was found. + return NULL; +} + +static void sli_si91x_clear_select_id(uint8_t id) +{ + // Check if the select request table is empty or if the provided ID is out of range. + if (sli_si91x_max_select_count == 0 || id >= sli_si91x_max_select_count) { + return; // If no requests or invalid ID, exit early. + } + + // Enter atomic section to ensure thread-safe access to the select_request_table. + CORE_irqState_t state = CORE_EnterAtomic(); + + // Mark the entry corresponding to the provided ID as not in use. + select_request_table[id].in_use = 0; + + // Exit atomic section after the operation is complete. + CORE_ExitAtomic(state); +} + +void sli_si91x_set_socket_event(uint32_t event_mask) +{ + osEventFlagsSet(si91x_socket_events, event_mask); +} + +sl_status_t sli_si91x_flush_select_request_table(uint16_t error_code) +{ + // Iterate over all entries in the select_request_table + for (unsigned int i = 0; i < sli_si91x_max_select_count; i++) { + // Check if the current select_request_table entry is in use + if (select_request_table[i].in_use) { + // If a callback function exists for this entry, it is async + if (select_request_table[i].select_callback != NULL) { + select_request_table[i].in_use = 0; // Mark as not in use + } else { + // If there is no callback, the request needs to be reset and so the response data pointer is cleared, indicating no data is available + select_request_table[i].response_data = NULL; + // Set the frame status to indicate rejoin failure in the request + select_request_table[i].frame_status = error_code; + // Set the appropriate event flag for the socket associated with the select_id + osEventFlagsSet(si91x_socket_select_events, BIT(select_request_table[i].select_id)); + } + } + } + // Return SL_STATUS_OK to indicate the function completed successfully + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/src/sl_rsi_utility.c b/wiseconnect/components/device/silabs/si91x/wireless/src/sl_rsi_utility.c new file mode 100644 index 000000000..da5166e82 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/src/sl_rsi_utility.c @@ -0,0 +1,2010 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_protocol_types.h" +#include "sl_si91x_constants.h" +#include "sl_si91x_driver.h" +#include "sl_wifi_constants.h" +#include "sl_wifi_credentials.h" +#include "sl_status.h" +#include "sl_constants.h" +#include "sl_wifi_types.h" +#include "sl_rsi_utility.h" +#include "cmsis_os2.h" // CMSIS RTOS2 +#include "sl_si91x_types.h" +#include "sl_si91x_core_utilities.h" +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +#include "sl_si91x_socket_constants.h" +#include "sl_si91x_socket_utility.h" +#endif +#include "em_core.h" +#include +#include "assert.h" + +/****************************************************** + * Macro Declarations + ******************************************************/ +// Macro to check the status and return it if it's not SL_STATUS_OK +#define VERIFY_STATUS(s) \ + do { \ + if (s != SL_STATUS_OK) \ + return s; \ + } while (0) + +// WLAN Management Frame Sub-Type +#define SLI_WIFI_FRAME_SUBTYPE_MASK 0xf0 // WLAN Management Frame Sub-Type Mask +#define SLI_WIFI_FRAME_SUBTYPE_PROBE_RESP 0x50 // WLAN Management Frame Sub-Type Probe Response Frame +#define SLI_WIFI_FRAME_SUBTYPE_BEACON 0x80 // WLAN Management Frame Sub-Type Beacon Frame +#define SLI_WIFI_MINIMUM_FRAME_LENGTH 36 // Minimum Frame Length of WLAN Management Frame +#define SLI_WIFI_HARDWARE_ADDRESS_LENGTH 6 // Hardware Address Length + +// WLAN Information Element Type +#define SLI_WLAN_TAG_SSID 0 // WLAN Information Element Type SSID +#define SLI_WLAN_TAG_RSN 48 // WLAN Robust Security Network Information Element +#define SLI_WLAN_TAG_VENDOR_SPECIFIC 221 // WLAN Vendor Specific Information Element + +// Authentication key Management Type +#define SLI_AUTH_KEY_MGMT_UNSPEC_802_1X 0x000FAC01 // Unspecified Authentication key Management Type +#define SLI_AUTH_KEY_MGMT_PSK_OVER_802_1X 0x000FAC02 // PSK Authentication key Management Type +#define SLI_AUTH_KEY_MGMT_802_1X_SHA256 0x000FAC05 // SHA256 Authentication key Management Type +#define SLI_AUTH_KEY_MGMT_PSK_SHA256 0x000FAC06 // PSK SHA256 Authentication key Management Type +#define SLI_AUTH_KEY_MGMT_SAE 0x000FAC08 // SAE Authentication key Management Type +#define SLI_AUTH_KEY_MGMT_FT_SAE 0x000FAC09 // FT_SAE Authentication key Management Type + +// Authentication key Management Type Flags +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA 0x00000001 // WPA AKM Type +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA2 0x00000002 // WPA2 AKM Type +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA_PSK 0x00000004 // WPA_PSK AKM Type +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA2_PSK 0x00000008 // WPA2_PSK AKM Type +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_SAE 0x00010000 // SAE AKM Type +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_FT_SAE 0x00100000 // FT_SAE AKM Type +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_802_1X_SHA256 0x00020000 // SHA256 AKM Type +#define SLI_WLAN_AUTH_KEY_MGMT_TYPE_PSK_SHA256 0x00040000 // PSK_SHA256 AKM Type + +/// Task register ID to save firmware status +#define SLI_FW_STATUS_STORAGE_INVALID_INDEX 0xFF // Invalid index for firmware status storage + +/****************************************************** + * Local Type Declarations + ******************************************************/ +// WLAN Frame +typedef struct { + uint8_t fc[2]; // Frame Control + uint8_t duration[2]; // Duration + uint8_t da[SLI_WIFI_HARDWARE_ADDRESS_LENGTH]; // Destination Address + uint8_t sa[SLI_WIFI_HARDWARE_ADDRESS_LENGTH]; // Source Address + uint8_t bssid[SLI_WIFI_HARDWARE_ADDRESS_LENGTH]; // BSS Id + uint8_t sc[2]; // Sequence Control Id + uint8_t timestamp[8]; // Time Stamp + uint8_t bi[2]; // Beacon Interval + uint8_t ci[2]; // Capability Information + uint8_t tagged_info[]; // Variable Information Elememt +} sli_wifi_data_frame_t; + +// WLAN Information Element +typedef struct { + uint8_t tag; // Information Element Tag Id + uint8_t data_length; // Information Element Data Length + uint8_t data[]; // Information Element Data +} sli_wifi_data_tagged_info_t; + +// Cipher suite +typedef struct { + uint8_t cs_oui[3]; // Cipher Suite OUI + uint8_t cs_type; // Cipher Suite Type +} sli_wlan_cipher_suite_t; + +// WLAN Robust Security Network Information Element +typedef struct { + uint8_t version[2]; // RSN Version + sli_wlan_cipher_suite_t gcs; // Group cipher suite + uint8_t pcsc[2]; // Pairwise cipher suite count + uint8_t pcsl[]; // Pairwise cipher suite list +} sli_wlan_rsn_element_t; + +// WLAN Vendor Specific Information Element +typedef struct { + uint8_t oui[3]; // Vendor OUI + uint8_t vs_oui; // Vendor specific OUI + uint8_t type; // WPA Information Element + uint8_t wpa_version[2]; // WPA Version + sli_wlan_cipher_suite_t mcs; // Multicast Cipher Suite + uint8_t ucsc; // Unicast Cipher Suite List Count + uint8_t ucsl[]; // Unicast Cipher Suite List +} sli_wlan_vendor_specific_element_t; + +// Scan Information +typedef struct sli_scan_info_s { + struct sli_scan_info_s *next; + uint8_t channel; ///< Channel number of the AP + uint8_t security_mode; ///< Security mode of the AP + uint8_t rssi; ///< RSSI value of the AP + uint8_t network_type; ///< AP network type + uint8_t ssid[34]; ///< SSID of the AP + uint8_t bssid[SLI_WIFI_HARDWARE_ADDRESS_LENGTH]; ///< BSSID of the AP +} sli_scan_info_t; + +/****************************************************** + * Variable Declarations + ******************************************************/ +osThreadId_t si91x_thread = 0; +osThreadId_t si91x_event_thread = 0; +osEventFlagsId_t si91x_events = 0; +osEventFlagsId_t si91x_bus_events = 0; +osEventFlagsId_t si91x_async_events = 0; +osMutexId_t malloc_free_mutex = 0; + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +osMutexId_t side_band_crypto_mutex = 0; +#endif + +sli_si91x_command_queue_t cmd_queues[SI91X_CMD_MAX]; +sl_si91x_buffer_queue_t sli_tx_data_queue; + +static bool sli_si91x_packet_status = 0; + +extern bool device_initialized; + +// Declaration of external functions +extern void si91x_bus_thread(void *args); +extern void si91x_event_handler_thread(void *args); +sl_status_t sl_si91x_host_power_cycle(void); +void convert_performance_profile_to_power_save_command(sl_si91x_performance_profile_t profile, + sl_si91x_power_save_request_t *power_save_request); +extern sl_status_t sl_create_generic_rx_packet_from_params(sli_si91x_queue_packet_t **queue_packet, + sl_wifi_buffer_t **packet_buffer, + uint16_t packet_id, + uint8_t flags, + void *sdk_context, + uint16_t frame_status); +void sl_debug_log(const char *format, ...); + +extern sli_si91x_performance_profile_t performance_profile; + +// NOTE: Boolean value determines whether firmware automatically closes the TCP socket in case of receiving termination from remote node or not. +static bool tcp_auto_close_enabled; + +// This value will be used in connect request/ AP configurations to set the TX power of the module +static sl_wifi_max_tx_power_t wifi_max_tx_power = { + .scan_tx_power = 0x1f, //Default power value set to max value supported in dBm + .join_tx_power = 0x1f, //Default power value set to max value supported in dBm +}; + +static sl_wifi_rate_t saved_wifi_data_rate = SL_WIFI_AUTO_RATE; + +static sl_wifi_ap_configuration_t ap_configuration; + +static bool is_card_ready_required = true; + +sl_si91x_performance_profile_t current_performance_profile = HIGH_PERFORMANCE; + +static sl_si91x_boot_configuration_t saved_boot_configuration = { 0 }; + +static sl_si91x_coex_mode_t coex_mode = 0; + +static sli_scan_info_t *scan_info_database = NULL; + +/****************************************************** + * Internal Function Declarations + ******************************************************/ +sl_status_t sli_fw_status_storage_index_init(void) +{ + sl_status_t status = SL_STATUS_OK; + + // Declare a variable to store the current interrupt state + CORE_DECLARE_IRQ_STATE; + + // Enter a critical section by disabling interrupts + // This ensures that the following operations are executed atomically + CORE_ENTER_CRITICAL(); +#ifdef SL_CATALOG_KERNEL_PRESENT + // Check if the code is running in a thread context & task register index is invalid + if (osThreadGetId() != NULL && sli_fw_status_storage_index == SLI_FW_STATUS_STORAGE_INVALID_INDEX) { + // Create a new task register id + status = sli_osTaskRegisterNew(&sli_fw_status_storage_index); + VERIFY_STATUS_AND_RETURN(status); + } +#endif + CORE_EXIT_CRITICAL(); + return status; +} + +// Function to update a existing entry or create new entry for scan results database +static sli_scan_info_t *sli_update_or_create_scan_info_element(const sli_scan_info_t *info) +{ + sli_scan_info_t *element = NULL; + + element = scan_info_database; + while (NULL != element) { + if (0 == memcmp(info->bssid, element->bssid, SLI_WIFI_HARDWARE_ADDRESS_LENGTH)) { + element->channel = element->channel; + element->security_mode = element->security_mode; + element->rssi = element->rssi; + element->network_type = element->network_type; + memcpy(element->ssid, info->ssid, 34); + break; + } + element = element->next; + } + + if (NULL == element) { + element = malloc(sizeof(sli_scan_info_t)); + memcpy(element, info, sizeof(sli_scan_info_t)); + element->next = NULL; + return element; + } + + return NULL; +} + +// Function to store a given scan info element in scan results database +static void sli_store_scan_info_element(sli_scan_info_t *info) +{ + sli_scan_info_t *element = NULL; + sli_scan_info_t *head = NULL; + sli_scan_info_t *tail = NULL; + + if (NULL == info) { + return; + } + + element = sli_update_or_create_scan_info_element(info); + if (NULL == element) { + return; + } + + if (NULL == scan_info_database) { + scan_info_database = element; + return; + } + + tail = scan_info_database; + while (NULL != tail) { + if (element->rssi < tail->rssi) { + element->next = tail; + if (NULL == head) { + scan_info_database = element; + } else { + head->next = element; + } + break; + } + + head = tail; + tail = tail->next; + + if (NULL == tail) { + head->next = element; + } + } + + return; +} + +// Function to identify Authentication Key Management Type +static uint32_t sli_get_key_management_info(const sli_wlan_cipher_suite_t *akms, const uint16_t akmsc) +{ + uint32_t key_mgmt = 0; + uint32_t oui_type; + + if (NULL == akms) { + return 0; + } + + for (int i = 0; i < akmsc; i++) { + oui_type = ((akms[i].cs_oui[0] << 24) | (akms[i].cs_oui[1] << 16) | (akms[i].cs_oui[2] << 8) | akms[0].cs_type); + + switch (oui_type) { + case SLI_AUTH_KEY_MGMT_UNSPEC_802_1X: + key_mgmt |= SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA | SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA2; + break; + case SLI_AUTH_KEY_MGMT_PSK_OVER_802_1X: + key_mgmt |= SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA_PSK | SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA2_PSK; + break; + case SLI_AUTH_KEY_MGMT_802_1X_SHA256: + key_mgmt |= SLI_WLAN_AUTH_KEY_MGMT_TYPE_802_1X_SHA256; + break; + case SLI_AUTH_KEY_MGMT_PSK_SHA256: + key_mgmt |= SLI_WLAN_AUTH_KEY_MGMT_TYPE_PSK_SHA256; + break; + case SLI_AUTH_KEY_MGMT_SAE: + key_mgmt |= SLI_WLAN_AUTH_KEY_MGMT_TYPE_SAE; + break; + case SLI_AUTH_KEY_MGMT_FT_SAE: + key_mgmt |= SLI_WLAN_AUTH_KEY_MGMT_TYPE_FT_SAE; + break; + default: + break; + } + } + return key_mgmt; +} + +// Helper function to process RSN element +static void process_rsn_element(const sli_wifi_data_tagged_info_t *info, sli_scan_info_t *scan_info) +{ + scan_info->security_mode = SL_WIFI_WPA2_ENTERPRISE; + sli_wlan_rsn_element_t *rsn = (sli_wlan_rsn_element_t *)info->data; + uint16_t pcsc = (uint16_t)(rsn->pcsc[0] | (rsn->pcsc[1] << 8)); + uint8_t *akmslc = (rsn->pcsl + (pcsc * sizeof(sli_wlan_cipher_suite_t))); + uint16_t akmsc = (uint16_t)(akmslc[0] | (akmslc[1] << 8)); + const sli_wlan_cipher_suite_t *akms = (sli_wlan_cipher_suite_t *)(akmslc + 2); + uint8_t wlan_gcs_oui[3] = { 0x00, 0x0F, 0xAC }; + + SL_DEBUG_LOG("RSN OUI %02x:%02x:%02x.\n", rsn->gcs.cs_oui[0], rsn->gcs.cs_oui[1], rsn->gcs.cs_oui[2]); + SL_DEBUG_LOG("Pairwise cipher suite count: %u.\n", pcsc); + + if (!memcmp(rsn->gcs.cs_oui, wlan_gcs_oui, 3)) { + scan_info->security_mode = SL_WIFI_WPA2; + uint32_t key = sli_get_key_management_info((const sli_wlan_cipher_suite_t *)akms, (const uint16_t)akmsc); + + if (akms[0].cs_type == 1) { + scan_info->security_mode = SL_WIFI_WPA2_ENTERPRISE; + } + + if (key & SLI_WLAN_AUTH_KEY_MGMT_TYPE_802_1X_SHA256) { + scan_info->security_mode = SL_WIFI_WPA3_ENTERPRISE; + if ((key & SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA) || (key & SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA2)) { + scan_info->security_mode = SL_WIFI_WPA3_TRANSITION_ENTERPRISE; + } + } + + if (key & SLI_WLAN_AUTH_KEY_MGMT_TYPE_SAE) { + scan_info->security_mode = SL_WIFI_WPA3; + if ((key & SLI_WLAN_AUTH_KEY_MGMT_TYPE_PSK_SHA256) || (key & SLI_WLAN_AUTH_KEY_MGMT_TYPE_WPA2_PSK)) { + scan_info->security_mode = SL_WIFI_WPA3_TRANSITION; + } + } + } +} + +// Helper function to process Vendor Specific element +static void process_vendor_specific_element(const sli_wifi_data_tagged_info_t *info, sli_scan_info_t *scan_info) +{ + sli_wlan_vendor_specific_element_t *vendor = (sli_wlan_vendor_specific_element_t *)info->data; + uint8_t wlan_oui[3] = { 0x00, 0x50, 0xF2 }; + + if ((!memcmp(vendor->oui, wlan_oui, 3)) && (vendor->vs_oui == 0x01) + && ((scan_info->security_mode == SL_WIFI_OPEN) || (scan_info->security_mode == SL_WIFI_WEP))) { + scan_info->security_mode = SL_WIFI_WPA; + uint8_t *list_count = (vendor->ucsl + (sizeof(sli_wlan_cipher_suite_t) * vendor->ucsc)); + uint16_t akmsc = (uint16_t)(list_count[0] | (list_count[1] << 8)); + const sli_wlan_cipher_suite_t *akms = (sli_wlan_cipher_suite_t *)(list_count + 2); + + if ((0 != akmsc) && (akms[akmsc - 1].cs_type == 1)) { + scan_info->security_mode = SL_WIFI_WPA_ENTERPRISE; + } + } +} + +// Function to parse Information elements in WiFi Beacon or Probe response frames +static void sli_process_tag_info(const sli_wifi_data_tagged_info_t *info, sli_scan_info_t *scan_info) +{ + switch (info->tag) { + case SLI_WLAN_TAG_SSID: + memcpy(scan_info->ssid, info->data, info->data_length); + scan_info->ssid[info->data_length] = 0; + break; + + case SLI_WLAN_TAG_RSN: + process_rsn_element(info, scan_info); + break; + + case SLI_WLAN_TAG_VENDOR_SPECIFIC: + process_vendor_specific_element(info, scan_info); + break; + + default: + break; + } + + return; +} + +// Function to identify expected scan result based on filter +static bool sli_filter_scan_info(const sli_scan_info_t *scan_info, + const sl_wifi_extended_scan_result_parameters_t *extended_scan_parameters) +{ + if (NULL == scan_info) { + return false; + } + + if ((NULL != extended_scan_parameters->channel_filter) + && (*(extended_scan_parameters->channel_filter) != scan_info->channel)) { + return false; + } + + if ((NULL != extended_scan_parameters->security_mode_filter) + && (*(extended_scan_parameters->security_mode_filter) != scan_info->security_mode)) { + return false; + } + + if ((NULL != extended_scan_parameters->rssi_filter) + && (*(extended_scan_parameters->rssi_filter) <= scan_info->rssi)) { + return false; + } + + if ((NULL != extended_scan_parameters->network_type_filter) + && (*(extended_scan_parameters->network_type_filter) != scan_info->network_type)) { + return false; + } + + return true; +} + +/****************************************************** + * Internal Function Declarations + ******************************************************/ +// Function to Parse the Beacon and Probe response Frames +void sli_handle_wifi_beacon(sl_si91x_packet_t *packet) +{ + uint8_t subtype = 0; + uint16_t recv_freq = 0; + sli_wifi_data_frame_t *wifi_frame = (sli_wifi_data_frame_t *)packet->data; + sli_scan_info_t scan_info = { 0 }; + uint16_t ies_length = 0; + + recv_freq = packet->desc[9]; + recv_freq = (recv_freq << 8) | packet->desc[8]; + scan_info.rssi = (~packet->desc[10]); + scan_info.channel = packet->desc[11]; + + // Check for ESS bit and TBSS status bit in capability info + // 1 in ESS bit indicates that the transmitter is an AP + if (1 == (wifi_frame->ci[0] & 0x03)) { + scan_info.network_type = 1; + } else { + scan_info.network_type = 0; + } + + if (wifi_frame->ci[0] & 0x08) { + scan_info.security_mode = SL_WIFI_WEP; + } else { + scan_info.security_mode = SL_WIFI_OPEN; + } + + subtype = wifi_frame->fc[0] & SLI_WIFI_FRAME_SUBTYPE_MASK; + switch (subtype) { + case SLI_WIFI_FRAME_SUBTYPE_PROBE_RESP: + case SLI_WIFI_FRAME_SUBTYPE_BEACON: { + if (packet->length <= SLI_WIFI_MINIMUM_FRAME_LENGTH) { + return; + } + ies_length = packet->length - SLI_WIFI_MINIMUM_FRAME_LENGTH; + + memcpy(scan_info.bssid, wifi_frame->bssid, SLI_WIFI_HARDWARE_ADDRESS_LENGTH); + + sli_wifi_data_tagged_info_t *info = (sli_wifi_data_tagged_info_t *)wifi_frame->tagged_info; + while (0 != ies_length) { + sli_process_tag_info(info, &scan_info); + ies_length -= (sizeof(sli_wifi_data_tagged_info_t) + info->data_length); + info = (sli_wifi_data_tagged_info_t *)&(info->data[info->data_length]); + + if (ies_length <= sizeof(sli_wifi_data_tagged_info_t)) { + ies_length = 0; + } + } + + sli_store_scan_info_element(&scan_info); + } break; + default: + return; + } + + return; +} + +// Function to get all or filtered scan results from scan result database +sl_status_t sli_wifi_get_stored_scan_results(sl_wifi_interface_t interface, + sl_wifi_extended_scan_result_parameters_t *extended_scan_parameters) +{ + UNUSED_PARAMETER(interface); + if (NULL == extended_scan_parameters) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_wifi_extended_scan_result_t *scan_results = extended_scan_parameters->scan_results; + uint16_t *result_count = extended_scan_parameters->result_count; + uint16_t length = extended_scan_parameters->array_length; + sli_scan_info_t *scan_info = scan_info_database; + + if ((NULL == scan_results) || (NULL == result_count) || (0 == length)) { + return SL_STATUS_INVALID_PARAMETER; + } + *result_count = 0; + + while ((0 != length) && (NULL != scan_info)) { + if (true == sli_filter_scan_info(scan_info, extended_scan_parameters)) { + scan_results[*result_count].rf_channel = scan_info->channel; + scan_results[*result_count].security_mode = scan_info->security_mode; + scan_results[*result_count].rssi = scan_info->rssi; + scan_results[*result_count].network_type = scan_info->network_type; + memcpy(scan_results[*result_count].bssid, scan_info->bssid, SLI_WIFI_HARDWARE_ADDRESS_LENGTH); + memcpy(scan_results[*result_count].ssid, scan_info->ssid, 34); + (*result_count)++; + length--; + } + scan_info = scan_info->next; + } + + return SL_STATUS_OK; +} + +// Function to Clean up all the scan results in scan result database +void sli_wifi_flush_scan_results_database(void) +{ + sli_scan_info_t *scan_info = scan_info_database; + sli_scan_info_t *node = NULL; + + while (NULL != scan_info) { + node = scan_info; + scan_info = scan_info->next; + free(node); + } + scan_info_database = NULL; + + return; +} + +/****************************************************** + * Function Declarations + ******************************************************/ +void save_wifi_current_performance_profile(const sl_wifi_performance_profile_t *profile) +{ + SL_ASSERT(profile != NULL); + memcpy(&performance_profile.wifi_performance_profile, profile, sizeof(sl_wifi_performance_profile_t)); + + performance_profile.coex_mode = get_coex_mode(); +} + +// Get the current Wi-Fi performance profile +void get_wifi_current_performance_profile(sl_wifi_performance_profile_t *profile) +{ + SL_ASSERT(profile != NULL); + memcpy(profile, &performance_profile.wifi_performance_profile, sizeof(sl_wifi_performance_profile_t)); +} + +// Get the coexistence performance profile based on the current coexistence mode +void get_coex_performance_profile(sl_si91x_performance_profile_t *profile) +{ + SL_ASSERT(profile != NULL); + uint8_t mode_decision = 0; + sl_si91x_coex_mode_t coex_mode = performance_profile.coex_mode; + if (coex_mode == SL_SI91X_WLAN_ONLY_MODE) { // Treat SL_SI91X_WLAN_ONLY_MODE as SL_SI91X_WLAN_MODE + coex_mode = SL_SI91X_WLAN_MODE; + } + // Determine the mode decision based on the coexistence mode + switch (coex_mode) { + case SL_SI91X_WLAN_MODE: { + // Wi-Fi only mode + mode_decision = (uint8_t)((performance_profile.wifi_performance_profile.profile << 4) + | (performance_profile.wifi_performance_profile.profile)); + } break; + case SL_SI91X_BLUETOOTH_MODE: + case SL_SI91X_BLE_MODE: + case SL_SI91X_DUAL_MODE: { + // Bluetooth only or dual-mode (BT + Wi-Fi) mode + mode_decision = (uint8_t)((performance_profile.bt_performance_profile.profile << 4) + | (performance_profile.bt_performance_profile.profile)); + } break; + case SL_SI91X_WLAN_BLUETOOTH_MODE: + case SL_SI91X_WLAN_DUAL_MODE: + case SL_SI91X_WLAN_BLE_MODE: { + // Wi-Fi + Bluetooth mode + mode_decision = (uint8_t)((performance_profile.wifi_performance_profile.profile << 4) + | (performance_profile.bt_performance_profile.profile)); + } break; + default: + break; + } + + // Determine the performance profile based on the mode decision + switch (mode_decision) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x10: + case 0x20: + case 0x30: + case 0x40: { + *profile = HIGH_PERFORMANCE; // High performance mode + } break; + case 0x11: + case 0x12: + case 0x31: + case 0x13: + case 0x14: + case 0x41: { + *profile = ASSOCIATED_POWER_SAVE; // Power save mode + } break; + case 0x22: + case 0x21: + case 0x32: + case 0x23: + case 0x42: + case 0x24: { + *profile = ASSOCIATED_POWER_SAVE_LOW_LATENCY; // Low latency power save mode + } break; + case 0x33: { + *profile = DEEP_SLEEP_WITHOUT_RAM_RETENTION; // Power save mode + } break; + case 0x44: { + *profile = DEEP_SLEEP_WITH_RAM_RETENTION; // Power save mode with RAM retention + } break; + default: { + // Do nothing + } break; + } + return; +} + +void reset_coex_current_performance_profile(void) +{ + memset(&performance_profile, 0, sizeof(sli_si91x_performance_profile_t)); +} + +void save_boot_configuration(const sl_si91x_boot_configuration_t *boot_configuration) +{ + memcpy(&saved_boot_configuration, boot_configuration, sizeof(sl_si91x_boot_configuration_t)); +} + +void get_saved_boot_configuration(sl_si91x_boot_configuration_t *boot_configuration) +{ + memcpy(boot_configuration, &saved_boot_configuration, sizeof(sl_si91x_boot_configuration_t)); +} + +void save_bt_current_performance_profile(const sl_bt_performance_profile_t *profile) +{ + SL_ASSERT(profile != NULL); + memcpy(&performance_profile.bt_performance_profile, profile, sizeof(sl_bt_performance_profile_t)); +} + +void get_bt_current_performance_profile(sl_bt_performance_profile_t *profile) +{ + SL_ASSERT(profile != NULL); + memcpy(profile, &performance_profile.bt_performance_profile, sizeof(sl_bt_performance_profile_t)); +} + +void save_tcp_auto_close_choice(bool is_tcp_auto_close_enabled) +{ + tcp_auto_close_enabled = is_tcp_auto_close_enabled; +} + +bool is_tcp_auto_close_enabled() +{ + return tcp_auto_close_enabled; +} + +void save_max_tx_power(uint8_t max_scan_tx_power, uint8_t max_join_tx_power) +{ + wifi_max_tx_power.scan_tx_power = max_scan_tx_power; + wifi_max_tx_power.join_tx_power = max_join_tx_power; +} + +sl_wifi_max_tx_power_t get_max_tx_power() +{ + return wifi_max_tx_power; +} + +void reset_max_tx_power() +{ + wifi_max_tx_power.scan_tx_power = 0x1f; + wifi_max_tx_power.join_tx_power = 0x1f; +} + +void set_card_ready_required(bool card_ready_required) +{ + is_card_ready_required = card_ready_required; +} + +bool get_card_ready_required() +{ + return is_card_ready_required; +} + +void save_coex_mode(sl_si91x_coex_mode_t mode) +{ + coex_mode = mode; +} + +sl_si91x_coex_mode_t get_coex_mode(void) +{ + return coex_mode; +} + +sl_status_t convert_si91x_wifi_client_info(sl_wifi_client_info_response_t *client_info_response, + const sl_si91x_client_info_response *sl_si91x_client_info_response) +{ + + SL_WIFI_ARGS_CHECK_NULL_POINTER(sl_si91x_client_info_response); + SL_WIFI_ARGS_CHECK_NULL_POINTER(client_info_response); + + client_info_response->client_count = + (uint8_t)(sl_si91x_client_info_response->sta_count[0] | sl_si91x_client_info_response->sta_count[1] << 8); + + for (uint8_t station_index = 0; station_index < client_info_response->client_count; station_index++) { + const uint8_t *si91x_ip_address; + uint8_t *sl_ip_address; + + sl_wifi_client_info_t *sl_client_info = &client_info_response->client_info[station_index]; + const sl_si91x_station_info_t *si91x_client_info = &sl_si91x_client_info_response->sta_info[station_index]; + + uint8_t ip_address_size = (uint8_t)(si91x_client_info->ip_version[0] | si91x_client_info->ip_version[1] << 8); + + si91x_ip_address = ip_address_size == SL_IPV4_ADDRESS_LENGTH ? si91x_client_info->ip_address.ipv4_address + : si91x_client_info->ip_address.ipv6_address; + sl_ip_address = ip_address_size == SL_IPV4_ADDRESS_LENGTH ? sl_client_info->ip_address.ip.v4.bytes + : sl_client_info->ip_address.ip.v6.bytes; + + sl_client_info->ip_address.type = ip_address_size == SL_IPV4_ADDRESS_LENGTH ? SL_IPV4 : SL_IPV6; + + memcpy(&sl_client_info->mac_adddress, si91x_client_info->mac, sizeof(sl_mac_address_t)); + memcpy(sl_ip_address, si91x_ip_address, ip_address_size); + } + + return SL_STATUS_OK; +} + +sl_wifi_event_t convert_si91x_event_to_sl_wifi_event(rsi_wlan_cmd_response_t command, uint16_t frame_status) +{ + // Define a constant indicating a fail indication event + const sl_wifi_event_t fail_indication = (frame_status != RSI_SUCCESS) ? SL_WIFI_EVENT_FAIL_INDICATION : 0; + + // Switch-case to map SI91x events to SL Wi-Fi events + switch (command) { + case RSI_WLAN_RSP_BG_SCAN: + case RSI_WLAN_RSP_SCAN: + return SL_WIFI_SCAN_RESULT_EVENT | fail_indication; + case RSI_WLAN_RSP_JOIN: + return SL_WIFI_JOIN_EVENT | fail_indication; + case RSI_WLAN_RSP_GET_STATS: + if (frame_status != RSI_SUCCESS) { + return SL_WIFI_STATS_RESPONSE_EVENTS | fail_indication; + } + return SL_WIFI_STATS_EVENT; + case RSI_WLAN_RSP_RX_STATS: + if (frame_status != RSI_SUCCESS) { + return SL_WIFI_STATS_RESPONSE_EVENTS | fail_indication; + } + return SL_WIFI_STATS_ASYNC_EVENT; + case RSI_WLAN_RATE_RSP_STATS: + if (frame_status != RSI_SUCCESS) { + return SL_WIFI_STATS_RESPONSE_EVENTS | fail_indication; + } + return SL_WIFI_STATS_TEST_MODE_EVENT; + case RSI_WLAN_RSP_EXT_STATS: + if (frame_status != RSI_SUCCESS) { + return SL_WIFI_STATS_RESPONSE_EVENTS | fail_indication; + } + return SL_WIFI_STATS_ADVANCE_EVENT; + case RSI_WLAN_RSP_MODULE_STATE: + if (frame_status != RSI_SUCCESS) { + return SL_WIFI_STATS_RESPONSE_EVENTS | fail_indication; + } + return SL_WIFI_STATS_MODULE_STATE_EVENT; + case RSI_WLAN_RSP_HTTP_OTAF: + return SL_WIFI_HTTP_OTA_FW_UPDATE_EVENT | fail_indication; + case RSI_WLAN_RSP_CLIENT_CONNECTED: + return SL_WIFI_CLIENT_CONNECTED_EVENT | fail_indication; + case RSI_WLAN_RSP_CLIENT_DISCONNECTED: + return SL_WIFI_CLIENT_DISCONNECTED_EVENT | fail_indication; + case RSI_WLAN_RSP_TWT_ASYNC: + if (frame_status == RSI_SUCCESS) { + return SL_WIFI_TWT_RESPONSE_EVENT; + } else { + return SL_WIFI_TWT_RESPONSE_EVENT | (frame_status << 16); + } + case RSI_WLAN_RSP_TRANSCEIVER_TX_DATA_STATUS: + return SL_WIFI_TRANSCEIVER_TX_DATA_STATUS_CB | fail_indication; + case SL_SI91X_WIFI_RX_DOT11_DATA: + return SL_WIFI_TRANSCEIVER_RX_DATA_RECEIVE_CB | fail_indication; + default: + return SL_WIFI_INVALID_EVENT; + } +} + +sl_status_t save_sl_wifi_rate(sl_wifi_rate_t transfer_rate) +{ + // Check if the provided transfer rate is valid + if (transfer_rate == SL_WIFI_RATE_INVALID) { + return SL_STATUS_INVALID_CONFIGURATION; + } + + saved_wifi_data_rate = transfer_rate; + + return SL_STATUS_OK; +} + +sl_status_t get_saved_sl_wifi_rate(sl_wifi_rate_t *transfer_rate) +{ + SL_WIFI_ARGS_CHECK_NULL_POINTER(transfer_rate); + + *transfer_rate = saved_wifi_data_rate; + return SL_STATUS_OK; +} + +void reset_sl_wifi_rate() +{ + saved_wifi_data_rate = 0; +} + +sl_status_t save_ap_configuration(const sl_wifi_ap_configuration_t *wifi_ap_configuration) +{ + // Check if the input pointer is valid + SL_WIFI_ARGS_CHECK_NULL_POINTER(wifi_ap_configuration); + ap_configuration = *wifi_ap_configuration; + + return SL_STATUS_OK; +} + +sl_status_t get_saved_ap_configuration(sl_wifi_ap_configuration_t *wifi_ap_configuration) +{ + SL_WIFI_ARGS_CHECK_NULL_POINTER(wifi_ap_configuration); + *wifi_ap_configuration = ap_configuration; + + return SL_STATUS_OK; +} + +void reset_ap_configuration() +{ + // Initialize the ap_configuration structure with zeros + ap_configuration = (sl_wifi_ap_configuration_t){ 0 }; +} + +sl_status_t get_rate_protocol_and_data_rate(const uint8_t data_rate, + sl_wifi_rate_protocol_t *rate_protocol, + sl_wifi_rate_t *mask) +{ + // Map the provided data_rate to a rate_protocol and set the mask accordingly + switch (data_rate) { + case SL_WIFI_AUTO_RATE: { + *rate_protocol = SL_WIFI_RATE_PROTOCOL_AUTO; + break; + } + case SL_WIFI_RATE_11B_1: + case SL_WIFI_RATE_11B_2: + case SL_WIFI_RATE_11B_5_5: + case SL_WIFI_RATE_11B_11: { + *rate_protocol = SL_WIFI_RATE_PROTOCOL_B_ONLY; + break; + } + case SL_WIFI_RATE_11G_6: + case SL_WIFI_RATE_11G_9: + case SL_WIFI_RATE_11G_12: + case SL_WIFI_RATE_11G_18: + case SL_WIFI_RATE_11G_24: + case SL_WIFI_RATE_11G_36: + case SL_WIFI_RATE_11G_48: + case SL_WIFI_RATE_11G_54: { + *rate_protocol = SL_WIFI_RATE_PROTOCOL_G_ONLY; + break; + } + case SL_WIFI_RATE_11N_MCS0: + case SL_WIFI_RATE_11N_MCS1: + case SL_WIFI_RATE_11N_MCS2: + case SL_WIFI_RATE_11N_MCS3: + case SL_WIFI_RATE_11N_MCS4: + case SL_WIFI_RATE_11N_MCS5: + case SL_WIFI_RATE_11N_MCS6: + case SL_WIFI_RATE_11N_MCS7: { + *rate_protocol = SL_WIFI_RATE_PROTOCOL_N_ONLY; + break; + } + case SL_WIFI_RATE_11AX_MCS0: + case SL_WIFI_RATE_11AX_MCS1: + case SL_WIFI_RATE_11AX_MCS2: + case SL_WIFI_RATE_11AX_MCS3: + case SL_WIFI_RATE_11AX_MCS4: + case SL_WIFI_RATE_11AX_MCS5: + case SL_WIFI_RATE_11AX_MCS6: + case SL_WIFI_RATE_11AX_MCS7: { + *rate_protocol = SL_WIFI_RATE_PROTOCOL_AX_ONLY; + break; + } + default: { + return SL_STATUS_INVALID_CONFIGURATION; + } + } + + *mask = data_rate; + + return SL_STATUS_OK; +} + +void convert_performance_profile_to_power_save_command(sl_si91x_performance_profile_t profile, + sl_si91x_power_save_request_t *power_save_request) +{ + SL_ASSERT(power_save_request != NULL); + if (performance_profile.wifi_performance_profile.monitor_interval) { + power_save_request->monitor_interval = performance_profile.wifi_performance_profile.monitor_interval; + } else { + power_save_request->monitor_interval = DEFAULT_MONITOR_INTERVAL; + } + + power_save_request->ulp_mode_enable = SL_ULP_WITH_RAM_RETENTION; + power_save_request->dtim_aligned_type = performance_profile.wifi_performance_profile.dtim_aligned_type; + power_save_request->num_of_dtim_skip = performance_profile.wifi_performance_profile.num_of_dtim_skip; + power_save_request->listen_interval = performance_profile.wifi_performance_profile.listen_interval; + power_save_request->psp_type = SL_MAX_PSP; + + // Depending on the specified performance profile, configure the power_save_request structure + switch (profile) { + case HIGH_PERFORMANCE: { + // For HIGH_PERFORMANCE profile, reset all fields in the power_save_request structure to zero + memset(power_save_request, 0, sizeof(sl_si91x_power_save_request_t)); + break; + } + + case ASSOCIATED_POWER_SAVE: { +#ifdef SLI_SI91X_MCU_INTERFACE + power_save_request->power_mode = SL_CONNECTED_M4_BASED_PS; +#else + power_save_request->power_mode = SL_CONNECTED_GPIO_BASED_PS; +#endif + break; + } + + case ASSOCIATED_POWER_SAVE_LOW_LATENCY: { +#ifdef SLI_SI91X_MCU_INTERFACE + power_save_request->power_mode = SL_CONNECTED_M4_BASED_PS; +#else + power_save_request->power_mode = SL_CONNECTED_GPIO_BASED_PS; +#endif + power_save_request->psp_type = SL_FAST_PSP; + break; + } + + case DEEP_SLEEP_WITHOUT_RAM_RETENTION: { +#ifdef SLI_SI91X_MCU_INTERFACE + power_save_request->power_mode = SL_M4_BASED_DEEP_SLEEP; +#else + power_save_request->power_mode = SL_GPIO_BASED_DEEP_SLEEP; +#endif + power_save_request->ulp_mode_enable = SL_ULP_WITHOUT_RAM_RET_RETENTION; + break; + } + + case DEEP_SLEEP_WITH_RAM_RETENTION: { +#ifdef SLI_SI91X_MCU_INTERFACE + power_save_request->power_mode = SL_M4_BASED_DEEP_SLEEP; +#else + power_save_request->power_mode = SL_GPIO_BASED_DEEP_SLEEP; +#endif + break; + } + default: { + // Do nothing + } break; + } + + return; +} + +//In Access point mode NWP only supports No Encryption, TKIP and CCMP encryptions. +sl_status_t convert_sl_wifi_to_sl_si91x_encryption(sl_wifi_encryption_t encryption_mode, uint8_t *encryption_request) +{ + switch (encryption_mode) { + case SL_WIFI_NO_ENCRYPTION: + *encryption_request = SL_SI91X_NO_ENCRYPTION; + break; + case SL_WIFI_TKIP_ENCRYPTION: + *encryption_request = SL_SI91X_TKIP_ENCRYPTION; + break; + case SL_WIFI_CCMP_ENCRYPTION: + case SL_WIFI_DEFAULT_ENCRYPTION: + *encryption_request = SL_SI91X_CCMP_ENCRYPTION; + break; + default: + return SL_STATUS_NOT_SUPPORTED; + } + + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_platform_init(void) +{ + sl_status_t status = SL_STATUS_OK; + + // Initialize the command queues + memset(cmd_queues, 0, sizeof(cmd_queues)); + + // Create event flags + if (NULL == si91x_events) { + si91x_events = osEventFlagsNew(NULL); + } + + if (NULL == si91x_bus_events) { + si91x_bus_events = osEventFlagsNew(NULL); + } + + if (NULL == si91x_async_events) { + si91x_async_events = osEventFlagsNew(NULL); + } + + // Create and start SI91X bus thread + if (NULL == si91x_thread) { + const osThreadAttr_t attr = { + + .name = "si91x_bus", + .priority = osPriorityRealtime, + .stack_mem = 0, + .stack_size = 1636, + .cb_mem = 0, + .cb_size = 0, + .attr_bits = 0u, + .tz_module = 0u, + }; + si91x_thread = osThreadNew(si91x_bus_thread, NULL, &attr); + } + + // Create and start SI91X event handler thread + if (NULL == si91x_event_thread) { + const osThreadAttr_t attr = { + .name = "si91x_event", + .priority = osPriorityRealtime1, + .stack_mem = 0, + .stack_size = SL_SI91X_EVENT_HANDLER_STACK_SIZE, + .cb_mem = 0, + .cb_size = 0, + .attr_bits = 0u, + .tz_module = 0u, + }; + si91x_event_thread = osThreadNew(si91x_event_handler_thread, NULL, &attr); + } + + // Initialize command queues and associated mutexes + for (int i = 0; i < SI91X_CMD_MAX; i++) { + cmd_queues[i].tx_queue.head = NULL; + cmd_queues[i].tx_queue.tail = NULL; + cmd_queues[i].rx_queue.head = NULL; + cmd_queues[i].rx_queue.tail = NULL; + cmd_queues[i].event_queue.head = NULL; + cmd_queues[i].event_queue.tail = NULL; + cmd_queues[i].mutex = osMutexNew(NULL); + cmd_queues[i].flag = (1 << i); + } + + // Create malloc/free mutex + if (malloc_free_mutex == NULL) { + malloc_free_mutex = osMutexNew(NULL); + } + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + // Create side_band_crypto_mutex mutex + side_band_crypto_mutex = osMutexNew(NULL); +#endif + + return status; +} + +sl_status_t sl_si91x_platform_deinit(void) +{ + + // Deallocate all threads, mutexes and event handlers + + // Terminate SI91X bus thread + if (NULL != si91x_thread) { + // Signal the thread to terminate + osEventFlagsSet(si91x_bus_events, SL_SI91X_TERMINATE_BUS_THREAD_EVENT); + + // Wait for thread termination acknowledgment + osStatus_t stat = osEventFlagsWait(si91x_events, SL_SI91X_TERMINATE_BUS_THREAD_EVENT_ACK, osFlagsWaitAny, 5000); + if (stat == osErrorTimeout) { + // Return timeout if acknowledgment is not received + return SL_STATUS_TIMEOUT; + } + + si91x_thread = NULL; + } + + // Terminate SI91X event handler thread + if (NULL != si91x_event_thread) { + osThreadTerminate(si91x_event_thread); + si91x_event_thread = NULL; + } + + // Delete event flags + if (NULL != si91x_events) { + osEventFlagsDelete(si91x_events); + si91x_events = NULL; + } + + if (NULL != si91x_bus_events) { + osEventFlagsDelete(si91x_bus_events); + si91x_bus_events = NULL; + } + + if (NULL != si91x_async_events) { + osEventFlagsDelete(si91x_async_events); + si91x_async_events = NULL; + } + + // Delete command queue mutexes + for (int i = 0; i < SI91X_CMD_MAX; i++) { + osMutexDelete(cmd_queues[i].mutex); + cmd_queues[i].mutex = NULL; + } + + // Delete malloc/free mutex + osMutexDelete(malloc_free_mutex); + malloc_free_mutex = NULL; + return SL_STATUS_OK; +} + +sl_si91x_host_timestamp_t sl_si91x_host_get_timestamp(void) +{ + return osKernelGetTickCount(); +} + +// Calculate elapsed time from the given starting timestamp +sl_si91x_host_timestamp_t sl_si91x_host_elapsed_time(uint32_t starting_timestamp) +{ + uint32_t current_tickcount = osKernelGetTickCount(); + + // Check if the tick count has overflow or not. + if (current_tickcount >= starting_timestamp) { + return (current_tickcount - starting_timestamp); + } else { + return ((0xFFFFFFFF - starting_timestamp) + current_tickcount); + } +} + +// Delay execution for a specified number of milliseconds using an OS-level delay +void sl_si91x_host_delay_ms(uint32_t delay_milliseconds) +{ + osDelay(delay_milliseconds); +} + +void sli_si91x_set_event(uint32_t event_mask) +{ + osEventFlagsSet(si91x_events, event_mask); +} + +void sl_si91x_host_set_bus_event(uint32_t event_mask) +{ + osEventFlagsSet(si91x_bus_events, event_mask); +} + +sl_status_t sli_si91x_add_to_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t *buffer) +{ + sli_si91x_append_to_buffer_queue(queue, buffer); + return SL_STATUS_OK; +} + +sl_status_t sli_si91x_remove_from_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t **buffer) +{ + return sli_si91x_pop_from_buffer_queue(queue, buffer); +} + +sl_status_t sli_si91x_flush_all_tx_wifi_queues(uint16_t frame_status) +{ + // free all TX queues except BT + for (int queue_id = 0; queue_id < SI91X_CMD_MAX; queue_id++) { + if (queue_id == SI91X_BT_CMD) { + continue; + } + sli_si91x_flush_queue_based_on_type(&cmd_queues[queue_id], + SL_SI91X_RESPONSE_FLAG(queue_id), + frame_status, + NULL, + NULL); + } + return SL_STATUS_OK; +} + +sl_status_t sli_si91x_flush_generic_data_queues(sl_si91x_buffer_queue_t *tx_data_queue) +{ + sl_wifi_buffer_t *current_packet = NULL; + sl_wifi_buffer_t *next_packet = NULL; + + // Validate input + if (tx_data_queue == NULL) { + return SL_STATUS_FAIL; + } + + // Prevent race conditions + CORE_irqState_t state = CORE_EnterAtomic(); + + // Free all packets in the queue + current_packet = tx_data_queue->head; + while (current_packet != NULL) { + next_packet = (sl_wifi_buffer_t *)current_packet->node.node; + sl_si91x_host_free_buffer(current_packet); + current_packet = next_packet; + } + + // Reset the queue + tx_data_queue->head = NULL; + tx_data_queue->tail = NULL; + + // Clear pending TX status + tx_generic_socket_data_queues_status &= ~(SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT); + + CORE_ExitAtomic(state); + + return SL_STATUS_OK; +} + +sl_status_t sli_si91x_flush_queue_based_on_type(sli_si91x_command_queue_t *queue, + uint32_t event_mask, + uint16_t frame_status, + sl_si91x_compare_function_t compare_function, + void *user_data) +{ + sl_wifi_buffer_t *current_packet = NULL; + sl_wifi_buffer_t *next_packet = NULL; + sli_si91x_queue_packet_t *queue_node = NULL; + sl_wifi_buffer_t *previous_packet = NULL; + sl_status_t status = SL_STATUS_FAIL; + + // Enter atomic section to prevent race conditions + CORE_irqState_t state = CORE_EnterAtomic(); + + // Check if the queue is not the BT command queue and has a command in flight + if ((queue != &cmd_queues[SI91X_BT_CMD]) && (queue->command_in_flight == true)) { + // Create a generic RX packet + status = sl_create_generic_rx_packet_from_params(&queue_node, + ¤t_packet, + queue->packet_id, + queue->flags, + queue->sdk_context, + frame_status); + if (status != SL_STATUS_OK) { + CORE_ExitAtomic(state); + return status; // Exit if packet creation fails + } + sl_wifi_buffer_t *dummy_packet_buffer = NULL; + + // Allocate buffer for the dummy packet + status = sl_si91x_host_allocate_buffer(&dummy_packet_buffer, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sl_si91x_packet_t), + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + if (status != SL_STATUS_OK) { + CORE_ExitAtomic(state); + sl_si91x_host_free_buffer(current_packet); // Free current_packet on failure + return status; // Exit if buffer allocation fails + } + + // Get the dummy packet data from the allocated buffer + sl_si91x_packet_t *dummy_packet = sl_si91x_host_get_buffer_data(dummy_packet_buffer, 0, NULL); + queue_node->host_packet = dummy_packet_buffer; // Link dummy packet to the node + dummy_packet->desc[2] = (uint8_t)queue->frame_type; + dummy_packet->desc[3] = (uint8_t)((0xFF00 & queue->frame_type) >> 8); + + if (!compare_function || compare_function(queue_node->host_packet, user_data)) { + + if (!(queue->flags & SI91X_PACKET_RESPONSE_PACKET)) { + sl_si91x_host_free_buffer(dummy_packet_buffer); + } + // Check if the packet in the queue is synchronous or asynchronous response + if (sl_si91x_host_elapsed_time(queue->command_tickcount) <= (queue->command_timeout)) { + // Add the packet to the response queue and set the event + sli_si91x_add_to_queue(&queue->rx_queue, current_packet); + sli_si91x_set_event(event_mask); + } else { + // no user thread is waiting for the response so flush the packet + sl_si91x_host_free_buffer(current_packet); + sl_si91x_host_free_buffer(dummy_packet_buffer); + } + tx_command_queues_command_in_flight_status &= ~(event_mask); + + // Reset command trace for the queue + queue->command_in_flight = false; + queue->frame_type = 0; + queue->flag = 0; + queue->command_tickcount = 0; + queue->command_timeout = 0; + } + } + + // Start with the head of the TX queue + current_packet = queue->tx_queue.head; + + // Iterate through all packets in the TX queue + while (current_packet != NULL) { + // Get the associated queue node + queue_node = sl_si91x_host_get_buffer_data(current_packet, 0, NULL); + if (queue_node == NULL) { + CORE_ExitAtomic(state); + return SL_STATUS_NOT_AVAILABLE; // Exit if queue node retrieval fails + } + + if (!compare_function || compare_function(queue_node->host_packet, user_data) == false) { + previous_packet = current_packet; + current_packet = (sl_wifi_buffer_t *)current_packet->node.node; + continue; + } + + // Save the next packet in the queue + next_packet = (sl_wifi_buffer_t *)current_packet->node.node; + + // Check if the packet in the TX queue is synchronous or asynchronous + if (queue_node->flags & SI91X_PACKET_RESPONSE_STATUS) { + // Update the frame_status and other details + queue_node->frame_status = frame_status; + current_packet->node.node = NULL; + + // Check if the TX packet is not expecting a response, then free the host packet + if (!(queue_node->flags & SI91X_PACKET_RESPONSE_PACKET)) { + if (queue_node->host_packet != NULL) { + sl_si91x_host_free_buffer(queue_node->host_packet); + queue_node->host_packet = NULL; + } + } + + // Check if the packet in the queue is synchronous or asynchronous response + if (sl_si91x_host_elapsed_time(queue_node->command_tickcount) <= (queue_node->command_timeout)) { + // Add the packet to the response queue and set the event + sli_si91x_add_to_queue(&queue->rx_queue, current_packet); + sli_si91x_set_event(event_mask); + } else { + // no user thread is waiting for the response so flush the packet + if ((queue_node->flags & SI91X_PACKET_RESPONSE_PACKET) == SI91X_PACKET_RESPONSE_PACKET) { + sl_si91x_host_free_buffer(queue_node->host_packet); + } + sl_si91x_host_free_buffer(current_packet); + } + } else { + // Handle asynchronous packets by freeing them + sl_si91x_host_free_buffer(current_packet); + } + + // Update the head of the queue if the current packet is the head + if (current_packet == queue->tx_queue.head) { + queue->tx_queue.head = next_packet; + } + + // Update the tail of the queue if the current packet is the tail + if (current_packet == queue->tx_queue.tail) { + queue->tx_queue.tail = previous_packet; + } + + // Move to the next packet + previous_packet = current_packet; + current_packet = next_packet; + } + + // Check if the queue is empty and update tx_command_queues_status + if (queue->tx_queue.head == NULL) { + // Clear the tail pointer of the TX queue + queue->tx_queue.tail = NULL; + tx_command_queues_status &= ~(event_mask); + } + + // Exit atomic section + CORE_ExitAtomic(state); + + // Return SL_STATUS_OK indicating the operation was successful + return SL_STATUS_OK; +} + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +sl_status_t sli_si91x_flush_all_socket_command_queues(uint16_t frame_status, uint8_t vap_id) +{ + sl_status_t status; + + // Loop through all sockets + for (int index = 0; index < NUMBER_OF_SOCKETS; index++) { + // Check if the socket exists and matches the required VAP ID + if ((sli_si91x_sockets[index] != NULL) && (sli_si91x_sockets[index]->vap_id == vap_id)) { + // Flush the command queues for the current socket based on queue type + status = sli_si91x_flush_socket_command_queues_based_on_queue_type(index, frame_status); + // If flushing fails, return the error status immediately + if (status != SL_STATUS_OK) { + return status; + } + } + } + // Return SL_STATUS_OK if all sockets were processed successfully + return SL_STATUS_OK; +} + +sl_status_t sli_si91x_flush_socket_command_queues_based_on_queue_type(uint8_t index, uint16_t frame_status) +{ + sl_wifi_buffer_t *current_packet = NULL; + sl_wifi_buffer_t *next_packet = NULL; + sli_si91x_queue_packet_t *queue_node = NULL; + + // Retrieve the socket using the provided index + sli_si91x_socket_t *socket = get_si91x_socket(index); + + if (socket == NULL) { + return SL_STATUS_FAIL; + } + + // Enter atomic state to prevent race conditions + CORE_irqState_t state = CORE_EnterAtomic(); + + // Check if there is a command currently in flight + if ((socket->command_queue.command_in_flight) && ((socket->command_queue.flags) & SI91X_PACKET_RESPONSE_STATUS)) { + // Create a generic RX packet from the current command parameters + sl_status_t status = sl_create_generic_rx_packet_from_params(&queue_node, + ¤t_packet, + socket->command_queue.packet_id, + socket->command_queue.flags, + socket->command_queue.sdk_context, + frame_status); + // If packet creation fails, exit atomic state and return the error status + if (status != SL_STATUS_OK) { + CORE_ExitAtomic(state); + return status; + } + + // Handle packets that expect a response + if (queue_node->flags & SI91X_PACKET_RESPONSE_PACKET) { + sl_wifi_buffer_t *host_packet = NULL; + uint16_t length = 0; + if (socket->command_queue.frame_type == RSI_WLAN_RSP_SOCKET_CLOSE) { + length = sizeof(sl_si91x_packet_t) + sizeof(sl_si91x_socket_close_response_t); + } else { + length = sizeof(sl_si91x_packet_t); + } + // Allocate a buffer for the host packet + status = sl_si91x_host_allocate_buffer(&host_packet, + SL_WIFI_RX_FRAME_BUFFER, + length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + // If buffer allocation fails, log an error, trigger a breakpoint, and return + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + + // Populate the packet descriptor with frame status + sl_si91x_packet_t *si91x_packet = (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data(host_packet, 0, NULL); + si91x_packet->desc[12] = (uint8_t)(frame_status & 0x00FF); + si91x_packet->desc[13] = (uint8_t)((frame_status & 0xFF00) >> 8); + queue_node->host_packet = host_packet; + host_packet->id = current_packet->id; + if (socket->command_queue.frame_type == RSI_WLAN_RSP_SOCKET_CLOSE) { + si91x_packet->desc[12] = 0; + si91x_packet->desc[13] = 0; + queue_node->frame_status = SL_STATUS_OK; + sl_si91x_socket_close_response_t *socket_close_response = + (sl_si91x_socket_close_response_t *)si91x_packet->data; + socket_close_response->socket_id = (uint16_t)socket->id; + socket_close_response->port_number = socket->local_address.sin6_port; + } + } + + // Add the packet to the appropriate queue and set the event + if (sl_si91x_host_elapsed_time(socket->command_queue.command_tickcount) <= socket->command_queue.command_timeout) { + if (socket->command_queue.frame_type == RSI_WLAN_RSP_SOCKET_READ_DATA) { + sli_si91x_add_to_queue(&socket->rx_data_queue, queue_node->host_packet); + } else { + sli_si91x_add_to_queue(&socket->command_queue.rx_queue, current_packet); + } + sli_si91x_set_socket_event((1 << socket->index)); + } else { + // no user thread is waiting for the response so flush the packet + if (queue_node->flags & SI91X_PACKET_RESPONSE_PACKET) { + sl_si91x_host_free_buffer(queue_node->host_packet); + } + sl_si91x_host_free_buffer(current_packet); + } + tx_socket_command_command_in_flight_queues_status |= (1 << socket->index); + // Reset command trace fields in the queue + socket->command_queue.command_in_flight = false; + socket->command_queue.command_tickcount = 0; + socket->command_queue.command_timeout = 0; + socket->command_queue.frame_type = 0; + } + + // Start processing the TX queue + current_packet = socket->command_queue.tx_queue.head; + + // Iterate through all packets in the command queue + while (current_packet != NULL) { + // Retrieve the queue node from the current packet + queue_node = sl_si91x_host_get_buffer_data(current_packet, 0, NULL); + if (queue_node == NULL) { + // If queue node is NULL, exit atomic state and return error status + CORE_ExitAtomic(state); + return SL_STATUS_NOT_AVAILABLE; + } + + // Assign next_packet to the next node in the list + next_packet = (sl_wifi_buffer_t *)current_packet->node.node; + + // Check if the packet in the TX queue is synchronous or asynchronous + if (queue_node->flags & SI91X_PACKET_RESPONSE_STATUS) { + // Update the frame_status and other details for synchronous packets + queue_node->frame_status = frame_status; + current_packet->node.node = NULL; + int32_t frame_type = sli_get_socket_command_from_host_packet(queue_node->host_packet); + // Check if the TX packet is not expecting a response, then free the host packet + if (!(queue_node->flags & SI91X_PACKET_RESPONSE_PACKET)) { + if (queue_node->host_packet != NULL) { + sl_si91x_host_free_buffer(queue_node->host_packet); + queue_node->host_packet = NULL; + } + } + + // Add to response queue and raise event based on frame type + if (sl_si91x_host_elapsed_time(queue_node->command_tickcount) <= queue_node->command_timeout) { + if (frame_type == RSI_WLAN_RSP_SOCKET_CLOSE) { + sl_si91x_host_free_buffer(queue_node->host_packet); + sl_wifi_buffer_t *host_packet = NULL; + // Allocate a buffer for the host packet + sl_status_t status = + sl_si91x_host_allocate_buffer(&host_packet, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sl_si91x_packet_t) + sizeof(sl_si91x_socket_close_response_t), + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + // If buffer allocation fails, log an error, trigger a breakpoint, and return + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + queue_node->host_packet = host_packet; + queue_node->frame_status = SL_STATUS_OK; + sl_si91x_packet_t *si91x_packet = + (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data(queue_node->host_packet, 0, NULL); + si91x_packet->desc[12] = 0; + si91x_packet->desc[13] = 0; + sl_si91x_socket_close_response_t *socket_close_response = + (sl_si91x_socket_close_response_t *)si91x_packet->data; + socket_close_response->socket_id = (uint16_t)socket->id; + socket_close_response->port_number = socket->local_address.sin6_port; + } + if (frame_type == RSI_WLAN_RSP_SOCKET_READ_DATA) { + sl_si91x_packet_t *si91x_packet = + (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data(queue_node->host_packet, 0, NULL); + if (si91x_packet != NULL) { + si91x_packet->desc[12] = (uint8_t)(frame_status & 0x00FF); + si91x_packet->desc[13] = (uint8_t)((frame_status & 0xFF00) >> 8); + sli_si91x_add_to_queue(&socket->rx_data_queue, queue_node->host_packet); + } + } else { + sli_si91x_add_to_queue(&socket->command_queue.rx_queue, current_packet); + } + + sli_si91x_set_socket_event((1 << socket->index)); + } else { + // no user thread is waiting for the response so flush the packet + if ((queue_node->flags & SI91X_PACKET_RESPONSE_PACKET) == SI91X_PACKET_RESPONSE_PACKET) { + sl_si91x_host_free_buffer(queue_node->host_packet); + } + sl_si91x_host_free_buffer(current_packet); + } + } else { + // Handle asynchronous packets by freeing the buffer + sl_si91x_host_free_buffer(current_packet); + } + + // Move to the next packet in the queue + current_packet = next_packet; + } + + // Clear the head and tail pointers of the TX queue + socket->command_queue.tx_queue.head = NULL; + socket->command_queue.tx_queue.tail = NULL; + // Clear the socket command queue status + tx_socket_command_queues_status &= ~(1 << socket->index); + + // Exit atomic state + CORE_ExitAtomic(state); + // Return successful status + return SL_STATUS_OK; +} +sl_status_t sli_si91x_flush_all_socket_data_queues(uint8_t vap_id) +{ + sl_status_t status; + + // Loop through all sockets + for (int index = 0; index < NUMBER_OF_SOCKETS; index++) { + // Retrieve the socket using the provided index + const sli_si91x_socket_t *socket = sli_si91x_sockets[index]; + + // Check if the socket exists and matches the required VAP ID + if ((socket != NULL) && (socket->vap_id == vap_id)) { + // Flush the data queues for the current socket based on queue type + status = sli_si91x_flush_socket_data_queues_based_on_queue_type(index); + // If flushing fails, return the error status immediately + if (status != SL_STATUS_OK) { + return status; + } + } + } + // Return SL_STATUS_OK if all sockets were processed successfully + return SL_STATUS_OK; +} + +sl_status_t sli_si91x_flush_socket_data_queues_based_on_queue_type(uint8_t index) +{ + sl_wifi_buffer_t *current_packet = NULL; + sl_wifi_buffer_t *next_packet = NULL; + + // Retrieve the socket using the provided index + sli_si91x_socket_t *socket = get_si91x_socket(index); + + if (socket == NULL) { + return SL_STATUS_FAIL; + } + + // Enter atomic section to prevent race conditions + CORE_irqState_t state = CORE_EnterAtomic(); + + // Start with the head of the TX data queue + current_packet = socket->tx_data_queue.head; + + // Iterate through all packets in the queue + while (current_packet != NULL) { + // Save the next packet in the queue + next_packet = (sl_wifi_buffer_t *)current_packet->node.node; + + // Free the current packet using the provided free function + sl_si91x_host_free_buffer(current_packet); + + // Move to the next packet + current_packet = next_packet; + } + + // Clear the head and tail pointers of the queue to indicate it is empty + socket->tx_data_queue.head = NULL; + socket->tx_data_queue.tail = NULL; + + // Clear the socket data queue status + tx_socket_data_queues_status &= ~(1 << socket->index); + + // Exit atomic section + CORE_ExitAtomic(state); + + // Return SL_STATUS_OK indicating the operation was successful + return SL_STATUS_OK; +} + +#endif + +uint32_t sl_si91x_host_queue_status(sl_si91x_buffer_queue_t *queue) +{ + return queue->head != NULL; +} + +uint32_t sli_si91x_wait_for_event(uint32_t event_mask, uint32_t timeout) +{ + uint32_t result = osEventFlagsWait(si91x_events, event_mask, osFlagsWaitAny, timeout); + + if (result == (uint32_t)osErrorTimeout || result == (uint32_t)osErrorResource) { + return 0; + } + return result; +} + +uint32_t si91x_host_wait_for_bus_event(uint32_t event_mask, uint32_t timeout) +{ + uint32_t result = osEventFlagsWait(si91x_bus_events, event_mask, osFlagsWaitAny, timeout); + + if (result == (uint32_t)osErrorTimeout || result == (uint32_t)osErrorResource) { + return 0; + } + return result; +} + +uint32_t sli_si91x_clear_event(uint32_t event_mask) +{ + uint32_t result = osEventFlagsClear(si91x_events, event_mask); + if (result == (uint32_t)osErrorResource) { + return 0; + } + return result; +} + +sl_status_t sli_si91x_send_power_save_request(const sl_wifi_performance_profile_t *wifi_profile, + const sl_bt_performance_profile_t *bt_profile) +{ + sl_status_t status; + sl_si91x_power_save_request_t power_save_request = { 0 }; + sl_si91x_performance_profile_t selected_coex_profile_mode = { 0 }; + // Disable power save mode by setting it to HIGH_PERFORMANCE profile + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_PWRMODE, + SI91X_COMMON_CMD, + &power_save_request, + sizeof(sl_si91x_power_save_request_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + if (NULL != wifi_profile) { + // Save the new Wi-Fi profile + save_wifi_current_performance_profile(wifi_profile); + } + + if (NULL != bt_profile) { + // Save the new BT/BLE profile + save_bt_current_performance_profile(bt_profile); + } + + // get the updated coex profile + get_coex_performance_profile(&selected_coex_profile_mode); + + // If the requested performance profile is HIGH_PERFORMANCE, no need to send the request to firmware + if (selected_coex_profile_mode == HIGH_PERFORMANCE) { + return SL_STATUS_OK; + } + + // Convert the performance profile to a power save request. + convert_performance_profile_to_power_save_command(selected_coex_profile_mode, &power_save_request); + + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_PWRMODE, + SI91X_COMMON_CMD, + &power_save_request, + sizeof(sl_si91x_power_save_request_t), + SL_SI91X_WAIT_FOR_RESPONSE(3000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_host_power_cycle(void) +{ + sl_si91x_host_hold_in_reset(); + sl_si91x_host_delay_ms(100); + + sl_si91x_host_release_from_reset(); + sl_si91x_host_delay_ms(100); + + return SL_STATUS_OK; +} + +void print_80211_packet(const uint8_t *packet, uint32_t packet_length, uint16_t max_payload_length) +{ + uint32_t dump_bytes = 0; + uint32_t header_length = MAC80211_HDR_MIN_LEN; + + header_length += (packet[0] & BIT(7)) ? 2 : 0; /* 2 bytes QoS control */ + header_length += ((packet[1] & BIT(0)) && (packet[1] & BIT(1))) ? 6 : 0; /* 6 byte Addr4 */ + + sl_debug_log("%02x %02x | ", packet[0], packet[1]); /* FC */ + sl_debug_log("%02x %02x | ", packet[2], packet[3]); /* Dur */ + sl_debug_log("%02x:%02x:%02x:%02x:%02x:%02x | ", + packet[4], + packet[5], + packet[6], + packet[7], + packet[8], + packet[9]); /* Addr1/RA */ + sl_debug_log("%02x:%02x:%02x:%02x:%02x:%02x | ", + packet[10], + packet[11], + packet[12], + packet[13], + packet[14], + packet[15]); /* Addr2/NWP */ + sl_debug_log("%02x:%02x:%02x:%02x:%02x:%02x | ", + packet[16], + packet[17], + packet[18], + packet[19], + packet[20], + packet[21]); /* Addr3/DA */ + sl_debug_log("%02x %02x | ", packet[22], packet[23]); /* Seq control */ + if ((packet[1] & BIT(0)) && (packet[1] & BIT(1))) { /* Addr4 */ + sl_debug_log("%02x:%02x:%02x:%02x:%02x:%02x | ", + packet[24], + packet[25], + packet[26], + packet[27], + packet[28], + packet[29]); + } + if (packet[0] & BIT(7)) { + sl_debug_log("%02x %02x | ", packet[30], packet[31]); /* QoS control */ + } + + // Determine number of payload bytes to print + dump_bytes = packet_length - header_length; + dump_bytes = max_payload_length > dump_bytes ? dump_bytes : max_payload_length; + + for (uint32_t i = header_length; i < header_length + dump_bytes; i++) { + sl_debug_log("%02x ", packet[i]); + } + + sl_debug_log("|\r\n"); +} + +sli_si91x_command_queue_t *sli_si91x_get_command_queue(sl_si91x_command_type_t type) +{ + switch (type) { + case SI91X_WLAN_CMD: + return &cmd_queues[SI91X_WLAN_CMD]; + case SI91X_NETWORK_CMD: + return &cmd_queues[SI91X_NETWORK_CMD]; + case SI91X_BT_CMD: + return &cmd_queues[SI91X_BT_CMD]; + case SI91X_SOCKET_CMD: + return &cmd_queues[SI91X_SOCKET_CMD]; + + case SI91X_COMMON_CMD: + default: + return &cmd_queues[SI91X_COMMON_CMD]; + } +} + +uint8_t sli_lmac_crc8_c(uint8_t crc8_din, uint8_t crc8_state, uint8_t end) +{ + uint8_t din[8]; + uint8_t state[8]; + uint8_t state_c[8]; + uint8_t crc8_out; + + din[0] = ((crc8_din & BIT(7)) >> 7); + din[1] = ((crc8_din & BIT(6)) >> 6); + din[2] = ((crc8_din & BIT(5)) >> 5); + din[3] = ((crc8_din & BIT(4)) >> 4); + din[4] = ((crc8_din & BIT(3)) >> 3); + din[5] = ((crc8_din & BIT(2)) >> 2); + din[6] = ((crc8_din & BIT(1)) >> 1); + din[7] = ((crc8_din & BIT(0)) >> 0); + + state[0] = ((crc8_state & BIT(0)) >> 0); + state[1] = ((crc8_state & BIT(1)) >> 1); + state[2] = ((crc8_state & BIT(2)) >> 2); + state[3] = ((crc8_state & BIT(3)) >> 3); + state[4] = ((crc8_state & BIT(4)) >> 4); + state[5] = ((crc8_state & BIT(5)) >> 5); + state[6] = ((crc8_state & BIT(6)) >> 6); + state[7] = ((crc8_state & BIT(7)) >> 7); + + state_c[7] = (state[7] ^ din[7]) ^ (state[6] ^ din[6]) ^ (state[5] ^ din[5]); + + state_c[6] = (state[6] ^ din[6]) ^ (state[5] ^ din[5]) ^ (state[4] ^ din[4]); + + state_c[5] = (state[5] ^ din[5]) ^ (state[4] ^ din[4]) ^ (state[3] ^ din[3]); + + state_c[4] = (state[4] ^ din[4]) ^ (state[3] ^ din[3]) ^ (state[2] ^ din[2]); + + state_c[3] = (state[1] ^ din[1]) ^ (state[2] ^ din[2]) ^ (state[3] ^ din[3]) ^ (state[7] ^ din[7]); + + state_c[2] = (state[0] ^ din[0]) ^ (state[1] ^ din[1]) ^ (state[2] ^ din[2]) ^ (state[6] ^ din[6]); + + state_c[1] = (state[0] ^ din[0]) ^ (state[1] ^ din[1]) ^ (state[6] ^ din[6]); + + state_c[0] = (state[0] ^ din[0]) ^ (state[7] ^ din[7]) ^ (state[6] ^ din[6]); + if (!end) { + crc8_out = (uint8_t)(((state_c[0] & BIT(0)) << 0) | ((state_c[1] & BIT(0)) << 1) | ((state_c[2] & BIT(0)) << 2) + | ((state_c[3] & BIT(0)) << 3) | ((state_c[4] & BIT(0)) << 4) | ((state_c[5] & BIT(0)) << 5) + | ((state_c[6] & BIT(0)) << 6) | ((state_c[7] & BIT(0)) << 7)); + } else { + crc8_out = (uint8_t)(((state_c[7] & BIT(0)) << 0) | ((state_c[6] & BIT(0)) << 1) | ((state_c[5] & BIT(0)) << 2) + | ((state_c[4] & BIT(0)) << 3) | ((state_c[3] & BIT(0)) << 4) | ((state_c[2] & BIT(0)) << 5)); + + crc8_out = ~crc8_out; + crc8_out &= 0x3f; + } + return crc8_out; +} + +uint8_t sli_multicast_mac_hash(const uint8_t *mac) +{ + uint8_t crc = 0xff; + for (uint8_t i = 0; i < 6; i++) { + crc = sli_lmac_crc8_c(mac[i], crc, ((i == 5) ? 1 : 0)); + } + return crc; +} + +/* Function to get the current status of the NVM command progress +Returns true if an NVM command is in progress, false otherwise*/ +bool sli_si91x_get_flash_command_status() +{ + return sli_si91x_packet_status; +} + +void sli_si91x_update_flash_command_status(bool flag) +{ + sli_si91x_packet_status = flag; +} + +/* This function is used to update the power manager to see whether the device is ready for sleep or not. + True indicates ready for sleep, and false indicates not ready for sleep.*/ +bool sli_si91x_is_sdk_ok_to_sleep() +{ + return ((!sli_si91x_get_flash_command_status()) && (sl_si91x_is_device_initialized())); +} + +bool sl_si91x_is_device_initialized(void) +{ + return device_initialized; +} + +sl_status_t sli_si91x_remove_buffer_from_queue_by_comparator(sl_si91x_buffer_queue_t *queue, + const void *user_data, + sli_si91x_wifi_buffer_comparator comparator, + sl_wifi_buffer_t **buffer) +{ + // Check if the queue is empty + if (queue->head == NULL) { + assert(queue->tail == NULL); + return SL_STATUS_EMPTY; + } + + CORE_irqState_t state = CORE_EnterAtomic(); + sl_wifi_buffer_t *current_buffer = queue->head; + sl_wifi_buffer_t *prev_buffer = NULL; + + // Iterate through the queue to find a matching buffer based on the comparator function + while (current_buffer != NULL) { + // Skip to the next buffer if this one doesn't match + if (!comparator(current_buffer, user_data)) { + prev_buffer = current_buffer; + current_buffer = (sl_wifi_buffer_t *)current_buffer->node.node; + continue; + } + + // Buffer matches, proceed to remove it + *buffer = current_buffer; + + if (current_buffer == queue->head) { + // Removing the head of the queue + queue->head = (sl_wifi_buffer_t *)current_buffer->node.node; + if (queue->head == NULL) { + queue->tail = NULL; // Queue is now empty + } + } else if (current_buffer == queue->tail) { + // Removing the tail of the queue + queue->tail = prev_buffer; + prev_buffer->node.node = NULL; + } else { + // Removing a buffer from the middle + prev_buffer->node.node = current_buffer->node.node; + } + + CORE_ExitAtomic(state); + return SL_STATUS_OK; + } + + // No matching buffer was found + CORE_ExitAtomic(state); + return SL_STATUS_NOT_FOUND; +} + +sl_status_t sl_si91x_host_get_credentials(sl_wifi_credential_id_t id, uint8_t type, sl_wifi_credential_t *cred) +{ + uint32_t credential_length = sizeof(sl_wifi_credential_t) - offsetof(sl_wifi_credential_t, pmk); + sl_status_t status = sl_wifi_get_credential(id, &cred->type, &cred->pmk, &credential_length); + VERIFY_STATUS_AND_RETURN(status); + + if (type == SL_WIFI_PSK_CREDENTIAL) { + if ((cred->type == SL_WIFI_PSK_CREDENTIAL) || (cred->type == SL_WIFI_PMK_CREDENTIAL)) { + return SL_STATUS_OK; + } else { + return SL_STATUS_FAIL; + } + } else if (type != cred->type) { + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/src/sl_si91x_driver.c b/wiseconnect/components/device/silabs/si91x/wireless/src/sl_si91x_driver.c new file mode 100644 index 000000000..8b2b8cd96 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/src/sl_si91x_driver.c @@ -0,0 +1,2711 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_wifi.h" +#include "sl_si91x_host_interface.h" +#include "sl_wifi_types.h" +#include "sl_si91x_status.h" +#include "sl_si91x_types.h" +#include "sl_si91x_protocol_types.h" +#include "sl_wifi_device.h" +#include "sl_rsi_utility.h" +#include "sl_si91x_driver.h" +#include "cmsis_os2.h" +#include +#include +#include +#include "sl_si91x_core_utilities.h" +#include "em_core.h" +#ifdef SLI_SI91X_MCU_INTERFACE +#include "sli_siwx917_soc.h" +#include "rsi_rom_clks.h" +#include "rsi_m4.h" +#include "rsi_wisemcu_hardware_setup.h" +#endif +#ifdef SLI_SI91X_ENABLE_BLE +#include "rsi_common_apis.h" +#endif + +#include "sl_wifi_region_db_config.h" + +#ifdef SLI_SI91X_SOCKETS +#include "sl_si91x_socket_utility.h" +#include "sl_si91x_socket_callback_framework.h" +#endif + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#include "rsi_m4.h" +#define SIDE_BAND_DONE (1 << 2) //! had to be redefined as this macro is not in .h +rsi_m4ta_desc_t crypto_desc[2]; +extern osEventFlagsId_t ta_events; +extern osMutexId_t side_band_crypto_mutex; +#endif + +#ifndef NULL +#define NULL (void *)0 +#endif + +#define htole16(x) (x) +#define htole32(x) (x) + +#ifndef SL_WIFI_SET_MAC_COMMAND_TIME_OUT +#define SL_WIFI_SET_MAC_COMMAND_TIME_OUT 30100 // Retrieved from SAPI 1.0 +#endif + +#define SLI_SI91X_GET_TCP_IP_TOTAL_SELECTS_BITS(x) ((x & 0x0000F000) >> 12) + +#define SL_SI91X_INVALID_MODE 0xFFFF + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#define SL_HOST_DESC_LEN 16 +#define SL_CRYPTO_PKT_LEN 128 +#endif + +// Enterprise configuration command parameters +/*=======================================================================*/ + +// Enterprise method ,should be one of among TLS, TTLS, FAST or PEAP + +#define SL_EAP_TLS_METHOD "TLS" +#define SL_EAP_TTLS_METHOD "TTLS" + +// This parameter is used to configure the module in Enterprise security mode +#define SL_EAP_INNER_METHOD "\"auth=MSCHAPV2\"" + +// Private Key Password is required for encrypted private key, format is like "\"12345678\"" +#define SL_DEFAULT_PRIVATE_KEY_PASSWORD "" + +/*========================================================================*/ +// 11ax params +/*========================================================================*/ +#define GUARD_INTERVAL 3 + +#ifdef SLI_SI91X_MCU_INTERFACE +#define TX_PKT_TRANSFER_DONE_INTERRUPT BIT(2) +#define RX_PKT_TRANSFER_DONE_INTERRUPT BIT(1) + +// Function declarations related to M4 interface +sl_status_t sli_si91x_submit_rx_pkt(void); +static sl_status_t sl_si91x_soft_reset(void); +void sli_siwx917_update_system_core_clock(void); +void sli_m4_ta_interrupt_init(void); +#endif + +// Structure to hold packet information and payload +typedef struct { + uint16_t packet_id; + sli_si91x_queue_packet_t *packet; + void *payload; +} sl_si91x_driver_context_t; + +static sl_si91x_timeout_t timeout_glbl = { .auth_assoc_timeout_value = SL_WIFI_DEFAULT_AUTH_ASSOCIATION_TIMEOUT, + .active_chan_scan_timeout_value = SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME, + .keep_alive_timeout_value = SL_WIFI_DEFAULT_KEEP_ALIVE_TIMEOUT, + .passive_scan_timeout_value = SL_WIFI_DEFAULT_PASSIVE_CHANNEL_SCAN_TIME }; + +sl_status_t sl_si91x_driver_send_command_packet(uint32_t command, + sl_si91x_command_type_t command_type, + sl_wifi_buffer_t *buffer, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer); +static sl_status_t sl_si91x_driver_send_data_packet(sl_wifi_buffer_t *buffer, uint32_t wait_time); +sl_status_t sl_si91x_driver_raw_send_command(uint8_t command, + const void *data, + uint32_t data_length, + uint32_t wait_time); +sl_status_t sl_si91x_allocate_data_buffer(sl_wifi_buffer_t **host_buffer, + void **buffer, + uint32_t data_size, + uint32_t wait_duration_ms); +sl_status_t sl_si91x_driver_init_wifi_radio(const sl_wifi_device_configuration_t *config); +sl_status_t sli_verify_device_boot(uint32_t *rom_version); +sl_status_t sl_si91x_enable_radio(void); +sl_status_t sli_wifi_select_option(const uint8_t configuration); +sl_status_t si91x_bootup_firmware(const uint8_t select_option); +sl_status_t sl_si91x_host_power_cycle(void); + +// This variable stores the frame status of response packet in case of API executed being failed. +// Note: This will not store the error values of asynchronous events. +sl_wifi_event_handler_t si91x_event_handler = NULL; + +// Global variables for device and driver management +sl_wifi_interface_t default_interface; +bool device_initialized = false; +bool interface_is_up[SL_WIFI_MAX_INTERFACE_INDEX] = { false, false, false, false, false }; +bool bg_enabled = false; +uint32_t frontend_switch_control = 0; +static uint32_t feature_bit_map = 0; +//static uint16_t queue_packet_id[SI91X_CMD_MAX] = { 0 }; +static uint8_t ap_join_feature_bitmap = SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID; +static uint8_t client_join_feature_bitmap = SL_SI91X_JOIN_FEAT_LISTEN_INTERVAL_VALID; +static uint32_t client_listen_interval = 1000; +static sl_si91x_efuse_data_t si91x_efuse_data = { 0 }; +//! Currently, initialized_opermode is used only to handle concurrent mode using sl_net_init() +static uint16_t initialized_opermode = SL_SI91X_INVALID_MODE; +extern sli_si91x_command_queue_t cmd_queues[SI91X_CMD_MAX]; +extern sl_si91x_buffer_queue_t sli_tx_data_queue; + +sli_si91x_performance_profile_t performance_profile; +extern osEventFlagsId_t si91x_events; +extern volatile uint32_t tx_command_queues_status; +extern volatile uint32_t tx_generic_socket_data_queues_status; + +#ifdef SLI_SI91X_ENABLE_BLE +//! Memory length for driver +#define GLOBAL_BUFF_LEN 1500 + +//! Memory to initialize driver +uint8_t global_buf[GLOBAL_BUFF_LEN] = { 0 }; +#endif +// clang-format off +const sl_wifi_scan_configuration_t default_wifi_scan_configuration = { .type = SL_WIFI_SCAN_TYPE_ACTIVE, + .flags = 0, + .periodic_scan_interval = 0, + .channel_bitmap_2g4 = 0xFFFF, + .channel_bitmap_5g = { 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF }, + .lp_mode = 0}; + +// clang-format on +const sl_wifi_buffer_configuration_t default_buffer_configuration = { + .control_buffer_quota = 10, + .tx_buffer_quota = 10, + .rx_buffer_quota = 10, +#ifdef SPI_EXTENDED_TX_LEN_2K + .block_size = 2300, +#else + .block_size = 1616, +#endif + .buffer_memory = NULL, +}; + +const sl_wifi_ap_configuration_t default_wifi_ap_configuration = { + .ssid = { .value = "SILICON_LABS_AP", .length = sizeof("SILICON_LABS_AP") - 1 }, + .security = SL_WIFI_WPA2, + .encryption = SL_WIFI_CCMP_ENCRYPTION, + .channel = { .channel = 11 }, + .rate_protocol = SL_WIFI_RATE_PROTOCOL_AUTO, + .options = 0, + .credential_id = 2, //SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID, + .keepalive_type = SL_SI91X_AP_NULL_BASED_KEEP_ALIVE, + .beacon_interval = 100, + .client_idle_timeout = 120000, + .dtim_beacon_count = 4, + .maximum_clients = 4 +}; + +// clang-format off +static uint8_t firmware_queue_id[SI91X_CMD_MAX] = { [SI91X_COMMON_CMD] = RSI_WLAN_MGMT_Q, + [SI91X_WLAN_CMD] = RSI_WLAN_MGMT_Q, + [SI91X_NETWORK_CMD] = RSI_WLAN_MGMT_Q, + [SI91X_SOCKET_CMD] = RSI_WLAN_MGMT_Q, + [SI91X_BT_CMD] = RSI_BT_Q }; +//static uint32_t response_event_map[SI91X_CMD_MAX] = { [SI91X_COMMON_CMD] = NCP_HOST_COMMON_RESPONSE_EVENT, +// [SI91X_WLAN_CMD] = NCP_HOST_WLAN_RESPONSE_EVENT, +// [SI91X_NETWORK_CMD] = NCP_HOST_NETWORK_RESPONSE_EVENT, +// [SI91X_SOCKET_CMD] = NCP_HOST_SOCKET_RESPONSE_EVENT, +// [SI91X_BT_CMD] = NCP_HOST_BT_RESPONSE_EVENT }; +// clang-format on +#ifdef SLI_SI91X_MCU_INTERFACE +extern sl_wifi_buffer_t *rx_pkt_buffer; +#endif + +static bool si91x_packet_identification_function(const sl_wifi_buffer_t *buffer, const void *user_data) +{ + const uint8_t *packet_id = (const uint8_t *)user_data; + + // Check if the packet's packet ID matches the expected one + return (*packet_id == buffer->id); +} + +void sl_si91x_get_efuse_data(sl_si91x_efuse_data_t *efuse_data) +{ + memcpy(efuse_data, &si91x_efuse_data, sizeof(sl_si91x_efuse_data_t)); +} + +void sl_si91x_set_efuse_data(const sl_si91x_efuse_data_t *efuse_data) +{ + memcpy(&si91x_efuse_data, efuse_data, sizeof(sl_si91x_efuse_data_t)); +} + +sl_status_t sl_si91x_driver_init_wifi_radio(const sl_wifi_device_configuration_t *config) +{ + sl_status_t status; + +// Set 11ax configuration with guard interval if SLI_SI91X_CONFIG_WIFI6_PARAMS is supported +#ifdef SLI_SI91X_CONFIG_WIFI6_PARAMS + status = sl_wifi_set_11ax_config(GUARD_INTERVAL); + VERIFY_STATUS_AND_RETURN(status); +#endif + + // Send WLAN request to set the operating band (2.4GHz or 5GHz) + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_BAND, + SI91X_WLAN_CMD, + &config->band, + 1, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + if (config->boot_config.oper_mode != SL_SI91X_ACCESS_POINT_MODE) { + if (timeout_glbl.active_chan_scan_timeout_value != SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME) { + status = + sl_si91x_configure_timeout(SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT, timeout_glbl.active_chan_scan_timeout_value); + VERIFY_STATUS_AND_RETURN(status); + } + + if (timeout_glbl.auth_assoc_timeout_value != SL_WIFI_DEFAULT_AUTH_ASSOCIATION_TIMEOUT) { + status = + sl_si91x_configure_timeout(SL_SI91X_AUTHENTICATION_ASSOCIATION_TIMEOUT, timeout_glbl.auth_assoc_timeout_value); + VERIFY_STATUS_AND_RETURN(status); + } + + if (timeout_glbl.keep_alive_timeout_value != SL_WIFI_DEFAULT_KEEP_ALIVE_TIMEOUT) { + status = sl_si91x_configure_timeout(SL_SI91X_KEEP_ALIVE_TIMEOUT, timeout_glbl.keep_alive_timeout_value); + VERIFY_STATUS_AND_RETURN(status); + } + if (timeout_glbl.passive_scan_timeout_value != SL_WIFI_DEFAULT_PASSIVE_CHANNEL_SCAN_TIME) { + status = + sl_si91x_configure_timeout(SL_SI91X_CHANNEL_PASSIVE_SCAN_TIMEOUT, timeout_glbl.passive_scan_timeout_value); + VERIFY_STATUS_AND_RETURN(status); + } + } + + // Initialize the WLAN subsystem + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_INIT, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + +#ifndef SL_SI91X_ACX_MODULE + if (IGNORE_REGION != config->region_code) { + // Set the device's region based on configuration + status = sl_si91x_set_device_region(config->boot_config.oper_mode, config->band, config->region_code); + VERIFY_STATUS_AND_RETURN(status); + } +#endif + + // Configure the RTS threshold for WLAN + sl_si91x_config_request_t config_request = { .config_type = CONFIG_RTSTHRESHOLD, .value = RSI_RTS_THRESHOLD }; + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_CONFIG, + SI91X_WLAN_CMD, + &config_request, + sizeof(config_request), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_driver_init(const sl_wifi_device_configuration_t *config, sl_wifi_event_handler_t event_handler) +{ + sl_status_t status; + sl_si91x_host_init_configuration init_config = { 0 }; + const uint8_t select_option = config->boot_option; + if (config->boot_config.coex_mode == SL_SI91X_WLAN_MODE) { // Check for not support mode + return SL_STATUS_NOT_SUPPORTED; + } + + // Determine the default interface based on operating mode (AP or Client) + if (config->boot_config.oper_mode == SL_SI91X_ACCESS_POINT_MODE) { + default_interface = SL_WIFI_AP_INTERFACE; + } else { + default_interface = SL_WIFI_CLIENT_INTERFACE; + } + + // Configure the interface for 5GHz band if selected (currently not supported for Si91x) + if (config->band == SL_SI91X_WIFI_BAND_5GHZ) { + default_interface |= SL_WIFI_5GHZ_INTERFACE; + } else { + default_interface |= SL_WIFI_2_4GHZ_INTERFACE; + } + + // Set the event handler for the SI91x wireless driver + si91x_event_handler = event_handler; + + // Check if the device is already initialized + if (device_initialized) { + // If it's already initialized, ensure the requested operating mode is compatible + if (initialized_opermode == SL_SI91X_CONCURRENT_MODE) { + return (initialized_opermode == config->boot_config.oper_mode) ? SL_STATUS_OK : SL_STATUS_WIFI_INVALID_OPERMODE; + } + return SL_STATUS_ALREADY_INITIALIZED; + } + // Initialize BLE if BLE is enabled +#ifdef SLI_SI91X_ENABLE_BLE + int32_t rsi_status = 0; + rsi_status = rsi_ble_driver_init(global_buf, GLOBAL_BUFF_LEN); + if ((rsi_status < 0) || (rsi_status > GLOBAL_BUFF_LEN)) { + return SL_STATUS_FAIL; + } +#endif + +#ifndef SLI_SI91X_ENABLE_IPV6 + uint32_t *tcp_ip_feature_bit_map = (uint32_t *)&(config->boot_config.tcp_ip_feature_bit_map); + + // check if the module network stack is in IPV6 mode. + if (*tcp_ip_feature_bit_map & (SI91X_IPV6_MODE)) { + return SL_STATUS_NOT_AVAILABLE; + } +#endif + + // Initialize the buffer manager + status = sl_si91x_host_init_buffer_manager(&default_buffer_configuration); + if (status != SL_STATUS_OK) { + return status; + } + + init_config.rx_irq = sl_si91x_bus_rx_irq_handler; + init_config.rx_done = sl_si91x_bus_rx_done_handler; + init_config.boot_option = config->boot_option; + + // Initialize the SI91x host + status = sl_si91x_host_init(&init_config); + VERIFY_STATUS_AND_RETURN(status); + + // Initialize the SI91x platform + status = sl_si91x_platform_init(); + VERIFY_STATUS_AND_RETURN(status); + + // Power cycle the SI91x device + status = sl_si91x_host_power_cycle(); + VERIFY_STATUS_AND_RETURN(status); + + // sl_si91x_bus_init() will be implemented for all available buses + status = sl_si91x_bus_init(); + VERIFY_STATUS_AND_RETURN(status); + +#ifdef SLI_SI91X_MCU_INTERFACE + // firmware bootup is require only for the first time, no need to do it again if we call init after deinit + static bool is_bootup_firmware_required = true; + if (is_bootup_firmware_required) { + status = si91x_bootup_firmware(select_option); + VERIFY_STATUS_AND_RETURN(status); + is_bootup_firmware_required = false; + } else { + // Initialize NWP interrupt and submit RX packets + sli_m4_ta_interrupt_init(); + sli_si91x_submit_rx_pkt(); + } +#else + status = si91x_bootup_firmware(select_option); + VERIFY_STATUS_AND_RETURN(status); +#endif + + // Initialize task register index to save firmware status + status = sli_fw_status_storage_index_init(); + VERIFY_STATUS_AND_RETURN(status); + +#ifdef SL_SI91X_SPI_HIGH_SPEED_ENABLE + // Enable high speed bus on the device and the host + status = sl_si91x_bus_enable_high_speed(); + VERIFY_STATUS_AND_RETURN(status); + sl_si91x_host_enable_high_speed_bus(); +#endif + sl_si91x_host_enable_bus_interrupt(); + +// Wait for card ready command response +#ifdef SLI_SI91X_MCU_INTERFACE + // NWP would not send card ready command response, if we call init after deinit + + if (get_card_ready_required()) { + uint32_t events = sli_si91x_wait_for_event(NCP_HOST_COMMON_RESPONSE_EVENT, 5000); + if (!(events & NCP_HOST_COMMON_RESPONSE_EVENT)) { + return SL_STATUS_CARD_READY_TIMEOUT; + } + set_card_ready_required(false); + } +#else + uint32_t events = sli_si91x_wait_for_event(NCP_HOST_COMMON_RESPONSE_EVENT, 3000); + if (!(events & NCP_HOST_COMMON_RESPONSE_EVENT)) { + return SL_STATUS_CARD_READY_TIMEOUT; + } +#endif + // Send WLAN request to set the operating mode and configuration + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_OPERMODE, + SI91X_COMMON_CMD, + &config->boot_config, + sizeof(sl_si91x_boot_configuration_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); +#ifdef SL_WDT_MANAGER_PRESENT + sl_si91x_nwp_configuration_t nwp_config; + + // NWP WDT configuration + memset(&nwp_config, 0, sizeof(sl_si91x_nwp_configuration_t)); + nwp_config.code = SL_SI91X_ENABLE_NWP_WDT_FROM_HOST; + nwp_config.values.wdt_timer_val = 0x20; + nwp_config.values.wdt_enable_in_ps = 0; + status = sl_si91x_set_nwp_config_request(nwp_config); + VERIFY_STATUS_AND_RETURN(status); +#endif + + feature_bit_map = config->boot_config.feature_bit_map; + +#ifdef SLI_SI91X_ENABLE_BLE + if (config->boot_config.coex_mode == SL_SI91X_BLE_MODE || config->boot_config.coex_mode == SL_SI91X_WLAN_BLE_MODE) { + // Wait for BT card ready + rsi_bt_common_init(); + } +#endif + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_DYNAMIC_POOL, + SI91X_WLAN_CMD, + &config->ta_pool, + sizeof(sl_si91x_dynamic_pool), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + // Configure various wireless features + sl_si91x_feature_frame_request feature_frame_request = { .pll_mode = PLL_MODE, + .rf_type = RF_TYPE, + .wireless_mode = WIRELESS_MODE, + .enable_ppp = ENABLE_PPP, + .afe_type = AFE_TYPE, + .feature_enables = FEATURE_ENABLES }; + + // Setting PLL mode to 1 in case of high clock frequency + //pll_mode 1 is not supported in coex mode + if ((!config->boot_config.coex_mode) + && (config->boot_config.custom_feature_bit_map + & (SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_160MHZ | SL_SI91X_CUSTOM_FEAT_SOC_CLK_CONFIG_120MHZ))) { + feature_frame_request.pll_mode = 1; + } else { + feature_frame_request.pll_mode = 0; + } + + // For the transmit test mode we need to disable BIT 0, 4, 5. These bitmaps are only required in powersave. + // To receive broadcast data packets in transceiver opermode, we need to enable BIT 1. + if (config->boot_config.oper_mode == SL_SI91X_TRANSMIT_TEST_MODE) { + feature_frame_request.feature_enables &= ~(FEATURE_ENABLES); + } else if (config->boot_config.oper_mode == SL_SI91X_TRANSCEIVER_MODE) { + feature_frame_request.feature_enables |= SI91X_FEAT_FRAME_PERMIT_UNDESTINED_PACKETS; + } else { + feature_frame_request.feature_enables = feature_frame_request.feature_enables; + } + + // Dispatch a feature request frame to the SI91x driver + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_FEATURE_FRAME, + SI91X_COMMON_CMD, + &feature_frame_request, + sizeof(feature_frame_request), + SL_SI91X_WAIT_FOR(10000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + // if 16th bit of ext_tcp_ip_feature_bit_map is not set, then firmware auto closes the TCP socket on remote termination. + save_tcp_auto_close_choice( + (config->boot_config.ext_tcp_ip_feature_bit_map & SL_SI91X_EXT_TCP_IP_WAIT_FOR_SOCKET_CLOSE) == 0); + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + sli_si91x_socket_init(SLI_SI91X_GET_TCP_IP_TOTAL_SELECTS_BITS(config->boot_config.ext_tcp_ip_feature_bit_map)); + VERIFY_STATUS_AND_RETURN(status); +#endif + + // Set the MAC address if provided in the configuration + if (config->mac_address != NULL) { + status = sl_wifi_set_mac_address(default_interface, config->mac_address); + VERIFY_STATUS_AND_RETURN(status); + } + + // Initialize the WiFi radio if the coexistence mode is not BLE + if (config->boot_config.coex_mode != SL_SI91X_BLE_MODE) { + status = sl_si91x_driver_init_wifi_radio(config); + VERIFY_STATUS_AND_RETURN(status); + } + + // Check and update the frontend switch control based on custom feature bit map + if (config->boot_config.custom_feature_bit_map & SL_SI91X_CUSTOM_FEAT_EXTENSION_VALID) { + frontend_switch_control = (config->boot_config.ext_custom_feature_bit_map & (BIT(29) | (BIT(30)))); + } + +#ifdef SLI_SI91X_MCU_INTERFACE + // Program wireless GPIO front-end switch controls + if (frontend_switch_control != 0) { + sli_si91x_configure_wireless_frontend_controls(frontend_switch_control); + } +#endif + // Mark the device as initialized + device_initialized = true; + initialized_opermode = config->boot_config.oper_mode; + + // Set interface status flags based on operating mode and band + if ((config->boot_config.oper_mode == SL_SI91X_CLIENT_MODE) + || (config->boot_config.oper_mode == SL_SI91X_ENTERPRISE_CLIENT_MODE) + || (config->boot_config.oper_mode == SL_SI91X_CONCURRENT_MODE) + || (config->boot_config.oper_mode == SL_SI91X_TRANSMIT_TEST_MODE)) { + if (config->band == SL_SI91X_WIFI_BAND_2_4GHZ) { + interface_is_up[SL_WIFI_CLIENT_2_4GHZ_INTERFACE_INDEX] = true; + } else if (config->band == SL_SI91X_WIFI_BAND_5GHZ) { + interface_is_up[SL_WIFI_CLIENT_5GHZ_INTERFACE_INDEX] = true; + } + } + // Save the coexistence mode in the driver + save_coex_mode(config->boot_config.coex_mode); +#ifdef SL_SI91X_GET_EFUSE_DATA + status = sl_si91x_get_flash_efuse_data(&si91x_efuse_data, config->efuse_data_type); +#endif +#ifdef SLI_SI91X_MCU_INTERFACE + if (status == SL_STATUS_OK) { + /* send a notification to the NWP indicating whether the M4 core is currently utilizing the XTAL as its clock source*/ + sli_si91x_send_m4_xtal_usage_notification_to_ta(); + } +#endif + + return status; +} + +sl_status_t sl_si91x_driver_deinit(void) +{ + sl_status_t status = SL_STATUS_OK; + + // Check if the device has been initialized if not, return an error + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + +#ifdef SLI_SI91X_MCU_INTERFACE + // If the SLI_SI91X_MCU_INTERFACE is defined, perform a soft reset + status = sl_si91x_soft_reset(); + VERIFY_STATUS_AND_RETURN(status); + + // Mask specific interrupts related to packet transfer + mask_ta_interrupt(TX_PKT_TRANSFER_DONE_INTERRUPT | RX_PKT_TRANSFER_DONE_INTERRUPT); +#endif + +#ifdef SLI_SI91X_ENABLE_BLE + int32_t rsi_status = 0; + // If SLI_SI91X_ENABLE_BLE is defined, deinitialize the BLE driver and check for errors + rsi_status = rsi_ble_driver_deinit(); + if (rsi_status != RSI_SUCCESS) { + return SL_STATUS_FAIL; + } +#endif + + // Flush all TX Wi-Fi queues with the status indicating Wi-Fi connection is lost + sli_si91x_flush_all_tx_wifi_queues(SL_STATUS_WIFI_CONNECTION_LOST); + + // Flush the generic TX data queue + sli_si91x_flush_generic_data_queues(&sli_tx_data_queue); + +#if defined(SLI_SI91X_OFFLOAD_NETWORK_STACK) && defined(SLI_SI91X_SOCKETS) + + // Flush all pending socket commands in the client VAP queue due to Wi-Fi connection loss + sli_si91x_flush_all_socket_command_queues(SL_STATUS_WIFI_CONNECTION_LOST, SL_SI91X_WIFI_CLIENT_VAP_ID); + + // Flush all pending socket data in the client VAP queue due to Wi-Fi connection loss + sli_si91x_flush_all_socket_data_queues(SL_SI91X_WIFI_CLIENT_VAP_ID); + + // Flush all pending socket commands in the AP VAP queue due to Wi-Fi connection loss + sli_si91x_flush_all_socket_command_queues(SL_STATUS_WIFI_CONNECTION_LOST, SL_SI91X_WIFI_AP_VAP_ID); + + // Flush all pending socket data in the AP VAP queue due to Wi-Fi connection loss + sli_si91x_flush_all_socket_data_queues(SL_SI91X_WIFI_AP_VAP_ID); + + // Shutdown and change the state of the client VAP sockets + status = sli_si91x_vap_shutdown(SL_SI91X_WIFI_CLIENT_VAP_ID); + VERIFY_STATUS_AND_RETURN(status); + + // Shutdown and change the state of the AP VAP sockets + status = sli_si91x_vap_shutdown(SL_SI91X_WIFI_AP_VAP_ID); + VERIFY_STATUS_AND_RETURN(status); + + // Deinitialize and free all socket-related resources + status = sli_si91x_socket_deinit(); + VERIFY_STATUS_AND_RETURN(status); + +#endif // End of check for offloaded network stack and sockets + + // Deinitialize the SI91x platform + status = sl_si91x_platform_deinit(); + VERIFY_STATUS_AND_RETURN(status); + + // Deinitialize the SI91x host + status = sl_si91x_host_deinit(); + VERIFY_STATUS_AND_RETURN(status); + +#ifdef SLI_SI91X_MCU_INTERFACE + // Check the RX buffer valid bit is set or not. + if (M4SS_P2P_INTR_SET_REG & RX_BUFFER_VALID) { + + // Clear the RX buffer valid bit. + M4SS_P2P_INTR_CLR_REG = (RX_BUFFER_VALID); + + // Clear the RX buffer. + sl_si91x_host_free_buffer(rx_pkt_buffer); + } +#endif + + // Deinitialize the buffer manager + status = sl_si91x_host_deinit_buffer_manager(); + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_host_disable_bus_interrupt(); + + status = sl_si91x_host_power_cycle(); + VERIFY_STATUS_AND_RETURN(status); + + // Clear the event handler and reset initialization status + si91x_event_handler = NULL; + device_initialized = false; + initialized_opermode = SL_SI91X_INVALID_MODE; + + // Reset all the interfaces + memset(interface_is_up, 0, sizeof(interface_is_up)); + + return status; +} + +sl_status_t sl_si91x_get_flash_efuse_data(sl_si91x_efuse_data_t *efuse_data, uint8_t efuse_data_type) +{ + sl_status_t status; + sl_wifi_buffer_t *buffer = NULL; + SL_WIFI_ARGS_CHECK_NULL_POINTER(efuse_data); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_GET_EFUSE_DATA, + SI91X_COMMON_CMD, + &efuse_data_type, + sizeof(efuse_data_type), + SL_SI91X_WAIT_FOR_RESPONSE(15000), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + const sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (packet->length > 0) { + switch (efuse_data_type) { + case SL_SI91X_EFUSE_MFG_SW_VERSION: + memcpy(&efuse_data->mfg_sw_version, packet->data, packet->length); + break; + case SL_SI91X_EFUSE_PTE_CRC: + memcpy(&efuse_data->pte_crc, packet->data, packet->length); + break; + default: + break; + } + } + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_driver_raw_send_command(uint8_t command, + const void *data, + uint32_t data_length, + uint32_t wait_time) +{ + UNUSED_PARAMETER(wait_time); + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sl_status_t status = SL_STATUS_OK; + + // Allocate a data buffer with space for the data and metadata + status = sl_si91x_allocate_data_buffer(&buffer, + (void **)&packet, + sizeof(sl_si91x_packet_t) + data_length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + VERIFY_STATUS_AND_RETURN(status); + + // If the packet is not allocated successfully, return an allocation failed error + if (packet == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + + // Clear the packet descriptor and copy the command data if available + memset(packet->desc, 0, sizeof(packet->desc)); + if (data != NULL) { + memcpy(packet->data, data, data_length); + } + packet->length = data_length & 0xFFF; + packet->command = command; + + // Adding the packet to the queue with atomic action + return sl_si91x_driver_send_data_packet(buffer, wait_time); +} + +sl_status_t sl_si91x_driver_send_socket_data(const sli_si91x_socket_send_request_t *request, + const void *data, + uint32_t wait_time) +{ + UNUSED_PARAMETER(wait_time); + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sli_si91x_socket_send_request_t *send; + + sl_status_t status = SL_STATUS_OK; + uint16_t header_length = (request->data_offset - sizeof(sli_si91x_socket_send_request_t)); + uint32_t data_length = request->length; + + if (data == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Allocate a buffer for the socket data with appropriate size + status = sl_si91x_host_allocate_buffer( + &buffer, + SL_WIFI_TX_FRAME_BUFFER, + sizeof(sl_si91x_packet_t) + sizeof(sli_si91x_socket_send_request_t) + header_length + data_length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + + VERIFY_STATUS_AND_RETURN(status); + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + // If the packet is not allocated successfully, return an allocation failed error + if (packet == NULL) { + return SL_STATUS_WIFI_BUFFER_ALLOC_FAIL; + } + + memset(packet->desc, 0, sizeof(packet->desc)); + + send = (sli_si91x_socket_send_request_t *)packet->data; + memcpy(send, request, sizeof(sli_si91x_socket_send_request_t)); + memcpy((send->send_buffer + header_length), data, data_length); + + // Fill frame type + packet->length = (sizeof(sli_si91x_socket_send_request_t) + header_length + data_length) & 0xFFF; + + return sl_si91x_driver_send_data_packet(buffer, wait_time); +} + +sl_status_t sl_si91x_custom_driver_send_command(uint32_t command, + sl_si91x_command_type_t command_type, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer, + uint8_t custom_host_desc) +{ + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sl_status_t status; + + // Check if the queue type is within valid range + if (command_type >= SI91X_CMD_MAX) { + return SL_STATUS_INVALID_INDEX; + } + + // Allocate a buffer for the command with appropriate size + status = sli_si91x_allocate_command_buffer(&buffer, + (void **)&packet, + sizeof(sl_si91x_packet_t) + data_length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + VERIFY_STATUS_AND_RETURN(status); + + // Clear the packet descriptor and copy the command data if available + memset(packet->desc, 0, sizeof(packet->desc)); + if (data != NULL) { + memcpy(packet->data, data, data_length); + } + + // Fill frame type + packet->length = data_length & 0xFFF; + packet->command = (uint16_t)command; + // Fill the packet identifier + packet->unused[1] = custom_host_desc; + return sl_si91x_driver_send_command_packet(command, command_type, buffer, wait_period, sdk_context, data_buffer); +} + +sl_status_t sl_si91x_driver_send_command(uint32_t command, + sl_si91x_command_type_t command_type, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer) +{ + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sl_status_t status; + + // Check if the queue type is within valid range + if (command_type >= SI91X_CMD_MAX) { + return SL_STATUS_INVALID_INDEX; + } + + // Allocate a buffer for the command with appropriate size + status = sli_si91x_allocate_command_buffer(&buffer, + (void **)&packet, + sizeof(sl_si91x_packet_t) + data_length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + VERIFY_STATUS_AND_RETURN(status); + + // Clear the packet descriptor and copy the command data if available + memset(packet->desc, 0, sizeof(packet->desc)); + if (data != NULL) { + memcpy(packet->data, data, data_length); + } + + // Set SLI_SI91X_FEAT_FW_UPDATE_NEW_CODE in the feature bit map to retrieve the latest firmware result codes + if (command == RSI_COMMON_REQ_OPERMODE) { + sl_si91x_boot_configuration_t *boot_configuration = (sl_si91x_boot_configuration_t *)packet->data; + boot_configuration->feature_bit_map |= SLI_SI91X_FEAT_FW_UPDATE_NEW_CODE; + } + + // Fill frame type + packet->length = data_length & 0xFFF; + packet->command = (uint16_t)command; + return sl_si91x_driver_send_command_packet(command, command_type, buffer, wait_period, sdk_context, data_buffer); +} + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +sl_status_t sl_si91x_driver_send_side_band_crypto(uint32_t command, + const void *data, + uint32_t data_length, + sl_si91x_wait_period_t wait_period) +{ + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + uint32_t result; + sl_status_t status = SL_STATUS_OK; + + // Allocate a buffer for the command with appropriate size + status = sli_si91x_allocate_command_buffer(&buffer, (void **)&packet, sizeof(sl_si91x_packet_t) + data_length, 1000); + VERIFY_STATUS_AND_RETURN(status); + + // Clear the packet descriptor and copy the command data if available + memset(packet->desc, 0, sizeof(packet->desc)); + if (data != NULL) { + memcpy(packet->data, data, data_length); + } + + // Fill frame type + packet->length = data_length & 0xFFF; + packet->command = command; + + // Acquire Mutex + osMutexAcquire(side_band_crypto_mutex, 0xFFFFFFFFUL); + + // fill crypto desc + crypto_desc[0].addr = (uint32_t)packet->desc; + crypto_desc[0].length = SL_HOST_DESC_LEN; + crypto_desc[1].addr = (uint32_t)packet->data; + crypto_desc[1].length = SL_CRYPTO_PKT_LEN; + + //! Enter Critical Section + __disable_irq(); + + sli_si91x_raise_side_band_interrupt_to_ta(); + + //! Exit Critical Section + __enable_irq(); + + result = + osEventFlagsWait(ta_events, SIDE_BAND_DONE, (osFlagsWaitAny), (wait_period & ~SL_SI91X_WAIT_FOR_RESPONSE_BIT)); + if (result == (uint32_t)osErrorTimeout || result == (uint32_t)osErrorResource) { + osMutexRelease(side_band_crypto_mutex); + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_TIMEOUT; + } + + status = + (((uint8_t *)crypto_desc[0].addr)[12] + (((uint8_t *)crypto_desc[0].addr)[13] << 8)); // Extract the frame status + + // Release Mutex + osMutexRelease(side_band_crypto_mutex); + + sl_si91x_host_free_buffer(buffer); + return status; +} +#endif + +sl_status_t sl_si91x_driver_send_bt_command(rsi_wlan_cmd_request_t command, + sl_si91x_command_type_t command_type, + sl_wifi_buffer_t *data, + uint8_t sync_command) +{ + sl_si91x_wait_period_t wait_period = SL_SI91X_RETURN_IMMEDIATELY; + + // Check if the queue type is within valid range + if (command_type >= SI91X_CMD_MAX) { + + return SL_STATUS_INVALID_INDEX; + } + + if (sync_command) { + return sl_si91x_driver_send_command_packet(command, command_type, data, wait_period, NULL, NULL); + } else { + return sl_si91x_driver_send_async_command(command, command_type, data, 0); + } +} + +sl_status_t sl_si91x_driver_wait_for_response(rsi_wlan_cmd_request_t command, sl_si91x_wait_period_t wait_period) +{ + UNUSED_PARAMETER(command); + UNUSED_PARAMETER(wait_period); +#ifdef SI91x_ENABLE_WAIT_ON_RESULTS + // Wait for WLAN response events with a specified timeout + uint32_t events = + sli_si91x_wait_for_event(NCP_HOST_WLAN_RESPONSE_EVENT, (wait_period & ~SL_SI91X_WAIT_FOR_RESPONSE_BIT)); + + sli_si91x_clear_event(NCP_HOST_WLAN_RESPONSE_EVENT); + + //TODO: Change error handling from event based to response + if (events & NCP_HOST_WLAN_RESPONSE_EVENT) { + return convert_and_save_firmware_status(si91x_frame_error_status); + } else if (events == 0) { + return SL_STATUS_TIMEOUT; + } +#endif + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sli_si91x_driver_wait_for_response_packet(sl_si91x_buffer_queue_t *queue, + osEventFlagsId_t event_flag, + uint32_t event_mask, + uint16_t packet_id, + sl_si91x_wait_period_t wait_period, + sl_wifi_buffer_t **packet_buffer) +{ + // Verify that packet_buffer is a valid pointer, return error if invalid + SL_VERIFY_POINTER_OR_RETURN(packet_buffer, SL_STATUS_INVALID_PARAMETER); + + // Variables to store event flags, start time, and elapsed time + uint32_t events = 0; + uint32_t start_time = osKernelGetTickCount(); // Capture the start time of the wait period + uint32_t elapsed_time = 0; // Elapsed time tracker + sl_wifi_buffer_t *buffer; + + do { + // Wait for event flag(s) to be set within the specified wait period. + // This blocks the thread until any event in the mask is set or a timeout occurs. + events = osEventFlagsWait(event_flag, event_mask, (osFlagsWaitAny | osFlagsNoClear), (wait_period - elapsed_time)); + + // If the event wait times out or resources are unavailable, return timeout status + if (events == (uint32_t)osErrorTimeout || events == (uint32_t)osErrorResource) { + return SL_STATUS_TIMEOUT; + } + + // Log the event and queue details (for debugging purposes) + SL_DEBUG_LOG("Event: %u, queue %u\n", events, queue); + + // Traverse the queue to check if the packet with the desired packet_id is at the head. + // Introduce a delay if the head of the queue packet doesn't belong to the current thread. + // This allows other threads to process the packet at the head. + do { + buffer = queue->head; // Peek at the head of the queue + } while ((buffer != NULL) && (buffer->id != packet_id) + && osDelay(1) == 0); // Delay to yield if packet_id does not match + + // Update the elapsed time since the start of the wait + elapsed_time = sl_si91x_host_elapsed_time(start_time); + + } while (buffer == NULL || (buffer->id != packet_id)); // Loop until the correct packet is found or timeout occurs + + // Remove the identified packet from the queue + sli_si91x_pop_from_buffer_queue(queue, &buffer); + + // Assign the identified packet to packet_buffer + *packet_buffer = buffer; + + // Enter atomic section to ensure thread safety while clearing the event flag + CORE_irqState_t state = CORE_EnterAtomic(); + // If the queue is empty after popping the packet, clear the event flag to avoid unnecessary waits + if (queue->head == NULL) { + osEventFlagsClear(event_flag, event_mask); + } + CORE_ExitAtomic(state); // Exit atomic section + + return SL_STATUS_OK; // Return success status +} + +sl_status_t sl_si91x_driver_send_command_packet(uint32_t command, + sl_si91x_command_type_t command_type, + sl_wifi_buffer_t *buffer, + sl_si91x_wait_period_t wait_period, + void *sdk_context, + sl_wifi_buffer_t **data_buffer) +{ + uint16_t firmware_status; + sli_si91x_queue_packet_t *node = NULL; + sl_status_t status; + sl_wifi_buffer_t *packet; + sl_wifi_buffer_t *response; + uint8_t flags = 0; + uint16_t data_length = 0; + // sl_si91x_driver_context_t context = { 0 }; + sl_si91x_wait_period_t wait_time = 0; + static uint8_t command_packet_id = 0; + + // Allocate a command packet and set flags based on the command type + status = sli_si91x_allocate_command_buffer(&packet, + (void **)&node, + sizeof(sli_si91x_queue_packet_t), + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + if (status != SL_STATUS_OK) { + sl_si91x_host_free_buffer(buffer); + return status; + } + +#ifdef RSI_CHIP_MFG_EN + // WLAN soc frequency + if (command == RSI_BOOTUP_PARAMS) { + host_desc[14] = RSI_SOC_FREQ; + } +#endif + + // Check the wait_period to determine the flags for packet handling + if (wait_period == SL_SI91X_RETURN_IMMEDIATELY) { + // If wait_period indicates an immediate return, set flags to 0 + flags = 0; + } else { + // If not an immediate return, set the SI91X_PACKET_RESPONSE_STATUS flag + flags |= SI91X_PACKET_RESPONSE_STATUS; + // Additionally, set the SI91X_PACKET_RESPONSE_PACKET flag if the SL_SI91X_WAIT_FOR_RESPONSE_BIT is set in wait_period + if (data_buffer != NULL) { + flags |= ((wait_period & SL_SI91X_WAIT_FOR_RESPONSE_BIT) ? SI91X_PACKET_RESPONSE_PACKET : 0); + } + } + + // Check the command type and set the flags accordingly + switch (command) { + case RSI_COMMON_REQ_PWRMODE: + case RSI_COMMON_REQ_OPERMODE: + case RSI_COMMON_REQ_SOFT_RESET: + flags |= SI91X_PACKET_GLOBAL_QUEUE_BLOCK; + break; + default: + break; + } + + // Set various properties of the node representing the command packet + node->host_packet = buffer; + node->firmware_queue_id = firmware_queue_id[command_type]; + node->command_type = command_type; + node->flags = flags; + node->sdk_context = sdk_context; + + // Configure the context for packet handling + // context.packet = node; + // context.payload = &(queue_packet_id[command_type]); + + if (flags != SI91X_PACKET_WITH_ASYNC_RESPONSE) { + node->command_tickcount = osKernelGetTickCount(); + // Calculate the wait time based on wait_period + if ((wait_period & SL_SI91X_WAIT_FOR_EVER) == SL_SI91X_WAIT_FOR_EVER) { + node->command_timeout = osWaitForever; + } else { + node->command_timeout = (wait_period & ~SL_SI91X_WAIT_FOR_RESPONSE_BIT); + } + } + + //! Enter Critical Section + CORE_irqState_t state = CORE_EnterAtomic(); + + const uint8_t this_packet_id = command_packet_id; + command_packet_id++; + buffer->id = this_packet_id; + packet->id = this_packet_id; + packet->node.node = NULL; + sli_si91x_append_to_buffer_queue(&cmd_queues[command_type].tx_queue, packet); + tx_command_queues_status |= SL_SI91X_TX_PENDING_FLAG(command_type); + sl_si91x_host_set_bus_event(SL_SI91X_TX_PENDING_FLAG(command_type)); + CORE_ExitAtomic(state); + + // Check if the command should return immediately or wait for a response + if (wait_period == SL_SI91X_RETURN_IMMEDIATELY) { + return SL_STATUS_IN_PROGRESS; + } + + // Calculate the wait time based on wait_period + if ((wait_period & SL_SI91X_WAIT_FOR_EVER) == SL_SI91X_WAIT_FOR_EVER) { + wait_time = osWaitForever; + } else { + wait_time = (wait_period & ~SL_SI91X_WAIT_FOR_RESPONSE_BIT); + } + + // Wait for a response packet and handle it + status = sli_si91x_driver_wait_for_response_packet(&cmd_queues[command_type].rx_queue, + si91x_events, + SL_SI91X_RESPONSE_FLAG(command_type), + this_packet_id, + wait_time, + &response); + // Check if the status is SL_STATUS_TIMEOUT, indicating a timeout has occurred + if (status == SL_STATUS_TIMEOUT) { + // Declare a temporary packet pointer to hold the packet to be removed + sl_wifi_buffer_t *temp_packet; + sl_status_t temp_status = sli_si91x_remove_buffer_from_queue_by_comparator(&cmd_queues[command_type].tx_queue, + &this_packet_id, + si91x_packet_identification_function, + &temp_packet); + + // Check if the packet removal was successful + if (temp_status == SL_STATUS_OK) { + + // Retrieve the actual packet node data from the removed buffer + sli_si91x_queue_packet_t *temp_node = sl_si91x_host_get_buffer_data(temp_packet, 0, NULL); + + // Free the host packet memory associated with the node (TX packet memory) + sl_si91x_host_free_buffer(temp_node->host_packet); + + // Free the temporary buffer memory that held the packet + sl_si91x_host_free_buffer(temp_packet); + } + } + VERIFY_STATUS_AND_RETURN(status); + + // Process the response packet and return the firmware status + node = (sli_si91x_queue_packet_t *)sl_si91x_host_get_buffer_data(response, 0, &data_length); + firmware_status = node->frame_status; + + // If a data_buffer is provided, set it to the host_packet + if (NULL != data_buffer) { + *data_buffer = node->host_packet; + } + // If the response packet flag is set, free the host_packet buffer + else if (SI91X_PACKET_RESPONSE_PACKET == (node->flags & SI91X_PACKET_RESPONSE_PACKET)) { + sl_si91x_host_free_buffer(node->host_packet); + } + + // Free the response buffer and return the firmware status + sl_si91x_host_free_buffer(response); + return convert_and_save_firmware_status(firmware_status); +} + +static sl_status_t sl_si91x_driver_send_data_packet(sl_wifi_buffer_t *buffer, uint32_t wait_time) +{ + UNUSED_PARAMETER(wait_time); + sli_si91x_append_to_buffer_queue(&sli_tx_data_queue, buffer); + CORE_irqState_t state = CORE_EnterAtomic(); + tx_generic_socket_data_queues_status |= SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT; + sl_si91x_host_set_bus_event(SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT); + CORE_ExitAtomic(state); + + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_driver_send_async_command(uint32_t command, + sl_si91x_command_type_t command_type, + void *data, + uint32_t data_length) +{ + + sli_si91x_queue_packet_t *node = NULL; + sl_status_t return_status; + // sl_si91x_driver_context_t context = { 0 }; + sl_wifi_buffer_t *raw_rx_buffer; + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *raw_rx_packet; + sl_status_t status; + + if (command_type == SI91X_BT_CMD) { + // BLE packet is created in upper layer, no allocations required here. + raw_rx_buffer = (sl_wifi_buffer_t *)data; + } else { + status = sli_si91x_allocate_command_buffer(&raw_rx_buffer, + (void **)&raw_rx_packet, + sizeof(sl_si91x_packet_t) + data_length, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + VERIFY_STATUS_AND_RETURN(status); + + memset(raw_rx_packet->desc, 0, sizeof(raw_rx_packet->desc)); + if (data != NULL) { + memcpy(raw_rx_packet->data, data, data_length); + } + + // Fill frame type + raw_rx_packet->length = data_length & 0xFFF; + raw_rx_packet->command = (uint16_t)command; + } + + return_status = sli_si91x_allocate_command_buffer(&buffer, + (void **)&node, + sizeof(sli_si91x_queue_packet_t), + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + + if (return_status != SL_STATUS_OK) { + sl_si91x_host_free_buffer(raw_rx_buffer); + return return_status; + } + +#ifdef RSI_CHIP_MFG_EN + // WLAN soc frequency + if (command == RSI_BOOTUP_PARAMS) { + host_desc[14] = RSI_SOC_FREQ; + } +#endif + + // Configure the node representing the command packet + node->host_packet = raw_rx_buffer; + node->firmware_queue_id = firmware_queue_id[command_type]; + node->command_type = command_type; + node->sdk_context = NULL; + node->flags = SI91X_PACKET_WITH_ASYNC_RESPONSE; + + CORE_irqState_t irqState = CORE_EnterAtomic(); + buffer->id = 0; // Does not use packet ID as async packets do not have a matching response + sli_si91x_append_to_buffer_queue(&cmd_queues[command_type].tx_queue, buffer); + tx_command_queues_status |= SL_SI91X_TX_PENDING_FLAG(command_type); + sl_si91x_host_set_bus_event(SL_SI91X_TX_PENDING_FLAG(command_type)); + CORE_ExitAtomic(irqState); + + return SL_STATUS_OK; +} + +/* + * Verifies that the device has booted successfully. + * @return SL_STATUS_OK if verification successful + * otherwise RSI_ERROR_WAITING_FOR_BOARD_READY, RSI_ERROR_BOOTUP_OPTIONS_NOT_SAVED, RSI_ERROR_BOOTUP_OPTIONS_CHECKSUM_FAIL + */ +sl_status_t sli_verify_device_boot(uint32_t *rom_version) +{ + sl_status_t status; + uint8_t value[2] = { 0, 0 }; + + // Read a memory register to check if it's valid + status = sl_si91x_bus_read_memory(RSI_HOST_INTF_REG_OUT, 2, &value[0]); + VERIFY_STATUS(status); + + // Verify register read was valid + if (value[1] != SLI_WIFI_REGISTER_VALID) { + return SL_STATUS_WAITING_FOR_BOARD_READY; + } + + // Verify register value + if (value[0] == RSI_BOOTUP_OPTIONS_LAST_CONFIG_NOT_SAVED) { + return SL_STATUS_BOOTUP_OPTIONS_NOT_SAVED; + } else if (value[0] == RSI_BOOTUP_OPTIONS_CHECKSUM_FAIL) { + return SL_STATUS_BOOTUP_OPTIONS_CHECKSUM_FAILURE; + } +#if RSI_BOOTLOADER_VERSION_CHECK + else if (value[0] == RSI_BOOTLOADER_VERSION) { + } else { + return SL_STATUS_BOOTLOADER_VERSION_MISMATCH; + } +#endif + + // Extract ROM version info + if (value[0] == RSI_BOOTLOADER_VERSION_1P0) { + *rom_version = RSI_ROM_VERSION_1P0; + } else if (value[0] == RSI_BOOTLOADER_VERSION_1P1) { + *rom_version = RSI_ROM_VERSION_1P1; + } + + return SL_STATUS_OK; +} + +/**************************************************************************/ /** + * @brief Allocate a buffer for the Wi-Fi driver + * + * @param buffer + * @param buffer_size is the size of the buffer to allocate + * @param wait_duration_ms is the duration before returning SL_TIMEOUT + * @return SL_STATUS_OK if the values are retrieved correctly, + * SL_TIMEOUT if the buffer is not allocated in time, SL_ERROR otherwise + *****************************************************************************/ +sl_status_t sli_si91x_allocate_command_buffer(sl_wifi_buffer_t **host_buffer, + void **buffer, + uint32_t requested_buffer_size, + uint32_t wait_duration_ms) +{ + // Allocate a buffer from the SI91x host for WLAN control messages + sl_status_t status = + sl_si91x_host_allocate_buffer(host_buffer, SL_WIFI_CONTROL_BUFFER, requested_buffer_size, wait_duration_ms); + VERIFY_STATUS_AND_RETURN(status); + + uint16_t temp; + // Get a pointer to the allocated buffer's data area + *buffer = sl_si91x_host_get_buffer_data(*host_buffer, 0, &temp); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_allocate_data_buffer(sl_wifi_buffer_t **host_buffer, + void **buffer, + uint32_t data_size, + uint32_t wait_duration_ms) +{ + // Allocate a buffer from the SI91x host for WLAN data transmission + sl_status_t status = + sl_si91x_host_allocate_buffer(host_buffer, + SL_WIFI_TX_FRAME_BUFFER, + sizeof(sl_si91x_packet_t) + sizeof(sli_si91x_socket_send_request_t) + data_size, + wait_duration_ms); + VERIFY_STATUS_AND_RETURN(status); + + uint16_t temp; + // Get a pointer to the allocated buffer's data area + *buffer = sl_si91x_host_get_buffer_data(*host_buffer, 0, &temp); + return SL_STATUS_OK; +} + +sl_status_t sli_wifi_select_option(const uint8_t configuration) +{ + uint16_t boot_command = 0; + sl_status_t status = 0; + uint16_t read_value = 0; + + // Write a boot command to initiate the option selection + status = sl_si91x_bus_write_memory(RSI_HOST_INTF_REG_OUT, 2, (uint8_t *)&boot_command); + VERIFY_STATUS_AND_RETURN(status); + + if ((configuration == BURN_NWP_FW) || (configuration == BURN_M4_FW)) { + boot_command = RSI_HOST_INTERACT_REG_VALID_FW | configuration; + } else { + boot_command = RSI_HOST_INTERACT_REG_VALID | configuration; + } + + if (configuration == BURN_M4_FW) { + boot_command |= M4_FW_IMAGE_NUMBER; + } + + // Write the configuration to the SI91x host for option selection + status = sl_si91x_bus_write_memory(RSI_HOST_INTF_REG_IN, 2, (uint8_t *)&boot_command); + VERIFY_STATUS_AND_RETURN(status); + + // Check for a specific response to ensure successful option selection + if ((configuration != LOAD_NWP_FW) && (configuration != LOAD_DEFAULT_NWP_FW_ACTIVE_LOW)) { + uint32_t timestamp = sl_si91x_host_get_timestamp(); + while (sl_si91x_host_elapsed_time(timestamp) < 300) { + status = sl_si91x_bus_read_memory(RSI_HOST_INTF_REG_OUT, 2, (uint8_t *)&read_value); + VERIFY_STATUS_AND_RETURN(status); + + if ((configuration == BURN_NWP_FW) || (configuration == BURN_M4_FW)) { + if (read_value == (RSI_HOST_INTERACT_REG_VALID | RSI_SEND_RPS_FILE)) { + return SL_STATUS_OK; + } + } else if (read_value == (RSI_HOST_INTERACT_REG_VALID | configuration)) { + return SL_STATUS_OK; + } + } + } else { + // Check up to 3 seconds for firmware load or upgrade status + uint32_t timestamp = sl_si91x_host_get_timestamp(); + uint16_t default_nwp_fw_selected = 0; + while (sl_si91x_host_elapsed_time(timestamp) < 3000) { + status = sl_si91x_bus_read_memory(RSI_HOST_INTF_REG_OUT, 2, (uint8_t *)&read_value); + if (status != SL_STATUS_OK) + continue; + + if ((read_value & 0xF000) == (RSI_HOST_INTERACT_REG_VALID_FW & 0xF000)) { + if ((read_value & 0xFF) == VALID_FIRMWARE_NOT_PRESENT) { + if (default_nwp_fw_selected == 0) { + boot_command = RSI_HOST_INTERACT_REG_VALID_FW | SELECT_DEFAULT_NWP_FW_IMAGE_NUMBER; + status = sl_si91x_bus_write_memory(RSI_HOST_INTF_REG_IN, 2, (uint8_t *)&boot_command); + if (status != SL_STATUS_OK) { + return status; + } + + while (sl_si91x_host_elapsed_time(timestamp) < 2000) { + status = sl_si91x_bus_read_memory(RSI_HOST_INTF_REG_OUT, 2, (uint8_t *)&read_value); + if (status != SL_STATUS_OK) + continue; + if (read_value == (RSI_HOST_INTERACT_REG_VALID | SELECT_DEFAULT_NWP_FW_IMAGE_NUMBER)) { + break; + } + } + + boot_command = RSI_HOST_INTERACT_REG_VALID_FW | configuration; + status = sl_si91x_bus_write_memory(RSI_HOST_INTF_REG_IN, 2, (uint8_t *)&boot_command); + if (status != SL_STATUS_OK) { + return status; + } + default_nwp_fw_selected = 1; + continue; + } else { + return SL_STATUS_VALID_FIRMWARE_NOT_PRESENT; + } + } + if ((read_value & 0xFF) == RSI_INVALID_OPTION) { + return SL_STATUS_INVALID_OPTION; + } + if ((read_value & 0xFF) == RSI_CHECKSUM_SUCCESS) { + return status; + } + } + } + } + return SL_STATUS_FW_LOAD_OR_UPGRADE_TIMEOUT; +} + +sl_status_t sl_si91x_enable_radio(void) +{ + uint8_t data = 1; + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_RADIO, + SI91X_WLAN_CMD, + &data, + 1, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_disable_radio(void) +{ + uint8_t data = 0; + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_RADIO, + SI91X_WLAN_CMD, + &data, + 1, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_write_calibration_data(const si91x_calibration_data_t *data) +{ + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_CALIB_WRITE, + SI91X_WLAN_CMD, + data, + sizeof(si91x_calibration_data_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_wifi_set_certificate_index(uint8_t certificate_type, + uint8_t certificate_index, + const uint8_t *buffer, + uint32_t certificate_length) +{ + uint32_t rem_len = 0; + uint16_t chunk_size = 0; + uint16_t data_size = 0; + uint8_t chunks_remaining = 0; + uint32_t offset = 0; + sl_status_t status = SL_STATUS_OK; + sl_si91x_req_set_certificate_t chunk_ptr = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + // Get the certificate chunk size + chunk_size = (SI91X_MAX_CERT_SEND_SIZE - sizeof(sl_si91x_cert_info_t)); + + // Get certificate length + rem_len = certificate_length; + + do { + // Memset the PKT + memset(&chunk_ptr, 0, sizeof(sl_si91x_req_set_certificate_t)); + + // If certificate length is 0, erase certificate + if (rem_len == 0) { + // Mark Data Size + data_size = 0; + + // More chunks to send + chunks_remaining = 0; + } else if (rem_len >= chunk_size) { + // Mark Data Size + data_size = chunk_size; + + // More chunks to send + chunks_remaining = 1; + } else { + // Mark Data Size + data_size = (uint16_t)rem_len; + + // More chunks to send + chunks_remaining = 0; + } + + if ((data_size > 0) && (NULL != buffer)) { + // Copy the certificate chunk + memcpy(chunk_ptr.certificate, buffer + offset, data_size); + } + + // Move the offset by chunk size + offset += data_size; + + // Subtract the rem_len by the chunk size + rem_len -= data_size; + + //Set the total length of certificate + memcpy(&chunk_ptr.cert_info.total_len, &certificate_length, sizeof(chunk_ptr.cert_info.total_len)); + + // Set the certificate type + chunk_ptr.cert_info.certificate_type = certificate_type; + + // Set the certificate index + chunk_ptr.cert_info.certificate_inx = certificate_index; + + // More chunks to send + chunk_ptr.cert_info.more_chunks = chunks_remaining; + + // Set the length of the certificate chunk + chunk_ptr.cert_info.certificate_length = data_size; + + // Send the driver command + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_CERTIFICATE, + SI91X_WLAN_CMD, + &chunk_ptr, + (sizeof(sl_si91x_cert_info_t) + data_size), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + } while (rem_len > 0); + + // Return status + return status; +} + +sl_status_t sl_si91x_set_rtc_timer(const sl_si91x_module_rtc_time_t *timer) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if ((timer->tm_sec > 59) || (timer->tm_min > 59) || (timer->tm_hour > 23) + || ((timer->tm_mday < 1) || (timer->tm_mday > 31)) || (timer->tm_mon > 11) + || ((timer->tm_wday < 1) || (timer->tm_wday > 7))) { + + // Checking Invalid Parameters + return SL_STATUS_INVALID_PARAMETER; + } + + // Send set RTC timer request + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_SET_RTC_TIMER, + SI91X_COMMON_CMD, + timer, + sizeof(sl_si91x_module_rtc_time_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_get_rtc_timer(sl_si91x_module_rtc_time_t *response) +{ + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *buffer = NULL; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_WIFI_ARGS_CHECK_NULL_POINTER(response); + + // Send get RTC timer request + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_GET_RTC_TIMER, + SI91X_COMMON_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(30000), + NULL, + &buffer); + + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + // Extract the RTC timer data from the response + const sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + memcpy(response, packet->data, sizeof(sl_si91x_module_rtc_time_t)); + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_set_device_region(sl_si91x_operation_mode_t operation_mode, + sl_si91x_band_mode_t band, + sl_si91x_region_code_t region_code) +{ + sl_status_t status = SL_STATUS_OK; + + switch (operation_mode) { + case SL_SI91X_CLIENT_MODE: + case SL_SI91X_ENTERPRISE_CLIENT_MODE: + case SL_SI91X_TRANSMIT_TEST_MODE: + case SL_SI91X_TRANSCEIVER_MODE: { + // For client and transmit test modes, send a command to set the region code + sl_si91x_set_region_request_t request = { 0 }; + + request.set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER; + request.region_code = (uint8_t)region_code; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_REGION, + SI91X_WLAN_CMD, + &request, + sizeof(sl_si91x_set_region_request_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + break; + } + + case SL_SI91X_CONCURRENT_MODE: + case SL_SI91X_ACCESS_POINT_MODE: { + if (operation_mode == SL_SI91X_CONCURRENT_MODE) { + // For concurrent mode, send a command to set the region code + sl_si91x_set_region_request_t request = { 0 }; + + request.set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER; + request.region_code = (uint8_t)region_code; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_REGION, + SI91X_WLAN_CMD, + &request, + sizeof(sl_si91x_set_region_request_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + } + + // For AP and concurrent modes, configure region-specific settings + sl_si91x_set_region_ap_request_t request = { 0 }; + request.set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER; + + // Configure region-specific settings based on the region code and band + switch (region_code) { + // Configure settings for different regions and bands + case DEFAULT_REGION: + case US: { + if (band == SL_SI91X_WIFI_BAND_2_4GHZ) { + request = default_US_region_2_4GHZ_configurations; + } else { + request = default_US_region_5GHZ_configurations; + } + break; + } + case EU: { + if (band == SL_SI91X_WIFI_BAND_2_4GHZ) { + request = default_EU_region_2_4GHZ_configurations; + } else { + request = default_EU_region_5GHZ_configurations; + } + break; + } + case JP: { + if (band == SL_SI91X_WIFI_BAND_2_4GHZ) { + request = default_JP_region_2_4GHZ_configurations; + } else { + request = default_JP_region_5GHZ_configurations; + } + break; + } + case KR: { + if (band == SL_SI91X_WIFI_BAND_2_4GHZ) { + request = default_KR_region_2_4GHZ_configurations; + } else { + request = default_KR_region_5GHZ_configurations; + } + break; + } + case SG: { + if (band == SL_SI91X_WIFI_BAND_2_4GHZ) { + request = default_SG_region_2_4GHZ_configurations; + } else { + request = default_SG_region_5GHZ_configurations; + } + break; + } + case CN: { + if (band == SL_SI91X_WIFI_BAND_2_4GHZ) { + request = default_CN_region_2_4GHZ_configurations; + } else { + request = default_CN_region_5GHZ_configurations; + } + break; + } + default: + return SL_STATUS_NOT_SUPPORTED; + } + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_REGION_AP, + SI91X_WLAN_CMD, + &request, + sizeof(sl_si91x_set_region_ap_request_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + break; + } + + default: + break; + } + + return status; +} + +#ifdef SLI_SI91X_MCU_INTERFACE + +sl_status_t sl_si91x_command_to_write_common_flash(uint32_t write_address, + const uint8_t *write_data, + uint16_t write_data_length, + uint8_t flash_sector_erase_enable) +{ + // Check if write_data_length is non-zero + if (write_data_length == 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_status_t status = SL_STATUS_OK; + sl_si91x_request_ta2m4_t ta_to_m4_request = { 0 }; + uint32_t send_size = 0; + uint16_t remaining_length = write_data_length; + + // If flash_sector_erase_enable is 1, Send request to NWP in chunks of 4k + if (flash_sector_erase_enable == 1) { + while (remaining_length > 0) { + // Calculate the chunk size, capped at 4k + size_t chunkSize = (remaining_length < FLASH_SECTOR_SIZE) ? remaining_length : FLASH_SECTOR_SIZE; + + // Fill the request structure + memset(&ta_to_m4_request, 0, sizeof(sl_si91x_request_ta2m4_t)); + ta_to_m4_request.sub_cmd = SL_SI91X_WRITE_TO_COMMON_FLASH; + ta_to_m4_request.addr = write_address; + ta_to_m4_request.input_buffer_length = (uint16_t)chunkSize; + ta_to_m4_request.flash_sector_erase_enable = flash_sector_erase_enable; + + send_size = sizeof(sl_si91x_request_ta2m4_t); + + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_TA_M4_COMMANDS, + SI91X_COMMON_CMD, + &ta_to_m4_request, + send_size, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + // Adjust write_address for the next chunk + write_address += chunkSize; + + // Adjust remaining_length for the next chunk + remaining_length -= chunkSize; + } + } + + else { + // Check if write_data pointer is valid + SL_VERIFY_POINTER_OR_RETURN(write_data, SL_STATUS_INVALID_PARAMETER); + + // Write in chunks of MAX_CHUNK_SIZE for flash_sector_erase_enable != 1 + while (write_data_length > 0) { + size_t chunkSize = (write_data_length < MAX_CHUNK_SIZE) ? write_data_length : MAX_CHUNK_SIZE; + + // Fill the request structure + memset(&ta_to_m4_request, 0, sizeof(sl_si91x_request_ta2m4_t)); + ta_to_m4_request.sub_cmd = SL_SI91X_WRITE_TO_COMMON_FLASH; + ta_to_m4_request.addr = write_address; + ta_to_m4_request.input_buffer_length = (uint16_t)chunkSize; + ta_to_m4_request.flash_sector_erase_enable = flash_sector_erase_enable; + + // Copy write_data into the request structure + memcpy(&ta_to_m4_request.input_data, write_data, chunkSize); + + // Calculate the send size and send the command to write to common flash + send_size = sizeof(sl_si91x_request_ta2m4_t) - MAX_CHUNK_SIZE + chunkSize; + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_TA_M4_COMMANDS, + SI91X_COMMON_CMD, + &ta_to_m4_request, + send_size, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + // Adjust pointers and counters + write_address += chunkSize; + write_data += chunkSize; + write_data_length -= chunkSize; + } + } + return status; +} + +sl_status_t sl_si91x_command_to_read_common_flash(uint32_t read_address, size_t length, uint8_t *output_buffer) +{ + // Check if output_buffer pointer is valid + SL_VERIFY_POINTER_OR_RETURN(output_buffer, SL_STATUS_INVALID_PARAMETER); + + // Check if length is non-zero + if (length == 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *buffer = NULL; + const sl_si91x_packet_t *packet = NULL; + + while (length > 0) { + size_t chunkSize = (length < MAX_CHUNK_SIZE) ? length : MAX_CHUNK_SIZE; + + sl_si91x_read_flash_request_t m4_to_ta_read_request = { 0 }; + memset(&m4_to_ta_read_request, 0, sizeof(sl_si91x_read_flash_request_t)); + m4_to_ta_read_request.sub_cmd = SL_SI91X_READ_FROM_COMMON_FLASH; + m4_to_ta_read_request.nwp_address = read_address; + m4_to_ta_read_request.output_buffer_length = (uint16_t)chunkSize; + + uint32_t send_size = sizeof(sl_si91x_read_flash_request_t); + + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_TA_M4_COMMANDS, + SI91X_COMMON_CMD, + &m4_to_ta_read_request, + send_size, + SL_SI91X_WAIT_FOR_RESPONSE(32000), + NULL, + &buffer); + if (status != SL_STATUS_OK) { + if (buffer != NULL) + sl_si91x_host_free_buffer(buffer); + return status; + } + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + memcpy(output_buffer, packet->data, packet->length); + sl_si91x_host_free_buffer(buffer); + + // Adjust pointers and counters + read_address += chunkSize; + output_buffer += chunkSize; + length -= chunkSize; + } + + return status; +} + +sl_status_t sl_si91x_m4_ta_secure_handshake(uint8_t sub_cmd_type, + uint8_t input_len, + const uint8_t *input_data, + uint8_t output_len, + const uint8_t *output_data) +{ + UNUSED_PARAMETER(output_len); + UNUSED_PARAMETER(output_data); + sl_si91x_ta_m4_handshake_parameters_t *handshake_request = NULL; + sl_status_t status = SL_STATUS_OK; + + SL_VERIFY_POINTER_OR_RETURN(input_data, SL_STATUS_INVALID_PARAMETER); + + handshake_request = malloc(sizeof(sl_si91x_ta_m4_handshake_parameters_t) + input_len); + SL_VERIFY_POINTER_OR_RETURN(handshake_request, SL_STATUS_ALLOCATION_FAILED); + memset(handshake_request, 0, sizeof(sl_si91x_ta_m4_handshake_parameters_t) + input_len); + handshake_request->sub_cmd = sub_cmd_type; + handshake_request->input_data_size = input_len; + memcpy(handshake_request->input_data, input_data, input_len); + + // Send the secure handshake command to the M4 core + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_TA_M4_COMMANDS, + SI91X_COMMON_CMD, + handshake_request, + sizeof(sl_si91x_ta_m4_handshake_parameters_t) + input_len, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + free(handshake_request); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +// Perform a soft reset +static sl_status_t sl_si91x_soft_reset(void) +{ + sl_status_t status; + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_SOFT_RESET, + SI91X_COMMON_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(30000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} +#endif + +sl_status_t sl_si91x_assert() +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + status = + sl_si91x_driver_send_command(RSI_COMMON_REQ_ASSERT, SI91X_WLAN_CMD, NULL, 0, SL_SI91X_WAIT_FOR(30000), NULL, NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_get_ram_log(uint32_t address, uint32_t length) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + sl_status_t status = SL_STATUS_OK; + sl_si91x_ram_dump_t ram = { .address = address, .length = length }; + + // Check for invalid length parameter + if (length == 0) { + return SL_STATUS_INVALID_PARAMETER; + } + // Send RAM log request + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_GET_RAM_DUMP, + SI91X_COMMON_CMD, + &ram, + sizeof(sl_si91x_ram_dump_t), + SL_SI91X_WAIT_FOR(31000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_transmit_test_start(const sl_si91x_request_tx_test_info_t *tx_test_info) +{ + sl_status_t status = SL_STATUS_OK; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TX_TEST_MODE, + SI91X_WLAN_CMD, + tx_test_info, + sizeof(sl_si91x_request_tx_test_info_t), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_transmit_test_stop(void) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_request_tx_test_info_t tx_test_info = { 0 }; + tx_test_info.enable = 0; + // Send the transmit test stop command + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TX_TEST_MODE, + SI91X_WLAN_CMD, + &tx_test_info, + sizeof(sl_si91x_request_tx_test_info_t), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_si91x_operation_mode_t get_opermode(void) +{ + return initialized_opermode; +} + +sl_status_t sl_si91x_calibration_write(sl_si91x_calibration_write_t calib_write) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_CALIB_WRITE, + SI91X_WLAN_CMD, + &calib_write, + sizeof(sl_si91x_calibration_write_t), + SL_SI91X_WAIT_FOR(30000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_calibration_read(sl_si91x_calibration_read_t target, sl_si91x_calibration_read_t *calibration_read) +{ + sl_wifi_buffer_t *buffer = NULL; + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + SL_VERIFY_POINTER_OR_RETURN(calibration_read, SL_STATUS_NULL_POINTER); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_CALIB_READ, + SI91X_WLAN_CMD, + &target, + sizeof(sl_si91x_calibration_read_t), + SL_SI91X_WAIT_FOR_RESPONSE(30100), + NULL, + &buffer); + + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + return status; + } + + const sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + memcpy(calibration_read, packet->data, sizeof(sl_si91x_calibration_read_t)); + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_si91x_frequency_offset(const sl_si91x_freq_offset_t *frequency_calibration) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(frequency_calibration, SL_STATUS_NULL_POINTER); + + // Send the frequency offset calibration command to the SI91x WLAN module + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_FREQ_OFFSET, + SI91X_WLAN_CMD, + frequency_calibration, + sizeof(sl_si91x_freq_offset_t), + SL_SI91X_WAIT_FOR_RESPONSE(35000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_evm_offset(const sl_si91x_evm_offset_t *evm_offset) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(evm_offset, SL_STATUS_NULL_POINTER); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_EVM_OFFSET, + SI91X_WLAN_CMD, + evm_offset, + sizeof(sl_si91x_evm_offset_t), + SL_SI91X_WAIT_FOR_RESPONSE(35000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_evm_write(const sl_si91x_evm_write_t *evm_write) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(evm_write, SL_STATUS_NULL_POINTER); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_EVM_WRITE, + SI91X_WLAN_CMD, + evm_write, + sizeof(sl_si91x_evm_write_t), + SL_SI91X_WAIT_FOR_RESPONSE(35000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_dpd_calibration(const sl_si91x_get_dpd_calib_data_t *dpd_calib_data) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(dpd_calib_data, SL_STATUS_NULL_POINTER); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_GET_DPD_DATA, + SI91X_WLAN_CMD, + dpd_calib_data, + sizeof(sl_si91x_get_dpd_calib_data_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_si91x_efuse_read(const sl_si91x_efuse_read_t *efuse_read, uint8_t *efuse_read_buf) +{ + sl_wifi_buffer_t *buffer = NULL; + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + SL_VERIFY_POINTER_OR_RETURN(efuse_read, SL_STATUS_NULL_POINTER); + SL_VERIFY_POINTER_OR_RETURN(efuse_read_buf, SL_STATUS_NULL_POINTER); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_EFUSE_READ, + SI91X_WLAN_CMD, + efuse_read, + sizeof(sl_si91x_efuse_read_t), + SL_SI91X_WAIT_FOR_RESPONSE(30100), + NULL, + &buffer); + + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + return status; + } + + const sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + memcpy(efuse_read_buf, packet->data, efuse_read->efuse_read_data_len); + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_si91x_set_join_configuration(sl_wifi_interface_t interface, uint8_t join_feature_bitmap) +{ + // Determine whether the configuration is for the client or AP interface + if (interface & SL_WIFI_CLIENT_INTERFACE) { + client_join_feature_bitmap = join_feature_bitmap; + } else if (interface & SL_WIFI_AP_INTERFACE) { + ap_join_feature_bitmap = join_feature_bitmap; + } else { + return SL_STATUS_FAIL; + } + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_get_join_configuration(sl_wifi_interface_t interface, uint8_t *join_feature_bitmap) +{ + SL_WIFI_ARGS_CHECK_NULL_POINTER(join_feature_bitmap); + + // Determine whether to retrieve the configuration for the client or AP interface + if (interface & SL_WIFI_CLIENT_INTERFACE) { + *join_feature_bitmap = client_join_feature_bitmap; + } else if (interface & SL_WIFI_AP_INTERFACE) { + *join_feature_bitmap = ap_join_feature_bitmap; + } else { + return SL_STATUS_WIFI_UNKNOWN_INTERFACE; + } + + return SL_STATUS_OK; +} + +void sl_si91x_set_listen_interval(uint32_t listen_interval) +{ + client_listen_interval = listen_interval; + return; +} + +uint32_t sl_si91x_get_listen_interval(void) +{ + return client_listen_interval; +} + +void sl_si91x_set_timeout(const sl_si91x_timeout_t *timeout_config) +{ + memcpy(&timeout_glbl, timeout_config, sizeof(sl_si91x_timeout_t)); + return; +} + +sl_status_t sl_si91x_configure_timeout(sl_si91x_timeout_type_t timeout_type, uint16_t timeout_value) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_request_timeout_t timeout_request = { 0 }; + + if (timeout_type > SL_SI91X_CHANNEL_PASSIVE_SCAN_TIMEOUT) { + return SL_STATUS_INVALID_PARAMETER; + } + + timeout_request.timeout_bitmap = BIT(timeout_type); + timeout_request.timeout_value = timeout_value; + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TIMEOUT, + SI91X_WLAN_CMD, + &timeout_request, + sizeof(sl_si91x_request_timeout_t), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + return status; +} + +uint16_t get_seq_ctrl(uint8_t is_qos) +{ + static uint16_t qos_pkt_count = 0; + static uint16_t non_qos_pkt_count = 0; + + if (qos_pkt_count > 4095) + qos_pkt_count = 0; + + if (non_qos_pkt_count > 4095) + non_qos_pkt_count = 0; + + return is_qos ? qos_pkt_count++ : non_qos_pkt_count++; +} + +int32_t encapsulate_tx_data_packet(sl_wifi_transceiver_tx_data_control_t *control, + uint8_t *pkt_data, + uint32_t mac_hdr_len) +{ + uint16_t seq_ctrl = 0; + uint16_t *frame_ctrl; + uint32_t qos_ctrl_off = MAC80211_HDR_MIN_LEN; + + SL_VERIFY_POINTER_OR_RETURN(control, SL_STATUS_NULL_POINTER); + + if (IS_MAC_ZERO(control->addr1)) { + return SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS; + } + + /* Auto-rate is unsupported if Peer DS feature in MAC layer is disabled */ + if ((!IS_PEER_DS_SUPPORT_ENABLED(feature_bit_map)) && !IS_FIXED_DATA_RATE(control->ctrl_flags)) { + return SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE; + } + + /* Ignore QoS flag for bcast/mcast frames */ + if (IS_BCAST_MCAST_MAC(control->addr1[0])) { + control->ctrl_flags &= ~TX_DATA_CTRL_FLAG_QOS_BIT; + } + + if ((IS_QOS_PKT(control->ctrl_flags) && !IS_BCAST_MCAST_MAC(control->addr1[0])) && (control->priority > 3)) { + return SL_STATUS_TRANSCEIVER_INVALID_QOS_PRIORITY; + } + + if (IS_4ADDR(control->ctrl_flags)) { + qos_ctrl_off += MAC80211_HDR_ADDR4_LEN; + } + + memset(pkt_data, 0, mac_hdr_len); + /* Add frame control (2 bytes) */ + frame_ctrl = (uint16_t *)&pkt_data[0]; + *frame_ctrl |= FC_TYPE_DATA; + + if (IS_4ADDR(control->ctrl_flags)) { + *frame_ctrl |= FC_TO_DS; + *frame_ctrl |= FC_FROM_DS; + } else { + *frame_ctrl |= IS_TODS(control->ctrl_flags) ? FC_TO_DS : 0; + *frame_ctrl |= IS_FROMDS(control->ctrl_flags) ? FC_FROM_DS : 0; + } + + /* Add Addr1, Addr2, Addr3 (18 bytes) */ + memcpy(&pkt_data[4], control->addr1, 6); + memcpy(&pkt_data[10], control->addr2, 6); + memcpy(&pkt_data[16], control->addr3, 6); + + if (!IS_PEER_DS_SUPPORT_ENABLED(feature_bit_map)) { + seq_ctrl = (uint16_t)(get_seq_ctrl(IS_QOS_PKT(control->ctrl_flags)) << 4); + memcpy(&pkt_data[22], &seq_ctrl, 2); + } + + /* Add Addr4 optionally based on ctrl_flag (6 bytes) */ + if (IS_4ADDR(control->ctrl_flags)) { + memcpy(&pkt_data[24], control->addr4, 6); /* sa */ + } + /* Add QoS control optionally based on ctrl_flag (2 bytes) */ + if (IS_QOS_PKT(control->ctrl_flags) && !IS_BCAST_MCAST_MAC(control->addr1[0])) { + *frame_ctrl |= FC_SUBTYPE_QOS_DATA; + pkt_data[qos_ctrl_off] = WME_AC_TO_TID(control->priority); + } + + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_driver_send_transceiver_data(sl_wifi_transceiver_tx_data_control_t *control, + const uint8_t *payload, + uint16_t payload_len, + uint32_t wait_time) +{ + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sl_status_t status = SL_STATUS_OK; + uint8_t *pkt_offset; + uint8_t ext_desc_size; + uint8_t *host_desc; + uint32_t mac_hdr_len = MAC80211_HDR_MIN_LEN; + + if (IS_QOS_PKT(control->ctrl_flags) && !IS_BCAST_MCAST_MAC(control->addr1[0])) { + mac_hdr_len += MAC80211_HDR_QOS_CTRL_LEN; + } + + if (IS_4ADDR(control->ctrl_flags)) { + mac_hdr_len += MAC80211_HDR_ADDR4_LEN; + } + + ext_desc_size = TRANSCEIVER_TX_DATA_EXT_DESC_SIZE; + + // Allocate a data buffer with space for the data and metadata + status = sl_si91x_allocate_data_buffer(&buffer, + (void **)&packet, + sizeof(sl_si91x_packet_t) + ext_desc_size + mac_hdr_len + payload_len, + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + VERIFY_STATUS_AND_RETURN(status); + + // If the packet is not allocated successfully, return an allocation failed error + if (packet == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + + pkt_offset = packet->data + ext_desc_size; + status = encapsulate_tx_data_packet(control, pkt_offset, mac_hdr_len); + if (status != SL_STATUS_OK) { + sl_si91x_host_free_buffer(buffer); + return status; + } + + memcpy(pkt_offset + mac_hdr_len, payload, payload_len); + +#ifdef TX_RX_FRAME_DUMP_BYTE_COUNT + print_80211_packet(pkt_offset, mac_hdr_len + payload_len, TX_RX_FRAME_DUMP_BYTE_COUNT); +#endif + + // Clear the packet descriptor and copy the command data if available + memset(packet->desc, 0, sizeof(packet->desc)); + + // Fill length in first 2 host_desc bytes + packet->length = (ext_desc_size + mac_hdr_len + payload_len) & 0xFFF; + + // Fill packet type + host_desc = packet->desc; + + host_desc[2] = 0x01; //! Frame Type + if (IS_CFM_TO_HOST_SET(control->ctrl_flags)) { + host_desc[3] |= CONFIRM_REQUIRED_TO_HOST; //! This bit is used to set CONFIRM_REQUIRED_TO_HOST in firmware. + } + host_desc[4] = ext_desc_size; //! xtend_desc size + host_desc[5] = (uint8_t)((mac_hdr_len + 3) & ~3); //! Mac_header length + + if (IS_BCAST_MCAST_MAC(control->addr1[0])) { + host_desc[7] |= BCAST_INDICATION; //! Bcast_indication + //! If auto-rate is enabled for bcast/mcast pkts, use 1 Mbps + if (!IS_FIXED_DATA_RATE(control->ctrl_flags)) { + host_desc[6] |= MAC_INFO_ENABLE; //! Fixed Rate + host_desc[8] = SL_WIFI_DATA_RATE_1; + } + } + + if (IS_FIXED_DATA_RATE(control->ctrl_flags)) { + host_desc[6] |= MAC_INFO_ENABLE; //! Fixed Rate + host_desc[8] = (uint8_t)control->rate; + } + + if (IS_QOS_PKT(control->ctrl_flags) && !IS_BCAST_MCAST_MAC(control->addr1[0])) { + host_desc[13] |= QOS_ENABLE; // QOS ENABLE + } + + host_desc[14] = + (uint8_t)(((WME_AC_TO_TID(control->priority) & 0xf) << 4) | (WME_AC_TO_QNUM(control->priority) & 0xf)); + + //! Initialize extended desc + memcpy(&host_desc[16], &control->token, TRANSCEIVER_TX_DATA_EXT_DESC_SIZE); + + // Send command packet to the SI91x socket data queue and await a response + return sl_si91x_driver_send_data_packet(buffer, wait_time); +} + +sl_status_t sl_si91x_bl_upgrade_firmware(uint8_t *firmware_image, uint32_t fw_image_size, uint8_t flags) +{ + static uint16_t boot_cmd = 0; + uint16_t read_value = 0; + uint32_t offset = 0; + uint32_t retval = 0; + uint32_t boot_insn = 0; + uint32_t poll_resp = 0; + + //! If it is a start of file set the boot cmd to pong valid + if (flags & SL_SI91X_FW_START_OF_FILE) { + boot_cmd = RSI_HOST_INTERACT_REG_VALID | RSI_PONG_VALID; + } + + //! check for invalid packet + if ((fw_image_size % SL_SI91X_MIN_CHUNK_SIZE != 0) && (!(flags & SL_SI91X_FW_END_OF_FILE))) { + return SL_STATUS_FAIL; + } + + //! loop to execute multiple of 4K chunks + while (offset < fw_image_size) { + switch (boot_cmd) { + case (RSI_HOST_INTERACT_REG_VALID | RSI_PING_VALID): + boot_insn = RSI_PONG_WRITE; + poll_resp = RSI_PING_AVAIL; + boot_cmd = RSI_HOST_INTERACT_REG_VALID | RSI_PONG_VALID; + break; + + case (RSI_HOST_INTERACT_REG_VALID | RSI_PONG_VALID): + boot_insn = RSI_PING_WRITE; + poll_resp = RSI_PONG_AVAIL; + boot_cmd = RSI_HOST_INTERACT_REG_VALID | RSI_PING_VALID; + break; + + default: + return SL_STATUS_FAIL; + } + + retval = sl_si91x_boot_instruction((uint8_t)boot_insn, (uint16_t *)(firmware_image + offset)); + VERIFY_STATUS_AND_RETURN(retval); + + while (1) { + retval = sl_si91x_boot_instruction(RSI_REG_READ, &read_value); + VERIFY_STATUS_AND_RETURN(retval); + + if (read_value == (RSI_HOST_INTERACT_REG_VALID | poll_resp)) { + break; + } + } + offset += SL_SI91X_MIN_CHUNK_SIZE; + } + + //! For last chunk set boot cmd as End of file reached + if (flags & SL_SI91X_FW_END_OF_FILE) { + boot_cmd = RSI_HOST_INTERACT_REG_VALID | RSI_EOF_REACHED; + + retval = sl_si91x_boot_instruction(RSI_REG_WRITE, &boot_cmd); + VERIFY_STATUS_AND_RETURN(retval); + + //! check for successful firmware upgrade + do { + retval = sl_si91x_boot_instruction(RSI_REG_READ, &read_value); + VERIFY_STATUS_AND_RETURN(retval); + + } while (read_value != (RSI_HOST_INTERACT_REG_VALID | RSI_FWUP_SUCCESSFUL)); + } + return retval; +} + +sl_status_t sl_si91x_set_fast_fw_up(void) +{ + uint32_t read_data = 0; + sl_status_t retval = 0; + retval = sl_si91x_bus_read_memory(SL_SI91X_SAFE_UPGRADE_ADDR, 4, (uint8_t *)&read_data); + VERIFY_STATUS_AND_RETURN(retval); + + //disabling safe upgradation bit + if (read_data & SL_SI91X_SAFE_UPGRADE) { + read_data &= ~(SL_SI91X_SAFE_UPGRADE); + retval = sl_si91x_bus_write_memory(SL_SI91X_SAFE_UPGRADE_ADDR, 4, (uint8_t *)&read_data); + VERIFY_STATUS_AND_RETURN(retval); + } + return retval; +} + +void sli_si91x_append_to_buffer_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t *buffer) +{ + CORE_irqState_t state = CORE_EnterAtomic(); + if (queue->tail == NULL) { + assert(queue->head == NULL); // Both should be NULL at the same time + queue->head = buffer; + queue->tail = buffer; + } else { + queue->tail->node.node = &buffer->node; + queue->tail = buffer; + } + CORE_ExitAtomic(state); +} + +sl_status_t sli_si91x_pop_from_buffer_queue(sl_si91x_buffer_queue_t *queue, sl_wifi_buffer_t **buffer) +{ + sl_status_t status = SL_STATUS_EMPTY; + CORE_irqState_t state = CORE_EnterAtomic(); + if (queue->head == NULL) { + assert(queue->tail == NULL); // Both should be NULL at the same time + *buffer = NULL; + status = SL_STATUS_EMPTY; + } else { + *buffer = queue->head; + status = SL_STATUS_OK; + if (queue->head == queue->tail) { + queue->head = NULL; + queue->tail = NULL; + } else { + queue->head = (sl_wifi_buffer_t *)queue->head->node.node; + } + } + CORE_ExitAtomic(state); + return status; +} + +sl_status_t sl_si91x_get_firmware_version(sl_si91x_firmware_version_t *version) +{ + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *buffer = NULL; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + SL_WIFI_ARGS_CHECK_NULL_POINTER(version); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_FULL_FW_VERSION, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(1000), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + if (packet == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (packet->length > 0) { + const sl_wifi_firmware_version_t *response = (const sl_wifi_firmware_version_t *)packet->data; + + if (response == NULL) { + return SL_STATUS_NULL_POINTER; + } + + version->chip_id = response->chip_id; + version->rom_id = response->rom_id; + version->major = response->major; + version->minor = response->minor; + version->security_version = response->security_version; + version->patch_num = response->patch_num; + version->customer_id = response->customer_id; + version->build_num = (packet->data[7] | packet->data[8]); + } + + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_si91x_get_firmware_size(void *buffer, uint32_t *fw_image_size) +{ + SL_WIFI_ARGS_CHECK_NULL_POINTER(buffer); + + const sl_si91x_firmware_header_t *fw = (const sl_si91x_firmware_header_t *)buffer; + + *fw_image_size = (fw->image_size + sizeof(sl_si91x_firmware_header_t)); + + return SL_STATUS_OK; +} + +sl_status_t sl_si91x_set_nwp_config_request(sl_si91x_nwp_configuration_t nwp_config) +{ + sl_status_t status = SL_STATUS_OK; + + if ((nwp_config.code & SL_SI91X_XO_CTUNE_FROM_HOST) || (nwp_config.code & SL_SI91X_ENABLE_NWP_WDT_FROM_HOST) + || (nwp_config.code & SL_SI91X_DISABLE_NWP_WDT_FROM_HOST)) { + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_SET_CONFIG, + SI91X_COMMON_CMD, + &nwp_config, + sizeof(sl_si91x_nwp_configuration_t), + SL_SI91X_WAIT_FOR_RESPONSE(3000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + } else + return SL_STATUS_NOT_SUPPORTED; + + return status; +} + +sl_status_t sl_si91x_get_nwp_config(const sl_si91x_nwp_get_configuration_t *nwp_config, uint8_t *response) +{ + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + + if (nwp_config->sub_command_type == GET_OPN_BOARD_CONFIG) { + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_GET_CONFIG, + SI91X_COMMON_CMD, + nwp_config, + sizeof(sl_si91x_nwp_get_configuration_t), + SL_SI91X_WAIT_FOR_RESPONSE(3000), + NULL, + &buffer); + if (status != SL_STATUS_OK) { + if (buffer != NULL) + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + memcpy(response, packet->data, packet->length); + sl_si91x_host_free_buffer(buffer); + } else { + return SL_STATUS_NOT_SUPPORTED; + } + return status; +} + +sl_status_t sl_si91x_debug_log(sl_si91x_assertion_t *assertion) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_debug_log_t debug_config = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if ((debug_config.assertion_type > SL_SI91X_ASSERTION_TYPE_ALL) + || (debug_config.assertion_level > SL_SI91X_ASSERTION_LEVEL_MAX)) { + return SL_STATUS_INVALID_PARAMETER; + } + + debug_config.assertion_type = assertion->assert_type; + debug_config.assertion_level = assertion->assert_level; + + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_DEBUG_LOG, + SI91X_COMMON_CMD, + &debug_config, + sizeof(sl_si91x_debug_log_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + return status; +} diff --git a/wiseconnect/components/device/silabs/si91x/wireless/threading/sli_si91x_multithreaded.c b/wiseconnect/components/device/silabs/si91x/wireless/threading/sli_si91x_multithreaded.c new file mode 100644 index 000000000..212f13f00 --- /dev/null +++ b/wiseconnect/components/device/silabs/si91x/wireless/threading/sli_si91x_multithreaded.c @@ -0,0 +1,1680 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_si91x_host_interface.h" +#include "sl_si91x_types.h" +#include "sl_si91x_protocol_types.h" +#include "sl_si91x_driver.h" +#include "sl_wifi_constants.h" +#include "sl_wifi_types.h" +#include "sl_rsi_utility.h" +#include "cmsis_os2.h" +#include "cmsis_compiler.h" +#include "sl_si91x_core_utilities.h" +#include +#ifdef SLI_SI91X_MCU_INTERFACE +#include "rsi_m4.h" +#endif +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +#include "sl_si91x_socket_types.h" +#include "sl_si91x_socket_utility.h" +#include "sl_net_si91x_integration_handler.h" +#else +// This macro defines a handler for dispatching network events. +// It is used to handle events related to the SI91x module +#define SL_NET_EVENT_DISPATCH_HANDLER(data, packet) \ + { \ + UNUSED_PARAMETER(data); \ + UNUSED_PARAMETER(packet); \ + } +#endif + +#ifdef SLI_SI91X_ENABLE_BLE +#include "rsi_bt_common.h" +#endif + +#define BUS_THREAD_EVENTS \ + (SL_SI91X_ALL_TX_PENDING_COMMAND_EVENTS | SL_SI91X_SOCKET_DATA_TX_PENDING_EVENT | SL_SI91X_NCP_HOST_BUS_RX_EVENT \ + | SL_SI91X_SOCKET_COMMAND_TX_PENDING_EVENT | SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT \ + | SL_SI91X_TA_BUFFER_FULL_CLEAR_EVENT | SL_SI91X_TERMINATE_BUS_THREAD_EVENT) + +/** + * All flags used with async events + */ +#define SL_SI91X_NOTIFICATION_FLAG(x) (1 << (x)) + +// Indicates asynchronous RX response received for WLAN command type +#define NCP_HOST_WLAN_NOTIFICATION_EVENT SL_SI91X_NOTIFICATION_FLAG(SI91X_WLAN_CMD) + +// Indicates asynchronous RX response received for NETWORK command type +#define NCP_HOST_NETWORK_NOTIFICATION_EVENT SL_SI91X_NOTIFICATION_FLAG(SI91X_NETWORK_CMD) + +// Indicates asynchronous RX response received for SOCKET command type +#define NCP_HOST_SOCKET_NOTIFICATION_EVENT SL_SI91X_NOTIFICATION_FLAG(SI91X_SOCKET_CMD) + +// Indicates asynchronous RX response received for SOCKET data type +#define NCP_HOST_SOCKET_DATA_NOTIFICATION_EVENT SL_SI91X_NOTIFICATION_FLAG(SI91X_CMD_MAX) + +/****************************************************** + * Variable Definitions + ******************************************************/ + +extern osEventFlagsId_t si91x_async_events; +extern osEventFlagsId_t si91x_events; + +volatile uint32_t tx_command_queues_status = 0; +volatile uint32_t tx_socket_command_queues_status = 0; +volatile uint32_t tx_socket_data_queues_status = 0; +volatile uint32_t tx_generic_socket_data_queues_status = 0; + +volatile uint32_t tx_command_queues_command_in_flight_status = 0; +volatile uint8_t tx_socket_command_command_in_flight_queues_status = 0; + +#if SLI_SI91X_MCU_INTERFACE +extern sl_si91x_buffer_queue_t sli_ahb_bus_rx_queue; +#endif + +#if SL_NCP_UART_INTERFACE +extern sl_si91x_buffer_queue_t sli_uart_bus_rx_queue; +#endif + +/****************************************************** + * Function Declarations + ******************************************************/ + +void si91x_event_handler_thread(const void *args); + +static void set_async_event(uint32_t event_mask); + +// Declaration of a global flag to indicate if background mode is enabled +extern bool bg_enabled; + +// Declaration of the SI91x event handler function +extern sl_wifi_event_handler_t si91x_event_handler; + +extern sli_si91x_command_queue_t cmd_queues[SI91X_CMD_MAX]; +extern sl_si91x_buffer_queue_t sli_tx_data_queue; + +void si91x_event_handler_thread(const void *args); + +extern sl_status_t sl_create_generic_rx_packet_from_params(sli_si91x_queue_packet_t **queue_packet, + sl_wifi_buffer_t **packet_buffer, + uint16_t packet_id, + uint8_t flags, + void *sdk_context, + uint16_t frame_status); + +void sli_submit_rx_buffer(void); +void si91x_bus_thread(const void *args); +void sli_handle_dhcp_and_rejoin_failure(void *sdk_context, sl_wifi_buffer_t *temp_buffer, uint16_t frame_status); +void si91x_event_handler_thread(const void *args); +#ifdef SLI_SI91X_MCU_INTERFACE +// External declaration of a function to configure M4 DMA descriptors on reset +extern void sli_si91x_config_m4_dma_desc_on_reset(void); +void unmask_ta_interrupt(uint32_t interrupt_no); +#endif + +static sl_status_t bus_write_data_frame(sl_si91x_buffer_queue_t *queue); + +static sl_status_t bus_write_frame(sli_si91x_command_queue_t *queue, + sl_si91x_command_type_t command_type, + sl_wifi_buffer_type_t buffer_type, + bool *global_queue_block); + +sl_status_t si91x_req_wakeup(void); +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +static sli_si91x_socket_t *get_socket_from_packet(sl_si91x_packet_t *socket_packet); +#endif +bool sli_si91x_is_bus_ready(bool global_queue_block); + +/****************************************************** + * Function Definitions + ******************************************************/ + +sl_status_t sl_create_generic_rx_packet_from_params(sli_si91x_queue_packet_t **queue_packet, + sl_wifi_buffer_t **packet_buffer, + uint16_t packet_id, + uint8_t flags, + void *sdk_context, + uint16_t frame_status) +{ + sli_si91x_queue_packet_t *packet = NULL; + sl_wifi_buffer_t *buffer = NULL; + sl_status_t status = SL_STATUS_OK; + uint16_t temp = 0; + + status = sl_si91x_host_allocate_buffer(&buffer, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sli_si91x_queue_packet_t), + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + + *packet_buffer = buffer; + + packet = sl_si91x_host_get_buffer_data(buffer, 0, &temp); + if (packet == NULL) { + return SL_STATUS_NOT_AVAILABLE; + } + + // Fill dummy packet with details passed + buffer->id = packet_id; + packet->sdk_context = sdk_context; + packet->flags = flags; + packet->frame_status = frame_status; + packet->firmware_queue_id = RSI_WLAN_MGMT_Q; + + *queue_packet = packet; + return SL_STATUS_OK; +} + +void sli_handle_dhcp_and_rejoin_failure(void *sdk_context, sl_wifi_buffer_t *response_buffer, uint16_t frame_status) +{ + sl_status_t status; + sl_wifi_buffer_t *temp_buffer = NULL; + sli_si91x_queue_packet_t *node; + + // Retrieve the packet data from the response buffer + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(response_buffer, 0, NULL); + + // Check for remote Wi-Fi client disconnection in concurrent mode + if (packet->command == RSI_WLAN_RSP_CLIENT_DISCONNECTED && (get_opermode() == SL_SI91X_CONCURRENT_MODE)) { + packet->desc[7] = SL_SI91X_WIFI_AP_VAP_ID; // Set the AP VAP ID + } + + // Create a generic RX packet from the parameters + status = sl_create_generic_rx_packet_from_params(&node, &temp_buffer, 0, 0, NULL, frame_status); + if (status != SL_STATUS_OK) { + return; // Exit if packet creation fails + } + + sl_wifi_buffer_t *dummy_packet_buffer = NULL; + + // Allocate buffer for the dummy packet + status = sl_si91x_host_allocate_buffer(&dummy_packet_buffer, + SL_WIFI_RX_FRAME_BUFFER, + (sizeof(packet->desc) + packet->length), + SL_WIFI_ALLOCATE_COMMAND_BUFFER_WAIT_TIME); + if (status != SL_STATUS_OK) { + sl_si91x_host_free_buffer(temp_buffer); // Free temp buffer on failure + return; // Exit if buffer allocation fails + } + + // Get the dummy packet data from the allocated buffer + sl_si91x_packet_t *dummy_packet = sl_si91x_host_get_buffer_data(dummy_packet_buffer, 0, NULL); + node->host_packet = dummy_packet_buffer; // Link dummy packet to the node + node->sdk_context = sdk_context; + + // Copy the original packet data to the dummy packet + memcpy(dummy_packet, packet, (sizeof(packet->desc) + packet->length)); + + // Enqueue the node packet and trigger the async event + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].event_queue, temp_buffer); + set_async_event(NCP_HOST_NETWORK_NOTIFICATION_EVENT); +} + +// Weak implementation of the function to process data frames received from the SI91x module +__WEAK sl_status_t sl_si91x_host_process_data_frame(sl_wifi_interface_t interface, sl_wifi_buffer_t *buffer) +{ + UNUSED_PARAMETER(interface); + UNUSED_PARAMETER(buffer); + return SL_STATUS_OK; +} + +/// Thread which handles the notification events. +void si91x_event_handler_thread(const void *args) +{ + UNUSED_PARAMETER(args); + sl_wifi_event_t wifi_event = 0; + uint32_t event = 0; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + sli_si91x_queue_packet_t *data = NULL; + uint16_t frame_status = 0; + const uint32_t event_mask = (NCP_HOST_WLAN_NOTIFICATION_EVENT | NCP_HOST_NETWORK_NOTIFICATION_EVENT + | NCP_HOST_SOCKET_NOTIFICATION_EVENT | NCP_HOST_SOCKET_DATA_NOTIFICATION_EVENT); + + while (1) { + event = osEventFlagsWait(si91x_async_events, event_mask, osFlagsWaitAny, osWaitForever); + // event = si91x_host_wait_for_async_event(event_mask, osWaitForever); + + if ((event & NCP_HOST_WLAN_NOTIFICATION_EVENT) != 0) { + // Process WLAN notification events + while (sl_si91x_host_queue_status(&cmd_queues[SI91X_WLAN_CMD].event_queue) != 0) { + if (sli_si91x_remove_from_queue(&cmd_queues[SI91X_WLAN_CMD].event_queue, &buffer) == SL_STATUS_OK) { + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + frame_status = get_si91x_frame_status(packet); + + // Call event handler + if (si91x_event_handler != NULL) { + wifi_event = convert_si91x_event_to_sl_wifi_event(packet->command, frame_status); + + if (RSI_WLAN_RSP_SCAN_RESULTS == packet->command) { + sli_handle_wifi_beacon(packet); + } + + if (wifi_event != SL_WIFI_INVALID_EVENT) { + si91x_event_handler(wifi_event, buffer); + } + } else { + // TODO: error handling + } + sl_si91x_host_free_buffer(buffer); + } + } + } + + // If firmware sends network events even if the sl_net component is not include + // (probably firmware issue), Free the resources of the packet to avoid memory leak + if ((event & NCP_HOST_NETWORK_NOTIFICATION_EVENT) != 0) { + while (sl_si91x_host_queue_status(&cmd_queues[SI91X_NETWORK_CMD].event_queue) != 0) { + if (sli_si91x_remove_from_queue(&cmd_queues[SI91X_NETWORK_CMD].event_queue, &buffer) == SL_STATUS_OK) { + data = (sli_si91x_queue_packet_t *)sl_si91x_host_get_buffer_data(buffer, 0, NULL); + packet = (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data(data->host_packet, 0, NULL); + + SL_NET_EVENT_DISPATCH_HANDLER(data, packet); + + // Free the resources associated with the packet. + sl_si91x_host_free_buffer(data->host_packet); + sl_si91x_host_free_buffer(buffer); + } else { + // TODO: error handling + } + } + } + + // Process socket notification events + if ((event & NCP_HOST_SOCKET_NOTIFICATION_EVENT) != 0) { + while (0 != sl_si91x_host_queue_status(&cmd_queues[SI91X_SOCKET_CMD].event_queue)) { + if (sli_si91x_remove_from_queue(&cmd_queues[SI91X_SOCKET_CMD].event_queue, &buffer) == SL_STATUS_OK) { + data = (sli_si91x_queue_packet_t *)sl_si91x_host_get_buffer_data(buffer, 0, NULL); + packet = (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data(data->host_packet, 0, NULL); + + SL_NET_EVENT_DISPATCH_HANDLER(data, packet); + + // Free the resources associated with the packet + sl_si91x_host_free_buffer(data->host_packet); + sl_si91x_host_free_buffer(buffer); + } else { + // TODO: error handling + } + } + } + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + // Process socket data events + if (event & NCP_HOST_SOCKET_DATA_NOTIFICATION_EVENT) { + for (int i = 0; i < NUMBER_OF_SOCKETS; ++i) { + if (sli_si91x_sockets[i] != NULL) { + if (sli_si91x_remove_from_queue(&sli_si91x_sockets[i]->rx_data_queue, &buffer) == SL_STATUS_OK) { + if (sli_si91x_sockets[i]->recv_data_callback != NULL) { + packet = (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data(buffer, 0, NULL); + sl_si91x_socket_metadata_t *receive_data = (sl_si91x_socket_metadata_t *)packet->data; + sli_si91x_sockets[i]->recv_data_callback(i, + &packet->data[receive_data->offset], + receive_data->length, + receive_data); + } + sl_si91x_host_free_buffer(buffer); + } + } + } + } +#endif + } +} + +// Thread which handles the TX and RX events. +void si91x_bus_thread(const void *args) +{ + UNUSED_PARAMETER(args); + sl_status_t status; + uint16_t temp; + sli_si91x_queue_packet_t *node = NULL; + sli_si91x_queue_packet_t *error_node = NULL; + sl_wifi_buffer_t *packet; + sl_wifi_buffer_t *error_packet = NULL; + sl_wifi_buffer_t *buffer; + uint8_t tx_queues_empty = 0; + uint32_t event = 0; + uint8_t *data; + uint16_t length; + uint8_t queue_id = 0; + uint16_t frame_type = 0; + uint16_t frame_status = 0; + bool global_queue_block = false; + uint16_t interrupt_status = 0; + sl_wifi_performance_profile_t current_power_profile_mode = { 0 }; + uint32_t bus_wait_time = 0; + + // Array to track the status of commands in flight + cmd_queues[SI91X_COMMON_CMD].sequential = true; + cmd_queues[SI91X_WLAN_CMD].sequential = true; + cmd_queues[SI91X_NETWORK_CMD].sequential = true; + cmd_queues[SI91X_BT_CMD].sequential = true; + cmd_queues[SI91X_SOCKET_CMD].sequential = true; + + while (1) { + // 0 - give up bus thread + // 1 - need to process some tx commands/data packets + tx_queues_empty = ( +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + (tx_socket_data_queues_status + || (tx_socket_command_queues_status & (~(tx_socket_command_command_in_flight_queues_status)))) + || +#endif + (tx_command_queues_status & (~(tx_command_queues_command_in_flight_status))) + || tx_generic_socket_data_queues_status); + // TODO: Add checking ALL socket command queues + + // Set wait time: + // If there might be a buffer to receive, do that immediately, + // If the last interrupt_status check indicates buffer full, wait up to 10ms, + // If there is queue not empty or some event to be processed do that immediately, + // Otherwise there is nothing left to do and thus wait for an event + if (event & SL_SI91X_NCP_HOST_BUS_RX_EVENT) { + bus_wait_time = 0; + } else if (interrupt_status & RSI_BUFFER_FULL) { + bus_wait_time = 10; + } else if (tx_queues_empty == 0) { + bus_wait_time = osWaitForever; + } else { + bus_wait_time = 0; + } + + event |= si91x_host_wait_for_bus_event(BUS_THREAD_EVENTS, bus_wait_time); + +#ifndef SLI_SI91X_MCU_INTERFACE + // Wake device, if needed + if ((current_performance_profile != HIGH_PERFORMANCE)) { + while (si91x_req_wakeup() != SL_STATUS_OK) { + osDelay(1); + } + } + + // Read the interrupt status + if (sl_si91x_bus_read_interrupt_status(&interrupt_status) != SL_STATUS_OK) { + continue; + } + + // Check if there is no RX packet pending or the bus RX event is not set + if (!((interrupt_status & RSI_RX_PKT_PENDING) || (event & SL_SI91X_NCP_HOST_BUS_RX_EVENT))) { + if (current_performance_profile != HIGH_PERFORMANCE) { + // Clear the sleep indicator if the device is not in high-performance mode + sl_si91x_host_clear_sleep_indicator(); + } + } +#endif + + // Check if there is an RX packet pending or bus RX event is set + if ((event & SL_SI91X_NCP_HOST_BUS_RX_EVENT) +#ifndef SLI_SI91X_MCU_INTERFACE + && (interrupt_status & RSI_RX_PKT_PENDING) +#endif + && (sl_si91x_bus_read_frame(&buffer) == SL_STATUS_OK)) { // Allocation from RX buffer type! + + if (current_performance_profile != HIGH_PERFORMANCE) { + sl_si91x_host_clear_sleep_indicator(); + } + + // Check if the rx queue is empty +#ifdef SLI_SI91X_MCU_INTERFACE + if (sli_si91x_buffer_queue_empty(&sli_ahb_bus_rx_queue)) { +#else +#ifdef SL_NCP_UART_INTERFACE + if (sli_si91x_buffer_queue_empty(&sli_uart_bus_rx_queue)) { +#else + { +#endif +#endif + event &= ~SL_SI91X_NCP_HOST_BUS_RX_EVENT; // Reset the event flag + } + + data = (uint8_t *)sl_si91x_host_get_buffer_data(buffer, 0, &length); + // Process the frame + queue_id = ((data[1] & 0xF0) >> 4); // Extract the queue ID + frame_type = (uint16_t)(data[2] + (data[3] << 8)); // Extract the frame type + frame_status = (uint16_t)(data[12] + (data[13] << 8)); // Extract the frame status +#ifdef SLI_SI91X_MCU_INTERFACE + if ((frame_type == RSI_COMMON_RSP_TA_M4_COMMANDS) || (frame_type == RSI_WLAN_REQ_SET_CERTIFICATE)) { + // clear flag + sli_si91x_update_flash_command_status(false); + } +#endif + + const sl_si91x_packet_t *response = (const sl_si91x_packet_t *)data; + SL_DEBUG_LOG("><<<< Rx -> queueId : %u, frameId : 0x%x, frameStatus: 0x%x, length : %u\n", + queue_id, + frame_type, + frame_status, + (response->length & (~(0xF000)))); + + switch (queue_id) { + case RSI_WLAN_MGMT_Q: { + // Erase queue ID as it overlays with the length field which is only 24-bit + data[1] &= 0xF; + switch (frame_type) { + // Handle different frame types within the WLAN management queue + case RSI_COMMON_RSP_OPERMODE: + case RSI_COMMON_RSP_SOFT_RESET: + case RSI_COMMON_RSP_PWRMODE: { + if (frame_type == cmd_queues[SI91X_COMMON_CMD].frame_type) { + if ((RSI_COMMON_RSP_PWRMODE == frame_type) && (frame_status == SL_STATUS_OK)) { + get_wifi_current_performance_profile(¤t_power_profile_mode); + current_performance_profile = current_power_profile_mode.profile; + } + if (current_performance_profile != HIGH_PERFORMANCE) { + // Clear the sleep indicator if the device is not in high-performance mode + sl_si91x_host_clear_sleep_indicator(); + } + global_queue_block = false; + } + } + // intentional fallthrough + __attribute__((fallthrough)); + case RSI_COMMON_RSP_GET_EFUSE_DATA: + case RSI_COMMON_RSP_GET_RAM_DUMP: + case RSI_COMMON_RSP_ANTENNA_SELECT: + case RSI_COMMON_RSP_ENCRYPT_CRYPTO: +#ifdef SLI_PUF_ENABLE + case RSI_COMMON_RSP_PUF_ENROLL: + case RSI_COMMON_RSP_PUF_DIS_ENROLL: + case RSI_COMMON_RSP_PUF_START: + case RSI_COMMON_RSP_PUF_SET_KEY: + case RSI_COMMON_RSP_PUF_DIS_SET_KEY: + case RSI_COMMON_RSP_PUF_GET_KEY: + case RSI_COMMON_RSP_PUF_DIS_GET_KEY: + case RSI_COMMON_RSP_PUF_LOAD_KEY: + case RSI_COMMON_RSP_AES_ENCRYPT: + case RSI_COMMON_RSP_AES_DECRYPT: + case RSI_COMMON_RSP_AES_MAC: + case RSI_COMMON_RSP_PUF_INTR_KEY: +#endif + case RSI_COMMON_RSP_SET_RTC_TIMER: + case RSI_COMMON_RSP_GET_RTC_TIMER: + case RSI_COMMON_RSP_TA_M4_COMMANDS: + case RSI_COMMON_RSP_SET_CONFIG: + case RSI_COMMON_RSP_GET_CONFIG: + case RSI_COMMON_RSP_DEBUG_LOG: + case RSI_COMMON_RSP_FEATURE_FRAME: { + ++cmd_queues[SI91X_COMMON_CMD].rx_counter; // Increment the received counter for common commands + + // Check if this command is expected to have a response status + if (((cmd_queues[SI91X_COMMON_CMD].flags & SI91X_PACKET_RESPONSE_STATUS) == SI91X_PACKET_RESPONSE_STATUS) + && (cmd_queues[SI91X_COMMON_CMD].frame_type == frame_type)) { + // Allocate a packet to store the response + status = sl_si91x_host_allocate_buffer(&packet, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sli_si91x_queue_packet_t), + 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Depending on the configuration, attach the original buffer or not + if (SI91X_PACKET_RESPONSE_PACKET + == (cmd_queues[SI91X_COMMON_CMD].flags & SI91X_PACKET_RESPONSE_PACKET)) { + node->host_packet = buffer; + } else { + node->host_packet = NULL; + sl_si91x_host_free_buffer(buffer); + } + + // Populate packet metadata + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_COMMON_CMD; + node->sdk_context = cmd_queues[SI91X_COMMON_CMD].sdk_context; + node->flags = cmd_queues[SI91X_COMMON_CMD].flags; + // node->packet_id = cmd_queues[SI91X_COMMON_CMD].packet_id; + buffer->id = cmd_queues[SI91X_COMMON_CMD].packet_id; + packet->id = cmd_queues[SI91X_COMMON_CMD].packet_id; + + if (sl_si91x_host_elapsed_time(cmd_queues[SI91X_COMMON_CMD].command_tickcount) + <= (cmd_queues[SI91X_COMMON_CMD].command_timeout)) { + // Add the response packet to the common response queue + sli_si91x_append_to_buffer_queue(&cmd_queues[SI91X_COMMON_CMD].rx_queue, packet); + sli_si91x_set_event(NCP_HOST_COMMON_RESPONSE_EVENT); + } else { + // no user thread is waiting for the response so flush the packet + sl_si91x_host_free_buffer(packet); + if ((cmd_queues[SI91X_COMMON_CMD].flags & SI91X_PACKET_RESPONSE_PACKET) + == SI91X_PACKET_RESPONSE_PACKET) { + sl_si91x_host_free_buffer(buffer); + } + } + cmd_queues[SI91X_COMMON_CMD].command_tickcount = 0; + cmd_queues[SI91X_COMMON_CMD].command_timeout = 0; + } else { + sl_si91x_host_free_buffer(buffer); + } + + // Marking a received frame as not in flight when it matches the expected type. + if (frame_type == cmd_queues[SI91X_COMMON_CMD].frame_type) { + cmd_queues[SI91X_COMMON_CMD].command_in_flight = false; + cmd_queues[SI91X_COMMON_CMD].frame_type = 0; + } + break; + } + case RSI_WLAN_RSP_BAND: + case RSI_WLAN_RSP_INIT: + case RSI_WLAN_RSP_RADIO: + case RSI_WLAN_RSP_EAP_CONFIG: + case RSI_WLAN_RSP_SET_CERTIFICATE: + case RSI_WLAN_RSP_HOST_PSK: + case RSI_WLAN_RSP_JOIN: + case RSI_WLAN_RSP_SCAN: + case RSI_WLAN_RSP_SCAN_RESULTS: + case RSI_WLAN_RSP_FW_VERSION: + case RSI_WLAN_RSP_FULL_FW_VERSION: + case RSI_WLAN_RSP_FWUP: + case RSI_WLAN_RSP_DISCONNECT: + case RSI_WLAN_RSP_AP_STOP: + case RSI_WLAN_RSP_RSSI: + case RSI_WLAN_RSP_TSF: + case RSI_WLAN_RSP_AP_CONFIGURATION: + case RSI_WLAN_RSP_WPS_METHOD: + case RSI_WLAN_RSP_QUERY_NETWORK_PARAMS: + case RSI_WLAN_RSP_SET_MAC_ADDRESS: + case RSI_WLAN_RSP_SET_REGION: + case RSI_WLAN_RSP_SET_REGION_AP: + case RSI_WLAN_RSP_MAC_ADDRESS: + case RSI_WLAN_RSP_EXT_STATS: + case RSI_WLAN_RSP_GET_STATS: + case RSI_WLAN_RSP_RX_STATS: + case RSI_WLAN_RSP_MODULE_STATE: + case RSI_WLAN_RSP_QUERY_GO_PARAMS: + case RSI_WLAN_RSP_ROAM_PARAMS: + case RSI_WLAN_RSP_HTTP_OTAF: + case RSI_WLAN_RSP_CLIENT_CONNECTED: + case RSI_WLAN_RSP_CLIENT_DISCONNECTED: + case RSI_WLAN_RSP_CALIB_WRITE: + case RSI_WLAN_RSP_GET_DPD_DATA: + case RSI_WLAN_RSP_CALIB_READ: + case RSI_WLAN_RSP_FREQ_OFFSET: + case RSI_WLAN_RSP_EVM_OFFSET: + case RSI_WLAN_RSP_EVM_WRITE: + case RSI_WLAN_RSP_EFUSE_READ: + case RSI_WLAN_RSP_FILTER_BCAST_PACKETS: + case RSI_WLAN_RSP_TWT_PARAMS: + case RSI_WLAN_RSP_TWT_ASYNC: + case RSI_WLAN_RSP_TWT_AUTO_CONFIG: + case RSI_WLAN_RSP_11AX_PARAMS: + case SL_WIFI_RSP_RESCHEDULE_TWT: + case RSI_WLAN_RSP_REJOIN_PARAMS: + case RSI_WLAN_RSP_GAIN_TABLE: + case RSI_WLAN_RSP_TX_TEST_MODE: + case RSI_WLAN_RSP_TIMEOUT: + case RSI_WLAN_RSP_BEACON_STOP: + case RSI_WLAN_RSP_DYNAMIC_POOL: + case RSI_WLAN_RSP_TRANSCEIVER_SET_CHANNEL: + case RSI_WLAN_RSP_TRANSCEIVER_CONFIG_PARAMS: + case RSI_WLAN_RSP_TRANSCEIVER_PEER_LIST_UPDATE: + case RSI_WLAN_RSP_TRANSCEIVER_SET_MCAST_FILTER: + case RSI_WLAN_RSP_TRANSCEIVER_FLUSH_DATA_Q: + case RSI_WLAN_RSP_TRANSCEIVER_TX_DATA_STATUS: + case RSI_WLAN_RSP_HT_CAPABILITIES: + case RSI_WLAN_RSP_SET_MULTICAST_FILTER: { + ++cmd_queues[SI91X_WLAN_CMD].rx_counter; + + // Marking a received frame as not in flight when it matches the expected type + if (frame_type == cmd_queues[SI91X_WLAN_CMD].frame_type) { + cmd_queues[SI91X_WLAN_CMD].command_in_flight = false; + } + + // Check if the frame type indicates a failed join operation or a disconnect + if (((RSI_WLAN_RSP_JOIN == frame_type) && (frame_status != SL_STATUS_OK)) + || (RSI_WLAN_RSP_DISCONNECT == frame_type) || (RSI_WLAN_RSP_CLIENT_DISCONNECTED == frame_type) + || (RSI_WLAN_RSP_AP_STOP == frame_type)) { + + // create dummy packets for respective queues to be cleared + sli_handle_dhcp_and_rejoin_failure(cmd_queues[SI91X_WLAN_CMD].sdk_context, buffer, frame_status); + } + if (((RSI_WLAN_RSP_JOIN == frame_type) && (frame_status != SL_STATUS_OK)) + || (RSI_WLAN_RSP_DISCONNECT == frame_type)) { + // Reset current performance profile and set it to high performance + reset_coex_current_performance_profile(); + current_performance_profile = HIGH_PERFORMANCE; + } + + // check if the frame type is valid + if (((cmd_queues[SI91X_WLAN_CMD].flags & SI91X_PACKET_RESPONSE_STATUS) == SI91X_PACKET_RESPONSE_STATUS) + && (cmd_queues[SI91X_WLAN_CMD].frame_type == frame_type)) { + + // Allocate a buffer for the response packet + status = sl_si91x_host_allocate_buffer(&packet, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sli_si91x_queue_packet_t), + 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Check if the packet response mode is set, and associate the host packet accordingly + if (SI91X_PACKET_RESPONSE_PACKET == (cmd_queues[SI91X_WLAN_CMD].flags & SI91X_PACKET_RESPONSE_PACKET)) { + node->host_packet = buffer; + } else { + node->host_packet = NULL; + sl_si91x_host_free_buffer(buffer); + } + + // Populate the response packet information + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_WLAN_CMD; + node->sdk_context = cmd_queues[SI91X_WLAN_CMD].sdk_context; + node->flags = cmd_queues[SI91X_WLAN_CMD].flags; + // node->packet_id = cmd_queues[SI91X_WLAN_CMD].packet_id; + packet->id = cmd_queues[SI91X_WLAN_CMD].packet_id; + buffer->id = cmd_queues[SI91X_WLAN_CMD].packet_id; + + if (sl_si91x_host_elapsed_time(cmd_queues[SI91X_WLAN_CMD].command_tickcount) + <= (cmd_queues[SI91X_WLAN_CMD].command_timeout)) { + // Add the response packet to the WLAN response queue and set the WLAN response event + sli_si91x_add_to_queue(&cmd_queues[SI91X_WLAN_CMD].rx_queue, packet); + sli_si91x_set_event(NCP_HOST_WLAN_RESPONSE_EVENT); + } else { + // no user thread is waiting for the response so flush the packet + sl_si91x_host_free_buffer(packet); + if ((cmd_queues[SI91X_WLAN_CMD].flags & SI91X_PACKET_RESPONSE_PACKET) + == SI91X_PACKET_RESPONSE_PACKET) { + sl_si91x_host_free_buffer(buffer); + } + } + cmd_queues[SI91X_WLAN_CMD].command_tickcount = 0; + cmd_queues[SI91X_WLAN_CMD].command_timeout = 0; + } else { + // The received frame does not match the expected response status and frame type, + // so add it to the WLAN event queue and set the WLAN notification event + sli_si91x_add_to_queue(&cmd_queues[SI91X_WLAN_CMD].event_queue, buffer); + set_async_event(NCP_HOST_WLAN_NOTIFICATION_EVENT); + } + + // Resetting the frame_type in cmd_queues when it matches the expected frame_type + if (frame_type == cmd_queues[SI91X_WLAN_CMD].frame_type) { + cmd_queues[SI91X_WLAN_CMD].frame_type = 0; + } + + break; + } + // Handle WLAN response frame type for background scan + case RSI_WLAN_RSP_BG_SCAN: { + ++cmd_queues[SI91X_WLAN_CMD].rx_counter; + + // Check if the received frame matches the expected response status and frame type + if (((cmd_queues[SI91X_WLAN_CMD].flags & SI91X_PACKET_RESPONSE_STATUS) == SI91X_PACKET_RESPONSE_STATUS) + && (cmd_queues[SI91X_WLAN_CMD].frame_type == frame_type)) { + // Allocate a buffer for the response packet + status = sl_si91x_host_allocate_buffer(&packet, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sli_si91x_queue_packet_t), + 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_WLAN_CMD; + node->sdk_context = cmd_queues[SI91X_WLAN_CMD].sdk_context; + node->flags = cmd_queues[SI91X_WLAN_CMD].flags; + // node->packet_id = cmd_queues[SI91X_WLAN_CMD].packet_id; + buffer->id = cmd_queues[SI91X_WLAN_CMD].packet_id; + packet->id = cmd_queues[SI91X_WLAN_CMD].packet_id; + node->host_packet = NULL; + + if (sl_si91x_host_elapsed_time(cmd_queues[SI91X_WLAN_CMD].command_tickcount) + <= (cmd_queues[SI91X_WLAN_CMD].command_timeout)) { + // Add the response packet to the WLAN response queue and set the WLAN response event + sli_si91x_add_to_queue(&cmd_queues[SI91X_WLAN_CMD].rx_queue, packet); + sli_si91x_set_event(NCP_HOST_WLAN_RESPONSE_EVENT); + } else { + // no user thread is waiting for the response so flush the packet and buffer + sl_si91x_host_free_buffer(packet); + } + cmd_queues[SI91X_WLAN_CMD].command_tickcount = 0; + cmd_queues[SI91X_WLAN_CMD].command_timeout = 0; + sl_si91x_host_free_buffer(buffer); + } else { + // If frame status is OK, set bg_enabled flag + if (frame_status == SL_STATUS_OK) { + bg_enabled = true; + } + // Add the received frame to the WLAN event queue and set the WLAN notification event + sli_si91x_add_to_queue(&cmd_queues[SI91X_WLAN_CMD].event_queue, buffer); + set_async_event(NCP_HOST_WLAN_NOTIFICATION_EVENT); + } + // Marking a received frame as not in flight when it matches the expected type + if (frame_type == cmd_queues[SI91X_WLAN_CMD].frame_type) { + cmd_queues[SI91X_WLAN_CMD].command_in_flight = false; + cmd_queues[SI91X_WLAN_CMD].frame_type = 0; + } + break; + } + case RSI_WLAN_RSP_CONFIG: { + ++cmd_queues[SI91X_WLAN_CMD].rx_counter; + + // Check if the received frame matches the expected response status and frame type + if (((cmd_queues[SI91X_WLAN_CMD].flags & SI91X_PACKET_RESPONSE_STATUS) == SI91X_PACKET_RESPONSE_STATUS) + && (cmd_queues[SI91X_WLAN_CMD].frame_type == frame_type)) { + // Allocate a buffer for the response packet + status = sl_si91x_host_allocate_buffer(&packet, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sli_si91x_queue_packet_t), + 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Check if the frame status indicates an invalid configuration type + if ((SL_STATUS_SI91X_INVALID_CONFIG_TYPE & 0xFF) == frame_status) { + node->frame_status = 0; + } else { + node->frame_status = frame_status; + } + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_WLAN_CMD; + node->sdk_context = cmd_queues[SI91X_WLAN_CMD].sdk_context; + node->flags = cmd_queues[SI91X_WLAN_CMD].flags; + // node->packet_id = cmd_queues[SI91X_WLAN_CMD].packet_id; + buffer->id = cmd_queues[SI91X_WLAN_CMD].packet_id; + packet->id = cmd_queues[SI91X_WLAN_CMD].packet_id; + node->host_packet = NULL; + + if (sl_si91x_host_elapsed_time(cmd_queues[SI91X_WLAN_CMD].command_tickcount) + <= (cmd_queues[SI91X_WLAN_CMD].command_timeout)) { + // Add the response packet to response queue and set the WLAN response event + sli_si91x_add_to_queue(&cmd_queues[SI91X_WLAN_CMD].rx_queue, packet); + sli_si91x_set_event(NCP_HOST_WLAN_RESPONSE_EVENT); + } else { + // no user thread is waiting for the response so flush the packet + sl_si91x_host_free_buffer(packet); + } + cmd_queues[SI91X_WLAN_CMD].command_tickcount = 0; + cmd_queues[SI91X_WLAN_CMD].command_timeout = 0; + } + + // check if the frame type is valid. + if (frame_type == cmd_queues[SI91X_WLAN_CMD].frame_type) { + cmd_queues[SI91X_WLAN_CMD].command_in_flight = false; + cmd_queues[SI91X_WLAN_CMD].frame_type = 0; + } + + sl_si91x_host_free_buffer(buffer); + break; + } + case RSI_COMMON_RSP_ULP_NO_RAM_RETENTION: { + //This frame will come, when the M4 is waken in without ram retention. This frame is equivalent to RSI_COMMON_RSP_CARDREADY + sl_si91x_host_clear_sleep_indicator(); + } + // intentional fallthrough + __attribute__((fallthrough)); + case RSI_COMMON_RSP_CARDREADY: { + ++cmd_queues[SI91X_COMMON_CMD].rx_counter; + + // Check if the frame type is valid + if (frame_type == cmd_queues[SI91X_COMMON_CMD].frame_type) { + // Mark the common command as not in flight + cmd_queues[SI91X_COMMON_CMD].command_in_flight = false; + cmd_queues[SI91X_COMMON_CMD].frame_type = 0; + cmd_queues[SI91X_COMMON_CMD].command_tickcount = 0; + cmd_queues[SI91X_COMMON_CMD].command_timeout = 0; + } + + sl_si91x_host_free_buffer(buffer); + sli_si91x_set_event(NCP_HOST_COMMON_RESPONSE_EVENT); + break; + } + case RSI_WLAN_RSP_IPCONFV4: + case RSI_WLAN_RSP_IPCONFV6: + case RSI_WLAN_RSP_IPV4_CHANGE: + case RSI_WLAN_RSP_OTA_FWUP: + case RSI_WLAN_RSP_DNS_QUERY: + case RSI_WLAN_RSP_DNS_SERVER_ADD: + case RSI_WLAN_RSP_SET_SNI_EMBEDDED: + case RSI_WLAN_RSP_MULTICAST: + case RSI_WLAN_RSP_PING_PACKET: + case RSI_WLAN_RSP_SNTP_CLIENT: + case RSI_WLAN_RSP_EMB_MQTT_CLIENT: + case RSI_WLAN_RSP_EMB_MQTT_PUBLISH_PKT: + case RSI_WLAN_RSP_MQTT_REMOTE_TERMINATE: + case RSI_WLAN_RSP_MDNSD: { + // Increment the received frame counter for network commands + ++cmd_queues[SI91X_NETWORK_CMD].rx_counter; + + // Allocate a buffer for the response packet + status = + sl_si91x_host_allocate_buffer(&packet, SL_WIFI_RX_FRAME_BUFFER, sizeof(sli_si91x_queue_packet_t), 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Set frame status, queue ID, and command type for the network response + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_NETWORK_CMD; + + // Check if the frame type is valid + if ((frame_type == cmd_queues[SI91X_NETWORK_CMD].frame_type) + || (frame_type == RSI_WLAN_RSP_IPCONFV6 + && cmd_queues[SI91X_NETWORK_CMD].frame_type == RSI_WLAN_REQ_IPCONFV6)) { + node->sdk_context = cmd_queues[SI91X_NETWORK_CMD].sdk_context; + node->flags = cmd_queues[SI91X_NETWORK_CMD].flags; + // node->packet_id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + packet->id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + buffer->id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + } else { + node->sdk_context = NULL; + node->flags = 0; + // node->packet_id = 0; + packet->id = 0; + buffer->id = 0; + } + // Set the host packet to the received buffer + node->host_packet = buffer; + + if (((frame_type == RSI_WLAN_RSP_MQTT_REMOTE_TERMINATE) + || (frame_type == RSI_WLAN_RSP_EMB_MQTT_CLIENT + && frame_status == (SL_STATUS_SI91X_MQTT_KEEP_ALIVE_TERMINATE_ERROR & ~BIT(16)))) + && (cmd_queues[SI91X_NETWORK_CMD].frame_type == RSI_WLAN_RSP_EMB_MQTT_CLIENT)) { + cmd_queues[SI91X_NETWORK_CMD].command_in_flight = false; + cmd_queues[SI91X_NETWORK_CMD].frame_type = 0; + + if (cmd_queues[SI91X_NETWORK_CMD].flags == 0) { + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].event_queue, packet); + set_async_event(NCP_HOST_NETWORK_NOTIFICATION_EVENT); + break; + } + + // if command present in cmd_queues, an error RX packet is enqueued to network queue and command in flight is set to false. + + // Allocate a buffer for the error packet + status = sl_si91x_host_allocate_buffer(&error_packet, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sli_si91x_queue_packet_t), + 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + error_node = sl_si91x_host_get_buffer_data(error_packet, 0, NULL); + error_node->frame_status = (SL_STATUS_SI91X_MQTT_REMOTE_TERMINATE_ERROR + & 0xFFFF); // error given by firmware for remote terminate + error_node->host_packet = NULL; + error_node->flags = cmd_queues[SI91X_NETWORK_CMD].flags; + // error_node->packet_id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + error_packet->id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].rx_queue, error_packet); + sli_si91x_set_event(NCP_HOST_NETWORK_RESPONSE_EVENT); + cmd_queues[SI91X_NETWORK_CMD].command_tickcount = 0; + cmd_queues[SI91X_NETWORK_CMD].command_timeout = 0; + break; + } + + // Check if it's a response packet, and handle accordingly + if (((cmd_queues[SI91X_NETWORK_CMD].flags & SI91X_PACKET_RESPONSE_STATUS) == SI91X_PACKET_RESPONSE_STATUS) + && ((cmd_queues[SI91X_NETWORK_CMD].frame_type == frame_type) + || (cmd_queues[SI91X_NETWORK_CMD].frame_type == RSI_WLAN_REQ_IPCONFV6 + && frame_type == RSI_WLAN_RSP_IPCONFV6))) { + + // Check if the response packet should be free or not + if (SI91X_PACKET_RESPONSE_PACKET + != (cmd_queues[SI91X_NETWORK_CMD].flags & SI91X_PACKET_RESPONSE_PACKET)) { + node->host_packet = NULL; + sl_si91x_host_free_buffer(buffer); + } + if (sl_si91x_host_elapsed_time(cmd_queues[SI91X_NETWORK_CMD].command_tickcount) + <= (cmd_queues[SI91X_NETWORK_CMD].command_timeout)) { + // Add the response packet to response queue and set the network response event + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].rx_queue, packet); + sli_si91x_set_event(NCP_HOST_NETWORK_RESPONSE_EVENT); + } else { + // no user thread is waiting for the response so flush the packet + sl_si91x_host_free_buffer(packet); + if ((cmd_queues[SI91X_NETWORK_CMD].flags & SI91X_PACKET_RESPONSE_PACKET) + == SI91X_PACKET_RESPONSE_PACKET) { + sl_si91x_host_free_buffer(buffer); + } + } + cmd_queues[SI91X_NETWORK_CMD].command_tickcount = 0; + cmd_queues[SI91X_NETWORK_CMD].command_timeout = 0; + } else { + // Add the packet to event queue and set the async network event + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].event_queue, packet); + set_async_event(NCP_HOST_NETWORK_NOTIFICATION_EVENT); + } + + // Check If the frame type is valid. + if ((frame_type == cmd_queues[SI91X_NETWORK_CMD].frame_type) + || (frame_type == RSI_WLAN_RSP_IPCONFV6 + && cmd_queues[SI91X_NETWORK_CMD].frame_type == RSI_WLAN_REQ_IPCONFV6)) { + cmd_queues[SI91X_NETWORK_CMD].command_in_flight = false; + cmd_queues[SI91X_NETWORK_CMD].frame_type = 0; + } + + // Check if the frame type indicates a failed join operation or a disconnect + if (((RSI_WLAN_RSP_IPCONFV4 == frame_type) && (frame_status != SL_STATUS_OK)) + || (RSI_WLAN_RSP_IPV4_CHANGE == frame_type)) { + // Reset current performance profile and set it to high performance + reset_coex_current_performance_profile(); + current_performance_profile = HIGH_PERFORMANCE; + // check for command in flight and create dummy packets for respective queues to be cleared + sli_handle_dhcp_and_rejoin_failure(cmd_queues[SI91X_NETWORK_CMD].sdk_context, buffer, frame_status); + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].event_queue, packet); + set_async_event(NCP_HOST_NETWORK_NOTIFICATION_EVENT); + } + break; + } +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + case RSI_WLAN_RSP_CONN_ESTABLISH: + frame_type = RSI_WLAN_RSP_SOCKET_ACCEPT; + // fall-through + case RSI_WLAN_RSP_SOCKET_CONFIG: + case RSI_WLAN_RSP_SOCKET_CREATE: + case RSI_WLAN_RSP_SOCKET_CLOSE: + case RSI_WLAN_RSP_SELECT_REQUEST: + case RSI_WLAN_RSP_SOCKET_READ_DATA: // Socket read data response only is expected incase of failure + case RSI_WLAN_RSP_SOCKET_ACCEPT: + case RSI_WLAN_RSP_REMOTE_TERMINATE: { + // Find relevant socket + sl_si91x_packet_t *socket_packet = (sl_si91x_packet_t *)data; + sli_si91x_socket_t *socket = get_socket_from_packet(socket_packet); + sli_si91x_command_queue_t *socket_command_queue; + + if ((socket == NULL) || (frame_type == RSI_WLAN_RSP_SELECT_REQUEST) + || (frame_type == RSI_WLAN_RSP_SOCKET_CREATE) || (frame_type == RSI_WLAN_RSP_SOCKET_CONFIG)) { + socket_command_queue = &cmd_queues[SI91X_SOCKET_CMD]; + } else { + socket_command_queue = &socket->command_queue; + } + + if (frame_type == RSI_WLAN_RSP_SELECT_REQUEST) { + // Allocate a buffer for the response packet + status = sl_si91x_host_allocate_buffer(&packet, + SL_WIFI_RX_FRAME_BUFFER, + sizeof(sli_si91x_queue_packet_t), + 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Set frame status, queue ID, and command type for the network response + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_SOCKET_CMD; + node->host_packet = buffer; + node->sdk_context = NULL; + // and set asynchronous socket notification event + sli_si91x_add_to_queue(&cmd_queues[SI91X_SOCKET_CMD].event_queue, packet); + set_async_event(NCP_HOST_SOCKET_NOTIFICATION_EVENT); + break; + } + ++socket_command_queue->rx_counter; + + if ((socket_command_queue->command_timeout != 0) + && (sl_si91x_host_elapsed_time(socket_command_queue->command_tickcount) + > (socket_command_queue->command_timeout))) { + sl_si91x_host_free_buffer(buffer); + socket_command_queue->command_tickcount = 0; + socket_command_queue->command_timeout = 0; + break; + } + + if (frame_type == RSI_WLAN_RSP_SOCKET_READ_DATA && socket_command_queue->frame_type == frame_type) { + buffer->id = (uint8_t)(socket->command_queue.packet_id); + socket_command_queue->command_in_flight = false; + socket_command_queue->frame_type = 0; + sli_si91x_add_to_queue(&socket->rx_data_queue, buffer); + sli_si91x_set_socket_event(1 << socket->index); + break; + } + + // Allocate a buffer for the response packet + status = + sl_si91x_host_allocate_buffer(&packet, SL_WIFI_RX_FRAME_BUFFER, sizeof(sli_si91x_queue_packet_t), 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Set frame status, queue ID, and command type for the socket response + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_SOCKET_CMD; + node->host_packet = buffer; + + // Check if the frame type is valid + if (socket_command_queue->frame_type == frame_type) { + node->sdk_context = socket_command_queue->sdk_context; + node->flags = socket_command_queue->flags; + // node->packet_id = socket_command_queue->packet_id; + buffer->id = socket_command_queue->packet_id; + packet->id = socket_command_queue->packet_id; + } else { + node->sdk_context = NULL; + node->flags = 0; + // node->packet_id = 0; + buffer->id = 0; + packet->id = 0; + } + + // Check if it's a response packet, and handle accordingly + if ((socket_command_queue->flags & SI91X_PACKET_RESPONSE_STATUS) + && (socket_command_queue->frame_type == frame_type)) { + + // Check if the response packet should be free or not + if ((socket_command_queue->flags & SI91X_PACKET_RESPONSE_PACKET) == 0) { + node->host_packet = NULL; + sl_si91x_host_free_buffer(buffer); + } + + // Add the response packet to the socket response queue and set the socket response event + sli_si91x_add_to_queue(&socket_command_queue->rx_queue, packet); + + if (socket_command_queue == &cmd_queues[SI91X_SOCKET_CMD]) { + sli_si91x_set_event(NCP_HOST_SOCKET_RESPONSE_EVENT); + } else { + sli_si91x_set_socket_event(1 << socket->index); + } + socket_command_queue->command_tickcount = 0; + socket_command_queue->command_timeout = 0; + + } else { + // and set asynchronous socket notification event + sli_si91x_add_to_queue(&cmd_queues[SI91X_SOCKET_CMD].event_queue, packet); + set_async_event(NCP_HOST_SOCKET_NOTIFICATION_EVENT); + } + + // If the frame_type matches the expected frame_type for the socket command + // mark the command as not in flight and clear the frame_type + if (frame_type == socket_command_queue->frame_type) { + socket_command_queue->command_in_flight = false; + socket_command_queue->frame_type = 0; + } + + break; + } +#endif + + // Handle TCP ACK Indication response + case RSI_WLAN_RSP_TCP_ACK_INDICATION: { + // Allocate memory for a new packet + status = + sl_si91x_host_allocate_buffer(&packet, SL_WIFI_RX_FRAME_BUFFER, sizeof(sli_si91x_queue_packet_t), 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Populate the packet's information + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_SOCKET_CMD; + node->host_packet = buffer; + + node->sdk_context = NULL; + node->flags = 0; + // node->packet_id = 0; + buffer->id = 0; + packet->id = 0; + + // Add the packet to the socket event queue and set the asynchronous socket notification event + sli_si91x_add_to_queue(&cmd_queues[SI91X_SOCKET_CMD].event_queue, packet); + set_async_event(NCP_HOST_SOCKET_NOTIFICATION_EVENT); + break; + } +#ifdef SLI_SI91X_INTERNAL_HTTP_CLIENT + case RSI_WLAN_RSP_HTTP_CLIENT_GET: + case RSI_WLAN_RSP_HTTP_CLIENT_POST: + case RSI_WLAN_RSP_HTTP_CLIENT_POST_DATA: { + ++cmd_queues[SI91X_NETWORK_CMD].rx_counter; + + if (cmd_queues[SI91X_NETWORK_CMD].frame_type == RSI_WLAN_RSP_HTTP_CLIENT_GET) { + // If it's an HTTP GET response, check if the frame_status is not OK or if end_of_data is set to 1. + sl_si91x_packet_t *get_response_packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + const uint16_t *end_of_data = (uint16_t *)&get_response_packet->data; + + if (frame_status != SL_STATUS_OK || *end_of_data == 1) { + // Mark the command as not in flight and clear the frame_type + cmd_queues[SI91X_NETWORK_CMD].command_in_flight = false; + cmd_queues[SI91X_NETWORK_CMD].frame_type = 0; + } + } else { + // For other HTTP responses, mark the command as not in flight and clear the frame_type + cmd_queues[SI91X_NETWORK_CMD].command_in_flight = false; + cmd_queues[SI91X_NETWORK_CMD].frame_type = 0; + } + + // Allocate memory for a new packet + status = + sl_si91x_host_allocate_buffer(&packet, SL_WIFI_RX_FRAME_BUFFER, sizeof(sli_si91x_queue_packet_t), 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Populate the packet's information + node->host_packet = buffer; + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_NETWORK_CMD; + node->sdk_context = cmd_queues[SI91X_NETWORK_CMD].sdk_context; + node->flags = cmd_queues[SI91X_NETWORK_CMD].flags; + // node->packet_id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + buffer->id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + packet->id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + + // Add the packet to the network event queue and set the asynchronous network notification event + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].event_queue, packet); + set_async_event(NCP_HOST_NETWORK_NOTIFICATION_EVENT); + break; + } + case RSI_WLAN_RSP_HTTP_ABORT: + case RSI_WLAN_RSP_HTTP_CLIENT_PUT: { + ++cmd_queues[SI91X_NETWORK_CMD].rx_counter; + + status = + sl_si91x_host_allocate_buffer(&packet, SL_WIFI_RX_FRAME_BUFFER, sizeof(sli_si91x_queue_packet_t), 1000); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n HEAP EXHAUSTED DURING ALLOCATION \r\n"); + BREAKPOINT(); + } + node = sl_si91x_host_get_buffer_data(packet, 0, &temp); + + // Populate the packet's information + node->frame_status = frame_status; + node->firmware_queue_id = RSI_WLAN_MGMT_Q; + node->command_type = SI91X_NETWORK_CMD; + node->sdk_context = cmd_queues[SI91X_NETWORK_CMD].sdk_context; + node->flags = cmd_queues[SI91X_NETWORK_CMD].flags; + // node->packet_id = command_trace[SI91X_NETWORK_CMD].packet_id; + buffer->id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + packet->id = cmd_queues[SI91X_NETWORK_CMD].packet_id; + + if (((cmd_queues[SI91X_NETWORK_CMD].flags & SI91X_PACKET_RESPONSE_STATUS) == SI91X_PACKET_RESPONSE_STATUS) + && (cmd_queues[SI91X_NETWORK_CMD].frame_type == frame_type)) { + // If it's a response status and the frame_type matches, set host_packet to NULL and free the buffer + node->host_packet = NULL; + sl_si91x_host_free_buffer(buffer); + + if (sl_si91x_host_elapsed_time(cmd_queues[SI91X_NETWORK_CMD].command_tickcount) + <= (cmd_queues[SI91X_NETWORK_CMD].command_timeout)) { + // Add the packet to the network response queue and set the network response event + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].rx_queue, packet); + sli_si91x_set_event(NCP_HOST_NETWORK_RESPONSE_EVENT); + } else { + // no user thread is waiting for the response so flush the packet and buffer + sl_si91x_host_free_buffer(packet); + if ((cmd_queues[SI91X_NETWORK_CMD].flags & SI91X_PACKET_RESPONSE_STATUS) + != SI91X_PACKET_RESPONSE_STATUS) { + sl_si91x_host_free_buffer(buffer); + } + } + } else { + // For other cases, set host_packet to buffer and add it to the network event queue + node->host_packet = buffer; + + sli_si91x_add_to_queue(&cmd_queues[SI91X_NETWORK_CMD].event_queue, packet); + set_async_event(NCP_HOST_NETWORK_NOTIFICATION_EVENT); + } + + if (frame_type == cmd_queues[SI91X_NETWORK_CMD].frame_type) { + // mark the command as not in flight and clear the frame_type + cmd_queues[SI91X_NETWORK_CMD].command_in_flight = false; + cmd_queues[SI91X_NETWORK_CMD].frame_type = 0; + cmd_queues[SI91X_NETWORK_CMD].command_tickcount = 0; + cmd_queues[SI91X_NETWORK_CMD].command_timeout = 0; + } + break; + } +#endif + default: { + // frame_type doesn't match any known cases + if (PRINT_ERROR_LOGS) { + PRINT_ERROR_STATUS(INFO_TAG, frame_type); + } + // Free the buffer + sl_si91x_host_free_buffer(buffer); + break; + } + } + break; + } + + case RSI_WLAN_DATA_Q: { + // Erase queue ID as it overlays with the length field which is only 24-bit + data[1] &= 0xF; + if (frame_type == RSI_RECEIVE_RAW_DATA) { + // If the frame type is raw data reception + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + SL_DEBUG_LOG("Raw Data\n"); + sl_si91x_packet_t *socket_packet = (sl_si91x_packet_t *)data; + sli_si91x_socket_t *socket = NULL; + int socket_id = sli_si91x_get_socket_id(socket_packet); + socket = sli_si91x_get_socket_from_id(socket_id, LISTEN, -1); + + // Check if we found a matching socket + if (socket != NULL) { + buffer->id = (uint8_t)(socket->command_queue.packet_id); + // Check if command has timed out + if (socket->command_queue.command_tickcount == 0 + || (sl_si91x_host_elapsed_time(socket->command_queue.command_tickcount) + <= (socket->command_queue.command_timeout))) { + if (((socket->command_queue.frame_type == RSI_WLAN_RSP_SOCKET_READ_DATA) + || (socket->command_queue.frame_type == socket_packet->command)) + && socket->command_queue.command_in_flight + && socket->command_queue.flags & SI91X_PACKET_RESPONSE_PACKET) { + socket->command_queue.command_in_flight = false; + sli_si91x_add_to_queue(&socket->rx_data_queue, buffer); + sli_si91x_set_socket_event(1 << socket->index); + } else { + sli_si91x_add_to_queue(&socket->rx_data_queue, buffer); + set_async_event(NCP_HOST_SOCKET_DATA_NOTIFICATION_EVENT); + } + } else { + sli_si91x_add_to_queue(&socket->rx_data_queue, buffer); + set_async_event(NCP_HOST_SOCKET_DATA_NOTIFICATION_EVENT); + // sl_si91x_host_free_buffer(buffer); + } + socket->command_queue.command_tickcount = 0; + socket->command_queue.command_timeout = 0; + } +#else + // If SLI_SI91X_OFFLOAD_NETWORK_STACK is not defined, process the data frame and free the buffer. + sl_si91x_host_process_data_frame(SL_WIFI_CLIENT_INTERFACE, buffer); + sl_si91x_host_free_buffer(buffer); +#endif + } else if (frame_type == SL_SI91X_WIFI_RX_DOT11_DATA) { + ++cmd_queues[SI91X_WLAN_CMD].rx_counter; + + // Marking a received frame as not in flight when it matches the expected type + if (frame_type == cmd_queues[SI91X_WLAN_CMD].frame_type) { + cmd_queues[SI91X_WLAN_CMD].command_in_flight = false; + cmd_queues[SI91X_WLAN_CMD].command_tickcount = 0; + cmd_queues[SI91X_WLAN_CMD].command_timeout = 0; + } + + // Add it to the WLAN event queue and set the WLAN notification event + sli_si91x_add_to_queue(&cmd_queues[SI91X_WLAN_CMD].event_queue, buffer); + set_async_event(NCP_HOST_WLAN_NOTIFICATION_EVENT); + } + break; + } + +#ifdef SLI_SI91X_ENABLE_BLE + case RSI_BT_Q: { + SL_DEBUG_LOG("Received BLE packet\n"); + // Increment the receive counter for the Bluetooth command + ++cmd_queues[SI91X_BT_CMD].rx_counter; + + if (frame_type == cmd_queues[SI91X_BT_CMD].frame_type) { + // Mark the command as not in flight and clear the frame_type + cmd_queues[SI91X_BT_CMD].command_in_flight = false; + cmd_queues[SI91X_BT_CMD].frame_type = 0; + } + + // Process the Bluetooth response data and free the buffer + rsi_driver_process_bt_resp_handler(data); + sl_si91x_host_free_buffer(buffer); + break; + } +#endif + default: { + // If the frame_type doesn't match any known cases + // Free the buffer + sl_si91x_host_free_buffer(buffer); + break; + } + } + sli_submit_rx_buffer(); + } else { + event &= ~SL_SI91X_NCP_HOST_BUS_RX_EVENT; // Reset the event flag + } + + if (event & SL_SI91X_ALL_TX_PENDING_COMMAND_EVENTS) { + // This condition is checked before writing frames to the bus + for (int i = 0; i < SI91X_CMD_MAX; i++) { + if (!(event & (SL_SI91X_TX_PENDING_FLAG(i)))) { + continue; + } + if (cmd_queues[i].command_in_flight == true) { + tx_command_queues_command_in_flight_status |= SL_SI91X_TX_PENDING_FLAG(i); + continue; + } else { + tx_command_queues_command_in_flight_status &= ~SL_SI91X_TX_PENDING_FLAG(i); + } + // Check if the bus is ready for a packet + if (!sli_si91x_is_bus_ready(global_queue_block)) { + break; + } + + bus_write_frame(&cmd_queues[i], i, SL_WIFI_CONTROL_BUFFER, &global_queue_block); + if (sli_si91x_buffer_queue_empty(&cmd_queues[i].tx_queue)) { + event &= ~SL_SI91X_TX_PENDING_FLAG(i); + tx_command_queues_status &= ~SL_SI91X_TX_PENDING_FLAG(i); + } + } + } + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK + if (tx_socket_command_queues_status & (~(tx_command_queues_command_in_flight_status))) { + for (int i = 0; i < NUMBER_OF_SOCKETS; i++) { + if (sli_si91x_sockets[i] != NULL + && !sli_si91x_buffer_queue_empty(&sli_si91x_sockets[i]->command_queue.tx_queue)) { + if (sli_si91x_sockets[i]->command_queue.command_in_flight == true) { + tx_socket_command_command_in_flight_queues_status |= (1 << i); + continue; + } else { + tx_socket_command_command_in_flight_queues_status &= ~(1 << i); + } + // Check if the bus is ready for a packet + if (!sli_si91x_is_bus_ready(global_queue_block)) { + break; + } + + // Send the socket specific command + bus_write_frame(&sli_si91x_sockets[i]->command_queue, + SI91X_SOCKET_CMD, + SL_WIFI_CONTROL_BUFFER, + &global_queue_block); + if (sli_si91x_buffer_queue_empty(&sli_si91x_sockets[i]->command_queue.tx_queue)) { + tx_socket_command_queues_status &= ~(1 << i); + } + } + } + // Clear the event flag for socket queues if there are no commands left + if (tx_socket_command_queues_status == 0) { + event &= ~SL_SI91X_SOCKET_COMMAND_TX_PENDING_EVENT; + } + } + + if (event & SL_SI91X_SOCKET_DATA_TX_PENDING_EVENT) { + bool all_socket_data_sent = true; + // Check each socket if it has something to send + for (int i = 0; i < NUMBER_OF_SOCKETS; ++i) { + if (sli_si91x_sockets[i] != NULL && !sli_si91x_buffer_queue_empty(&sli_si91x_sockets[i]->tx_data_queue)) { + all_socket_data_sent = false; + + // Check if the bus is ready for a packet + if (!sli_si91x_is_bus_ready(global_queue_block)) { + break; + } + + sl_status_t status = bus_write_data_frame(&sli_si91x_sockets[i]->tx_data_queue); + if (status == SL_STATUS_OK) { + --sli_si91x_sockets[i]->data_buffer_count; + } + if (sli_si91x_buffer_queue_empty(&sli_si91x_sockets[i]->tx_data_queue)) { + tx_socket_data_queues_status &= ~(1 << i); + } + } + } + + // Clear event bit if we confirmed no more packets to send + if (all_socket_data_sent) { + event &= ~SL_SI91X_SOCKET_DATA_TX_PENDING_EVENT; + } + } +#endif + if (event & SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT) { + // Check if the bus is ready for a packet + sl_si91x_bus_read_interrupt_status(&interrupt_status); + if (!(interrupt_status & RSI_BUFFER_FULL)) { + bus_write_data_frame(&sli_tx_data_queue); + if (sli_si91x_buffer_queue_empty(&sli_tx_data_queue)) { + event &= ~SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT; + tx_generic_socket_data_queues_status &= ~(SL_SI91X_GENERIC_DATA_TX_PENDING_EVENT); + } + } +#ifdef SLI_SI91X_MCU_INTERFACE + else { + unmask_ta_interrupt(TA_RSI_BUFFER_FULL_CLEAR_EVENT); + } +#endif + } + if (event & SL_SI91X_TERMINATE_BUS_THREAD_EVENT) { + // Clear the termination event flag + event &= ~SL_SI91X_TERMINATE_BUS_THREAD_EVENT; + + // Acknowledge the termination request + osEventFlagsSet(si91x_events, SL_SI91X_TERMINATE_BUS_THREAD_EVENT_ACK); + + // Terminate the current thread + osThreadTerminate(osThreadGetId()); + } + } + //To suppress warning unused parameter, no code effect + UNUSED_PARAMETER(event); +} + +static sl_status_t bus_write_frame(sli_si91x_command_queue_t *queue, + sl_si91x_command_type_t command_type, + sl_wifi_buffer_type_t buffer_type, + bool *global_queue_block) +{ + UNUSED_PARAMETER(buffer_type); + UNUSED_PARAMETER(command_type); + sl_status_t status; + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + sli_si91x_queue_packet_t *node = NULL; + + if ((current_performance_profile != HIGH_PERFORMANCE) && (si91x_req_wakeup() != SL_STATUS_OK)) { + return SL_STATUS_TIMEOUT; + } + + status = sli_si91x_remove_from_queue(&queue->tx_queue, &buffer); + if (status != SL_STATUS_OK) { + if (current_performance_profile != HIGH_PERFORMANCE) { + sl_si91x_host_clear_sleep_indicator(); + } + VERIFY_STATUS_AND_RETURN(status); + } + + node = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + packet = sl_si91x_host_get_buffer_data(node->host_packet, 0, NULL); + uint16_t length = packet->length; + + // Modify the packet's descriptor to include the firmware queue ID in the length field + packet->desc[1] |= (node->firmware_queue_id << 4); + + if (packet->command) { + // Set the global_queue_block flag if it is present in the packet's flags + if (SI91X_PACKET_GLOBAL_QUEUE_BLOCK & node->flags) { + *global_queue_block = true; + } + + if (SI91X_PACKET_WITH_ASYNC_RESPONSE != (node->flags & SI91X_PACKET_WITH_ASYNC_RESPONSE)) { + // Update trace information with packet details + // If the packet doesn't have an async response, mark the command as in flight + queue->command_in_flight = true; + queue->packet_id = node->host_packet->id; + queue->firmware_queue_id = node->firmware_queue_id; + queue->frame_type = packet->command; + queue->flags = node->flags; + queue->command_timeout = node->command_timeout; + queue->command_tickcount = node->command_tickcount; + queue->sdk_context = node->sdk_context; + } + } +#ifdef SLI_SI91X_MCU_INTERFACE + if ((packet->command == RSI_COMMON_RSP_TA_M4_COMMANDS) || (packet->command == RSI_WLAN_REQ_SET_CERTIFICATE)) { + // set flag + sli_si91x_update_flash_command_status(true); + } +#endif + // Write the frame to the bus using packet data and length + status = sl_si91x_bus_write_frame(packet, packet->data, length); + +#ifdef SLI_SI91X_MCU_INTERFACE + if (packet->desc[2] == RSI_COMMON_REQ_SOFT_RESET) { + sli_si91x_config_m4_dma_desc_on_reset(); + } +#endif + + // Handle errors during frame writing + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n BUS_WRITE_ERROR \r\n"); + BREAKPOINT(); + } + + SL_DEBUG_LOG("<>>>> Tx -> queueId : %u, frameId : 0x%x, length : %u\n", + node->firmware_queue_id, + packet->command, + length); + + if (current_performance_profile != HIGH_PERFORMANCE) { + sl_si91x_host_clear_sleep_indicator(); + } + +#ifdef SLI_SI91X_ENABLE_BLE + if (command_type == SI91X_BT_CMD) { + rsi_bt_common_tx_done(packet); + } +#endif + + sl_si91x_host_free_buffer(node->host_packet); + sl_si91x_host_free_buffer(buffer); + + queue->tx_counter++; + return SL_STATUS_OK; +} + +// This function is called for writing data +static sl_status_t bus_write_data_frame(sl_si91x_buffer_queue_t *queue) +{ + sl_status_t status; + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + + if ((current_performance_profile != HIGH_PERFORMANCE) && (si91x_req_wakeup() != SL_STATUS_OK)) { + return SL_STATUS_TIMEOUT; + } + + status = sli_si91x_remove_from_queue(queue, &buffer); + if (status != SL_STATUS_OK) { + if (current_performance_profile != HIGH_PERFORMANCE) { + sl_si91x_host_clear_sleep_indicator(); + } + VERIFY_STATUS_AND_RETURN(status); + } + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + uint16_t length = packet->length; + + // Modify the packet's descriptor to include the firmware queue ID in the length field + packet->desc[1] |= (5 << 4); + + // Write the frame to the bus using packet data and length + status = sl_si91x_bus_write_frame(packet, packet->data, length); + + // Handle errors during frame writing + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\n BUS_WRITE_ERROR \r\n"); + BREAKPOINT(); + } + + SL_DEBUG_LOG("<>>>> Tx -> queueId : %u, frameId : 0x%x, length : %u\n", 5, 0, length); + + if (current_performance_profile != HIGH_PERFORMANCE) { + sl_si91x_host_clear_sleep_indicator(); + } + + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +static void set_async_event(uint32_t event_mask) +{ + osEventFlagsSet(si91x_async_events, event_mask); +} + +// Function to check if the bus is ready for writing +bool sli_si91x_is_bus_ready(bool global_queue_block) +{ + if (global_queue_block) { + return false; + } + uint16_t interrupt_status = 0; + sl_si91x_bus_read_interrupt_status(&interrupt_status); + if (interrupt_status & RSI_BUFFER_FULL) { +#ifdef SLI_SI91X_MCU_INTERFACE + unmask_ta_interrupt(TA_RSI_BUFFER_FULL_CLEAR_EVENT); +#endif + return false; + } + return true; +} + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +static sli_si91x_socket_t *get_socket_from_packet(sl_si91x_packet_t *socket_packet) +{ + int socket_id = sli_si91x_get_socket_id(socket_packet); + + if (socket_packet->command == RSI_WLAN_RSP_CONN_ESTABLISH) { + socket_packet->command = RSI_WLAN_RSP_SOCKET_ACCEPT; + } + + if (socket_packet->command == RSI_WLAN_RSP_SOCKET_CREATE) { + sl_si91x_socket_create_response_t *socket_create_response = + ((sl_si91x_socket_create_response_t *)socket_packet->data); + return sli_si91x_get_socket_from_id( + -1, + RESET, + (int16_t)(socket_create_response->socket_type[0] | (socket_create_response->socket_type[1] << 8))); + } else if (socket_packet->command == RSI_WLAN_RSP_SOCKET_ACCEPT) { + const sli_si91x_socket_t *si91x_socket = sli_si91x_get_socket_from_id(socket_id, RESET, -1); + return get_si91x_socket(si91x_socket->client_id); + } else if (socket_packet->command == RSI_WLAN_RSP_SOCKET_CLOSE) { + return sli_si91x_get_socket_from_id(socket_id, RESET, -1); + } else { + return sli_si91x_get_socket_from_id(socket_id, LISTEN, -1); + } +} +#endif diff --git a/wiseconnect/components/protocol/wifi/inc/sl_wifi.h b/wiseconnect/components/protocol/wifi/inc/sl_wifi.h new file mode 100644 index 000000000..c4633daa2 --- /dev/null +++ b/wiseconnect/components/protocol/wifi/inc/sl_wifi.h @@ -0,0 +1,1605 @@ +/***************************************************************************/ /** + * @file + * @brief SL Wi-Fi API + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once +#include "sl_wifi_device.h" +#include "sl_wifi_types.h" +#include "sl_wifi_host_interface.h" +#include +#include + +/// Default Wi-Fi scan configuration +extern const sl_wifi_scan_configuration_t default_wifi_scan_configuration; + +/// Default Wi-Fi AP configuration +extern const sl_wifi_ap_configuration_t default_wifi_ap_configuration; + +/** \addtogroup WIFI_COMMON_API Common + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * This function initializes the Wi-Fi module using the specified device configuration, + * device context, and event handler. It configures the Wi-Fi device and establishes + * the event handler for Wi-Fi events. This function must be called before using any + * other Wi-Fi functions. + * @param[in] configuration + * [sl_wifi_device_configuration_t](../wiseconnect-api-reference-guide-si91x-driver/sl-wifi-device-configuration-t) object that contains Wi-Fi device configuration. + * @param[in] device_context + * Reserved for future use. + * @param[in] event_handler + * Wi-Fi event handler function of type @ref sl_wifi_event_handler_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This function should be called before calling any other sl_wifi functions. + ******************************************************************************/ +sl_status_t sl_wifi_init(const sl_wifi_device_configuration_t *configuration, + sl_wifi_device_context_t *device_context, + sl_wifi_event_handler_t event_handler); + +/***************************************************************************/ /** + * @brief + * This function ensures proper shutdown of the Wi-Fi driver, resetting configurations and releasing resources. + * Call this API to deinitialize the Wi-Fi module to avoid resource leaks + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_deinit(void); + +/***************************************************************************/ /** + * @brief + * Check if Wi-Fi interface is up. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @return + * 1. true: interface is up. + * 2. false: interface is down. + ******************************************************************************/ +bool sl_wifi_is_interface_up(sl_wifi_interface_t interface); + +/***************************************************************************/ /** + * @brief + * Return the firmware version running on the Wi-Fi device. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] version + * @ref sl_wifi_firmware_version_t object that contains the version string. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * Moving forward, this API will be deprecated. Instead, please use the [sl_si91x_get_firmware_version](../wiseconnect-api-reference-guide-si91x-driver/si91-x-driver-functions#sl-si91x-get-firmware-version) API. + ******************************************************************************/ +sl_status_t sl_wifi_get_firmware_version(sl_wifi_firmware_version_t *version); + +/***************************************************************************/ /** + * @brief + * Gets wlan info in AP mode / Client mode. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] info + * [sl_si91x_rsp_wireless_info_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-rsp-wireless-info-t) object that contains the wlan info. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_wireless_info(sl_si91x_rsp_wireless_info_t *info); + +/***************************************************************************/ /** + * @brief + * Return the firmware image size from firmware image. + * @param[in] buffer + * Buffer pointing to firmware image file. + * @param[out] fw_image_size + * Size of the firmware image passed in the input buffer param. The value returned in this param is valid only if this API returns SL_STATUS_OK(0). + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * Moving forward, this API will be deprecated. Instead, please use the [sl_si91x_get_firmware_size](../wiseconnect-api-reference-guide-si91x-driver/si91-x-driver-functions#sl-si91x-get-firmware-size) API. + ******************************************************************************/ +sl_status_t sl_wifi_get_firmware_size(void *buffer, uint32_t *fw_image_size); + +/***************************************************************************/ /** + * @brief + * Set the default Wi-Fi interface as supported by @ref sl_wifi_interface_t. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + ******************************************************************************/ +void sl_wifi_set_default_interface(sl_wifi_interface_t interface); + +/***************************************************************************/ /** + * @brief + * Get the default interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @return + * @ref sl_wifi_interface_t previously set by @ref sl_wifi_set_default_interface + ******************************************************************************/ +sl_wifi_interface_t sl_wifi_get_default_interface(void); + +/***************************************************************************/ /** + * @brief + * Retrieves the MAC addresses of the specified Wi-Fi interface, in concurrent mode retrieves two MAC addresses. + * @details + * MAC address of the module. In concurrent mode, two MAC addresses are returned, MAC_Address1 is the station MAC + * address and MAC_Address2 is the created AP MAC address. MAC address is returned in 6-bytes in hex format. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] mac + * [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t) object that contains the MAC address of the interface. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_mac_address(sl_wifi_interface_t interface, sl_mac_address_t *mac); + +/***************************************************************************/ /** + * @brief + * Set the Wi-Fi interface MAC address. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] mac + * [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t) object to store the MAC address. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not supported by Si917 when called directly due to firmware constraints. + * Alternatively, @ref sl_wifi_init can be used to configure the MAC address. sl_wifi_init ensures the appropriate state of firmware and calls this API to set MAC address. + ******************************************************************************/ +sl_status_t sl_wifi_set_mac_address(sl_wifi_interface_t interface, const sl_mac_address_t *mac); + +/** @} */ + +/** \addtogroup WIFI_RADIO_API Radio + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ + +// Radio management functions + +/***************************************************************************/ /** + * @brief + * Get the maximum Wi-Fi transmit power. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] max_tx_power + * A variable that contains current maximum transmit power as identified by by @ref sl_wifi_max_tx_power_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This function gets the transmit power for a particular radio interface: SL_WIFI_2_4GHZ_INTERFACE. + ******************************************************************************/ +sl_status_t sl_wifi_get_max_tx_power(sl_wifi_interface_t interface, sl_wifi_max_tx_power_t *max_tx_power); + +/***************************************************************************/ /** + * @brief + * Set the maximum Wi-Fi transmit power. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] max_tx_power + * Max transmission power as identified by @ref sl_wifi_max_tx_power_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This function sets the transmit power for a particular radio interface: SL_WIFI_2_4GHZ_INTERFACE. + * Eg: Setting transmit power for client interface at 2.4 GHz will also set transmit power of the AP interface at 2.4 GHz. + * @note + * The effective transmit power is subject to regional and device limitations. If the specified transmit power exceeds the + * maximum supported value for that region, the transmission will occur at the maximum supported transmit power. + ******************************************************************************/ +sl_status_t sl_wifi_set_max_tx_power(sl_wifi_interface_t interface, sl_wifi_max_tx_power_t max_tx_power); + +/***************************************************************************/ /** + * @brief + * Set the Wi-Fi antenna for an interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] antenna + * Antenna to select as identified by @ref sl_wifi_antenna_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_set_antenna(sl_wifi_interface_t interface, sl_wifi_antenna_t antenna); + +/***************************************************************************/ /** + * @brief + * Get the Wi-Fi antenna for an interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] antenna + * @ref sl_wifi_antenna_t object that contains current antenna selection. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_antenna(sl_wifi_interface_t interface, sl_wifi_antenna_t *antenna); + +/***************************************************************************/ /** + * @brief + * Get the current channel for the given Wi-Fi interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] channel + * @ref sl_wifi_channel_t object that contains current channel information. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_channel(sl_wifi_interface_t interface, sl_wifi_channel_t *channel); + +/***************************************************************************/ /** + * @brief + * Set the channel for the given Wi-Fi Access Point interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] channel + * Channel as identified by @ref sl_wifi_channel_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_set_channel(sl_wifi_interface_t interface, sl_wifi_channel_t channel); + +/***************************************************************************/ /** + * @brief + * Set the Wi-Fi transmit rate for the given 802.11 protocol on the specified Wi-Fi interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * - + * In AP mode, this API should be called before sl_net_wifi_ap_up. This configured data rate will be passed as part of the AP configuration while bringing up the AP interface. + * - + * In Wi-Fi client mode, this API should be called after @ref sl_wifi_connect. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] rate_protocol + * 802.11 protocol as identified by @ref sl_wifi_rate_protocol_t + * @param[in] mask + * Data rate as identified by @ref sl_wifi_rate_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * Only 1 and 2 Mbps rates are allowed in channel 14. + ******************************************************************************/ +sl_status_t sl_wifi_set_transmit_rate(sl_wifi_interface_t interface, + sl_wifi_rate_protocol_t rate_protocol, + sl_wifi_rate_t mask); + +/***************************************************************************/ /** + * @brief + * Get the Wi-Fi transmit rate for the given 802.11 protocol on the specified Wi-Fi interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] rate_protocol + * 802.11 protocol as identified by @ref sl_wifi_rate_protocol_t + * @param[out] mask + * Data rate as identified by @ref sl_wifi_rate_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_transmit_rate(sl_wifi_interface_t interface, + sl_wifi_rate_protocol_t *rate_protocol, + sl_wifi_rate_t *mask); + +/***************************************************************************/ /** + * @brief + * Set the Wi-Fi client interface listen interval. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] listen_interval + * @ref sl_wifi_listen_interval_t object + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * By default listen interval is set 1000 millisecs. User can call this API to overwrite the value. + * Si91X implementation allows this API ONLY to be called before calling @ref sl_wifi_connect(), @ref sl_wifi_start_ap(), @ref sl_wifi_start_wps() + ******************************************************************************/ +sl_status_t sl_wifi_set_listen_interval(sl_wifi_interface_t interface, sl_wifi_listen_interval_t listen_interval); + +/***************************************************************************/ /** + * @brief + * Get the Wi-Fi client listen interval. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] listen_interval + * @ref sl_wifi_listen_interval_t object that will contain the current listen interval. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note +* By default, the listen interval is set to 1000 millisecs. + ******************************************************************************/ +sl_status_t sl_wifi_get_listen_interval(sl_wifi_interface_t interface, sl_wifi_listen_interval_t *listen_interval); + +/***************************************************************************/ /** + * @brief + * Assign the user configurable channel gain values in different regions to the module from user. + * @pre Pre-conditions: + * - + * This method is used for overwriting default gain tables that are present in firmware. + * @pre Pre-conditions: + * - + * Customer can load gain tables for 2.4 GHz-20 MHz. + * @pre Pre-conditions: + * - + * This is a blocking API. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] band + * 1 - 2.4 GHz + * @param[in] bandwidth + * 0 - 20 MHz + * @param[in] payload + * Pass channel gain values for different regions in a given array format. + * @param[in] payload_len + * Max payload length (table size) in 2.4 GHz is 128 bytes. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * 1. This frame must be used only by customers who have done FCC/ETSI/TELEC/KCC certification with their own antenna. Silicon Labs is not liable for inappropriate usage of this frame that may result in violation of FCC/ETSI/TELEC/KCC or any certifications. + * 2. Internally, firmware maintains two tables: Worldwide table & Region-based table. Worldwide table is populated by the firmware with max power values that the chip can transmit and meet target specs like EVM. Region-based table has a default gain value set. + * 3. When certifying with user antenna, the Region has to be set to Worldwide and sweep the power from 0 to 21 dBm. Arrive at a max power level that will pass certifications, especially band-edge. + * 4. The FCC/ETSI/TELEC/KCC max power level should be loaded in an end-to-end mode via WLAN User Gain table. This has to be called done for every boot-up as this information is not saved inside the flash. Region-based user gain table sent by the application is copied onto the Region-based table. SoC uses this table in FCC/ETSI/TELEC/KCC to limit the power and to not violate the allowed limits. + * 5. For Worldwide region, the firmware uses the Worldwide table for Tx. For other regions (FCC/ETSI/TELEC/KCC), the firmware uses the min value out of the Worldwide & Region-based table for Tx. Also, there will be part to part variation across the chips. Offsets that are estimated during the flow of manufacture will be applied as correction factor during normal mode of operation. + * 6. In a 2.4 GHz band, 40 MHz is not supported. + * 7. Executing this API will overwrite calibration values in certified modules. + * 8. In FCC-certified modules, this API will trigger an error SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE if used, except when in SL_SI91X_TRANSMIT_TEST_MODE mode. + ******************************************************************************/ +sl_status_t sl_wifi_update_gain_table(uint8_t band, uint8_t bandwidth, uint8_t *payload, uint16_t payload_len); + +/***************************************************************************/ /** + * @brief + * Configure the 11ax params. This is a blocking API. + * @pre Pre-conditions: + * - + * This API should be called before @ref sl_wifi_connect + * @param[in] guard_interval + * Period of time delta between two packets in wireless transmission. Valid values : 0 - 3 (0 = 8 us, 1 = 16 us, 2 = 32 us, 3 = 64 us). + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_set_11ax_config(uint8_t guard_interval); + +/** @} */ + +/** \addtogroup WIFI_SCANNING_API Scanning + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ + +// Scanning functions +/***************************************************************************/ /** + * @brief + * Initiates a Wi-Fi scan operation on the specified interface, supporting advanced and background scan types. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] optional_ssid + * Optional SSID of type @ref sl_wifi_ssid_t can be used to scan for a particular Wi-Fi network + * @param[in] configuration + * @ref sl_wifi_scan_configuration_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * For 911x, advanced scan results are not populated to user. + * Default Active Channel time is 100 milliseconds. If the user wants to modify the time, + * sl_wifi_set_advanced_scan_configuration can be called. If the scan_type is not ADV_SCAN, then + * the time is for foreground scan. Otherwise, it is used for background scanning. + * If the user wants to enable Passive Scanning, user should set the scan_type to SL_WIFI_SCAN_TYPE_PASSIVE. + * If the user wants to enable Low Power (LP) mode in Passive Scan, user should enable lp_mode in sl_wifi_scan_configuration_t. + * The default channel time for passive scanning is set to 400 milliseconds. If user wants to modify the time, users can call the sl_si91x_set_timeout API to modify the time as per their requirements. + * Use the SL_WIFI_SCAN_TYPE_EXTENDED to obtain the scan results that exceed the SL_WIFI_MAX_SCANNED_AP. In this scan type, the number of scan results is not restricted; it is only limited by the amount of dynamic memory that the host can provide. + * Default Passive Scan Channel time is 400 milliseconds. If the user wants to modify the time, sl_si91x_set_timeout can be called. + * In case of SL_WIFI_SCAN_TYPE_EXTENDED scan type, use @ref sl_wifi_get_stored_scan_results() API to get the scan results; after the scan status callback is received. + * This API is not applicable for ADV_SCAN scan_type in AP mode + * AP scan is supported - to trigger this, send a scan after sl_wifi_start_ap() API with the SL_WIFI_SCAN_TYPE_ACTIVE scan_type. + ******************************************************************************/ +sl_status_t sl_wifi_start_scan(sl_wifi_interface_t interface, + const sl_wifi_ssid_t *optional_ssid, + const sl_wifi_scan_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Returns the stored scan results of a detailed scan in the user provided scan results array. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in out] extended_scan_parameters + * A pointer to a structure of type @ref sl_wifi_extended_scan_result_parameters_t, where the scan results will be stored. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/4.1/common/api/group-status for details. + * @note + * This API will only hold scan results if sl_wifi_start_scan is called with scan type as SL_WIFI_SCAN_TYPE_EXTENDED. + * These results are stored until another call to sl_wifi_start_scan is made with scan type as SL_WIFI_SCAN_TYPE_EXTENDED. + ******************************************************************************/ +sl_status_t sl_wifi_get_stored_scan_results(sl_wifi_interface_t interface, + sl_wifi_extended_scan_result_parameters_t *extended_scan_parameters); + +/***************************************************************************/ /** + * @brief + * Stops an ongoing Wi-Fi scan operation on the specified interface, including background scanning. + * @pre Pre-conditions: + * This API is applicable only for client interface. + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * For 911x, sl_wifi_stop_scan is ONLY supported for advanced scan. + ******************************************************************************/ +sl_status_t sl_wifi_stop_scan(sl_wifi_interface_t interface); + +/***************************************************************************/ /** + * @brief + * Configures advanced scan settings for a Wi-Fi interface and enables instant scan capability. + * @details + * @ref sl_wifi_advanced_scan_configuration_t object that will contain the advanced scan configuration. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] configuration + * Set advanced scan configuration as identified by @ref sl_wifi_advanced_scan_configuration_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * Advance scan is not applicable in AP mode. + ******************************************************************************/ +sl_status_t sl_wifi_set_advanced_scan_configuration(const sl_wifi_advanced_scan_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Retrieves the current advanced scan configuration parameters from the Wi-Fi interface. + * @details + * This function should be used after successful Wi-Fi connection. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] configuration + * @ref sl_wifi_advanced_scan_configuration_t object that will contain the current advanced scan configuration. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_advanced_scan_configuration(sl_wifi_advanced_scan_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Wait for current scan to complete and store the results in the provided array. + * @pre Pre-conditions: + * - + * This function also returns when the scan result array is full. + * @pre Pre-conditions: + * - + * Once the scan result array is full, any further scan results will be lost. + * @param[in] scan_result_array + * Array of @ref sl_wifi_scan_result_t objects to store the scan results. + * @param[in] max_scan_result_count + * The maximum number of scan result objects that can fit in the scan result array. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not supported in the current release. + ******************************************************************************/ +sl_status_t sl_wifi_wait_for_scan_results(sl_wifi_scan_result_t **scan_result_array, uint32_t max_scan_result_count); + +/** @} */ + +/** \addtogroup WIFI_CLIENT_API Client + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ +// Wi-Fi Client functions + +/***************************************************************************/ /** + * @brief + * Connect to the given Wi-Fi AP. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi client interface as identified by @ref sl_wifi_interface_t + * @param[in] access_point + * @ref sl_wifi_client_configuration_t object that contains the Access Point details. + * @param[in] timeout_ms + * Timeout value in milliseconds. The function will abort and return when the timeout timer expires. + * A value of 0 indicates an asynchronous action. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * If channel, band, and BSSID are provided, this API will attempt to connect without scanning. + * If security_type is SL_WIFI_WPA3/SL_WIFI_WPA3_ENTERPRISE then SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED join feature is enabled internally by SDK. + * If security_type is SL_WIFI_WPA3_TRANSITION/SL_WIFI_WPA3_TRANSITION_ENTERPRISE then SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED join feature is disabled and SL_SI91X_JOIN_FEAT_MFP_CAPABLE_ONLY join feature is enabled internally by SDK. + * Default Active Channel time is 100 milliseconds. If the user wants to modify the time, sl_wifi_set_advanced_scan_configuration can be called. + * Default Authentication timeout and Association timeout is 300 milliseconds. If the user wants to modify the time, sl_wifi_set_advanced_client_configuration can be called. + * Default Keep Alive timeout is 30 milliseconds. If the user wants to modify the time, sl_wifi_set_advanced_client_configuration can be called. + * @note + * In FCC certified module the behavior is as follows + * 1. Region configuration is not supported and if triggered will return error SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE. + * 2. STA mode channels 1 to 11 are actively scanned and 12,13,14 are passively scanned. + * 3. Concurrent mode supports only 1 to 11 channels. + ******************************************************************************/ +sl_status_t sl_wifi_connect(sl_wifi_interface_t interface, + const sl_wifi_client_configuration_t *access_point, + uint32_t timeout_ms); + +/***************************************************************************/ /** + * @brief + * Disconnect the Wi-Fi client interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_connect should be called before this API. + * @param[in] interface + * Wi-Fi client interface as identified by @ref sl_wifi_interface_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_disconnect(sl_wifi_interface_t interface); + +/***************************************************************************/ /** + * @brief + * Retrieve the RSSI value of the Access Point to which the Wi-Fi client is connected. + * @pre Pre-conditions: + * - + * @ref sl_wifi_connect should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] rssi + * signal strength (RSSI) in dBm. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_signal_strength(sl_wifi_interface_t interface, int32_t *rssi); + +/***************************************************************************/ /** + * @brief + * Get the station Timing Synchronization Function (TSF) time which is synchronised with connected AP beacon TSF. + * @pre + * Pre-condition: @ref sl_wifi_connect should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] tsf + * 64-bit TSF time in microseconds stored in @ref sl_wifi_tsf64_t structure. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API returns an error if the station is not connected to an Access Point or at least one beacon is not received. + ******************************************************************************/ +sl_status_t sl_wifi_get_sta_tsf(sl_wifi_interface_t interface, sl_wifi_tsf64_t *tsf); + +/***************************************************************************/ /** + * @brief + * Set the Wi-Fi roaming configuration. + * @pre Pre-conditions: + * - + * @ref sl_wifi_set_advanced_scan_configuration should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] roam_configuration + * @ref sl_wifi_roam_configuration_t object to store Wi-Fi roaming configuration. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * For si91x chips, following ranges are valid: + * trigger_level: [-10, -100] , + * trigger_level_change: [0, 90] + ******************************************************************************/ +sl_status_t sl_wifi_set_roam_configuration(sl_wifi_interface_t interface, + sl_wifi_roam_configuration_t *roam_configuration); + +/***************************************************************************/ /** + * @brief + * Get the Wi-Fi roaming configuration. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] roam_configuration + * @ref sl_wifi_roam_configuration_t object that will contain the current roam configuration. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_get_roam_configuration(sl_wifi_interface_t interface, + sl_wifi_roam_configuration_t *roam_configuration); + +/***************************************************************************/ /** + * @brief + * Verify the Wi-Fi client configuration is valid and available. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] ap + * @ref sl_wifi_client_configuration_t object that contains the details of Access Point. + * @param[in] timeout_ms + * Timeout value in milliseconds. The function will abort and return when the timeout timer expires. + * A timeout value of 0 means the function will initiate the verification process and return immediately, without waiting for the process to complete. This indicates that the action will be handled asynchronously. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_test_client_configuration(sl_wifi_interface_t interface, + const sl_wifi_client_configuration_t *ap, + uint32_t timeout_ms); + +/***************************************************************************/ /** + * @brief + * Load the certificate into the device. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] certificate_type + * Certificate type being set + * @param[in] buffer + * Pointer to buffer containing the certificate. + * @param[in] certificate_length + * Length of certificate buffer data. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_set_certificate(uint8_t certificate_type, const uint8_t *buffer, uint32_t certificate_length); + +/***************************************************************************/ /** + * @brief + * Load the certificate into the device. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] certificate_type + * Certificate type being set. + * @param[in] certificate_index + * Certificate to be loaded in specified index. + * @param[in] buffer + * Pointer to buffer containing the certificate. + * @param[in] certificate_length + * Length of certificate buffer data. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_set_certificate_with_index(uint8_t certificate_type, + uint8_t certificate_index, + uint8_t *buffer, + uint32_t certificate_length); + +/***************************************************************************/ /** +* Set the advanced configuration options of a client interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. +* @param[in] interface +* Wi-Fi interface as identified by @ref sl_wifi_interface_t +* @param[in] configuration +* Wi-Fi client advanced configuration. See @ref sl_wifi_advanced_client_configuration_t +* @return +* sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. +******************************************************************************/ +sl_status_t sl_wifi_set_advanced_client_configuration(sl_wifi_interface_t interface, + const sl_wifi_advanced_client_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Send raw data frame. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] data + * Data buffer. + * @param[in] data_length + * length of the data. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_send_raw_data_frame(sl_wifi_interface_t interface, const void *data, uint16_t data_length); + +/***************************************************************************/ /** + * @brief + * Configure TWT parameters. Enables a TWT session. This is blocking API. + * @pre Pre-conditions: + * - + * @ref sl_wifi_connect should be called before this API. + * @param[in] twt_req + * Configurable TWT parameters specified in @ref sl_wifi_twt_request_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_enable_target_wake_time(sl_wifi_twt_request_t *twt_req); + +/***************************************************************************/ /** + * @brief + * Configure TWT parameters. Disables a TWT session. This is blocking API. + * @pre Pre-conditions: + * - + * @ref sl_wifi_enable_target_wake_time should be called before this API. + * @param[in] twt_req + * Configurable TWT parameters specified in @ref sl_wifi_twt_request_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_disable_target_wake_time(sl_wifi_twt_request_t *twt_req); + +/***************************************************************************/ /** + * @brief + * Calculates and configures TWT parameters based on the given inputs. Enables or disables a TWT session. This is blocking API. + * @pre Pre-conditions: + * - + * @ref sl_wifi_connect should be called before this API. + * @param[in] twt_selection_req + * @ref sl_wifi_twt_selection_t object containing configurable TWT selection parameters. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_target_wake_time_auto_selection(sl_wifi_twt_selection_t *twt_selection_req); + +/***************************************************************************/ /** + * @brief + * Suspends the TWT agreement corresponding to given flow id and resumes it when suspend duration expires. + * This API performs the following actions on TWT agreement: SL_WIFI_SUSPEND_INDEFINITELY, SL_WIFI_RESUME_IMMEDIATELY, SL_WIFI_SUSPEND_FOR_DURATION. + * @note + * The reschedule TWT actions are valid till the end of current TWT agreement. If the TWT agreement is terminated + * (TWT tear down or WLAN disconnection), these actions are not retained. + * To reapply these actions upon new TWT agreement, the user must re-issue the command. + * @pre Pre-conditions: + * - + * @ref sl_wifi_connect should be called before this API. + * @param[in] flow_id + * Flow id of the twt agreement. + * @param[in] twt_action + * @ref sl_wifi_reschedule_twt_action_t specifying different actions that can be taken in relation to rescheduling TWT. + * @param[in] suspend_duration + * Time interval until which twt agreement is suspended, value taken in milliseconds. + * ## The table below outlines the valid values for TWT actions and their corresponding suspend durations: + * | twt_action | Valid values for suspend duration | + * | -------------------- | --------------------------------- | + * | SL_WIFI_SUSPEND_INDEFINITELY | 0 | + * | SL_WIFI_RESUME_IMMEDIATELY | 0 | + * | SL_WIFI_SUSPEND_FOR_DURATION | 1 to 86400000 | + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_reschedule_twt(uint8_t flow_id, + sl_wifi_reschedule_twt_action_t twt_action, + uint64_t suspend_duration); + +/***************************************************************************/ /** + * @brief + * Send Filter Broadcast Request frame. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] beacon_drop_threshold + * The amount of time that FW waits to receive full beacon. Default value is 5000 ms. + * @param[in] filter_bcast_in_tim + * If this bit is set, then from the next dtim any broadcast data pending bit in TIM indicated will be ignored valid values: 0 - 1. + * @param[in] filter_bcast_tim_till_next_cmd + * 0 - filter_bcast_in_tim is valid till disconnect of the STA. + * 1 - filter_bcast_in_tim is valid till next update by giving the same command. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_filter_broadcast(uint16_t beacon_drop_threshold, + uint8_t filter_bcast_in_tim, + uint8_t filter_bcast_tim_till_next_cmd); + +/***************************************************************************/ /** + * @brief + * Generate PMK if PSK and SSID are provided. This is a blocking API. + * @pre Pre-conditions: + * - + * This API should be called after @ref sl_wifi_init and called before @ref sl_wifi_connect. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] type + * Possible values of this field are 1, 2, and 3, but we only pass 3 for generation of PMK. + * @param[in] ssid + * SSID of type @ref sl_wifi_ssid_t has the SSID of the access point + * @param[in] pre_shared_key + * Expected parameters are pre-shared key(PSK) of the access point + * @param[in] pairwise_master_key + * PMK array + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_pairwise_master_key(sl_wifi_interface_t interface, + const uint8_t type, + const sl_wifi_ssid_t *ssid, + const char *pre_shared_key, + uint8_t *pairwise_master_key); + +/***************************************************************************/ /** + * @brief + * Configure multicast filter parameters. This is a blocking API. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] multicast_filter_info + * Configurable multicast filter parameters specified in @ref sl_wifi_multicast_filter_info_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_configure_multicast_filter(sl_wifi_multicast_filter_info_t *multicast_filter_info); + +/** @} */ + +/** \addtogroup WIFI_AP_API Access Point + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ +// Access point functions + +/***************************************************************************/ /** + * @brief + * Start a Wi-Fi access point (AP) interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] configuration + * Wi-Fi AP configuration. See @ref sl_wifi_ap_configuration_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * For AP mode with WPA3 security, only SAE-H2E method is supported. SAE hunting and pecking method is not supported. + * TKIP encryption mode is not supported. Encryption mode is automatically configured to RSI_CCMP. + * PMKSA is not supported in WPA3 AP mode. + * @note + * In FCC-certified modules, + * 1. Region configuration is not supported and if triggered will return error SL_STATUS_SI91X_FEATURE_NOT_AVAILABLE. + * 2. AP supports only 1 to 11 channels. + * 3. AP will not advertise the Country IE. + ******************************************************************************/ +sl_status_t sl_wifi_start_ap(sl_wifi_interface_t interface, const sl_wifi_ap_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Reconfigure the dynamic parameters of a Wi-Fi access point (AP) interface. + * @pre + * @ref sl_wifi_start_ap should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] config + * Wi-Fi AP dynamic configuration. See @ref sl_si91x_ap_reconfiguration_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * The access point continues to transmit beacons when a client is connected, regardless of the beacon_stop configuration. + ******************************************************************************/ +sl_status_t sl_wifi_reconfigure_ap(sl_wifi_interface_t interface, sl_si91x_ap_reconfiguration_t config); + +/***************************************************************************/ /** + * @brief + * Set the configuration of a running Wi-Fi access point (AP). + * If the new configuration modifies vital settings such as SSID or security, the AP will be stopped and restarted automatically. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] configuration + * Wi-Fi AP configuration. See @ref sl_wifi_ap_configuration_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_set_ap_configuration(sl_wifi_interface_t interface, + const sl_wifi_ap_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Get the configuration of a Wi-Fi AP interface. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] configuration + * @ref sl_wifi_ap_configuration_t object that contains the AP configuration. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_ap_configuration(sl_wifi_interface_t interface, sl_wifi_ap_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Set the advanced configuration options of a running Wi-Fi access point (AP). + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] configuration + * Wi-Fi AP advanced configuration. See @ref sl_wifi_advanced_ap_configuration_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_set_advanced_ap_configuration(sl_wifi_interface_t interface, + const sl_wifi_advanced_ap_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Get the advanced configuration options of a running Wi-Fi access point interface. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] configuration + * @ref sl_wifi_advanced_ap_configuration_t object that will contain the AP advanced configuration. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_get_advanced_ap_configuration(sl_wifi_interface_t interface, + const sl_wifi_advanced_ap_configuration_t *configuration); + +/***************************************************************************/ /** + * @brief + * Stop Wi-Fi access point. + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_ap should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_stop_ap(sl_wifi_interface_t interface); + +/***************************************************************************/ /** + * @brief + * Disconnects a client with the specified MAC address from Access Point (AP). + * @details + * Use this function to disassociate (disconnect) a client from Access Point. + * This API is used when the device is in AP mode. + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_ap should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @param[in] mac + * Wi-Fi client's MAC address of type [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t) + * @param[in] reason + * Reason for de-authentication as specified in @ref sl_wifi_deauth_reason_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is supported only in AP mode. + ******************************************************************************/ +sl_status_t sl_wifi_disconnect_ap_client(sl_wifi_interface_t interface, + const sl_mac_address_t *mac, + sl_wifi_deauth_reason_t reason); + +/***************************************************************************/ /** + * @brief + * Return the Wi-Fi client information of all clients connected to the AP. + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_ap should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @param[out] client_info + * @ref sl_wifi_client_info_response_t object to store the client info. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is supported only in AP mode. + ******************************************************************************/ +sl_status_t sl_wifi_get_ap_client_info(sl_wifi_interface_t interface, sl_wifi_client_info_response_t *client_info); + +/***************************************************************************/ /** + * @brief + * Return a list of Wi-Fi clients connected to the Wi-Fi access point. + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_ap should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @param[in] client_list_count + * The number of [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t) objects the client_list can store. + * @param[out] client_list + * A pointer to an array of client_list_count number of [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t) objects where the client list will be copied to. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is supported only in AP mode. + ******************************************************************************/ +sl_status_t sl_wifi_get_ap_client_list(sl_wifi_interface_t interface, + uint16_t client_list_count, + sl_mac_address_t *client_list); + +/***************************************************************************/ /** + * @brief + * Provide the number of Wi-Fi clients connected to the Wi-Fi access point + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_ap should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @param[out] client_count + * A uint32_t pointer that will store the number of associated clients. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is supported only in AP mode. + ******************************************************************************/ +sl_status_t sl_wifi_get_ap_client_count(sl_wifi_interface_t interface, uint32_t *client_count); + +/** @} */ + +/** \addtogroup WIFI_POWER_API Power and Performance + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ +// Power management functions + +/***************************************************************************/ /** + * @brief + * Set Wi-Fi performance profile. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] profile + * Wi-Fi performance profile as indicated by [sl_wifi_performance_profile_t](../wiseconnect-api-reference-guide-si91x-driver/sl-wifi-performance-profile-t) + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * For SI91x chips Enhanced MAX PSP is supported when profile is set to ASSOCIATED_POWER_SAVE_LOW_LATENCY and SL_SI91X_ENABLE_ENHANCED_MAX_PSP bit is enabled in config feature bitmap + * @note + * For further more details on connected and non-connected mode please refer https://www.silabs.com/documents/public/application-notes/an1430-siwx917-soc-low-power.pdf. + ******************************************************************************/ +sl_status_t sl_wifi_set_performance_profile(const sl_wifi_performance_profile_t *profile); + +/***************************************************************************/ /** + * @brief + * Get Wi-Fi performance profile. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] profile + * Wi-Fi performance profile as indicated by [sl_wifi_performance_profile_t](../wiseconnect-api-reference-guide-si91x-driver/sl-wifi-performance-profile-t) + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_performance_profile(sl_wifi_performance_profile_t *profile); + +/** @} */ + +// "Monitor Mode" functions + +/***************************************************************************/ /** + * @brief + * Enable monitor (promiscuous) mode on the Wi-Fi device. + * In this mode, all types of Wi-Fi frames will be forwarded to the host. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_enable_monitor_mode(sl_wifi_interface_t interface); + +/***************************************************************************/ /** + * @brief + * Disable monitor mode on the Wi-Fi interface. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_disable_monitor_mode(sl_wifi_interface_t interface); + +// P2P functions + +/***************************************************************************/ /** + * @brief + * Start Wi-Fi direct discovery. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] configuration + * P2P configuration as identified by @ref sl_wifi_p2p_configuration_t + * @param[in] credential_id + * Credential ID as identified by @ref sl_wifi_credential_id_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_start_p2p_discovery(sl_wifi_interface_t interface, + const sl_wifi_p2p_configuration_t *configuration, + sl_wifi_credential_id_t credential_id); + +/***************************************************************************/ /** + * @brief + * Start Wi-Fi direct connection. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] configuration + * P2P configuration as identified by @ref sl_wifi_p2p_configuration_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_p2p_connect(sl_wifi_interface_t interface, const sl_wifi_p2p_configuration_t *configuration); + +/** \addtogroup WIFI_WPS_API Wi-Fi Protected Setup + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ +// WPS functions + +/***************************************************************************/ /** + * @brief + * Generate Wi-Fi Protected Setup (WPS) pin. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[out] response + * @ref sl_wifi_wps_pin_t object that will contain the WPS pin. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_generate_wps_pin(sl_wifi_wps_pin_t *response); + +/***************************************************************************/ /** + * @brief + * Start Wi-Fi Protected Setup (WPS). + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_ap should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @param[in] mode + * WPS mode as identified by @ref sl_wifi_wps_mode_t + * @param[in] optional_wps_pin + * WPS pin object @ref sl_wifi_wps_pin_t when @ref SL_WIFI_WPS_PIN_MODE is used. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is supported only in AP mode. + ******************************************************************************/ +sl_status_t sl_wifi_start_wps(sl_wifi_interface_t interface, + sl_wifi_wps_mode_t mode, + const sl_wifi_wps_pin_t *optional_wps_pin); + +/***************************************************************************/ /** + * @brief + * Stop current running Wi-Fi Protected Setup (WPS). + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_wps should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is supported only in AP mode. + ******************************************************************************/ +sl_status_t sl_wifi_stop_wps(sl_wifi_interface_t interface); + +/** @} */ + +/** \addtogroup WIFI_DEBUG_API Debugging + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ + +// Debug functions +/***************************************************************************/ /** + * @brief + * Return Wi-Fi operational statistics. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] statistics + * @ref sl_wifi_statistics_t object that contains Wi-Fi statistics. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_statistics(sl_wifi_interface_t interface, sl_wifi_statistics_t *statistics); + +/***************************************************************************/ /** + * @brief + * Return Wi-Fi operational statistics. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[out] operational_statistics + * @ref sl_wifi_operational_statistics_t object that contains Wi-Fi statistics. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_operational_statistics(sl_wifi_interface_t interface, + sl_wifi_operational_statistics_t *operational_statistics); + +/***************************************************************************/ /** + * @brief + * Start collecting statistical data. + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] channel + * Provides the statistics report on the channel specified by @ref sl_wifi_channel_t. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_start_statistic_report(sl_wifi_interface_t interface, sl_wifi_channel_t channel); + +/***************************************************************************/ /** + * @brief + * Stop collecting statistical data. + * @pre Pre-conditions: + * - + * @ref sl_wifi_start_statistic_report should be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_wifi_stop_statistic_report(sl_wifi_interface_t interface); + +/** @} */ + +/***************************************************************************/ /** + * @brief + * Return the status of the Wi-Fi device. + * @param[out] wifi_status + * @ref sl_wifi_status_t object that will contain the Wi-Fi status. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_wifi_get_status(sl_wifi_status_t *wifi_status); + +/** \addtogroup WIFI_TRANSCEIVER_API Wi-Fi Transceiver + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ +// Wi-Fi Transceiver functions +/***************************************************************************/ /** + * @brief + * Start a Wi-Fi Transceiver interface. + * @pre Pre-conditions: + * - @ref sl_wifi_init shall be called before this API. + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] config + * Wi-Fi Transceiver configuration. See @ref sl_wifi_transceiver_configuration_t + * @return + * sl_status_t. See [Status Codes](../../wiseconnect-api-reference-guide-err-codes/pages/sl-additional-status-errors). Possible Error Codes: + * - `0x11` - SL_STATUS_NOT_INITIALIZED + * - `0x21` - SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE + * - `0x22` - SL_STATUS_NULL_POINTER + * - `0x0B65` - SL_STATUS_TRANSCEIVER_INVALID_CHANNEL + * - `0x0B67` - SL_STATUS_TRANSCEIVER_INVALID_CONFIG + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note `sl_wifi_transceiver_up` internally calls @ref sl_wifi_set_transceiver_parameters and @ref sl_wifi_transceiver_set_channel. Additionally, DUT MAC address is queried using @ref sl_wifi_get_mac_address and used as Addr2 for TX data packets. + ******************************************************************************/ +sl_status_t sl_wifi_transceiver_up(sl_wifi_interface_t interface, sl_wifi_transceiver_configuration_t *config); + +/***************************************************************************/ /** + * @brief Configure channel from the host. + * + * @pre Pre-conditions: + * - @ref sl_wifi_init shall be called before this API. + * + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] channel + * Application shall decide the channel at which device operates and transmits frames. See @ref sl_wifi_transceiver_set_channel_t. + * | Param | Description + * |:-----------------------|:----------------------------------------------------------- + * |channel | Primary channel number. Valid channels are 1-14. + * |band | Reserved + * |bandwidth | Reserved + * |tx_power | Max transmission power + * + * @return + * sl_status_t. See [Status Codes](../../wiseconnect-api-reference-guide-err-codes/pages/sl-additional-status-errors). Possible Error Codes: + * - `0x11` - SL_STATUS_NOT_INITIALIZED + * - `0x21` - SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE + * - `0x0B65` - SL_STATUS_TRANSCEIVER_INVALID_CHANNEL + * + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note This is a blocking API. + * @note The effective transmit power is subject to regional and device limitations. If the specified transmit power exceeds the maximum supported value for that region, the transmission will occur at the maximum supported transmit power. + * + * Sample command usage: + * @code + * // Initialize channel + * sl_wifi_transceiver_set_channel_t channel = { + * .chan_info.channel = 14, + * }; + * + * // Set channel + * sl_wifi_transceiver_set_channel(SL_WIFI_TRANSCEIVER_INTERFACE, channel); + * @endcode + * + ******************************************************************************/ +sl_status_t sl_wifi_transceiver_set_channel(sl_wifi_interface_t interface, sl_wifi_transceiver_set_channel_t channel); + +/***************************************************************************/ /** + * @brief This API shall be used to configure the CWmin, CWmax, and AIFSN per access category and retransmit count. + * + * @pre Pre-conditions: + * - @ref sl_wifi_init shall be called before this API. + * + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * + * @param[in] params + * Transceiver parameters as identified by @ref sl_wifi_transceiver_parameters_t. Shall be used to set/get the contention parameters per access category and the retransmit count in MAC layer. + * + * @return + * sl_status_t. See [Status Codes](../../wiseconnect-api-reference-guide-err-codes/pages/sl-additional-status-errors). Possible Error Codes: + * - `0x11` - SL_STATUS_NOT_INITIALIZED + * - `0x21` - SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE + * - `0x22` - SL_STATUS_NULL_POINTER + * - `0x0B67` - SL_STATUS_TRANSCEIVER_INVALID_CONFIG + * + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note Set is allowed only once before the first call to sl_wifi_transceiver_set_channel API. + * @note This API is optional. Default configurations are used if API is not called. + * @note This is a blocking API. + * + * Sample command usage: + * @code + * // Initialize parameters + * sl_wifi_transceiver_parameters_t params = { + * .set = 1, + * .retransmit_count = 15, + * .cw_params[0].aifsn = 3, + * }; + * + * // Set parameters + * sl_wifi_set_transceiver_parameters(SL_WIFI_TRANSCEIVER_INTERFACE, ¶ms); + * @endcode + ******************************************************************************/ +sl_status_t sl_wifi_set_transceiver_parameters(sl_wifi_interface_t interface, sl_wifi_transceiver_parameters_t *params); + +/***************************************************************************/ /** + * @brief When new peer is added or deleted from the network, application shall call this API to update peer information to the MAC layer. + * + * @pre Pre-conditions: + * - @ref sl_wifi_transceiver_set_channel shall be called before this API. + * + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] peer + * Peer to be added/deleted in MAC layer. See @ref sl_wifi_transceiver_peer_update_t. + * + * @return + * sl_status_t. See [Status Codes](../../wiseconnect-api-reference-guide-err-codes/pages/sl-additional-status-errors). Possible Error Codes: + * - `0x11` - SL_STATUS_NOT_INITIALIZED + * - `0x0B44` - SL_STATUS_WIFI_INTERFACE_NOT_UP + * - `0x0B63` - SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS + * - `0x0B66` - SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE + * - `0x10096` - SL_STATUS_SI91X_TRANSCEIVER_PEER_DS_FEAT_DISABLED + * - `0x10097` - SL_STATUS_SI91X_TRANSCEIVER_PEER_ALREADY_EXISTS + * - `0x10098` - SL_STATUS_SI91X_TRANSCEIVER_MAX_PEER_LIMIT_REACHED + * - `0x10099` - SL_STATUS_SI91X_TRANSCEIVER_PEER_NOT_FOUND + * + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note This is a blocking API. + * @note MAC layer supports storing up to 100 peers. + * @note To add peers in MAC layer, it is mandatory to enable SL_SI91X_FEAT_TRANSCEIVER_MAC_PEER_DS_SUPPORT/BIT(13) in [sl_wifi_device_configuration_t](../wiseconnect-api-reference-guide-si91x-driver/sl-wifi-device-configuration-t) feature_bit_map passed in @ref sl_wifi_init. + * + * Sample command usage: + * @code + * // Initialize peer + * sl_wifi_transceiver_peer_update_t peer; + * uint8_t peer_mac[6] = {0x00, 0x23, 0xa7, 0x20, 0x21, 0x24}; + * memcpy(peer.peer_mac_address, peer_mac, 6); + * peer.peer_supported_rate_bitmap = PEER_DS_BITMAP_DATA_RATE_48 | PEER_DS_BITMAP_DATA_RATE_54; + * peer.flags |= BIT(0)); // Set bit 0 to add peer + * + * // Add peer + * sl_wifi_update_transceiver_peer_list(SL_WIFI_TRANSCEIVER_INTERFACE, peer); + * @endcode + ******************************************************************************/ +sl_status_t sl_wifi_update_transceiver_peer_list(sl_wifi_interface_t interface, sl_wifi_transceiver_peer_update_t peer); + +/***************************************************************************/ /** + * @brief This API configures the multicast MAC address to filter Rx multicast packets. + * + * @pre Pre-conditions: + * - @ref sl_wifi_transceiver_set_channel shall be called before this API. + * + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * @param[in] mcast + * Multicast MAC address to be added/deleted from MAC layer for filtering. See @ref sl_wifi_transceiver_mcast_filter_t. + * + * @return + * sl_status_t. See [Status Codes](../../wiseconnect-api-reference-guide-err-codes/pages/sl-additional-status-errors). Possible Error Codes: + * - `0x11` - SL_STATUS_NOT_INITIALIZED + * - `0x21` - SL_STATUS_INVALID_PARAMETER + * - `0x0B44` - SL_STATUS_WIFI_INTERFACE_NOT_UP + * - `0x0B63` - SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS + * + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note This API can be called dynamically. + * @note Maximum of two multicast MAC addresses can be configured for filtering. + * + * Sample command usage: + * @code + * // Initialize multicast filter address structure + * sl_wifi_transceiver_mcast_filter_t mcast; + * uint8_t filter_mac[6] = { 0x01, 0x00, 0x5e, 0x00, 0x01, 0x01 }; + * mcast.flags |= BIT(0); + * mcast.num_of_mcast_addr = 1; + * memcpy(mcast.mac[0], filter_mac, 6); + * + * // Add MAC address to be filtered + * sl_wifi_set_transceiver_multicast_filter(SL_WIFI_TRANSCEIVER_INTERFACE, mcast); + * @endcode + ******************************************************************************/ +sl_status_t sl_wifi_set_transceiver_multicast_filter(sl_wifi_interface_t interface, + sl_wifi_transceiver_mcast_filter_t mcast); + +/***************************************************************************/ /** + * @brief This API shall flush the entire software buffer pool. + * + * @pre Pre-conditions: + * - @ref sl_wifi_transceiver_set_channel shall be called before this API. + * + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * + * @return + * sl_status_t. See [Status Codes](../../wiseconnect-api-reference-guide-err-codes/pages/sl-additional-status-errors). Possible Error Codes: + * - `0x11` - SL_STATUS_NOT_INITIALIZED + * - `0x0B44` - SL_STATUS_WIFI_INTERFACE_NOT_UP + * + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note All priority queues shall be flushed. + * + * Sample command usage: + * @code + * sl_wifi_flush_transceiver_data(SL_WIFI_TRANSCEIVER_INTERFACE); + * @endcode + ******************************************************************************/ +sl_status_t sl_wifi_flush_transceiver_data(sl_wifi_interface_t interface); + +/***************************************************************************/ /** + * @brief Host shall call this API to encapsulate the data with 802.11 MAC header and send it to MAC layer. + * + * @pre Pre-conditions: + * - @ref sl_wifi_transceiver_set_channel shall be called before this API. + * + * @param[in] interface + * Wi-Fi interface as identified by @ref sl_wifi_interface_t + * + * @param[in] control + * API uses metadata for preparing data packet along with MAC header for sending to MAC layer. See @ref sl_wifi_transceiver_tx_data_control_t. + * @param[in] payload + * Pointer to payload (encrypted by host) to be sent to LMAC. + * @param[in] payload_len + * Length of the payload. Valid range is 1 - 2020 bytes. + * + * @return + * sl_status_t. See [Status Codes](../../wiseconnect-api-reference-guide-err-codes/pages/sl-additional-status-errors). Possible Error Codes: + * - `0x11` - SL_STATUS_NOT_INITIALIZED + * - `0x0B44` - SL_STATUS_WIFI_INTERFACE_NOT_UP + * - `0x0B63` - SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS + * - `0x0B64` - SL_STATUS_TRANSCEIVER_INVALID_QOS_PRIORITY + * - `0x0B66` - SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE + * - `0x21` - SL_STATUS_INVALID_PARAMETER + * - `0x22` - SL_STATUS_NULL_POINTER + * + * #### Format of encapsulated data sent to MAC #### + * | Field name | Frame Control | Duration | Addr1 | Addr2 | Adddr3 | Seq Ctrl | Addr4 | QoS ctrl | Payload (LLC + Data) | + * |:-----------|:---------------|:---------|:------|:------|:-------|:---------|:-----------------------|:----------------------|:----------------------| + * | Size(bytes)| 2 | 2 | 6 | 6 | 6 | 2 | 6 (Optionally present) | 2 (Optionally present)| Variable | + * + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note Once sl_wifi_send_transceiver_data() returns, the calling API is responsible for freeing control and payload. The calling API refers to the function that invoked sl_wifi_send_transceiver_data(). + * @note On chip MAC level encryption is not supported in transceiver mode. + * @note This is not a blocking API. Callback SL_WIFI_TRANSCEIVER_TX_DATA_STATUS_CB can be registered to get the status report from firmware. + * @note Only 11b/g rates shall be supported. + * @note It is recommended to use basic rate for multicast/broadcast packets. + * @note Sample command usage: + * @code + * // Prepare payload + * + * + * control->ctrl_flags = BIT(0) | BIT(1) | BIT(2) | BIT(5); // Enable 4-addr MAC hdr, QoS frame, Fixed data rate, send status report for data packet + * control->priority = 2; // Voice priority queue + * control->rate = SL_WIFI_DATA_RATE_36; + * control->token = token; + * + * + * // Call API to encapsulate the data with 802.11 MAC header and send it to MAC layer. + * sl_wifi_send_transceiver_data(SL_WIFI_TRANSCEIVER_INTERFACE, control, payload, payload_len); + * @endcode + ******************************************************************************/ +sl_status_t sl_wifi_send_transceiver_data(sl_wifi_interface_t interface, + sl_wifi_transceiver_tx_data_control_t *control, + uint8_t *payload, + uint16_t payload_len); +/** @} */ + +/** + * @brief Refreshes the Access Point (AP) client information. + * + * This function fetches the current client details for the specified + * AP interface and updates the internal client information structure sl_wifi_client_info_t for all connected clients. + * + * @return sl_status_t + * - SL_STATUS_OK if the operation is successful. + * - Appropriate error code otherwise. + */ +sl_status_t sli_si91x_update_ap_client_info(); + +/** + * @brief Retrieve the IP address of an AP client using its MAC address. + * + * This function searches through the list of connected clients and returns the IP address + * of the client that matches the provided MAC address. + * + * @param[in] mac_add The MAC address of the client whose IP address is to be retrieved. + * + * @return A pointer to the IP address of the client if found, otherwise NULL. + */ +sl_ip_address_t *sli_si91x_get_ap_client_ip_address_from_mac_address(const sl_mac_address_t mac_add); \ No newline at end of file diff --git a/wiseconnect/components/protocol/wifi/inc/sl_wifi_callback_framework.h b/wiseconnect/components/protocol/wifi/inc/sl_wifi_callback_framework.h new file mode 100644 index 000000000..ffce9c89c --- /dev/null +++ b/wiseconnect/components/protocol/wifi/inc/sl_wifi_callback_framework.h @@ -0,0 +1,521 @@ +/***************************************************************************/ /** + * @file sl_wifi_callback_framework.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_wifi_host_interface.h" +#include "sl_wifi_device.h" // To access the device specific structs +#include + +/** \addtogroup WIFI_CALLBACK_FRAMEWORK Callback Framework + * \ingroup SL_WIFI + * @{ */ + +/// Generic macro for callback functions to check if the event has failed. +#define SL_WIFI_CHECK_IF_EVENT_FAILED(event) ((event & SL_WIFI_EVENT_FAIL_INDICATION) ? true : false) + +/** + * @typedef sl_wifi_callback_function_t + * @brief Generic callback for Wi-Fi group events of type @ref sl_wifi_event_group_t. + * + * This typedef defines a callback function that handles Wi-Fi events of type @ref sl_wifi_event_t. + * The callback is invoked when a Wi-Fi event occurs, providing the event details and any associated data. + * + * @param event + * Wi-Fi event of type @ref sl_wifi_event_t. This parameter indicates the specific Wi-Fi event that triggered the callback. + * @param data + * Pointer to the data received. The type and content of this data depend on the specific event. + * @param data_length + * Length of the data received in bytes. + * @param optional_arg + * Optional user-provided argument passed in @ref sl_wifi_set_callback. This parameter allows the user to pass additional context or information to the callback function. + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In case of event failure, the `SL_WIFI_FAIL_EVENT_STATUS_INDICATION` bit is set in the `event` parameter. + * When this bit is set, the `data` parameter will be of type `sl_status_t`, and the `data_length` parameter can be ignored. + */ +typedef sl_status_t (*sl_wifi_callback_function_t)(sl_wifi_event_t event, + void *data, + uint32_t data_length, + void *optional_arg); + +/** + * @typedef sl_wifi_scan_callback_t + * @brief Callback for SL_WIFI_SCAN_RESULT_EVENTS group event of type @ref sl_wifi_event_group_t. + * + * This typedef defines a callback function that handles Wi-Fi scan result events of type @ref sl_wifi_event_t. + * The callback is triggered when a Wi-Fi module tries to scan and receive the response, providing the event details and any associated scan results. + * + * @param event + * Wi-Fi event of type @ref sl_wifi_event_t. This parameter indicates the specific Wi-Fi event that triggered the callback. + * | @ref sl_wifi_event_t | Description | + * |:-------------------------------------|:---------------------------------------------------------------------| + * | SL_WIFI_SCAN_RESULT_EVENTS | It is an indication to host that the scan was successful or failed | + * @param data + * Pointer to the scan results of type @ref sl_wifi_scan_result_t. This parameter provides the scan results obtained from the Wi-Fi scan operation. + * @param data_length + * Length of the scan results data received in bytes. + * @param optional_arg + * Optional user provided argument passed in [sl_wifi_set_scan_callback](../wiseconnect-api-reference-guide-wi-fi/wifi-callback-framework#sl-wifi-set-scan-callback). + * + * @pre Wi-Fi module must call @ref sl_wifi_start_scan to receive SL_WIFI_SCAN_RESULT_EVENTS event. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In case of event failure, SL_WIFI_FAIL_EVENT_STATUS_INDICATION bit is set in the event. + * When this bit is set, the `data` parameter will be of type `sl_status_t`, and the `data_length` parameter can be ignored. + */ +typedef sl_status_t (*sl_wifi_scan_callback_t)(sl_wifi_event_t event, + sl_wifi_scan_result_t *data, + uint32_t data_length, + void *optional_arg); + +/** + * @typedef sl_wifi_stats_callback_t + * @brief Callback for SL_WIFI_STATS_RESPONSE_EVENTS group events of type @ref sl_wifi_event_group_t. + * + * This typedef defines a callback function that handles Wi-Fi statistics response events of type @ref sl_wifi_event_t. + * The callback is invoked when a Wi-Fi statistics response event occurs, providing the event details and any associated data. + * + * @param event + * Wi-Fi event of type @ref sl_wifi_event_t that triggered the callback. + * Individual Wi-Fi events related to SL_WIFI_STATS_RESPONSE_EVENTS is as follows: + * | @ref sl_wifi_event_t | DataType | + * |:-------------------------------------|:--------------------------------------------| + * | SL_WIFI_STATS_EVENT | Not supported in current release | + * | SL_WIFI_STATS_ASYNC_EVENT | [sl_si91x_async_stats_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-async-stats-response-t) | + * | SL_WIFI_STATS_ADVANCE_EVENT | Not supported in current release | + * | SL_WIFI_STATS_TEST_MODE_EVENT | Not supported in current release | + * | SL_WIFI_STATS_MODULE_STATE_EVENT | [sl_si91x_module_state_stats_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-module-state-stats-response-t) | + * @param data + * Pointer to the payload received. + * @param data_length + * Length of the payload received in bytes. + * @param optional_arg + * Optional user provided argument passed in [sl_wifi_set_stats_callback](../wiseconnect-api-reference-guide-wi-fi/wifi-callback-framework#sl-wifi-set-stats-callback). + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * SL_WIFI_STATS_MODULE_STATE_EVENT messages are used to indicate module state to the host. These messages are enabled by setting the 10th bit of the custom feature bitmap in opermode. + * For the event SL_WIFI_STATS_MODULE_STATE_EVENT response structure refer [sl_si91x_module_state_stats_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-module-state-stats-response-t). + * - state_code of this response (1 byte), indicates the state of the module. `state_code` contains two parts, the upper nibble and lower nibble. + * The state code is formed by combining the upper nibble and the lower nibble using a bitwise OR operation, i.e., State code = upper nibble | lower nibble + * For example, if the state code is 82 but isn’t found in the table, it can be divided as follows: state_code = 80 | 02, where 80 is the upper nibble and 02 is the lower nibble. + * + * The upper nibble indicates the state of the rejoin process. + * The following table documents the possible values of the upper nibble of the state_code. + * | Module state code | upper nibble | Description | + * |:------------------------------------|------------- |----------------------------------------------------------------------------| + * | Scan Trigger (State I) | 0x00 | Startup (Initial state or idle state). | + * | Indicates the reason for the scan |--------------|----------------------------------------------------------------------------| + * | triggered. | 0x10 | Beacon Loss (Failover Roam). | + * | |--------------|----------------------------------------------------------------------------| + * | | 0x20 | De-authentication from AP. | + * |-------------------------------------|--------------|----------------------------------------------------------------------------| + * | Scan Result/Decision (State II) | 0x50 | Current AP is best. | + * | Indicates a state change based on |--------------|--------------------------------------------------------------------------- | + * | the scan result. | 0x60 | Better AP found while roaming. | + * | |--------------|----------------------------------------------------------------------------| + * | | 0x70 | No AP found. | + * |-------------------------------------|--------------|----------------------------------------------------------------------------| + * | Final Connection or Join (State III)| 0x80 | Associated or joined to an Access point. | + * |Indicates the connection state |--------------|----------------------------------------------------------------------------| + * |change | 0x90 | Unassociated(Disconnected from host or join failure). | + * + * @note + * The lower nibble of state_code indicates the reason for a state change. + * The table below lists the possible values of the lower nibble of the state_code. + * | Module state code lower nibble | Description | + * |:-------------------------------|:----------------------------------------------| + * | 0x00 | No reason specified (Initial state or idle state). | + * | 0x01 | No response from AP for authentication request(Authentication denial). | + * | 0x02 | Association denial (Association timeout or Association failure due to unknown reasons). | + * | 0x03 | User configured AP is not present. | + * | 0x05 | Four-way Handshake failure. | + * | 0x06 | Deauthentication from user. | + * | 0x07 | PSK not configured. | + * | 0x08 | key-handshake failure during rejoin/roaming/after connection(Disconnection from supplicant). | + * | 0x09 | Roaming not enabled. | + * + * @note + * | Module reason code | Description | + * |:-------------------|:-----------------------------------------------------------| + * | 0x00 | No reason specified (Initial state or idle state). | + * | 0x01 | No response from AP for authentication request(Authentication denial). | + * | 0x02 | Association denial (caused by Association timeout or Association failure due to unknown reasons). | + * | 0x03 | User configured AP is not present. | + * | 0x05 | Four-way Handshake failure. | + * | 0x06 | Deauthentication from user. | + * | 0x07 | PSK not configured. | + * | 0x08 | key-handshake failure during rejoin/roaming/after connection(Disconnection from supplicant). | + * | 0x09 | Roaming not enabled | + * | 0x10 | Beacon Loss (Failover Roam). | + * | 0x20 | De-authentication from AP. | + * | 0x28 | TLS CA Cert not present | + * | 0x29 | TLS PRIVATE key not present. | + * | 0x2A | TLS Client Cert not present. | + * | 0x2B | TLS no Cert present. | + * | 0x2C | PEAP CA Cert not present. | + * | 0x2D | Server Cert Invalid Key Type. | + * | 0x2E | Server Intermediate CA Invalid Key Type. | + * | 0x2F | Server Root CA Invalid Key Type. | + * | 0x30 | Client Cert Invalid Key Type. | + * | 0x31 | Client Root CA Invalid Key Type. | + * | 0x37 | Server Cert 4096-bit length support is not enabled. | + * | 0x38 | Server Intermediate CA 4096-bit length support is not enabled. | + * | 0x39 | Server Root CA 4096-bit length support is not enabled. | + * | 0x3A | Client Cert 4096-bit length support is not enabled. | + * | 0x3B | Client Root CA 4096-bit length support is not enabled. | + * | 0x3C | Server Cert Invalid Sign Alg. | + * | 0x3D | Server Intermediate CA Invalid Sign Alg. | + * | 0x3E | Server Root CA Invalid Sign Length. | + * | 0x3F | Client Cert Invalid Sign Alg. | + * | 0x40 | Client Root CA Invalid Sign Length. | + * | 0x41 | Server Intermediate CA not Present. | + * | 0x42 | Server Root CA Parse Error. | + * | 0x43 | Server Intermediate Root CA Parse Error. | + * | 0x44 | Sever Cert Parse Error. | + * | 0x45 | Client Cert Parse Error. | + * | 0x46 | Incorrect Private Key Password. | + * | 0x47 | EAP Failure Received. | + * | 0x48 | Client Cert Bad Date Error. | + * | 0x49 | Server Cert Bad Date Error. | + * | 0x4A | Server Root CA Bad Date Error. | + * | 0x4B | Client Root CA Bad Date Error. | + * | 0x4C | Server Intermediate Root CA Bad Date Error. | + * | 0x4D | Pem Header Error. | + * | 0x4E | Pem Footer Error. | + * | 0x4F | Client Intermediate CA Invalid Sign Length. | + * | 0x50 | Client Intermediate CA Invalid Length. | + * | 0x52 | Client Intermediate CA invalid Key Type. | + * | 0x53 | Pem Error. | + * | 0x54 | Pathlen certificate is Invalid. | + * + * @note + * In addition to the above, the reason code received in the Deauthentication/Disassociation frame from the AP is modified by setting the most significant bit (MSB) of the reason code. + * If the MSB (Most Significant Bit) is set in the reason code, it should be masked with 0x7F to extract the actual reason code received in the Deauthentication/Disassociation frame. + * Pem Header Error (0x4D) and Pem Footer Error (0x4E) apply only when certificates are loaded individually. + * If certificates are loaded together in a single file, only the Pem Error (0x53) will be triggered for any header or footer errors. + * @note + * In case of event failure, the `SL_WIFI_FAIL_EVENT_STATUS_INDICATION` bit is set in the `event` parameter. + * When this bit is set, the `data` parameter will be of type `sl_status_t`, and the `data_length` parameter can be ignored. + */ +typedef sl_status_t (*sl_wifi_stats_callback_t)(sl_wifi_event_t event, + void *data, + uint32_t data_length, + void *optional_arg); + +/** + * @typedef sl_wifi_join_callback_t + * @brief Callback for SL_WIFI_JOIN_EVENTS group events of type @ref sl_wifi_event_group_t. + * + * This typedef defines a callback function that handles Wi-Fi join events of type @ref sl_wifi_event_t. + * The callback is invoked when a Wi-Fi join event occurs, providing the event details and any associated data. + * + * @param event + * Wi-Fi event of type @ref sl_wifi_event_t that triggered the callback. + * @param data + * Pointer to the response data received (1 byte). + * The possible values and their descriptions are as follows: + * | Data received | Description | + * |:----------------|:---------------------------| + * | C | Module connection success | + * | F | Module connection failed | + * @param data_length + * Length of the data received in bytes. This parameter indicates the size of the data buffer pointed to by the `data` parameter. + * @param optional_arg + * Optional user provided argument passed in [sl_wifi_set_join_callback](../wiseconnect-api-reference-guide-wi-fi/wifi-callback-framework#sl-wifi-set-join-callback). + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note This is valid in WiFi client mode only + * @note + * In case of event failure, the `SL_WIFI_FAIL_EVENT_STATUS_INDICATION` bit is set in the `event` parameter. + * When this bit is set, the `data` parameter will be of type `sl_status_t`, and the `data_length` parameter can be ignored. + */ +typedef sl_status_t (*sl_wifi_join_callback_t)(sl_wifi_event_t event, + char *data, + uint32_t data_length, + void *optional_arg); + +/** + * @typedef sl_wifi_twt_config_callback_t + * @brief Callback for SL_WIFI_TWT_RESPONSE_EVENTS group events + * + * This typedef defines a callback function that handles Wi-Fi Target Wake Time (TWT) configuration response events. + * The callback is invoked when a TWT response event occurs, providing the event details and any associated data. + * + * @param event + * Wi-Fi event of type @ref sl_wifi_event_t that triggered the callback. + * Individual Wi-Fi events related to SL_WIFI_TWT_RESPONSE_EVENTS is as follows: + * | @ref sl_wifi_event_t | Description | + * |:----------------------------------------------|:--------------------------------------------------------| + * | SL_WIFI_TWT_UNSOLICITED_SESSION_SUCCESS_EVENT | Unsolicited TWT session was successfully established. | + * | SL_WIFI_TWT_AP_REJECTED_EVENT | TWT request was rejected by the Access Point (AP). | + * | SL_WIFI_TWT_OUT_OF_TOLERANCE_EVENT | TWT response out of tolerance limits | + * | SL_WIFI_TWT_RESPONSE_NOT_MATCHED_EVENT | TWT response did not match the request. | + * | SL_WIFI_TWT_UNSUPPORTED_RESPONSE_EVENT | TWT response is unsupported. | + * | SL_WIFI_TWT_TEARDOWN_SUCCESS_EVENT | TWT session teardown was successful. | + * | SL_WIFI_TWT_AP_TEARDOWN_SUCCESS_EVENT | AP successfully tore down the TWT session. | + * | SL_WIFI_TWT_FAIL_MAX_RETRIES_REACHED_EVENT | Reached maximum number of retries for TWT setup. | + * | SL_WIFI_TWT_INACTIVE_DUE_TO_ROAMING_EVENT | TWT session became inactive due to roaming. | + * | SL_WIFI_TWT_INACTIVE_DUE_TO_DISCONNECT_EVENT | TWT session became inactive due to disconnection. | + * | SL_WIFI_TWT_INACTIVE_NO_AP_SUPPORT_EVENT | Connected AP does not support TWT | + * | SL_WIFI_RESCHEDULE_TWT_SUCCESS_EVENT | TWT session was successfully rescheduled. | + * | SL_WIFI_TWT_INFO_FRAME_EXCHANGE_FAILED_EVENT | TWT information frame exchange failed. | + * @param data + * Pointer to the data received of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + * This parameter provides detailed information about the TWT response event. The structure contains various fields that describe the TWT session parameters and status. + * @param data_length + * Length of the data received in bytes. + * @param optional_arg + * Optional user provided argument passed in [sl_wifi_set_twt_config_callback](../wiseconnect-api-reference-guide-wi-fi/wifi-callback-framework#sl-wifi-set-twt-config-callback). + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In case of event failure, the `SL_WIFI_FAIL_EVENT_STATUS_INDICATION` bit is set in the `event` parameter. + * When this bit is set, the `data` parameter will be of type `sl_status_t`, and the `data_length` parameter can be ignored. + */ +typedef sl_status_t (*sl_wifi_twt_config_callback_t)(sl_wifi_event_t event, + sl_si91x_twt_response_t *data, + uint32_t data_length, + void *optional_arg); + +/** + * @typedef sl_wifi_transceiver_callback_t + * @brief Callback for SL_WIFI_TRANSCEIVER_EVENTS group events + * + * This typedef defines a callback function that handles Wi-Fi transceiver events. + * The callback is invoked when a transceiver event occurs, providing the event details and any associated data. + * + * @param[out] event + * Wi-Fi event of type @ref sl_wifi_event_t. This parameter indicates the specific Wi-Fi event that triggered the callback. + * Individual Wi-Fi events related to SL_WIFI_TRANSCEIVER_EVENTS are as follows: + * | @ref sl_wifi_event_t | Description | + * |:---------------------------------------|:------------------------------------------------------------| + * | SL_WIFI_TRANSCEIVER_RX_DATA_RECEIVE_CB | Indicates that data has been received by the transceiver. | + * | SL_WIFI_TRANSCEIVER_TX_DATA_STATUS_CB | Indicates the status of the data sent by the transceiver. | + * @param[out] data + * - Data received is of type @ref sl_wifi_transceiver_rx_data_t for SL_WIFI_TRANSCEIVER_RX_DATA_RECEIVE_CB event. + * - Data received is of type @ref sl_wifi_transceiver_tx_data_confirmation_t for SL_WIFI_TRANSCEIVER_TX_DATA_STATUS_CB event. + * @param[out] data_length + * Reserved. + * @param[out] optional_arg + * Optional user provided argument passed in [sl_wifi_set_transceiver_callback](../pages/wifi-callback-framework#sl-wifi-set-transceiver-callback) + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/4.1/common/api/group-status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note This API is only supported in Wi-Fi Transceiver opermode (7). + * @note + * In case of event failure, the `SL_WIFI_FAIL_EVENT_STATUS_INDICATION` bit is set in the `event` parameter. + * When this bit is set, the `data` parameter will be of type `sl_status_t`, and the `data_length` parameter can be ignored. + */ +typedef sl_status_t (*sl_wifi_transceiver_callback_t)(sl_wifi_event_t event, + void *data, + uint32_t data_length, + void *optional_arg); + +/***************************************************************************/ +/** + * @brief + * Register a callback for a selected event group. All the individual Wi-Fi events related to specific group would be triggered via this group callback. + * + * This function allows the user to register a callback function for a specific group of Wi-Fi events @ref sl_wifi_event_group_t. + * When any event within the specified group occurs, the registered callback function will be invoked, providing the event details and any associated data. + * + * @param[in] group + * Group ID of the event for which the callback is registered. See @ref sl_wifi_event_group_t for possible values. + * @param[in] function + * Function pointer to callback of type @ref sl_wifi_callback_function_t that would be invoked when an event in the specified group occurs. + * @param[in] optional_arg + * Optional user provided argument to pass additional context or information to the callback function. This would be passed back to callback handler of type @ref sl_wifi_callback_function_t. + * @pre Pre-conditions: + * - The Wi-Fi module must be initialized by calling @ref sl_wifi_init before this API can be used. + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * Callbacks can be set only for event groups defined in @ref sl_wifi_event_group_t, not for individual events defined in @ref sl_wifi_event_t. + ******************************************************************************/ +sl_status_t sl_wifi_set_callback(sl_wifi_event_group_t group, sl_wifi_callback_function_t function, void *optional_arg); + +/***************************************************************************/ /** + * @brief + * Default Wi-Fi event handler to be passed to @ref sl_wifi_init. This event handler would dispatch all the Wi-Fi events and invoke respective Wi-Fi group event. + * + * This function serves as the default event handler for Wi-Fi events. + * When passed to the @ref sl_wifi_init function, it would handle incoming Wi-Fi events by dispatching them to the appropriate group event functions. + * + * @param[in] event + * Wi-Fi event of type of @ref sl_wifi_event_t. + * @param[in] buffer + * Buffer containing raw data from NWP firmware + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * Passing the event handler is optional. User can implement their own event dispatching handler if they prefer. + ******************************************************************************/ +extern sl_status_t sl_wifi_default_event_handler(sl_wifi_event_t event, sl_wifi_buffer_t *buffer); + +/***************************************************************************/ +/** + * @brief + * Register a callback for the SL_WIFI_SCAN_RESULT_EVENTS group event from @ref sl_wifi_event_group_t. + * + * This function allows the user to register a callback function for the SL_WIFI_SCAN_RESULT_EVENTS group. + * When any event within this group occurs, the registered callback function would be invoked, providing the event details and any associated data. + * + * @param[in] function + * Callback function to register. This parameter specifies the callback function of type @ref sl_wifi_scan_callback_t that would be invoked when an event in the SL_WIFI_SCAN_RESULT_EVENTS group occurs. + * @param[in] optional_arg + * Optional user provided argument. This would be passed back to callback handler of type @ref sl_wifi_scan_callback_t. + * @pre Pre-conditions: + * - @ref sl_wifi_init should be called before this API. + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * All the individual Wi-Fi events related to this group would be triggered via this callback. + ******************************************************************************/ +static inline sl_status_t sl_wifi_set_scan_callback(sl_wifi_scan_callback_t function, void *optional_arg) +{ + return sl_wifi_set_callback(SL_WIFI_SCAN_RESULT_EVENTS, (sl_wifi_callback_function_t)function, optional_arg); +} + +/***************************************************************************/ +/** + * @brief + * Register a callback for SL_WIFI_JOIN_EVENTS group event from @ref sl_wifi_event_group_t. + * + * This function allows the user to register a callback function for the SL_WIFI_JOIN_EVENTS group. + * When any event within this group occurs, the registered callback function would be invoked, providing the event details and any associated data. + * + * @param[in] function + * Function pointer to callback of type @ref sl_wifi_join_callback_t. This parameter specifies the callback function that would be invoked when an event in the SL_WIFI_JOIN_EVENTS group occurs. + * @param[in] optional_arg + * Optional user provided argument. This parameter allows the user to pass additional context or information to the callback function. This would be passed back to callback handler of type @ref sl_wifi_twt_config_callback_t. + * @pre Pre-conditions: + * @ref sl_wifi_init should be called before this API. + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * All the individual Wi-Fi events related to this group will be triggered via this callback. + ******************************************************************************/ +static inline sl_status_t sl_wifi_set_join_callback(sl_wifi_join_callback_t function, void *optional_arg) +{ + return sl_wifi_set_callback(SL_WIFI_JOIN_EVENTS, (sl_wifi_callback_function_t)function, optional_arg); +} + +/***************************************************************************/ +/** + * @brief + * Register a callback for SL_WIFI_TWT_RESPONSE_EVENTS group event from @ref sl_wifi_event_group_t. + * + * This function allows the user to register a callback function for the SL_WIFI_TWT_RESPONSE_EVENTS group. + * When any event within this group occurs, the registered callback function will be invoked, providing the event details and any associated data. + * + * @param[in] function + * Function pointer to the callback of type @ref sl_wifi_twt_config_callback_t. This parameter specifies the callback function that would be invoked when an event in the SL_WIFI_TWT_RESPONSE_EVENTS group occurs. + * @param[in] optional_arg + * Optional user provided argument. This would be passed back to callback handler. + * @pre Pre-conditions: + * @ref sl_wifi_init should be called before this API. + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * All the individual Wi-Fi events related to this group would be triggered via this callback. + ******************************************************************************/ +static inline sl_status_t sl_wifi_set_twt_config_callback(sl_wifi_twt_config_callback_t function, void *optional_arg) +{ + return sl_wifi_set_callback(SL_WIFI_TWT_RESPONSE_EVENTS, (sl_wifi_callback_function_t)function, optional_arg); +} + +/***************************************************************************/ +/** + * @brief + * Register a callback for SL_WIFI_STATS_RESPONSE_EVENTS group event from @ref sl_wifi_event_group_t. + * + * This function allows the user to register a callback function for the SL_WIFI_STATS_RESPONSE_EVENTS group. + * When any event within this group occurs, the registered callback function would be invoked, providing the event details and any associated data. + * + * @param[in] function + * Function pointer to the callback of type @ref sl_wifi_stats_callback_t. This parameter specifies the callback function that would be invoked when an event in the SL_WIFI_STATS_RESPONSE_EVENTS group occurs. + * @param[in] optional_arg + * Optional user provided argument. This parameter allows the user to pass additional context or information to the callback function. This would be passed back to callback handler. + * @pre Pre-conditions: + * @ref sl_wifi_init should be called before this API. + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * All the individual Wi-Fi events related to this group would be triggered via this callback. + ******************************************************************************/ +static inline sl_status_t sl_wifi_set_stats_callback(sl_wifi_stats_callback_t function, void *optional_arg) +{ + return sl_wifi_set_callback(SL_WIFI_STATS_RESPONSE_EVENTS, (sl_wifi_callback_function_t)function, optional_arg); +} + +/***************************************************************************/ /** + * @brief + * Register a callback for SL_WIFI_TRANSCEIVER_EVENTS group event of tye @ref sl_wifi_event_group_t. + * + * This function allows the user to register a callback function for the SL_WIFI_TRANSCEIVER_EVENTS group. + * When any event within this group occurs, the registered callback function would be invoked, providing the event details and any associated data. + * + * @param[in] function + * Function pointer to the callback of type @ref sl_wifi_transceiver_callback_t. This parameter specifies the callback function that would be invoked when an event in the SL_WIFI_TRANSCEIVER_EVENTS group occurs. + * @param[in] optional_arg + * Optional user provided argument. This parameter allows the user to pass additional context or information to the callback function. This would be passed back to callback handler. + * @pre Pre-conditions: + * - @ref sl_wifi_init should be called before this API. + * @return +* sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/4.1/common/api/group-status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * All the individual Wi-Fi events related to this group will be triggered via this callback. + ******************************************************************************/ +static inline sl_status_t sl_wifi_set_transceiver_callback(sl_wifi_transceiver_callback_t function, void *optional_arg) +{ + return sl_wifi_set_callback(SL_WIFI_TRANSCEIVER_EVENTS, (sl_wifi_callback_function_t)function, optional_arg); +} + +/** @} */ diff --git a/wiseconnect/components/protocol/wifi/inc/sl_wifi_constants.h b/wiseconnect/components/protocol/wifi/inc/sl_wifi_constants.h new file mode 100644 index 000000000..d15edcd38 --- /dev/null +++ b/wiseconnect/components/protocol/wifi/inc/sl_wifi_constants.h @@ -0,0 +1,665 @@ +/***************************************************************************/ /** + * @file sl_wifi_constants.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_WIFI_CONSTANTS_H_ +#define _SL_WIFI_CONSTANTS_H_ + +#include + +/** \addtogroup SL_WIFI_CONSTANTS Constants + * @{ */ + +/// Maximum number of Access Points are scanned in response to a normal scan request. +/// @note This is not a configurable value. +#define SL_WIFI_MAX_SCANNED_AP 11 + +/// Maximum number of clients supported when module is running in Access Point mode. +#define SL_WIFI_MAX_CLIENT_COUNT 16 + +/// Maximum length of the Wi-Fi Pre-Shared Key (PSK) credential. +#define SL_WIFI_MAX_PSK_LENGTH 32 + +/// Maximum length of the Wi-Fi Pairwise Master Key (PMK) credential. +#define SL_WIFI_MAX_PMK_LENGTH 64 + +/// Maximum length of the key in WEP security. +#define SL_WIFI_WEP_KEY_LENGTH 32 + +/// Maximum number of keys supported for WEP security. +#define SL_WIFI_WEP_KEY_COUNT 4 + +/// Maximum length of the username in enterprise security. +#define SL_WIFI_EAP_USER_NAME_LENGTH 64 + +/// Maximum length of the password in enterprise security. +#define SL_WIFI_EAP_PASSWORD_LENGTH 128 + +/// Maximum length of the certificate key in enterprise security. +#define SL_WIFI_EAP_CERTIFICATE_KEY_LENGTH 80 + +/// Select Internal Antenna for Wi-Fi. +#define SL_WIFI_SELECT_INTERNAL_ANTENNA 0 + +/// Select External Antenna for Wi-Fi. +#define SL_WIFI_SELECT_EXTERNAL_ANTENNA 1 + +/// Macro to get the default Wi-Fi interface. +#define SL_WIFI_DEFAULT_INTERFACE sl_wifi_get_default_interface() + +/// Maximum interval for Wi-Fi roaming trigger in milliseconds. +#define SL_WIFI_NEVER_ROAM 0x7FFFFFFF + +/** + * @enum sl_wifi_security_t + * @brief Enumeration for Wi-Fi security types. + * + * @note WPA3 Transition security type is not currently supported while running as an Access Point (AP). + */ +typedef enum { + SL_WIFI_OPEN = 0, ///< Wi-Fi Open security type + SL_WIFI_WPA = 1, ///< Wi-Fi WPA security type + SL_WIFI_WPA2 = 2, ///< Wi-Fi WPA2 security type + SL_WIFI_WEP = 3, ///< Wi-Fi WEP security type + SL_WIFI_WPA_ENTERPRISE = 4, ///< Wi-Fi WPA enterprise security type + SL_WIFI_WPA2_ENTERPRISE = 5, ///< Wi-Fi WPA2 enterprise security type + SL_WIFI_WPA_WPA2_MIXED = 6, ///< Wi-Fi WPA/WPA2 mixed security type that supports both WPA and WPA2 + SL_WIFI_WPA3 = 7, ///< Wi-Fi WPA3 security type + SL_WIFI_WPA3_TRANSITION = 8, ///< Wi-Fi WPA3 Transition security type (not currently supported in AP mode) + SL_WIFI_WPA3_ENTERPRISE = 9, ///< Wi-Fi WPA3 enterprise security type + SL_WIFI_WPA3_TRANSITION_ENTERPRISE = 10, ///< Wi-Fi WPA3 Transition enterprise security type + + SL_WIFI_SECURITY_UNKNOWN = 0xFFFF, ///< Wi-Fi Unknown Security type +} sl_wifi_security_t; + +/** + * @enum sl_wifi_encryption_t + * @brief Enumeration for Wi-Fi encryption methods. + * + * @note Some encryption types are not currently supported in station (STA) mode. + * @note If encryption type is configured anything other than SL_WIFI_DEFAULT_ENCRYPTION, then make sure the AP (third party) supports the configured encryption type. If not, there might be a possibility of getting join failure due to the encryption type mismatch between AP (third party) and STA. + */ +typedef enum { + SL_WIFI_DEFAULT_ENCRYPTION, ///< Default Wi-Fi encryption + SL_WIFI_NO_ENCRYPTION, ///< Wi-Fi with no Encryption (not currently supported in STA mode) + SL_WIFI_WEP_ENCRYPTION, ///< Wi-Fi with WEP Encryption (not currently supported in STA mode) + SL_WIFI_TKIP_ENCRYPTION, ///< Wi-Fi with TKIP Encryption (not currently supported in STA mode) + SL_WIFI_CCMP_ENCRYPTION, ///< Wi-Fi with CCMP Encryption + SL_WIFI_EAP_TLS_ENCRYPTION, ///< Wi-Fi with Enterprise TLS Encryption + SL_WIFI_EAP_TTLS_ENCRYPTION, ///< Wi-Fi with Enterprise TTLS Encryption + SL_WIFI_EAP_FAST_ENCRYPTION, ///< Wi-Fi with Enterprise FAST Encryption + SL_WIFI_PEAP_MSCHAPV2_ENCRYPTION, ///< Wi-Fi with Enterprise PEAP Encryption + SL_WIFI_EAP_LEAP_ENCRYPTION ///< Wi-Fi with Enterprise LEAP Encryption +} sl_wifi_encryption_t; + +/** + * @enum sl_wifi_tdi_t + * @brief Enumeration for Wi-Fi Transition Disable Indication (TDI). + * + * @note TDI is supported only in WPA3 (Personal or Personal Transition) security in Access Point (AP) mode. + */ +typedef enum { + SL_WIFI_TDI_NONE = 0, ///< Allows stations to transition within AP network. + SL_WIFI_TDI_SAE = + (1 + << 4), ///< Disallows stations from transitioning within the AP network and only allows connections with WPA3-SAE security mode. +} sl_wifi_tdi_t; + +/** + * @enum sl_wifi_credential_type_t + * @brief Enumeration for Wi-Fi Credential Types. + */ +typedef enum { + SL_WIFI_PSK_CREDENTIAL = 0, ///< Wi-Fi Personal Credential + SL_WIFI_PMK_CREDENTIAL, ///< Wi-Fi Pairwise Master Key + SL_WIFI_WEP_CREDENTIAL, ///< Wi-Fi WEP Credential + SL_WIFI_EAP_CREDENTIAL, ///< Wi-Fi Enterprise Client Credential + SL_WIFI_USER_CREDENTIAL = (1 << 31) ///< Wi-Fi User Credential +} sl_wifi_credential_type_t; + +/** + * @enum sl_wifi_antenna_t + * @brief Enumeration of Wi-Fi antenna selections. + * + * @note Only the internal antenna is currently supported. + */ +typedef enum { + SL_WIFI_ANTENNA_1, ///< Wi-Fi Radio Antenna 1 (not currently supported) + SL_WIFI_ANTENNA_2, ///< Wi-Fi Radio Antenna 2 (not currently supported) + SL_WIFI_ANTENNA_AUTO, ///< Wi-Fi Radio Antenna Auto Selection (not currently supported) + SL_WIFI_ANTENNA_EXTERNAL, ///< Wi-Fi Radio External Antenna (not currently supported) + SL_WIFI_ANTENNA_INTERNAL, ///< Wi-Fi Radio Internal Antenna +} sl_wifi_antenna_t; + +/** + * @enum sl_wifi_interface_index_t + * @brief Enumeration of Wi-Fi interface indices. + * + * @note 5 GHz interfaces are not currently supported. + */ +typedef enum { + SL_WIFI_CLIENT_2_4GHZ_INTERFACE_INDEX = 0, ///< Wi-Fi client on 2.4 GHz interface + SL_WIFI_AP_2_4GHZ_INTERFACE_INDEX, ///< Wi-Fi access point on 2.4 GHz interface + SL_WIFI_CLIENT_5GHZ_INTERFACE_INDEX, ///< Wi-Fi client on 5 GHz interface (not currently supported) + SL_WIFI_AP_5GHZ_INTERFACE_INDEX, ///< Wi-Fi access point on 5 GHz interface (not currently supported) + SL_WIFI_TRANSCEIVER_INTERFACE_INDEX, ///< Wi-Fi transceiver mode + SL_WIFI_MAX_INTERFACE_INDEX ///< Used for internally by SDK +} sl_wifi_interface_index_t; + +/** + * @enum sl_wifi_interface_t + * @brief Enumeration of Wi-Fi interfaces. + * + * @note 5 GHz radio interfaces are not currently supported. + */ +typedef enum { + SL_WIFI_INVALID_INTERFACE = 0, ///< Invalid interface + + SL_WIFI_CLIENT_INTERFACE = (1 << 0), ///< Wi-Fi client interface + SL_WIFI_AP_INTERFACE = (1 << 1), ///< Wi-Fi access point interface + + SL_WIFI_2_4GHZ_INTERFACE = (1 << 2), ///< 2.4 GHz radio interface + SL_WIFI_5GHZ_INTERFACE = (1 << 3), ///< 5 GHz radio interface (currently not supported for Si91x) + + // BIT(4), BIT(5) - Reserved for 6 GHz and Sub-GHz + + SL_WIFI_TRANSCEIVER_INTERFACE = (1 << 7), ///< Wi-Fi Transceiver mode interface + + SL_WIFI_CLIENT_2_4GHZ_INTERFACE = SL_WIFI_CLIENT_INTERFACE + | SL_WIFI_2_4GHZ_INTERFACE, ///< Wi-Fi client interface on 2.4 GHz radio + SL_WIFI_AP_2_4GHZ_INTERFACE = SL_WIFI_AP_INTERFACE + | SL_WIFI_2_4GHZ_INTERFACE, ///< Wi-Fi access point interface on 2.4 GHz radio + + SL_WIFI_CLIENT_5GHZ_INTERFACE = + SL_WIFI_CLIENT_INTERFACE + | SL_WIFI_5GHZ_INTERFACE, ///< Wi-Fi client interface on 5 GHz radio (currently not supported for Si91x) + SL_WIFI_AP_5GHZ_INTERFACE = + SL_WIFI_AP_INTERFACE + | SL_WIFI_5GHZ_INTERFACE, ///< Wi-Fi access point interface on 5 GHz radio (currently not supported for Si91x) + + SL_WIFI_ALL_INTERFACES = + SL_WIFI_CLIENT_INTERFACE | SL_WIFI_AP_INTERFACE | SL_WIFI_2_4GHZ_INTERFACE + | SL_WIFI_5GHZ_INTERFACE, ///< All available Wi-Fi interfaces (5GHz is currently not supported for Si91x) + +} sl_wifi_interface_t; + +/// Enumeration of de-authentication reasons from an access point. +typedef enum { + SL_WIFI_DEAUTH, ///< De-Authentication from radius server + SL_WIFI_DEAUTH_UNSPECIFIED, ///< Unspecified de-authentication reason +} sl_wifi_deauth_reason_t; + +/** + * @enum sl_wifi_regulatory_region_t + * @brief Enumeration of Wi-Fi regulatory regions. + * + * @note Australia and France regions are not currently supported. + */ +typedef enum { + SL_WIFI_REGION_AUSTRALIA, ///< Wi-Fi Region Australia (not currently supported) + SL_WIFI_REGION_FRANCE, ///< Wi-Fi Region France (not currently supported) + SL_WIFI_REGION_EUROPEAN_UNION, ///< Wi-Fi Region European Union + SL_WIFI_REGION_JAPAN, ///< Wi-Fi Region Japan + SL_WIFI_REGION_UNITED_STATES, ///< Wi-Fi Region United States +} sl_wifi_regulatory_region_t; + +/** + * @brief Wi-Fi rate protocols. + * @note Recommended value for default behavior is SL_WIFI_RATE_PROTOCOL_AUTO. + * @note 802.11ac not currently supported. + */ +typedef enum { + SL_WIFI_RATE_PROTOCOL_B_ONLY, ///< 802.11b rates only (rates go here) + SL_WIFI_RATE_PROTOCOL_G_ONLY, ///< 802.11g rates only (rates go here) + SL_WIFI_RATE_PROTOCOL_N_ONLY, ///< 802.11n rates only (rates go here) + SL_WIFI_RATE_PROTOCOL_AC_ONLY, ///< 802.11ac rates only (rates go here) (not currently supported) + SL_WIFI_RATE_PROTOCOL_AX_ONLY, ///< 802.11ax rates only (rates go here) + SL_WIFI_RATE_PROTOCOL_AUTO, ///< Automatic rate selection +} sl_wifi_rate_protocol_t; + +/// Wi-Fi scan types. +typedef enum { + SL_WIFI_SCAN_TYPE_ACTIVE = 0x00, ///< Active scan: Transmit probe requests and listen for responses + SL_WIFI_SCAN_TYPE_PASSIVE = + 0x01, ///< Passive scan: No active transmissions, listen for AP beacons and broadcast probe responses + SL_WIFI_SCAN_TYPE_EXTENDED = + 0x02, ///< Extended Active scan. Transmit probe requests and listen for responses to get more than SL_WIFI_MAX_SCANNED_AP number of results + SL_WIFI_SCAN_TYPE_PROHIBITED_CHANNELS = 0x04, ///< Scan channels prohibited by regulatory region + SL_WIFI_SCAN_TYPE_ADV_SCAN = 0X08 ///< Advanced scan: Scan for Access Points while the module is in connected state +} sl_wifi_scan_type_t; + +/** + * @enum sl_wifi_rate_t + * @brief Enumeration of Wi-Fi transfer rates. + */ +typedef enum { + SL_WIFI_AUTO_RATE = 0, ///< Wi-Fi Auto transfer rate + + SL_WIFI_RATE_11B_1, ///< Wi-Fi 1 Mbps transfer rate for 802.11b + SL_WIFI_RATE_11B_MIN = SL_WIFI_RATE_11B_1, ///< Wi-Fi Minimum transfer rate for 802.11b + SL_WIFI_RATE_11B_2, ///< Wi-Fi 2 Mbps transfer rate for 802.11b + SL_WIFI_RATE_11B_5_5, ///< Wi-Fi 5.5 Mbps transfer rate for 802.11b + SL_WIFI_RATE_11B_11, ///< Wi-Fi 11 Mbps transfer rate for 802.11b + SL_WIFI_RATE_11B_MAX = SL_WIFI_RATE_11B_11, ///< Wi-Fi Maximum transfer rate for 802.11b + + SL_WIFI_RATE_11G_6, ///< Wi-Fi 6 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_MIN = SL_WIFI_RATE_11G_6, ///< Wi-Fi Minimum transfer rate for 802.11g + SL_WIFI_RATE_11G_9, ///< Wi-Fi 9 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_12, ///< Wi-Fi 12 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_18, ///< Wi-Fi 18 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_24, ///< Wi-Fi 24 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_36, ///< Wi-Fi 36 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_48, ///< Wi-Fi 48 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_54, ///< Wi-Fi 54 Mbps transfer rate for 802.11g + SL_WIFI_RATE_11G_MAX = SL_WIFI_RATE_11G_54, ///< Wi-Fi Maximum transfer rate for 802.11g + + SL_WIFI_RATE_11N_MCS0, ///< Wi-Fi MCS index 0 transfer rate for 802.11n + SL_WIFI_RATE_11N_MIN = SL_WIFI_RATE_11N_MCS0, ///< Wi-Fi Minimum transfer rate for 802.11n + SL_WIFI_RATE_11N_MCS1, ///< Wi-Fi MCS index 1 transfer rate for 802.11n + SL_WIFI_RATE_11N_MCS2, ///< Wi-Fi MCS index 2 transfer rate for 802.11n + SL_WIFI_RATE_11N_MCS3, ///< Wi-Fi MCS index 3 transfer rate for 802.11n + SL_WIFI_RATE_11N_MCS4, ///< Wi-Fi MCS index 4 transfer rate for 802.11n + SL_WIFI_RATE_11N_MCS5, ///< Wi-Fi MCS index 5 transfer rate for 802.11n + SL_WIFI_RATE_11N_MCS6, ///< Wi-Fi MCS index 6 transfer rate for 802.11n + SL_WIFI_RATE_11N_MCS7, ///< Wi-Fi MCS index 7 transfer rate for 802.11n + SL_WIFI_RATE_11N_MAX = SL_WIFI_RATE_11N_MCS7, ///< Wi-Fi Maximum transfer rate for 802.11n + + SL_WIFI_RATE_11AX_MCS0, ///< Wi-Fi MCS index 0 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MIN = SL_WIFI_RATE_11AX_MCS0, ///< Wi-Fi Minimum transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MCS1, ///< Wi-Fi MCS index 1 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MCS2, ///< Wi-Fi MCS index 2 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MCS3, ///< Wi-Fi MCS index 3 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MCS4, ///< Wi-Fi MCS index 4 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MCS5, ///< Wi-Fi MCS index 5 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MCS6, ///< Wi-Fi MCS index 6 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MCS7, ///< Wi-Fi MCS index 7 transfer rate for 802.11ax + SL_WIFI_RATE_11AX_MAX = SL_WIFI_RATE_11AX_MCS7, ///< Wi-Fi Maximum transfer rate for 802.11ax + + SL_WIFI_RATE_INVALID = 0xFF ///< Wi-Fi Invalid transfer rate +} sl_wifi_rate_t; + +/** + * @enum sl_wifi_bss_type_t + * @brief Enumeration of Wi-Fi Basic Service Set (BSS) types. + */ +typedef enum { + SL_WIFI_BSS_TYPE_INFRASTRUCTURE = + 0, ///< Infrastructure BSS: Standard Wi-Fi Infrastructure network with an access point + SL_WIFI_BSS_TYPE_ADHOC = 1, ///< Ad-hoc BSS: Peer-to-peer Wi-Fi network without an access point + SL_WIFI_BSS_TYPE_ANY = 2, ///< Any Wi-Fi BSS type + SL_WIFI_BSS_TYPE_UNKNOWN = 0xFF ///< Unknown Wi-Fi BSS type +} sl_wifi_bss_type_t; + +/** + * @enum sl_wifi_band_t + * @brief Enumeration of Wi-Fi radio bands. + * + * @note Only the 2.4 GHz band is currently supported. + */ +typedef enum { + SL_WIFI_AUTO_BAND = 0, ///< Wi-Fi Band Auto + SL_WIFI_BAND_900MHZ = 1, ///< Wi-Fi Band 900 MHz (not currently supported) + SL_WIFI_BAND_2_4GHZ = 2, ///< Wi-Fi Band 2.4 GHz + SL_WIFI_BAND_5GHZ = 3, ///< Wi-Fi Band 5 GHz (not currently supported) + SL_WIFI_BAND_6GHZ = 4, ///< Wi-Fi Band 6 GHz (not currently supported) + SL_WIFI_BAND_60GHZ = 5, ///< Wi-Fi Band 60 GHz (not currently supported) +} sl_wifi_band_t; + +/** + * @enum sl_wifi_bandwidth_t + * @brief Enumeration of Wi-Fi bandwidth options. + * + * @note Only 20 MHz bandwidth is currently supported. + */ +typedef enum { + SL_WIFI_AUTO_BANDWIDTH = 0, ///< Wi-Fi Bandwidth Auto + SL_WIFI_BANDWIDTH_10MHz = 0, ///< Wi-Fi Bandwidth 10 MHz (not currently supported) + SL_WIFI_BANDWIDTH_20MHz = 1, ///< Wi-Fi Bandwidth 20 MHz + SL_WIFI_BANDWIDTH_40MHz = 2, ///< Wi-Fi Bandwidth 40 MHz (not currently supported) + SL_WIFI_BANDWIDTH_80MHz = 3, ///< Wi-Fi Bandwidth 80 MHz (not currently supported) + SL_WIFI_BANDWIDTH_160MHz = 4, ///< Wi-Fi Bandwidth 160 MHz (not currently supported) +} sl_wifi_bandwidth_t; + +/** + * @enum sl_wifi_client_flag_t + * @brief Option flags for Wi-Fi client interfaces. + */ +typedef enum { + SL_WIFI_NO_JOIN_OPTION = 0, ///< Wi-Fi Client Join with no flags + SL_WIFI_JOIN_WITH_NO_CSA = (1 << 0), ///< Wi-Fi Client Join without Channel Switch Announcement (CSA) + SL_WIFI_JOIN_WITH_SCAN = (1 << 1) ///< Wi-Fi Client Join with Scan +} sl_wifi_client_flag_t; + +/** + * @enum sl_wifi_ap_flag_t + * @brief Option flags for Access Point (AP) interfaces. + */ +typedef enum { + SL_WIFI_HIDDEN_SSID = (1 << 0), ///< Hide the SSID of the AP +} sl_wifi_ap_flag_t; + +/** + * @enum sl_wifi_listen_interval_time_unit_t + * @brief Enumeration of listen interval time units. + */ +typedef enum { + SL_WIFI_LISTEN_INTERVAL_TIME_UNIT_BEACON, ///< Time units specified in beacon periods + SL_WIFI_LISTEN_INTERVAL_TIME_UNIT_DTIM ///< Time units specified in Delivery Traffic Indication Message (DTIM) periods +} sl_wifi_listen_interval_time_unit_t; + +/** + * @enum sl_wifi_wps_mode_t + * @brief Enumeration of Wi-Fi WPS (Wi-Fi Protected Setup) modes. + */ +typedef enum { + SL_WIFI_WPS_PIN_MODE, ///< WPS pin mode: Requires a PIN to be entered on the client device. + SL_WIFI_WPS_PUSH_BUTTON_MODE, ///< WPS push button mode: Requires the user to press a physical or virtual button on both the AP and the client device. +} sl_wifi_wps_mode_t; + +/** + * @enum sl_wifi_event_group_t + * @brief Enumeration of Wi-Fi event groups. + */ +typedef enum { + SL_WIFI_SCAN_RESULT_EVENTS, ///< Event group for Wi-Fi scan results + SL_WIFI_JOIN_EVENTS, ///< Event group for Wi-Fi join status + SL_WIFI_RX_PACKET_EVENTS, ///< Event group for Wi-Fi received packet. This feature is not supported in current release + SL_WIFI_COMMAND_RESPONSE_EVENTS, ///< Event group for Wi-Fi command response. This feature is not supported in current release + SL_WIFI_STATS_RESPONSE_EVENTS, ///< Event group for Wi-Fi statistics response + SL_WIFI_HTTP_OTA_FW_UPDATE_EVENTS, ///< Event group for Wi-Fi OTA firmware update status via HTTP + SL_WIFI_NETWORK_DOWN_EVENTS, ///< Event group for Wi-Fi network down. This feature is not supported in current release + SL_WIFI_NETWORK_UP_EVENTS, ///< Event group for Wi-Fi network up. This feature is not supported in current release + SL_WIFI_CLIENT_CONNECTED_EVENTS, ///< Event group for Wi-Fi client connected status + SL_WIFI_TWT_RESPONSE_EVENTS, ///< Event group for Wi-Fi TWT response + SL_WIFI_CLIENT_DISCONNECTED_EVENTS, ///< Event group for Wi-Fi client disconnection status + SL_WIFI_TRANSCEIVER_EVENTS, ///< Event group for Wi-Fi transceiver events + SL_WIFI_EVENT_GROUP_COUNT, ///< Event group for Wi-Fi maximum default group count. Used internally by SDK + SL_WIFI_EVENT_FAIL_INDICATION_EVENTS = (1 << 31), ///< Event group for Wi-Fi fail indication +} sl_wifi_event_group_t; + +/** + * @enum sl_wifi_event_t + * @brief Enumeration of Wi-Fi events. + * + * @note Each event group has a matching event. + * @note Each event group may be a source of multiple different events. + */ +typedef enum { + SL_WIFI_SCAN_RESULT_EVENT = + SL_WIFI_SCAN_RESULT_EVENTS, ///< Event for Wi-Fi scan result. Data would be type of @ref sl_wifi_scan_result_t + SL_WIFI_JOIN_EVENT = SL_WIFI_JOIN_EVENTS, ///< Event for Wi-Fi join status. Data would be of type string + SL_WIFI_RX_PACKET_EVENT = + SL_WIFI_RX_PACKET_EVENTS, ///< Event for Wi-Fi received packet. This feature is not supported in current release + SL_WIFI_COMMAND_RESPONSE_EVENT = + SL_WIFI_COMMAND_RESPONSE_EVENTS, ///< Event for Wi-Fi command response. This feature is not supported in current release + SL_WIFI_STATS_RESPONSE_EVENT = + SL_WIFI_STATS_RESPONSE_EVENTS, ///< Event for Wi-Fi statistics response. Data would be NULL + SL_WIFI_HTTP_OTA_FW_UPDATE_EVENT = + SL_WIFI_HTTP_OTA_FW_UPDATE_EVENTS, ///< Event for Wi-Fi OTA firmware update status via HTTP. Data would be NULL + SL_WIFI_NETWORK_DOWN_EVENT = + SL_WIFI_NETWORK_DOWN_EVENTS, ///< Event for Wi-Fi network down. This feature is not supported in current release + SL_WIFI_NETWORK_UP_EVENT = + SL_WIFI_NETWORK_UP_EVENTS, ///< Event for Wi-Fi network up. This feature is not supported in current release + SL_WIFI_CLIENT_CONNECTED_EVENT = + SL_WIFI_CLIENT_CONNECTED_EVENTS, ///< Event for Wi-Fi client connected status in Access Point Mode. Data would be of type [sl_mac_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-types#sl-mac-address-t). + SL_WIFI_TWT_RESPONSE_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS, ///< Event for Wi-Fi TWT response in WiFi Client mode. Data would be NULL + SL_WIFI_CLIENT_DISCONNECTED_EVENT = + SL_WIFI_CLIENT_DISCONNECTED_EVENTS, ///< Event for Wi-Fi client disconnection status in Access Point Mode. Data would of type [sl_mac_address_t](../wiseconnect-api-reference-guide-common/ieee802#sl-mac-address-t). + SL_WIFI_TRANSCEIVER_EVENT = + SL_WIFI_TRANSCEIVER_EVENTS, ///< Event for Wi-Fi transceiver TX/RX events in WiFi Client mode. + // TWT specific events + SL_WIFI_TWT_UNSOLICITED_SESSION_SUCCESS_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (1 + << 16), ///< Event for TWT unsolicited session success. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_AP_REJECTED_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (4 + << 16), ///< Event for TWT AP rejection. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_OUT_OF_TOLERANCE_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (5 + << 16), ///< Event for TWT out of tolerance. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_RESPONSE_NOT_MATCHED_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (6 + << 16), ///< Event for TWT response not matched. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_UNSUPPORTED_RESPONSE_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (10 + << 16), ///< Event for TWT unsupported response. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_TEARDOWN_SUCCESS_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (11 + << 16), ///< Event for TWT teardown success. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_AP_TEARDOWN_SUCCESS_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (12 + << 16), ///< Event for TWT AP teardown success. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_FAIL_MAX_RETRIES_REACHED_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (15 + << 16), ///< Event for TWT maximum retries reached. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_INACTIVE_DUE_TO_ROAMING_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (16 + << 16), ///< Event for TWT inactive due to roaming. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_INACTIVE_DUE_TO_DISCONNECT_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (17 + << 16), ///< Event for TWT inactive due to disconnect. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_INACTIVE_NO_AP_SUPPORT_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (18 + << 16), ///< Event for TWT inactive due to no AP support. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_RESCHEDULE_TWT_SUCCESS_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (19 + << 16), ///< Event for TWT suspend resume success. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_INFO_FRAME_EXCHANGE_FAILED_EVENT = + SL_WIFI_TWT_RESPONSE_EVENTS + | (20 + << 16), ///< Event for TWT info frame exchange failure. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + SL_WIFI_TWT_EVENTS_END = + SL_WIFI_TWT_RESPONSE_EVENTS + | (21 + << 16), ///< Event for TWT event end. Data would be of type [sl_si91x_twt_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-twt-response-t). + + // Stats specific events + SL_WIFI_STATS_EVENT = SL_WIFI_STATS_RESPONSE_EVENTS + | (1 << 16), ///< Event for Wi-Fi statistics. This feature is not supported in current release + SL_WIFI_STATS_ASYNC_EVENT = + SL_WIFI_STATS_RESPONSE_EVENTS + | (2 + << 16), ///< Event for Wi-Fi asynchronous statistics. Data would be of type [sl_si91x_async_stats_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-async-stats-response-t) + SL_WIFI_STATS_ADVANCE_EVENT = + SL_WIFI_STATS_RESPONSE_EVENTS + | (3 + << 16), ///< Event for Wi-Fi advance statistics. Data would be of type [sl_si91x_advance_stats_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-advance-stats-response-t) + SL_WIFI_STATS_TEST_MODE_EVENT = + SL_WIFI_STATS_RESPONSE_EVENTS + | (4 << 16), ///< Event for Wi-Fi test mode statistics. This feature is not supported in current release + SL_WIFI_STATS_MODULE_STATE_EVENT = + SL_WIFI_STATS_RESPONSE_EVENTS + | (5 + << 16), ///< Event for Wi-Fi module state statistics. Data would be of type [sl_si91x_module_state_stats_response_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91x-module-state-stats-response-t) + + SL_WIFI_TRANSCEIVER_RX_DATA_RECEIVE_CB = SL_WIFI_TRANSCEIVER_EVENTS | (1 << 16), + SL_WIFI_TRANSCEIVER_TX_DATA_STATUS_CB = SL_WIFI_TRANSCEIVER_EVENTS | (2 << 16), + + // Single bit to indicate relevant event is related to a failure condition + SL_WIFI_EVENT_FAIL_INDICATION = (1 << 31), ///< Event for Wi-Fi event failure indication + SL_WIFI_INVALID_EVENT = 0xFFFFFFFF, ///< Invalid Wi-Fi event. Data would be NULL +} sl_wifi_event_t; + +/** + * @enum sl_wifi_reschedule_twt_action_t + * @brief Enumeration defining actions related to Target Wake Time (TWT). + */ +typedef enum { + SL_WIFI_SUSPEND_INDEFINITELY, ///< Suspend TWT indefinitely, effectively disabling TWT functionality until explicitly resumed. + SL_WIFI_SUSPEND_FOR_DURATION, ///< Suspend TWT for a specified duration, after which it can automatically resume. + SL_WIFI_RESUME_IMMEDIATELY ///< Resume TWT immediately, allowing devices to continue adhering to TWT schedules. +} sl_wifi_reschedule_twt_action_t; + +/** + * @enum sl_wifi_data_rate_t + * @brief Enumeration of Wi-Fi data rates. + */ +typedef enum { + SL_WIFI_DATA_RATE_1 = 0, ///< Wi-Fi 1 Mbps transfer rate + SL_WIFI_DATA_RATE_2 = 2, ///< Wi-Fi 2 Mbps transfer rate + SL_WIFI_DATA_RATE_5_5 = 4, ///< Wi-Fi 5.5 Mbps transfer rate + SL_WIFI_DATA_RATE_11 = 6, ///< Wi-Fi 11 Mbps transfer rate + SL_WIFI_DATA_RATE_6 = 139, ///< Wi-Fi 6 Mbps transfer rate + SL_WIFI_DATA_RATE_9 = 143, ///< Wi-Fi 9 Mbps transfer rate + SL_WIFI_DATA_RATE_12 = 138, ///< Wi-Fi 12 Mbps transfer rate + SL_WIFI_DATA_RATE_18 = 142, ///< Wi-Fi 18 Mbps transfer rate + SL_WIFI_DATA_RATE_24 = 137, ///< Wi-Fi 24 Mbps transfer rate + SL_WIFI_DATA_RATE_36 = 141, ///< Wi-Fi 36 Mbps transfer rate + SL_WIFI_DATA_RATE_48 = 136, ///< Wif-Fi 48 Mbps transfer rate + SL_WIFI_DATA_RATE_54 = 140, ///< Wi-Fi 54 Mbps transfer rate + SL_WIFI_DATA_RATE_MCS0 = 256, ///< Wi-Fi MCS index 0 transfer rate + SL_WIFI_DATA_RATE_MCS1 = 257, ///< Wi-Fi MCS index 1 transfer rate + SL_WIFI_DATA_RATE_MCS2 = 258, ///< Wi-Fi MCS index 2 transfer rate + SL_WIFI_DATA_RATE_MCS3 = 259, ///< Wi-Fi MCS index 3 transfer rate + SL_WIFI_DATA_RATE_MCS4 = 260, ///< Wi-Fi MCS index 4 transfer rate + SL_WIFI_DATA_RATE_MCS5 = 261, ///< Wi-Fi MCS index 5 transfer rate + SL_WIFI_DATA_RATE_MCS6 = 262, ///< Wi-Fi MCS index 6 transfer rate + SL_WIFI_DATA_RATE_MCS7 = 263, ///< Wi-Fi MCS index 7 transfer rate + SL_WIFI_DATA_RATE_MCS7_SG = 775, +} sl_wifi_data_rate_t; + +/** + * @enum sl_wifi_tx_test_mode_t + * @brief Enumeration of Wi-Fi TX test modes. + */ +typedef enum { + SL_WIFI_TEST_BURST_MODE = 0, ///< Burst Mode + SL_WIFI_TEST_CONTINOUS_MODE = 1, ///< Continuous Mode + SL_WIFI_TEST_CONTINOUS_WAVE_MODE = 2, ///< CW Mode + SL_WIFI_TEST_CONTINOUS_WAVE_MODE_OFF_CENTER_LOW = 3, ///< CW Mode center frequency - 2.5 MHZ Mode + SL_WIFI_TEST_CONTINOUS_WAVE_MODE_OFF_CENTER_HIGH = 4, ///< CW Mode center frequency + 5 MHZ Mode +} sl_wifi_tx_test_mode_t; + +/** + * @enum sl_wifi_high_throughput_capability_types_t + * @brief Enumeration of High Throughput (HT) capabilities. + */ +typedef enum { + SL_WIFI_HT_CAPS_NUM_RX_STBC = (1 << 8), ///< Number of RX Space-Time Block Coding (STBC) streams supported + SL_WIFI_HT_CAPS_SHORT_GI_20MHZ = (1 << 5), ///< Support for Short Guard Interval (GI) in 20 MHz channels + SL_WIFI_HT_CAPS_GREENFIELD_EN = + (1 << 4), ///< Support for Greenfield mode, which improves efficiency by eliminating legacy preambles + SL_WIFI_HT_CAPS_SUPPORT_CH_WIDTH = (1 << 1), ///< Support for wider channel bandwidths +} sl_wifi_high_throughput_capability_types_t; + +/** + * @enum sl_wifi_multicast_filter_command_t + * @brief Enumeration of multicast filter command types. + */ +typedef enum { + SL_WIFI_MULTICAST_MAC_ADD_BIT = 0, ///< To set particular bit in multicast bitmap + SL_WIFI_MULTICAST_MAC_CLEAR_BIT = 1, ///< To reset particular bit in multicast bitmap + SL_WIFI_MULTICAST_MAC_CLEAR_ALL = 2, ///< To clear all the bits in multicast bitmap + SL_WIFI_MULTICAST_MAC_SET_ALL = 3, ///< To set all the bits in multicast bitmap +} sl_wifi_multicast_filter_command_t; + +/** + * @enum sl_wifi_eap_client_flag_t + * @brief Option flags for EAP (Extensible Authentication Protocol) client interfaces. + */ +typedef enum { + SL_WIFI_EAP_ENABLE_OKC = (1 << 0), ///< Wi-Fi EAP Client flag to enable Opportunistic Key Caching (OKC) + SL_WIFI_EAP_ENABLE_PEAP_CA = + (1 << 1), ///< Wi-Fi EAP Client flag to enable CA certificate requirement for PEAP connection + SL_WIFI_EAP_DHE_RSA_AES256_SHA256 = + (1 << 2), ///< Wi-Fi EAP Client flag to use DHE-RSA-AES256-SHA256 Cipher for EAP connection + SL_WIFI_EAP_DHE_RSA_AES128_SHA256 = + (1 << 3), ///< Wi-Fi EAP Client flag to use DHE-RSA-AES128-SHA256 Cipher for EAP connection + SL_WIFI_EAP_DHE_RSA_AES256_SHA = + (1 << 4), ///< Wi-Fi EAP Client flag to use DHE-RSA-AES256-SHA Cipher for EAP connection + SL_WIFI_EAP_DHE_RSA_AES128_SHA = + (1 << 5), ///< Wi-Fi EAP Client flag to use DHE-RSA-AES128-SHA Cipher for EAP connection + SL_WIFI_EAP_AES256_SHA256 = (1 << 6), ///< Wi-Fi EAP Client flag to use AES256-SHA256 Cipher for EAP connection + SL_WIFI_EAP_AES128_SHA256 = (1 << 7), ///< Wi-Fi EAP Client flag to use AES128-SHA256 Cipher for EAP connection + SL_WIFI_EAP_AES256_SHA = (1 << 8), ///< Wi-Fi EAP Client flag to use AES256-SHA Cipher for EAP connection + SL_WIFI_EAP_AES128_SHA = (1 << 9), ///< Wi-Fi EAP Client flag to use AES128-SHA Cipher for EAP connection + SL_WIFI_EAP_RC4_SHA = (1 << 10), ///< Wi-Fi EAP Client flag to use RC4-SHA Cipher for EAP connection + SL_WIFI_EAP_DES_CBC3_SHA = (1 << 11), ///< Wi-Fi EAP Client flag to use DES-CBC3-SHA Cipher for EAP connection + SL_WIFI_EAP_RC4_MD5 = (1 << 12) ///< Wi-Fi EAP Client flag to use RC4-MD5 Cipher for EAP connection +} sl_wifi_eap_client_flag_t; + +/** + * @def SL_WIFI_AUTO_CHANNEL + * @brief Macro to enable Auto Channel Selection (ACS). + * + * This macro defines the value to enable the Auto Channel Selection (ACS) feature, which automatically determines the operating channel for the Access Point (AP). + * + * @note + * - The channel in which the AP operates. A value of zero enables the ACS feature. + * - If ACS is enabled, AP start may take approximately 9 seconds as the device scans all channels to select the best channel. + */ +#define SL_WIFI_AUTO_CHANNEL 0 + +/** + * @def SL_WIFI_DEFAULT_CHANNEL_BITMAP + * @brief Macro to define the default channel bitmap for scanning. + * + * @note + * - The selected or preferred channels to be scanned before the client connects to the AP. A value of zero means to scan on all available channels. + */ +#define SL_WIFI_DEFAULT_CHANNEL_BITMAP 0 + +/** + * @def SL_WIFI_ARGS_CHECK_NULL_POINTER(ptr) + * @brief Macro to check for null pointers in API inputs. + */ +#define SL_WIFI_ARGS_CHECK_NULL_POINTER(ptr) \ + do { \ + if (ptr == NULL) { \ + return SL_STATUS_NULL_POINTER; \ + } \ + } while (0) + +/** + * @def SL_WIFI_ARGS_CHECK_INVALID_INTERFACE(interface) + * @brief Macro to check for invalid Wi-Fi interfaces in API inputs. + */ +#define SL_WIFI_ARGS_CHECK_INVALID_INTERFACE(interface) \ + { \ + if (!((interface == SL_WIFI_CLIENT_INTERFACE) || (interface == SL_WIFI_AP_INTERFACE) \ + || (interface == SL_WIFI_CLIENT_2_4GHZ_INTERFACE) || (interface == SL_WIFI_AP_2_4GHZ_INTERFACE) \ + || (interface == SL_WIFI_2_4GHZ_INTERFACE))) { \ + return SL_STATUS_WIFI_UNKNOWN_INTERFACE; \ + } \ + } + +/** @} */ +#endif // _SL_WIFI_CONSTANTS_H_ diff --git a/wiseconnect/components/protocol/wifi/inc/sl_wifi_credentials.h b/wiseconnect/components/protocol/wifi/inc/sl_wifi_credentials.h new file mode 100644 index 000000000..af564f823 --- /dev/null +++ b/wiseconnect/components/protocol/wifi/inc/sl_wifi_credentials.h @@ -0,0 +1,113 @@ +/** + * @file sl_wifi_credentials.h + * @brief This file defines the Credential Management for Wi-Fi operations. + * + * This file contains the definitions and structures used for managing Credentials. + * It includes enumerations for buffer types and structures for Credential management. + * + * EVALUATION AND USE OF THIS SOFTWARE IS SUBJECT TO THE TERMS AND + * CONDITIONS OF THE CONTROLLING LICENSE AGREEMENT FOUND AT LICENSE.md + * IN THIS SDK. IF YOU DO NOT AGREE TO THE LICENSE TERMS AND CONDITIONS, + * PLEASE RETURN ALL SOURCE FILES TO SILICON LABORATORIES. + * + * (c) Copyright 2024, Silicon Laboratories Inc. All rights reserved. + */ + +#ifndef SL_WIFI_CREDENTIALS_H +#define SL_WIFI_CREDENTIALS_H + +#include "sl_wifi_types.h" + +/** + * \addtogroup WIFI_CREDENTIAL_FUNCTIONS Wi-Fi Credential + * \ingroup SL_WIFI_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Store a credential in specified credential identifier. + * + * @details + * This function stores the credential type and data for the specified credential ID. + * The credential data can include client credentials, access point credentials and user credentials. + * + * Repeatedly calling this API with the same ID will overwrite the existing credential type and data. + * + * @pre Pre-conditions: + * - @ref sl_wifi_init should be called before this API. + * + * @param[in] id + * Credential identifier as identified by @ref sl_wifi_credential_id_t. + * + * @param[in] type + * Credential type as identified by @ref sl_wifi_credential_type_t. + * + * @param[in] credential + * Pointer to the credential data object. + * + * @param[in] credential_length + * Length of the credential data object. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_wifi_set_credential(sl_wifi_credential_id_t id, + sl_wifi_credential_type_t type, + const void *credential, + uint32_t credential_length); + +/***************************************************************************/ /** + * @brief + * Retrieve a stored credential. + * + * @details + * This function retrieves the credential data for the specified credential ID. + * The retrieved credential data is stored in the provided credential object. + * + * @pre Pre-conditions: + * - @ref sl_wifi_init should be called before this API. + * + * @param[in] id + * Credential identifier as identified by @ref sl_wifi_credential_id_t. + * + * @param[out] type + * Credential type as identified by @ref sl_wifi_credential_type_t. + * + * @param[out] credential + * Pointer to location where credential data is stored. + * + * @param[in,out] credential_length + * in: Number of bytes available at credential, + * out: Number of bytes written. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_wifi_get_credential(sl_wifi_credential_id_t id, + sl_wifi_credential_type_t *type, + void *credential, + uint32_t *credential_length); + +/***************************************************************************/ /** + * @brief + * Delete a stored credential. + * + * @details + * This function deletes the credential data for the specified credential ID and type. + * Once deleted, the credential cannot be used for any operations. + * + * @pre Pre-conditions: + * - + * @ref sl_wifi_init should be called before this API. + * + * @param[in] id + * Credential identifier as identified by @ref sl_wifi_credential_id_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_wifi_delete_credential(sl_wifi_credential_id_t id); + +/** @} */ + +#endif //SL_WIFI_CREDENTIALS_H \ No newline at end of file diff --git a/wiseconnect/components/protocol/wifi/inc/sl_wifi_host_interface.h b/wiseconnect/components/protocol/wifi/inc/sl_wifi_host_interface.h new file mode 100644 index 000000000..c5e485256 --- /dev/null +++ b/wiseconnect/components/protocol/wifi/inc/sl_wifi_host_interface.h @@ -0,0 +1,79 @@ +/***************************************************************************/ /** + * @file sl_wifi_host_interface.h + * @brief This file defines the host interface for Wi-Fi operations. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_status.h" +#include "sl_slist.h" +#include "sl_common.h" +#include +#include + +/** \addtogroup SL_WIFI_TYPES + * @{ */ + +/** + * @enum sl_wifi_buffer_type_t + * @brief Enumeration for types of Wi-Fi buffers. + */ +typedef enum { + SL_WIFI_TX_FRAME_BUFFER, ///< Buffer for sending socket data to NWP + SL_WIFI_RX_FRAME_BUFFER, ///< Buffer for storing response from NWP + SL_WIFI_CONTROL_BUFFER, ///< Buffer for sending command to NWP + SL_WIFI_SCAN_RESULT_BUFFER, ///< Buffer for storing scan results +} sl_wifi_buffer_type_t; + +/** + * @struct sl_wifi_buffer_t + * @brief Structure representing a Wi-Fi buffer. + */ +typedef struct { + sl_slist_node_t node; ///< Pointer to the node of the list of which the buffer is part of + uint32_t length; ///< Size of the buffer in bytes + uint8_t + type; ///< Indicates the buffer type (SL_WIFI_TX_FRAME_BUFFER, SL_WIFI_RX_FRAME_BUFFER, and so on.) corresponding to the buffer. + uint8_t id; ///< Buffer identifier. Can be used to uniquely identify a buffer. Loops every 256 packets. + uint8_t _reserved[2]; ///< Reserved. + uint8_t data[]; ///< Stores the data (header + payload) to be send to NWP +} sl_wifi_buffer_t; + +/** + * @struct sl_wifi_buffer_configuration_t + * @brief Structure representing the Wi-Fi buffer configuration. + */ +typedef struct { + uint8_t tx_buffer_quota; ///< Indicates the limit on buffers used for sending the data to NWP + uint8_t rx_buffer_quota; ///< Indicates the limit on buffers used for storing the response from NWP + uint8_t control_buffer_quota; ///< Indicates the limit on buffers used for sending the command to NWP + uint32_t block_size; ///< Indicates the block size in bytes + void *buffer_memory; ///< Pointer to the chunk of memory allocated on the first invocation of malloc +} sl_wifi_buffer_configuration_t; + +/** @} */ diff --git a/wiseconnect/components/protocol/wifi/inc/sl_wifi_types.h b/wiseconnect/components/protocol/wifi/inc/sl_wifi_types.h new file mode 100644 index 000000000..5e0463165 --- /dev/null +++ b/wiseconnect/components/protocol/wifi/inc/sl_wifi_types.h @@ -0,0 +1,878 @@ +/******************************************************************************** + * @file sl_wifi_types.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_wifi_constants.h" +#include "sl_wifi_host_interface.h" +#include "sl_ieee802_types.h" +#include "sl_status.h" +#include "sl_ip_types.h" +#include + +// Default Timeout Configuration +#define SL_WIFI_DEFAULT_AUTH_ASSOCIATION_TIMEOUT 0xFFFF +#define SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME 0xFFFF +#define SL_WIFI_DEFAULT_KEEP_ALIVE_TIMEOUT 0xFFFF +#define SL_WIFI_DEFAULT_PASSIVE_CHANNEL_SCAN_TIME 0 + +/// Wi-Fi transceiver mode configurations +#define MAX_PAYLOAD_LEN 2020 +#define MAC_INFO_ENABLE BIT(0) +#define BCAST_INDICATION BIT(1) +#define CONFIRM_REQUIRED_TO_HOST BIT(2) +#define QOS_ENABLE BIT(4) +#define MAC80211_HDR_MIN_LEN 24 +#define MAC80211_HDR_QOS_CTRL_LEN 2 +#define MAC80211_HDR_ADDR4_LEN 6 +#define WME_AC_BE 0 /* best effort */ +#define WME_AC_BK 1 /* background */ +#define WME_AC_VI 2 /* video */ +#define WME_AC_VO 3 /* voice */ +#define WME_AC_TO_TID(_ac) (((_ac) == WME_AC_VO) ? 6 : ((_ac) == WME_AC_VI) ? 5 : ((_ac) == WME_AC_BK) ? 1 : 0) +#define WME_AC_TO_QNUM(_ac) (((_ac) == WME_AC_BK) ? 0 : ((_ac) == WME_AC_BE) ? 1 : ((_ac) == WME_AC_VI) ? 2 : 3) +#define FC_TYPE_DATA BIT(3) +#define FC_SUBTYPE_QOS_DATA BIT(7) +#define FC_TO_DS BIT(8) +#define FC_FROM_DS BIT(9) +#define TX_DATA_CTRL_FLAG_QOS_BIT BIT(1) +#define IS_QOS_PKT(ctrl_flags) (ctrl_flags & TX_DATA_CTRL_FLAG_QOS_BIT) +#define IS_PEER_DS_SUPPORT_ENABLED(bitmap) (bitmap & SL_SI91X_FEAT_TRANSCEIVER_MAC_PEER_DS_SUPPORT) +#define IS_4ADDR(ctrl_flags) (ctrl_flags & BIT(0)) +#define IS_FIXED_DATA_RATE(ctrl_flags) (ctrl_flags & BIT(2)) +#define IS_TODS(ctrl_flags) (ctrl_flags & BIT(3)) +#define IS_FROMDS(ctrl_flags) (ctrl_flags & BIT(4)) +#define IS_CFM_TO_HOST_SET(ctrl_flags) (ctrl_flags & BIT(5)) +#define IS_BCAST_MCAST_MAC(addr) (addr & BIT(0)) +#define IS_MAC_ZERO(mac) (!(mac[0] | mac[1] | mac[2] | mac[3] | mac[4] | mac[5])) +#define MAX_RETRANSMIT_COUNT 15 +#define MAX_CW_EXPN_COUNT 15 +#define MAX_AIFSN 15 +#define TRANSCEIVER_PEER_ADD_FLAG BIT(0) +#define TRANSCEIVER_PEER_AUTO_RATE_FLAG BIT(1) +#define TRANSCEIVER_MCAST_FILTER_EN BIT(0) +#define TRANSCEIVER_MCAST_FILTER_ADDR_LIMIT 2 +#define TRANSCEIVER_TX_DATA_EXT_DESC_SIZE 4 +#define SL_STATUS_ACK_ERR 0x1 +#define SL_STATUS_CS_BUSY 0x2 +#define SL_STATUS_UNKNOWN_PEER 0x3 +#define TRANSCEIVER_RX_PKT_TA_MATCH_BIT BIT(20) + +/** @addtogroup SL_WIFI_CONSTANTS + * @{ */ +#define SL_WIFI_TRANSCEIVER_CHANNEL_NO 14 ///< Wi-Fi transceiver default channel +#define SL_WIFI_TRANSCEIVER_TX_POWER 20 ///< Wi-Fi transceiver default TX power +#define SL_WIFI_TRANSCEIVER_DEFAULT_RETRANSMIT_COUNT 15 ///< Wi-Fi transceiver default retransmit count +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_BE_CWMIN 4 ///< Wi-Fi transceiver default BE cwmin contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_BE_CWMAX 6 ///< Wi-Fi transceiver default BE cwmax contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_BE_AIFSN 3 ///< Wi-Fi transceiver default BE aifsn contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_BK_CWMIN 4 ///< Wi-Fi transceiver default BK cwmin contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_BK_CWMAX 10 ///< Wi-Fi transceiver default BK cwmax contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_BK_AIFSN 7 ///< Wi-Fi transceiver default BK aifsn contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_VI_CWMIN 3 ///< Wi-Fi transceiver default VI cwmin contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_VI_CWMAX 4 ///< Wi-Fi transceiver default VI cwmax contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_VI_AIFSN 1 ///< Wi-Fi transceiver default VI aifsn contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_VO_CWMIN 2 ///< Wi-Fi transceiver default VO cwmin contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_VO_CWMAX 3 ///< Wi-Fi transceiver default VO cwmax contention param value +#define SL_WIFI_TRANSCEIVER_DEFAULT_QOS_VO_AIFSN 1 ///< Wi-Fi transceiver default VO aifsn contention param value +/** @} */ + +/** @addtogroup SL_WIFI_TYPES Types + * @{ */ + +/** + * @typedef sl_wifi_event_handler_t + * @brief Generic callback for handling Wi-Fi events. + * + * @param event + * Wi-Fi event of type @ref sl_wifi_event_t. + * @param buffer + * Pointer to a Wi-Fi buffer contains information related to the event, of type @ref sl_wifi_buffer_t + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * In case of event failure, SL_WIFI_FAIL_EVENT_STATUS_INDICATION bit is set in the event. + * The data would be of type sl_status_t, and data_length can be ignored. + */ +typedef sl_status_t (*sl_wifi_event_handler_t)(sl_wifi_event_t event, sl_wifi_buffer_t *buffer); + +/// Wi-Fi credential handle +typedef uint32_t sl_wifi_credential_id_t; + +/** + * @struct sl_wifi_channel_t + * @brief Wi-Fi channel configuration. + */ +typedef struct { + uint16_t channel; ///< Channel number + sl_wifi_band_t band; ///< Wi-Fi radio band of type @ref sl_wifi_band_t + sl_wifi_bandwidth_t bandwidth; ///< Channel bandwidth of type @ref sl_wifi_bandwidth_t +} sl_wifi_channel_t; + +/** + * @struct sl_wifi_ssid_t + * @brief SSID data structure. + * + * Specifies the Service Set Identifier (SSID) used in Wi-Fi networks. + */ +typedef struct { + uint8_t value[32]; ///< SSID value + uint8_t length; ///< Length of the SSID +} sl_wifi_ssid_t; + +/** + * @struct sl_wifi_roam_configuration_t + * @brief Wi-Fi roaming configuration structure. + */ +typedef struct { + int32_t + trigger_level; ///< RSSI level to trigger the roam algorithm, setting the value to SL_WIFI_NEVER_ROAM will disable roaming configuration + uint32_t trigger_level_change; ///< RSSI level delta change to trigger the roam algorithm +} sl_wifi_roam_configuration_t; + +/** + * @struct sl_wifi_firmware_version_t + * @brief Wi-Fi firmware version information. + * + * Contains the detailed information about the Wi-Fi firmware version. + */ +typedef struct { + uint8_t chip_id; ///< Chip ID + uint8_t rom_id; ///< ROM ID + uint8_t major; ///< Major version number + uint8_t minor; ///< Minor version number + uint8_t security_version; ///< Security enabled or disabled + uint8_t patch_num; ///< Patch number + uint8_t customer_id; ///< Customer ID + uint16_t build_num; ///< Build number +} sl_wifi_firmware_version_t; + +/** + * @struct sl_wifi_scan_result_t + * @brief Wi-Fi scan result structure. + * + * Indicates the results of a Wi-Fi scan operation. + */ +typedef struct { + uint32_t scan_count; ///< Number of available scan results + uint32_t reserved; ///< Reserved + struct { + uint8_t rf_channel; ///< Channel number of the AP + uint8_t security_mode; ///< Security mode of the AP + uint8_t rssi_val; ///< RSSI value of the AP + uint8_t network_type; ///< AP network type + uint8_t ssid[34]; ///< SSID of the AP + uint8_t bssid[6]; ///< BSSID of the AP + uint8_t reserved[2]; ///< Reserved + } scan_info[]; ///< Array of scan result data +} sl_wifi_scan_result_t; + +/// Extended Wi-Fi scan result +typedef struct { + uint8_t rf_channel; ///< Channel number of the AP + uint8_t security_mode; ///< Security mode of the AP + uint8_t rssi; ///< RSSI value of the AP + uint8_t network_type; ///< Network type of the AP + uint8_t ssid[34]; ///< SSID of the AP + uint8_t bssid[6]; ///< BSSID of the AP +} sl_wifi_extended_scan_result_t; + +/// Extended Wi-Fi scan result parameters +typedef struct { + sl_wifi_extended_scan_result_t + *scan_results; ///< Pointer to an array containing scan results of type @ref sl_wifi_extended_scan_result_t + uint16_t array_length; ///< Length of the scan results array provided by the user. + uint16_t *result_count; ///< Pointer to store the total count of scan results returned. + uint8_t *channel_filter; ///< Pointer to Channel number (Filter based on Channel number of the AP). + uint8_t *security_mode_filter; ///< Pointer to Security mode (Filter based on the Security mode of the AP). + uint8_t *rssi_filter; ///< Pointer to RSSI (Filter for APs with an RSSI greater than or equal to given RSSI value). + uint8_t *network_type_filter; ///< Pointer to Network type (Filter based on APs network type). +} sl_wifi_extended_scan_result_parameters_t; + +/** + * @struct sl_wifi_scan_configuration_t + * @brief Wi-Fi scan configuration structure. + * + * Indicates the configuration parameters for a Wi-Fi scan operation. + * + * @note The Quick Scan feature is enabled when a specific channel and SSID are given for scanning. + * SiWx91x scans for the AP given in the scan API and posts the scan results immediately + * after finding the access point. + * @note The `channel_bitmap_2g4` uses the lower 14 bits to represent channels from 1 to 14, + * where channel 1 = (1 << 0), channel 2 = (1 << 1), and so on. + * @note 5GHz is not supported. + * + * | Channel Number 2.4 GHz | channel_bitmap_2g4 | + * |------------------------|-----------------------| + * | 1 | (1 << 0) | + * | 2 | (1 << 1) | + * | 3 | (1 << 2) | + * | 4 | (1 << 3) | + * | 5 | (1 << 4) | + * | 6 | (1 << 5) | + * | 7 | (1 << 6) | + * | 8 | (1 << 7) | + * | 9 | (1 << 8) | + * | 10 | (1 << 9) | + * | 11 | (1 << 10) | + * | 12 | (1 << 11) | + * | 13 | (1 << 12) | + * | 14 | (1 << 13) | + */ +typedef struct { + sl_wifi_scan_type_t type; ///< Scan type to be configured of type @ref sl_wifi_scan_type_t + uint32_t flags; ///< Reserved + uint32_t periodic_scan_interval; ///< Duration in milliseconds between periodic scans + uint16_t channel_bitmap_2g4; ///< Bitmap of selected 2.4GHz channels + uint32_t channel_bitmap_5g[8]; ///< Bitmap of selected 5GHz channels (currently not supported) + uint8_t lp_mode; ///< Enable LP mode, 1 - Enable LP mode, 0 - Disable LP mode +} sl_wifi_scan_configuration_t; + +/** + * @struct sl_wifi_advanced_scan_configuration_t + * @brief Wi-Fi advanced scan configuration options. + * + * Indicates the configuration parameters for an advanced Wi-Fi scan operation. + */ +typedef struct { + int32_t trigger_level; ///< RSSI level to trigger advanced scan + uint32_t trigger_level_change; ///< RSSI level change to trigger advanced scan + uint16_t active_channel_time; ///< Time spent on each channel during active scan (milliseconds) + uint16_t passive_channel_time; ///< Time spent on each channel during passive scan (milliseconds) + uint8_t enable_instant_scan; ///< Flag to start advanced scan immediately + uint8_t + enable_multi_probe; ///< Flag to send multiple probes to AP. If the value is set to 1, a probe request would be sent to all access points in addition to the connected SSID. +} sl_wifi_advanced_scan_configuration_t; + +/** + * @struct sl_wifi_ap_configuration_t + * @brief Wi-Fi Access Point configuration structure. + * + * Indicates the configuration parameters for setting up a Wi-Fi Access Point (AP). + */ +typedef struct { + sl_wifi_ssid_t ssid; ///< SSID (Service Set Identifier) of the Access Point + sl_wifi_security_t security; ///< Security mode of the Access Point + sl_wifi_encryption_t encryption; ///< Encryption mode of the Access Point + sl_wifi_channel_t channel; ///< Channel configuration of the Access Point + sl_wifi_rate_protocol_t rate_protocol; ///< Rate protocol of the Access Point + sl_wifi_ap_flag_t options; ///< Optional flags for AP configuration + sl_wifi_credential_id_t credential_id; ///< ID of secure credentials + uint8_t + keepalive_type; ///< Keep alive type of the access point. One of the values from [sl_si91x_ap_keepalive_type_t](../wiseconnect-api-reference-guide-si91x-driver/sl-si91-x-types#sl-si91x-ap-keepalive-type-t) + uint16_t beacon_interval; ///< Beacon interval of the access point in milliseconds + uint32_t client_idle_timeout; ///< Duration in milliseconds to kick idle client + uint16_t dtim_beacon_count; ///< Number of beacons per DTIM + uint8_t maximum_clients; ///< Maximum number of associated clients + uint8_t beacon_stop; ///< Flag to stop beaconing when there are no associated clients + sl_wifi_tdi_t + tdi_flags; ///< Flags to enable Transition Disable Indication (TDI). One of the values from @ref sl_wifi_tdi_t + uint8_t is_11n_enabled; ///< A flag to enable 11n. +} sl_wifi_ap_configuration_t; + +/** + * @struct sl_wifi_advanced_ap_configuration_t + * @brief Wi-Fi Access Point advanced configuration structure. + * + * Indicates the advanced configuration parameters for a Wi-Fi Access Point (AP). + */ +typedef struct { + uint8_t csa_announcement_delay; ///< In beacon periods + uint32_t tbd; ///< Advanced configuration option to be added +} sl_wifi_advanced_ap_configuration_t; + +/** + * @struct sl_si91x_ap_reconfiguration_t + * @brief Wi-Fi Access Point dynamic configuration structure. + * + * Specifies the dynamic configuration parameters for a Wi-Fi Access Point (AP). + */ +typedef struct { + uint8_t beacon_stop; ///< Beaconing control when no clients are connected +} sl_si91x_ap_reconfiguration_t; + +/** + * @struct sl_wifi_channel_bitmap_t + * @brief Channel bitmap for scanning in a set of selective channels. + * + * @note A 2.4 GHz channel is enabled by setting the bit of the corresponding channel number minus 1. + * For example, for channel 1, set bit 0; + for channel 2, set bit 1, and so on. @ref sl_wifi_scan_configuration_t + * @note 5 GHz chnannels are not supported. + */ +typedef struct { + uint16_t channel_bitmap_2_4; ///< Channel bitmap for scanning in a set of selective channels in 2.4 GHz. + uint32_t + channel_bitmap_5; ///< Channel bitmap for scanning in a set of selective channels in 5 GHz. (Currently not supported.) +} sl_wifi_channel_bitmap_t; + +/** + * @struct sl_wifi_client_configuration_t + * @brief Wi-Fi Client interface configuration structure. + * + * Defines the configuration parameters for a Wi-Fi client interface. + */ +typedef struct { + sl_wifi_ssid_t ssid; ///< SSID (Service Set Identifier) of the Wi-Fi network. This is of type @ref sl_wifi_ssid_t + sl_wifi_channel_t channel; ///< The channel configuration of the Wi-Fi network. This is of type @ref sl_wifi_channel_t + sl_mac_address_t bssid; ///< BSSID of the Wi-Fi network + sl_wifi_bss_type_t bss_type; ///< BSS type of the Wi-Fi network + sl_wifi_security_t security; ///< Security mode of type @ref sl_wifi_security_t + sl_wifi_encryption_t encryption; ///< Encryption mode of the Wi-Fi network. This is of type @ref sl_wifi_encryption_t + sl_wifi_client_flag_t client_options; ///< Optional flags for client configuration of type @ref sl_wifi_client_flag_t + sl_wifi_credential_id_t credential_id; ///< ID of secure credentials of type @ref sl_wifi_credential_id_t + sl_wifi_channel_bitmap_t channel_bitmap; ///< Channel bitmap for scanning of type @ref sl_wifi_channel_bitmap_t +} sl_wifi_client_configuration_t; + +/** + * @struct sl_wifi_advanced_client_configuration_t + * @brief Wi-Fi Client interface advanced configuration structure. + */ +typedef struct { + uint32_t max_retry_attempts; ///< Maximum number of retries before indicating join failure + uint32_t scan_interval; ///< Scan interval in seconds between each retry + uint32_t beacon_missed_count; ///< Number of missed beacons that will trigger rejoin + uint32_t first_time_retry_enable; ///< Retry enable or disable for first time joining +} sl_wifi_advanced_client_configuration_t; + +/** + * @struct sl_wifi_psk_credential_t + * @brief Wi-Fi PSK (Pre-Shared Key) security credentials structure. + * + * Specifies the PSK security credentials used for Wi-Fi connections. + * The PSK is used for authenticating and securing the Wi-Fi connection. + */ +typedef struct { + uint8_t value[SL_WIFI_MAX_PSK_LENGTH]; ///< PSK buffer +} sl_wifi_psk_credential_t; + +/** + * @struct sl_wifi_pmk_credential_t + * @brief Wi-Fi PMK (Pairwise Master Key) security credentials structure. + * + * Specifies the PMK security credentials used for Wi-Fi connections. + * The PMK is used for authenticating and securing the Wi-Fi connection. + */ +typedef struct { + uint8_t value[SL_WIFI_MAX_PMK_LENGTH]; ///< PMK buffer +} sl_wifi_pmk_credential_t; + +/** + * @struct sl_wifi_wep_credential_t + * @brief Wi-Fi WEP (Wired Equivalent Privacy) security credentials structure. + * + * Specifies the WEP security credentials used for Wi-Fi connections. + * These keys are used for authenticating and securing the Wi-Fi connection. + */ +typedef struct { + uint8_t index[2]; ///< Index of the active WEP key + uint8_t key[SL_WIFI_WEP_KEY_COUNT][SL_WIFI_WEP_KEY_LENGTH]; ///< WEP Keys +} sl_wifi_wep_credential_t; + +/** + * @struct sl_wifi_eap_credential_t + * @brief Wi-Fi Enterprise security credentials structure. + * + * Specifies the security credentials used for Wi-Fi Enterprise authentication. + */ +typedef struct { + uint8_t username[SL_WIFI_EAP_USER_NAME_LENGTH]; ///< Enterprise User Name + uint8_t password[SL_WIFI_EAP_PASSWORD_LENGTH]; ///< Enterprise password + uint8_t certificate_key[SL_WIFI_EAP_CERTIFICATE_KEY_LENGTH]; ///< Certificate password + uint32_t certificate_id; ///< Certificate Id for Enterprise authentication + /** + * @note + * - BIT[0] of Opportunistic Key Caching (OKC) is used to enable or disable OKC: + * - 0 – disable + * - 1 – enable + * When this is enabled, the module will use cached PMKID to get the Master Session Key (MSK), which is needed for generating PMK that is needed for the 4-way handshake. + * - BIT[1] of OKC is used to enable or disable CA certification for PEAP connection: + * – 0 – CA certificate is not required + * – 1 – CA certificate is required + * - BIT[2-12] of OKC argument are used for cipher list selection for EAP connection. All possible ciphers are listed below: + * | BIT position| Cipher selected | + * |-------------|-----------------------| + * | 2 | DHE-RSA-AES256-SHA256 | + * | 3 | DHE-RSA-AES128-SHA256 | + * | 4 | DHE-RSA-AES256-SHA | + * | 5 | DHE-RSA-AES128-SHA | + * | 6 | AES256-SHA256 | + * | 7 | AES128-SHA256 | + * | 8 | AES256-SHA | + * | 9 | AES128-SHA | + * | 10 | RC4-SHA | + * | 11 | DES-CBC3-SHA | + * | 12 | RC4-MD5 | + * - BIT[13-31] of OKC argument is reserved. + * @note If a user sets BIT[1] and does not provide the CA certificate for PEAP connection, an error is thrown. If a user provides an invalid CA certificate, an error is also thrown. A user can set either one or multiple bits from BIT[2-12] to provide the cipher list. If a user does not provide any values in OKC BIT[2-12], all ciphers are selected by default. + */ + uint32_t eap_flags; ///< EAP Flags of type @ref sl_wifi_eap_client_flag_t +} sl_wifi_eap_credential_t; + +#if defined(__Keil) +#pragma anon_unions +#endif + +/** + * @struct sl_wifi_credential_t + * @brief Wi-Fi security credentials structure. + */ +typedef struct { + sl_wifi_credential_type_t type; ///< Credential type + union { + sl_wifi_psk_credential_t psk; ///< WiFi Personal credentials + sl_wifi_pmk_credential_t pmk; ///< WiFi PMK credentials + sl_wifi_wep_credential_t wep; ///< WEP keys + sl_wifi_eap_credential_t eap; ///< Enterprise client credentials + }; ///< WiFi Credential structure +} sl_wifi_credential_t; + +/** + * @struct sl_wifi_twt_request_t + * @brief TWT (Target Wake Time) request structure to configure a session. + */ +typedef struct { + uint8_t wake_duration; ///< Nominal minimum wake duration. Range : 0 - 255 + uint8_t + wake_duration_tol; ///< Tolerance allowed for wake duration in case of suggest TWT. Received TWT wake duration from AP will be validated against tolerance limits and decided if TWT config received is in acceptable range. Range : 0 - 255. + uint8_t wake_int_exp; ///< Wake interval exponent to the base 2. Range : 0 - 31. + uint8_t + wake_int_exp_tol; ///< Tolerance allowed for wake_int_exp in case of suggest TWT request. Received TWT wake interval exponent from AP will be validated against tolerance limits and decided if TWT config received is in acceptable range. Range : 0 - 31. + uint16_t wake_int_mantissa; ///< Wake interval mantissa. Range : 0 - 65535. + uint16_t + wake_int_mantissa_tol; ///< Tolerance allowed for wake_int_mantissa in case of suggest TWT. Received TWT wake interval mantissa from AP will be validated against tolerance limits and decided if TWT config received is in acceptable range. Range : 0 - 65535. + uint8_t + implicit_twt; ///< If enabled (1), the TWT requesting STA calculates the next TWT by adding a fixed value to the current TWT value. Explicit TWT is currently not allowed. + uint8_t + un_announced_twt; ///< If enabled (1), the TWT requesting STA does not announce its wake up to AP through PS-POLLs or UAPSD Trigger frames. Values : 0 or 1. + uint8_t + triggered_twt; ///< If enabled(1), at least one trigger frame is included in the TWT Service Period(TSP). Values : 0 or 1. + uint8_t negotiation_type; ///< Negotiation type : 0 - Individual TWT; 1 - Broadcast TWT. + uint8_t twt_channel; ///< Currently this configuration is not supported. Range : 0 - 7. + uint8_t + twt_protection; ///< If enabled (1), TSP is protected. This is negotiable with AP. Currently this is not supported. Values : 0 or 1. + uint8_t twt_flow_id; ///< TWT session flow id. 0 - 7 valid. 0xFF to disable all active TWT sessions. + uint8_t + restrict_tx_outside_tsp; ///< 1 - Any Tx outside the TSP is restricted. 0 - TX can happen outside the TSP also. + uint8_t twt_retry_limit; ///< TWT retry limit. Range : 0 - 15. + uint8_t twt_retry_interval; ///< TWT retry interval in seconds between two twt requests. Range : 5 - 255. + uint8_t req_type; ///< TWT request type. 0 - Request TWT; 1 - Suggest TWT; 2 - Demand TWT. + uint8_t twt_enable; ///< TWT enable. 0 - TWT session teardown; 1 - TWT session setup. + uint8_t wake_duration_unit; ///< Wake duration unit. 0 - 256 microseconds ; 1 - 1024 microseconds. +} sl_wifi_twt_request_t; + +/** + * @struct sl_wifi_twt_selection_t + * @brief TWT (Target Wake Time) request structure to auto select a session. + */ +typedef struct { + uint8_t twt_enable; ///< TWT enable. 0 - TWT session teardown; 1 - TWT session setup. + uint16_t + average_tx_throughput; ///< This is the expected average Tx throughput in Kbps. Value ranges from 0 to 10Mbps, which is half of the default [device_average_throughput](https://docs.silabs.com/wiseconnect/latest/wiseconnect-api-reference-guide-wi-fi/sl-wifi-twt-selection-t#device-average-throughput) (20Mbps by default). + uint32_t + tx_latency; ///< The allowed latency, in milliseconds, within which the given Tx operation is expected to be completed. If 0 is configured, maximum allowed Tx latency is same as rx_latency. Otherwise, valid values are in the range of [200ms - 6hrs]. + uint32_t + rx_latency; ///< The maximum latency, in milliseconds, for receiving buffered packets from the AP. The device wakes up at least once for a TWT service period within the configured rx_latency if there are any pending packets destined for the device from the AP. If set to 0, the default latency of 2 seconds is used. Valid range is between 2 seconds to 6 hours. Recommended range is 2 seconds to 60 seconds to avoid connection failures with AP due to longer sleep time. + uint16_t + device_average_throughput; ///< Refers to the average Tx throughput that the device is capable of achieving in Kbps. The default value is 20Mbps. Internal SDK use only: do not use. + uint8_t + estimated_extra_wake_duration_percent; ///< The percentage by which wake duration is supposed to be overestimated to compensate for bss congestion. Recommended input range is 0 - 50%. The default value is 0. Internal SDK use only: do not use. + uint8_t + twt_tolerable_deviation; ///< The allowed deviation percentage of wake duration TWT response. Recommended input range is 0 - 50%. The default value is 10. Internal SDK use only: do not use. + uint32_t + default_wake_interval_ms; ///< Default minimum wake interval. Recommended Range: 512ms to 1024ms. The default value is 1024msec. Internal SDK use only: do not use. + uint32_t + default_minimum_wake_duration_ms; ///< Default minimum wake interval. Recommended Range: 8ms - 16ms. The default value is 8ms. Internal SDK use only: do not use. + uint8_t + beacon_wake_up_count_after_sp; ///< The number of beacons after the service period completion for which the module wakes up and listens for any pending RX. The default value is 2. Internal SDK use only: do not use. +} sl_wifi_twt_selection_t; + +/** + * @struct sl_wifi_reschedule_twt_config_t + * @brief TWT (Target Wake Time) reschedule configuration structure. + */ +typedef struct { + uint8_t flow_id; ///< TWT session flow ID + sl_wifi_reschedule_twt_action_t + twt_action; ///< Specifies the action need to be taken for rescheduling the TWT session. This determines how and when the TWT session would be suspended or adjusted. See @ref sl_wifi_reschedule_twt_action_t for the possible actions. + uint16_t reserved1; ///< Reserved + uint8_t reserved2; ///< Reserved + uint64_t suspend_duration; ///< Duration to suspend the respective TWT session, in microseconds. +} sl_wifi_reschedule_twt_config_t; + +/** + * @struct sl_wifi_status_t + * @brief Wi-Fi device status structure. + * + * Indicates the status of various Wi-Fi functionalities on the device. + * It uses bit fields to indicate the status of different Wi-Fi modes and operations. + */ +typedef struct { + uint8_t client_active : 1; ///< WiFi Client active + uint8_t ap_active : 1; ///< WiFi Access point active + uint8_t monitor_mode_active : 1; ///< WiFi promiscuous mode active + uint8_t wfd_go_active : 1; ///< Reserved Status bit + uint8_t wfd_client_active : 1; ///< Reserved Status bit + uint8_t scan_active : 1; ///< Scan in Progress + uint8_t _reserved : 1; ///< Reserved Status bit + uint8_t _reserved2 : 1; ///< Reserved Status bit +} sl_wifi_status_t; + +/** + * @struct sl_wifi_statistics_t + * @brief Wi-Fi interface statistics structure. + */ +typedef struct { + uint32_t beacon_lost_count; ///< Number of missed beacons + uint32_t beacon_rx_count; ///< Number of received beacons + uint32_t mcast_rx_count; ///< Multicast packets received + uint32_t mcast_tx_count; ///< Multicast packets transmitted + uint32_t ucast_rx_count; ///< Unicast packets received + uint32_t ucast_tx_count; ///< Unicast packets transmitted + uint32_t + overrun_count; ///< Number of packets dropped either at ingress or egress, due to lack of buffer memory to retain all packets. +} sl_wifi_statistics_t; + +/** + * @struct sl_wifi_operational_statistics_t + * @brief Wi-Fi Operational Statistics structure. + */ +typedef struct { + uint8_t operating_mode; ///< Operating mode of the Wi-Fi interface + uint8_t + dtim_period; ///< DTIM (Delivery Traffic Indication Message) period. Indicates the number of beacon intervals between DTIM frames + uint8_t ideal_beacon_info[2]; ///< Idle beacon information + uint8_t busy_beacon_info[2]; ///< Busy beacon information + uint8_t beacon_interval + [2]; ///< Beacon Interval. Indicates the time interval between successive beacons, in Time Units (TUs). +} sl_wifi_operational_statistics_t; + +/** + * @struct sl_wifi_p2p_configuration_t + * @brief Wi-Fi Direct (P2P) configuration structure. + */ +typedef struct { + uint16_t group_owner_intent; ///< Group owner intent + const char *device_name; ///< Device name + sl_wifi_channel_t channel; ///< Wi-Fi channel. This is of type @ref sl_wifi_channel_t + char ssid_suffix[6]; ///< SSID suffix +} sl_wifi_p2p_configuration_t; + +/** + * @union sl_wifi_event_data_t + * @brief Wi-Fi event data. + * + * Indicates the data associated with a Wi-Fi event. + */ +typedef union { + sl_wifi_scan_result_t scan_results; ///< Scan Result structure. This is of type @ref sl_wifi_scan_result_t + uint32_t join_status; ///< Join status +} sl_wifi_event_data_t; + +/** + * @struct sl_wifi_wps_pin_t + * @brief Wi-Fi WPS PIN object that is an 8 digit number. + */ +typedef struct { + char digits[8]; ///< Array to store digits of WPS Pin +} sl_wifi_wps_pin_t; + +/** + * @struct sl_wifi_listen_interval_t + * @brief Wi-Fi Listen interval structure. + * + * Specifies the Wi-Fi Listen interval in milliseconds. + * The listen interval is the time interval between two consecutive Target Beacon Transmission (TBTT) events. + */ +typedef struct { + uint32_t listen_interval; ///< Wi-Fi Listen interval in millisecs +} sl_wifi_listen_interval_t; + +/** + * @struct sl_wifi_client_info_t + * @brief Wi-Fi client information structure. + * + * Indicates the MAC and IP address information related to a Wi-Fi client connected to the network. + */ +typedef struct { + sl_mac_address_t mac_adddress; ///< MAC address of the client + sl_ip_address_t ip_address; ///< IP address of client +} sl_wifi_client_info_t; + +/** + * @struct sl_wifi_client_info_response_t + * @brief Wi-Fi client information response structure. + */ +typedef struct { + uint8_t client_count; ///< Indicates the total count of Wi-Fi clients currently connected to the network + sl_wifi_client_info_t client_info[SL_WIFI_MAX_CLIENT_COUNT]; ///< Array of client information +} sl_wifi_client_info_response_t; + +/** + * @struct sl_wifi_max_tx_power_t + * @brief Wi-Fi maximum transmit power structure. + * + * Indicates the maximum transmit power settings for the Wi-Fi interface. + * + * @note + * The effective transmit power is subject to regional and device limitations. If the specified transmit power exceeds the + * maximum supported value for that region, or if the specified transmit power exceeds the maximum supported value of the device, + * the transmission would occur at the maximum supported transmit power. + * + * @note + * There are three available configurations for join_tx_power: low, medium, and high, which correspond to the values 0, 1, and 2, respectively. + * Each configuration has a specified power level. + * Low power (7 +/- 1) dBm + * Medium power (10 +/- 1) dBm + * High power (18 +/- 2) dBm + * An absolute power level can be set using the most significant bit (MSB) of an 8-bit value. This is achieved by setting the MSB to 128 (binary: 1000 0000). + * To configure the absolute transmission power, add the desired Tx power to 128. + * For example, setting the parameter to 148 (128 + 20) configures the transmission power to 20 dBm. + * + */ +typedef struct { + uint8_t scan_tx_power; ///< Transmit power during scan. Valid input range: 1 dBm to 31 dBm + uint8_t join_tx_power; ///< Transmit power during join. Valid input range: 1 dBm to 31 dBm +} sl_wifi_max_tx_power_t; + +/** + * @struct sl_wifi_multicast_filter_info_t + * @brief Wi-Fi Multicast filter information structure. + */ +typedef struct { + sl_wifi_multicast_filter_command_t + command_type; ///< Command type for multicast filter operation. Specifies the action to be taken (for example, add or remove a multicast filter). See @ref sl_wifi_multicast_filter_command_t for possible values. + sl_mac_address_t mac_address; ///< MAC address to which the filter has to be applied. +} sl_wifi_multicast_filter_info_t; + +/** + * @struct sl_wifi_tsf64_t + * @brief Wi-Fi station TSF (Timing Synchronization Function) structure. + * + * Contains the 64-bit TSF timer value for a Wi-Fi station. + */ +typedef struct { + uint32_t tsf_l; ///< Lower 32 bits of the TSF timer. Used to store the Least Significant Bits (LSB) of the TSF + uint32_t tsf_m; ///< Upper 32 bits of the TSF timer. Used to store the Most Significant Bits (MSB) of the TSF. +} sl_wifi_tsf64_t; + +/** + * @struct sl_wifi_transceiver_tx_data_control_t + * @brief Control block structure used to hold metadata for the payload passed in @ref sl_wifi_send_transceiver_data. + * + * Contains control flags and other metadata for the payload. + * The control flags specify various options for the packet, such as whether it is a 4-address packet, a QoS packet, or if a fixed data rate should be used. + */ +typedef struct { + /// Control flags bit description: + /// | Bit position | ctrl_flags bit description | + /// |--------------|------------------------------------------------------------------------------------------------------------------------------------------------| + /// | 0 | Should be set for 4-address packet or unset for 3-address packet. addr4 is ignored if set to 0. | + /// | 1 | Should be set for QoS packet. QoS control field shall not be present in the MAC header for non-QoS packet. priority is ignored if set to 0. | + /// | 2 | Should be set to use the fixed data rate provided in the rate field. If set to 0, rate field is ignored and auto rate shall be used. | + /// | 3 | Should be set to enable To DS bit in Frame Control. Valid only for 3-addr packet (bit 0 is unset). | + /// | 4 | Should be set to enable From DS bit in Frame Control. Valid only for 3-addr packet (bit 0 is unset). | + /// | 5 | Should be set if host requires TX data status report. Token is used for synchronization between data packets sent and reports received. | + /// | 6:7 | Reserved. | + /// @note If addr1 is multicast/broadcast, ctrl_flags bit 1 is ignored, and the frame is sent as a non-QoS frame, that is, QoS control field should not be present in the MAC header. + uint8_t ctrl_flags; + uint8_t reserved1; ///< Reserved + uint8_t reserved2; ///< Reserved + uint8_t + priority; ///< Data Packets are queued to respective queue based on priority. Best Effort - 0, Background - 1, Video - 2, Voice - 3 + sl_wifi_data_rate_t + rate; ///< Rates shall be provided as per @ref sl_wifi_data_rate_t. Only 11b/g rates shall be supported + uint32_t + token; ///< Used for synchronization between data packets sent and reports received. Application shall provide token/identifier as per PPDU. MAC layer sends the same token/identifier in status report along with the status of the transmitted packet + uint8_t addr1[6]; ///< Receiver MAC address + uint8_t addr2[6]; ///< Transmitter MAC address + uint8_t addr3[6]; ///< Destination MAC address + uint8_t addr4[6]; ///< Source MAC address. Initialization of addr4 is optional +} sl_wifi_transceiver_tx_data_control_t; + +/** + * @struct sl_wifi_transceiver_cw_config_t + * @brief Wi-Fi transceiver contention window configuration structure. + * + * Specifies the configuration parameters for the contention window of the Wi-Fi transceiver. + */ +typedef struct { + uint8_t + cwmin; ///< Minimum contention window size. Value is calculated from 2^N - 1 where exponent is provided as the input. Valid values for exponent N are 0 - 15 + uint8_t + cwmax; ///< Maximum contention window size. Value is calculated from 2^N - 1 where exponent is provided as the input. Valid values for exponent N are 0 - 15 + uint8_t aifsn; ///< Arbitration Inter-Frame Space Number (AIFSN). Valid range is 0 to 15 + uint8_t reserved; ///< Reserved +} sl_wifi_transceiver_cw_config_t; + +/** + * @struct sl_wifi_transceiver_parameters_t + * @brief Wi-Fi transceiver parameters structure. + * + * Specifies the configuration parameters for a Wi-Fi transceiver. + */ +typedef struct { + uint8_t + set; ///< Set to 1 to configure the transceiver config params in MAC layer. Sets to 0 to query the transceiver config params from MAC layer + uint8_t + retransmit_count; ///< Retransmit count. Common across all peers and access categories and valid only for unicast data frames. Valid range is 1 to 15 + uint16_t flags; ///< Reserved + sl_wifi_transceiver_cw_config_t + cw_params[4]; ///< CW params for respective queues. AC index: Best Effort - 0, Background - 1, Video - 2, Voice - 3 +} sl_wifi_transceiver_parameters_t; + +/** + * @struct sl_wifi_transceiver_set_channel_t + * @brief Wi-Fi transceiver channel information structure. + * + * Indicates the channel information for the Wi-Fi transceiver. + */ +typedef struct { + sl_wifi_channel_t chan_info; ///< Channel information + uint8_t tx_power; ///< Maximum transmission power +} sl_wifi_transceiver_set_channel_t; + +/** + * @struct sl_wifi_transceiver_peer_update_t + * @brief Wi-Fi transceiver peer update structure. + * + * Defines the configuration parameters for adding or deleting a peer in the Wi-Fi transceiver. + * The peer can be added or deleted based on the MAC address. + */ +typedef struct { + /// | Bit position | Flags bit description | + /// |--------------|--------------------------------------------------------------------------------------------------------------------| + /// | 0 | Shall be set to add the peer, else reset to 0 to delete the peer. | + /// | 1 | Shall be set for auto-rate enable. To enable auto-rate, application needs to provide peer_supported_rate_bitmap | + uint8_t flags; + /// MAC address of peer to be added or deleted. + uint8_t peer_mac_address[6]; + /// Rate bitmap of peer station + /// | peer_supported_rate_bitmap | Data rate | + /// | :--------------------------| :----------| + /// | BIT(0) | 1 Mbps | + /// | BIT(1) | 2 Mbps | + /// | BIT(2) | 5.5 Mbps | + /// | BIT(3) | 11 Mbps | + /// | BIT(4) | 6 Mbps | + /// | BIT(5) | 9 Mbps | + /// | BIT(6) | 12 Mbps | + /// | BIT(7) | 18 Mbps | + /// | BIT(8) | 24 Mbps | + /// | BIT(9) | 36 Mbps | + /// | BIT(10) | 48 Mbps | + /// | BIT(11) | 54 Mbps | + /// | BIT(12:31) | Reserved | + uint32_t peer_supported_rate_bitmap; +} sl_wifi_transceiver_peer_update_t; + +/** + * @struct sl_wifi_transceiver_mcast_filter_t + * @brief Wi-Fi transceiver multicast filter structure. + * + * Defines the configuration parameters for enabling or disabling multicast filtering in the Wi-Fi transceiver. + */ +typedef struct { + uint8_t + flags; ///< Bit 0 is set to 1 to enable filtering for the specified MAC addresses, else set to 0 to disable filtering + uint8_t + num_of_mcast_addr; ///< Number of multicast addresses. Valid values are 1, and 2. This field is ignored when filtering is disabled + uint8_t mac[2][6]; ///< List of multicast addresses. This field is ignored when filtering is disabled +} sl_wifi_transceiver_mcast_filter_t; + +/** + * @struct sl_wifi_transceiver_configuration_t + * @brief Wi-Fi transceiver interface configuration structure. + */ +typedef struct { + sl_wifi_transceiver_set_channel_t + channel; ///< Channel information. See @ref sl_wifi_transceiver_set_channel_t for details on channel settings. + sl_mac_address_t dut_mac; ///< DUT MAC address + sl_wifi_transceiver_parameters_t + parameters; ///< Transceiver parameters. See @ref sl_wifi_transceiver_parameters_t for details on transceiver settings +} sl_wifi_transceiver_configuration_t; + +/** + * @struct sl_wifi_transceiver_tx_data_confirmation_t + * @brief Wi-Fi transceiver TX data confirmation structure. + * + * Indicates the status report for a transmitted data packet identified by a token. + */ +typedef struct { + /// Status report for the data packet identified by token. + /// | Status | Description | + /// | :----------------------------| :-----------------------------------------------------------------------------------------------------------------------------------| + /// | SL_STATUS_OK (0x0) | Received Ack | + /// | SL_STATUS_ACK_ERR (0x1) | Ack error | + /// | SL_STATUS_CS_BUSY (0x2) | Carrier sense busy | + /// | SL_STATUS_UNKNOWN_PEER (0x3) | If @ref sl_wifi_send_transceiver_data was called for a peer that was not added or was deleted before the data packet was sent out. | + sl_status_t status; + /// Rate at which data packet has been sent. Rate is invalid if error is SL_STATUS_CS_BUSY or SL_STATUS_UNKNOWN_PEER. + uint32_t rate; + /// Priority used for the data packet from control->priority in the corresponding call to @ref sl_wifi_send_transceiver_data. + uint8_t priority; + /// Data packet identifier from control->token value passed in the corresponding call to @ref sl_wifi_send_transceiver_data. + uint32_t token; +} sl_wifi_transceiver_tx_data_confirmation_t; + +/** + * @struct sl_wifi_transceiver_rx_data_t + * @brief Structure for handling received Wi-Fi transceiver data. + * + * Contains information about the received Wi-Fi transceiver data, which includes status, RSSI, data rate, length, and the actual data buffer. + */ +typedef struct { + /// Status code for the received RX packet. + /// | Status | Description | + /// | :----------------------------| :------------------------------------------------------------------------------------------------------------------------------------| + /// | SL_STATUS_OK (0x0) | Success | + /// | SL_STATUS_UNKNOWN_PEER (0x3) | If SL_SI91X_FEAT_TRANSCEIVER_MAC_PEER_DS_SUPPORT feature is enabled and data packet is received from a peer not present in MAC layer | + sl_status_t status; + /// RSSI of the received 802.11 frame. This field is valid only if status is set to success. + int8_t rssi; + /// Rate of the received 802.11 frame as per @ref sl_wifi_data_rate_t. This field is valid only if status is set to success. + uint32_t rate; + /// Length of the buffer. + uint32_t length; + /// IEEE 802.11 frame received from firmware. `buffer` points to the beginning of the MAC header. Contents are not valid once the function returns. If the contents need to be accessed after return, it needs to be copied to the application buffer. If the status is not successful, buffer is set to NULL and shall not be accessed. + /// + /// *Format of IEEE 802.11 frame received from firmware in buffer* + /// | Field name | Frame Control | Duration | Addr1 | Addr2 | Adddr3 | Seq Ctrl | Addr4 | QoS ctrl | Payload (LLC + Data) | + /// |:-----------|:---------------|:---------|:------|:------|:-------|:---------|:-----------------------|:----------------------|:----------------------| + /// | Size(bytes)| 2 | 2 | 6 | 6 | 6 | 2 | 6 (Optionally present) | 2 (Optionally present)| Variable | + /// @note All unicast data frames received where Address 1 (RA) matches the device MAC address are passed to the host application. + /// @note All broadcast data frames are sent to the host. + /// @note All multicast data frames are sent to the host unless filtering is enabled using @ref sl_wifi_set_transceiver_multicast_filter. + /// @note On chip duplicate detection is not supported and is expected to be handled by the application. + /// @note On chip MAC level decryption is not supported. + uint8_t *buffer; +} sl_wifi_transceiver_rx_data_t; + +/** @} */ diff --git a/wiseconnect/components/protocol/wifi/si91x/sl_wifi.c b/wiseconnect/components/protocol/wifi/si91x/sl_wifi.c new file mode 100644 index 000000000..62cd77fa1 --- /dev/null +++ b/wiseconnect/components/protocol/wifi/si91x/sl_wifi.c @@ -0,0 +1,2586 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_wifi.h" +#include "sl_wifi_types.h" +#include "sl_wifi_device.h" +#include "sl_si91x_host_interface.h" +#include "sl_si91x_status.h" +#include "sl_si91x_types.h" +#include "sl_si91x_protocol_types.h" +#include "sl_si91x_driver.h" +#include "sl_rsi_utility.h" +#if defined(SLI_SI91X_SOCKETS) +#include "sl_si91x_socket_utility.h" +#endif +#include +#include + +#ifndef SL_NCP_DEFAULT_COMMAND_WAIT_TIME +#define SL_NCP_DEFAULT_COMMAND_WAIT_TIME 3000 +#endif + +#ifdef SL_SI91X_SIDE_BAND_CRYPTO +#include "sl_si91x_driver.h" +#include "rsi_m4.h" +extern rsi_m4ta_desc_t crypto_desc[2]; +#endif + +#ifdef SLI_SI91X_MCU_INTERFACE +#include "rsi_wisemcu_hardware_setup.h" +#endif + +#ifdef SLI_SI91X_OFFLOAD_NETWORK_STACK +#include "sl_net_si91x_integration_handler.h" +#else + +// This macro defines a handler for cleaning up resources. +#define SLI_NETWORK_CLEANUP_HANDLER() \ + { \ + } +#endif +// Enterprise configuration command parameters +/*=======================================================================*/ + +// Enterprise method ,should be one of among TLS, TTLS, FAST or PEAP + +#define SL_EAP_TLS_METHOD "TLS" +#define SL_EAP_TTLS_METHOD "TTLS" +#define SL_EAP_FAST_METHOD "FAST" +#define SL_EAP_PEAP_METHOD "PEAP" +#define SL_EAP_LEAP_METHOD "LEAP" + +// This parameter is used to configure the module in Enterprise security mode +#define SL_EAP_INNER_METHOD "\"auth=MSCHAPV2\"" + +// Private Key Password is required for encrypted private key, format is like "\"12345678\"" +#define SL_DEFAULT_PRIVATE_KEY_PASSWORD "" + +#define JOIN_TIMEOUT 8000 + +#define ALWAYS_ROAM 1 +#define NEVER_ROAM 0 +#define MAX_FLOW_ID 7 +#define MAX_WAKE_INTERVAL_EXPONENT 31 +#define MAX_WAKE_INTERVAL_EXPONENT_TOLERANCE 31 +#define MAX_WAKE_DURATION_UNIT 1 +#define MAX_TWT_RETRY_LIMIT 15 +#define MIN_TWT_RETRY_INTERVAL 5 +#define MAX_TWT_REQ_TYPE 2 +#define REQUEST_TWT 0 +#define SUGGEST_TWT 1 +#define DEMAND_TWT 1 +#define TWT_WAKE_DURATION_UNIT_1024TU 1024 +#define TWT_WAKE_DURATION_UNIT_256TU 256 +#define DEVICE_AVERAGE_THROUGHPUT 20000 +#define MAX_TX_AND_RX_LATENCY_LIMIT 21600000 +#define MAX_TWT_SUSPEND_DURATION 0x5265c00 +#define ABSOLUTE_POWER_VALUE_TOGGLE 0x80 +#define PASSIVE_SCAN_ENABLE BIT(7) +#define LP_CHAIN_ENABLE BIT(6) +#define QUICK_SCAN_ENABLE 1 +#define SCAN_RESULTS_TO_HOST 2 +#define MAX_2_4G_CHANNEL 14 + +/*========================================================================*/ +// 11ax params +/*========================================================================*/ +#define NOMINAL_PE 2 +#define DCM_ENABLE 0 +#define LDPC_ENABLE 0 +#define NG_CB_ENABLE 0 +#define NG_CB_VALUES 0 +#define UORA_ENABLE 0 +#define TRIGGER_RESP_IND 0xF +#define IPPS_VALID_VALUE 0 +#define TX_ONLY_ON_AP_TRIG 0 +#define CONFIG_ER_SU 0 // 0 - NO ER_SU support, 1 - Use ER_SU rates along with Non_ER_SU rates, 2 - Use ER_SU rates only +#define SLI_SI91X_ENABLE_TWT_FEATURE 1 +#define SLI_SI91X_DISABLE_SU_BEAMFORMEE_SUPPORT 0 +/*=======================================================================*/ +extern bool device_initialized; +extern bool bg_enabled; +extern bool interface_is_up[SL_WIFI_MAX_INTERFACE_INDEX]; +extern sl_wifi_interface_t default_interface; +static sl_wifi_advanced_scan_configuration_t advanced_scan_configuration = { 0 }; +static sl_wifi_advanced_client_configuration_t advanced_client_configuration = { 0 }; +int32_t validate_datarate(sl_wifi_data_rate_t data_rate); +sl_status_t sl_wifi_get_associated_client_list(void *client_list_buffer, uint16_t buffer_length, uint32_t timeout); +static sl_wifi_client_info_response_t sli_si91x_client_info = { 0 }; + +static sl_status_t fill_join_request_security_using_encryption(sl_wifi_encryption_t encryption_mode, + uint8_t *security_type) +{ + if (encryption_mode == SL_WIFI_CCMP_ENCRYPTION) { + *security_type |= BIT(7); + } + return SL_STATUS_OK; +} + +static sl_status_t get_configured_join_request(sl_wifi_interface_t module_interface, + const void *configuration, + sl_si91x_join_request_t *join_request) +{ + SL_WIFI_ARGS_CHECK_NULL_POINTER(configuration); + SL_WIFI_ARGS_CHECK_NULL_POINTER(join_request); + sl_status_t status = SL_STATUS_OK; + + if (module_interface & SL_WIFI_CLIENT_INTERFACE) { + // get join feature bitmap + status = sl_si91x_get_join_configuration(SL_WIFI_CLIENT_INTERFACE, &(join_request->join_feature_bitmap)); + VERIFY_STATUS_AND_RETURN(status); + + sl_wifi_client_configuration_t *client_configuration = (sl_wifi_client_configuration_t *)configuration; + + // narrowing conversion from Enum of uint16 to uint8 + get_saved_sl_wifi_rate(&join_request->data_rate); + memcpy(join_request->ssid, client_configuration->ssid.value, client_configuration->ssid.length); + + join_request->ssid_len = client_configuration->ssid.length; + join_request->security_type = client_configuration->security; + if ((join_request->security_type == SL_WIFI_WPA3) + || (join_request->security_type == SL_WIFI_WPA3_ENTERPRISE)) { //check for WPA3 security + join_request->join_feature_bitmap |= SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED; + } else if ((join_request->security_type == SL_WIFI_WPA3_TRANSITION) + || join_request->security_type == SL_WIFI_WPA3_TRANSITION_ENTERPRISE) { + join_request->join_feature_bitmap &= ~(SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED); + join_request->join_feature_bitmap |= SL_SI91X_JOIN_FEAT_MFP_CAPABLE_ONLY; + } else if (join_request->security_type == SL_WIFI_WPA2 || join_request->security_type == SL_WIFI_WPA_WPA2_MIXED) { + join_request->join_feature_bitmap |= SL_SI91X_JOIN_FEAT_MFP_CAPABLE_ONLY; + } + + fill_join_request_security_using_encryption(client_configuration->encryption, &(join_request->security_type)); + + join_request->vap_id = SL_SI91X_WIFI_CLIENT_VAP_ID; // For Station vap_id will be 0 + join_request->listen_interval = sl_si91x_get_listen_interval(); + memcpy(join_request->join_bssid, client_configuration->bssid.octet, sizeof(join_request->join_bssid)); + } else if (module_interface & SL_WIFI_AP_INTERFACE) { + // get join feature bitmap + status = sl_si91x_get_join_configuration(SL_WIFI_AP_INTERFACE, &(join_request->join_feature_bitmap)); + VERIFY_STATUS_AND_RETURN(status); + + sl_wifi_ap_configuration_t *ap_configuration = (sl_wifi_ap_configuration_t *)configuration; + + get_saved_sl_wifi_rate(&join_request->data_rate); + memcpy(join_request->ssid, ap_configuration->ssid.value, ap_configuration->ssid.length); + + join_request->ssid_len = ap_configuration->ssid.length; + join_request->security_type = ap_configuration->security; + join_request->vap_id = 0; + if (join_request->security_type == SL_WIFI_WPA3) { //check for WPA3 security + join_request->join_feature_bitmap |= SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED; + } else if (join_request->security_type == SL_WIFI_WPA3_TRANSITION) { //check for WPA3 Tranisition security + join_request->join_feature_bitmap &= ~(SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED); + join_request->join_feature_bitmap |= SL_SI91X_JOIN_FEAT_MFP_CAPABLE_ONLY; + } + + if (get_opermode() == SL_SI91X_CONCURRENT_MODE) { + join_request->vap_id = SL_SI91X_WIFI_AP_VAP_ID; // For Concurrent mode AP vap_id should be 1 else 0. + } + } else { + return SL_STATUS_FAIL; + } + + sl_wifi_max_tx_power_t wifi_max_tx_power = get_max_tx_power(); + + /* Within the 1-byte 'power_level' variable, bit 0 and bit 1 are allocated for encoding power level thresholds(low, mid, high). + * The Most Significant Bit serves as an indicator for toggling between absolute power value representation. + * When the MSB is set, the 'power_level' variable encodes the absolute power value using bits 2 through 6. */ + join_request->power_level = (wifi_max_tx_power.join_tx_power << 2) | ABSOLUTE_POWER_VALUE_TOGGLE; + + return SL_STATUS_OK; +} + +/***************************************************************************/ /** + * @brief + * to enable/disable ht capabilities + * @pre Pre-conditions: + * - @ref sl_wifi_init should be called before this API. + * @param[in] interface + * Wi-Fi Access Point interface as identified by @ref sl_wifi_interface_t + * @param[in] HtCaps + * HtCaps is identified by @ref sl_si91x_request_ap_high_throughput_capability_t + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + * @note + * Client interfaces are not supported. + ******************************************************************************/ +static sl_status_t sli_si91x_set_high_throughput_capability(sl_wifi_interface_t interface, + sl_si91x_request_ap_high_throughput_capability_t HtCaps) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_CLIENT_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + sl_status_t status = SL_STATUS_OK; + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_HT_CAPABILITIES, + SI91X_WLAN_CMD, + &HtCaps, + sizeof(sl_si91x_request_ap_high_throughput_capability_t), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_init(const sl_wifi_device_configuration_t *configuration, + sl_wifi_device_context_t *device_context, + sl_wifi_event_handler_t event_handler) +{ + UNUSED_PARAMETER(device_context); +#ifdef SLI_SI91X_MCU_INTERFACE +#if defined(SLI_SI917) + sl_si91x_efuse_data_t efuse_data; +#endif +#endif + sl_status_t status = SL_STATUS_OK; + status = sl_si91x_driver_init(configuration, event_handler); +#ifdef SL_SI91X_SIDE_BAND_CRYPTO + if (status == SL_STATUS_OK) { + uint32_t crypto_desc_ptr = (uint32_t)crypto_desc; + uint32_t *desc_ptr = &crypto_desc_ptr; + status = sl_si91x_m4_ta_secure_handshake(SL_SI91X_ENABLE_SIDE_BAND, sizeof(uint32_t), (uint8_t *)desc_ptr, 0, NULL); + } +#endif +#ifdef SLI_SI91X_MCU_INTERFACE +#if defined(SLI_SI917) + if (status == SL_STATUS_OK) { + /*Getting PTE CRC value to distinguish firmware 17 and 18 boards.*/ + sl_si91x_get_flash_efuse_data(&efuse_data, SL_SI91X_EFUSE_PTE_CRC); + + /*PTE FW version check.*/ + if (efuse_data.pte_crc == FIRMWARE_17_PTE_CRC_VALUE) { + /* Enable Higher PWM RO Frequency Mode for PMU for FW17 boards*/ + RSI_IPMU_Set_Higher_Pwm_Ro_Frequency_Mode_to_PMU(); + /* Set the RETN_LDO voltage to 0.8V for FW17 boards*/ + RSI_IPMU_Retn_Voltage_To_Default(); + } + } +#endif +#endif + return status; +} + +sl_status_t sl_wifi_set_antenna(sl_wifi_interface_t interface, sl_wifi_antenna_t antenna) +{ + UNUSED_PARAMETER(interface); + sl_status_t status; + sl_si91x_antenna_select_t rsi_antenna = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + // Antenna type + rsi_antenna.antenna_value = (antenna == SL_WIFI_ANTENNA_EXTERNAL) ? SL_WIFI_SELECT_EXTERNAL_ANTENNA + : SL_WIFI_SELECT_INTERNAL_ANTENNA; + + status = sl_si91x_driver_send_command(RSI_COMMON_REQ_ANTENNA_SELECT, + SI91X_COMMON_CMD, + &rsi_antenna, + sizeof(rsi_antenna), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_wait_for_scan_results(sl_wifi_scan_result_t **scan_results, uint32_t max_scan_result_count) +{ + UNUSED_PARAMETER(scan_results); + UNUSED_PARAMETER(max_scan_result_count); + +#ifdef SI91x_ENABLE_WAIT_ON_RESULTS + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + sl_status_t status; + sl_wifi_buffer_t *buffer; + sl_si91x_packet_t *packet; + + status = sl_si91x_driver_wait_for_response(RSI_WLAN_RSP_SCAN, SL_SI91X_WAIT_FOR(3000)); + VERIFY_STATUS_AND_RETURN(status); + + status = sl_si91x_host_remove_from_queue(SI91X_WLAN_RESPONSE_QUEUE, &buffer); + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + status = convert_and_save_firmware_status(get_si91x_frame_status(packet)); + VERIFY_STATUS_AND_RETURN(status); + + if (packet->command == RSI_WLAN_RSP_SCAN) { + *scan_results = (sl_wifi_scan_result_t *)malloc(packet->length); + if (scan_results == NULL) { + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_ALLOCATION_FAILED; + } + memcpy(*scan_results, packet->data, packet->length); + } + sl_si91x_host_free_buffer(buffer); +#endif + + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_wifi_start_scan(sl_wifi_interface_t interface, + const sl_wifi_ssid_t *optional_ssid, + const sl_wifi_scan_configuration_t *configuration) +{ + sl_status_t status = SL_STATUS_FAIL; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + if (SL_WIFI_SCAN_TYPE_ADV_SCAN != configuration->type) { + sl_si91x_req_scan_t scan_request = { 0 }; + + //! copying SSID & length + if (optional_ssid != NULL) { + memcpy(scan_request.ssid, optional_ssid->value, optional_ssid->length); + } + + if ((interface & SL_WIFI_2_4GHZ_INTERFACE) && (configuration->channel_bitmap_2g4 != 0xFFFF)) { + memcpy(&scan_request.channel_bit_map_2_4, + &configuration->channel_bitmap_2g4, + sizeof(scan_request.channel_bit_map_2_4)); + + uint16_t channel_bitmap = configuration->channel_bitmap_2g4; + // Set channel, if only one channel is selected in channel_bitmap + // if channel is 0, scan on all channels. + if ((channel_bitmap > 0) && (0 == (channel_bitmap & (channel_bitmap - 1)))) { + for (uint8_t channel = 1; channel <= MAX_2_4G_CHANNEL; channel++) { + if (BIT((channel - 1)) == channel_bitmap) { + scan_request.channel[0] = channel; + break; + } + } + } + } + + if (configuration->type == SL_WIFI_SCAN_TYPE_PASSIVE) { + scan_request.pscan_bitmap[3] |= PASSIVE_SCAN_ENABLE; + } + if (configuration->lp_mode) { + scan_request.pscan_bitmap[3] |= LP_CHAIN_ENABLE; + } + sl_wifi_max_tx_power_t wifi_max_tx_power = get_max_tx_power(); + // Within the 1-byte scan_feature_bimap variable, last 5 bits(bit 3 through bit 7) are allocated for + // encoding the transmit power during scan procedure. + scan_request.scan_feature_bitmap = (wifi_max_tx_power.scan_tx_power << 3); + + // Enable Quick Scan, if SSID and channel are available + // Quick Scan is disabled, if channel is 0 + if ((optional_ssid != NULL) && (scan_request.channel[0] != 0)) { + scan_request.scan_feature_bitmap |= QUICK_SCAN_ENABLE; + } + + if (advanced_scan_configuration.active_channel_time != SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME) { + sl_status_t status = sl_si91x_configure_timeout(SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT, + advanced_scan_configuration.active_channel_time); + VERIFY_STATUS_AND_RETURN(status); + } + + if (SL_WIFI_SCAN_TYPE_EXTENDED == configuration->type) { + scan_request.scan_feature_bitmap |= SCAN_RESULTS_TO_HOST; + } + sli_wifi_flush_scan_results_database(); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SCAN, + SI91X_WLAN_CMD, + &scan_request, + sizeof(scan_request), + SL_SI91X_RETURN_IMMEDIATELY, + NULL, + NULL); + } else { + sl_si91x_req_bg_scan_t scan_request = { 0 }; + + scan_request.bgscan_enable = SI91X_BG_SCAN_ENABLE; + scan_request.enable_instant_bgscan = advanced_scan_configuration.enable_instant_scan; + scan_request.passive_scan_duration = advanced_scan_configuration.passive_channel_time; + scan_request.active_scan_duration = advanced_scan_configuration.active_channel_time; + scan_request.bgscan_periodicity = (uint16_t)configuration->periodic_scan_interval; + scan_request.rssi_tolerance_threshold = (uint16_t)advanced_scan_configuration.trigger_level_change; + scan_request.bgscan_threshold = -1 * advanced_scan_configuration.trigger_level; + scan_request.multi_probe = advanced_scan_configuration.enable_multi_probe; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_BG_SCAN, + SI91X_WLAN_CMD, + &scan_request, + sizeof(sl_si91x_req_bg_scan_t), + SL_SI91X_RETURN_IMMEDIATELY, + NULL, + NULL); + } + + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_get_stored_scan_results(sl_wifi_interface_t interface, + sl_wifi_extended_scan_result_parameters_t *extended_scan_parameters) +{ + return sli_wifi_get_stored_scan_results(interface, extended_scan_parameters); +} + +sl_status_t sl_wifi_connect(sl_wifi_interface_t interface, + const sl_wifi_client_configuration_t *ap, + uint32_t timeout_ms) +{ + sl_status_t status; + sl_si91x_req_psk_t psk_request; + sl_si91x_req_eap_config_t eap_req = { 0 }; + sl_si91x_join_request_t join_request; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + sl_si91x_req_scan_t scan_request = { 0 }; + uint8_t uid_len = 0; + uint8_t psk_len = 0; + uint8_t key_len = 0; + sl_wifi_credential_t cred = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_AP_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_WIFI_ARGS_CHECK_NULL_POINTER(ap); + memset(&scan_request, 0, sizeof(scan_request)); + //! copying SSID & length + if (ap->ssid.length > 0) { + memcpy(scan_request.ssid, ap->ssid.value, ap->ssid.length); + } else { + return SL_STATUS_INVALID_PARAMETER; + } + + // Configure channel bitmap for selective channel scan + + if ((interface & SL_WIFI_CLIENT_2_4GHZ_INTERFACE) && (ap->channel_bitmap.channel_bitmap_2_4 > 0)) { + memcpy(&scan_request.channel_bit_map_2_4, + &ap->channel_bitmap.channel_bitmap_2_4, + sizeof(scan_request.channel_bit_map_2_4)); + } + + if ((interface & SL_WIFI_CLIENT_5GHZ_INTERFACE) && (ap->channel_bitmap.channel_bitmap_5 > 0)) { + memcpy(&scan_request.channel_bit_map_5, + &ap->channel_bitmap.channel_bitmap_5, + sizeof(scan_request.channel_bit_map_5)); + } + + sl_wifi_max_tx_power_t wifi_max_tx_power = get_max_tx_power(); + // Within the 1-byte scan_feature_bimap variable, last 5 bits(bit 3 through bit 7) are allocated for + // encoding the transmit power during scan procedure. + scan_request.scan_feature_bitmap = (wifi_max_tx_power.scan_tx_power << 3); + + if (advanced_scan_configuration.active_channel_time != SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME) { + sl_status_t status = + sl_si91x_configure_timeout(SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT, advanced_scan_configuration.active_channel_time); + VERIFY_STATUS_AND_RETURN(status); + } + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SCAN, + SI91X_WLAN_CMD, + &scan_request, + sizeof(scan_request), + SL_SI91X_WAIT_FOR(60000), + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + + if ((SL_WIFI_WPA_ENTERPRISE == ap->security) || (SL_WIFI_WPA2_ENTERPRISE == ap->security) + || (SL_WIFI_WPA3_ENTERPRISE == ap->security) || (SL_WIFI_WPA3_TRANSITION_ENTERPRISE == ap->security)) { + memset(&eap_req, 0, sizeof(eap_req)); + eap_req.user_identity[0] = '"'; + eap_req.password[0] = '"'; + + status = sl_si91x_host_get_credentials(ap->credential_id, SL_WIFI_EAP_CREDENTIAL, &cred); + VERIFY_STATUS_AND_RETURN(status); + + memcpy(&(eap_req.user_identity[1]), cred.eap.username, 63); + memcpy(&(eap_req.password[1]), cred.eap.password, 127); + uid_len = strlen((char *)eap_req.user_identity); + psk_len = strlen((char *)eap_req.password); + eap_req.user_identity[uid_len] = '"'; + eap_req.password[psk_len] = '"'; + eap_req.user_identity[uid_len + 1] = 0; + eap_req.password[psk_len + 1] = 0; + + // copy enterprise configuration data + if (SL_WIFI_EAP_TLS_ENCRYPTION == ap->encryption) { + strcpy((char *)eap_req.eap_method, SL_EAP_TLS_METHOD); + } else if (SL_WIFI_EAP_TTLS_ENCRYPTION == ap->encryption) { + strcpy((char *)eap_req.eap_method, SL_EAP_TTLS_METHOD); + } else if (SL_WIFI_EAP_FAST_ENCRYPTION == ap->encryption) { + strcpy((char *)eap_req.eap_method, SL_EAP_FAST_METHOD); + } else if (SL_WIFI_PEAP_MSCHAPV2_ENCRYPTION == ap->encryption) { + strcpy((char *)eap_req.eap_method, SL_EAP_PEAP_METHOD); + } else if (SL_WIFI_EAP_LEAP_ENCRYPTION == ap->encryption) { + strcpy((char *)eap_req.eap_method, SL_EAP_LEAP_METHOD); + } else { + return SL_STATUS_WIFI_INVALID_ENCRYPTION_METHOD; + } + + strcpy((char *)eap_req.inner_method, SL_EAP_INNER_METHOD); + memcpy(eap_req.okc_enable, &cred.eap.eap_flags, sizeof(cred.eap.eap_flags)); + + key_len = strlen((const char *)cred.eap.certificate_key); + if ((key_len > 0)) { + eap_req.private_key_password[0] = '"'; + strcpy((char *)eap_req.private_key_password, (const char *)cred.eap.certificate_key); + eap_req.private_key_password[key_len + 1] = '"'; + } else { + strcpy((char *)eap_req.private_key_password, SL_DEFAULT_PRIVATE_KEY_PASSWORD); + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_EAP_CONFIG, + SI91X_WLAN_CMD, + &eap_req, + sizeof(eap_req), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + } else if ((SL_WIFI_WPA == ap->security) || (SL_WIFI_WPA2 == ap->security) || (SL_WIFI_WPA_WPA2_MIXED == ap->security) + || (SL_WIFI_WPA3 == ap->security) || (SL_WIFI_WPA3_TRANSITION == ap->security)) { + + memset(&psk_request, 0, sizeof(psk_request)); + status = sl_si91x_host_get_credentials(ap->credential_id, SL_WIFI_PSK_CREDENTIAL, &cred); + VERIFY_STATUS_AND_RETURN(status); + psk_request.type = cred.type == SL_WIFI_PSK_CREDENTIAL ? 1 : 2; + memcpy(psk_request.psk_or_pmk, cred.pmk.value, SL_WIFI_MAX_PMK_LENGTH); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_HOST_PSK, + SI91X_WLAN_CMD, + &psk_request, + sizeof(psk_request), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + } else if (SL_WIFI_WEP == ap->security) { + return SL_STATUS_NOT_SUPPORTED; + } else if (SL_WIFI_OPEN != ap->security) { + return SL_STATUS_WIFI_UNKNOWN_SECURITY_TYPE; + } + + memset(&join_request, 0, sizeof(join_request)); + + status = get_configured_join_request(SL_WIFI_CLIENT_INTERFACE, ap, &join_request); + + VERIFY_STATUS_AND_RETURN(status); + + status = + sl_si91x_driver_send_command(RSI_WLAN_REQ_JOIN, + SI91X_WLAN_CMD, + &join_request, + sizeof(join_request), + timeout_ms ? SL_SI91X_WAIT_FOR_RESPONSE(timeout_ms) : SL_SI91X_RETURN_IMMEDIATELY, + NULL, + &buffer); + + if (timeout_ms != 0 && status != SL_STATUS_OK) { + if (buffer != NULL) { + sl_si91x_host_free_buffer(buffer); + } + sl_status_t temp_status = sl_si91x_driver_send_command(RSI_WLAN_REQ_INIT, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(temp_status); + } + + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + if (packet->data[0] != 'C') { + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_NOT_AVAILABLE; + } + + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_set_advanced_client_configuration(sl_wifi_interface_t interface, + const sl_wifi_advanced_client_configuration_t *configuration) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_AP_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + sl_si91x_rejoin_params_t rejoin_request = { .max_retry_attempts = configuration->max_retry_attempts, + .scan_interval = configuration->scan_interval, + .beacon_missed_count = configuration->beacon_missed_count, + .first_time_retry_enable = configuration->first_time_retry_enable }; + + if (rejoin_request.beacon_missed_count < 40) { + SL_DEBUG_LOG("\r\nBeacon Missed Count minimum value should be 40, Updating to the minimum value.\r\n"); + rejoin_request.beacon_missed_count = 40; + } + + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_REJOIN_PARAMS, + SI91X_WLAN_CMD, + &rejoin_request, + sizeof(rejoin_request), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + memcpy(&advanced_client_configuration, configuration, sizeof(sl_wifi_advanced_client_configuration_t)); + + return status; +} + +sl_status_t sl_wifi_get_signal_strength(sl_wifi_interface_t interface, int32_t *rssi) +{ + sl_status_t status; + sl_wifi_buffer_t *buffer = NULL; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(rssi, SL_STATUS_WIFI_NULL_PTR_ARG); + + if (interface & SL_WIFI_AP_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_RSSI, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(15000), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + *rssi = -(packet->data[0]); + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_sta_tsf(sl_wifi_interface_t interface, sl_wifi_tsf64_t *tsf) +{ + sl_status_t status; + sl_wifi_buffer_t *buffer = NULL; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(tsf, SL_STATUS_WIFI_NULL_PTR_ARG); + + if (interface & SL_WIFI_AP_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TSF, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(15000), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + memcpy(tsf, packet->data, packet->length); + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_set_mac_address(sl_wifi_interface_t interface, const sl_mac_address_t *mac_address) +{ + UNUSED_PARAMETER(interface); + + SL_VERIFY_POINTER_OR_RETURN(mac_address, SL_STATUS_NULL_POINTER); + + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_MAC_ADDRESS, + SI91X_WLAN_CMD, + mac_address, + sizeof(sl_mac_address_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_mac_address(sl_wifi_interface_t interface, sl_mac_address_t *mac) +{ + sl_status_t status; + sl_wifi_buffer_t *buffer = NULL; + + SL_WIFI_ARGS_CHECK_NULL_POINTER(mac); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_MAC_ADDRESS, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(15000), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (packet->length > 0) { + // In Concurrent mode, for Client Interface, mac address will be at offset 0 + uint8_t mac_address_offset = 0; + if ((SL_SI91X_CONCURRENT_MODE == get_opermode()) && (SL_WIFI_AP_INTERFACE == interface)) { + // In Concurrent mode, for AP Interface, mac address will be at offset 6 + mac_address_offset = sizeof(sl_mac_address_t); + } + memcpy(mac->octet, packet->data + mac_address_offset, sizeof(*mac)); + } + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_set_channel(sl_wifi_interface_t interface, sl_wifi_channel_t channel) +{ + UNUSED_PARAMETER(channel); + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + // Firmware doesn't support to change the channel of a running Access Point interface. + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_wifi_get_channel(sl_wifi_interface_t interface, sl_wifi_channel_t *channel_info) +{ + sl_status_t status = SL_STATUS_FAIL; + sl_wifi_buffer_t *buffer = NULL; + rsi_wlan_cmd_request_t command = 0; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + if ((interface == SL_WIFI_CLIENT_2_4GHZ_INTERFACE) || (interface == SL_WIFI_CLIENT_5GHZ_INTERFACE)) + command = RSI_WLAN_REQ_QUERY_NETWORK_PARAMS; + else if ((interface == SL_WIFI_AP_2_4GHZ_INTERFACE) || (interface == SL_WIFI_AP_5GHZ_INTERFACE)) + command = RSI_WLAN_REQ_QUERY_GO_PARAMS; + + status = sl_si91x_driver_send_command(command, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(SL_SI91X_GET_CHANNEL_TIMEOUT), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + switch (interface) { + case SL_WIFI_CLIENT_2_4GHZ_INTERFACE: { + channel_info->channel = ((sl_si91x_network_params_response_t *)packet->data)->channel_number; + channel_info->band = SL_WIFI_BAND_2_4GHZ; + break; + } + case SL_WIFI_AP_2_4GHZ_INTERFACE: { + memcpy(&channel_info->channel, ((sl_si91x_client_info_response *)packet->data)->channel_number, 2); + channel_info->band = SL_WIFI_BAND_2_4GHZ; + break; + } + default: + break; + } + + sl_si91x_host_free_buffer(buffer); + return status; +} + +/* + * This API doesn't have any affect if it is called after connect/start ap. + */ +sl_status_t sl_wifi_set_max_tx_power(sl_wifi_interface_t interface, sl_wifi_max_tx_power_t max_tx_power) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if ( + (interface & SL_WIFI_CLIENT_INTERFACE) // For the client interface, it’s necessary to check if the interface is up. However, for the AP interface, this check isn’t required since this API will be called before starting the AP. + && (!sl_wifi_is_interface_up(interface))) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + uint8_t max_scan_tx_power = max_tx_power.scan_tx_power; + uint8_t max_join_tx_power = max_tx_power.join_tx_power; + + if ((max_scan_tx_power < 1 || max_scan_tx_power > 31) || (max_join_tx_power < 1 || max_join_tx_power > 31)) { + return SL_STATUS_INVALID_PARAMETER; + } + + save_max_tx_power(max_scan_tx_power, max_join_tx_power); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_max_tx_power(sl_wifi_interface_t interface, sl_wifi_max_tx_power_t *max_tx_power) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_WIFI_ARGS_CHECK_NULL_POINTER(max_tx_power); + + *max_tx_power = get_max_tx_power(); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_start_ap(sl_wifi_interface_t interface, const sl_wifi_ap_configuration_t *configuration) +{ + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *rx_buffer = NULL; + sl_si91x_packet_t *join_response = NULL; + sl_si91x_ap_config_request request = { 0 }; + sl_si91x_join_request_t join_request = { 0 }; + sl_wifi_credential_t cred = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + memcpy(request.ssid, configuration->ssid.value, configuration->ssid.length); + request.security_type = configuration->security; + + //This encryption convertions is only required in access point mode + status = convert_sl_wifi_to_sl_si91x_encryption(configuration->encryption, &request.encryption_mode); + VERIFY_STATUS_AND_RETURN(status); + + //Configures TDI[7-4] value here + if ((configuration->security == SL_WIFI_WPA3) || (configuration->security == SL_WIFI_WPA3_TRANSITION)) { + request.encryption_mode |= configuration->tdi_flags & 0xF0; + } + status = sl_si91x_host_get_credentials(configuration->credential_id, SL_WIFI_PSK_CREDENTIAL, &cred); + VERIFY_STATUS_AND_RETURN(status); + + memcpy(request.psk, cred.psk.value, sizeof(request.psk)); + + request.channel = configuration->channel.channel; + request.beacon_interval = configuration->beacon_interval; + request.dtim_period = configuration->dtim_beacon_count; + request.max_sta_support = configuration->maximum_clients; + if (configuration->keepalive_type) { + request.ap_keepalive_type = configuration->keepalive_type; + request.ap_keepalive_period = configuration->client_idle_timeout; + } + if (configuration->beacon_stop) { + // Using a free bit in ap_keepalive_type since there are no available bits in join feature bitmap. + request.ap_keepalive_type |= BIT(2); + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_AP_CONFIGURATION, + SI91X_WLAN_CMD, + &request, + sizeof(request), + SL_SI91X_WAIT_FOR(15000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + if (configuration->is_11n_enabled) { + sl_si91x_request_ap_high_throughput_capability_t htcaps = { 0 }; + htcaps.mode_11n_enable = true; + htcaps.ht_caps_bitmap = SL_WIFI_HT_CAPS_NUM_RX_STBC | SL_WIFI_HT_CAPS_SHORT_GI_20MHZ | SL_WIFI_HT_CAPS_GREENFIELD_EN + | SL_WIFI_HT_CAPS_SUPPORT_CH_WIDTH; + status = sli_si91x_set_high_throughput_capability(SL_WIFI_AP_INTERFACE, htcaps); + VERIFY_STATUS_AND_RETURN(status); + } + + status = get_configured_join_request(SL_WIFI_AP_INTERFACE, configuration, &join_request); + VERIFY_STATUS_AND_RETURN(status); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_JOIN, + SI91X_WLAN_CMD, + &join_request, + sizeof(join_request), + SL_SI91X_WAIT_FOR_RESPONSE(15000), + NULL, + &rx_buffer); + if ((status != SL_STATUS_OK) && (rx_buffer != NULL)) { + sl_si91x_host_free_buffer(rx_buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + join_response = sl_si91x_host_get_buffer_data(rx_buffer, 0, NULL); + + if (join_response->data[0] != 'G') { + sl_si91x_host_free_buffer(rx_buffer); + return SL_STATUS_NOT_AVAILABLE; + } + + save_ap_configuration(configuration); + if (interface == SL_WIFI_AP_2_4GHZ_INTERFACE || interface == SL_WIFI_AP_INTERFACE) + interface_is_up[SL_WIFI_AP_2_4GHZ_INTERFACE_INDEX] = true; + else if (interface == SL_WIFI_AP_5GHZ_INTERFACE) + interface_is_up[SL_WIFI_AP_5GHZ_INTERFACE_INDEX] = true; + + sl_si91x_host_free_buffer(rx_buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_pairwise_master_key(sl_wifi_interface_t interface, + const uint8_t type, + const sl_wifi_ssid_t *ssid, + const char *pre_shared_key, + uint8_t *pairwise_master_key) +{ + UNUSED_PARAMETER(interface); + sl_status_t status; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_req_psk_t pairwise_master_key_request = { 0 }; + + if (pairwise_master_key == NULL) { + return SL_STATUS_WIFI_NULL_PTR_ARG; + } + + pairwise_master_key_request.type = type; + memcpy(pairwise_master_key_request.psk_or_pmk, pre_shared_key, strlen(pre_shared_key)); + memcpy(pairwise_master_key_request.ap_ssid, ssid->value, ssid->length); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_HOST_PSK, + SI91X_WLAN_CMD, + &pairwise_master_key_request, + sizeof(sl_si91x_req_psk_t), + SL_SI91X_WAIT_FOR_RESPONSE(35000), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + memcpy(pairwise_master_key, packet->data, packet->length); + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_associated_client_list(void *client_list_buffer, uint16_t buffer_length, uint32_t timeout) +{ + UNUSED_PARAMETER(client_list_buffer); + UNUSED_PARAMETER(buffer_length); + UNUSED_PARAMETER(timeout); + return SL_STATUS_NOT_SUPPORTED; + // sl_status_t status; + // sl_wifi_buffer_t *buffer; + + // status = sl_si91x_driver_send_command(RSI_WLAN_REQ_QUERY_GO_PARAMS, + // SI91X_WLAN_CMD, + // NULL, + // 0, + // SL_SI91X_WAIT_FOR_RESPONSE(10000), + // NULL, + // &buffer); + // if (status == SL_STATUS_OK) { + // sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + // // si91x_go_parameters_t* data = &packet->data; + // // Process data here + + // sl_si91x_host_free_buffer(buffer); + // } + // return status; +} + +sl_status_t sl_wifi_disconnect_ap_client(sl_wifi_interface_t interface, + const sl_mac_address_t *mac, + sl_wifi_deauth_reason_t reason) +{ + UNUSED_PARAMETER(reason); + SL_WIFI_ARGS_CHECK_NULL_POINTER(mac); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + sl_si91x_disassociation_request_t disconnect_request = { 0 }; + + disconnect_request.mode_flag = SL_SI91X_WIFI_AP_VAP_ID; + memcpy(&disconnect_request.client_mac_address, mac, sizeof(sl_mac_address_t)); + + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_DISCONNECT, + SI91X_WLAN_CMD, + &disconnect_request, + sizeof(disconnect_request), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + (void *)mac, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_get_ap_client_info(sl_wifi_interface_t interface, sl_wifi_client_info_response_t *client_info) +{ + sl_status_t status; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet; + sl_si91x_client_info_response sl_si91x_client_info_response = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_CLIENT_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(SL_WIFI_AP_INTERFACE)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_WIFI_ARGS_CHECK_NULL_POINTER(client_info); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_QUERY_GO_PARAMS, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_COMMAND_RESPONSE, + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + memcpy(&sl_si91x_client_info_response, packet->data, sizeof(sl_si91x_client_info_response)); + convert_si91x_wifi_client_info(client_info, &sl_si91x_client_info_response); + + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_wifi_get_firmware_version(sl_wifi_firmware_version_t *version) +{ + return sl_si91x_get_firmware_version((sl_si91x_firmware_version_t *)version); +} + +sl_status_t sl_wifi_get_wireless_info(sl_si91x_rsp_wireless_info_t *info) +{ + sl_status_t status = 0; + sl_wifi_buffer_t *buffer = NULL; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + SL_WIFI_ARGS_CHECK_NULL_POINTER(info); + + if (get_opermode() == SL_SI91X_ACCESS_POINT_MODE) { + // Send cmd for wlan info in AP mode + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_QUERY_GO_PARAMS, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(1000), + NULL, + &buffer); + } else if ((get_opermode() == SL_SI91X_CLIENT_MODE) || (get_opermode() == SL_SI91X_ENTERPRISE_CLIENT_MODE)) { + //! Send cmd for wlan info in client mode + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_QUERY_NETWORK_PARAMS, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(1000), + NULL, + &buffer); + } else { + return SL_STATUS_NOT_SUPPORTED; + } + + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + sl_si91x_packet_t *packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + + memset((sl_si91x_rsp_wireless_info_t *)info, 0, sizeof(sl_si91x_rsp_wireless_info_t)); + + //In AP mode, receives a buffer equivalent to sl_si91x_client_info_response. + if (packet->length > 0 && get_opermode() == SL_SI91X_ACCESS_POINT_MODE) { + sl_si91x_client_info_response *response = (sl_si91x_client_info_response *)packet->data; + // wlan state: no of stations connected in AP mode + memcpy(&info->wlan_state, (uint16_t *)&response->sta_count, sizeof(uint16_t)); + memcpy(&info->channel_number, (uint16_t *)&response->channel_number, sizeof(uint16_t)); + memcpy(info->ssid, response->ssid, MIN(sizeof(info->ssid), sizeof(response->ssid))); + memcpy(info->mac_address, response->mac_address, 6); + // PSK for AP mode, PMK for Client mode + memcpy(info->psk_pmk, response->psk, 64); + memcpy(info->ipv4_address, response->ipv4_address, 4); + memcpy(info->ipv6_address, response->ipv6_address, 16); + } + //In Client mode, receives a buffer equivalent to sl_si91x_network_params_response_t. + else if (packet->length > 0 + && ((get_opermode() == SL_SI91X_CLIENT_MODE) || (get_opermode() == SL_SI91X_ENTERPRISE_CLIENT_MODE))) { + sl_si91x_network_params_response_t *response = (sl_si91x_network_params_response_t *)packet->data; + memcpy(&info->wlan_state, (uint16_t *)&response->wlan_state, sizeof(uint8_t)); + memcpy((uint8_t *)&info->channel_number, &response->channel_number, sizeof(uint8_t)); + memcpy(info->ssid, response->ssid, MIN(sizeof(info->ssid), sizeof(response->ssid))); + memcpy(info->mac_address, response->mac_address, 6); + memcpy(&info->sec_type, &response->sec_type, sizeof(uint8_t)); + // PSK for AP mode, PMK for Client mode + memcpy(info->psk_pmk, response->psk, 64); + memcpy(info->ipv4_address, response->ipv4_address, 4); + memcpy(info->ipv6_address, response->ipv6_address, 16); + } + + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_wifi_get_firmware_size(void *buffer, uint32_t *fw_image_size) +{ + return sl_si91x_get_firmware_size(buffer, fw_image_size); +} + +sl_status_t sl_wifi_disconnect(sl_wifi_interface_t interface) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_AP_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + sl_si91x_disassociation_request_t disconnect_request = { 0 }; + + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_DISCONNECT, + SI91X_WLAN_CMD, + &disconnect_request, + sizeof(disconnect_request), + SL_NCP_DEFAULT_COMMAND_WAIT_TIME, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + reset_coex_current_performance_profile(); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_INIT, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + return status; +} + +sl_status_t sl_wifi_stop_ap(sl_wifi_interface_t interface) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_disassociation_request_t disconnect_request = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_CLIENT_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + disconnect_request.mode_flag = SL_SI91X_WIFI_AP_VAP_ID; + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_AP_STOP, + SI91X_WLAN_CMD, + &disconnect_request, + sizeof(disconnect_request), + SL_NCP_DEFAULT_COMMAND_WAIT_TIME, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + reset_ap_configuration(); + if (interface == SL_WIFI_AP_2_4GHZ_INTERFACE || interface == SL_WIFI_AP_INTERFACE) + interface_is_up[SL_WIFI_AP_2_4GHZ_INTERFACE_INDEX] = false; + else if (interface == SL_WIFI_AP_5GHZ_INTERFACE) + interface_is_up[SL_WIFI_AP_5GHZ_INTERFACE_INDEX] = false; + + return status; +} + +sl_status_t sl_wifi_get_statistics(sl_wifi_interface_t interface, sl_wifi_statistics_t *statistics) +{ + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_WIFI_ARGS_CHECK_INVALID_INTERFACE(interface); + SL_WIFI_ARGS_CHECK_NULL_POINTER(statistics); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_EXT_STATS, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(30500), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (packet->length != sizeof(sl_wifi_statistics_t)) { + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_FAIL; + } + + if (packet->length > 0) { + memcpy(statistics, packet->data, packet->length); + } + + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_wifi_get_operational_statistics(sl_wifi_interface_t interface, + sl_wifi_operational_statistics_t *operational_statistics) +{ + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_WIFI_ARGS_CHECK_INVALID_INTERFACE(interface); + SL_WIFI_ARGS_CHECK_NULL_POINTER(operational_statistics); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_GET_STATS, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_RESPONSE(30500), + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (packet->length != sizeof(sl_wifi_operational_statistics_t)) { + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_FAIL; + } + + if (packet->length > 0) { + memcpy(operational_statistics, packet->data, packet->length); + } + + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_wifi_start_statistic_report(sl_wifi_interface_t interface, sl_wifi_channel_t channel) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + sl_status_t status = SL_STATUS_OK; + sl_si91x_req_rx_stats_t rx_stats = { 0 }; + + // Configure to start RX stats + rx_stats.start[0] = START_STATISTICS_REPORT; + // Copy the channel number + memcpy(rx_stats.channel, &channel.channel, sizeof(rx_stats.channel)); + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_RX_STATS, + SI91X_WLAN_CMD, + &rx_stats, + sizeof(rx_stats), + SL_SI91X_RETURN_IMMEDIATELY, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_stop_statistic_report(sl_wifi_interface_t interface) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + sl_si91x_req_rx_stats_t rx_stats = { 0 }; + + // Configure to stop RX stats + rx_stats.start[0] = STOP_STATISTICS_REPORT; + + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_RX_STATS, + SI91X_WLAN_CMD, + &rx_stats, + sizeof(rx_stats), + SL_SI91X_WAIT_FOR_COMMAND_RESPONSE, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_set_performance_profile(const sl_wifi_performance_profile_t *profile) +{ + sl_status_t status; + sl_si91x_performance_profile_t selected_coex_profile_mode = { 0 }; + sl_wifi_performance_profile_t current_wifi_profile_mode = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_WIFI_ARGS_CHECK_NULL_POINTER(profile); + + if (profile->profile > DEEP_SLEEP_WITH_RAM_RETENTION) { + return SL_STATUS_INVALID_MODE; + } + + // Take backup of current wifi profile + get_wifi_current_performance_profile(¤t_wifi_profile_mode); + + // Send the power save command for the requested profile + status = sli_si91x_send_power_save_request(profile, NULL); + if (status != SL_STATUS_OK) { + save_wifi_current_performance_profile(¤t_wifi_profile_mode); + return status; + } + get_coex_performance_profile(&selected_coex_profile_mode); + + // Set device_initialized as false since RAM of module will be not retained + // in ULTRA_POWER_SAVE and module needs to be started from init again + if (selected_coex_profile_mode == DEEP_SLEEP_WITHOUT_RAM_RETENTION) { + device_initialized = false; + +#ifdef SLI_SI91X_MCU_INTERFACE + // In soc mode m4 does not get the card ready for next init after deinit, but if device in DEEP_SLEEP_WITHOUT_RAM_RETENTION mode, m4 should wait for card ready for next init + set_card_ready_required(true); +#endif + reset_coex_current_performance_profile(); + } + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_performance_profile(sl_wifi_performance_profile_t *profile) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + get_wifi_current_performance_profile(profile); + return SL_STATUS_OK; +} + +sl_wifi_interface_t sl_wifi_get_default_interface(void) +{ + return default_interface; +} + +void sl_wifi_set_default_interface(sl_wifi_interface_t interface) +{ + default_interface = interface; +} + +sl_status_t sl_wifi_deinit(void) +{ + sl_status_t status; + bg_enabled = false; + reset_coex_current_performance_profile(); + reset_max_tx_power(); + reset_ap_configuration(); + reset_sl_wifi_rate(); + memset(&advanced_scan_configuration, 0, sizeof(sl_wifi_advanced_scan_configuration_t)); + status = sl_si91x_driver_deinit(); + sli_wifi_flush_scan_results_database(); + + SLI_NETWORK_CLEANUP_HANDLER(); + + return status; +} + +// 5GHz interface is currently not supported for Si91x +bool sl_wifi_is_interface_up(sl_wifi_interface_t interface) +{ + switch (interface) { + case SL_WIFI_CLIENT_INTERFACE: + return interface_is_up[SL_WIFI_CLIENT_2_4GHZ_INTERFACE_INDEX] + | interface_is_up[SL_WIFI_CLIENT_5GHZ_INTERFACE_INDEX]; + case SL_WIFI_AP_INTERFACE: + return interface_is_up[SL_WIFI_AP_2_4GHZ_INTERFACE_INDEX] | interface_is_up[SL_WIFI_AP_5GHZ_INTERFACE_INDEX]; + case SL_WIFI_CLIENT_2_4GHZ_INTERFACE: + return interface_is_up[SL_WIFI_CLIENT_2_4GHZ_INTERFACE_INDEX]; + case SL_WIFI_AP_2_4GHZ_INTERFACE: + return interface_is_up[SL_WIFI_AP_2_4GHZ_INTERFACE_INDEX]; + case SL_WIFI_CLIENT_5GHZ_INTERFACE: + return interface_is_up[SL_WIFI_CLIENT_5GHZ_INTERFACE_INDEX]; + case SL_WIFI_AP_5GHZ_INTERFACE: + return interface_is_up[SL_WIFI_AP_5GHZ_INTERFACE_INDEX]; + case SL_WIFI_2_4GHZ_INTERFACE: + return interface_is_up[SL_WIFI_CLIENT_2_4GHZ_INTERFACE_INDEX] + | interface_is_up[SL_WIFI_AP_2_4GHZ_INTERFACE_INDEX]; + case SL_WIFI_5GHZ_INTERFACE: + return interface_is_up[SL_WIFI_CLIENT_5GHZ_INTERFACE_INDEX] | interface_is_up[SL_WIFI_AP_5GHZ_INTERFACE_INDEX]; + case SL_WIFI_ALL_INTERFACES: + return interface_is_up[SL_WIFI_CLIENT_5GHZ_INTERFACE_INDEX] | interface_is_up[SL_WIFI_AP_5GHZ_INTERFACE_INDEX] + | interface_is_up[SL_WIFI_CLIENT_2_4GHZ_INTERFACE_INDEX] + | interface_is_up[SL_WIFI_AP_2_4GHZ_INTERFACE_INDEX]; + case SL_WIFI_TRANSCEIVER_INTERFACE: + return interface_is_up[SL_WIFI_TRANSCEIVER_INTERFACE_INDEX]; + default: + return false; + } +} + +sl_status_t sl_wifi_set_certificate_with_index(uint8_t certificate_type, + uint8_t certificate_index, + uint8_t *buffer, + uint32_t certificate_length) +{ + return sl_si91x_wifi_set_certificate_index(certificate_type, certificate_index, buffer, certificate_length); +} + +sl_status_t sl_wifi_set_certificate(uint8_t certificate_type, const uint8_t *buffer, uint32_t certificate_length) +{ + return sl_si91x_wifi_set_certificate_index(certificate_type, 0, buffer, certificate_length); +} + +sl_status_t sl_wifi_set_transmit_rate(sl_wifi_interface_t interface, + sl_wifi_rate_protocol_t rate_protocol, + sl_wifi_rate_t mask) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (sl_wifi_is_interface_up(interface)) { + if (interface == SL_WIFI_AP_INTERFACE) { + return SL_STATUS_WIFI_UNSUPPORTED; + } + } else { + if (interface == SL_WIFI_CLIENT_INTERFACE) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + } + + switch (rate_protocol) { + case SL_WIFI_RATE_PROTOCOL_B_ONLY: { + if (mask < SL_WIFI_RATE_11B_MIN || mask > SL_WIFI_RATE_11B_MAX) { + return SL_STATUS_INVALID_CONFIGURATION; + } + break; + } + case SL_WIFI_RATE_PROTOCOL_G_ONLY: { + if (mask < SL_WIFI_RATE_11G_MIN || mask > SL_WIFI_RATE_11G_MAX) { + return SL_STATUS_INVALID_CONFIGURATION; + } + break; + } + case SL_WIFI_RATE_PROTOCOL_N_ONLY: { + if (mask < SL_WIFI_RATE_11N_MIN || mask > SL_WIFI_RATE_11N_MAX) { + return SL_STATUS_INVALID_CONFIGURATION; + } + break; + } + case SL_WIFI_RATE_PROTOCOL_AC_ONLY: { + return SL_STATUS_NOT_SUPPORTED; + } + case SL_WIFI_RATE_PROTOCOL_AX_ONLY: { + if (mask < SL_WIFI_RATE_11AX_MIN || mask > SL_WIFI_RATE_11AX_MAX) { + return SL_STATUS_INVALID_CONFIGURATION; + } + break; + } + case SL_WIFI_RATE_PROTOCOL_AUTO: { + if (mask != SL_WIFI_AUTO_RATE) { + return SL_STATUS_INVALID_CONFIGURATION; + } + break; + } + default: { + return SL_STATUS_INVALID_CONFIGURATION; + } + } + + return save_sl_wifi_rate(mask); +} + +sl_status_t sl_wifi_get_transmit_rate(sl_wifi_interface_t interface, + sl_wifi_rate_protocol_t *rate_protocol, + sl_wifi_rate_t *mask) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_WIFI_ARGS_CHECK_NULL_POINTER(rate_protocol); + SL_WIFI_ARGS_CHECK_NULL_POINTER(mask); + + sl_wifi_rate_t transfer_rate; + get_saved_sl_wifi_rate(&transfer_rate); + + return get_rate_protocol_and_data_rate(transfer_rate, rate_protocol, mask); +} + +sl_status_t sl_wifi_get_ap_client_count(sl_wifi_interface_t interface, uint32_t *client_list_count) +{ + sl_wifi_client_info_response_t client_info = { 0 }; + + SL_WIFI_ARGS_CHECK_NULL_POINTER(client_list_count); + + sl_status_t status = sl_wifi_get_ap_client_info(interface, &client_info); + + if (status == SL_STATUS_OK) { + memcpy(client_list_count, (uint32_t *)&client_info.client_count, sizeof(uint32_t)); + } + + return status; +} + +sl_status_t sl_wifi_get_ap_client_list(sl_wifi_interface_t interface, + uint16_t client_list_count, + sl_mac_address_t *client_list) +{ + sl_wifi_client_info_response_t client_info = { 0 }; + + sl_status_t status = sl_wifi_get_ap_client_info(interface, &client_info); + + if (status == SL_STATUS_OK) { + for (uint16_t station_info_index = 0; + station_info_index < client_info.client_count && station_info_index < client_list_count; + station_info_index++) { + memcpy(client_list[station_info_index].octet, + client_info.client_info[station_info_index].mac_adddress.octet, + sizeof(sl_mac_address_t)); + } + } + + return status; +} +sl_status_t sl_wifi_generate_wps_pin(sl_wifi_wps_pin_t *wps_pin) +{ + sl_status_t status = SL_STATUS_OK; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + sl_si91x_wps_method_request_t wps_method_request = { 0 }; + + SL_WIFI_ARGS_CHECK_NULL_POINTER(wps_pin); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + // Set configuration to generate new WPS pin + wps_method_request.wps_method = SI91X_SET_WPS_METHOD_PIN; + wps_method_request.generate_pin = SI91X_SET_WPS_GENERATE_PIN; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_WPS_METHOD, + SI91X_WLAN_CMD, + &wps_method_request, + sizeof(sl_si91x_wps_method_request_t), + SL_SI91X_WAIT_FOR_COMMAND_RESPONSE, + NULL, + &buffer); + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (packet->length > 0) { + memcpy(wps_pin->digits, packet->data, sizeof(sl_wifi_wps_pin_t)); + } + + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_wifi_start_wps(sl_wifi_interface_t interface, + sl_wifi_wps_mode_t mode, + const sl_wifi_wps_pin_t *optional_wps_pin) +{ + UNUSED_PARAMETER(optional_wps_pin); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (mode != SL_WIFI_WPS_PUSH_BUTTON_MODE || (interface & SL_WIFI_AP_INTERFACE) == 0) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + sl_status_t status; + sl_si91x_join_request_t wps_button_press_request = { 0 }; + sl_wifi_ap_configuration_t ap_configuration = { 0 }; + + get_saved_ap_configuration(&ap_configuration); + status = get_configured_join_request(SL_WIFI_AP_INTERFACE, &ap_configuration, &wps_button_press_request); + + VERIFY_STATUS_AND_RETURN(status); + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_JOIN, + SI91X_WLAN_CMD, + &wps_button_press_request, + sizeof(wps_button_press_request), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + return status; +} +sl_status_t sl_wifi_set_roam_configuration(sl_wifi_interface_t interface, + sl_wifi_roam_configuration_t *roam_configuration) +{ + sl_si91x_req_roam_params_t roam_param_request = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_AP_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + if (roam_configuration->trigger_level != SL_WIFI_NEVER_ROAM) { + roam_param_request.roam_enable = ALWAYS_ROAM; + } + + roam_param_request.roam_threshold = -1 * roam_configuration->trigger_level; + roam_param_request.roam_hysteresis = roam_configuration->trigger_level_change; + + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_ROAM_PARAMS, + SI91X_WLAN_CMD, + &roam_param_request, + sizeof(sl_si91x_req_roam_params_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_set_advanced_scan_configuration(const sl_wifi_advanced_scan_configuration_t *configuration) +{ + SL_WIFI_ARGS_CHECK_NULL_POINTER(configuration); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + memcpy(&advanced_scan_configuration, configuration, sizeof(sl_wifi_advanced_scan_configuration_t)); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_advanced_scan_configuration(sl_wifi_advanced_scan_configuration_t *configuration) +{ + SL_WIFI_ARGS_CHECK_NULL_POINTER(configuration); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + memcpy(configuration, &advanced_scan_configuration, sizeof(sl_wifi_advanced_scan_configuration_t)); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_stop_scan(sl_wifi_interface_t interface) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_req_bg_scan_t scan_request = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_AP_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + // Once stop_scan() support for foreground scan is available, "bg_enabled" should be removed. + if (bg_enabled == true) { + scan_request.bgscan_enable = SI91X_BG_SCAN_DISABLE; + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_BG_SCAN, + SI91X_WLAN_CMD, + &scan_request, + sizeof(sl_si91x_req_bg_scan_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + bg_enabled = false; + } else { + return SL_STATUS_NOT_SUPPORTED; + } + + return status; +} + +sl_status_t sl_wifi_set_ap_configuration(sl_wifi_interface_t interface, const sl_wifi_ap_configuration_t *configuration) +{ + UNUSED_PARAMETER(interface); + UNUSED_PARAMETER(configuration); + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + //Firmware unable to configure the ap configuration of a running AP interface + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_wifi_get_ap_configuration(sl_wifi_interface_t interface, sl_wifi_ap_configuration_t *configuration) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(configuration, SL_STATUS_NULL_POINTER); + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + sl_wifi_ap_configuration_t saved_ap_configuration = { 0 }; + get_saved_ap_configuration(&saved_ap_configuration); + + memcpy(configuration, &saved_ap_configuration, sizeof(sl_wifi_ap_configuration_t)); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_reconfigure_ap(sl_wifi_interface_t interface, sl_si91x_ap_reconfiguration_t config) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (interface & SL_WIFI_CLIENT_INTERFACE) { + return SL_STATUS_NOT_SUPPORTED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_BEACON_STOP, + SI91X_WLAN_CMD, + &config, + sizeof(sl_si91x_ap_reconfiguration_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + + return status; +} + +sl_status_t sl_wifi_test_client_configuration(sl_wifi_interface_t interface, + const sl_wifi_client_configuration_t *ap, + uint32_t timeout_ms) +{ + sl_status_t status = sl_wifi_connect(interface, ap, timeout_ms); + VERIFY_STATUS_AND_RETURN(status); + + status = sl_wifi_disconnect(SL_WIFI_CLIENT_INTERFACE); + VERIFY_STATUS_AND_RETURN(status); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_send_raw_data_frame(sl_wifi_interface_t interface, const void *data, uint16_t data_length) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_VERIFY_POINTER_OR_RETURN(data, SL_STATUS_NULL_POINTER); + + if (data_length == 0) { + return SL_STATUS_INVALID_PARAMETER; + } + return sl_si91x_driver_raw_send_command(RSI_SEND_RAW_DATA, data, data_length, RSI_SEND_RAW_DATA_RESPONSE_WAIT_TIME); +} + +sl_status_t sl_wifi_enable_target_wake_time(sl_wifi_twt_request_t *twt_req) +{ + if (!twt_req->twt_enable) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->twt_flow_id > MAX_FLOW_ID) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->wake_int_exp > MAX_WAKE_INTERVAL_EXPONENT) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->wake_int_exp_tol > MAX_WAKE_INTERVAL_EXPONENT_TOLERANCE) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->wake_duration_unit > MAX_WAKE_DURATION_UNIT) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->un_announced_twt > 1 || twt_req->triggered_twt > 1 || twt_req->restrict_tx_outside_tsp > 1) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->twt_retry_limit > MAX_TWT_RETRY_LIMIT) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->twt_retry_interval < MIN_TWT_RETRY_INTERVAL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_req->req_type > MAX_TWT_REQ_TYPE) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((twt_req->req_type != REQUEST_TWT) + && (twt_req->wake_duration == 0 || twt_req->wake_int_mantissa == 0 + || ((uint32_t)twt_req->wake_duration + * (uint32_t)(twt_req->wake_duration_unit ? TWT_WAKE_DURATION_UNIT_1024TU : TWT_WAKE_DURATION_UNIT_256TU)) + > ((uint64_t)((twt_req->wake_int_mantissa) * ((uint64_t)1 << twt_req->wake_int_exp))))) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((twt_req->twt_channel != 0) || (twt_req->twt_protection != 0) || (twt_req->implicit_twt != 1)) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TWT_PARAMS, + SI91X_WLAN_CMD, + twt_req, + sizeof(sl_wifi_twt_request_t), + SL_SI91X_WAIT_FOR(35000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_target_wake_time_auto_selection(sl_wifi_twt_selection_t *twt_auto_request) +{ + if ((twt_auto_request->twt_enable != 0) && (twt_auto_request->twt_enable != 1)) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((twt_auto_request->twt_enable == 1) + && ((twt_auto_request->rx_latency > MAX_TX_AND_RX_LATENCY_LIMIT) + || (twt_auto_request->tx_latency > MAX_TX_AND_RX_LATENCY_LIMIT))) { + return SL_STATUS_INVALID_PARAMETER; + } + twt_auto_request->rx_latency = (twt_auto_request->rx_latency == 0) ? 2000 : twt_auto_request->rx_latency; + if ((twt_auto_request->rx_latency < 2000) + || (twt_auto_request->average_tx_throughput > (DEVICE_AVERAGE_THROUGHPUT / 2))) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((twt_auto_request->tx_latency < 200) && (twt_auto_request->tx_latency != 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TWT_AUTO_CONFIG, + SI91X_WLAN_CMD, + twt_auto_request, + sizeof(sl_wifi_twt_selection_t), + SL_SI91X_WAIT_FOR(35000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_disable_target_wake_time(sl_wifi_twt_request_t *twt_req) +{ + if ((!twt_req->twt_enable) && ((twt_req->twt_flow_id == 0xFF) || (twt_req->twt_flow_id <= 7))) { + sl_status_t status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TWT_PARAMS, + SI91X_WLAN_CMD, + twt_req, + sizeof(sl_wifi_twt_request_t), + SL_SI91X_WAIT_FOR(35000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; + } + + return SL_STATUS_INVALID_PARAMETER; +} + +sl_status_t sl_wifi_reschedule_twt(uint8_t flow_id, + sl_wifi_reschedule_twt_action_t twt_action, + uint64_t suspend_duration) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + if (flow_id > MAX_FLOW_ID) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((twt_action == SL_WIFI_SUSPEND_INDEFINITELY || twt_action == SL_WIFI_RESUME_IMMEDIATELY) + && suspend_duration > 0) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_action == SL_WIFI_SUSPEND_FOR_DURATION + && (suspend_duration < 1 || suspend_duration > MAX_TWT_SUSPEND_DURATION)) { + return SL_STATUS_INVALID_PARAMETER; + } + if (twt_action != SL_WIFI_SUSPEND_INDEFINITELY && twt_action != SL_WIFI_SUSPEND_FOR_DURATION + && twt_action != SL_WIFI_RESUME_IMMEDIATELY) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_wifi_reschedule_twt_config_t reschedule_twt_config = { 0 }; + reschedule_twt_config.flow_id = flow_id; + reschedule_twt_config.twt_action = twt_action; + reschedule_twt_config.suspend_duration = suspend_duration; + sl_status_t status = sl_si91x_driver_send_command(SL_WIFI_REQ_RESCHEDULE_TWT, + SI91X_WLAN_CMD, + &reschedule_twt_config, + sizeof(sl_wifi_reschedule_twt_config_t), + SL_SI91X_WAIT_FOR(35000), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_filter_broadcast(uint16_t beacon_drop_threshold, + uint8_t filter_bcast_in_tim, + uint8_t filter_bcast_tim_till_next_cmd) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_request_wlan_filter_broadcast_t sl_filter_bcast = { 0 }; + sl_filter_bcast.beacon_drop_threshold[0] = beacon_drop_threshold & 0x00FF; + sl_filter_bcast.beacon_drop_threshold[1] = (beacon_drop_threshold >> 8) & 0x00FF; + sl_filter_bcast.filter_bcast_in_tim = filter_bcast_in_tim; + sl_filter_bcast.filter_bcast_tim_till_next_cmd = filter_bcast_tim_till_next_cmd; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_FILTER_BCAST_PACKETS, + SI91X_WLAN_CMD, + &sl_filter_bcast, + sizeof(sl_si91x_request_wlan_filter_broadcast_t), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_update_gain_table(uint8_t band, uint8_t bandwidth, uint8_t *payload, uint16_t payload_length) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_gain_table_info_t *sl_gain_table_info = malloc(sizeof(sl_si91x_gain_table_info_t) + payload_length); + if (sl_gain_table_info == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + sl_gain_table_info->band = band; + sl_gain_table_info->bandwidth = bandwidth; + sl_gain_table_info->size = payload_length; + sl_gain_table_info->reserved = 0; + + memcpy(sl_gain_table_info->gain_table, payload, payload_length); + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_GAIN_TABLE, + SI91X_WLAN_CMD, + sl_gain_table_info, + sizeof(sl_si91x_gain_table_info_t) + (sl_gain_table_info->size), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + free(sl_gain_table_info); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_set_11ax_config(uint8_t guard_interval) +{ + sl_status_t status = SL_STATUS_OK; +#if !(SLI_SI91X_CONFIG_WIFI6_PARAMS) + return SL_STATUS_NOT_SUPPORTED; +#endif + sl_si91x_11ax_config_params_t config_11ax_params = { 0 }; + config_11ax_params.guard_interval = guard_interval; + config_11ax_params.nominal_pe = NOMINAL_PE; + config_11ax_params.dcm_enable = DCM_ENABLE; + config_11ax_params.ldpc_enable = LDPC_ENABLE; + config_11ax_params.ng_cb_enable = NG_CB_ENABLE; + config_11ax_params.ng_cb_values = NG_CB_VALUES; + config_11ax_params.uora_enable = UORA_ENABLE; + config_11ax_params.trigger_rsp_ind = TRIGGER_RESP_IND; + config_11ax_params.ipps_valid_value = IPPS_VALID_VALUE; + config_11ax_params.tx_only_on_ap_trig = TX_ONLY_ON_AP_TRIG; + config_11ax_params.twt_support = SLI_SI91X_ENABLE_TWT_FEATURE; + config_11ax_params.config_er_su = CONFIG_ER_SU; + config_11ax_params.disable_su_beamformee_support = SLI_SI91X_DISABLE_SU_BEAMFORMEE_SUPPORT; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_11AX_PARAMS, + SI91X_WLAN_CMD, + &config_11ax_params, + sizeof(config_11ax_params), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_wifi_set_listen_interval(sl_wifi_interface_t interface, sl_wifi_listen_interval_t listen_interval) +{ + UNUSED_PARAMETER(interface); + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + sl_si91x_set_listen_interval(listen_interval.listen_interval); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_listen_interval(sl_wifi_interface_t interface, sl_wifi_listen_interval_t *listen_interval) +{ + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + SL_WIFI_ARGS_CHECK_NULL_POINTER(listen_interval); + + listen_interval->listen_interval = sl_si91x_get_listen_interval(); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_enable_monitor_mode(sl_wifi_interface_t interface) +{ + UNUSED_PARAMETER(interface); + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_wifi_disable_monitor_mode(sl_wifi_interface_t interface) +{ + UNUSED_PARAMETER(interface); + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_wifi_start_p2p_discovery(sl_wifi_interface_t interface, + const sl_wifi_p2p_configuration_t *configuration, + sl_wifi_credential_id_t credential_id) +{ + UNUSED_PARAMETER(interface); + UNUSED_PARAMETER(configuration); + UNUSED_PARAMETER(credential_id); + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_wifi_p2p_connect(sl_wifi_interface_t interface, const sl_wifi_p2p_configuration_t *configuration) +{ + UNUSED_PARAMETER(interface); + UNUSED_PARAMETER(configuration); + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_wifi_transceiver_set_channel(sl_wifi_interface_t interface, sl_wifi_transceiver_set_channel_t channel) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_operation_mode_t opermode; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + opermode = get_opermode(); + if (opermode != SL_SI91X_TRANSCEIVER_MODE) { + SL_DEBUG_LOG("Invalid mode: %d. Command only supported in Wi-Fi transceiver opermode(7)\r\n", opermode); + return SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE; + } + + if ((channel.chan_info.channel < 1) || (channel.chan_info.channel > 14)) { + return SL_STATUS_TRANSCEIVER_INVALID_CHANNEL; + } + + // User configuration for band and bandwidth are unsupported + channel.chan_info.band = SL_WIFI_BAND_2_4GHZ; + channel.chan_info.bandwidth = SL_WIFI_BANDWIDTH_20MHz; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_TRANSCEIVER_CHANNEL, + SI91X_WLAN_CMD, + &channel, + sizeof(channel), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + + if (interface == SL_WIFI_TRANSCEIVER_INTERFACE) { + interface_is_up[SL_WIFI_TRANSCEIVER_INTERFACE_INDEX] = true; + } + + return status; +} + +sl_status_t sl_wifi_set_transceiver_parameters(sl_wifi_interface_t interface, sl_wifi_transceiver_parameters_t *params) +{ + sl_status_t status = SL_STATUS_OK; + sl_si91x_operation_mode_t opermode = 0; + sl_wifi_buffer_t *buffer = NULL; + sl_si91x_packet_t *packet = NULL; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + opermode = get_opermode(); + if (opermode != SL_SI91X_TRANSCEIVER_MODE) { + SL_DEBUG_LOG("Invalid mode: %d. Command only supported in Wi-Fi transceiver opermode(7)\r\n", opermode); + return SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE; + } + + SL_VERIFY_POINTER_OR_RETURN(params, SL_STATUS_NULL_POINTER); + + if (params->set) { + //! Transceiver configurations shall not be changed dynamically + if (sl_wifi_is_interface_up(interface)) { + return SL_STATUS_SI91X_COMMAND_GIVEN_IN_INVALID_STATE; + } + + if ((!params->retransmit_count) || (params->retransmit_count > MAX_RETRANSMIT_COUNT)) { + return SL_STATUS_TRANSCEIVER_INVALID_CONFIG; + } + for (uint8_t i = 0; i < 4; i++) { + if ((params->cw_params[i].cwmin > MAX_CW_EXPN_COUNT) || (params->cw_params[i].cwmax > MAX_CW_EXPN_COUNT) + || (params->cw_params[i].aifsn > MAX_AIFSN)) { + return SL_STATUS_TRANSCEIVER_INVALID_CONFIG; + } + } + } + + status = + sl_si91x_driver_send_command(RSI_WLAN_REQ_TRANSCEIVER_CONFIG_PARAMS, + SI91X_WLAN_CMD, + params, + sizeof(sl_wifi_transceiver_parameters_t), + params->set ? SL_SI91X_WAIT_FOR_COMMAND_SUCCESS : SL_SI91X_WAIT_FOR_COMMAND_RESPONSE, + NULL, + &buffer); + + //! Return if API called to set params. Otherwise, if API called to get params, continue further to copy params received from firmware. + if (params->set) { + return status; + } + + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + + VERIFY_STATUS_AND_RETURN(status); + + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + if (packet->length > 0) { + memcpy(params, packet->data, sizeof(sl_wifi_transceiver_parameters_t)); + } + + sl_si91x_host_free_buffer(buffer); + return status; +} + +sl_status_t sl_wifi_transceiver_up(sl_wifi_interface_t interface, sl_wifi_transceiver_configuration_t *config) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + SL_VERIFY_POINTER_OR_RETURN(config, SL_STATUS_NULL_POINTER); + + status = sl_wifi_set_transceiver_parameters(interface, &config->parameters); + if (status != RSI_SUCCESS) { + SL_DEBUG_LOG("\r\nSet transceiver config params failed, error code : 0x%lX\r\n", status); + return status; + } else { + SL_DEBUG_LOG("\r\nSet transceiver config params successful"); + } + + // Update params.set = 0 to fetch transceiver config params + memset(&config->parameters, 0, sizeof(sl_wifi_transceiver_parameters_t)); + status = sl_wifi_set_transceiver_parameters(interface, &config->parameters); + if (status != RSI_SUCCESS) { + SL_DEBUG_LOG("\r\nGet transceiver config params failed, error code : 0x%lX\r\n", status); + } else { + SL_DEBUG_LOG("\r\nTransceiver config params:"); + SL_DEBUG_LOG("\r\nRetransmit count: %d", config->parameters.retransmit_count); + for (uint8_t i = 0; i < 4; i++) { + SL_DEBUG_LOG("\r\nAC index[%d] - cwmin: %d, cwmax: %d, aifsn: %d", + i, + config->parameters.cw_params[i].cwmin, + config->parameters.cw_params[i].cwmax, + config->parameters.cw_params[i].aifsn); + } + } + + // Set transceiver mode channel + status = sl_wifi_transceiver_set_channel(interface, config->channel); + if (status != SL_STATUS_OK) { + SL_DEBUG_LOG("\r\nSet Channel Failed, Error Code : 0x%lX\r\n", status); + return status; + } else { + SL_DEBUG_LOG("\r\nSet Channel(%d) Initialization success\r\n", config->channel.chan_info.channel); + } + + // Get DUT MAC address to use as Addr2/Transmitter Addresss + status = sl_wifi_get_mac_address(interface, &config->dut_mac); + if (status == SL_STATUS_OK) { + SL_DEBUG_LOG("\r\nDevice MAC address: %x:%x:%x:%x:%x:%x\r\n", + config->dut_mac.octet[0], + config->dut_mac.octet[1], + config->dut_mac.octet[2], + config->dut_mac.octet[3], + config->dut_mac.octet[4], + config->dut_mac.octet[5]); + } else { + SL_DEBUG_LOG("\r\nFailed to get mac address: 0x%lX\r\n", status); + return SL_STATUS_FAIL; + } + + return SL_STATUS_OK; +} + +int32_t validate_datarate(sl_wifi_data_rate_t data_rate) +{ + switch (data_rate) { + case SL_WIFI_DATA_RATE_1: + case SL_WIFI_DATA_RATE_2: + case SL_WIFI_DATA_RATE_5_5: + case SL_WIFI_DATA_RATE_11: + case SL_WIFI_DATA_RATE_6: + case SL_WIFI_DATA_RATE_9: + case SL_WIFI_DATA_RATE_12: + case SL_WIFI_DATA_RATE_18: + case SL_WIFI_DATA_RATE_24: + case SL_WIFI_DATA_RATE_36: + case SL_WIFI_DATA_RATE_48: + case SL_WIFI_DATA_RATE_54: + return SL_STATUS_OK; + default: + return SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE; + } +} + +sl_status_t sl_wifi_send_transceiver_data(sl_wifi_interface_t interface, + sl_wifi_transceiver_tx_data_control_t *control, + uint8_t *payload, + uint16_t payload_len) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + if ((!payload_len) || (payload_len > MAX_PAYLOAD_LEN)) { + return SL_STATUS_INVALID_PARAMETER; + } + + SL_VERIFY_POINTER_OR_RETURN(control, SL_STATUS_NULL_POINTER); + SL_VERIFY_POINTER_OR_RETURN(payload, SL_STATUS_NULL_POINTER); + + if (IS_FIXED_DATA_RATE(control->ctrl_flags)) { + if (validate_datarate(control->rate)) { + return SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE; + } + } + + status = sl_si91x_driver_send_transceiver_data(control, payload, payload_len, SL_SI91X_WAIT_FOR(1000)); + + return status; +} + +sl_status_t sl_wifi_update_transceiver_peer_list(sl_wifi_interface_t interface, sl_wifi_transceiver_peer_update_t peer) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + if ((peer.flags & TRANSCEIVER_PEER_ADD_FLAG) && (peer.flags & TRANSCEIVER_PEER_AUTO_RATE_FLAG) + && (!peer.peer_supported_rate_bitmap)) { + return SL_STATUS_TRANSCEIVER_INVALID_DATA_RATE; + } + + if (IS_MAC_ZERO(peer.peer_mac_address)) { + return SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS; + } + if (IS_BCAST_MCAST_MAC(peer.peer_mac_address[0])) { + return SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS; + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TRANSCEIVER_PEER_LIST_UPDATE, + SI91X_WLAN_CMD, + &peer, + sizeof(sl_wifi_transceiver_peer_update_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + return status; +} + +sl_status_t sl_wifi_set_transceiver_multicast_filter(sl_wifi_interface_t interface, + sl_wifi_transceiver_mcast_filter_t mcast) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + if (mcast.flags & TRANSCEIVER_MCAST_FILTER_EN) { + if ((!mcast.num_of_mcast_addr) || mcast.num_of_mcast_addr > TRANSCEIVER_MCAST_FILTER_ADDR_LIMIT) { + return SL_STATUS_INVALID_PARAMETER; + } + for (uint8_t i = 0; i < mcast.num_of_mcast_addr; i++) { + if (IS_MAC_ZERO(mcast.mac[i])) { + return SL_STATUS_TRANSCEIVER_INVALID_MAC_ADDRESS; + } + } + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_TRANSCEIVER_MCAST_FILTER, + SI91X_WLAN_CMD, + &mcast, + sizeof(sl_wifi_transceiver_mcast_filter_t), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + return status; +} + +sl_status_t sl_wifi_flush_transceiver_data(sl_wifi_interface_t interface) +{ + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + if (!sl_wifi_is_interface_up(interface)) { + return SL_STATUS_WIFI_INTERFACE_NOT_UP; + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_TRANSCEIVER_FLUSH_DATA_Q, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + return status; +} + +sl_status_t sl_wifi_configure_multicast_filter(sl_wifi_multicast_filter_info_t *multicast_filter_info) +{ + uint16_t multicast_bitmap = 0; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + multicast_bitmap = (uint16_t)multicast_filter_info->command_type; + + if ((multicast_filter_info->command_type == SL_WIFI_MULTICAST_MAC_ADD_BIT) + || (multicast_filter_info->command_type == SL_WIFI_MULTICAST_MAC_CLEAR_BIT)) { + multicast_bitmap |= (sli_multicast_mac_hash((uint8_t *)&(multicast_filter_info->mac_address)) << 8); + } + + sl_status_t status = SL_STATUS_OK; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_SET_MULTICAST_FILTER, + SI91X_WLAN_CMD, + &multicast_bitmap, + sizeof(multicast_bitmap), + SL_SI91X_WAIT_FOR(30100), + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sli_si91x_update_ap_client_info() +{ + return sl_wifi_get_ap_client_info(SL_WIFI_AP_INTERFACE, &sli_si91x_client_info); +} + +sl_ip_address_t *sli_si91x_get_ap_client_ip_address_from_mac_address(const sl_mac_address_t mac_add) +{ + + for (uint16_t station_info_index = 0; station_info_index < sli_si91x_client_info.client_count; station_info_index++) { + sl_wifi_client_info_t *station_info = &sli_si91x_client_info.client_info[station_info_index]; + if (!memcmp((const uint8_t *)&mac_add, (uint8_t *)&station_info->mac_adddress, sizeof(sl_mac_address_t))) { + return &station_info->ip_address; + } + } + return NULL; +} diff --git a/wiseconnect/components/protocol/wifi/src/sl_wifi_basic_credentials.c b/wiseconnect/components/protocol/wifi/src/sl_wifi_basic_credentials.c new file mode 100644 index 000000000..ce1a6fd45 --- /dev/null +++ b/wiseconnect/components/protocol/wifi/src/sl_wifi_basic_credentials.c @@ -0,0 +1,126 @@ +/***************************************************************************/ /** + * @file sl_wifi_basic_credentials.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_wifi.h" +#include "sl_wifi_types.h" +#include "sl_common.h" + +#ifndef SL_WIFI_MAX_CREDENTIAL_COUNT +#define SL_WIFI_MAX_CREDENTIAL_COUNT 12 +#endif + +typedef struct { + sl_wifi_credential_type_t type; + uint16_t data_length; + uint8_t data[]; +} sl_wifi_basic_credential_entry_t; + +static sl_wifi_basic_credential_entry_t *credentials[SL_WIFI_MAX_CREDENTIAL_COUNT] = { 0 }; + +sl_status_t sl_wifi_set_credential(sl_wifi_credential_id_t id, + sl_wifi_credential_type_t type, + const void *credential, + uint32_t credential_length) +{ + sl_wifi_basic_credential_entry_t *entry = NULL; + + if (id >= SL_WIFI_MAX_CREDENTIAL_COUNT) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check if the credential is invalid parameter + if ((NULL == credential) || (0 == credential_length)) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (credentials[id] == NULL) { + credentials[id] = malloc(sizeof(sl_wifi_basic_credential_entry_t) + credential_length); + if (credentials[id] == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + memset(credentials[id], 0, sizeof(sl_wifi_basic_credential_entry_t) + credential_length); + credentials[id]->data_length = (uint16_t)credential_length; + } + entry = credentials[id]; + entry->type = type; + entry->data_length = (uint16_t)credential_length; + memcpy(entry->data, credential, entry->data_length); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_get_credential(sl_wifi_credential_id_t id, + sl_wifi_credential_type_t *type, + void *credential, + uint32_t *credential_length) +{ + const sl_wifi_basic_credential_entry_t *entry = NULL; + + // Check if the credential ID is invalid parameter + if (id >= SL_WIFI_MAX_CREDENTIAL_COUNT) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check if the credential is invalid parameter + if ((NULL == credential) || (0 == *credential_length)) { + return SL_STATUS_INVALID_PARAMETER; + } + + entry = credentials[id]; + + if (NULL == entry) { + return SL_STATUS_NOT_FOUND; + } + + if (*credential_length < entry->data_length) { + return SL_STATUS_FAIL; + } + + *type = entry->type; + *credential_length = entry->data_length; + memcpy(credential, entry->data, entry->data_length); + + return SL_STATUS_OK; +} + +sl_status_t sl_wifi_delete_credential(sl_wifi_credential_id_t id) +{ + // Check if the credential ID is invalid parameter + if (id >= SL_WIFI_MAX_CREDENTIAL_COUNT) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (NULL != credentials[id]) { + free(credentials[id]); + credentials[id] = NULL; + } + + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/protocol/wifi/src/sl_wifi_callback_framework.c b/wiseconnect/components/protocol/wifi/src/sl_wifi_callback_framework.c new file mode 100644 index 000000000..8e718ee1a --- /dev/null +++ b/wiseconnect/components/protocol/wifi/src/sl_wifi_callback_framework.c @@ -0,0 +1,158 @@ +/***************************************************************************/ /** + * @file sl_wifi_callback_framework.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_wifi_callback_framework.h" +#include "sl_si91x_host_interface.h" +#include "sl_constants.h" +#include "sl_si91x_core_utilities.h" +#include "sl_si91x_driver.h" +#include "sl_wifi.h" + +/// Entry in the callback table +typedef struct { + sl_wifi_callback_function_t function; /// User provided callback function pointer + void *arg; /// User provided callback argument +} sl_wifi_callback_entry_t; + +//#define EXECUTE_CALLBACK(id, packet) do { if (registered_callbacks[id].function) {return registered_callbacks[id].function(packet->command, packet->data, packet->length, registered_callbacks[id].arg); } } while(0) +static sl_wifi_callback_entry_t *get_callback_entry(sl_wifi_event_group_t group); +static sl_wifi_event_group_t get_event_group_from_event(sl_wifi_event_t event); + +sl_wifi_callback_entry_t registered_callbacks[SL_WIFI_EVENT_GROUP_COUNT]; + +sl_status_t sl_wifi_set_callback(sl_wifi_event_group_t group, sl_wifi_callback_function_t function, void *optional_arg) +{ + sl_wifi_callback_entry_t *entry = get_callback_entry(group); + if (entry != NULL) { + entry->function = function; + entry->arg = optional_arg; + return SL_STATUS_OK; + } + return SL_STATUS_FAIL; +} + +sl_status_t sl_wifi_default_event_handler(sl_wifi_event_t event, sl_wifi_buffer_t *buffer) +{ + sl_wifi_callback_entry_t *entry = get_callback_entry((sl_wifi_event_group_t)event); + + // Verify there is a callback registered, if not return immediately + if (entry == NULL || entry->function == NULL) { + return SL_STATUS_OK; + } + + // Start processing the event + sl_si91x_packet_t *packet = (sl_si91x_packet_t *)sl_si91x_host_get_buffer_data((sl_wifi_buffer_t *)buffer, 0, NULL); + if (SL_WIFI_CHECK_IF_EVENT_FAILED(event)) { + sl_status_t status = convert_and_save_firmware_status(get_si91x_frame_status(packet)); + if (packet->command == RSI_WLAN_RSP_JOIN) { + sl_status_t temp_status = sl_si91x_driver_send_command(RSI_WLAN_REQ_INIT, + SI91X_WLAN_CMD, + NULL, + 0, + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + VERIFY_STATUS_AND_RETURN(temp_status); + } + + return entry->function(event, &status, 0, entry->arg); + } + if (RSI_WLAN_RSP_CLIENT_CONNECTED == packet->command) { + sli_si91x_update_ap_client_info(); + } + + if (event == SL_WIFI_TRANSCEIVER_TX_DATA_STATUS_CB) { + sl_wifi_transceiver_tx_data_confirmation_t tx_cfm_cb_data = { 0 }; + tx_cfm_cb_data.status = packet->desc[15]; + tx_cfm_cb_data.rate = packet->data[0]; //Extended descriptor in data[] for rate + tx_cfm_cb_data.priority = packet->data[4]; //Extended descriptor in data[] for priority + memcpy(&tx_cfm_cb_data.token, &packet->data[8], 4); //Extended descriptor in data[] for token + + return entry->function(event, &tx_cfm_cb_data, 0, entry->arg); + } else if (event == SL_WIFI_TRANSCEIVER_RX_DATA_RECEIVE_CB) { + sl_wifi_transceiver_rx_data_t rx_cb_data = { 0 }; + uint16_t payload_offset = packet->desc[4]; + uint16_t payload_length = packet->length & 0xFFF; + uint32_t status = *(uint32_t *)(&packet->data[12]); + + rx_cb_data.length = payload_length - payload_offset; + rx_cb_data.buffer = packet->data + payload_offset; + rx_cb_data.rssi = *(uint16_t *)(&packet->data[0]); //Extended descriptor in data[] for rssi + rx_cb_data.rate = *(uint16_t *)(&packet->data[2]); //Extended descriptor in data[] for rate + + /* + * SL_STATUS_UNKNOWN_PEER - If SL_SI91X_FEAT_TRANSCEIVER_MAC_PEER_DS_SUPPORT is enabled but + * data packet is received from a peer not present in MAC layer. + */ + if ((status & TRANSCEIVER_RX_PKT_TA_MATCH_BIT) || IS_BCAST_MCAST_MAC(rx_cb_data.buffer[4])) + rx_cb_data.status = SL_STATUS_OK; + else + rx_cb_data.status = SL_STATUS_UNKNOWN_PEER; + + return entry->function(event, &rx_cb_data, 0, entry->arg); + } + + if (packet->length) { + return entry->function(event, packet->data, packet->length, entry->arg); + } else { + return entry->function(event, NULL, packet->length, entry->arg); + } +} + +static sl_wifi_callback_entry_t *get_callback_entry(sl_wifi_event_group_t group) +{ + if (group > SL_WIFI_EVENT_GROUP_COUNT) { + group = get_event_group_from_event((sl_wifi_event_t)group); + } + return ®istered_callbacks[group]; +} + +static sl_wifi_event_group_t get_event_group_from_event(sl_wifi_event_t event) +{ + //For TWT Events + if (event == SL_WIFI_TWT_UNSOLICITED_SESSION_SUCCESS_EVENT || event == SL_WIFI_TWT_AP_REJECTED_EVENT + || event == SL_WIFI_TWT_OUT_OF_TOLERANCE_EVENT || event == SL_WIFI_TWT_RESPONSE_NOT_MATCHED_EVENT + || event == SL_WIFI_TWT_UNSUPPORTED_RESPONSE_EVENT || event == SL_WIFI_TWT_TEARDOWN_SUCCESS_EVENT + || event == SL_WIFI_TWT_AP_TEARDOWN_SUCCESS_EVENT || event == SL_WIFI_TWT_FAIL_MAX_RETRIES_REACHED_EVENT + || event == SL_WIFI_TWT_INACTIVE_DUE_TO_ROAMING_EVENT || event == SL_WIFI_TWT_INACTIVE_DUE_TO_DISCONNECT_EVENT + || event == SL_WIFI_RESCHEDULE_TWT_SUCCESS_EVENT || event == SL_WIFI_TWT_INFO_FRAME_EXCHANGE_FAILED_EVENT + || event == SL_WIFI_TWT_INACTIVE_NO_AP_SUPPORT_EVENT) { + return SL_WIFI_TWT_RESPONSE_EVENTS; + } + // for STATS Events + else if (event == SL_WIFI_STATS_EVENT || event == SL_WIFI_STATS_ASYNC_EVENT || event == SL_WIFI_STATS_ADVANCE_EVENT + || event == SL_WIFI_STATS_TEST_MODE_EVENT || event == SL_WIFI_STATS_MODULE_STATE_EVENT) { + return SL_WIFI_STATS_RESPONSE_EVENTS; + } else if (event == SL_WIFI_TRANSCEIVER_RX_DATA_RECEIVE_CB || event == SL_WIFI_TRANSCEIVER_TX_DATA_STATUS_CB) { + return SL_WIFI_TRANSCEIVER_EVENTS; + } else { + event = SL_WIFI_INVALID_EVENT; + } + return (sl_wifi_event_group_t)event; +} diff --git a/wiseconnect/components/service/bsd_socket/si91x_socket/sl_si91x_socket_support.h b/wiseconnect/components/service/bsd_socket/si91x_socket/sl_si91x_socket_support.h new file mode 100644 index 000000000..031c72770 --- /dev/null +++ b/wiseconnect/components/service/bsd_socket/si91x_socket/sl_si91x_socket_support.h @@ -0,0 +1,96 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SI91X_SOCKET_SUPPORT_INCLUDED_H +#define SL_SI91X_SOCKET_SUPPORT_INCLUDED_H + +#include +#include +#include + +#include "sl_status.h" +#include "sl_si91x_protocol_types.h" + +/** + * @addtogroup SI91X_SOCKET_FUNCTIONS + * @{ + */ +/** + * @brief Structure for query SiWx91x socket information. + * + * @details + * The structure queries the information about a specific socket, in the SiWx91x series. + * It includes details such as:socket identifier, type, source and destination ports, + * and the IP address of the remote host. The IP address can be either IPv4 or IPv6, + * determined by the context structure which is used. + */ +typedef struct { + uint8_t sock_id[2]; ///< Socket Identifier. + + uint8_t sock_type[2]; ///< Socket type (for example,TCP, and UDP). + + uint8_t source_port[2]; ///< Source port number used by the socket. + + uint8_t dest_port[2]; ///< Destination port number used by the socket. + + union { + uint8_t ipv4_address[4]; ///< IPv4 address of the remote host. + + uint8_t ipv6_address[16]; ///< IPv6 address of the remote host. + } dest_ip_address; ///< IP address of the destination host. +} sl_si91x_sock_info_query_t; + +/** + * @brief Structure for SiWx91x socket information response. + * + * @details + * The structure holds the response information for a query about the currently opened sockets + * in the SiWx91x series. It includes the total number of opened sockets and an array containing + * detailed information about each socket. + */ +typedef struct { + uint16_t number_of_opened_sockets; ///< Total number of currently opened sockets. + + sl_si91x_sock_info_query_t + socket_info[SL_SI91X_SOCKET_INFO_RESPONSE_SOCKETS_COUNT]; ///< Array contains information about each open socket. +} sl_si91x_socket_info_response_t; + +/** + * @brief + * Retrieve information about currently opened sockets from the network stack. + * @param[out] socket_info_response + * Pointer to a sl_si91x_socket_info_response_t structure that will hold the response from the firmware. + * @return + * sl_status_t + * @note The socket IDs in the response are specific to the firmware and should not be used as file descriptors in socket APIs. +*/ +sl_status_t sl_si91x_get_socket_info(sl_si91x_socket_info_response_t *socket_info_response); +/** @} */ + +#endif //SL_SI91X_SOCKET_SUPPORT_INCLUDED_H diff --git a/wiseconnect/components/service/network_manager/inc/sl_net.h b/wiseconnect/components/service/network_manager/inc/sl_net.h new file mode 100644 index 000000000..4ead17ee2 --- /dev/null +++ b/wiseconnect/components/service/network_manager/inc/sl_net.h @@ -0,0 +1,586 @@ +/***************************************************************************/ /** + * @file + * @brief SL Network API + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_status.h" +#include "sl_net_types.h" + +/** + * \addtogroup NET_INTERFACE_FUNCTIONS Network Interface + * + * @note Stack overflows may occur if you invoke functions or use your own variables or data structures while handling callbacks. + * Please configure the stack size by modifying the pre-processor macro `SL_SI91X_EVENT_HANDLER_STACK_SIZE` as + * per your application's requirements. See [here](https://docs.silabs.com/wiseconnect/latest/wiseconnect-developers-guide-prog-preprocessor-build-settings/list-of-preprocessor-build-settings) + * for the instructions for modifying a pre-processor macro. + * @note Event/Callback handlers must not contain function calls or code which can block or delay the execution of + * the event/callback handler as it will cause all the other events to queue up and delay the execution of + * other events since all the events are invoked and handled from a single thread. + * @note Do not call any synchronous SDK APIs from within the Event/Callback handlers. + * + * \ingroup SL_NET_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief Initialize the specified network interface. + * + * This function initializes the specified network interface with the provided configuration, + * network context, and event handler. It supports various network interfaces such as Wi-Fi client, + * Wi-Fi access point. + * + * Once the user passes a function pointer to the event handler, the network context is passed in the callback, + * and various events can be received through this callback. + * + * @param[in] interface + * The network interface to initialize. One of the values from @ref sl_net_interface_t + * @param[in] configuration + * Pointer to the configuration structure for the specified interface of type [sl_wifi_device_configuration_t](../wiseconnect-api-reference-guide-si91x-driver/sl-wifi-device-configuration-t). + * If NULL, then the following configuration is used internally by SDK: + * | sl_net_interface_t | Default configuration | + * |:-----------------------------|:--------------------------------------| + * | SL_NET_WIFI_CLIENT_INTERFACE | sl_wifi_default_client_configuration | + * | SL_NET_WIFI_AP_INTERFACE | sl_wifi_default_ap_configuration | + * @param[in] network_context + * Runtime context specific to network interface. + * @param[in] event_handler + * Function pointer to the network event handler callback of @ref sl_net_event_handler_t type + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * @note + * For Wi-Fi events, sl_net uses the wifi callback framework. Register the corresponding Wi-Fi event handlers using [sl_wifi_set_callback](../wiseconnect-api-reference-guide-wi-fi/wifi-callback-framework#sl-wifi-set-callback) API. + * @note + * The \p network_context parameter is used only when the module is acting as a station in external stack mode (lwIP). + * In this case, \p network_context should refer to a valid @ref sl_net_wifi_lwip_context_t variable. + ******************************************************************************/ +sl_status_t sl_net_init(sl_net_interface_t interface, + const void *configuration, + void *network_context, + sl_net_event_handler_t event_handler); + +/***************************************************************************/ /** + * @brief + * De-initialize a network interface. + * + * This function de-initializes the specified network interface, releasing any resources that were allocated during initialization. + * + * After this, the user will not receive callbacks related to events. + * + * For the `SL_NET_WIFI_CLIENT_INTERFACE` and `SL_NET_WIFI_AP_INTERFACE` interface, this function ensures proper shutdown of the Wi-Fi driver, soft resets the NWP, and releases resources. + * + * @pre Pre-conditions: + * - @ref sl_net_init should be called before this API. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_deinit(sl_net_interface_t interface); + +/***************************************************************************/ /** + * @brief + * Bring a network interface up. + * + * @details + * This function brings the specified network interface up, making it ready for network communication. + * + * For `SL_NET_WIFI_CLIENT_INTERFACE`, the API fetches profile data from the profile ID, scans the network and connects to the network, configures the IP address, and updates the profile data. + * + * For `SL_NET_WIFI_AP_INTERFACE`, the API fetches profile data from the profile ID, configures the IP address, updates the profile data, and starts the Access Point (AP). + * + * @pre Pre-conditions: + * - + * @ref sl_net_init should be called before this API. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. + * + * @param[in] profile_id + * Network profile identifier for the specific interface of type @ref sl_net_profile_id_t + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * By default, profile and credential configurations in sl_net_defaults.h are used by SDK. + * @note + * To enable support for both IPv4 and IPv6, the ip.type in the profile should be set to (SL_IPV4|SL_IPV6). + * @note + * The user can define their profile and credential configurations for an interface by calling @ref sl_net_set_profile and @ref sl_net_set_credential APIs before calling @ref sl_net_up API. + * ******************************************************************************/ +sl_status_t sl_net_up(sl_net_interface_t interface, sl_net_profile_id_t profile_id); + +/***************************************************************************/ /** + * @brief + * Bring a network interface down. + * + * @details + * This function deactivates the specified network interface, effectively + * disconnecting it from the WLAN network. It should be called to properly + * shut down the interface and release any associated resources. + * + * @pre Pre-conditions: + * - @ref sl_net_up should be called before this API to ensure the interface + * is active before attempting to bring it down. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. This parameter specifies + * which network interface to bring down. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) + * and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_down(sl_net_interface_t interface); + +/** @} */ + +/** + * \addtogroup NET_IP_MANAGEMENT_FUNCTIONS IP Management + * \ingroup SL_NET_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Configure IP address of given interface. + * @pre Pre-conditions: + * - + * @ref sl_net_up should be called before this API. + * @param[in] interface + * Interface identified by @ref sl_net_interface_t + * @param[in] ip_config + * Multicast IP address of type @ref sl_net_ip_configuration_t + * @param[in] timeout + * The maximum time to wait for the IP address Configuration, in milliseconds. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. +@note + * - This API doesn't support async mode operation, so passing 0 in timeout parameter leads to an error. + ******************************************************************************/ +sl_status_t sl_net_configure_ip(sl_net_interface_t interface, + const sl_net_ip_configuration_t *ip_config, + uint32_t timeout); + +/***************************************************************************/ /** + * @brief + * This function retrieves the IP address of the specified network interface. + * @pre Pre-conditions: + * - + * @ref sl_net_up should be called before this API. + * @param[in] interface + * Interface identified by @ref sl_net_interface_t + * @param[in] ip_address + * IP address of type @ref sl_net_ip_address_t + * @param[in] timeout + * The maximum time to wait for the IP address retrieval, in milliseconds. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. +@note + * - This API doesn't support async mode operation, so passing 0 in timeout parameter leads to an error. + * - If the interface is setup in SL_IP_MANAGEMENT_STATIC_IP mode, this API only returns its mode and doesn't return ip address. + ******************************************************************************/ +sl_status_t sl_net_get_ip_address(sl_net_interface_t interface, sl_net_ip_address_t *ip_address, uint32_t timeout); + +/** @} */ + +/** + * \addtogroup NET_PROFILE_FUNCTIONS Network Profiles + * \ingroup SL_NET_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Store a network profile for a given interface. + * + * @details + * This function stores the network profile data such as WIFI Credentials and Network Credentials for the specified interface. + * The profile can be used later to bring the interface up with the stored settings. + * + * The user can use the id to store multiple profiles for the same interface and pass the id to different APIs. + * + * @pre Pre-conditions: + * - @ref sl_net_init should be called before this API. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. + * + * @param[in] id + * Profile storage index / identifier of type @ref sl_net_profile_id_t. + * + * @param[in] profile + * Pointer to profile data of type @ref sl_net_profile_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_set_profile(sl_net_interface_t interface, sl_net_profile_id_t id, const sl_net_profile_t *profile); + +/***************************************************************************/ /** + * @brief + * Retrieve a stored network profile for a given interface. + * + * @details + * This function retrieves the network profile data for the specified interface and profile ID. + * The retrieved profile data is stored in the provided profile object. + * + * @pre Pre-conditions: + * - + * @ref sl_net_init should be called before this API. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. + * + * @param[in] id + * Profile storage index / identifier of type @ref sl_net_profile_id_t. + * + * @param[out] profile + * Pointer to @ref sl_net_profile_t object that will store the retrieved profile data. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_get_profile(sl_net_interface_t interface, sl_net_profile_id_t id, sl_net_profile_t *profile); + +/***************************************************************************/ /** + * @brief + * Delete a stored network profile for a given interface. + * + * @details + * This function deletes the network profile data for the specified interface and profile ID. + * Once deleted, the profile cannot be used to bring the interface up. + * + * @pre Pre-conditions: + * - @ref sl_net_init should be called before this API. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. + * + * @param[in] id + * Profile storage index / identifier of type @ref sl_net_profile_id_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_delete_profile(sl_net_interface_t interface, sl_net_profile_id_t id); + +/** @} */ + +/** + * \addtogroup NET_CREDENTIAL_FUNCTIONS Network Credential + * \ingroup SL_NET_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Set a network credential including client credentials, certificates, and keys. + * + * @details + * This function sets the network credential type and data for the specified credential ID. + * The credential data can include client credentials, certificates, and keys. + * + * Repeatedly calling this API with the same ID will overwrite the existing credential type and data. + * + * @pre Pre-conditions: + * - @ref sl_net_init should be called before this API. + * + * @param[in] id + * Network credential identifier as identified by @ref sl_net_credential_id_t. + * + * @param[in] type + * Network credential type as identified by @ref sl_net_credential_type_t. + * + * @param[in] credential + * Pointer to the credential data object. + * + * @param[in] credential_length + * Length of the credential data object. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * If the credential is NULL or the credential length is zero, this API will return an error `SL_STATUS_INVALID_PARAMETER`. + * @note + * - Certificates should follow standard *.pem format + * - A PEM encoded file includes Base64 data. + * - After every 64 bytes, the special character `\n` should be used as a delimiter. + * - The private key is prefixed with a header like "-----BEGIN PRIVATE KEY-----" line and postfixed with an footer like"-----END PRIVATE KEY-----". + * - Certificates are prefixed with a header like "-----BEGIN CERTIFICATE-----" line and postfixed with an footer like"-----END CERTIFICATE-----" line. + * - Text outside the prefix and postfix lines is ignored and can be used for metadata. + * - The above mentioned Headers and Footers might vary + * - This API does not support the OPEN Security type for Wi-Fi client credentials. + ******************************************************************************/ +sl_status_t sl_net_set_credential(sl_net_credential_id_t id, + sl_net_credential_type_t type, + const void *credential, + uint32_t credential_length); + +/***************************************************************************/ /** + * @brief + * Retrieve a stored network credential. + * + * @details + * This function retrieves the network credential data for the specified credential ID. + * The retrieved credential data is stored in the provided credential object. + * + * @pre Pre-conditions: + * - @ref sl_net_init should be called before this API. + * + * @param[in] id + * Network credential identifier as identified by @ref sl_net_credential_id_t. + * + * @param[out] type + * Network credential type as identified by @ref sl_net_credential_type_t. + * + * @param[out] credential + * Pointer to location where credential data is stored. + * + * @param[in,out] credential_length + * in: Number of bytes available at credential, + * out: Number of bytes written. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @note + * Currently, @ref SL_NET_CERTIFICATE and @ref SL_NET_SIGNING_CERTIFICATE are not supported for retrieval. + ******************************************************************************/ +sl_status_t sl_net_get_credential(sl_net_credential_id_t id, + sl_net_credential_type_t *type, + void *credential, + uint32_t *credential_length); + +/***************************************************************************/ /** + * @brief + * Delete a stored network credential. + * + * @details + * This function deletes the network credential data for the specified credential ID and type. + * Once deleted, the credential cannot be used for network operations. + * + * @pre Pre-conditions: + * - + * @ref sl_net_init should be called before this API. + * + * @param[in] id + * Network credential identifier as identified by @ref sl_net_credential_id_t. + * + * @param[out] type + * Network credential type as identified by @ref sl_net_credential_type_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_delete_credential(sl_net_credential_id_t id, sl_net_credential_type_t type); + +/** @} */ + +/***************************************************************************/ /** + * @brief + * @param[in] id + * @param[in] data + * @param[in] data_length + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_net_set_certificate(sl_net_certificate_id_t id, const void *data, uint32_t data_length); + +/***************************************************************************/ /** + * @brief + * @param[in] id + * @param[out] data + * @param[in] data_length + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_net_get_certificate(sl_net_certificate_id_t id, const void *data, uint32_t data_length); + +/***************************************************************************/ /** + * @note + * This API is not yet implemented. + ******************************************************************************/ +sl_status_t sl_net_verify_certificate(); + +/***************************************************************************/ /** + * @brief + * Convert an IPv4 address in string of from a.b.c.d to a binary uint32_t value + * @param[in] addr + * IPV4 address. + * @param[out] value + * Binary value of the given IP address. + * @return + * sl_status_t. See https://docs.silabs.com/gecko-platform/latest/platform-common/status for details. + ******************************************************************************/ +sl_status_t sl_net_inet_addr(const char *addr, uint32_t *value); + +/** + * \addtogroup NET_MULTICAST_FUNCTIONS Network Multicast + * \ingroup SL_NET_FUNCTIONS + * @{ */ + +/***************************************************************************/ /** + * @brief + * Enable multicast for the given IP address. + * + * @details + * This function enables multicast for the specified IP address on the given interface. + * It allows the interface to receive/send multicast packets sent to the specified IP address. + * + * Users can use [sendto](../wiseconnect-api-reference-guide-sockets/bsd-socket-functions#sendto) and [recvfrom](../wiseconnect-api-reference-guide-sockets/bsd-socket-functions#recvfrom) socket APIs to send and receive data. + * + * @pre Pre-conditions: + * - @ref sl_net_up should be called before this API. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. + * + * @param[in] ip_address + * Multicast IP address of type [sl_ip_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ip-address-t). + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_join_multicast_address(sl_net_interface_t interface, const sl_ip_address_t *ip_address); + +/***************************************************************************/ /** + * @brief + * Disable multicast for the given IP address. + * + * @details + * This function disables multicast for the specified IP address on the given interface. + * It prevents the interface from receiving/sending multicast packets sent to the specified IP address. + * + * @pre Pre-conditions: + * - @ref sl_net_up should be called before this API. + * + * @param[in] interface + * Interface identified by @ref sl_net_interface_t. + * + * @param[in] ip_address + * Multicast IP address of type [sl_ip_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ip-address-t). + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + ******************************************************************************/ +sl_status_t sl_net_leave_multicast_address(sl_net_interface_t interface, const sl_ip_address_t *ip_address); + +/** @} */ + +// Helper functions +/** + * @brief Initializes the Wi-Fi client interface. + * + * This function initializes the Wi-Fi client with the specified configuration and event handler. + * + * @param interface The network interface to initialize. + * @param configuration Pointer to the configuration parameters. + * @param context User-defined context passed to the event handler. + * @param event_handler Callback function for network events. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_client_init(sl_net_interface_t interface, + const void *configuration, + void *context, + sl_net_event_handler_t event_handler); + +/** + * @brief Deinitializes the Wi-Fi client interface. + * + * This function deinitializes the Wi-Fi client, freeing any resources allocated during initialization. + * + * @param interface The network interface to deinitialize. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_client_deinit(sl_net_interface_t interface); + +/** + * @brief Brings up the Wi-Fi client interface. + * + * This function activates the Wi-Fi client interface using the specified profile. + * + * @param interface The network interface to activate. + * @param profile_id The profile ID to use for connection. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_client_up(sl_net_interface_t interface, sl_net_profile_id_t profile_id); + +/** + * @brief Brings down the Wi-Fi client interface. + * + * This function deactivates the Wi-Fi client interface. + * + * @param interface The network interface to deactivate. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_client_down(sl_net_interface_t interface); + +/** + * @brief Initializes the Wi-Fi AP (Access Point) interface. + * + * This function initializes the Wi-Fi AP with the specified configuration and event handler. + * + * @param interface The network interface to initialize. + * @param configuration Pointer to the configuration parameters. + * @param context User-defined context passed to the event handler. + * @param event_handler Callback function for network events. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_ap_init(sl_net_interface_t interface, + const void *configuration, + const void *context, + sl_net_event_handler_t event_handler); + +/** + * @brief Deinitializes the Wi-Fi AP interface. + * + * This function deinitializes the Wi-Fi AP, freeing any resources allocated during initialization. + * + * @param interface The network interface to deinitialize. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_ap_deinit(sl_net_interface_t interface); + +/** + * @brief Brings up the Wi-Fi AP interface. + * + * This function activates the Wi-Fi AP interface using the specified profile. + * + * @param interface The network interface to activate. + * @param profile_id The profile ID to use for the AP. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_ap_up(sl_net_interface_t interface, sl_net_profile_id_t profile_id); + +/** + * @brief Brings down the Wi-Fi AP interface. + * + * This function deactivates the Wi-Fi AP interface. + * + * @param interface The network interface to deactivate. + * @return sl_status_t Status of the operation. + */ +sl_status_t sl_net_wifi_ap_down(sl_net_interface_t interface); diff --git a/wiseconnect/components/service/network_manager/inc/sl_net_constants.h b/wiseconnect/components/service/network_manager/inc/sl_net_constants.h new file mode 100644 index 000000000..2791a10b9 --- /dev/null +++ b/wiseconnect/components/service/network_manager/inc/sl_net_constants.h @@ -0,0 +1,296 @@ +/***************************************************************************/ /** + * @file + * @brief Networking constants + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include +#include +#include "sl_wifi_constants.h" + +/// Network Interface Type mask +#define NETWORK_INTERFACE_TYPE_MASK 0xFFF8 + +/// Interface Type Selection +#define SL_NET_INTERFACE_TYPE(x) (x & NETWORK_INTERFACE_TYPE_MASK) + +/** \addtogroup SL_NET_CONSTANTS Constants + * @{ */ + +// Enumeration of network interfaces. +// @note Only Wi-Fi client and Wi-Fi access point interfaces currently supported. +/** + * @enum sl_net_interface_t + * @brief Enumeration of network interfaces. + * + * @details + * This enumeration defines the various network interfaces supported by the system. Currently, only `SL_NET_WIFI_CLIENT_INTERFACE` and `SL_NET_WIFI_AP_INTERFACE` are supported. + */ +typedef enum { + SL_NET_WIFI_CLIENT_INTERFACE = (1 << 3), ///< Wi-Fi Client Interface + SL_NET_WIFI_AP_INTERFACE = (2 << 3), ///< Wi-Fi Access Point Interface + SL_NET_ETHERNET_INTERFACE = (3 << 3), ///< Ethernet Interface (not currently supported) + SL_NET_THREAD_INTERFACE = (4 << 3), ///< Thread Interface (not currently supported) + SL_NET_BLUETOOTH_INTERFACE = (5 << 3), ///< Bluetooth Interface (not currently supported) + SL_NET_ZWAVE_INTERFACE = (6 << 3), ///< Z-Wave Interface (not currently supported) +} sl_net_interface_t; +/** @} */ + +/// WiFi Client Interface +#define SL_NET_WIFI_CLIENT_INTERFACE (1 << 3) + +/// WiFi Access Point Interface +#define SL_NET_WIFI_AP_INTERFACE (2 << 3) + +/// Ethernet Interface +#define SL_NET_ETHERNET_INTERFACE (3 << 3) + +/// Thread Interface +#define SL_NET_THREAD_INTERFACE (4 << 3) + +/// Bluetooth Interface +#define SL_NET_BLUETOOTH_INTERFACE (5 << 3) + +/// Zwave Interface +#define SL_NET_ZWAVE_INTERFACE (6 << 3) + +/** \addtogroup SL_NET_CONSTANTS Constants + * @{ */ +/** + * @enum sl_net_dns_resolution_ip_type_t + * @brief Enumeration of DNS resolution IP types. + * + * @details + * This enumeration defines the types of IP addresses that can be resolved by DNS. It includes both IPv4 and IPv6 address types. + */ +typedef enum { + SL_NET_DNS_TYPE_IPV4, ///< IPV4 DNS Address resolution. + SL_NET_DNS_TYPE_IPV6 ///< IPV6 DNS Address resolution. +} sl_net_dns_resolution_ip_type_t; + +/** + * @enum sl_net_event_t + * @brief Enumeration of SL-Net Events. + * + * @details + * This enumeration defines the various network events that can be handled by the system. Each event type corresponds to a specific network-related occurrence. + */ +typedef enum { + SL_NET_PING_RESPONSE_EVENT, ///< Event triggered when a ping response is received. + SL_NET_DNS_RESOLVE_EVENT, ///< Event triggered when a DNS address resolution occurs. + SL_NET_OTA_FW_UPDATE_EVENT, ///< Event triggered when an OTA firmware update is completed. + SL_NET_DHCP_NOTIFICATION_EVENT, ///< Event triggered when a DHCP notification is received. + SL_NET_IP_ADDRESS_CHANGE_EVENT, ///< Event triggered when there is a DHCP IP address change. + SL_NET_EVENT_COUNT ///< Represents the maximum count of events. Used internally by the SDK. +} sl_net_event_t; + +/** + * @enum sl_net_profile_id_t + * @brief Enumeration of SL Network profile IDs. + * + * @details + * This enumeration defines the various profile IDs that can be used in the SL Network. Each profile ID corresponds to a specific network profile. + * + * @note + * Ethernet, Thread, and Z-Wave profiles are defined but not currently supported. + */ +typedef enum { + SL_NET_PROFILE_ID_0 = 0, ///< Profile Id 0 + SL_NET_PROFILE_ID_1 = 1, ///< Profile Id 1 + SL_NET_PROFILE_ID_2 = 2, ///< Profile Id 2 + SL_NET_PROFILE_ID_3 = 3, ///< Profile Id 3 + SL_NET_PROFILE_ID_4 = 4, ///< Profile Id 4 + SL_NET_PROFILE_ID_5 = 5, ///< Profile Id 5 + SL_NET_PROFILE_ID_6 = 6, ///< Profile Id 6 + SL_NET_PROFILE_ID_7 = 7, ///< Profile Id 7 + SL_NET_PROFILE_ID_8 = 8, ///< Profile Id 8 + SL_NET_PROFILE_ID_9 = 9, ///< Profile Id 9 + SL_NET_PROFILE_ID_10 = 10, ///< Profile Id 10 + + SL_NET_DEFAULT_WIFI_CLIENT_PROFILE_ID = SL_NET_PROFILE_ID_0, ///< Wi-Fi Client Default Profile. + SL_NET_DEFAULT_WIFI_AP_PROFILE_ID = SL_NET_PROFILE_ID_0, ///< Wi-Fi Access Point Default Profile. + SL_NET_DEFAULT_ETHERNET_PROFILE_ID = SL_NET_PROFILE_ID_0, ///< Ethernet Default Profile (not currently supported). + SL_NET_DEFAULT_THREAD_PROFILE_ID = SL_NET_PROFILE_ID_0, ///< Thread Default Profile (not currently supported). + SL_NET_DEFAULT_ZWAVE_PROFILE_ID = SL_NET_PROFILE_ID_0, ///< Zwave Default Profile (not currently supported). +} sl_net_profile_id_t; + +/** + * @enum sl_net_credential_type_t + * @brief Enumeration of network credential types. + * + * @details + * This enumeration defines the various types of network credentials that can be used for authentication and security purposes. + */ +typedef enum { + SL_NET_INVALID_CREDENTIAL_TYPE, ///< Invalid Credential Type. + SL_NET_WIFI_PSK, ///< Wi-Fi PSk Credential. + SL_NET_WIFI_PMK, ///< Wi-Fi PMK Credential. + SL_NET_WIFI_WEP, ///< Wi-Fi WEP Credential. + SL_NET_CERTIFICATE, ///< TLS Client Certificate. + SL_NET_PUBLIC_KEY, ///< TLS Certificate Public key. + SL_NET_PRIVATE_KEY, ///< TLS Certificate Private key. + SL_NET_PACK_FILE, ///< EAP Fast Pack File. + SL_NET_SIGNING_CERTIFICATE, ///< TLS CA Certificate. + SL_NET_HTTP_CLIENT_CREDENTIAL, ///< HTTP Client Credential. + SL_NET_EAP_CLIENT_CREDENTIAL, ///< Wi-Fi EAP Credential. + SL_NET_MQTT_CLIENT_CREDENTIAL ///< MQTT Client Credential. +} sl_net_credential_type_t; + +/** + * @typedef sl_net_certificate_id_t + * @brief Unique identifier for a certificate in the certificate store. + * + * @details + * This defines a unique identifier for the certificates stored in the certificate store. It is used as a reference and to manage certificates within the system. + */ +typedef uint32_t sl_net_certificate_id_t; + +/** + * @enum sl_net_credential_id_t + * @brief Enumeration of network credential identifiers. + * + * @details + * This enumeration defines the various identifiers for network credentials used within the system. Each identifier corresponds to a specific type of credential. + * + * @note + * - In case of @ref sl_net_credential_type_t of @ref SL_NET_CERTIFICATE, @ref SL_NET_PUBLIC_KEY, @ref SL_NET_PRIVATE_KEY, @ref SL_NET_SIGNING_CERTIFICATE, @ref SL_NET_PACK_FILE, the user can ONLY set @ref SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID, @ref SL_NET_WIFI_EAP_SERVER_CREDENTIAL_ID, @ref SL_NET_TLS_CLIENT_CREDENTIAL_START, or @ref SL_NET_TLS_SERVER_CREDENTIAL_START at a time for Si91x devices. + */ +typedef enum { + SL_NET_INVALID_CREDENTIAL_ID = 0, ///< Invalid Credential Id. + SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID = 1, ///< Wi-Fi Client Credential Id. + ///< @note In case of `Basic Network Configuration Manager`, by default `default_wifi_client_credential` from `sl_net_default_values.h` is used. User can choose to override this by setting the credential using @ref sl_net_set_credential. + SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID = 2, ///< Wi-Fi Access Point Credential Id. + ///< @note In case of `Basic Network Configuration Manager`, by default `default_wifi_ap_credential` from `sl_net_default_values.h` is used. User can choose to override this by setting the credential using @ref sl_net_set_credential. + SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID = 3, ///< Wi-Fi EAP Client Credential Id. + SL_NET_WIFI_EAP_SERVER_CREDENTIAL_ID = 4, ///< Wi-Fi EAP Server Credential Id. + SL_NET_USER_CREDENTIAL_ID = 5, ///< User Credential Id. + SL_NET_TLS_CLIENT_CREDENTIAL_START = (1 << 8), ///< TLS Client Credential Id. + SL_NET_TLS_SERVER_CREDENTIAL_START = (2 << 8), ///< TLS Server Credential Id. + SL_NET_MQTT_SERVER_CREDENTIAL_START = (3 << 8), ///< MQTT Server Credential Id. + SL_NET_MQTT_CLIENT_CREDENTIAL_START = (4 << 8), ///< MQTT Client Credential Id. + SL_NET_HTTP_SERVER_CREDENTIAL_START = (5 << 8), ///< HTTP Server Credential Id. + SL_NET_HTTP_CLIENT_CREDENTIAL_START = (6 << 8), ///< HTTP Client Credential Id. +} sl_net_credential_id_t; + +/** + * @def SL_NET_CREDENTIAL_GROUP_MASK + * @brief Mask for extracting the credential group from a credential ID. + * + * @details + * This mask is used to extract the group portion of a credential ID. It helps in identifying the group to which a credential belongs. + * + * The credential group can be one of the value from @ref sl_net_credential_id_t. + */ +#define SL_NET_CREDENTIAL_GROUP_MASK 0xFF00 + +/** + * @def SL_NET_TLS_CLIENT_CREDENTIAL_ID(x) + * @brief Macro to generate a TLS Client Credential ID. + * + * @details + * This macro generates a unique TLS Client Credential ID by adding an offset to the base TLS Client Credential ID. + * + * x Offset to be added to the base TLS Client Credential ID. + * + * @note + * - In case of @ref sl_net_credential_type_t of @ref SL_NET_CERTIFICATE, @ref SL_NET_PUBLIC_KEY, @ref SL_NET_PRIVATE_KEY, @ref SL_NET_SIGNING_CERTIFICATE, @ref SL_NET_PACK_FILE, the valid values for x are 0 to 2 for Si91x devices. + * - In case of other types in @ref sl_net_credential_type_t, the valid values for x is only 0. + */ +#define SL_NET_TLS_CLIENT_CREDENTIAL_ID(x) (SL_NET_TLS_CLIENT_CREDENTIAL_START + x) + +/** + * @def SL_NET_TLS_SERVER_CREDENTIAL_ID(x) + * @brief Macro to generate a TLS Server Credential ID. + * + * @details + * This macro generates a unique TLS Server Credential ID by adding an offset to the base TLS Server Credential ID. + * + * x Offset to be added to the base TLS Server Credential ID. + * + * @note + * - In case of @ref sl_net_credential_type_t of @ref SL_NET_CERTIFICATE, @ref SL_NET_PUBLIC_KEY, @ref SL_NET_PRIVATE_KEY, @ref SL_NET_SIGNING_CERTIFICATE, @ref SL_NET_PACK_FILE, the valid values for x are 0 to 2 for Si91x devices. + * - In case of other types in @ref sl_net_credential_type_t, the valid values for x is only 0. + */ +#define SL_NET_TLS_SERVER_CREDENTIAL_ID(x) (SL_NET_TLS_SERVER_CREDENTIAL_START + x) + +/** + * @def SL_NET_MQTT_SERVER_CREDENTIAL_ID(x) + * @brief Macro to generate an MQTT Server Credential ID. + * + * @details + * This macro generates a unique MQTT Server Credential ID by adding an offset to the base MQTT Server Credential ID. + * + * x Offset to be added to the base MQTT Server Credential ID. + * + * @note + * The valid values for x is only 0. + */ +#define SL_NET_MQTT_SERVER_CREDENTIAL_ID(x) (SL_NET_MQTT_SERVER_CREDENTIAL_START + x) + +/** + * @def SL_NET_MQTT_CLIENT_CREDENTIAL_ID(x) + * @brief Macro to generate an MQTT Client Credential ID. + * + * @details + * This macro generates a unique MQTT Client Credential ID by adding an offset to the base MQTT Client Credential ID. + * + * x Offset to be added to the base MQTT Client Credential ID. + * + * @note + * The valid values for x is only 0. + */ +#define SL_NET_MQTT_CLIENT_CREDENTIAL_ID(x) (SL_NET_MQTT_CLIENT_CREDENTIAL_START + x) + +/** + * @def SL_NET_HTTP_SERVER_CREDENTIAL_ID(x) + * @brief Macro to generate an HTTP Server Credential ID. + * + * @details + * This macro generates a unique HTTP Server Credential ID by adding an offset to the base HTTP Server Credential ID. + * + * x Offset to be added to the base HTTP Server Credential ID. + * + * @note + * The valid values for x is only 0. + */ +#define SL_NET_HTTP_SERVER_CREDENTIAL_ID(x) (SL_NET_HTTP_SERVER_CREDENTIAL_START + x) + +/** + * @def SL_NET_HTTP_CLIENT_CREDENTIAL_ID(x) + * @brief Macro to generate an HTTP Client Credential ID. + * + * @details + * This macro generates a unique HTTP Client Credential ID by adding an offset to the base HTTP Client Credential ID. + * + * x Offset to be added to the base HTTP Client Credential ID. + * + * @note + * The valid values for x is only 0. + */ +#define SL_NET_HTTP_CLIENT_CREDENTIAL_ID(x) (SL_NET_HTTP_CLIENT_CREDENTIAL_START + x) +/** @} */ diff --git a/wiseconnect/components/service/network_manager/inc/sl_net_dns.h b/wiseconnect/components/service/network_manager/inc/sl_net_dns.h new file mode 100644 index 000000000..37f4245c1 --- /dev/null +++ b/wiseconnect/components/service/network_manager/inc/sl_net_dns.h @@ -0,0 +1,115 @@ +/***************************************************************************/ /** + * @file sl_net_dns.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_ip_types.h" +#include "sl_status.h" +#include "sl_net_constants.h" + +/** \addtogroup SL_NET_TYPES Types + * @{ */ + +/** + * @brief Structure to hold DNS server addresses for configuration. + * + * @details + * This structure contains pointers to the primary and secondary DNS server addresses. + * It is used as a parameter in the sl_net_set_dns_server function to set the DNS server IP addresses. + */ +typedef struct { + sl_ip_address_t *primary_server_address; ///< Primary DNS server address + sl_ip_address_t *secondary_server_address; ///< Secondary DNS server address +} sl_net_dns_address_t; + +/** @} */ + +/** + * \addtogroup NET_INTERFACE_FUNCTIONS Network Interface + * \ingroup SL_NET_FUNCTIONS + * @{ */ + +/** + * @brief + * Resolve the given host name to an IP address. + * + * @details + * This function resolves a host name to its corresponding IP address. It requires + * the DNS client feature to be enabled in the TCP/IP feature bitmap before calling. + * + + * + * @pre Pre-conditions: + * - The [SL_SI91X_TCP_IP_FEAT_DNS_CLIENT](../wiseconnect-api-reference-guide-si91x-driver/si91-x-tcp-ip-feature-bitmap#sl-si91-x-tcp-ip-feat-dns-client) bit should be enabled in the TCP/IP feature bitmap. + * + * @param[in] host_name + * Host name that needs to be resolved. + * @param[in] timeout + * Timeout in milliseconds. + * - If the timeout value is greater than zero, the caller will be blocked until the timeout period to get the response. + * - If the value is zero, the response will be sent through @ref sl_net_event_handler_t. + * + * @param[in] dns_resolution_ip + * DNS resolution by IP of type @ref sl_net_dns_resolution_ip_type_t. + * @param[out] ip_address + * IP address object to store resolved IP address of type [sl_ip_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ip-address-t). + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + */ +sl_status_t sl_net_dns_resolve_hostname(const char *host_name, + const uint32_t timeout, + const sl_net_dns_resolution_ip_type_t dns_resolution_ip, + sl_ip_address_t *ip_address); + +/** + * @brief + * Sets DNS server IP addresses. + * + * @details + * This function configures the DNS server IP addresses for the specified network interface. + * + * If both primary and secondary server addresses are NULL, the DNS mode will be set to DHCP. + * Otherwise, the DNS mode will be set to static. + * + * @pre Pre-conditions: + * - The [SL_SI91X_TCP_IP_FEAT_DNS_CLIENT](../wiseconnect-api-reference-guide-si91x-driver/si91-x-tcp-ip-feature-bitmap#sl-si91-x-tcp-ip-feat-dns-client) bit should be enabled in the TCP/IP feature bitmap. + * + * @param[in] interface + * The network interface of type @ref sl_net_interface_t. + * + * @param[in] address + * The structure containing the primary and secondary server addresses of type @ref sl_net_dns_address_t. + * + * @return + * sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + */ +sl_status_t sl_net_set_dns_server(sl_net_interface_t interface, const sl_net_dns_address_t *address); + +/** @} */ diff --git a/wiseconnect/components/service/network_manager/inc/sl_net_ip_types.h b/wiseconnect/components/service/network_manager/inc/sl_net_ip_types.h new file mode 100644 index 000000000..2aa0b6fb9 --- /dev/null +++ b/wiseconnect/components/service/network_manager/inc/sl_net_ip_types.h @@ -0,0 +1,123 @@ +/***************************************************************************/ /** + * @file sl_net_ip_types.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include +#include +#include "sl_ip_types.h" + +/** \addtogroup SL_NET_TYPES Types + * @{ */ + +/** + * @brief IPv4 address settings for a network interface. + * + * @details + * This structure holds the IPv4 address configuration for a network interface, including the IP address, gateway, and netmask. + * + * @note + * Each field is of type [sl_ipv4_address_t](../wiseconnect-api-reference-guide-common/sl-ipv4-address-t). + */ +typedef struct { + sl_ipv4_address_t + ip_address; ///< IPv4 address of type [sl_ipv4_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ipv4-address-t) + sl_ipv4_address_t + gateway; ///< IPv4 gateway address of [sl_ipv4_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ipv4-address-t) + sl_ipv4_address_t + netmask; ///< IPv4 netmask of type of [sl_ipv4_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ipv4-address-t) +} sl_net_ipv4_setting_t; + +/** + * @brief IPv6 address settings for a network interface. + * + * @details + * This structure holds the IPv6 address configuration for a network interface, including the link-local address, global address, and gateway. + * + * @note + * Each field is of type [sl_ipv6_address_t](../wiseconnect-api-reference-guide-common/sl-ipv6-address-t). + */ +typedef struct { + sl_ipv6_address_t + link_local_address; ///< IPv6 link local address of type [sl_ipv6_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ipv6-address-t) + sl_ipv6_address_t + global_address; ///< IPv6 global address of type [sl_ipv6_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ipv6-address-t) + sl_ipv6_address_t + gateway; ///< IPv6 gateway address of type of [sl_ipv6_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ipv6-address-t) +} sl_net_ipv6_setting_t; + +/** + * @brief Structure representing the DHCP configuration for the network manager. + * + * This structure holds the DHCP configuration parameters for the network manager. + * It includes the minimum and maximum retry intervals for discovery and request, + * as well as the minimum and maximum number of retries for discovery and request. + * + * @note + * This configuration is not supported for IPv6 in SI91X_INTERNAL_STACK. + */ +typedef struct { + uint16_t min_discover_retry_interval; ///< Minimum retry interval for discovery + uint16_t max_discover_retry_interval; ///< Maximum retry interval for discovery + uint16_t min_request_retry_interval; ///< Minimum retry interval for request + uint16_t max_request_retry_interval; ///< Maximum retry interval for request + uint8_t min_discover_retries; ///< Minimum number of retries for discovery + uint8_t max_request_retries; ///< Maximum number of retries for request +} sl_net_dhcp_configuration_t; + +/// IP configuration for a network interface +typedef struct { + sl_ip_management_t + mode; ///< IP Assignment Type of [sl_ip_management_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-constants#sl-ip-management-t) + sl_ip_address_type_t + type; ///< IP Address Type of [sl_ip_address_type_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-net-constants#sl-ip-address-type-t) + char *host_name; ///< Host name visible on network + struct { + sl_net_ipv4_setting_t + v4; ///< IPv4 setting to be used in case of static IP address assignment of type @ref sl_net_ipv4_setting_t + sl_net_ipv6_setting_t + v6; ///< IPv6 setting to be used in case of static IP address assignment of type @ref sl_net_ipv6_setting_t + } ip; ///< IP setting to be used for static IP address assignment + + sl_net_dhcp_configuration_t dhcp_config; ///< DHCP configuration for the network manager +} sl_net_ip_configuration_t; + +/// IP Address of a network interface +typedef struct { + sl_ip_management_t + mode; ///< IP Assignment Type of [sl_ip_management_t](../wiseconnect-api-reference-guide-common/ip-addresses#sl-ip-management-t) + sl_ip_address_type_t + type; ///< IP Address Type of [sl_ip_address_type_t](../wiseconnect-api-reference-guide-common/ip-addresses#sl-ip-address-type-t) + sl_net_ipv4_setting_t + v4; ///< IPv4 setting to be used in case of static IP address assignment of type @ref sl_net_ipv4_setting_t + sl_net_ipv6_setting_t + v6; ///< IPv6 setting to be used in case of static IP address assignment of type @ref sl_net_ipv6_setting_t +} sl_net_ip_address_t; + +/** @} */ \ No newline at end of file diff --git a/wiseconnect/components/service/network_manager/inc/sl_net_types.h b/wiseconnect/components/service/network_manager/inc/sl_net_types.h new file mode 100644 index 000000000..bb2c3720a --- /dev/null +++ b/wiseconnect/components/service/network_manager/inc/sl_net_types.h @@ -0,0 +1,103 @@ +/***************************************************************************/ /** + * @file + * @brief Network types + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#pragma once + +#include "sl_ip_types.h" +#include "sl_net_constants.h" +#include "sl_net_ip_types.h" +#include "sl_constants.h" +#include "sl_status.h" +#include + +/** \addtogroup SL_NET_TYPES Types + * @{ */ + +/** + * @typedef sl_net_event_handler_t + * @brief Generic callback for network events. + * + * @details + * This typedef defines a callback function for handling various network events. The callback function receives the event type, status, data, and data length as parameters. + * + * @param event + * Network event of type @ref sl_net_event_t. + * | @ref sl_net_event_t | DataType | + * |:-------------------------------------|:---------------------------------------| + * | SL_NET_PING_RESPONSE_EVENT | @ref sl_si91x_ping_response_t | + * | SL_NET_DNS_RESOLVE_EVENT | [sl_ip_address_t](../wiseconnect-api-reference-guide-nwk-mgmt/sl-ip-address-t) | + * | SL_NET_OTA_FW_UPDATE_EVENT | NULL in case of success, else uint16_t chunk number in case of failure | + * | SL_NET_DHCP_NOTIFICATION_EVENT | NULL | + * | SL_NET_IP_ADDRESS_CHANGE_EVENT | @ref sl_net_ip_configuration_t | + * | SL_NET_EVENT_COUNT | Not Applicable, Internally used by SDK | + * + * @param status + * Status of type sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + * + * @param data + * Data received, corresponding to the event type. + * + * @param data_length + * Length of the data received. + * + * @return + * Status of type sl_status_t. See [Status Codes](https://docs.silabs.com/gecko-platform/latest/platform-common/status) and [Additional Status Codes](../wiseconnect-api-reference-guide-err-codes/sl-additional-status-errors) for details. + */ +typedef sl_status_t (*sl_net_event_handler_t)(sl_net_event_t event, + sl_status_t status, + void *data, + uint32_t data_length); + +/** + * @brief Abstract profile for SL Net. + * + * @details + * This type represents an abstract profile in the SL Net framework. + * + * @note + * This type is used internally by the SL Net framework and should be cast to the appropriate profile type when used. + */ +typedef void sl_net_profile_t; + +/** + * @brief Ping Response structure. + * + * @details + * This structure holds the response data for a ping operation, including the IP version, ping size, and the pinged IP address. + */ +typedef struct { + uint16_t + ip_version; ///< IP version (e.g., IPv4 or IPv6). One of the values from [sl_ip_version_t](../wiseconnect-api-reference-guide-common/ip-addresses#sl-ip-version-t). + uint16_t ping_size; ///< Size of the ping packet + union { + uint8_t ipv4_address[4]; ///< IPv4 address + uint8_t ipv6_address[16]; ///< IPv6 address + } ping_address; ///< Pinged IP address +} sl_si91x_ping_response_t; +/** @} */ diff --git a/wiseconnect/components/service/network_manager/inc/sl_net_wifi_types.h b/wiseconnect/components/service/network_manager/inc/sl_net_wifi_types.h new file mode 100644 index 000000000..b69b6ec8c --- /dev/null +++ b/wiseconnect/components/service/network_manager/inc/sl_net_wifi_types.h @@ -0,0 +1,86 @@ +/***************************************************************************/ /** + * @file sl_net_wifi_types.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once +#include "sl_net_types.h" +#include "sl_net_ip_types.h" +#include "sl_wifi_device.h" // The device specific Wi-Fi structures and definitions +#include "sl_wifi_types.h" + +/** \addtogroup SL_NET_TYPES + * @{ */ +/** + * @brief Network Wi-Fi client profile. + * + * @details + * This structure holds the configuration for a Wi-Fi client profile, including the Wi-Fi client settings and the network IP configuration. + */ +typedef struct { + sl_wifi_client_configuration_t + config; ///< Wi-Fi client configuration of type [sl_wifi_client_configuration_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-client-configuration-t) + sl_net_ip_configuration_t ip; ///< Network IP configuration of type @ref sl_net_ip_configuration_t +} sl_net_wifi_client_profile_t; + +/** + * @brief Network Wi-Fi AP profile. + * + * @details + * This structure holds the configuration for a Wi-Fi Access Point (AP) profile, including the Wi-Fi AP settings and the network IP configuration. + */ +typedef struct { + sl_wifi_ap_configuration_t + config; ///< Wi-Fi AP configuration of type [sl_wifi_ap_configuration_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-ap-configuration-t) + sl_net_ip_configuration_t ip; ///< Network IP configuration of type @ref sl_net_ip_configuration_t +} sl_net_wifi_ap_profile_t; + +/** + * @brief Network Wi-Fi PSK credential entry. + * + * @details + * This structure holds the Pre-Shared Key (PSK) credentials for a Wi-Fi network, including the credential type, data length, and the actual credential data. + */ +typedef struct { + sl_net_credential_type_t type; ///< Network credential type of @ref sl_net_credential_type_t + uint16_t data_length; ///< Data length + uint8_t data[196]; ///< Data +} sl_net_wifi_psk_credential_entry_t; + +/** + * @brief Network Wi-Fi EAP credential entry. + * + * @details + * This structure holds the Extensible Authentication Protocol (EAP) credentials for a Wi-Fi network, including the credential type, data length, and the actual EAP credential data. + */ +typedef struct { + sl_net_credential_type_t type; ///< Network credential type of @ref sl_net_credential_type_t + uint16_t data_length; ///< Data length + sl_wifi_eap_credential_t + data; ///< Data of type [sl_wifi_eap_credential_t](../wiseconnect-api-reference-guide-wi-fi/sl-wifi-eap-credential-t) +} sl_net_wifi_eap_credential_entry_t; +/** @} */ diff --git a/wiseconnect/components/service/network_manager/si91x/sl_net_si91x.c b/wiseconnect/components/service/network_manager/si91x/sl_net_si91x.c new file mode 100644 index 000000000..9b5d2e09d --- /dev/null +++ b/wiseconnect/components/service/network_manager/si91x/sl_net_si91x.c @@ -0,0 +1,394 @@ +/***************************************************************************/ /** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_status.h" +#include "sl_wifi_types.h" +#include "sl_net.h" +#include "stddef.h" +#include "sl_status.h" +#include "sl_utility.h" +#include "sl_net.h" +#include "sl_wifi.h" +#include "sl_net_wifi_types.h" +#include "sl_net_si91x.h" +#include "sl_si91x_host_interface.h" +#include "sl_si91x_driver.h" +#include "sl_rsi_utility.h" +#include "sl_net_rsi_utility.h" +#include "sl_si91x_core_utilities.h" +#include +#include +#include "sl_wifi_callback_framework.h" +#include "sl_net_dns.h" + +typedef enum { SLI_SI91X_CLIENT = 0, SLI_SI91X_AP = 1, SLI_SI91X_MAX_INTERFACES } sli_si91x_interfaces_t; + +static sl_status_t sli_si91x_send_multicast_request(sl_wifi_interface_t interface, + const sl_ip_address_t *ip_address, + uint8_t command_type); +sl_status_t sl_net_dns_resolve_hostname(const char *host_name, + const uint32_t timeout, + const sl_net_dns_resolution_ip_type_t dns_resolution_ip, + sl_ip_address_t *sl_ip_address); + +extern bool device_initialized; + +static sl_ip_management_t dhcp_type[SLI_SI91X_MAX_INTERFACES] = { 0 }; + +sl_status_t sl_net_wifi_client_init(sl_net_interface_t interface, + const void *configuration, + void *context, + sl_net_event_handler_t event_handler) +{ + UNUSED_PARAMETER(interface); + UNUSED_PARAMETER(context); + sl_status_t status = SL_STATUS_FAIL; + + // Set the user-defined event handler for client mode + sl_si91x_register_event_handler(event_handler); + + status = sl_wifi_init(configuration, NULL, sl_wifi_default_event_handler); + // Verify the initialization status and return it + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_net_wifi_client_deinit(sl_net_interface_t interface) +{ + UNUSED_PARAMETER(interface); + return sl_wifi_deinit(); +} + +sl_status_t sl_net_wifi_client_up(sl_net_interface_t interface, sl_net_profile_id_t profile_id) +{ + UNUSED_PARAMETER(interface); + sl_status_t status; + sl_net_wifi_client_profile_t profile; + + // Get the client profile using the provided profile_id + status = sl_net_get_profile(SL_NET_WIFI_CLIENT_INTERFACE, profile_id, &profile); + VERIFY_STATUS_AND_RETURN(status); + + // Connect to the Wi-Fi network + status = sl_wifi_connect(SL_WIFI_CLIENT_INTERFACE, &profile.config, 18000); + VERIFY_STATUS_AND_RETURN(status); + + // Configure the IP address settings + status = sl_si91x_configure_ip_address(&profile.ip, SL_SI91X_WIFI_CLIENT_VAP_ID); + VERIFY_STATUS_AND_RETURN(status); + dhcp_type[SLI_SI91X_CLIENT] = profile.ip.mode; + + // Set the client profile + status = sl_net_set_profile(SL_NET_WIFI_CLIENT_INTERFACE, profile_id, &profile); + return status; +} + +sl_status_t sl_net_wifi_client_down(sl_net_interface_t interface) +{ + UNUSED_PARAMETER(interface); + + // Disconnect from the Wi-Fi network + return sl_wifi_disconnect(SL_WIFI_CLIENT_INTERFACE); +} + +sl_status_t sl_net_wifi_ap_init(sl_net_interface_t interface, + const void *configuration, + const void *workspace, + sl_net_event_handler_t event_handler) +{ + UNUSED_PARAMETER(interface); + UNUSED_PARAMETER(workspace); + sl_status_t status = SL_STATUS_FAIL; + + // Set the user-defined event handler for AP mode + sl_si91x_register_event_handler(event_handler); + + status = sl_wifi_init(configuration, NULL, sl_wifi_default_event_handler); + VERIFY_STATUS_AND_RETURN(status); + return status; +} + +sl_status_t sl_net_wifi_ap_deinit(sl_net_interface_t interface) +{ + UNUSED_PARAMETER(interface); + return sl_wifi_deinit(); +} + +sl_status_t sl_net_wifi_ap_up(sl_net_interface_t interface, sl_net_profile_id_t profile_id) +{ + UNUSED_PARAMETER(interface); + sl_status_t status; + sl_net_wifi_ap_profile_t profile; + + status = sl_net_get_profile(SL_NET_WIFI_AP_INTERFACE, profile_id, &profile); + VERIFY_STATUS_AND_RETURN(status); + + // Validate if profile configuration is valid + // AP + DHCP client not supported + // AP + link local not supported + if (profile.ip.mode != SL_IP_MANAGEMENT_STATIC_IP) { + return SL_STATUS_INVALID_CONFIGURATION; + } + status = sl_si91x_configure_ip_address(&profile.ip, SL_SI91X_WIFI_AP_VAP_ID); + VERIFY_STATUS_AND_RETURN(status); + dhcp_type[SLI_SI91X_AP] = profile.ip.mode; + + // Set the AP profile + status = sl_net_set_profile(SL_NET_WIFI_AP_INTERFACE, profile_id, &profile); + VERIFY_STATUS_AND_RETURN(status); + + status = sl_wifi_start_ap(SL_WIFI_AP_2_4GHZ_INTERFACE, &profile.config); + VERIFY_STATUS_AND_RETURN(status); + + return status; +} + +sl_status_t sl_net_wifi_ap_down(sl_net_interface_t interface) +{ + UNUSED_PARAMETER(interface); + return sl_wifi_stop_ap(SL_WIFI_AP_INTERFACE); +} + +sl_status_t sl_net_join_multicast_address(sl_net_interface_t interface, const sl_ip_address_t *ip_address) +{ + return sli_si91x_send_multicast_request((sl_wifi_interface_t)interface, ip_address, SL_WIFI_MULTICAST_JOIN); +} + +sl_status_t sl_net_leave_multicast_address(sl_net_interface_t interface, const sl_ip_address_t *ip_address) +{ + return sli_si91x_send_multicast_request((sl_wifi_interface_t)interface, ip_address, SL_WIFI_MULTICAST_LEAVE); +} + +static sl_status_t sli_si91x_send_multicast_request(sl_wifi_interface_t interface, + const sl_ip_address_t *ip_address, + uint8_t command_type) +{ + UNUSED_PARAMETER(interface); + si91x_req_multicast_t multicast = { 0 }; + sl_status_t status = SL_STATUS_OK; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + //Fill IP version and IP address + if (ip_address->type == SL_IPV6) { + multicast.ip_version[0] = 6; + memcpy(multicast.multicast_address.ipv6_address, ip_address->ip.v6.bytes, RSI_IP_ADDRESS_LEN * 4); + } else { + multicast.ip_version[0] = 4; + memcpy(multicast.multicast_address.ipv4_address, ip_address->ip.v4.bytes, RSI_IP_ADDRESS_LEN); + } + multicast.type[0] = command_type; + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_MULTICAST, + SI91X_NETWORK_CMD, + &multicast, + sizeof(multicast), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + VERIFY_STATUS_AND_RETURN(status); + return SL_STATUS_OK; +} + +// Resolve a host name to an IP address using DNS +sl_status_t sl_net_dns_resolve_hostname(const char *host_name, + const uint32_t timeout, + const sl_net_dns_resolution_ip_type_t dns_resolution_ip, + sl_ip_address_t *sl_ip_address) +{ + // Check for a NULL pointer for sl_ip_address + SL_WIFI_ARGS_CHECK_NULL_POINTER(sl_ip_address); + + sl_status_t status; + sl_si91x_packet_t *packet; + sl_wifi_buffer_t *buffer = NULL; + const sl_si91x_dns_response_t *dns_response = { 0 }; + sl_si91x_dns_query_request_t dns_query_request = { 0 }; + + // Determine the wait period based on the timeout value + sl_si91x_wait_period_t wait_period = timeout == 0 ? SL_SI91X_RETURN_IMMEDIATELY : SL_SI91X_WAIT_FOR_RESPONSE(timeout); + // Determine the IP version to be used (IPv4 or IPv6) + dns_query_request.ip_version[0] = (dns_resolution_ip == SL_NET_DNS_TYPE_IPV4) ? 4 : 6; + memcpy(dns_query_request.url_name, host_name, sizeof(dns_query_request.url_name)); + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_DNS_QUERY, + SI91X_NETWORK_CMD, + &dns_query_request, + sizeof(dns_query_request), + wait_period, + NULL, + &buffer); + + // Check if the command failed and free the buffer if it was allocated + if ((status != SL_STATUS_OK) && (buffer != NULL)) { + sl_si91x_host_free_buffer(buffer); + } + VERIFY_STATUS_AND_RETURN(status); + + // Extract the DNS response from the SI91X packet buffer + packet = sl_si91x_host_get_buffer_data(buffer, 0, NULL); + dns_response = (sl_si91x_dns_response_t *)packet->data; + + // Convert the SI91X DNS response to the sl_ip_address format + convert_si91x_dns_response(sl_ip_address, dns_response); + sl_si91x_host_free_buffer(buffer); + return SL_STATUS_OK; +} + +sl_status_t sl_net_set_dns_server(sl_net_interface_t interface, const sl_net_dns_address_t *address) +{ + UNUSED_PARAMETER(interface); + sl_status_t status = 0; + sli_dns_server_add_request_t dns_server_add_request = { 0 }; + + if (!device_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + + //! Check for invalid parameters + if ((address->primary_server_address && address->primary_server_address->type != SL_IPV4 + && address->primary_server_address->type != SL_IPV6) + || (address->secondary_server_address && address->secondary_server_address->type != SL_IPV4 + && address->secondary_server_address->type != SL_IPV6)) { + //! Throw error in case of invalid parameters + return SL_STATUS_INVALID_PARAMETER; + } + + //! Set DNS mode + dns_server_add_request.dns_mode[0] = + (address->primary_server_address == NULL && address->secondary_server_address == NULL) ? 1 /*dhcp*/ : 0 /*static*/; + + if (address->primary_server_address && address->primary_server_address->type == SL_IPV4) { + dns_server_add_request.ip_version[0] = SL_IPV4_VERSION; + //! Fill Primary IP address + memcpy(dns_server_add_request.sli_ip_address1.primary_dns_ipv4, + address->primary_server_address->ip.v4.bytes, + SL_IPV4_ADDRESS_LENGTH); + } else if (address->primary_server_address && address->primary_server_address->type == SL_IPV6) { + dns_server_add_request.ip_version[0] = SL_IPV6_VERSION; + //! Fill Primary IP address + memcpy(dns_server_add_request.sli_ip_address1.primary_dns_ipv6, + address->primary_server_address->ip.v6.bytes, + SL_IPV6_ADDRESS_LENGTH); + } + + if (address->secondary_server_address && address->secondary_server_address->type == SL_IPV4) { + dns_server_add_request.ip_version[0] = SL_IPV4_VERSION; + //! Fill Secondary IP address + memcpy(dns_server_add_request.sli_ip_address2.secondary_dns_ipv4, + address->secondary_server_address->ip.v4.bytes, + SL_IPV4_ADDRESS_LENGTH); + } else if (address->secondary_server_address && address->secondary_server_address->type == SL_IPV6) { + dns_server_add_request.ip_version[0] = SL_IPV6_VERSION; + //! Fill Secondary IP address + memcpy(dns_server_add_request.sli_ip_address2.secondary_dns_ipv6, + address->secondary_server_address->ip.v6.bytes, + SL_IPV6_ADDRESS_LENGTH); + } + + status = sl_si91x_driver_send_command(RSI_WLAN_REQ_DNS_SERVER_ADD, + SI91X_NETWORK_CMD, + &dns_server_add_request, + sizeof(dns_server_add_request), + SL_SI91X_WAIT_FOR_COMMAND_SUCCESS, + NULL, + NULL); + + return status; +} + +sl_status_t sl_net_configure_ip(sl_net_interface_t interface, + const sl_net_ip_configuration_t *ip_config, + uint32_t timeout) +{ + uint8_t vap_id = 0; + sl_net_ip_configuration_t config = { 0 }; + + if (SL_NET_WIFI_CLIENT_INTERFACE == SL_NET_INTERFACE_TYPE(interface)) { + vap_id = SL_SI91X_WIFI_CLIENT_VAP_ID; + dhcp_type[SLI_SI91X_CLIENT] = ip_config->mode; + } else if (SL_NET_WIFI_AP_INTERFACE == SL_NET_INTERFACE_TYPE(interface)) { + vap_id = SL_SI91X_WIFI_AP_VAP_ID; + dhcp_type[SLI_SI91X_AP] = ip_config->mode; + } else { + return SL_STATUS_WIFI_UNSUPPORTED; + } + + memcpy(&config, ip_config, sizeof(sl_net_ip_configuration_t)); + return sli_si91x_configure_ip_address(&config, vap_id, timeout); +} + +sl_status_t sl_net_get_ip_address(sl_net_interface_t interface, sl_net_ip_address_t *ip_address, uint32_t timeout) +{ + uint8_t vap_id = 0; + sl_status_t status = 0; + sl_net_ip_configuration_t ip_config = { 0 }; + + if (SL_NET_WIFI_CLIENT_INTERFACE == SL_NET_INTERFACE_TYPE(interface)) { + vap_id = SL_SI91X_WIFI_CLIENT_VAP_ID; + ip_address->mode = dhcp_type[SLI_SI91X_CLIENT]; + } else if (SL_NET_WIFI_AP_INTERFACE == SL_NET_INTERFACE_TYPE(interface)) { + vap_id = SL_SI91X_WIFI_AP_VAP_ID; + ip_address->mode = dhcp_type[SLI_SI91X_AP]; + return SL_STATUS_OK; + } else { + return SL_STATUS_WIFI_UNSUPPORTED; + } + + ip_config.mode = SL_IP_MANAGEMENT_DHCP; +#ifdef SLI_SI91X_ENABLE_IPV6 + ip_config.type = SL_IPV6; +#else + ip_config.type = SL_IPV4; +#endif + status = sli_si91x_configure_ip_address(&ip_config, vap_id, timeout); + if (status != SL_STATUS_OK) { + return status; + } + + ip_address->type = ip_config.type; + // Copy the IPv4 addresses to the address structure + memcpy(ip_address->v4.ip_address.bytes, (const uint8_t *)ip_config.ip.v4.ip_address.bytes, sizeof(sl_ipv4_address_t)); + memcpy(ip_address->v4.netmask.bytes, (const uint8_t *)ip_config.ip.v4.netmask.bytes, sizeof(sl_ipv4_address_t)); + memcpy(ip_address->v4.gateway.bytes, (const uint8_t *)ip_config.ip.v4.gateway.bytes, sizeof(sl_ipv4_address_t)); + + // Copy the IPv6 addresses to the address structure + memcpy(&ip_address->v6.link_local_address.bytes, + (const uint8_t *)ip_config.ip.v6.link_local_address.bytes, + sizeof(sl_ipv6_address_t)); + memcpy(&ip_address->v6.global_address.bytes, + (const uint8_t *)ip_config.ip.v6.global_address.bytes, + sizeof(sl_ipv6_address_t)); + memcpy(&ip_address->v6.gateway.bytes, (const uint8_t *)ip_config.ip.v6.gateway.bytes, sizeof(sl_ipv6_address_t)); + + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/service/network_manager/src/sl_net.c b/wiseconnect/components/service/network_manager/src/sl_net.c new file mode 100644 index 000000000..efa69d952 --- /dev/null +++ b/wiseconnect/components/service/network_manager/src/sl_net.c @@ -0,0 +1,219 @@ +/***************************************************************************/ /** + * @file sl_net.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_net.h" +#include "sl_net_constants.h" +#include "sl_wifi_device.h" +#include "sl_net_default_values.h" + +#ifndef NETWORK_INTERFACE_VALID +#error Need to define NETWORK_INTERFACE_VALID in sl_board_configuration.h +#endif + +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_CLIENT_INTERFACE) || NETWORK_INTERFACE_VALID(SL_NET_WIFI_AP_INTERFACE) +#include "sl_wifi_device.h" +#endif + +sl_status_t sl_net_init(sl_net_interface_t interface, + const void *configuration, + void *network_context, + sl_net_event_handler_t event_handler) +{ + switch (SL_NET_INTERFACE_TYPE(interface)) { +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_CLIENT_INTERFACE) + case SL_NET_WIFI_CLIENT_INTERFACE: + if (configuration == NULL) { + configuration = (const void *)&sl_wifi_default_client_configuration; + } + + sl_net_set_credential(SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID, + default_wifi_client_credential.type, + (const void *)default_wifi_client_credential.data, + default_wifi_client_credential.data_length); + sl_net_set_profile(SL_NET_WIFI_CLIENT_INTERFACE, + SL_NET_DEFAULT_WIFI_CLIENT_PROFILE_ID, + &DEFAULT_WIFI_CLIENT_PROFILE); + return sl_net_wifi_client_init(interface, configuration, network_context, event_handler); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_AP_INTERFACE) + case SL_NET_WIFI_AP_INTERFACE: + if (configuration == NULL) { + configuration = (const void *)&sl_wifi_default_ap_configuration; + } + + sl_net_set_credential(SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID, + default_wifi_ap_credential.type, + (const void *)default_wifi_ap_credential.data, + default_wifi_ap_credential.data_length); + sl_net_set_profile(SL_NET_WIFI_AP_INTERFACE, + SL_NET_DEFAULT_WIFI_AP_PROFILE_ID, + &DEFAULT_WIFI_ACCESS_POINT_PROFILE); + return sl_net_wifi_ap_init(interface, configuration, network_context, event_handler); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_ETHERNET_INTERFACE) + case SL_NET_ETHERNET_INTERFACE: + return sl_net_ethernet_init(interface, configuration, network_context, event_handler); + break; +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_THREAD_INTERFACE) + case SL_NET_THREAD_INTERFACE: + return sl_net_thread_init(interface, configuration, network_context, event_handler); + break; +#endif + default: + return SL_STATUS_NOT_SUPPORTED; + } +} + +sl_status_t sl_net_deinit(sl_net_interface_t interface) +{ + switch (SL_NET_INTERFACE_TYPE(interface)) { +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_CLIENT_INTERFACE) + case SL_NET_WIFI_CLIENT_INTERFACE: + return sl_net_wifi_client_deinit(interface); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_AP_INTERFACE) + case SL_NET_WIFI_AP_INTERFACE: + return sl_net_wifi_ap_deinit(interface); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_ETHERNET_INTERFACE) + case SL_NET_ETHERNET_INTERFACE: + return sl_net_ethernet_deinit(interface); + break; +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_THREAD_INTERFACE) + case SL_NET_THREAD_INTERFACE: + return sl_net_thread_deinit(interface); + break; +#endif + default: + return SL_STATUS_NOT_SUPPORTED; + } +} + +sl_status_t sl_net_up(sl_net_interface_t interface, sl_net_profile_id_t profile_id) +{ + switch (SL_NET_INTERFACE_TYPE(interface)) { +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_CLIENT_INTERFACE) + case SL_NET_WIFI_CLIENT_INTERFACE: + return sl_net_wifi_client_up(interface, profile_id); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_AP_INTERFACE) + case SL_NET_WIFI_AP_INTERFACE: + return sl_net_wifi_ap_up(interface, profile_id); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_ETHERNET_INTERFACE) + case SL_NET_ETHERNET_INTERFACE: + return sl_net_ethernet_up(interface, profile_id); + break; +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_THREAD_INTERFACE) + case SL_NET_THREAD_INTERFACE: + return sl_net_thread_up(interface, profile_id); + break; +#endif + default: + return SL_STATUS_NOT_SUPPORTED; + } +} + +sl_status_t sl_net_down(sl_net_interface_t interface) +{ + switch (SL_NET_INTERFACE_TYPE(interface)) { +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_CLIENT_INTERFACE) + case SL_NET_WIFI_CLIENT_INTERFACE: + return sl_net_wifi_client_down(interface); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_WIFI_AP_INTERFACE) + case SL_NET_WIFI_AP_INTERFACE: + return sl_net_wifi_ap_down(interface); +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_ETHERNET_INTERFACE) + case SL_NET_ETHERNET_INTERFACE: + return sl_net_ethernet_down(interface); + break; +#endif +#if NETWORK_INTERFACE_VALID(SL_NET_THREAD_INTERFACE) + case SL_NET_THREAD_INTERFACE: + return sl_net_thread_down(interface); + break; +#endif + default: + return SL_STATUS_NOT_SUPPORTED; + } +} + +sl_status_t sl_net_inet_addr(const char *addr, uint32_t *value) +{ + uint8_t ip_bytes[5] = { 0 }; + int i; + int digits; + int j; + + if ((NULL == addr) || (NULL == value)) { + return SL_STATUS_INVALID_PARAMETER; + } + + digits = 0; + + // Iterate through the characters in the IP address string + for (i = 0, j = 0; 0 != addr[i]; i++) { + if ('.' == addr[i]) { + ++j; + digits = 0; + continue; + } + + // Check if the character is a digit (0-9) + if ((addr[i] < '0') || (addr[i] > '9')) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Convert character to numeric value and update IP bytes + ip_bytes[j] = (ip_bytes[j] * 10) + (uint8_t)(addr[i] - '0'); + + digits++; + if (digits > 3) { + return SL_STATUS_INVALID_PARAMETER; + } + } + + // Ensure that there are exactly three '.' separators in the IP address + if (j != 3) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Calculate the 32-bit integer value of the IP address + *value = (uint32_t)ip_bytes[0]; + *value |= (uint32_t)(ip_bytes[1] << 8); + *value |= (uint32_t)(ip_bytes[2] << 16); + *value |= (uint32_t)(ip_bytes[3] << 24); + + return SL_STATUS_OK; +} diff --git a/wiseconnect/components/service/network_manager/src/sl_net_basic_profiles.c b/wiseconnect/components/service/network_manager/src/sl_net_basic_profiles.c new file mode 100644 index 000000000..65860e7e2 --- /dev/null +++ b/wiseconnect/components/service/network_manager/src/sl_net_basic_profiles.c @@ -0,0 +1,122 @@ +/***************************************************************************/ /** + * @file sl_net_basic_profiles.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_net.h" +#include "sl_net_ip_types.h" +#include "sl_net_wifi_types.h" +#include "sl_net_default_values.h" +#include + +#define MAX_WIFI_CLIENT_PROFILES 2 +#define MAX_WIFI_AP_PROFILES 2 + +static sl_net_wifi_client_profile_t wifi_client_profiles[MAX_WIFI_CLIENT_PROFILES] = { 0 }; +static sl_net_wifi_ap_profile_t wifi_ap_profiles[MAX_WIFI_AP_PROFILES] = { 0 }; + +sl_status_t sl_net_set_profile(sl_net_interface_t interface, + sl_net_profile_id_t profile_id, + const sl_net_profile_t *profile) +{ + + switch (interface) { +#ifdef SL_WIFI_COMPONENT_INCLUDED + case SL_NET_WIFI_CLIENT_INTERFACE: + if (profile_id >= MAX_WIFI_CLIENT_PROFILES) { + return SL_STATUS_INVALID_INDEX; + } + memcpy(&wifi_client_profiles[profile_id], + (const sl_net_wifi_client_profile_t *)profile, + sizeof(sl_net_wifi_client_profile_t)); + return SL_STATUS_OK; + + case SL_NET_WIFI_AP_INTERFACE: + if (profile_id >= MAX_WIFI_AP_PROFILES) { + return SL_STATUS_INVALID_INDEX; + } + memcpy(&wifi_ap_profiles[profile_id], + (const sl_net_wifi_ap_profile_t *)profile, + sizeof(sl_net_wifi_ap_profile_t)); + return SL_STATUS_OK; +#endif + default: + return SL_STATUS_NOT_SUPPORTED; + } +} + +sl_status_t sl_net_get_profile(sl_net_interface_t interface, sl_net_profile_id_t profile_id, sl_net_profile_t *profile) +{ + + SL_WIFI_ARGS_CHECK_NULL_POINTER(profile); + + switch (interface) { +#ifdef SL_WIFI_COMPONENT_INCLUDED + case SL_NET_WIFI_CLIENT_INTERFACE: + if (profile_id >= MAX_WIFI_CLIENT_PROFILES) { + return SL_STATUS_INVALID_INDEX; + } + memcpy(profile, &wifi_client_profiles[profile_id], sizeof(sl_net_wifi_client_profile_t)); + return SL_STATUS_OK; + + case SL_NET_WIFI_AP_INTERFACE: + if (profile_id >= MAX_WIFI_AP_PROFILES) { + return SL_STATUS_INVALID_INDEX; + } + memcpy(profile, &wifi_ap_profiles[profile_id], sizeof(sl_net_wifi_ap_profile_t)); + return SL_STATUS_OK; +#endif + + default: + return SL_STATUS_NOT_SUPPORTED; + } +} + +sl_status_t sl_net_delete_profile(sl_net_interface_t interface, sl_net_profile_id_t profile_id) +{ + + switch (interface) { +#ifdef SL_WIFI_COMPONENT_INCLUDED + case SL_NET_WIFI_CLIENT_INTERFACE: + if (profile_id >= MAX_WIFI_CLIENT_PROFILES) { + return SL_STATUS_INVALID_INDEX; + } + memset(&wifi_client_profiles[profile_id], 0, sizeof(sl_net_wifi_client_profile_t)); + return SL_STATUS_OK; + + case SL_NET_WIFI_AP_INTERFACE: + if (profile_id >= MAX_WIFI_AP_PROFILES) { + return SL_STATUS_INVALID_INDEX; + } + memset(&wifi_ap_profiles[profile_id], 0, sizeof(sl_net_wifi_ap_profile_t)); + return SL_STATUS_OK; +#endif + + default: + return SL_STATUS_NOT_SUPPORTED; + } +} diff --git a/wiseconnect/components/service/network_manager/src/sl_net_credentials.c b/wiseconnect/components/service/network_manager/src/sl_net_credentials.c new file mode 100644 index 000000000..3c0e14e46 --- /dev/null +++ b/wiseconnect/components/service/network_manager/src/sl_net_credentials.c @@ -0,0 +1,251 @@ +/******************************************************************************* + * @file sl_net_credentials.c + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_net.h" +#include "sl_net_default_values.h" +#include "sl_wifi_credentials.h" +#include "sl_common.h" +#if defined(SLI_SI917) || defined(SLI_SI915) +#include "sl_net_si91x.h" +#endif +#include + +#define CRED_TYPE_CERT 0 +#define CRED_TYPE_CRED 1 + +// [SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID] +// [SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID] + +sl_status_t sl_si91x_delete_credential(sl_net_credential_id_t id, sl_net_credential_type_t type); + +static int sli_si91x_check_cred_type(sl_net_credential_type_t type) +{ + if ((SL_NET_CERTIFICATE == type) || (SL_NET_PUBLIC_KEY == type) || (SL_NET_PRIVATE_KEY == type) + || (SL_NET_SIGNING_CERTIFICATE == type) || (SL_NET_PACK_FILE == type)) { + return CRED_TYPE_CERT; + } + + return CRED_TYPE_CRED; +} + +static sl_status_t sli_si91x_get_wifi_credential_type(sl_net_credential_type_t type, + sl_wifi_credential_type_t *wifi_type) +{ + // Map the network credential type to WiFi credential type + switch (type) { + case SL_NET_WIFI_PSK: + // Set the credential type to Pre-Shared Key (PSK) + *wifi_type = SL_WIFI_PSK_CREDENTIAL; + break; + case SL_NET_WIFI_PMK: + // Set the credential type to Pairwise Master Key (PMK) + *wifi_type = SL_WIFI_PMK_CREDENTIAL; + break; + case SL_NET_WIFI_WEP: + // Set the credential type to Wired Equivalent Privacy (WEP) + *wifi_type = SL_WIFI_WEP_CREDENTIAL; + break; + case SL_NET_EAP_CLIENT_CREDENTIAL: + // Set the credential type to Extensible Authentication Protocol (EAP) + *wifi_type = SL_WIFI_EAP_CREDENTIAL; + break; + default: + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +static sl_status_t sli_si91x_get_net_credential_type(sl_wifi_credential_type_t type, sl_net_credential_type_t *net_type) +{ + // Map the WiFi credential type to network credential type + switch (type) { + case SL_WIFI_PSK_CREDENTIAL: + // Set the credential type to Pre-Shared Key (PSK) + *net_type = SL_NET_WIFI_PSK; + break; + case SL_WIFI_PMK_CREDENTIAL: + // Set the credential type to Pairwise Master Key (PMK) + *net_type = SL_NET_WIFI_PMK; + break; + case SL_WIFI_WEP_CREDENTIAL: + // Set the credential type to Wired Equivalent Privacy (WEP) + *net_type = SL_NET_WIFI_WEP; + break; + case SL_WIFI_EAP_CREDENTIAL: + // Set the credential type to Extensible Authentication Protocol (EAP) + *net_type = SL_NET_EAP_CLIENT_CREDENTIAL; + break; + default: + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +sl_status_t sl_net_set_credential(sl_net_credential_id_t id, + sl_net_credential_type_t type, + const void *credential, + uint32_t credential_length) +{ + // Check if the credential is invalid parameter + if ((NULL == credential) || (0 == credential_length)) { + return SL_STATUS_INVALID_PARAMETER; + } + + int group_id = 0; + int cred_id = 0; + sl_status_t status = 0; + sl_wifi_credential_type_t cred_type = 0; + + if (CRED_TYPE_CERT == sli_si91x_check_cred_type(type)) { +#if defined(SLI_SI917) || defined(SLI_SI915) + return sl_si91x_set_credential(id, type, credential, credential_length); +#else + return SL_STATUS_FAIL; +#endif + } + + group_id = (id & SL_NET_CREDENTIAL_GROUP_MASK); + + if (group_id > 0) { + cred_id = (SL_NET_USER_CREDENTIAL_ID + (group_id >> 8)); + } else { + group_id = id; + cred_id = id; + } + + switch (group_id) { + case SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID: + case SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID: + case SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID: + case SL_NET_WIFI_EAP_SERVER_CREDENTIAL_ID: + status = sli_si91x_get_wifi_credential_type(type, &cred_type); + VERIFY_STATUS_AND_RETURN(status); + break; + case SL_NET_USER_CREDENTIAL_ID: + status = sli_si91x_get_wifi_credential_type(type, &cred_type); + if (status != SL_STATUS_OK) { + cred_type = (SL_WIFI_USER_CREDENTIAL | type); + } + break; + case SL_NET_TLS_CLIENT_CREDENTIAL_START: + case SL_NET_TLS_SERVER_CREDENTIAL_START: + case SL_NET_MQTT_SERVER_CREDENTIAL_START: + case SL_NET_MQTT_CLIENT_CREDENTIAL_START: + case SL_NET_HTTP_SERVER_CREDENTIAL_START: + case SL_NET_HTTP_CLIENT_CREDENTIAL_START: + cred_type = (SL_WIFI_USER_CREDENTIAL | type); + break; + + default: + return SL_STATUS_FAIL; + } + + return sl_wifi_set_credential(cred_id, cred_type, credential, credential_length); +} + +sl_status_t sl_net_get_credential(sl_net_credential_id_t id, + sl_net_credential_type_t *type, + void *credential, + uint32_t *credential_length) +{ + // Check if the credential ID is one of the invalid parameters + if ((id == SL_NET_WIFI_EAP_SERVER_CREDENTIAL_ID) || (SL_NET_TLS_CLIENT_CREDENTIAL_START == (id & ~0xff)) + || (SL_NET_TLS_SERVER_CREDENTIAL_START == (id & ~0xff))) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check if the credential is invalid parameter + if ((NULL == credential) || (0 == *credential_length)) { + return SL_STATUS_INVALID_PARAMETER; + } + + int group_id = 0; + int cred_id = 0; + sl_status_t status = 0; + sl_wifi_credential_type_t cred_type = 0; + + group_id = (id & SL_NET_CREDENTIAL_GROUP_MASK); + + if (group_id > 0) { + cred_id = (SL_NET_USER_CREDENTIAL_ID + (group_id >> 8)); + } else { + group_id = id; + cred_id = id; + } + + status = sl_wifi_get_credential(cred_id, &cred_type, credential, credential_length); + VERIFY_STATUS_AND_RETURN(status); + + switch (group_id) { + case SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID: + case SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID: + case SL_NET_WIFI_EAP_CLIENT_CREDENTIAL_ID: + case SL_NET_WIFI_EAP_SERVER_CREDENTIAL_ID: + sli_si91x_get_net_credential_type(cred_type, type); + break; + case SL_NET_USER_CREDENTIAL_ID: + case SL_NET_TLS_CLIENT_CREDENTIAL_START: + case SL_NET_TLS_SERVER_CREDENTIAL_START: + case SL_NET_MQTT_SERVER_CREDENTIAL_START: + case SL_NET_MQTT_CLIENT_CREDENTIAL_START: + case SL_NET_HTTP_SERVER_CREDENTIAL_START: + case SL_NET_HTTP_CLIENT_CREDENTIAL_START: + *type = ((~SL_WIFI_USER_CREDENTIAL) & cred_type); + break; + default: + return SL_STATUS_FAIL; + } + return SL_STATUS_OK; +} + +sl_status_t sl_net_delete_credential(sl_net_credential_id_t id, sl_net_credential_type_t type) +{ + if (CRED_TYPE_CERT == sli_si91x_check_cred_type(type)) { +#if defined(SLI_SI917) || defined(SLI_SI915) + return sl_si91x_delete_credential(id, type); +#else + return SL_STATUS_FAIL; +#endif + } + + int group_id = 0; + int cred_id = 0; + + group_id = (id & SL_NET_CREDENTIAL_GROUP_MASK); + + if (group_id > 0) { + cred_id = (SL_NET_USER_CREDENTIAL_ID + (group_id >> 8)); + } else { + cred_id = id; + } + + return sl_wifi_delete_credential(cred_id); +} diff --git a/wiseconnect/license.md b/wiseconnect/license.md new file mode 100644 index 000000000..c8ad53c6c --- /dev/null +++ b/wiseconnect/license.md @@ -0,0 +1,7 @@ +# WiSeConnectâ„¢ 3 SDK Licensing Terms + +Source code in this SDK is covered by one of several different licenses. The default license is the [Master Software License Agreement](https://www.silabs.com/about-us/legal/master-software-license-agreement) (MSLA), which applies unless otherwise noted. + +Some files use different licensing terms. If so, they will be clearly marked in the beginning of the file. + +Some code from third parties has been included in this SDK under a separate license. diff --git a/wiseconnect/resources/defaults/sl_net_default_values.h b/wiseconnect/resources/defaults/sl_net_default_values.h new file mode 100644 index 000000000..4c2795781 --- /dev/null +++ b/wiseconnect/resources/defaults/sl_net_default_values.h @@ -0,0 +1,161 @@ +/***************************************************************************/ /** + * @file sl_net_default_values.h + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#pragma once + +#include "sl_net_wifi_types.h" + +#if defined(__GNUC__) +// Ignore warning of unused variables. It is expected that some or all of these are unused +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-variable" +#endif + +#ifdef SLI_SI91X_ENABLE_IPV6 +#define REQUIRED_IP_TYPE SL_IPV6 +#else +#define REQUIRED_IP_TYPE SL_IPV4 +#endif + +#ifndef DEFAULT_WIFI_CLIENT_PROFILE_SSID +#define DEFAULT_WIFI_CLIENT_PROFILE_SSID "YOUR_AP_SSID" +#endif + +#ifndef DEFAULT_WIFI_CLIENT_CREDENTIAL +#define DEFAULT_WIFI_CLIENT_CREDENTIAL "YOUR_AP_PASSPHRASE" +#endif + +#ifndef DEFAULT_WIFI_AP_PROFILE_SSID +#define DEFAULT_WIFI_AP_PROFILE_SSID "MY_AP_SSID" +#endif + +#ifndef DEFAULT_WIFI_AP_CREDENTIAL +#define DEFAULT_WIFI_AP_CREDENTIAL "MY_AP_PASSPHRASE" +#endif + +#ifndef DEFAULT_WIFI_CLIENT_SECURITY_TYPE +#define DEFAULT_WIFI_CLIENT_SECURITY_TYPE SL_WIFI_WPA2 +#endif + +#ifndef DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE +#define DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE SL_WIFI_DEFAULT_ENCRYPTION +#endif + +//! IP address of the module +//! E.g: 0x0A0AA8C0 == 192.168.10.10 +#ifndef DEFAULT_WIFI_MODULE_IP_ADDRESS +#define DEFAULT_WIFI_MODULE_IP_ADDRESS 0x0A0AA8C0 +#endif + +//! IP address of netmask +//! E.g: 0x00FFFFFF == 255.255.255.0 +#ifndef DEFAULT_WIFI_SN_MASK_ADDRESS +#define DEFAULT_WIFI_SN_MASK_ADDRESS 0x00FFFFFF +#endif + +//! IP address of Gateway +//! E.g: 0x0A0AA8C0 == 192.168.10.10 +#ifndef DEFAULT_WIFI_GATEWAY_ADDRESS +#define DEFAULT_WIFI_GATEWAY_ADDRESS 0x0A0AA8C0 +#endif + +#define DEFAULT_WIFI_CLIENT_PROFILE \ + (sl_net_wifi_client_profile_t) \ + { \ + .config = { \ + .ssid.value = DEFAULT_WIFI_CLIENT_PROFILE_SSID, \ + .ssid.length = sizeof(DEFAULT_WIFI_CLIENT_PROFILE_SSID)-1, \ + .channel.channel = SL_WIFI_AUTO_CHANNEL, \ + .channel.band = SL_WIFI_AUTO_BAND, \ + .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ + .channel_bitmap.channel_bitmap_2_4 = SL_WIFI_DEFAULT_CHANNEL_BITMAP, \ + .bssid = {{0}}, \ + .bss_type = SL_WIFI_BSS_TYPE_INFRASTRUCTURE, \ + .security = DEFAULT_WIFI_CLIENT_SECURITY_TYPE, \ + .encryption = DEFAULT_WIFI_CLIENT_ENCRYPTION_TYPE, \ + .client_options = 0, \ + .credential_id = SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID, \ + }, \ + .ip = { \ + .mode = SL_IP_MANAGEMENT_DHCP, \ + .type = REQUIRED_IP_TYPE, \ + .host_name = NULL, \ + .ip = {{{0}}}, \ + } \ + } + +#define DEFAULT_WIFI_ACCESS_POINT_PROFILE \ + (sl_net_wifi_ap_profile_t) \ + { \ + .config = { \ + .ssid.value = DEFAULT_WIFI_AP_PROFILE_SSID, \ + .ssid.length = sizeof(DEFAULT_WIFI_AP_PROFILE_SSID)-1, \ + .channel.channel = SL_WIFI_AUTO_CHANNEL, \ + .channel.band = SL_WIFI_AUTO_BAND, \ + .channel.bandwidth = SL_WIFI_AUTO_BANDWIDTH, \ + .security = SL_WIFI_WPA2, \ + .encryption = SL_WIFI_CCMP_ENCRYPTION, \ + .rate_protocol = SL_WIFI_RATE_PROTOCOL_AUTO, \ + .options = 0, \ + .credential_id = SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID, \ + .keepalive_type = SL_SI91X_AP_NULL_BASED_KEEP_ALIVE, \ + .beacon_interval = 100, \ + .client_idle_timeout = 0xFF, \ + .dtim_beacon_count = 3, \ + .maximum_clients = 3, \ + .beacon_stop = 0, \ + .tdi_flags =SL_WIFI_TDI_NONE, \ + .is_11n_enabled = 1, \ + }, \ + .ip = { \ + .mode = SL_IP_MANAGEMENT_STATIC_IP, \ + .type = SL_IPV4, \ + .host_name = NULL, \ + .ip = { \ + .v4.ip_address.value = DEFAULT_WIFI_MODULE_IP_ADDRESS, \ + .v4.gateway.value = DEFAULT_WIFI_GATEWAY_ADDRESS, \ + .v4.netmask.value = DEFAULT_WIFI_SN_MASK_ADDRESS \ + }, \ + } \ + } + +static sl_net_wifi_psk_credential_entry_t default_wifi_client_credential = { + .type = SL_NET_WIFI_PSK, + .data_length = sizeof(DEFAULT_WIFI_CLIENT_CREDENTIAL) - 1, + .data = DEFAULT_WIFI_CLIENT_CREDENTIAL +}; + +static sl_net_wifi_psk_credential_entry_t default_wifi_ap_credential = { .type = SL_NET_WIFI_PSK, + .data_length = + sizeof(DEFAULT_WIFI_AP_CREDENTIAL) - 1, + .data = DEFAULT_WIFI_AP_CREDENTIAL }; +#if defined(__GNUC__) +// Restore GCC diagnostics +#pragma GCC diagnostic pop +#endif diff --git a/wiseconnect/resources/defaults/sl_wifi_region_db_config.h b/wiseconnect/resources/defaults/sl_wifi_region_db_config.h new file mode 100644 index 000000000..a3245b9d9 --- /dev/null +++ b/wiseconnect/resources/defaults/sl_wifi_region_db_config.h @@ -0,0 +1,129 @@ +/******************************************************************************* +* @file sl_wifi_region_db_config.h +* @brief +******************************************************************************* +* # License +* Copyright 2024 Silicon Laboratories Inc. www.silabs.com +******************************************************************************* +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is distributed to you in Source Code format and is governed by the +* sections of the MSLA applicable to Source Code. +* +******************************************************************************/ + +#pragma once + +// Define default region-specific configurations for 2.4GHz and 5GHz bands +const sl_si91x_set_region_ap_request_t default_US_region_2_4GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "US ", + .no_of_rules = 1, + .channel_info[0] = { .first_channel = 1, .no_of_channels = 11, .max_tx_power = 27 } +}; + +const sl_si91x_set_region_ap_request_t default_US_region_5GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "US ", + .no_of_rules = 5, + .channel_info[0] = { .first_channel = 36, .no_of_channels = 4, .max_tx_power = 16 }, + .channel_info[1] = { .first_channel = 52, .no_of_channels = 4, .max_tx_power = 23 }, + .channel_info[2] = { .first_channel = 100, .no_of_channels = 5, .max_tx_power = 23 }, + .channel_info[3] = { .first_channel = 132, .no_of_channels = 3, .max_tx_power = 23 }, + .channel_info[4] = { .first_channel = 149, .no_of_channels = 5, .max_tx_power = 29 } +}; + +// Define default configurations for the European region for 2.4GHz and 5GHz bands +const sl_si91x_set_region_ap_request_t default_EU_region_2_4GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "EU ", + .no_of_rules = 1, + .channel_info[0] = { .first_channel = 1, .no_of_channels = 13, .max_tx_power = 20 } +}; + +const sl_si91x_set_region_ap_request_t default_EU_region_5GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "EU ", + .no_of_rules = 3, + .channel_info[0] = { .first_channel = 36, .no_of_channels = 4, .max_tx_power = 23 }, + .channel_info[1] = { .first_channel = 52, .no_of_channels = 4, .max_tx_power = 23 }, + .channel_info[2] = { .first_channel = 100, .no_of_channels = 11, .max_tx_power = 30 } +}; + +// Define default configurations for the Japanese region for 2.4GHz and 5GHz bands +const sl_si91x_set_region_ap_request_t default_JP_region_2_4GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "JP ", + .no_of_rules = 1, + .channel_info[0] = { .first_channel = 1, .no_of_channels = 14, .max_tx_power = 20 } +}; + +const sl_si91x_set_region_ap_request_t default_JP_region_5GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "JP ", + .no_of_rules = 3, + .channel_info[0] = { .first_channel = 36, .no_of_channels = 4, .max_tx_power = 20 }, + .channel_info[1] = { .first_channel = 52, .no_of_channels = 4, .max_tx_power = 20 }, + .channel_info[2] = { .first_channel = 100, .no_of_channels = 11, .max_tx_power = 30 } +}; + +// Define default configurations for the Korean region for 2.4GHz and 5GHz bands +const sl_si91x_set_region_ap_request_t default_KR_region_2_4GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "KR ", + .no_of_rules = 1, + .channel_info[0] = { .first_channel = 1, .no_of_channels = 13, .max_tx_power = 23 } +}; + +const sl_si91x_set_region_ap_request_t default_KR_region_5GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "KR ", + .no_of_rules = 4, + .channel_info[0] = { .first_channel = 36, .no_of_channels = 4, .max_tx_power = 23 }, + .channel_info[1] = { .first_channel = 52, .no_of_channels = 4, .max_tx_power = 20 }, + .channel_info[2] = { .first_channel = 100, .no_of_channels = 11, .max_tx_power = 20 }, + .channel_info[3] = { .first_channel = 149, .no_of_channels = 5, .max_tx_power = 23 } +}; + +// Define default configurations for the Singapore region for 2.4GHz and 5GHz bands +const sl_si91x_set_region_ap_request_t default_SG_region_2_4GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "SG ", + .no_of_rules = 1, + .channel_info[0] = { .first_channel = 1, .no_of_channels = 13, .max_tx_power = 27 } +}; + +const sl_si91x_set_region_ap_request_t default_SG_region_5GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "SG ", + .no_of_rules = 5, + .channel_info[0] = { .first_channel = 36, .no_of_channels = 4, .max_tx_power = 16 }, + .channel_info[1] = { .first_channel = 52, .no_of_channels = 4, .max_tx_power = 23 }, + .channel_info[2] = { .first_channel = 100, .no_of_channels = 5, .max_tx_power = 23 }, + .channel_info[3] = { .first_channel = 132, .no_of_channels = 3, .max_tx_power = 23 }, + .channel_info[4] = { .first_channel = 149, .no_of_channels = 4, .max_tx_power = 29 } +}; + +// Define default configurations for the China region for 2.4GHz and 5GHz bands +const sl_si91x_set_region_ap_request_t default_CN_region_2_4GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "CN ", + .no_of_rules = 1, + .channel_info[0] = { .first_channel = 1, .no_of_channels = 13, .max_tx_power = 20 } +}; + +const sl_si91x_set_region_ap_request_t default_CN_region_5GHZ_configurations = { + .set_region_code_from_user_cmd = SET_REGION_CODE_FROM_USER, + .country_code = "CN ", + .no_of_rules = 2, + .channel_info[0] = { .first_channel = 36, .no_of_channels = 9, .max_tx_power = 20 }, + .channel_info[4] = { .first_channel = 149, .no_of_channels = 5, .max_tx_power = 33 } +}; + +#if defined(__GNUC__) +// Restore GCC diagnostics +#pragma GCC diagnostic pop +#endif diff --git a/zephyr/module.yml b/zephyr/module.yml index 84070724a..1197c7829 100644 --- a/zephyr/module.yml +++ b/zephyr/module.yml @@ -4,88 +4,104 @@ build: kconfig-ext: True blobs: # libbluetooth_controller - - path: simplicity_sdk/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a - sha256: 1c287778cef166f821afaaced661b5b1c2726c97924b8c8d9d52bf0201c329d3 + - path: simplicity_sdk/protocol/bluetooth/bgstack/ll/build/gcc/xg22/release/liblinklayer.a + sha256: 77b50c2d3c22c4f23a848d719737f4c0fd6efe764458739559cb36b9554b996b type: lib - version: '2024.6.2' - license-path: zephyr/blobs/license/MSLA.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/1c/28/1c287778cef166f821afaaced661b5b1c2726c97924b8c8d9d52bf0201c329d3 + version: "2024.12.0" + license-path: zephyr/blobs/license/Zlib.txt + url: https://artifacts.silabs.net/artifactory/gsdk/objects/77/b5/77b50c2d3c22c4f23a848d719737f4c0fd6efe764458739559cb36b9554b996b description: "Bluetooth Controller library (Link Layer) for EFR32" doc-url: https://github.com/SiliconLabs/simplicity_sdk - - path: simplicity_sdk/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg24_gcc_release.a - sha256: 0b0cf0a60aa2ddebc427b5a5b9bbd6938fac7fb0a954160c644c579eece18ea9 + - path: simplicity_sdk/protocol/bluetooth/bgstack/ll/build/gcc/xg24/release/liblinklayer.a + sha256: 8f8c77f3eeb612efc2523ae9dacf520ecc61a61319838a5868c5c8383a56870d type: lib - version: '2024.6.2' - license-path: zephyr/blobs/license/MSLA.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/0b/0c/0b0cf0a60aa2ddebc427b5a5b9bbd6938fac7fb0a954160c644c579eece18ea9 + version: "2024.12.0" + license-path: zephyr/blobs/license/Zlib.txt + url: https://artifacts.silabs.net/artifactory/gsdk/objects/8f/8c/8f8c77f3eeb612efc2523ae9dacf520ecc61a61319838a5868c5c8383a56870d description: "Bluetooth Controller library (Link Layer) for EFR32" doc-url: https://github.com/SiliconLabs/simplicity_sdk - - path: simplicity_sdk/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg27_gcc_release.a - sha256: 709c55c5f2e640992523a46b241f20d521c552e0f803234cac14720a4a7527c6 + - path: simplicity_sdk/protocol/bluetooth/bgstack/ll/build/gcc/xg27/release/liblinklayer.a + sha256: f7c7e60a3dde8b38fd7ef0d8e374f0fb1d1e9828b434a2ea717bf1125c53a40b type: lib - version: '2024.6.2' - license-path: zephyr/blobs/license/MSLA.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/70/9c/709c55c5f2e640992523a46b241f20d521c552e0f803234cac14720a4a7527c6 + version: "2024.12.0" + license-path: zephyr/blobs/license/Zlib.txt + url: https://artifacts.silabs.net/artifactory/gsdk/objects/f7/c7/f7c7e60a3dde8b38fd7ef0d8e374f0fb1d1e9828b434a2ea717bf1125c53a40b + description: "Bluetooth Controller library (Link Layer) for EFR32" + doc-url: https://github.com/SiliconLabs/simplicity_sdk + - path: simplicity_sdk/protocol/bluetooth/bgstack/ll/build/gcc/xg29/release/liblinklayer.a + sha256: 93579e2431c68423e06096065b8b6ac493e14400f7eb1f22ac1b248ac16332e1 + type: lib + version: "2024.12.0" + license-path: zephyr/blobs/license/Zlib.txt + url: https://artifacts.silabs.net/artifactory/gsdk/objects/93/57/93579e2431c68423e06096065b8b6ac493e14400f7eb1f22ac1b248ac16332e1 description: "Bluetooth Controller library (Link Layer) for EFR32" doc-url: https://github.com/SiliconLabs/simplicity_sdk # libbgcommon - path: simplicity_sdk/protocol/bluetooth/bgcommon/lib/build/gcc/cortex-m33/bgcommon/release/libbgcommon.a - sha256: 0b1b60532d17f444535a516475e434ddf7e60b4d8ea0c29c701885133b8346c2 + sha256: f562d2d1f340181ec43ddfa2d6c5c1cb278f6689a0eedc92bc95e001ff2b0a7b type: lib - version: '2024.6.2' + version: "2024.12.0" license-path: zephyr/blobs/license/MSLA.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/0b/1b/0b1b60532d17f444535a516475e434ddf7e60b4d8ea0c29c701885133b8346c2 + url: https://artifacts.silabs.net/artifactory/gsdk/objects/f5/62/f562d2d1f340181ec43ddfa2d6c5c1cb278f6689a0eedc92bc95e001ff2b0a7b description: "Bluetooth Utility library for EFR32" doc-url: https://github.com/SiliconLabs/simplicity_sdk # librail for simplicity_sdk (series 2) - path: simplicity_sdk/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg21_gcc_release.a - sha256: d45f7fbd2169c1b229077eadf01b71edb35ad7e37228490948645a7e317fe920 + sha256: 27450969a71f072465a926f94920957872084c717638d7b47706b17f9c4e08ce type: lib - version: '2024.6.2' + version: "2024.12.0" license-path: zephyr/blobs/license/Zlib.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/d4/5f/d45f7fbd2169c1b229077eadf01b71edb35ad7e37228490948645a7e317fe920 + url: https://artifacts.silabs.net/artifactory/gsdk/objects/27/45/27450969a71f072465a926f94920957872084c717638d7b47706b17f9c4e08ce description: "Radio Abstraction Interface Library (RAIL) supporting EFR32 radio subsystem" doc-url: https://github.com/SiliconLabs/simplicity_sdk - path: simplicity_sdk/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_gcc_release.a - sha256: d5c577bc2a0a484a41b1b3d6b5e11b07f428a3f7b6a4e00b76f7c711e7550eef + sha256: 2fd82a535badff2b6e8d768e61284354f4cdff638a60f20472631eddffcc0a2d type: lib - version: '2024.6.2' + version: "2024.12.0" license-path: zephyr/blobs/license/Zlib.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/d5/c5/d5c577bc2a0a484a41b1b3d6b5e11b07f428a3f7b6a4e00b76f7c711e7550eef + url: https://artifacts.silabs.net/artifactory/gsdk/objects/2f/d8/2fd82a535badff2b6e8d768e61284354f4cdff638a60f20472631eddffcc0a2d description: "Radio Abstraction Interface Library (RAIL) supporting EFR32 radio subsystem" doc-url: https://github.com/SiliconLabs/simplicity_sdk - path: simplicity_sdk/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg23_gcc_release.a - sha256: fb8ba2614c0c11656e0600b54379029ef37e65b8fbbd7268eb2fcca93e389bdc + sha256: 26eb8ed1be21ee0217f2f793ce096d22ccdb97f56a4b4a482fc183ebb83fbd09 type: lib - version: '2024.6.2' + version: "2024.12.0" license-path: zephyr/blobs/license/Zlib.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/fb/8b/fb8ba2614c0c11656e0600b54379029ef37e65b8fbbd7268eb2fcca93e389bdc + url: https://artifacts.silabs.net/artifactory/gsdk/objects/26/eb/26eb8ed1be21ee0217f2f793ce096d22ccdb97f56a4b4a482fc183ebb83fbd09 description: "Radio Abstraction Interface Library (RAIL) supporting EFR32 radio subsystem" doc-url: https://github.com/SiliconLabs/simplicity_sdk - path: simplicity_sdk/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg24_gcc_release.a - sha256: 331a581f55526efa2c18e6b7c1f05e9bacf2f5113e1c3c5b7eb4cc6cc38dfcd7 + sha256: f8d026207d60d69fdb078de4174ff4678b10a5c3b7d7090d1e547eeaf09f92be type: lib - version: '2024.6.2' + version: "2024.12.0" license-path: zephyr/blobs/license/Zlib.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/33/1a/331a581f55526efa2c18e6b7c1f05e9bacf2f5113e1c3c5b7eb4cc6cc38dfcd7 + url: https://artifacts.silabs.net/artifactory/gsdk/objects/f8/d0/f8d026207d60d69fdb078de4174ff4678b10a5c3b7d7090d1e547eeaf09f92be description: "Radio Abstraction Interface Library (RAIL) supporting EFR32 radio subsystem" doc-url: https://github.com/SiliconLabs/simplicity_sdk - path: simplicity_sdk/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg25_gcc_release.a - sha256: bd9cb19b00d8a6533a3bfde971ed2d16f6f3e8191fab30277f475dbe9491bb68 + sha256: 341a995c4f49cc7aa23be3ea5804192d0567535b619fd901f26c9a6cca19d27c type: lib - version: '2024.6.2' + version: "2024.12.0" license-path: zephyr/blobs/license/Zlib.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/bd/9c/bd9cb19b00d8a6533a3bfde971ed2d16f6f3e8191fab30277f475dbe9491bb68 + url: https://artifacts.silabs.net/artifactory/gsdk/objects/34/1a/341a995c4f49cc7aa23be3ea5804192d0567535b619fd901f26c9a6cca19d27c description: "Radio Abstraction Interface Library (RAIL) supporting EFR32 radio subsystem" doc-url: https://github.com/SiliconLabs/simplicity_sdk - path: simplicity_sdk/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg27_gcc_release.a - sha256: 816e0b7b79d530aba5012ac100adf951ce882c73f002d378becfcf3b274a6b7b + sha256: 48b191217805f6e9f07a99d78eef8c6d73390104d6473ef64d316409dba89276 + type: lib + version: "2024.12.0" + license-path: zephyr/blobs/license/Zlib.txt + url: https://artifacts.silabs.net/artifactory/gsdk/objects/48/b1/48b191217805f6e9f07a99d78eef8c6d73390104d6473ef64d316409dba89276 + description: "Radio Abstraction Interface Library (RAIL) supporting EFR32 radio subsystem" + doc-url: https://github.com/SiliconLabs/simplicity_sdk + - path: simplicity_sdk/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg29_gcc_release.a + sha256: 53fb836230bd945197166e944e78a4d83addade66846216a08b0dfd2ae9f40f3 type: lib - version: '2024.6.2' + version: "2024.12.0" license-path: zephyr/blobs/license/Zlib.txt - url: https://artifacts.silabs.net/artifactory/gsdk/objects/81/6e/816e0b7b79d530aba5012ac100adf951ce882c73f002d378becfcf3b274a6b7b + url: https://artifacts.silabs.net/artifactory/gsdk/objects/53/fb/53fb836230bd945197166e944e78a4d83addade66846216a08b0dfd2ae9f40f3 description: "Radio Abstraction Interface Library (RAIL) supporting EFR32 radio subsystem" doc-url: https://github.com/SiliconLabs/simplicity_sdk